MT24D836

OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs DRAM MODULE FEATURES • JEDEC- and industry-standard pinout in a 72-pin, single in-line memory module (SIMM) • 16MB (4 Meg x 36) and 32MB (8 Meg x 36) parity versions • High-performance CMOS silicon-gate process • Single 5V ±10% power supply • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR) and HIDDEN • 2,048-cycle refresh distributed across 32ms • FAST PAGE MODE (FPM) access cycle • Multiple RAS# lines allow x18 or x36 widths MT12D436 MT24D836 PIN ASSIGNMENT (Front View) 72-Pin SIMM (DD-5) 4 Meg x 36 (shown) (DD-6) 8 Meg x 36 (DD-7) 4 Meg x 36 Low Profile OPTIONS • Timing 60ns access MARKING -6 M G DM DG PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN 1 Vss 19 A10 37 DQ18 55 2 DQ1 20 DQ5 38 DQ36 56 3 DQ19 21 DQ23 39 Vss 57 4 DQ2 22 DQ6 40 CAS0# 58 5 DQ20 23 DQ24 41 CAS2# 59 6 DQ3 24 DQ7 42 CAS3# 60 7 DQ21 25 DQ25 43 CAS1# 61 8 DQ4 26 DQ8 44 RAS0# 62 9 DQ22 27 DQ26 45 NC/RAS1#* 63 10 Vcc 28 A7 46 NC 64 11 NC 29 NC (A11) 47 WE# 65 12 A0 30 Vcc 48 NC 66 13 A1 31 A8 49 DQ10 67 14 A2 32 A9 50 DQ28 68 15 A3 33 NC/RAS3#* 51 DQ11 69 16 A4 34 RAS2# 52 DQ29 70 17 A5 35 DQ27 53 DQ12 71 18 A6 36 DQ9 54 DQ30 72 *32MB version only SYMBOL DQ13 DQ31 DQ14 DQ32 Vcc DQ33 DQ15 DQ34 DQ16 DQ35 DQ17 NC PRD1 PRD2 PRD3 PRD4 NC Vss • Packages 72 -pin SIMM 72 -pin SIMM (gold) 72-pin SIMM low profile (1.00") 72-pin SIMM (gold) low profile (1.00") KEY TIMING PARAMETERS SPEED -6 tRC tRAC tPC tAA tCAC tRP 110ns 60ns 35ns 30ns 15ns 40ns PART NUMBERS PART NUMBER MT12D436G-xx MT12D436M-xx MT12D436DG-xx MT12D436DM-xx MT24D836G-xx MT24D836M-xx xx = speed CONFIGURATION 4 Meg x 36 4 Meg x 36 4 Meg x 36 4 Meg x 36 8 Meg x 36 8 Meg x 36 PLATING Gold Tin/Lead Gold Tin/Lead Gold Tin/Lead HEIGHT 1.190" 1.190" 1.000" 1.000" 1.190" 1.190" NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. GENERAL DESCRIPTION The MT12D436 and MT24D836 are randomly accessed 16MB and 32MB solid-state memories organized in a x36 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits, which are entered 11 bits (A0 -A10) at a time. RAS# is used to latch the first 11 bits and CAS# the latter 11 bits. A READ or WRITE 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 cycle is selected with the WE# input. A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of CAS#. Since WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST PAGE MODE FAST PAGE MODE operations allow faster data operations (READ or WRITE) within a row-address-defined (A0 A10) page boundary. The FAST PAGE MODE cycle is always initiated with a row address strobed-in by RAS# followed by a column address strobed-in by CAS#. CAS# may be toggled-in by holding RAS# LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST PAGE MODE operation. the RAS# HIGH time. Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS# ONLY, CBR or HIDDEN) so that all 2,048 combinations of RAS# addresses (A 0-A10) are executed at least every 32ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic RAS# addressing. x18 CONFIGURATION For x18 applications, the corresponding DQ and CAS# pins must be connected together (DQ1 to DQ19, DQ2 to DQ20 and so forth, and CAS0# to CAS2# and CAS1# to CAS3#). Each RAS# is then a bank select for the x18 memory organization. REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during FUNCTIONAL BLOCK DIAGRAM MT12D436 (16MB) DQ1 DQ9 DQ10 DQ18 DQ1-4 WE# U1 CAS0# RAS0# CAS# RAS# OE# A0-A10 DQ1-4 WE# U2 CAS# RAS# OE# A0-A10 D WE# Q DQ1-4 WE# DQ1-4 WE# D WE# Q U9 CAS# RAS# A0-A10 CAS# RAS# U5 CAS# RAS# U6 CAS# RAS# U10 OE# A0-A10 OE# A0-A10 A0-A10 CAS1# WE# 11 11 11 11 11 11 DQ19 DQ27 DQ28 DQ36 DQ1-4 WE# U3 CAS2# RAS2# CAS# RAS# OE# A0-A10 DQ1-4 WE# U4 CAS# RAS# OE# A0-A10 D WE# Q DQ1-4 WE# DQ1-4 WE# D WE# Q U11 CAS# RAS# A0-A10 CAS# RAS# U7 CAS# RAS# U8 CAS# RAS# U12 OE# A0-A10 OE# A0-A10 A0-A10 CAS3# A0-A10 11 11 11 11 11 11 VCC VSS U1-U12 U1-U12 U1-U8 = 4 Meg x 4 DRAMs U9-U12 = 4 Meg x 1 DRAMs 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FUNCTIONAL BLOCK DIAGRAM MT24D836 (32MB) DQ1 DQ9 DQ10 DQ18 DQ1 - 4 WE# U1 CAS0# RAS0# CAS# RAS# OE# A0-A10 DQ1 - 4 WE# U2 CAS# RAS# OE# A0-A10 D WE# Q DQ1 - 4 WE# DQ1 - 4 WE# D WE# Q U17 CAS# RAS# A0-A10 CAS# RAS# U5 CAS# RAS# U6 CAS# RAS# U18 OE# A0-A10 OE# A0-A10 A0-A10 CAS1# 11 11 11 11 11 11 DQ19 DQ27 DQ28 DQ36 DQ1 - 4 WE# CAS2# RAS2# WE# U3 CAS# RAS# OE# A0-A10 DQ1 - 4 WE# U4 CAS# RAS# OE# A0-A10 D WE# Q DQ1 - 4 WE# DQ1 - 4 WE# D WE# Q U19 CAS# RAS# A0-A10 CAS# RAS# U7 CAS# RAS# U8 CAS# RAS# U20 OE# A0-A10 OE# A0-A10 A0-A10 CAS3# A0-A10 11 11 11 11 11 11 DQ1 DQ9 DQ10 DQ18 DQ1 - 4 WE# U15 CAS# RAS1# RAS# OE# A0-A10 DQ1 - 4 WE# U16 CAS# RAS# OE# A0-A10 D WE# Q DQ1 - 4 WE# DQ1 - 4 WE# D WE# Q U21 CAS# RAS# A0-A10 CAS# RAS# U11 CAS# RAS# U12 CAS# RAS# U22 OE# A0-A10 OE# A0-A10 A0-A10 11 11 11 11 11 11 DQ19 DQ27 DQ28 DQ36 DQ1 - 4 WE# U13 CAS# RAS3# RAS# OE# A0-A10 DQ1 - 4 WE# U14 CAS# RAS# OE# A0-A10 D WE# Q DQ1 - 4 WE# DQ1 - 4 WE# D WE# Q U23 CAS# RAS# A0-A10 CAS# RAS# U9 CAS# RAS# U10 CAS# RAS# U24 OE# A0-A10 OE# A0-A10 A0-A10 11 11 11 11 11 11 VCC VSS U1-U24 U1-U24 U1-U16 = 4 Meg x 4 DRAMs U17-U24 = 4 Meg x 1 DRAMs 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs TRUTH TABLE ADDRESSES FUNCTION Standby READ EARLY WRITE FAST-PAGE-MODE READ FAST-PAGE-MODE EARLY-WRITE RAS#-ONLY REFRESH HIDDEN REFRESH CBR REFRESH READ WRITE 1st Cycle 2nd Cycle 1st Cycle 2nd Cycle RAS# H L L L L L L L L→H→L L→H→L H→L CAS# H →X L L H →L H→L H →L H→L H L L L WE# X H L H H L L X H L H tR tC DATA-IN/OUT DQ1-DQ36 High-Z Data-Out Data-In Data-Out Data-Out Data-In Data-In High-Z Data-Out Data-In High-Z X ROW ROW ROW n/a ROW n/a ROW ROW ROW X X COL COL COL COL COL COL n/a COL COL X JEDEC-DEFINED PRESENCE-DETECT – MT12D436 (16MB) SYMBOL PRD1 PRD2 PRD3 PRD4 PIN 67 68 69 70 -6 VSS NC NC NC JEDEC-DEFINED PRESENCE-DETECT – MT24D836 (32MB) SYMBOL PRD1 PRD2 PRD3 PRD4 PIN 67 68 69 70 -6 NC VSS NC NC 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to VSS .................... -1V to +7V Operating Temperature, TA (ambient) .......... 0°C to +70°C Storage Temperature (plastic) .................... -55°C to +125°C Power Dissipation ........................................................... 12W Short Circuit Output Current ..................................... 50mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VCC = +5V ±10%) PARAMETER/CONDITION Supply Voltage Input High (Logic 1) Voltage, all inputs Input Low (Logic 0) Voltage, all inputs INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ 5.5V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQ is disabled; 0V ≤ VOUT ≤ 5.5V) OUTPUT LEVELS Output High Voltage (IOUT = -5mA) Output Low Voltage (IOUT = 4.2mA) RAS0#-RAS3# A0-A10, WE# CAS0#-CAS3# DQ1-DQ36 SYMBOL VCC VIH VIL II1 II2 II3 IOZ VOH VOL MIN 4.5 2.4 -1.0 -12 -48 -12 -10 2.4 0.4 MAX 5.5 5.5 0.8 12 48 12 10 UNITS V V V µA µA µA µA V V 23 23 23 NOTES MAX PARAMETER/CONDITION STANDBY CURRENT: (TTL) (RAS# = CAS# = VIH) STANDBY CURRENT: (CMOS) (RAS# = CAS# = other inputs = VCC -0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) SYMBOL ICC1 ICC2 SIZE 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB -6 22 44 16 32 1,400 1,422 1,040 1,062 1,400 1,422 1,400 1,422 UNITS NOTES mA mA mA 3, 22 ICC3 ICC4 mA 3, 22 ICC5 mA 3, 22 ICC6 mA 3, 4 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs CAPACITANCE PARAMETER Input Capacitance: A0-A10 Input Capacitance: WE# Input Capacitance: RAS0#, RAS1#, RAS2#, RAS3# Input Capacitance: CAS0#, CAS1#, CAS2#, CAS3# Input/Output Capacitance: DQ1-DQ8, DQ10-DQ17, DQ19-DQ26, DQ28-DQ35 Input/Output Capacitance: DQ9, DQ18, DQ27, DQ36 CI1 CI2 CI3 CI4 CIO1 CIO2 70 94 50 25 10 16 MAX SYMBOL 16MB 32MB 140 188 50 50 18 28 UNITS pF pF pF pF pF pF NOTES 2 2 2 2 2 2 AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +5V ±10%) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR REFRESH) CAS# to output in Low-Z CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR REFRESH) Write command to CAS# lead time Data-in hold time Data-in setup time Output buffer turn-off delay FAST-PAGE-MODE READ or WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time Read command hold time (referenced to CAS#) Read command setup time Refresh period (2,048 cycles) RAS# precharge time RAS# to CAS# precharge time -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWL tDH tDS tOFF tPC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS tREF tRP tRPC MIN 45 0 0 15 10 15 15 3 10 10 60 10 15 10 0 3 35 15 10 60 60 110 20 0 0 40 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns NOTES 4 21 13 35 4 18 18 17, 21 15 60 15 10,000 125,000 14 16 32 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +5V ±10%) AC CHARACTERISTICS PARAMETER Read command hold time (referenced to RAS#) RAS# hold time Write command to RAS# lead time Transition time (rise or fall) Write command hold time Write command hold time (referenced to RAS#) WE# command setup time Write command pulse width WE# hold time (CBR REFRESH) WE# setup time (CBR REFRESH) -6 SYMBOL tRRH tRSH tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 0 15 15 2 10 45 0 10 10 10 MAX UNITS ns ns ns ns ns ns ns ns ns ns NOTES 16 50 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. Capacitance is measured using MIL-STD-883C, Method 3012.1 (1 MHz AC, VCC = 4.5V, DC bias = 2.4V at 15mV RMS). 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after power-up, followed by eight RAS# refresh cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = V IH, data output is High-Z. 11. If CAS# = V IL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates and 100pF, VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 14. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 15. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles. 19. OE# is tied permanently LOW; LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. 20. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21. The 3ns minimum is a parameter guaranteed by design. 22. Column address changed once each cycle. 23. 16MB module values will be half of those shown. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs READ CYCLE tRC tRAS V IH V IL tCSH tRSH tCAS tRRH tRP RAS# CAS# ADDR WE# DQ ,,, , ,,,, ,,, , , , , ,, , ,, , , ,, ,, ,, , tCRP tRCD V IH V IL tAR tRAD tRAH tASR tASC tCAH V IH V IL ROW COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tCLZ tOFF V IOH V IOL OPEN VALID DATA OPEN TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOFF , -6 DON’T CARE UNDEFINED MIN 45 0 0 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH MIN 15 10 60 110 20 0 0 40 0 15 MAX 60 UNITS ns ns ns ns ns ns ns ns ns ns ns 10,000 15 10 15 3 10 60 3 15 10,000 ns 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs EARLY WRITE CYCLE tRC tRAS RAS# V IH V IL tCSH tRSH tCAS tRP CAS# ADDR WE# V DQ V IOH IOL , ,,,,,, ,, ,, , ,,,, , , ,,,,,, ,, , ,, , ,, , , ,, ,,, , , , ,, ,, tCRP tRCD V IH V IL tAR tRAD tRAH tASR tASC tCAH V IH V IL ROW COLUMN ROW tCWL tRWL tWCR tWCH tWP tWCS V IH V IL tDS tDH VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD -6 MAX UNITS ns ns ns 10,000 ns ns ns ns ns ns ns ns SYMBOL tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP MIN 45 0 0 10 15 10 60 15 10 0 15 MIN 10 60 110 20 40 15 15 10 45 0 10 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ADDR WE# DQ , ,, ,,, ,,, ,,,,, ,, ,, , , , ,, , ,, , , , , , , , ,, , , , , , ,,, , V IH V IL tAR tRAD tRAH tASR tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRCS tRCS tRCS tRCH tRCH tRCH tRRH V IH V IL tAA tAA tAA tRAC tCAC tCPA tCPA tOFF tCAC tOFF tCAC tOFF tCLZ tCLZ tCLZ V IOH V IOL OPEN VALID DATA VALID DATA VALID DATA OPEN DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH -6 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH MIN 45 0 0 MIN 3 35 15 10 60 20 0 0 40 0 15 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns 15 10 15 3 10 10 60 10,000 125,000 35 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE EARLY-WRITE CYCLE tRASP V IH V IL tCSH tPC tCP tRSH tCRP tRCD tCAS tCAS tCP tCAS tCP tRP RAS# CAS# ADDR ,,, , , ,,,,, ,, , ,,,, ,,, ,,, ,,, , , , ,, , , , V IH V IL tAR tRAD tASR tRAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN tCWL tWP tCWL tWP tWCS tWCH tWCS tWCH WE# V IH V IL tWCR tDH tDS tDS tDH V DQ V IOH IOL VALID DATA VALID DATA tASC COLUMN tWCS tDS VALID DATA ,, ,,, ,,,, ,,, , , tCAH ROW tCWL tWP tWCH tRWL tDH TIMING PARAMETERS -6 SYMBOL tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC , -6 DON’T CARE UNDEFINED MIN 45 0 0 10 15 10 10 60 15 10 0 35 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP MIN 15 10 60 20 40 15 15 10 45 0 10 MAX 125,000 UNITS ns ns ns ns ns ns ns ns ns ns ns 10,000 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs FAST-PAGE-MODE READ-EARLY-WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASP V IH V IL tRSH tCSH tCRP tRCD tCAS tCP tPC tCAS tCP tRP RAS# CAS# ADDR WE# DQ TIMING PARAMETERS ,, ,, ,,, ,,,, ,, ,, ,, ,, , ,, , , ,, , , ,, , V IH V IL tAR tRAD tASR tRAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN ROW tCWL tRCS tRWL tWP tWCS tWCH V IH V IL tCAC t CLZ NOTE 1 t OFF tDS tDH V OH V OL OPEN VALID DATA VALID DATA tAA t RAC -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS MIN 45 0 0 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP , MIN 3 35 15 10 60 20 0 40 15 15 10 0 10 DON’T CARE UNDEFINED -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15 10 15 3 10 10 60 15 10 0 10,000 125,000 NOTE: 1. Do not drive data prior to tristate. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs RAS#-ONLY REFRESH CYCLE (WE# = DON’T CARE) tRC RAS# CAS# ADDR V DQ V OH OL ,, V IH V IL V IH V IL V IH V IL tCRP tASR tRAH ROW ,,,,,, ,, , , , tRPC OPEN tRAS tRP ROW CBR REFRESH CYCLE (Addresses = DON’T CARE) tRP RAS# V IH V IL tRPC tRPC tRAS tRP tRAS CAS# DQ WE# ,,,,,,,,,,,,,,,,, ,, ,, ,, , tCP tCSR tCHR tCSR tCHR V IH V IL V OH V OL OPEN tWRP tWRH tWRP tWRH V IH V IL , MIN 60 110 40 0 10 10 DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tASR tCHR tCP tCRP tCSR tRAH -6 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC tRP tRPC tWRH tWRP MIN 0 15 10 10 10 10 MAX 10,000 UNITS ns ns ns ns ns ns 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs HIDDEN REFRESH CYCLE 20 (WE# = HIGH) tRAS V IH V IL tRP tRAS RAS# CAS# ADDR DQ V IOH V IOL , ,,,,,,,,,,,,, , ,, , , , , , , , tCRP tRCD tRSH tCHR V IH V IL tAR tRAD tASR tRAH tASC tCAH V IH V IL ROW COLUMN tAA tRAC tCAC tCLZ tOFF OPEN VALID DATA OPEN , -6 MIN 3 15 10 60 20 40 15 DON’T CARE UNDEFINED TIMING PARAMETERS -6 SYMBOL tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP MIN 45 0 0 MAX 30 15 10 15 3 10 UNITS ns ns ns ns ns ns ns ns ns SYMBOL tOFF tRAC tRAD tRAH tRAS tRCD tRP tRSH MAX 15 60 UNITS ns ns ns ns ns ns ns ns 10,000 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs 72-Pin SIMM (16MB) 4.260 (108.20) 4.240 (107.70) .200 (5.08) MAX 1.200 (30.48) 1.180 (29.97) .125 (3.18) TYP .250 (6.35) .400 (10.16) TYP .054 (1.37) .047 (1.19) .250 (6.35) .050 (1.27) TYP .040 (1.02) TYP .133 (3.38) TYP 1.75 (44.45) TYP .080 (2.03) PIN 1 3.75 (95.25) 72-Pin SIMM (16MB) 4.260 (108.20) 4.240 (107.70) .350 (8.89) MAX 1.200 (30.48) 1.180 (29.97) .125 (3.18) TYP. .250 (6.35) .400 (10.16) TYP. .054 (1.37) .047 (1.19) .250 (6.35) .050 (1.27) TYP. .040 (1.02) TYP. .133 (3.38) TYP. 1.75 (44.45) TYP. .080 (2.03) PIN 1 3.75 (95.25) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc. OBSOLETE 4, 8 MEG x 36 PARITY DRAM SIMMs 72-Pin SIMM (32MB) FRONT VIEW 4.260 (108.20) 4.240 (107.70) .133 (3.38) TYP .350 (8.98) MAX .125 (3.18) TYP 1.010 (25.65) .990 (25.15) .400 (10.16) TYP .054 (1.37) .047 (1.19) .250 (6.35) 1.75 (44.45) TYP .080 (2.03) PIN 1 .250 (6.35) 3.75 (95.25) .050 (1.27) TYP .040 (1.02) TYP .235 (5.97) MIN BACK VIEW NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4, 8 Meg x 36 Parity DRAM SIMMs DM45.pm5 – Rev. 3/97 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. „1997, Micron Technology, Inc.