8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
FLASH MEMORY
Features
Dedicated commands to decrease programming times for both in-factory and in-system operations Fast programming algorithm (FPA) for fast PROGRAM operation 16-word page Flexible 8Mb multipartition architecture Single word (16-bit) data bus Support for true concurrent operation with zero latency Basic configuration: • 135 individually programmable/erasable blocks • 16 partitions (8Mb each for code and data storage) Operating Voltage • VCC = 1.70V (MIN)–1.95V (MAX) • VCCQ = 1.70V (MIN)–2.24V (MAX) VPP = 1.8V (TYP) for in-system PROGRAM/ERASE • 12V ±5% (HV) VPP tolerant (factory programming compatibility) Random access time: 60ns @ 1.70V VCC Burst mode read access • MAX clock rate: 66 MHz (tCLK = 15ns) • MAX clock rate: 54 MHz (tCLK = 18.5ns) • Burst latency 60ns @1.70V VCC and 66 MHz • 4 word, 8 word, 16 word, and continuous burst modes • tACLK: 14ns @ 1.70V VCC and 54 MHz • tACLK: 11ns @ 1.70V VCC and 66 MHz Page mode read access • Interpage read access: 60ns @ 1.70V VCC • Intrapage read access: 15ns @ 1.70V VCC Low power consumption (VCC = 1.95V) • Burst read @ 66 MHz 50µs T2 > 1µs VPP2
Table 16: VPP Range (V)
SYMBOL VPP1 VPP2 MIN 0.9 11.4 MAX 1.95 12.6
Device Reset
To reset the device, the RST# signal must be asserted (RST# = VIL) for a minimum of tRP. After reset, the device defaults to read array mode, the status register is set to 80h, and the read configuration register defaults to asynchronous/page read mode. A delayed access time of tRWH from the rising edge of RST# must elapse before data can be read from the device. The circuitry used to generate the RST# signal needs to be common with the system reset. Refer to the timing diagram for further details. If RST# is asserted during a PROGRAM or ERASE operation, the operation will be aborted and the memory contents at the aborted block or address are invalid.
Standby Mode ICC supply current is reduced by applying a logic HIGH level on CE# to enter the standby mode. In the standby mode, the outputs are at a high impedance state independent of OE#. Applying a logic HIGH level on CE# reduces the current to ICCs. If the device is deselected during an ERASE operation or during programming, the device continues to draw current until the operation is complete. Automatic Power Save (APS) Mode Substantial power savings are realized during periods when the array is not being read and the device is in active mode. During this time, the device switches to the automatic power save (APS) mode. When the device switches to APS mode, ICC is reduced to a level comparable to ICCS. Further power savings can be realized by applying a logic HIGH level on CE# to place the device in standby mode. The low level of power is maintained until another operation is initiated. In this mode, the I/Os retain the data from the last memory address read until a new address is read. This mode is entered automatically if no address or control signals toggle.
Power-Up Sequence
The device is protected against accidental block erasure or programming during power transitions. If VCC, VCCQ, and VPP are connected together, it does not matter whether VPP or VCC powers up first.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 18: Reset Operations
tRP tRWH
A) Reset during read mode
RST#
VIH VIL
tPRD
B) Reset during program or block erase tPRD ≥ tRP tERD ≥ tRP
RST#
VIH VIL
tERD
Abort Complete
tRWH
tPRD
Abort
tRWH
C) Reset during program or block erase tPRD ≤ tRP tERD ≤ tRP
RST#
VIH VIL
tERD Complete
DQ0–DQ15
VOH VO L
tVCCRS
VALID OUTPUT
VCC
VCC 0V
Table 17: Reset Parameter Definitions
PARAMETER RST# pulse width RST# HIGH to output delay RST# LOW during PROGRAM to RESET operation complete RST# LOW during BLOCK ERASE to RESET operation complete VCC setup to RST# going HIGH
t t t t
SYMBOL
t
MIN 100
MAX 150 10 20
UNIT ns ns µs µs µs
RP
RWH PRD ERD 60
VCCRS
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Electrical Specificatons Table 18: Absolute Maximum Ratings
Note 1 VOLTAGE Voltage to any ball except VCC, VCCQ, and VPP VPP Voltage VCC Supply Voltage VCCQ Supply Voltage Output Short Circuit Current Operating Temperature Range Storage Temperature Range Soldering Cycle MIN -0.5 -0.2 -0.2 -0.2 -40 -65° MAX +2.45 +14 +2.45 +2.45 100 +85° +125° +260 UNITS V V V V mA °C °C °C NOTES 2
3
NOTE: 1. Stresses greater than those listed in Table 18 may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum DC voltage on VPP may overshoot to +14V for periods < 20ns. 3. See technical note TN-00-15, “Recommended Soldering Techniques,” for more information.
Table 19: Recommended Operating Conditions
PARAMETER Operating Temperature VCC Supply Voltage I/O Supply Voltage Input/Output Capacitance: DQs VPP Voltage VPP In-factory Programming Voltage Block Erase Cycling (VPP = VPP1) Block Erase Cycling (VPP = VPP2) Time for VPP at VPP2 SYMBOL A VCC VCCQ CIO VPP1 VPP2
T
MIN -40 1.70 1.70 – 0.9 11.4 – –
TYP – – – 4.0 – – – –
MAX +85 1.95 2.24 6.5 1.95 12.6 100,000 1,000 100
UNITS C V V pF V V Cycles Cycles Hours
o
t
PPH
Table 20: Capacitance
TA = +25°C; f = 1 MHz PARAMETER/CONDITION Input Capacitance Output Capacitance Clock Capacitance SYMBOL CIN COUT CCLK TYP 5 8 10 MAX 8 10 12 UNITS pF pF pF
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 21: DC Characteristics
All currents are in RMS unless otherwise noted VCC = 1.70V–1.95V VCCQ = 1.70V–2.24V PARAMETER Input Low Voltage Input High Voltage Output Low Voltage IOL = 100µA Output High Voltage IOH = -100µA VPP Lockout Voltage VCC Lock Input Load Current Output Leakage Current VCC Standby Current Asynchronous Read Current @ 5 MHz 4-word Page Read Current @ 13 MHz 8-word Page Read Current @ 13 MHz 16-word Page Read Current @ 13 MHz Vcc Continuous Burst Read Current 4-word Page Read Current @ 54 MHz/66 MHz 8-word Page Read Current @ 54 MHz/66 MHz 16-word Page Read Current @ 54 MHz/66 MHz Continous Burst Read Current @ 54 MHz/66 MHz VCC Program Current VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VCC Block Erase Current VPP = VPP1, Block Erase in Progress VPP = VPP2, Block Erase in Progress VCC Program Suspend Current VCC Erase Suspend Current VCC Automatic Power Save Current VPP Standby Current VPP Program Suspend Current VPP Erase Suspend Current VPP Read Current SYM VIL VIH VOL VOH VPPLK VLKO ILI ILO ICCS ICCR ICCR MIN -0.4 VCCQ - 0.4 -0.1 VCCQ - 0.1 0.4 1.0 0.2 10 5 2 2 2 3 3 3 8 18 8 ICCE 18 8 10 10 10 0.2 0.2 2 30 15 50 50 50 5 5 15 ±1 ±1 50 7 4 4 4 5 5 5 12 25 15 mA TYP MAX 0.4 VCCQ + 0.03 0.1 UNITS V V V V V V µA µA µA mA mA NOTES 1 1
2, 3
ICCR
mA
5
ICCW
mA
ICCWS ICCES ICCAPS IPPS IPPWS IPPES IPPR
µA µA µA µA µA
4 4 4
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 21: DC Characteristics
All currents are in RMS unless otherwise noted VCC = 1.70V–1.95V VCCQ = 1.70V–2.24V PARAMETER VPP Program Current VPP = VPP1, Program in Progress VPP = VPP2, Program in Progress VPP Erase Current VPP = VPP1, Erase in Progress VPP = VPP2, Erase in Progress SYM IPPW 0.05 8 IPPE 0.05 8 0.10 22 0.10 22 mA MIN TYP MAX UNITS mA NOTES
NOTE: 1. VIL may decrease to -0.4V and VIH may increase to VCCQ + 0.3V for durations not to exceed 20ns. 2. APS mode reduces ICC to approximately ICCS levels. 3. Test conditions: VCC = VCC (MAX), CE# = VIL, OE# = VIH. All other inputs = VIH or VIL. 4. ICCES and ICCWS values are valid when the device is deselected. Any READ operation performed while in suspend mode will have an additional current draw of suspend current (ICCES or ICCWS). 5. ICCR Burst current measurements are made in wrap mode.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 22: Asynchronous READ Cycle Timing Requirements
See Figure 19 and Figure 20 for timing requirements and load configuration. -60 PARAMETER READ cycle time Address to output delay CE# LOW to output delay OE# LOW to output delay RST# HIGH to output delay CE# LOW to output in Low-Z OE# LOW to output in Low-Z CE# or OE# HIGH to output High-Z Output hold from address, CE# or OE# transition Address setup to ADV# HIGH CE# LOW to ADV# HIGH ADV# LOW to output delay ADV# pulse width LOW ADV# pulse width HIGH Address hold from ADV# HIGH Page address access
t t t t t t
-70 MAX 60 60 20 150 MIN 70 70 70 30 150 0 0 5 20 0 7 7 60 70 7 7 7 15 22 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SYMBOL
t t
MIN 60
RC
AA
ACE
AOE CEZ OD OH 0 7 7 7 7 7 0 0
RWH
t
t
OEZ
t t t
AVS CVS VP
t
AADV
t
VPH
AVH APA
t
Figure 19: AC Input/Output Reference Waveforms
VCCQ Input VSS VCCQ Input VSS Rise and Fall Levels 10% VCCQ 90% VCCQ VCCQ/2 Test Points VCCQ/2 Output
NOTE: AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input timing begins at VCCQ/2, and output timing ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns.
Figure 20: Output Load Circuit1
VCCQ 16.7K I/O 16.7K VSS 30pF
NOTE: 1. Minimum recommended capacitive loading is 5pF.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 23: Burst READ Cycle Timing Requirements
-606 PARAMETER CLK period CLK frequency CLK HIGH (LOW) time CLK fall (rise) time Address valid setup to CLK ADV# LOW setup to CLK CE# LOW setup to CLK CLK to output valid (latency codes 3, 4, and 5) CLK to output valid (latency code 2) Output hold from CLK Address hold from CLK CLK to WAIT# valid CE# LOW to WAIT# valid CE# HIGH to WAIT# High-Z CE# HIGH between subsequent burst READs SYM
t f
-705 MAX MIN 18.5 66 54 6 2 3 7 7 7 11 14 See Note 1 3 7 11 11 11 14 14 14 18 ns ns ns ns ns ns MAX UNITS ns MHz ns ns ns ns ns ns
MIN 15
CLK CLK KP
t
3
tKHKL tAKS tVKS tCKS tACLK tACLK tKOH tAKH tKHTL tCEWV tCEWZ t
7 7 7
See Note 1 3 7
CBPH
14
NOTE: 1. Maximum frequency for latency code 2 = 40 MHz (tACLK = 20ns).
Table 24:
WRITE Cycle Timing Requirements
-60/-70
PARAMETER RST# HIGH recovery to CE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# (CE#) going HIGH Address setup to WE# (CE#) going HIGH CE# hold from WE# HIGH Data hold from WE# (CE#) HIGH Address hold from WE# HIGH Write pulse width HIGH VPP setup to WE# going HIGH VPP hold from valid SRD WP# hold from valid SRD WP# setup to WE# going HIGH WE# HIGH to OE# LOW Write recovery before READ WE# HIGH to output valid WE# HIGH to address valid WE# HIGH to CLK valid WE# HIGH to ADV# HIGH
SYMBOL
tRS tCS tWP t t t t t t
MIN 150 0 40 40 40 0 0 0 20 200 0 0 200 0 50
tAA+20
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
DS AS
CH
DH AH
WPH VPS
t
tVPPH tRHH tRHS tWOA tWOS tWB t
WAV WCV
0 12 12
t
tWAH
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 25: ERASE and PROGRAM Timing Requirements
VPP1 OPERATION Erase Time Suspend Latency PARAMETER
t t
VPP2 TYP 0.25 0.4 5 20 8 0.03 0.24 3.5 15 120 5 5 2.7 1.7 5.6 130 5.6 130 MAX 2.5 4 10 25 130 0.07 0.6 16 UNIT s s µs µs µs s s µs ms ms µs µs µs 1, 2 1, 2 NOTES 1, 2 1, 2 1 1 1 1, 2 1, 2
DESCRIPTION
TYP
MAX 2.5 4 10 25
ERS/PB SUSP/P SUSP/E
Erasing and Suspending 0.3 8KW parameter block 64KW main block PROGRAM SUSPEND ERASE SUSPEND 0.7 5 20
ERS/MB
t t
Program Time
t t t
PROG/W
Conventional Word Programming 8 130 Single word 8KW parameter block 64KW main block Single word 0.03 0.24 0.07 0.6 16
PROG/PB
PROG/MB
t t t
Program
FPA/W
Fast Programming Algorithm 3.5 15 120 2.7 1.7
FPA/PB
8KW parameter block 64KW main block FPA Setup Program-to-verify transition Verify
FPA/MB
Operation Latency
t
FPA/SETUP FPA/TRAN
t t
FPA/VERIFY
NOTE: 1. Excludes external system-level overhead. 2. Exact results may vary based on system overhead.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 21: Single Asynchronous READ Operation (Nonlatched Mode)
tRC
A0–A22
VIH VIL
tAA
VALID ADDRESS
CE#
VIH VIL
tACE tAOE tOD
OE#
VIH VIL
tOEZ
tOD
WE#
VIH VIL
tCEZ tOH
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
tRC t
-70 MAX MIN 70 60 60 20 70 70 30 MAX UNITS ns ns ns ns SYMBOL
tCEZ t
-60 MIN 0 0 5 0 0 MAX MIN 0 0
-70 MAX UNITS ns ns 20 ns ns
MIN 60
AA
OEZ
tACE t
tOD t
AOE
OH
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 22: Latched Asynchronous READ Operation
tRC
A3–A22
VIH VIL VIH VIL
VALID ADDRESS
VALID ADDRESS
A0–A3
VALID ADDRESS
tAA tAVS tVPH tAVH
VALID ADDRESS
ADV#
VIH VIL
tVP tAADV tACE
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tOEZ tOD
WE#
VIH VIL
tCEZ
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t
-70 MAX MIN 70 60 60 20 150 70 70 30 150 0 0 5 20 MAX UNITS ns ns ns ns ns ns ns ns SYMBOL
t
-60 MIN 0 7 7 60 7 7 7 7 7 7 MAX MIN 0 7 7
-70 MAX UNITS ns ns ns 70 ns ns ns ns
MIN 60
RC
OH
tAA t t t t
tAVS t t t t
ACE AOE RWH CEZ 0 0
CVS AADV VP VPH
tOEZ t
tAVH
OD
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 23: Page Mode READ Operation
A3–A22 VIH VIL VIH VIL VALID ADDRESS
A0–A3
VALID ADDRESS
tAA tAVS tVPH tAVH
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
ADV#
VIH VIL
tVP tAADV tACE
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tOEZ tOD
WE#
VIH VIL
tCEZ
WAIT#
VOH VO L
High-Z Note 1
tAPA tOH
High-Z
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. WAIT# is shown active LOW.
READ Timing Parameters
-60 SYMBOL
tAA t
-70 MAX 60 60 30 150 MIN MAX 70 70 30 150 0 0 5 20 0 UNITS ns ns ns ns ns ns ns ns SYMBOL
tAVS t
-60 MIN 7 7 60 7 7 7 15 7 7 7 MAX MIN 7 7
-70 MAX UNITS ns ns 70 ns ns ns ns 22 ns
MIN
ACE
CVS
tAOE t
tAADV t
RWH 0 0
VP
tCEZ t t t
tVPH t t
OEZ OD OH
AVH APA
0
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 24: Single Burst READ Operation
tCLK
CLK
VIH VIL
tAKS
Note 1
tAKH tKP tKP
A0–A22
VIH VIL
tVPH
VALID ADDRESS
tAVS tVKS tAVH
ADV#
VIH VIL VIH VIL VIH VIL
tCKS tOEZ tOD tVP tCEWZ
CE#
tCVS
tAOE
OE#
WE#
VIH VIL
tCEWV High-Z tOD
WAIT#
VOH VOL
Note 2
tACLK tKOH
High-Z
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAOE t t t t t t
-705 MIN MAX 30 0 5 20 0 7 7 7 7 7 18.5 7 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tVKS t
t
-606 MIN 7 7
1
-705 MIN 7 7 11 20 14 20 3 7 TBD TBD 14 14 ns ns ns ns MAX UNITS ns ns ns
MIN
MAX 20
MAX
OEZ OD OH AVS CVS VP
0
CKS
ACLK
0 7 7 7 7 7 15 7
tACLK2
t t t t
KOH AKH CEWV CEWZ
3 7
tVPH t
AVH
tCLK t
AKS
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 25: READ Timing Parameters for Four-Word BURST Operation
tCLK
CLK
VIH VIL
tAKS tAKH
Note 1
tKP tKP
A0–A22
VIH VIL
VALID ADDRESS
tAVS tVPH tVKS tAVH
ADV#
VIH VIL VIH VIL
tCVS tAOE tVP
tCBPH
CE#
OE#
VIH VIL
tCKS
tOD
tOEZ
tOD
WE#
VIH VIL
tCEZ
tKHTL
tOH
WAIT#
VOH VOL
High-Z
Note 2
tACLK tKOH
High-Z
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 18.5 7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
t
-606 MIN 7 7
1
-705 MIN 7 7 11 20 14 20 3 7 11 14 18 ns ns ns ns MAX UNITS ns ns ns
MIN
MAX 20
MAX
AOE 0 0
VKS
tCEZ t
tCKS
t t
OEZ
ACLK
tOD t t t t
ACLK2
OH AVS CVS VP
0 7 7 7 7 7 15 7
tKOH t t t
3 7
AKH KHTL CBPH
14
tVPH t
AVH
tCLK t
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
AKS
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 26: WAIT# Functionality for End-of-Word Line (EOWL) Condition
CLK VIH VIL
tAKS tAKH
Note 1
A0–A22
VIH VIL
VALID ADDRESS
tAA tAVS tVPH tVKS
tAVH
ADV#
VIH VIL VIH VIL
tVP tAADV tACE
CE#
OE#
VIH VIL
tCVS
tAOE
tCKS
VIH WE# VIL WAIT# VOH VOL High-Z
tCEWV
tCEZ
tOEZ
tKHTL
Note 2
tACLK tKOH
High-Z
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAA t
-705 MIN MAX 70 70 30 0 0 7 7 60 70 7 7 7 7 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
tVKS t
t
-606 MIN 7 7 11 20 3 7 11 TBD 3 7 MAX MIN 7 7
-705 MAX UNITS ns ns 14 20 ns ns 14 14 ns ns ns
MIN
MAX 60 60 20
ACE 0 0 7 7
CKS
tAOE t t t t
ACLK1
CEZ OEZ AVS CVS
tACLK2
t t t t
KOH AKH KHTL CEWV
tAADV t
VP
7 7 7 7
tVPH t
AVH
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
tAKS
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 27: WAIT# Signal in Burst Non-READ ARRAY Operation
CLK VIH VIL
tAKS tAKH
Note 1
A0–A22
VIH VIL
VALID ADDRESS
tAVS tVPH tVKS tAVH
ADV#
VIH VIL
tVP
CE#
VIH VIL
tCVS tAOE tOD
OE#
VIH VIL
tCKS
WE#
VIH VIL High-Z
tCEZ
tOEZ
tOD
WAIT#
VOH VOL
High-Z
Note 2
tACLK tOH tKOH
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access. 2. WAIT# is shown active LOW, and WAIT# configured during delay (RCR8 = 0, RCR10 = 0).
READ Timing Parameters
-606 SYMBOL
tAOE t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
tAKS t
-606 MIN 7 7 7 11 20 3 7 3 7 MAX MIN 7 7 7
-705 MAX UNITS ns ns ns 14 20 ns ns ns
MIN
MAX 20
CEZ
0 0
VKS
tOEZ t
tCKS
tACLK1 t
OD 0 7 7 7 7 7
tOH t t t t
ACLK2
AVS CVS VP VPH
tKOH t
AKH
tAVH
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 28: WAIT# Signal in Asynchronous READ Operation
tRC
A0–A22
VIH VIL
tAA
VALID ADDRESS
CE#
VIH VIL
tACE
tAOE
tOD
OE#
VIH VIL
tOEZ
tOD
WE#
VIH VIL
tCEZ
WAIT#
VOH VOL
High-Z Note 1
High-Z
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
tOH
High-Z
UNDEFINED
NOTE: 1. WAIT# shown active LOW.
READ Timing Parameters
-60 SYMBOL
t t t t
-70 MAX MIN 70 60 60 20 70 70 30 MAX UNITS ns ns ns ns SYMBOL
t t t t
-60 MIN 0 0 5 0 0 MAX MIN 0 0
-70 MAX UNITS ns ns 20 ns ns
MIN 60
RC AA ACE AOE
CEZ OEZ OD OH
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 29: Two-Cycle WRITE Operation
Note 1 A0–A22 VIH VIL VALID ADDRESS
tAS tAH
VALID ADDRESS
tWAV tAVS
VALID ADDRESS
tAVH
ADV#
VIH VIL
tVP tWAH
CE# (WE#)
VIH VIL
tCS tCH
OE#
VIH VIL
tWP tWPH tWOS
WE# (CE#)
VIH VIL
tRS tDH tWB
DQ0–DQ15
VIH VIL VIH
High-Z
DATA IN
High-Z
DATA IN
tDS
High-Z
VALID SRD
High-Z
RST#
VIL VIH
tRHS
tRHH
WP#
VIL VVPPH
tVPS
tVPPH
VPP VPPLK VIL
UNDEFINED
NOTE:
1. Status register data (SRD) may be read after a two-cycle PROGRAM/ERASE sequence to determine completion of the PROGRAM/ERASE algorithm.
READ/WRITE Timing Parameters
-60/-70 SYMBOL
t t t t
-60/-70 MAX UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL
t t t t
MIN 150 0 40 40 40 0 0 0 7 7
MIN 20 7 200 0 0 200 50
t
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
RS CS WP DS
WPH VP VPS VPPH
tAS t
tRHH t
CH
RHS
tDH t
tWOS t
AH
WB
AA + 20 0 12
tAVH t
tWAV t
AVS
WAH
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 30: Clock Suspend
VIH CLK VIL
tCLK tAKS tKP tKP tAKH
VIH A0–A22 VIL
tVPH
VALID ADDRESS
tAVS tVKS
tAVH
VALID ADDRESS
ADV#
VIH VIL
tVP tCBPH
CE#
VIH VIL
tCVS tCEZ tAOE tOD
OE#
VIH VIL
tCKS tOEZ
tOD tAOE
WE#
VIH VIL
tKHTL
tOH
WAIT#
VOH VOL
High-Z
High-Z
tACLK
tKOH
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
High-Z
VALID OUTPUT
VALID OUTPUT
High-Z
UNDEFINED
READ Timing Parameters
-606 SYMBOL
t
-705 MIN MAX 30 0 0 5 20 0 7 7 7 7 7 18.5 6 2 3 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL
t
-606 MIN 7 7 7 11 20 3 7 11 14 18 3 7 MAX MIN 7 7 7
-705 MAX UNITS ns ns ns 14 20 ns ns 14 ns ns ns
MIN
MAX 20
AOE 0 0
AKS
tCEZ t
tVKS t
OEZ
CKS
tOD t
tACLK1 tACLK2
OH
0 7 7 7 7 7 15 3
tAVS t t t t
t
KOH
CVS VP VPH AVH
tAKH t t
KHTL CBPH
tCLK t
KP
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
tKHKL
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 31: Asynchronous READ-to-WRITE Operation
tRC tAA tAS tAH
A0–A22
VIH VIL VIH VIL
VALID ADDRESS
tACE tOD
VALID ADDRESS
CE#
tAOE
tOD
OE#
VIH VIL VIH VIL
tCEZ tOEZ tOH tDS tDH tCS
tWP
tCH
WE#
DQ0–DQ15
VOH VO L
High-Z
VALID OUTPUT
High-Z
DATA IN
High-Z
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t t t t
WRITE Timing Parameters
-70 -60/-70 MAX UNITS ns 70 70 30 ns ns ns ns ns 20 ns ns SYMBOL
t t t t
MIN 60
MAX
MIN 70
MIN 0 40 40 40 0 0 0
MAX
UNITS ns ns ns ns ns ns ns
RC AA ACE AOE
CS WP DS AS
60 60 20 0 0 5 0 0 0 0
tCEZ t
tCH t
OEZ
DH
tOD t
tAH
OH
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 32: WRITE-to-Asynchronous-READ Operation
tAS tAH tRC
A0–A22
VIH VIL VIH VIL
tCS
VALID ADDRESS
tCH
VALID ADDRESS
tOH
CE#
tWP
tWAV
VIH WE# VIL VIH OE# VIL
tAOE tAA tDS tDH tACE tOD tOD tWOA
DQ0–DQ15
VOH VO L VIH
tRS
High-Z
DATA IN
High-Z
VALID OUTPUT
High-Z
RST#
VIL
UNDEFINED
READ Timing Parameters
-60 SYMBOL
t
WRITE Timing Parameters
-70 -60/-70 MAX UNITS ns 70 70 30 20 ns ns ns ns ns SYMBOL
t
MIN 60
MAX
MIN 70
MIN 150 0 40 40 40 0 0 0 0 0
MAX
UNITS ns ns ns ns ns ns ns ns ns ns
RC
RS
tAA t
60 60 20 5 0 0
tCS t
ACE
WP
tAOE t t
tDS t t t t
OD OH
AS CH DH AH
tWOA t
WAV
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 33: Burst READ-to-WRITE Operation
tAKS tAKH
Note 1
tWAV
CLK
tAVS tAS
A0–A22
tVPH
VALID ADDRESS
tAVH
VALID ADDRESS
VALID ADDRESS
tAH
tVKS
ADV#
tCKS tCVS tCBPH
tCH
CE#
tAOE tOD
OE#
tCS tWP tWPH
WE#
tKHTL
WAIT#
tCEZ tOEZ tACLK tKOH tDS tDH
DQ0–DQ15
High-Z
High-Z
VALID OUTPUT
High-Z
DATA IN
High-Z
DATA IN
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606 SYMBOL
t t t t t t t
WRITE Timing Parameters
-705 -60/-70 UNITS
ns ns
MIN
0 0
MAX
20
MIN
0 0
MAX
30
SYMBOL
t t
MIN 0 40 40 40 0 0 0 0 20
MAX
UNITS ns ns ns ns ns ns ns ns ns
AOE CEZ OEZ OD AVS CVS VPH 7 7 7 7 7 7 7
CS WP
tDS
5 7 7 7 7 7 7 7
20
t
AS
tCH t
DH
tAVH tAKS t t
ns ns ns ns
tAH t t
WAV WPH
VKS CKS
tACLK1 tACLK2 tKOH tAKH t t
11 20
3 7 11 14 18 3 7
14 20
ns
ns ns
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
KHTL CBPH
14
ns ns
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 34: Write-to-BURST READ Operation
tVKS tAKS
Note 1
CLK
tAS
tAH tAKH
A0–A22
VALID ADDRESS
tWAH tVP
VALID ADDRESS
tAVH
ADV#
tCS
tCH
tCBPH
tCKS
CE#
tWAV
tWP
tWCV
WE#
tAOE
OE#
tKHTL
WAIT#
tDS tDH
tACLK
tACLK tKOH
DQ0–DQ15
tRS
High-Z
DATA IN
VALID OUTPUT
VALID OUTPUT
RST#
UNDEFINED
NOTE: 1. Figure 6 on page 19 describes how to insert clock cycles during initial access.
READ Timing Parameters
-606 SYMBOL
tAOE t
WRITE Timing Parameters
-705 -60/-70 UNITS ns ns ns ns ns ns 14 20 ns ns ns 14 ns ns SYMBOL
tRS t
MIN
MAX 20
MIN
MAX 30
MIN 150 0 40 40 40 0 0 0 0 12 12
MAX
UNITS ns ns ns ns ns ns ns ns ns ns ns
VP
7 7 7 7 7
1
7 7 7 7 7 11 20
CS
tAVH t
tWP t
AKS
DS
tVKS t
t
tAS t t t t
CKS
CH DH AH WAV
ACLK
tACLK2
t t
KOH AKH
3 7 11 14
3 7
tWCV t
tKHTL t
WAH
CBPH
18
NOTE: 1. Latency codes 3, 4, and 5. 2. Latency code 2.
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Appendix A: CFI Table Table 26: CFI
OFFSET 00 002C 0089 01 44C8 44C9 reserved 0051, 0052 0059 0003, 0000 0039, 0000 0000, 0000 0000, 0000 0017 0019 00B4 00C6 0003 0000 000A 0000 0004 0000 0002 0000 0018 0001 0000 0000, 0000 0002 007E, 0000 0007, 0000 0000, 0002 0040, 0000 0007, 0000 007E, 0000 0040, 0000 0000, 0002 0000, 0000 0000, 0000 0050, 0052 DATA DESCRIPTION Manufacturer’s ID (ManID) Micron Intel Device ID Code (DevID) Top boot block device code (Micron) Bottom boot block device code (Micron) Reserved “QR” “Y” Primary OEM command set Address for primary extended table Alternate OEM command set Address for OEM extended table VCC MIN for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD VCC MAX for Erase/Write; Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD VPP MIN for Erase/Write; Bit 7–bit 4 volts in hex; Bit 3–bit 0 100mV in BCD VPP MAX for Erase/Write; Bit 7–bit 4 volts in hex; Bit 3–bit 0 100mV in BCD Typical timeout for single byte/word program, 2nµs, 0000 = not supported Typical timeout for maximum size multiple byte/word program, 2nµs, 0000 = not supported Typical timeout for individual block erase, 2nms, 0000 = not supported Typical timeout for full chip erase, 2ns, 0000 = not supported Maximum timeout for single byte/word program, 2nµs times typical, 0000 = not supported Maximum timeout for maximum size multiple byte/word program, 2nµs, 0000 = not supported Maximum timeout for individual block erase, 2ns, 0000 = not supported Maximum timeout for full chip erase, 2ns, 0000 = not supported Device size, 2n bytes Bus interface x8 = 0, x16 = 1, x32 = 2, x64 = 3 Flash device interface description 0000 = async Maximum number of bytes in multibyte program or page, 2n Number of erase block regions within device (8K words and 64K words) Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 1 Bottom boot block device erase block region information 1 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Top boot block device erase block region information 2 Bottom boot block device erase block region information 2 Reserved for future erase block region information Reserved for future erase block region information “PR”
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02 – 0F 10, 11 12 13, 14 15, 16 17, 18 19, 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A, 2B 2C 2D, 2E 2F, 30 31, 32 33, 34 35, 36 37, 38 39, 3A
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET 3B 3C 3D 3E 3F 40 41 DATA 0049 0031 0033 00E6 0003 0000 0000 DESCRIPTION “I” Major version number, ASCII Minor version number, ASCII Optional Feature And Command Support Bit 0 Chip erase supported no = 0 Bit 1 Suspend erase supported = yes = 1 Bit 2 Suspend program supported = yes = 1 Bit 3 Chip lock/unlock supported = no = 0 Bit 4 Queued erase supported = no = 0 Bit 5 Instant individual block locking supported = yes = 1 Bit 6 Protection bits supported = yes = 1 Bit 7 Page mode read supported = yes = 1 Bit 8 Synchronous read supported = yes = 1 Bit 9 Simultaneous operation supported = yes = 1 Program supported after erase suspend = yes Bit 0 block lock status active = yes; Bit 1 block lock down active = yes VCC supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD VPP supply optimum, 00 = not supported, Bit 7–bit 4 volts in BCD; Bit 3–bit 0 100mV in BCD Number of protection register fields in JEDEC ID space Lock bytes LOW address, lock bytes HIGH address 2n factory programmed bytes, 2n user programmable bytes Page mode read capability, 2n bytes Number of synchronous mode read configuration fields that follow Synchronous mode read capability configuration 1 Synchronous mode read capability configuration 2 Synchronous mode read capability configuration 3 Synchronous mode read capability configuration 4 Number of device hardware partition regions within the device Number of identical partitions within the partition region Number of identical partitions within the partition region Number of PROGRAM/ERASE operations allowed in a partition Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode Types of erase block regions in this partition region Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information Partition region 1 erase block type 1 information
42 43, 44 45 46 47 48, 49 4A, 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B
0001 0003, 0000 0018 00C0 0001 0080, 0000 0003, 0003 0005 0004 0001 0002 0003 0007 Top: 0002 Bot: 0002 Top: 000F Bot: 0001 Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0001 Bot: 0002 Top: 0007 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0040
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET 5C 5D 5E 5F 60 DATA Top: 0002 Bot: 0000 Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 Bot: 0006 Partition region 1 erase block type 2 information Bot: 62 Bot: 63 Bot: 64 Bot: 65 Bot: 66 Bot: 67 Bot: 68 Top: 61 Bot: 69 Top: 62 Bot: 6A Top: 63 Bot: 6B Top: 64 Bot: 6C Top: 65 Bot: 6D Top: 66 Bot: 6E Top: 67 Bot: 6F Top: 68 Bot: 70 Top: 69 Bot: 71 Bot: 0000 Partition region 1 erase block type 2 information Bot: 0000 Partition region 1 erase block type 2 information Bot: 0002 Partition region 1 (erase block type 2) Bot: 0064 Partition region 1 (erase block type 2) Bot: 0000 Partition region 1 (erase block type 2) bits per cell Bot: 0001 Partition region 1 (erase block type 2) page mode and synchronous mode capabilities Bot: 0003 Top: 0001 Bot: 000F Top: 0000 Bot: 0000 Top: 0011 Bot: 0011 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Top: 0002 Bot: 0001 Top: 0006 Bot: 0007 Top: 0000 Bot: 0000 Top: 0000 Bot: 0000 Number of identical partitions within the partition region Number of identical partitions within the partition region Number of PROGRAM/ERASE operations allowed in a partition Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in program mode. Simultaneous PROGRAM/ERASE operations allowed in other partitions while a partition in this region is in erase mode. Types of erase block regions in this partition region Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information Partition region 2 erase block type 1 information DESCRIPTION Partition region 1 erase block type 1 information Partition 1 (erase block type 1) Partition 1 (erase block type 1) Partition 1 (erase block type 1) bits per cell; internal ECC Partition 1 (erase block type 1) page mode and synchronous mode capabilities Partition region 1 erase block type 2 information Bot: 61
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Table 26: CFI (continued)
OFFSET Top: 6A Bot: 72 Top: 6B Bot: 73 Top: 6C Bot: 74 Top: 6D Bot: 75 Top: 6E Bot: 76 Top: 6F Top: 70 Top: 71 Top: 72 Top: 73 Top: 74 Top: 75 Top: 76 77 78 DATA Top: 0002 Bot: 0002 Top: 0064 Bot: 0064 Top: 0000 Bot: 0000 Top: 0001 Bot: 0001 Top: 0003 Bot: 0003 Top: 0007 Top: 0000 Top: 0040 Top: 0000 Top: 0064 Top: 0000 Top: 0001 Top: 0003 DESCRIPTION Partition region 2 erase block type 1 information Partition 2 (erase block type 1) Partition 2 (erase block type 1) Partition 2 (erase block type 1) bits per cell Partition 2 (erase block type 1) page mode and synchronous mode capabilities Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition region 2 erase block type 2 information Partition 2 (erase block type 2) Partition 2 (erase block type 2) Partition 2 (erase block type 2) bits per cell Partition 2 (erase block type 2) page mode and synchronous mode capabilities TBD Reserved
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
Appendix B: CSM Table Table 27: Command State Machine Transition
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a time.
DEVICE NEXT STATE AFTER COMMAND INPUT BLOCK ERASE CONFIRM, PROGRAM/ ERASE RESUME, UNLOCK BLOCK CONFIRM9 (D0h)
CURRENT CHIP STATE8
READ ARRAY3 (FFh)
PROGRAM SETUP4,5 (10h/40h)
ERASE SETUP4,5 (20h)
FPA SETUP4 (30h)
PROGRAM/ ERASE SUSPEND (B0h)
READ STATUS (70h)
CLEAR STATUS REGISTER 6 (50h)
READ ID/ QUERY (90h, 98h)
LOCK, UNLOCK, LOCK DOWN, RCR SETUP5 (60h)
OTP SETUP5 (C0h)
LOCK BLOCK CONFIRM9 (01h)
LOCK DOWN BLOCK CONFIRM9 (2Fh)
WRITE RCR CONFIRM9 (03h)
FPA EXIT (ADDRESS BA) (FFFFh)
ILLEGAL COMMANDS OR FPA DATA (OTHER CODES)2
WSM OPERATION COMPLETES
READY LOCK/RCR SETUP SETUP OTP BUSY SETUP PROGRAM BUSY SUSPEND SETUP BUSY ERASE SUSPEND
Ready
Program Setup
Erase Setup
FPA Setup Ready
Ready Ready (Lock Error)
Lock/RCR Setup
OTP Setup Ready
Ready Ready (Lock Error) N/A
Ready (Lock Error)
OTP Busy Ready Program Busy Program Busy Program Suspend Ready (Error) Erase Busy Program in Erase Suspend Setup Program Busy Erase Busy Erase Suspend Lock/RCR Setup in Erase Suspend Program Suspend Program Busy Program Suspend N/A Ready (Error) N/A Ready
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Erase Busy
Ready
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Erase Suspend
Erase Suspend
Erase Busy
Erase Suspend
Erase Suspend N/A
SETUP
Program in Erase Suspend Busy Program Suspend in Erase Suspend Program in Erase Suspend Busy Erase Suspend FPA Busy FPA Busy7 Verify Busy7 Erase Suspend (Lock Error) Ready (Error) FPA Verify Ready FPA Busy7 FPA Verify7 Ready Erase Suspend
PROGRAM IN ERASE SUSPEND
BUSY
Program in Erase Suspend Busy
Program in Erase Suspend Busy
SUSPEND
Program Suspend in Erase Suspend
Program Suspend in Erase Suspend
N/A
LOCK/RCR SETUP IN ERASE SUSPEND SETUP FAST PROGRAMMING ALGORITHM FPA BUSY FPA VERIFY
Erase Suspend (Lock Error) Ready (Error)
Erase Suspend
Erase Suspend (Lock Error) N/A
09005aef80b425b4 MT28F1284W18_D.fm - Rev. D, 11/03 EN
Table 27: Command State Machine Transition (continued)
Note that this table shows that the command state transitions are based on incoming commands. Only one partition can actively program or erase at a time.
DEVICE NEXT STATE AFTER COMMAND INPUT BLOCK ERASE CONFIRM, PROGRAM/ ERASE RESUME, UNLOCK BLOCK CONFIRM9 (D0h)
CURRENT CHIP STATE8
READ ARRAY3 (FFh)
PROGRAM SETUP4,5 (10h/40h)
ERASE SETUP4,5 (20h)
FPA SETUP4 (30h)
PROGRAM/ ERASE SUSPEND (B0h)
READ STATUS (70h)
CLEAR STATUS REGISTER 6 (50h)
READ ID/ QUERY (90h, 98h)
LOCK, UNLOCK, LOCK DOWN, RCR SETUP5 (60h)
OTP SETUP5 (C0h)
LOCK BLOCK CONFIRM9 (01h)
LOCK DOWN BLOCK CONFIRM9 (2Fh)
WRITE RCR CONFIRM9 (03h)
FPA EXIT (ADDRESS BA) (FFFFh)
ILLEGAL COMMANDS OR FPA DATA (OTHER CODES)2
WSM OPERATION COMPLETES
OUTPUT NEXT STATE AFTER COMMAND INPUT1 PROGRAM SETUP, ERASE SETUP, OTP SETUP, PROGRAM IN ERASE SUSPEND SETUP, FPA SETUP, FPA BUSY, VERIFY BUSY LOCK/RCR SETUP, LOCK/RCR SETUP IN ERASE SUSPEND OTP BUSY READY, PROGRAM BUSY, PROGRAM SUSPEND, ERASE BUSY, ERASE SUSPEND, PROGRAM IN ERASE SUSPEND BUSY, PROGRAM SUSPEND IN ERASE SUSPEND
Status
Status Status Array3 Output does not change
Array
Status Output does not change
Status
Output does not change
Status
Status ID/ Query
Status
Output does not change
Array
Output does not change
NOTE: 1. The output state shows the type of data that appears at the outputs if the block address is the same as the command address.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
64
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, Micron Technology, Inc.
2. Illegal commands are those not defined in the command set. 3. All blocks default to read array mode at power up. 4. Both cycles of two-cycle commands should be issued to the same block address. If they are issued to different blocks, the second WRITE determines the active block. 5. If the CSM is active, both cycles of a two-cycle command are ignored. 6. The CLEAR STATUS command clears the status register error bits except when the CSM is running or during SUSPEND. 7. FPA writes are allowed only when SR0 = 0. FPA is busy if BA = address at FPA CONFIRM command. Any other commands are treated as data. 8. The current state is that of the WSM, not the block. 9. Confirm commands perform the operation and the move to the ready state.
8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Figure 35: 56-Ball VFBGA
0.10 C 0.700 ±0.075
SEATING PLANE C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3% Ag , 0.5% Cu 5.25 SUBSTRATE: PLASTIC LAMINATE BALL A1 ID MOLD COMPOUND: EPOXY NOVOLAC BALL A1 ID BALL A1 4.50 ±0.05
56X Ø 0.375 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW BALL DIAMETER IS 0.35 ON A 0.30 SMD BALL PAD.
0.75 TYP
BALL A8 4.50 2.25 ±0.05 0.75 TYP 9.00 ±0.10
1.00 MAX 2.625 ±0.050 11.00 ±0.10 5.50 ±0.05
NOTE: 1. All dimensions in millimeters.
Data Sheet Designation
Production: This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
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8 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY
Revision History
Rev. D, Production .........................................................................................................................................................11/03 Updated Vcc and VCCQ MINs Updated DC Table Updated CFI Table Removed TBDs from Timing Table Rev. C, Production .........................................................................................................................................................10/03 Added Lead-free package Updated DC Table Updated Erase and Program Timing Tables Updated CFI Table Rev. B, Advance ................................................................................................................................................................8/03 • Removed support for the “Interleaved” Burst Option • Expanded definition for tACLK • Updated VFBGA package drawing and notes • Added value for tCEWV and tCEWZ Original document, Rev A., Advance .............................................................................................................................3/03
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology. Inc.
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