MT29F128G08AJAAAWP-ITZ:A

Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features NAND Flash Memory MT29F32G08ABAAA, MT29F64G08AFAAA, MT29F128G08A[J/K/M]AAA MT29F256G08AUAAA, MT29F32G08ABCAB, MT29F64G08AECAB MT29F128G08A[K/M]CAB, MT29F256G08AUCAB Features • Operation status byte provides software method for detecting – Operation completion – Pass/fail condition – Write-protect status • Data strobe (DQS) signals provide a hardware method for synchronizing data DQ in the synchronous interface • Copyback operations supported within the plane from which data is read • Quality and reliability – Data retention: JESD47G compliant; see qualification report – Endurance: 60,000 PROGRAM/ERASE cycles • Operating temperature: – Commercial: 0°C to +70°C – Industrial (IT): –40ºC to +85ºC • Package – 52-pad LGA – 48-pin TSOP – 100-ball BGA – 132-ball BGA • Open NAND Flash Interface (ONFI) 2.2-compliant1 • Single-level cell (SLC) technology • Organization – Page size x8: 8640 bytes (8192 + 448 bytes) – Block size: 128 pages (1024K + 56K bytes) – Plane size: 2 planes x 2048 blocks per plane – Device size: 32Gb: 4096 blocks; 64Gb: 8192 blocks; 128Gb: 16,384 blocks; 256Gb: 32,768 blocks • Synchronous I/O performance – Up to synchronous timing mode 5 – Clock rate: 10ns (DDR) – Read/write throughput per pin: 200 MT/s • Asynchronous I/O performance – Up to asynchronous timing mode 5 – tRC/tWC: 20ns (MIN) – Read/write throughput per pin: 50 MT/s • Array performance – Read page: 35µs (MAX) – Program page: 350µs (TYP) – Erase block: 1.5ms (TYP) • Operating Voltage Range – VCC: 2.7–3.6V – VCCQ: 1.7–1.95V, 2.7–3.6V • Command set: ONFI NAND Flash Protocol • Advanced Command Set – Program cache – Read cache sequential – Read cache random – One-time programmable (OTP) mode – Multi-plane commands – Multi-LUN operations – Read unique ID – Copyback • First block (block address 00h) is valid when shipped from factory. For minimum required ECC, see Error Management (page 114). • RESET (FFh) required as first command after power-on PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Note: 1 1. The ONFI 2.2 specification is available at www.onfi.org. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Part Numbering MT 29F 32G 08 A B A A A WP Z Micron Technology Design Revision Production Status 29F = NAND Flash memory Blank = Production ES = Engineering sample Density Reserved for Future Use 32G = 32Gb 64G = 64Gb 128G = 128Gb 256G = 256Gb Blank Wafer Process Applied Blank = Polyimide Process Not Applied Z = Polyimide Process Applied Device Width 08 = 8 bits Operating Temperature Range Blank = Commercial (0°C to +70°C) IT = Industrial (–40°C to +85°C) Level Bit/Cell Speed Grade (synchronous mode only) 1-bit -10 = 200 MT/s Classification Package Code C5 = 52-pad VLGA 14mm x 18mm x 1.0mm1 H1 = 100-ball VBGA 12mm x 18mm x 1.0mm1 H2 = 100-ball TBGA 12mm x 18mm x 1.2mm1 H3 = 100-ball LBGA 12mm x 18mm x 1.4mm1 J1 = 132-ball VBGA 12mm x 18mm x 1.0mm1 J2 = 132-ball TBGA 12mm x 18mm x 1.2mm1 J3 = 132-ball LBGA 12mm x 18mm x 1.4mm1 WP = 48-pin TSOP1 (CPL) Die # of CE# # of R/B# I/O B 1 1 1 E 2 2 2 Separate F 2 2 2 Common J 4 2 2 Common K 4 2 2 Separate M 4 4 4 Separate U 8 4 4 Separate Common Interface A = Async only B = Sync/Async Operating Voltage Range A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V) C = VCC: 3.3V (2.7–3.6V), VCCQ: 1.8V (1.7–1.95V) Note: :A A = First revision NAND Flash A ES Generation Feature Set A = First set of device features 1. Pb-free package. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features Contents General Description ......................................................................................................................................... 9 Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9 Signal Assignments ......................................................................................................................................... 11 Package Dimensions ....................................................................................................................................... 15 Architecture ................................................................................................................................................... 23 Device and Array Organization ........................................................................................................................ 24 Bus Operation – Asynchronous Interface ......................................................................................................... 32 Asynchronous Enable/Standby ................................................................................................................... 32 Asynchronous Bus Idle ............................................................................................................................... 32 Asynchronous Pausing Data Input/Output .................................................................................................. 33 Asynchronous Commands .......................................................................................................................... 33 Asynchronous Addresses ............................................................................................................................ 34 Asynchronous Data Input ........................................................................................................................... 35 Asynchronous Data Output ......................................................................................................................... 36 Write Protect .............................................................................................................................................. 37 Ready/Busy# .............................................................................................................................................. 37 Bus Operation – Synchronous Interface ........................................................................................................... 42 Synchronous Enable/Standby ..................................................................................................................... 43 Synchronous Bus Idle/Driving .................................................................................................................... 43 Synchronous Pausing Data Input/Output .................................................................................................... 44 Synchronous Commands ............................................................................................................................ 44 Synchronous Addresses .............................................................................................................................. 45 Synchronous DDR Data Input ..................................................................................................................... 46 Synchronous DDR Data Output .................................................................................................................. 47 Write Protect .............................................................................................................................................. 49 Ready/Busy# .............................................................................................................................................. 49 Device Initialization ....................................................................................................................................... 50 Activating Interfaces ....................................................................................................................................... 52 Activating the Asynchronous Interface ........................................................................................................ 52 Activating the Synchronous Interface .......................................................................................................... 52 Command Definitions .................................................................................................................................... 54 Reset Operations ............................................................................................................................................ 56 RESET (FFh) ............................................................................................................................................... 56 SYNCHRONOUS RESET (FCh) .................................................................................................................... 57 RESET LUN (FAh) ....................................................................................................................................... 58 Identification Operations ................................................................................................................................ 59 READ ID (90h) ............................................................................................................................................ 59 READ ID Parameter Tables .......................................................................................................................... 60 READ PARAMETER PAGE (ECh) .................................................................................................................. 61 Parameter Page Data Structure Tables ..................................................................................................... 62 READ UNIQUE ID (EDh) ............................................................................................................................ 72 Configuration Operations ............................................................................................................................... 73 SET FEATURES (EFh) .................................................................................................................................. 73 GET FEATURES (EEh) ................................................................................................................................. 74 Status Operations ........................................................................................................................................... 78 READ STATUS (70h) ................................................................................................................................... 79 READ STATUS ENHANCED (78h) ................................................................................................................ 80 Column Address Operations ........................................................................................................................... 81 CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 81 CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 82 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features CHANGE WRITE COLUMN (85h) ................................................................................................................ 83 CHANGE ROW ADDRESS (85h) ................................................................................................................... 84 Read Operations ............................................................................................................................................. 86 READ MODE (00h) ..................................................................................................................................... 88 READ PAGE (00h-30h) ................................................................................................................................ 89 READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 90 READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 91 READ PAGE CACHE LAST (3Fh) .................................................................................................................. 93 READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 94 Program Operations ....................................................................................................................................... 96 PROGRAM PAGE (80h-10h) ......................................................................................................................... 96 PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 98 PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................ 100 Erase Operations ........................................................................................................................................... 102 ERASE BLOCK (60h-D0h) ........................................................................................................................... 102 ERASE BLOCK MULTI-PLANE (60h-D1h) ................................................................................................... 103 Copyback Operations .................................................................................................................................... 104 COPYBACK READ (00h-35h) ...................................................................................................................... 105 COPYBACK PROGRAM (85h–10h) .............................................................................................................. 106 COPYBACK READ MULTI-PLANE (00h-32h) ............................................................................................... 106 COPYBACK PROGRAM MULTI-PLANE (85h-11h) ....................................................................................... 107 One-Time Programmable (OTP) Operations ................................................................................................... 108 PROGRAM OTP PAGE (80h-10h) ................................................................................................................ 109 PROTECT OTP AREA (80h-10h) .................................................................................................................. 110 READ OTP PAGE (00h-30h) ........................................................................................................................ 111 Multi-Plane Operations ................................................................................................................................. 112 Multi-Plane Addressing ............................................................................................................................. 112 Interleaved Die (Multi-LUN) Operations ......................................................................................................... 113 Error Management ........................................................................................................................................ 114 Output Drive Impedance ............................................................................................................................... 115 AC Overshoot/Undershoot Specifications ....................................................................................................... 118 Synchronous Input Slew Rate ......................................................................................................................... 119 Output Slew Rate ........................................................................................................................................... 120 Electrical Specifications ................................................................................................................................. 121 Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 124 Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 125 Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 125 Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 127 Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 129 Electrical Specifications – Array Characteristics .............................................................................................. 132 Asynchronous Interface Timing Diagrams ...................................................................................................... 133 Synchronous Interface Timing Diagrams ........................................................................................................ 144 Revision History ............................................................................................................................................ 166 Rev. H Production – 2/14 ............................................................................................................................ 166 Rev. G Production – 1/14 ............................................................................................................................ 166 Rev. F Production – 5/12 ............................................................................................................................ 166 Rev. E Production – 4/12 ............................................................................................................................ 166 Rev. D Production – 6/11 ............................................................................................................................ 166 Rev. C – 12/10 ............................................................................................................................................ 166 Rev. B – 7/10 .............................................................................................................................................. 167 Rev. A – 2/10 .............................................................................................................................................. 167 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features List of Tables Table 1: Asynchronous and Synchronous Signal Definitions .............................................................................. 9 Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 31 Table 3: Asynchronous Interface Mode Selection ............................................................................................ 32 Table 4: Synchronous Interface Mode Selection .............................................................................................. 42 Table 5: Command Set .................................................................................................................................. 54 Table 6: Read ID Parameters for Address 00h .................................................................................................. 60 Table 7: Read ID Parameters for Address 20h .................................................................................................. 60 Table 8: Parameter Page Data Structure .......................................................................................................... 62 Table 9: Feature Address Definitions .............................................................................................................. 73 Table 10: Feature Address 01h: Timing Mode .................................................................................................. 75 Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 76 Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 76 Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 77 Table 14: Status Register Definition ................................................................................................................ 78 Table 15: OTP Area Details ............................................................................................................................ 109 Table 16: Error Management Details ............................................................................................................. 114 Table 17: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) ...................................................................... 115 Table 18: Output Drive Strength Impedance Values (V CCQ = 1.7–1.95V) ........................................................... 115 Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 116 Table 20: Output Drive Strength Impedance Values (V CCQ = 2.7–3.6V) ............................................................ 116 Table 21: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 117 Table 22: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 118 Table 23: Synchronous Overshoot/Undershoot Parameters ............................................................................ 118 Table 24: Test Conditions for Input Slew Rate ................................................................................................ 119 Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) ................................................................................................. 119 Table 26: Test Conditions for Output Slew Rate .............................................................................................. 120 Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) ............................................................................................... 120 Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 120 Table 29: Absolute Maximum Ratings by Device ............................................................................................ 121 Table 30: Recommended Operating Conditions ............................................................................................. 121 Table 31: Valid Blocks per LUN ...................................................................................................................... 121 Table 32: Capacitance: 100-Ball BGA Package ................................................................................................ 122 Table 33: Capacitance: 132-Ball BGA Package ................................................................................................ 123 Table 34: Capacitance: 48-Pin TSOP Package ................................................................................................. 123 Table 35: Capacitance: 52-Pad LGA Package .................................................................................................. 123 Table 36: Test Conditions .............................................................................................................................. 124 Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 124 Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 125 Table 39: DC Characteristics and Operating Conditions (3.3V V CCQ) ............................................................... 125 Table 40: DC Characteristics and Operating Conditions (1.8V V CCQ) ............................................................... 126 Table 41: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 127 Table 42: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 129 Table 43: Array Characteristics ...................................................................................................................... 132 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features List of Figures Figure 1: Part Numbering ................................................................................................................................ 2 Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 11 Figure 3: 52-Pad LGA (Top View) .................................................................................................................... 12 Figure 4: 100-Ball BGA (Ball-Down, Top View) ................................................................................................ 13 Figure 5: 132-Ball BGA (Ball-Down, Top View) ................................................................................................ 14 Figure 6: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 15 Figure 7: 52-Pad VLGA ................................................................................................................................... 16 Figure 8: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) ......................................................................... 17 Figure 9: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) ......................................................................... 18 Figure 10: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) ....................................................................... 19 Figure 11: 132-Ball VBGA – 12mm x 18mm (Package Code: J1) ......................................................................... 20 Figure 12: 132-Ball TBGA – 12mm x 18mm (Package Code: J2) ......................................................................... 21 Figure 13: 132-Ball LBGA – 12mm x 18mm (Package Code: J3) ......................................................................... 22 Figure 14: NAND Flash Die (LUN) Functional Block Diagram .......................................................................... 23 Figure 15: Device Organization for Single-Die Package (TSOP/BGA) ................................................................ 24 Figure 16: Device Organization for Two-Die Package (TSOP) ........................................................................... 25 Figure 17: Device Organization for Two-Die Package (BGA) ............................................................................. 26 Figure 18: Device Organization for Four-Die Package (TSOP) .......................................................................... 27 Figure 19: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) ....................................... 28 Figure 20: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) ................... 29 Figure 21: Device Organization for Eight-Die Package (BGA/LGA) ................................................................... 30 Figure 22: Array Organization per Logical Unit (LUN) ..................................................................................... 31 Figure 23: Asynchronous Command Latch Cycle ............................................................................................ 33 Figure 24: Asynchronous Address Latch Cycle ................................................................................................ 34 Figure 25: Asynchronous Data Input Cycles .................................................................................................... 35 Figure 26: Asynchronous Data Output Cycles ................................................................................................. 36 Figure 27: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 37 Figure 28: READ/BUSY# Open Drain .............................................................................................................. 38 Figure 29: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 39 Figure 30: tFall and tRise (VCCQ = 1.7-1.95V) .................................................................................................... 39 Figure 31: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 40 Figure 32: IOL vs Rp (VCCQ = 1.7-1.95V) .......................................................................................................... 40 Figure 33: TC vs Rp ........................................................................................................................................ 41 Figure 34: Synchronous Bus Idle/Driving Behavior ......................................................................................... 44 Figure 35: Synchronous Command Cycle ....................................................................................................... 45 Figure 36: Synchronous Address Cycle ........................................................................................................... 46 Figure 37: Synchronous DDR Data Input Cycles ............................................................................................. 47 Figure 38: Synchronous DDR Data Output Cycles ........................................................................................... 49 Figure 39: R/B# Power-On Behavior ............................................................................................................... 50 Figure 40: Activating the Synchronous Interface ............................................................................................. 53 Figure 41: RESET (FFh) Operation .................................................................................................................. 56 Figure 42: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 57 Figure 43: RESET LUN (FAh) Operation .......................................................................................................... 58 Figure 44: READ ID (90h) with 00h Address Operation .................................................................................... 59 Figure 45: READ ID (90h) with 20h Address Operation .................................................................................... 59 Figure 46: READ PARAMETER (ECh) Operation .............................................................................................. 61 Figure 47: READ UNIQUE ID (EDh) Operation ............................................................................................... 72 Figure 48: SET FEATURES (EFh) Operation .................................................................................................... 74 Figure 49: GET FEATURES (EEh) Operation .................................................................................................... 74 Figure 50: READ STATUS (70h) Operation ...................................................................................................... 80 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features Figure 51: READ STATUS ENHANCED (78h) Operation ................................................................................... 80 Figure 52: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 81 Figure 53: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation .......................................................... 82 Figure 54: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 83 Figure 55: CHANGE ROW ADDRESS (85h) Operation ...................................................................................... 85 Figure 56: READ PAGE (00h-30h) Operation ................................................................................................... 89 Figure 57: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 90 Figure 58: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 92 Figure 59: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 93 Figure 60: READ PAGE MULTI-PLANE (00h-32h) Operation ............................................................................ 95 Figure 61: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 97 Figure 62: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 99 Figure 63: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 99 Figure 64: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation ................................................................... 101 Figure 65: ERASE BLOCK (60h-D0h) Operation ............................................................................................. 102 Figure 66: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation ...................................................................... 103 Figure 67: COPYBACK READ (00h-35h) Operation ......................................................................................... 105 Figure 68: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation ......................... 105 Figure 69: COPYBACK PROGRAM (85h–10h) Operation ................................................................................. 106 Figure 70: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ........................ 106 Figure 71: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation .......................................................... 107 Figure 72: PROGRAM OTP PAGE (80h-10h) Operation ................................................................................... 109 Figure 73: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 110 Figure 74: PROTECT OTP AREA (80h-10h) Operation ..................................................................................... 111 Figure 75: READ OTP PAGE (00h-30h) Operation ........................................................................................... 111 Figure 76: Overshoot .................................................................................................................................... 118 Figure 77: Undershoot .................................................................................................................................. 118 Figure 78: RESET Operation .......................................................................................................................... 133 Figure 79: RESET LUN Operation .................................................................................................................. 133 Figure 80: READ STATUS Cycle ..................................................................................................................... 134 Figure 81: READ STATUS ENHANCED Cycle .................................................................................................. 134 Figure 82: READ PARAMETER PAGE ............................................................................................................. 135 Figure 83: READ PAGE .................................................................................................................................. 135 Figure 84: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 136 Figure 85: CHANGE READ COLUMN ............................................................................................................ 137 Figure 86: READ PAGE CACHE SEQUENTIAL ................................................................................................ 138 Figure 87: READ PAGE CACHE RANDOM ...................................................................................................... 139 Figure 88: READ ID Operation ...................................................................................................................... 140 Figure 89: PROGRAM PAGE Operation .......................................................................................................... 140 Figure 90: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 141 Figure 91: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ......................................................... 141 Figure 92: PROGRAM PAGE CACHE .............................................................................................................. 142 Figure 93: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 142 Figure 94: COPYBACK .................................................................................................................................. 143 Figure 95: ERASE BLOCK Operation .............................................................................................................. 143 Figure 96: SET FEATURES Operation ............................................................................................................ 144 Figure 97: READ ID Operation ...................................................................................................................... 145 Figure 98: GET FEATURES Operation ............................................................................................................ 146 Figure 99: RESET (FCh) Operation ................................................................................................................ 147 Figure 100: READ STATUS Cycle ................................................................................................................... 148 Figure 101: READ STATUS ENHANCED Operation ......................................................................................... 149 Figure 102: READ PARAMETER PAGE Operation ............................................................................................ 150 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Features Figure 103: Figure 104: Figure 105: Figure 106: Figure 107: Figure 108: Figure 109: Figure 110: Figure 111: Figure 112: Figure 113: Figure 114: Figure 115: Figure 116: Figure 117: Figure 118: Figure 119: Figure 120: Figure 121: Figure 122: READ PAGE Operation ................................................................................................................ 151 CHANGE READ COLUMN ........................................................................................................... 152 READ PAGE CACHE SEQUENTIAL (1 of 2) ................................................................................... 153 READ PAGE CACHE SEQUENTIAL (2 of 2) ................................................................................... 154 READ PAGE CACHE RANDOM (1 of 2) ......................................................................................... 155 READ PAGE CACHE RANDOM (2 of 2) ......................................................................................... 155 Multi-Plane Read Page (1 of 2) ..................................................................................................... 156 Multi-Plane Read Page (2 of 2) ..................................................................................................... 157 PROGRAM PAGE Operation (1 of 2) ............................................................................................. 158 PROGRAM PAGE Operation (2 of 2) ............................................................................................. 158 CHANGE WRITE COLUMN ......................................................................................................... 159 Multi-Plane Program Page ........................................................................................................... 160 ERASE BLOCK ............................................................................................................................ 161 COPYBACK (1 of 3) ..................................................................................................................... 161 COPYBACK (2 of 3) ..................................................................................................................... 162 COPYBACK (3 of 3) ..................................................................................................................... 162 READ OTP PAGE ......................................................................................................................... 163 PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 164 PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 164 PROTECT OTP AREA ................................................................................................................... 165 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND General Description General Description Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer commands, address, and data. There are five control signals used to implement the asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control hardware write protection (WP#) and monitor device status (R/B#). This Micron NAND Flash device additionally includes a synchronous data interface for high-performance I/O operations. When the synchronous interface is active, WE# becomes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe (DQS). This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign. A target is the unit of memory accessed by a chip enable signal. A target contains one or more NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred to as a logical unit (LUN). For further details, see Device and Array Organization. Asynchronous and Synchronous Signal Descriptions Table 1: Asynchronous and Synchronous Signal Definitions Asynchronous Signal1 Synchronous Signal1 Type Description2 ALE ALE Input Address latch enable: Loads an address from DQx into the address register. CE# CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target1. CLE CLE Input Command latch enable: Loads a command from DQx into the command register. DQx DQx I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and command information. – DQS I/O Data strobe: Provides a synchronous reference for data input and output. RE# W/R# Input Read enable and write/read: RE# transfers serial data from the NAND Flash to the host system when the asynchronous interface is active. When the synchronous interface is active, W/R# controls the direction of DQx and DQS. WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and serial data from the host system to the NAND Flash when the asynchronous interface is active. When the synchronous interface is active, CLK latches command and address cycles. WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE operations. R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires an external pull-up resistor. This signal indicates target array activity. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous and Synchronous Signal Descriptions Table 1: Asynchronous and Synchronous Signal Definitions (Continued) Asynchronous Signal1 Synchronous Signal1 Type VCC VCC Supply VCC: Core power supply VCCQ VCCQ Supply VCCQ: I/O power supply VSS VSS Supply VSS: Core ground connection VSSQ VSSQ Supply VSSQ: I/O ground connection NC NC – No connect: NCs are not internally connected. They can be driven or left unconnected. DNU DNU – Do not use: DNUs must be left unconnected. RFU RFU – Reserved for future use: RFUs must be left unconnected. Notes: Description2 1. See Device and Array Organization for detailed signal connections. 2. See Bus Operation – Asynchronous Interface (page 32) and Bus Operation – Synchronous Interface (page 42) for detailed asynchronous and synchronous interface signal descriptions. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Signal Assignments Signal Assignments Figure 2: 48-Pin TSOP Type 1 (Top View) Notes: Sync x8 Async x8 NC NC NC NC NC R/B2#1 R/B# W/R# CE# CE2#1 NC VCC VSS NC NC CLE ALE CLK WP# NC NC NC NC NC NC NC NC NC NC R/B2#1 R/B# RE# CE# CE2#1 NC VCC VSS NC NC CLE ALE WE# WP# NC NC NC NC NC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1l 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Async x8 Sync x8 DNU/VSSQ2 NC NC NC DQ7 DQ6 DQ5 DQ4 NC DNU/VCCQ2 DNU VCC VSS DNU DNU/VCCQ2 NC DQ3 DQ2 DQ1 DQ0 NC NC DNU DNU/VSSQ2 DNU/VSSQ2 NC NC NC DQ7 DQ6 DQ5 DQ4 NC DNU/VCCQ2 DNU VCC VSS DQS DNU/VCCQ2 NC DQ3 DQ2 DQ1 DQ0 NC NC DNU DNU/VSSQ2 1. CE2# and R/B2# are available on dual die and quad die packages. They are NC for other configurations. 2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or VSSQ to these pins, do not use them. 3. TSOP devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Signal Assignments Figure 3: 52-Pad LGA (Top View) 0 1 2 3 4 5 6 7 8 NC OA CE4#2 R/B4#2 A CE3#2 B OB VSS VCC NC CLE-21 ALE-1 CE2#1 ALE-21 D RE#-1 RE#-21 DNU OC DNU E WE#-21 F G J OD DNU/ VSS WE#-1 DQ0-21 VSS DQ0-1 DQ7-21 WP#-21 DQ1-1 DQ1-21 R/B2#1 R/B# WP#-1 H DQ7-1 DQ2-1 DQ6-21 DQ6-1 DNU K L DQ3-1 DQ2-21 DQ5-1 VSS DQ5-21 DQ4-1 DNU/ VSS NC M N OF R/B3#2 CE# NC C OE CLE-1 NC VSS DNU/ VCC VCC DQ3-21 DQ4-21 DNU/ VCC NC Top View, Pads Down Notes: 1. These signals are available on quad and octal die packages. They are NC for other configurations. 2. These signals are available on quad die four CE# or octal die packages. They are NC for other configurations. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Signal Assignments Figure 4: 100-Ball BGA (Ball-Down, Top View) 1 2 A NC NC B NC 4 5 6 7 8 9 10 NC NC A NC B D RFU DNU NC WP#-23 NC NC DNU RFU D E RFU DNU NC WP#-1 NC NC DNU RFU E F VCC VCC VCC VCC VCC VCC VCC VCC F G VSS VSS VSS VSS VSS VSS VSS VSS G H Vssq Vccq RFU RFU R/B2#3 R/B4#4 Vccq Vssq H J DQ0-23 DQ2-23 ALE-23 CE4#4 R/B# R/B3#4 DQ5-23 DQ7-23 J K DQ0-1 DQ2-1 ALE-1 CE3#4 CE2#3 CE# DQ5-1 DQ7-1 K L Vccq Vssq Vccq CLE-23 RE#-23 (W/R#-2) Vccq Vssq Vccq L M DQ1-23 DQ3-23 Vssq CLE-1 RE#-1 (W/R#-1) Vssq DQ4-23 DQ6-23 M N DQ1-1 DQ3-1 RFU N/A1 (DQS-23) RFU WE#-23 (CLK-2) DQ4-1 DQ6-1 N Vssq Vccq RFU N/A1 (DQS-1) RFU WE#-1 (CLK-1) Vccq Vssq P Notes: 3 T NC U NC NC 1 2 3 4 5 6 7 8 P NC T NC NC U 9 10 1. N/A: This signal is tri-stated when the asynchronous interface is active. 2. Signal names in parentheses are the signal names when the synchronous interface is active. 3. These signals are available on dual, quad, and octal die packages. They are NC for other configurations. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Signal Assignments 4. These signals are available on quad die four CE# or octal die packages. They are NC for other configurations. Figure 5: 132-Ball BGA (Ball-Down, Top View) 1 2 3 9 10 11 A NC NC NC NC NC NC A B NC NC NC NC NC NC B C R R R R R DNU C D R VCCQ VCCQ DQ3-2 VSS VCC DQ4-2 VCCQ VCCQ R D E R VSSQ DQ2-2 VSSQ DQS-21 W/R#-2 VSSQ DQ5-2 VSSQ R E F DQ0-2 DQ1-2 NC NC WE#-2 CLK-2 NC DQ6-2 DQ7-2 F G VSSQ VCCQ ALE-2 CLE-2 NC NC VCCQ VSSQ G H NC NC WP#-2 R CE4# 2 CE2# R R H J VSS VCC R/B# R/B3# R/B4# 2 R/B2# VCC VSS J K R R CE# CE3# 2 NC WP#-1 R R K VSSQ VCCQ NC NC CLE-1 ALE-1 VCCQ VSSQ DQ7-1 DQ6-1 NC WE#-1 CLK-1 NC NC DQ1-1 DQ0-1 VSSQ DQ2-1 VSSQ R N DQ3-1 VCCQ VCCQ R P L M 4 5 6 7 8 RE#-2 2 L M N R VSSQ DQ5-1 VSSQ W/R#-1 P R VCCQ VCCQ DQ4-1 VCC R R R R R R R T NC NC NC NC NC NC U NC NC NC NC NC NC 1 2 3 9 10 11 Notes: 4 RE#-1 5 1 DQS-1 VSS 6 7 8 R T U 1. N/A: This signal is tri-stated when the asynchronous interface is active. 2. These signals are available on quad die four CE# packages or octal die packages. They are NC for other configurations. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Package Dimensions Figure 6: 48-Pin TSOP – Type 1 CPL (Package Code: WP) 20.00 ±0.25 18.40 ±0.08 48 0.25 for reference only 0.50 TYP for reference only 1 Mold compound: Epoxy novolac Plated lead finish: 100% Sn Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side. 12.00 ±0.08 0.27 MAX 0.17 MIN 24 25 0.25 0.10 0.15 +0.03 -0.02 See detail A 1.20 MAX 0.10 Gage plane +0.10 -0.05 0.50 ±0.1 0.80 Detail A Note: 1. All dimensions are in millimeters. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 7: 52-Pad VLGA Seating plane 0.1 A See Detail B Substrate material: plastic laminate. Mold compound: epoxy novolac. 6 CTR 4 CTR 12X Ø11 8 7 6 5 4 3 2 1 OA 0 Terminal A1 ID B C D OC E F A A G 2 TYP Terminal A1 ID A OB 13 12 10 CTR CTR CTR See Note 1 Detail B2 Not to scale Section A–A 40X Ø0.71 A 18 ±0.1 H J OD K L OE M N OF 2 TYP 1.0 MAX including package bow. 2 TYP 10 CTR Bottom side saw fiducials may or may not be covered with soldermask. 14 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 8: 100-Ball VBGA – 12mm x 18mm (Package Code: H1) Seating plane A 0.12 A 100X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.4 SMD ball pads. Ball A1 ID (covered by SR) 10 9 8 7 6 5 4 3 2 Ball A1 ID 1 A B D E F G 18 ±0.1 H 10 CTR J K 16 CTR L M N P T 1 TYP U 1 TYP 0.9 ±0.1 0.25 MIN 9 CTR 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 9: 100-Ball TBGA – 12mm x 18mm (Package Code: H2) Seating plane A 0.12 A 100X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.4 SMD ball pads. Ball A1 ID (covered by SR) 10 9 8 7 6 5 4 3 2 Ball A1 ID 1 A B D E F G 16 CTR 18 ±0.1 H 10 CTR J K L M N P T 1 TYP U 1 TYP 1.1 ±0.1 9 CTR 0.25 MIN 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 10: 100-Ball LBGA – 12mm x 18mm (Package Code: H3) Seating plane 0.12 A A 100X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.40 SMD ball pads. Ball A1 ID (covered by SR) 10 9 8 7 6 5 4 3 2 Ball A1 ID 1 A B D E F 18 ±0.1 G H 10 CTR J K 16 CTR L M N P T 1 TYP U 1.3 ±0.1 0.25 MIN 1 TYP 9 CTR 12 ±0.1 Note: 1. All dimensions are in millimeters. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 11: 132-Ball VBGA – 12mm x 18mm (Package Code: J1) Seating plane A 132X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.4 SMD ball pads. 0.12 A Ball A1 ID (covered by SR) 11 10 9 8 7 5 4 3 Ball A1 ID 2 1 A B C D 18 ±0.1 E F 16 CTR G H J K L M N P R T 1 TYP U 1 TYP 0.25 MIN 0.9 ±0.1 10 CTR 12 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 12: 132-Ball TBGA – 12mm x 18mm (Package Code: J2) Seating plane A 132X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.4 SMD ball pads. 0.12 A Ball A1 ID (covered by SR) 11 10 9 8 7 5 4 3 Ball A1 ID 2 1 A B C D E F G 18 ±0.1 H J 16 CTR K L M N P R T 1 TYP U 1 TYP 0.25 MIN +0.1 1.1 –0.15 10 CTR 12 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Package Dimensions Figure 13: 132-Ball LBGA – 12mm x 18mm (Package Code: J3) Seating plane A 132X Ø0.45 Dimensions apply to solder balls post-reflow on Ø0.4 SMD ball pads. 11 10 9 8 7 0.12 A Ball A1 ID (covered by SR) 5 4 3 2 Ball A1 ID 1 A B C D E F G H 18 ±0.1 J 16 CTR K L M N P R T 1 TYP U 1 TYP 0.25 MIN 1.3 +0.1 –0.15 10 CTR 12 ±0.1 Notes: 1. All dimensions are in millimeters. 2. Solder ball material: SAC305 (96.5% Sn, 3% Ag, 0.5% Cu). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Architecture Architecture These devices use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same pins and received by I/O control circuits. The commands received at the I/O control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte by byte, through a data register and a cache register. The NAND Flash memory array is programmed and read using page-based operations and is erased using block-based operations. During normal page operations, the data and cache registers act as a single register. During cache operations, the data and cache registers operate independently to increase data throughput. The status register reports the status of die (LUN) operations. Figure 14: NAND Flash Die (LUN) Functional Block Diagram Vcc Async Vccq Vssq Sync DQ[7:0] DQ[7:0] N/A Vss I/O control DQS Address register Status register Command register CE# CLE CLE ALE ALE WE# CLK RE# WP# W/R# WP# R/B# R/B# Column decode Decode Column Control logic Row RowDecode Decode CE# NANDFlash Flash NAND array Array (2 planes) Data register Register Data Cache register Register Cache Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active. 2. Some devices do not include the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Device and Array Organization Figure 15: Device Organization for Single-Die Package (TSOP/BGA) Async Sync CE# CE# CLE CLE ALE ALE WE# CLK RE# W/R# Package Target 1 LUN 1 R/B# DQ[7:0] DQ[7:0] Note: N/A DQS WP# WP# 1. TSOP devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 16: Device Organization for Two-Die Package (TSOP) Note: Async Sync CE# CE# CLE CLE ALE ALE WE# CLK RE# W/R# DQ[7:0] DQ[7:0] N/A DQS WP# WP# CE2# CE2# CLE CLE ALE ALE WE# CLK RE# W/R# DQ[7:0] DQ[7:0] N/A DQS WP# WP# Package Target 1 LUN 1 R/B# Target 2 LUN 1 R/B2# 1. TSOP devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 17: Device Organization for Two-Die Package (BGA) Async Sync CE# CE# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE2# CE2# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 DQ[7:0]-2 DQ[7:0]-2 N/A DQS-2 WP#-2 WP#-2 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Package Target 1 LUN 1 R/B# Target 2 LUN 1 R/B2# 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 18: Device Organization for Four-Die Package (TSOP) Note: Async Sync CE# CE# CLE CLE ALE ALE WE# CLK RE# W/R# DQ[7:0] DQ[7:0] N/A DQS WP# WP# CE2# CE2# CLE CLE ALE ALE WE# CLK RE# W/R# DQ[7:0] DQ[7:0] N/A DQS WP# WP# Package Target 1 LUN 1 LUN 2 R/B# Target 2 LUN 1 LUN 2 R/B2# 1. TSOP devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 19: Device Organization for Four-Die Package with CE# and CE2# (BGA/LGA) Note: Async CE# Sync CE# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE2# CE2# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 DQ[7:0]-2 DQ[7:0]-2 N/A DQS-2 WP#-2 WP#-2 Package Target 1 LUN 1 LUN 2 R/B# Target 2 LUN 1 LUN 2 R/B2# 1. LGA devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 20: Device Organization for Four-Die Package with CE#, CE2#, CE3#, and CE4# (BGA/LGA) Async Sync CE# CE# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 Package Target 1 LUN 1 R/B# DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE2# CE2# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 Target 2 LUN 1 R/B2# DQ[7:0]-2 DQ[7:0]-2 N/A DQS-2 WP#-2 WP#-2 CE3# CE3# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 Target 3 LUN 1 R/B3# DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE4# CE4# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 Target 4 LUN 1 R/B4# DQ[7:0]-2 DQ[7:0]-2 Note: N/A DQS-2 WP#-2 WP#-2 1. LGA devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 21: Device Organization for Eight-Die Package (BGA/LGA) Async Sync CE# CE# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 Package Target 1 LUN 1 LUN 2 R/B# DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE2# CE2# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 Target 2 LUN 1 LUN 2 R/B2# DQ[7:0]-2 DQ[7:0]-2 N/A DQS-2 WP#-2 WP#-2 CE3# CE3# CLE-1 CLE-1 ALE-1 ALE-1 WE#-1 CLK-1 RE#-1 W/R#-1 Target 3 LUN 1 LUN 2 R/B3# DQ[7:0]-1 DQ[7:0]-1 N/A DQS-1 WP#-1 WP#-1 CE4# CE4# CLE-2 CLE-2 ALE-2 ALE-2 WE#-2 CLK-2 RE#-2 W/R#-2 Target 4 LUN 1 LUN 2 R/B4# DQ[7:0]-2 DQ[7:0]-2 Note: N/A DQS-2 WP#-2 WP#-2 1. LGA devices do not support the synchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device and Array Organization Figure 22: Array Organization per Logical Unit (LUN) Logical Unit (LUN) 8640 bytes 8640 bytes DQ7 Cache Registers 8192 448 8192 448 Data Registers 8192 448 8192 448 DQ0 1 page = (8K + 448 bytes) 1 block = (8K + 448) bytes x 128 pages = (1024K + 56K) bytes 2048 blocks per plane 1 Block 4096 blocks per LUN 1 Block 1 Block 1 plane = (1024K + 56K) bytes x 2048 blocks = 17,280Mb 1 LUN = 17,280Mb x 2 planes = 34,560Mb Plane 0 (0, 2, 4, ..., 4094) Plane 1 (1, 3, 5, ..., 4095) Table 2: Array Addressing for Logical Unit (LUN) Cycle DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA02 Second LOW LOW CA133 CA12 CA11 CA10 CA9 CA8 Third BA74 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 Fifth LOW LOW LOW LOW LA05 BA18 BA17 BA16 Notes: 1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the page address, block address, and LUN address are collectively called the row address. 2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle always returns one even byte and one odd byte. 3. Column addresses 8640 (21C0h) through 16,383 (3FFFh) are invalid, out of bounds, do not exist in the device, and cannot be addressed. 4. BA[7] is the plane-select bit: Plane 0: BA[7] = 0 Plane 1: BA[7] = 1 5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target; otherwise, it should be held LOW. LUN 0: LA0 = 0 LUN 1: LA0 = 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Bus Operation – Asynchronous Interface The asynchronous interface is active when the NAND Flash device powers on. The I/O bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS signal, if present, is tri-stated when the asynchronous interface is active. Asynchronous interface bus modes are summarized below. Table 3: Asynchronous Interface Mode Selection Mode CE# Standby H Bus idle Command input CLE ALE WE# RE# DQS Notes 2 X X X L X X H H X X X L H L H X input H Address input L L H H X input H Data input L L L H X input H Data output L L L H X output X Write protect X X X X X X L Notes: X WP# X X X DQx 0V/VCCQ 2 1. DQS is tri-stated when the asynchronous interface is active. 2. WP# should be biased to CMOS LOW or HIGH for standby. 3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL. Asynchronous Enable/Standby A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept commands, addresses, and data I/O. There may be more than one target in a NAND Flash package. Each target is controlled by its own chip enable; the first target (Target 0) is controlled by CE#; the second target (if present) is controlled by CE2#, etc. A target is disabled when CE# is driven HIGH, even when the target is busy. When disabled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionality is also known as CE# "Don't Care". While the target is disabled, other devices can utilize the disabled NAND signals that are shared with the NAND Flash. A target enters low-power standby when it is disabled and is not busy. If the target is busy when it is disabled, the target enters standby after all of the die (LUNs) complete their operations. Standby helps reduce power consumption. Asynchronous Bus Idle A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH. During bus idle, all of the signals are enabled except DQS, which is not used when the asynchronous interface is active. No commands, addresses, and data are latched into the target; no data is output. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Asynchronous Pausing Data Input/Output Pausing data input or data output is done by keeping WE# or RE# HIGH, respectively. Asynchronous Commands An asynchronous command is written from DQ[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH. Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs) even when they are busy. Figure 23: Asynchronous Command Latch Cycle CLE tCLS tCS tCLH tCH CE# tWP WE# tALS tALH tDS tDH ALE DQx COMMAND Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Asynchronous Addresses An asynchronous address is written from DQ[7:0] to the address register on the rising edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH. Bits that are not part of the address space must be LOW (see Device and Array Organization). The number of cycles required for each command varies. Refer to the command descriptions to determine addressing requirements (see Command Definitions). Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses are accepted by die (LUNs) even when they are busy; for example, address cycles that follow the READ STATUS ENHANCED (78h) command. Figure 24: Asynchronous Address Latch Cycle CLE tCLS tCS CE# tWP tWC tWH WE# tALS tALH ALE tDS tDH DQx Col add 1 Col add 2 Row add 1 Row add 2 Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 34 Row add 3 Undefined Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Asynchronous Data Input Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH. Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Figure 25: Asynchronous Data Input Cycles CLE tCLH CE# tALS tCH ALE tWP tWC tWP tWP WE# tWH tDS tDH DQx DIN M tDS tDH DIN M+1 tDS tDH DIN N Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Asynchronous Data Output Data can be output from a die (LUN) if it is in a READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH. If the host controller is using a tRC of 30ns or greater, the host can latch the data on the rising edge of RE# (see Figure 26 for proper timing). If the host controller is using a tRC of less than 30ns, the host can latch the data on the next falling edge of RE# (see Figure 27 (page 37) for extended data output (EDO) timing). Using the READ STATUS ENHANCED (78h) command prevents data contention following an interleaved die (multi-LUN) operation. After issuing the READ STATUS ENHANCED (78h) command, to enable data output, issue the READ MODE (00h) command. Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by first issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command. Figure 26: Asynchronous Data Output Cycles tCEA CE# tREA tREA tRP tCHZ tREA tREH tCOH RE# tRHZ tRHZ tRHOH DOUT DQx tRR DOUT DOUT tRC RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Figure 27: Asynchronous Data Output Cycles (EDO Mode) CE# tRC tRP tCHZ tREH tCOH RE# tREA tCEA DQx tREA tRHZ tRLOH tRHOH DOUT DOUT DOUT tRR RDY Don’t Care Write Protect The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When WP# is HIGH, PROGRAM and ERASE operations are enabled. It is recommended that the host drive WP# LOW during power-on until Vcc and Vccq are stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for additional details). WP# must be transitioned only when the target is not busy and prior to beginning a command sequence. After a command sequence is complete and the target is ready, WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command. The WP# signal is always an active input, even when CE# is HIGH. This signal should not be multiplexed with other signals. Ready/Busy# The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy (RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each die (LUN) contains a status register, it is possible to determine the independent status of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations for details regarding die (LUN) status). This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the target is ready, and transitions LOW when the target is busy. The signal's open-drain PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an interrupt pin on the system controller (see Figure 28 (page 38)). The combination of Rp and capacitive loading of the R/B# circuit determines the rise time of the R/B# signal. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10to 90-percent points on the R/B# waveform, the rise time is approximately two time constants (TC). TC = R × C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load. The fall time of the R/B# signal is determined mainly by the output impedance of the R/B# signal and the total load capacitance. Approximate Rp values using a circuit load of 100pF are provided in Figure 33 (page 41). The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and Vccq. Vcc (MAX) - Vol (MAX) IOL + Σil Where Σil is the sum of the input currents of all devices tied to the R/B# pin. Rp = Figure 28: READ/BUSY# Open Drain VCCQ Rp VCC To controller R/B# Open drain output IOL VSS Device PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Figure 29: tFall and tRise (VCCQ = 2.7-3.6V) 3.50 3.00 2.50 V tFall tRise 2.00 1.50 1.00 0.50 0.00 –1 0 2 4 0 2 4 TC 6 VCCQ 3.3V 1. tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC). 2. tRise dependent on external capacitance and resistive loading and output transistor impedance. 3. tRise primarily dependent on external pull-up resistor and external capacitive loading. 4. tFall = 10ns at 3.3V 5. See TC values in Figure 33 (page 41) for approximate Rp value and TC. Notes: Figure 30: tFall and tRise (VCCQ = 1.7-1.95V) 3.50 3.00 2.50 V tFall 2.00 tRise 1.50 1.00 0.50 0.00 -1 0 2 4 0 TC Notes: 1. 2. 3. 4. 2 4 6 VCCQ 1.8V tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC). tRise is primarily dependent on external pull-up resistor and external capacitive loading. tFall ≈ 7ns at 1.8V. See TC values in Figure 33 (page 41) for TC and approximate Rp value. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Figure 31: IOL vs Rp (VCCQ = 2.7-3.6V) 3.50 3.00 2.50 2.00 I (mA) 1.50 1.00 0.50 0.00 0 2000 400 0 6000 8000 10,000 12,000 Rp (Ω) IOL at Vccq (MAX) Figure 32: IOL vs Rp (VCCQ = 1.7-1.95V) 3.50 3.00 2.50 2.00 I (mA) 1.50 1.00 0.50 0.00 0 2000 4000 6000 8000 10,000 12,000 Rp (Ω) IOL at Vccq (MAX) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Asynchronous Interface Figure 33: TC vs Rp 1200 1000 800 T(ns) 600 400 200 0 0 2000 4000 6000 8000 Rp (Ω) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 41 10,000 12,000 Iol at VCCQ (MAX) RC = TC C = 100pF Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Bus Operation – Synchronous Interface These NAND Flash devices have two interfaces—a synchronous interface for fast data I/O transfer and an asynchronous interface that is backward compatible with existing NAND Flash devices. The NAND Flash command protocol for both the asynchronous and synchronous interfaces is identical. However, there are some differences between the asynchronous and synchronous interfaces when issuing command, address, and data I/O cycles using the NAND Flash signals. When the synchronous interface is activated on a target (see Activating Interfaces), the target is capable of high-speed DDR data transfers. Existing signals are redefined for high-speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The RE# signal becomes W/R#. CLK provides a clock reference to the NAND Flash device. DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND Flash device. During data input, DQS is controlled by the host controller while inputting data on DQ[7:0]. The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# signal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is latched LOW, the NAND Flash is driving the DQ bus and DQS. The synchronous interface bus modes are summarized below. Table 4: Synchronous Interface Mode Selection Mode CE# CLE ALE CLK W/R# DQS DQ[7:0] WP# Notes Standby H X X X X X X 0V/VCCQ 1, 2 Bus idle L L L H X X X Bus driving L L L L output output X Command input L H L H X input H 3 Address input L L H H X input H 3 Data input L H H H input H 4 Data output L H H L See Note 5 output X 5 Write protect X X X X X X L Undefined L L H L output output X Undefined L H L L output output X Notes: X 1. CLK can be stopped when the target is disabled, even when R/B# is LOW. 2. WP# should be biased to CMOS LOW or HIGH for standby. 3. Commands and addresses are latched on the rising edge of CLK. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface 4. During data input to the device, DQS is the “clock” that latches the data in the cache register. 5. During data output from the NAND Flash device, DQS is an output generated from CLK after tDQSCK delay. 6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH or VIL. Synchronous Enable/Standby In addition to the description found in Asynchronous Enable/Standby (page 32), the following requirements also apply when the synchronous interface is active. Before enabling a target, CLK must be running and ALE and CLE must be LOW. When CE# is driven LOW, all of the signals for the selected target are enabled. The target is not enabled until tCS completes; the target's bus is then idle. Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is driven HIGH, even when it is busy. All of the target's signals are disabled except CE#, WP#, and R/B#. After the target is disabled, CLK can be stopped. A target enters low-power standby when it is disabled and is not busy. If the target is busy when it is disabled, the target enters standby after all of the die (LUNs) complete their operations. Synchronous Bus Idle/Driving A target's bus is idle or driving when CLK is running, CE# is LOW, ALE is LOW, and CLE is LOW. The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses, or data are latched into the target; no data is output. When entering the bus idle mode, the host must wait a minimum of tCAD before changing the bus mode. In the bus idle mode, the only valid bus modes supported are: bus driving, command, address, and DDR data input. The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH, but no valid data is output. Following the bus driving mode, the only valid bus modes supported are bus idle and DDR data output. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Figure 34: Synchronous Bus Idle/Driving Behavior CE# CLE ALE CLK tCALS tCALS W/R# tDQSD tDQSHZ DQS DQ[7:0] Bus idle Bus driving Bus idle Undefined (driven by NAND) Note: 1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multiLUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data output contention. Synchronous Pausing Data Input/Output Pausing data input or data output is done by setting ALE and CLE to LOW. The host may continue data transfer by setting ALE and CLE to HIGH after the applicable tCAD time has passed. Synchronous Commands A command is written from DQ[7:0] to the command register on the rising edge of CLK when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH. After a command is latched—and prior to issuing the next command, address, or data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except when the clock period, tCK, is greater than tCAD. Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some commands, such as READ STATUS (70h) and READ STATUS ENHANCED (78h), are accepted by die (LUNs), even when they are busy. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Figure 35: Synchronous Command Cycle tCS tCH CE# tCALS tCALS tCALH CLE tCALS tCALH tCAD tCALS tCALH ALE tCKL tCKH CLK tCK W/R# tCALS tCAD starts here1 tCALH tDQSHZ DQS tCAS tCAH Command DQ[7:0] Undefined Note: Don’t Care 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s). Synchronous Addresses A synchronous address is written from DQ[7:0] to the address register on the rising edge of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH. After an address is latched—and prior to issuing the next command, address, or data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except when the clock period, tCK, is greater than tCAD. Bits not part of the address space must be LOW (see Device and Array Organization). The number of address cycles required for each command varies. Refer to the command descriptions to determine addressing requirements. Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some addresses such as address cycles that follow the READ STATUS ENHANCED (78h) command, are accepted by die (LUNs), even when they are busy. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Figure 36: Synchronous Address Cycle tCS tCH CE# tCALS tCALH CLE tCALS tCAD tCALS tCALH ALE tCKL tCKH tCALS tCALH CLK tCAD tCK starts here1 W/R# tCALS tCALH tDQSHZ DQS tCAS DQ[7:0] tCAH Address Undefined Don’t Care 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the command cycle is latched for subsequent command, address, data input, or data output cycle(s). Note: Synchronous DDR Data Input To enter the DDR data input mode, the following conditions must be met: • • • • • • CLK is running CE# is LOW W/R# is HIGH tCAD is met DQS is LOW ALE and CLE are HIGH on the rising edge of CLK Upon entering the DDR data input mode after tDQSS, data is written from DQ[7:0] to the cache register on each and every rising and falling edge of DQS (center-aligned) when CLK is running and the DQS to CLK skew meets tDSH and tDSS, CE# is LOW, W/R# is HIGH, and ALE and CLE are HIGH on the rising edge of CLK. To exit DDR data input mode, the following conditions must be met: • • • • CLK is running and the DQS to CLK skew meets tDSH and tDSS CE# is LOW W/R# is HIGH ALE and CLE are latched LOW on the rising edge of CLK PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface • The final two data bytes of the data input sequence are written to DQ[7:0] to the cache register on the rising and falling edges of DQS after the last cycle in the data input sequence in which ALE and CLE are latched HIGH. • DQS is held LOW for tWPST (after the final falling edge of DQS) Following tWPST, the bus enters bus idle mode and tCAD begins on the next rising edge of CLK. After tCAD starts, the host can disable the target if desired. Data input is ignored by die (LUNs) that are not selected or are busy. Figure 37: Synchronous DDR Data Input Cycles tCS tCH CE# tCALS tCALS tCALH CLE tCALH tCALS tCALS tCAD tCALS tCALH ALE tCKL tCKH tCALH tCALS CLK tCAD tCK starts here1 W/R# tDQSS tDSH tDSS tDSH tDSH tDSS tDSH tDSS DQS tWPRE DQ[7:0] tDQSH tDQSL tDQSH D1 D0 tDS tDH D2 D3 tDQSL tDQSH DN-2 DN-1 tDS tWPST DN tDH Don’t Care 1. When CE# remains LOW, tCAD begins at the first rising edge of the clock after tWPST completes. 2. tDSH (MIN) generally occurs during tDQSS (MIN). 3. tDSS (MIN) generally occurs during tDQSS (MAX). Notes: Synchronous DDR Data Output Data can be output from a die (LUN) if it is ready. Data output is supported following a READ operation from the NAND Flash array. To enter the DDR data output mode, the following conditions must be met: • • • • CLK is running CE# is LOW The host has released the DQ[7:0] bus and DQS W/R# is latched LOW on the rising edge of CLK to enable the selected die (LUN) to take ownership of the DQ[7:0] bus and DQS within tWRCK • tCAD is met • ALE and CLE are HIGH on the rising edge of CLK PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay of tDQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data edge-aligned to the rising and falling edges of DQS, with the first transition delayed by no more than tAC. DDR data output mode continues as long as CLK is running, CE# is LOW, W/R# is LOW, and ALE and CLE are HIGH on the rising edge of CLK. To exit DDR data output mode, the following conditions must be met: • • • • CLK is running CE# is LOW W/R# is LOW ALE and CLE are latched LOW on the rising edge of CLK The final two data bytes are output on DQ[7:0] on the final rising and falling edges of DQS. The final rising and falling edges of DQS occur tDQSCK after the last cycle in the data output sequence in which ALE and CLE are latched HIGH. After tCKWR, the bus enters bus idle mode and tCAD begins on the next rising edge of CLK. Once tCAD starts the host can disable the target if desired. Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); however, it is possible to output data from the status register even when a die (LUN) is busy by issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Bus Operation – Synchronous Interface Figure 38: Synchronous DDR Data Output Cycles tCS tCH CE# tCALS tCALS tCALH tCALS tCALH CLE tCALH tCALS tCALS tCAD ALE tCKL tCALH tCALS tCKH tHP CLK tHP tHP tHP tHP tHP tDQSCK tCK tCKWR tDQSCK tDQSCK tCALS tWRCK tCAD starts here1 tDQSCK tDQSCK tDQSCK W/R# tDQSD tCALS tDQSHZ DQS tAC DQ[7:0] tDQSQ tDVW tDVW tDVW D0 D1 D2 tDQSQ tQH tQH tDVW DN-2 tDQSQ Undefined (driven by NAND) Notes: DN-1 tDVW DN tDQSQ tQH tQH Don’t Care Data Transitioning 1. When CE# remains LOW, tCAD begins at the rising edge of the clock after tCKWR for subsequent command or data output cycle(s). 2. See Figure 35 (page 45) for details of W/R# behavior. 3. tAC is the DQ output window relative to CLK and is the long-term component of DQ skew. 4. For W/R# transitioning HIGH, DQ[7:0] and DQS go to tri-state. 5. For W/R# transitioning LOW, DQ[7:0] drives current state and DQS goes LOW. 6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid. Write Protect See Write Protect (page 37). Ready/Busy# See Ready/Busy# (page 37). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device Initialization Device Initialization Some NAND Flash devices do not support V CCQ. For these devices all references to V CCQ are replaced with V CC. Micron NAND Flash devices are designed to prevent data corruption during power transitions. V CC is internally monitored. (The WP# signal supports additional hardware protection during power transitions.) When ramping V CC and V CCQ, use the following procedure to initialize the device: 1. Ramp V CC. 2. Ramp V CCQ. V CCQ must not exceed V CC. 3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to any target (see Figure 39). The R/B# signal becomes valid when 50µs has elapsed since the beginning the V CC ramp, and 10µs has elapsed since V CCQ reaches V CCQ (MIN) and V CC reaches V CC (MIN). 4. If not monitoring R/B#, the host must wait at least 100µs after V CCQ reaches V CCQ (MIN) and V CC reaches V CC (MIN). If monitoring R/B#, the host must wait until R/B# is HIGH. 5. The asynchronous interface is active by default for each target. Each LUN draws less than an average of IST measured over intervals of 1ms until the RESET (FFh) command is issued. 6. The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for tPOR after a RESET command is issued. The RESET busy time can be monitored by polling R/B# or issuing the READ STATUS (70h) command to poll the status register. 7. The device is now initialized and ready for normal operation. At power-down, V CCQ must go LOW, either before, or simultaneously with, V CC going LOW. Figure 39: R/B# Power-On Behavior 50µs (MIN) Vccq = Vccq (MIN) Vccq 10µs (MAX) Vcc = Vcc (MIN) Vcc > 0µs R/B# 100µs (MAX) Vcc ramp starts Reset (FFh) is issued Invalid Note: 1. Disregard VCCQ for devices that use only VCC. To initialize a discovered target, the following steps shall be taken. The initialization process should be followed for each connected CE# signal, including performing the READ PARAMETER PAGE (ECh) command for each target. Each chip enable corre- PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Device Initialization sponds to a unique target with its own independent properties that the host shall observe and subsequently use. The host should issue the READ PARAMETET PAGE (ECh) command. This command returns information that includes the capabilities, features, and operating parameters of the device. When the information is read from the device, the host shall check the CRC to ensure that the data was received correctly and without error prior to taking action on that data. If the CRC of the first parameter page read is not valid, the host should read redundant parameter page copies. The host can determine whether a redundant parameter page is present or not by checking if the first four bytes contain at least two bytes of the parameter page signature. If the parameter page signature is present, then the host should read the entirety of that redundant parameter page. The host should then check the CRC of that redundant parameter page. If the CRC is correct, the host may take action based on the contents of that redundant parameter page. If the CRC is incorrect, then the host should attempt to read the next redundant parameter page by the same procedure. The host should continue reading redundant parameter pages until the host is able to accurately reconstruct the parameter page contents. The host may use bit-wise majority or other ECC techniques to recover the contents of the parameter page from the parameter page copies present. When the host determines that a parameter page signature is not present, then all parameter pages have been read. After successfully retrieving the parameter page, the host has all information necessary to successfully communicate with that target. If the host has not previously mapped defective block information for this target, the host should next map out all defective blocks in the target. The host may then proceed to utilize the target, including erase and program operations. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Activating Interfaces Activating Interfaces After performing the steps under Device Initialization (page 50), the asynchronous interface is active for all targets on the device. Each target's interface is independent of other targets, so the host is responsible for changing the interface for each target. If the host and NAND Flash device, through error, are no longer using the same interface, then steps under Activating the Asynchronous Interface are performed to resynchronize the interfaces. Activating the Asynchronous Interface To activate the asynchronous NAND interface, once the synchronous interface is active, the following steps are repeated for each target: 1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous interface. 2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asynchronous command cycle. 3. R/B# goes LOW for tRST. 4. After tITC, and during tRST, the device enters the asynchronous NAND interface. READ STATUS (70h) and READ STATUS ENHANCED (78h) are the only commands that can be issued. 5. After tRST, R/B# goes HIGH. Timing mode feature address (01h), subfeature parameter P1 is set to 00h, indicating that the asynchronous NAND interface is active and that the device is set to timing mode 0. For further details, see Reset Operations. Activating the Synchronous Interface To activate the synchronous NAND Flash interface, the following steps are repeated for each target: 1. Issue the SET FEATURES (EFh) command. 2. Write address 01h, which selects the timing mode. 3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous interface (see Configuration Operations). 4. Write P2–P4 as 00h-00h-00h. 5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host should not issue any type of command, including status commands, to the NAND Flash device. 6. After tITC, R/B# goes HIGH and the synchronous interface is enabled. Before pulling CE# LOW, the host should enable the clock. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Activating Interfaces Figure 40: Activating the Synchronous Interface CE# may transition HIGH A Cycle type CMD ADDR DIN DIN DIN DIN TM P2 P3 P4 B CE# may transition LOW C tADL DQ[7:0] EFh 01h tWB tITC R/B# tCAD 100ns Note: 1. TM = Timing mode. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Command Definitions Command Definitions Table 5: Command Set Command Cycle #1 Number of Valid Address Cycles Data Input Cycles RESET FFh 0 – – Yes Yes SYNCHRONOUS RESET FCh 0 – – Yes Yes RESET LUN FAh 3 – – Yes Yes READ ID 90h 1 – – READ PARAMETER PAGE ECh 1 – – READ UNIQUE ID EDh 1 – – GET FEATURES EEh 1 – – 3 SET FEATURES EFh 1 4 – 4 READ STATUS 70h 0 – – Yes READ STATUS ENHANCED 78h 3 – – Yes Command Valid While Command Selected LUN Cycle #2 is Busy1 Valid While Other LUNs are Busy2 Notes Reset Operations Identification Operations 3 Configuration Operations Status Operations Yes Column Address Operations CHANGE READ COLUMN 05h 2 – E0h Yes CHANGE READ COLUMN ENHANCED 06h 5 – E0h Yes CHANGE WRITE COLUMN 85h 2 Optional – Yes CHANGE ROW ADDRESS 85h 5 Optional – Yes READ MODE 00h 0 – – Yes READ PAGE 00h 5 – 30h Yes READ PAGE MULTIPLANE 00h 5 – 32h Yes READ PAGE CACHE SEQUENTIAL 31h 0 – – Yes 7 READ PAGE CACHE RANDOM 00h 5 – 31h Yes 6,7 READ PAGE CACHE LAST 3Fh 0 – – Yes 7 PROGRAM PAGE 80h 5 Yes 10h Yes PROGRAM PAGE MULTI-PLANE 80h 5 Yes 11h Yes 5 Read Operations 6 Program Operations PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Command Definitions Table 5: Command Set (Continued) Command Cycle #1 Number of Valid Address Cycles Data Input Cycles 80h 5 Yes ERASE BLOCK 60h 3 ERASE BLOCK MULTI-PLANE 60h COPYBACK READ Valid While Other LUNs are Busy2 Notes 15h Yes 8 – D0h Yes 3 – D1h Yes 00h 5 – 35h Yes COPYBACK PROGRAM 85h 5 Optional 10h Yes COPYBACK PROGRAM MULTI-PLANE 85h 5 Optional 11h Yes Command PROGRAM PAGE CACHE Valid While Command Selected LUN Cycle #2 is Busy1 Erase Operations Copyback Operations Notes: 6 1. Busy means RDY = 0. 2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved Die (Multi-LUN) Operations (page 113)). 3. The READ ID (90h) and GET FEATURES (EEh) output identical data on rising and falling DQS edges. 4. The SET FEATURES (EFh) command requires data transition prior to the rising edge of CLK, with identical data for the rising and falling edges. 5. Command cycle #2 of 11h is conditional. See CHANGE ROW ADDRESS (85h) for more details. 6. This command can be preceded by up to one READ PAGE MULTI-PLANE (00h-32h) command to accommodate a maximum simultaneous two-plane array operation. 7. Issuing a READ PAGE CACHE-series (31h, 00h-31h, 00h-32h, 3Fh) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h) or READ PAGE CACHE-series command; otherwise, it is prohibited. 8. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1, ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE (80h-15h) command; otherwise, it is prohibited. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Reset Operations Reset Operations RESET (FFh) The RESET (FFh) command is used to put a target into a known condition and to abort command sequences in progress. This command is accepted by all die (LUNs), even when they are busy. When FFh is written to the command register, the target goes busy for tRST. During the selected target (CE#) discontinues all array operations on all die (LUNs). All pending single- and multi-plane operations are cancelled. If this command is issued while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data may be partially programmed or erased and is invalid. The command register is cleared and ready for the next command. The data register and cache register contents are invalid. tRST, RESET must be issued as the first command to each target following power-up (see Device Initialization). Use of the READ STATUS ENHANCED (78h) command is prohibited during the power-on RESET. To determine when the target is ready, use READ STATUS (70h). If the RESET (FFh) command is issued when the synchronous interface is enabled, the target's interface is changed to the asynchronous interface and the timing mode is set to 0. The RESET (FFh) command can be issued asynchronously when the synchronous interface is active, meaning that CLK does not need to be continuously running when CE# is transitioned LOW and FFh is latched on the rising edge of CLK. After this command is latched, the host should not issue any commands during tITC. After tITC, and during or after tRST, the host can poll each LUN's status register. If the RESET (FFh) command is issued when the asynchronous interface is active, the target's asynchronous timing mode remains unchanged. During or after tRST, the host can poll each LUN's status register. Figure 41: RESET (FFh) Operation Cycle type DQ[7:0] Command FFh tWB tRST R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Reset Operations SYNCHRONOUS RESET (FCh) When the synchronous interface is active, the SYNCHRONOUS RESET (FCh) command is used to put a target into a known condition and to abort command sequences in progress. This command is accepted by all die (LUNs), even when they are BUSY. When FCh is written to the command register, the target goes busy for tRST. During the selected target (CE#) discontinues all array operations on all die (LUNs). All pending single- and multi-plane operations are cancelled. If this command is issued while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data may be partially programmed or erased and is invalid. The command register is cleared and ready for the next command. The data register and cache register contents are invalid and the synchronous interface remains active. tRST, During or after tRST, the host can poll each LUN's status register. SYNCHRONOUS RESET is only accepted while the synchronous interface is active. Its use is prohibited when the asynchronous interface is active. Figure 42: SYNCHRONOUS RESET (FCh) Operation Cycle type DQ[7:0] Command FCh tWB tRST R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Reset Operations RESET LUN (FAh) The RESET LUN (FAh) command is used to put a particular LUN on a target into a known condition and to abort command sequences in progress. This command is accepted by only the LUN addressed by the RESET LUN (FAh) command, even when that LUN is busy. When FAh is written to the command register, the addressed LUN goes busy for tRST. During tRST, the selected LUN discontinues all array operations. All pending single- and multi-plane operations are canceled. If this command is issued while a PROGRAM or ERASE operation is occurring on the addressed LUN, the data may be partially programmed or erased and is invalid. The command register is cleared and ready for the next command. The data register and cache register contents are invalid. If the RESET LUN (FAh) command is issued when the synchronous interface is enabled, the targets's interface remains in synchronous mode. If the RESET LUN (FAh) command is issued when the asynchronous interface is enabled, the target's interface remains in asynchronous mode. During or after tRST, the host can poll each LUN's status register. The RESET LUN (FAh) command is prohibited when not in the default array operation mode. The RESET LUN (FAh) command can only be issued to a target (CE#) after the RESET (FFh) command has been issued as the first command to a target following power-up. Figure 43: RESET LUN (FAh) Operation Cycle type DQ[7:0] Command Address Address Address FAh R1 R2 R3 tWB tRST R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Identification Operations READ ID (90h) The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing 90h to the command register puts the target in read ID mode. The target stays in this mode until another valid command is issued. When the 90h command is followed by a 00h address cycle, the target returns a 5-byte identifier code that includes the manufacturer ID, device configuration, and part-specific information. When the 90h command is followed by a 20h address cycle, the target returns the 4-byte ONFI identifier code. After the 90h and address cycle are written to the target, the host enables data output mode to read the identifier information. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one data byte is output per rising edge of DQS when ALE and CLE are HIGH; the data byte on the falling edge of DQS is identical to the data byte output on the previous rising edge of DQS. Figure 44: READ ID (90h) with 00h Address Operation Cycle type Command Address DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 tWHR DQ[7:0] Note: 90h 00h 1. See the READ ID Parameter tables for byte definitions. Figure 45: READ ID (90h) with 20h Address Operation Cycle type Command Address DOUT DOUT DOUT DOUT 4Fh 4Eh 46h 49h tWHR DQ[7:0] Note: 90h 20h 1. See the READ ID Parameter tables for byte definitions. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations READ ID Parameter Tables Table 6: Read ID Parameters for Address 00h Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 MT29F32G08ABAAA 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F32G08ABCAB 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F64G08AFAAA 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F64G08AECAB 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F128G08AJAAA 2Ch 88h 01h A7h A9h 00h 00h 00h MT29F128G08AKAAA 2Ch 88h 01h A7h A9h 00h 00h 00h MT29F128G08AKCAB 2Ch 88h 01h A7h A9h 00h 00h 00h MT29F128G08AMAAA 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F128G08AMCAB 2Ch 68h 00h 27h A9h 00h 00h 00h MT29F256G08AUAAA 2Ch 88h 01h A7h A9h 00h 00h 00h MT29F256G08AUCAB 2Ch 88h 01h A7h A9h 00h 00h 00h Note: 1. h = hexadecimal. Table 7: Read ID Parameters for Address 20h Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 All 4Fh 4Eh 46h 49h XXh Notes: 1. h = hexadecimal. 2. XXh = Undefined. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations READ PARAMETER PAGE (ECh) The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing ECh to the command register puts the target in read parameter page mode. The target stays in this mode until another valid command is issued. When the ECh command is followed by an 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. Use of the READ STATUS ENHANCED (78h) command is prohibited while the target is busy and during data output. After tR completes, the host enables data output mode to read the parameter page. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one data byte is output for each rising or falling edge of DQS. A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. If desired, the CHANGE READ COLUMN (05h-E0h) command can be used to change the location of data output. Use of the CHANGE READ COLUMN ENHANCED (06h-E0h) command is prohibited. The READ PARAMETER PAGE (ECh) output data can be used by the host to configure its internal settings to properly use the NAND Flash device. Parameter page data is static per part, however the value can be changed through the product cycle of NAND Flash. The host should interpret the data and configure itself accordingly. Figure 46: READ PARAMETER (ECh) Operation Cycle type DQ[7:0] Command Address DOUT DOUT DOUT DOUT DOUT DOUT ECh 00h P00 P10 … P01 P11 … tWB tR tRR R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Parameter Page Data Structure Tables Table 8: Parameter Page Data Structure Byte Description Device Values Revision information and features block 0–3 Parameter page signature Byte 0: 4Fh, “O” Byte 1: 4Eh, “N” Byte 2: 46h, “F” Byte 3: 49h, “I” – 4Fh, 4Eh, 46h, 49h 4–5 Revision number Bit[15:5]: Reserved (0) Bit 4: 1 = supports ONFI version 2.2 Bit 3: 1 = supports ONFI verion 2.1 Bit 2: 1 = supports ONFI version 2.0 Bit 1: 1 = supports ONFI version 1.0 Bit 0: Reserved (0) – 1Eh, 00h 6–7 Features supported Bit[15:9]: Reserved (0) Bit 8: 1 = supports program page register clear enhancement Bit 7: 1 = supports extended parameter page Bit 6: 1 = supports interleaved (multi-plane) read operations Bit 5: 1 = supports synchronous interface Bit 4: 1 = supports odd-to-even page copyback Bit 3: 1 = supports interleaved (multi-plane) program and erase operations Bit 2: 1 = supports non-sequential page programming Bit 1: 1 = supports multiple LUN operations Bit 0: 1 = supports 16-bit data bus width MT29F32G08ABAAA 58h, 01h 8–9 MT29F64G08AFAAA MT29F128G08AMAAA MT29F128G08AJAAA 5Ah, 01h MT29F128G08AKAAA MT29F256G08AUAAA MT29F32G08ABCAB 78h, 01h MT29F64G08AECAB MT29F128G08AMCAB MT29F128G08AKCAB 7Ah, 01h MT29F256G08AUCAB Optional commands supported Bit[15:10]: Reserved (0) Bit 9: 1 = supports Reset LUN command Bit 8: 1 = supports small data move Bit 7: 1 = supports CHANGE ROW ADDRESS Bit 6: 1 = supports CHANGE READ COLUMN ENHANCED Bit 5: 1 = supports READ UNIQUE ID Bit 4: 1 = supports COPYBACK Bit 3: 1 = supports READ STATUS ENHANCED Bit 2: 1 = supports GET FEATURES and SET FEATURES Bit 1: 1 = supports read cache commands Bit 0: 1 = supports PROGRAM PAGE CACHE – FFh, 03h 10–11 Reserved (0) – All 00h 12–13 Reserved (0) – All 00h Number of parameter pages – 03h Reserved (0) – All 00h 14 15–31 Manufacturer information block PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte Description 32–43 Device manufacturer (12 ASCII characters) Micron 44–63 Device model (20 ASCII characters) 44–63 Device model (20 ASCII characters) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 63 Device Values – 4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h, 20h, 20h MT29F32G08ABAAAWP 4Dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 41h, 42h, 41h, 41h, 41h, 57h, 50h, 20h, 20h, 20h MT29F64G08AFAAAWP 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 46h, 41h, 41h, 41h, 57h, 50h, 20h, 20h, 20h MT29F128G08AJAAAWP 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Ah, 41h, 41h, 41h, 57h, 50h, 20h, 20h MT29F128G08AKAAAC5 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Bh, 41h, 41h, 41h, 43h, 35h, 20h, 20h MT29F128G08AMAAAC5 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Dh, 41h, 41h, 41h, 43h, 35h, 20h, 20h MT29F256G08AUAAAC5 4Dh, 54h, 32h, 39h, 46h, 32h, 35h, 36h, 47h, 30h, 38h, 41h, 55h, 41h, 41h, 41h, 43h, 35h, 20h, 20h MT29F32G08ABCABH1 4Dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 41h, 42h, 43h, 41h, 42h, 48h, 31h, 20h, 20h, 20h Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte Description 44–63 Device model (20 ASCII characters) 44–63 64 Device model (20 ASCII characters) Device Values MT29F64G08AECABH1 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 45h, 43h, 41h, 42h, 48h, 31h, 20h, 20h, 20h MT29F128G08AKCABH2 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Bh, 43h, 41h, 42h, 48h, 32h, 20h, 20h MT29F128G08AMCABH2 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Dh, 43h, 41h, 42h, 48h, 32h, 20h, 20h MT29F256G08AUCABH3 4Dh, 54h, 32h, 39h, 46h, 32h, 35h, 36h, 47h, 30h, 38h, 41h, 55h, 43h, 41h, 42h, 48h, 33h, 20h, 20h MT29F64G08AECABJ1 4Dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 41h, 45h, 43h, 41h, 42h, 4Ah, 31h, 20h, 20h, 20h MT29F128G08AMCABJ2 4Dh, 54h, 32h, 39h, 46h, 31h, 32h, 38h, 47h, 30h, 38h, 41h, 4Dh, 43h, 41h, 42h, 4Ah, 32h, 20h, 20h MT29F256G08AUCABJ3 4Dh, 54h, 32h, 39h, 46h, 32h, 35h, 36h, 47h, 30h, 38h, 41h, 55h, 43h, 41h, 42h, 4Ah, 33h, 20h, 20h JEDEC manufacturer ID – 2Ch 65–66 Date code – 00h, 00h 67–79 Reserved (0) – All 00h Memory organization block 80–83 Number of data bytes per page – 00h, 20h, 00h, 00h 84–85 Number of spare bytes per page – C0h, 01h 86–91 Reserved (0) – All 00h 92–95 Number of pages per block – 80h, 00h, 00h, 00h 96–99 Number of blocks per LUN – 00h, 10h, 00h, 00h PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte 100 Description Number of LUNs per chip enable Device Values MT29F32G08ABAAA 01h MT29F32G08ABCAB MT29F64G08AECAB MT29F64G08AFAAA MT29F128G08AMAAA MT29F128G08AMCAB MT29F128G08AJAAA 02h MT29F128G08AKAAA MT29F128G08AKCAB MT29F256G08AUAAA MT29F256G08AUCAB 101 Number of address cycles Bit[7:4]: Column address cycles Bit[3:0]: Row address cycles – 23h 102 Number of bits per cell – 01h 103–104 Bad blocks maximum per LUN – 50h, 00h 105–106 Block endurance – 06h, 04h 107 Guaranteed valid blocks at beginning of target – 01h Block endurance for guaranteed valid blocks – 00h, 00h 110 Number of programs per page – 04h 111 Reserved (0) – 00h 112 Number of bits ECC correctability – 08h 113 Number of interleaved address bits Bit[7:4]: Reserved (0) Bit[3:0]: Number of interleaved address bits – 01h 114 Interleaved operation attributes Bit[7:6]: Reserved (0) Bit 5: Reserved Bit 4: 1 = supports read cache Bit 3: Address restrictions for cache operations Bit 2: 1 = supports program cache Bit 1: 1 = no block address restrictions Bit 0: Overlapped/concurrent interleaving support – 1Eh Reserved (0) – All 00h 108–109 115–127 Electrical parameters block 128 I/O pin capacitance per chip enable PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte Device Values Timing mode support Bit[15:6]: Reserved (0) Bit 5: 1 = supports timing mode 5 Bit 4: 1 = supports timing mode 4 Bit 3: 1 = supports timing mode 3 Bit 2: 1 = supports timing mode 2 Bit 1: 1 = supports timing mode 1 Bit 0: 1 = supports timing mode 0, shall be 1 – 3Fh, 00h 131–132 Reserved (0) – All 00h 133–134 tPROG – 30h, 02h – 58h, 1Bh – 23h, 00h – C8h, 00h MT29F32G08ABAAAWP 00h, 00h 129–130 Description Maximum PROGRAM PAGE time (µs) 135–136 tBERS 137–138 tR 139–140 tCCS 141–142 Source synchronous timing mode support Bit[15:6]: Reserved (0) Bit 5: 1 = supports timing mode 5 Bit 4: 1 = supports timing mode 4 Bit 3: 1 = supports timing mode 3 Bit 2: 1 = supports timing mode 2 Bit 1: 1 = supports timing mode 1 Bit 0: 1 = supports timing mode 0 Maximum BLOCK ERASE time (µs) Maximum PAGE READ time (µs) Minimum change column setup time (ns) MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 3Fh, 00h MT29F64G08AECABH1 MT29F128G08AKCABH2 MT29F128G08AMCABH2 MT29F256G08AUCABH3 MT29F64G08AECABJ1 MT29F128G08AMCABJ2 MT29F256G08AUCABJ3 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte 143 Description Source synchronous features Bit[7:3]: Reserved (0) Bit 2: 1 = devices support CLK stopped for data input Bit 1: 1 = typical capacitance values present Bit 0: 0 = use tCAD MIN value Device Values MT29F32G08ABAAAWP 00h MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 02h MT29F64G08AECABH1 MT29F128G08AKCABH2 MT29F128G08AMCABH2 MT29F256G08AUCABH3 MT29F64G08AECABJ1 MT29F128G08AMCABJ2 MT29F256G08AUCABJ3 144–145 CLK input pin capacitance, typical MT29F32G08ABAAAWP 00h, 00h MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 28h, 00h MT29F64G08AECABH1 MT29F128G08AKCABH2 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 67 3Eh, 00h MT29F128G08AMCABH2 1Fh, 00h MT29F256G08AUCABH3 35h, 00h MT29F64G08AECABJ1 2Dh, 00h MT29F128G08AMCABJ2 23h, 00h MT29F256G08AUCABJ3 3Ch, 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte 146–147 Description I/O pin capacitance, typical Device Values MT29F32G08ABAAAWP 00h, 00h MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 2Dh, 00h MT29F64G08AECABH1 148–149 Input capacitance, typical MT29F128G08AKCABH2 50h, 00h MT29F128G08AMCABH2 28h, 00h MT29F256G08AUCABH3 49h, 00h MT29F64G08AECABJ1 31h, 00h MT29F128G08AMCABJ2 28h, 00h MT29F256G08AUCABJ3 46h, 00h MT29F32G08ABAAAWP 00h, 00h MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 28h, 00h MT29F64G08AECABH1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 68 MT29F128G08AKCABH2 44h, 00h MT29F128G08AMCABH2 22h, 00h MT29F256G08AUCABH3 35h, 00h MT29F64G08AECABJ1 2Ch, 00h MT29F128G08AMCABJ2 22h, 00h MT29F256G08AUCABJ3 3Bh, 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte 150 Description Input pin capacitance, maximum Device Values MT29F32G08ABAAAWP 0Ah MT29F64G08AFAAAWP 07h MT29F128G08AJAAAWP 09h MT29F128G08AKAAAC5 0Ah MT29F128G08AMAAAC5 05h MT29F256G08AUAAAC5 07h MT29F32G08ABCABH1 05h MT29F64G08AECABH1 151 Driver strength support Bit[7:3]: Reserved (0) Bit 2: 1 = Supports overdrive (2 drive strength) Bit 1: 1 = Supports overdrive (1 drive strength) Bit 0: 1 = Supports driver strength settings 152–153 tR 154-155 tADL 156–163 Reserved (0) maximum interleaved (multi-plane) page read time (µs) program page register clear enhancement value (ns) MT29F128G08AKCABH2 08h MT29F128G08AMCABH2 04h MT29F256G08AUCABH3 07h MT29F64G08AECABJ1 06h MT29F128G08AMCABJ2 05h MT29F256G08AUCABJ3 07h – 07h – 23h, 00h – 6Eh, 00h – All 00h Vendor block 164–165 Vendor-specific revision number – 01h, 00h 166 TWO-PLANE PAGE READ support Bit[7:1]: Reserved (0) Bit 0: 1 = Support for TWO-PLANE PAGE READ – 01h 167 Read cache support Bit[7:1]: Reserved (0) Bit 0: 0 = Does not support Micron-specific read cache function – 00h 168 READ UNIQUE ID support Bit[7:1]: Reserved (0) Bit 0: 0 = Does not support Micron-specific READ UNIQUE ID – 00h 169 Programmable DQ output impedance support Bit[7:1]: Reserved (0) Bit 0: 0 = No support for programmable DQ output impedance by B8h command – 00h PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte Device Values 170 Number of programmable DQ output impedance settings Bit[7:3]: Reserved (0) Bit [2:0] = Number of programmable DQ output impedance settings – 04h 171 Programmable DQ output impedance feature address Bit[7:0] = Programmable DQ output impedance feature address – 10h 172 Programmable R/B# pull-down strength support Bit[7:1]: Reserved (0) Bit 0: 1 = Support programmable R/B# pull-down strength – 01h 173 Programmable R/B# pull-down strength feature address Bit[7:0] = Feature address used with programmable R/B# pull-down strength – 81h 174 Number of programmable R/B# pull-down strength settings Bit[7:3]: Reserved (0) Bit[2:0] = Number of programmable R/B# pull-down strength settings – 04h 175 OTP mode support Bit[7:2]: Reserved (0) Bit 1: 1 = Supports Get/Set Features command set Bit 0: 0 = Does not support A5h/A0h/AFh OTP command set – 02h 176 OTP page start Bit[7:0] = Page where OTP page space begins – 02h 177 OTP DATA PROTECT address Bit[7:0] = Page address to use when issuing OTP DATA PROTECT command – 01h 178 Number of OTP pages Bit[15:5]: Reserved (0) Bit[4:0] = Number of OTP pages – 1Eh 179 OTP Feature Address – 90h Reserved (0) – All 00h 180–252 Description PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations Table 8: Parameter Page Data Structure (Continued) Byte 253 Description Parameter page revision Device Values MT29F32G08ABAAAWP 04h MT29F64G08AFAAAWP MT29F128G08AJAAAWP MT29F128G08AKAAAC5 MT29F128G08AMAAAC5 MT29F256G08AUAAAC5 MT29F32G08ABCABH1 MT29F64G08AECABH1 MT29F128G08AKCABH2 MT29F128G08AMCABH2 MT29F256G08AUCABH3 MT29F64G08AECABJ1 02h MT29F128G08AMCABJ2 MT29F256G08AUCABJ3 254–255 Integrity CRC MT29F32G08ABAAAWP 1Fh, A6h MT29F64G08AFAAAWP 1Dh, 32h MT29F128G08AJAAAWP C8h, DFh MT29F128G08AKAAAC5 89h, 05h MT29F128G08AMAAAC5 27h, 00h MT29F256G08AUAAAC5 F0h, 5Dh MT29F32G08ABCABH1 92h, 8Ah MT29F64G08AECABH1 16h, 4Eh MT29F128G08AKCABH2 93h, BBh MT29F128G08AMCABH2 3Dh, FCh MT29F256G08AUCABH3 7Eh, 89h MT29F64G08AECABJ1 99h, 5Ah MT29F128G08AMCABJ2 65h, EAh MT29F256G08AUCABJ3 A7h, 80h Redundant parameter pages 256–511 Value of bytes 0–255 – See bytes 0–255 512–767 Value of bytes 0–255 – See bytes 0–255 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Identification Operations READ UNIQUE ID (EDh) The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EDh to the command register puts the target in read unique ID mode. The target stays in this mode until another valid command is issued. When the EDh command is followed by a 00h address cycle, the target goes busy for tR. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. After tR completes, the host enables data output mode to read the unique ID. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, two data bytes are output, one byte for each rising or falling edge of DQS. Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16 bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In the event that a non-FFh result is returned, the host can repeat the XOR operation on a subsequent copy of the unique ID data. If desired, the CHANGE READ COLUMN (05hE0h) command can be used to change the data output location. Use of the CHANGE READ COLUMN ENHANCED (06h-E0h) command is prohibited. Figure 47: READ UNIQUE ID (EDh) Operation Cycle type DQ[7:0] Command Address EDh 00h tWB tR DOUT DOUT DOUT DOUT DOUT DOUT U00 U10 … U01 U11 … tRR R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Configuration Operations Configuration Operations The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the target's default power-on behavior. These commands use a one-byte feature address to determine which subfeature parameters will be read or modified. Each feature address (in the 00h to FFh range) is defined in Table 9. The SET FEATURES (EFh) command writes subfeature parameters (P1-P4) to the specified feature address. The GET FEATURES command reads the subfeature parameters (P1-P4) at the specified feature address. Unless otherwise specifed, the values of the feature addresses do not change when RESET (FFh, FCh) is issued by the host. Table 9: Feature Address Definitions Feature Address Definition 00h Reserved 01h Timing mode 02h–0Fh 10h 11h–7Fh Reserved Programmable output drive strength Reserved 80h Programmable output drive strength 81h Programmable RB# pull-down strength 82h–8Fh 90h 91h–FFh Reserved Array operation mode Reserved SET FEATURES (EFh) The SET FEATURES (EFh) command writes the subfeature parameters (P1-P4) to the specified feature address to enable or disable target-specific features. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EFh to the command register puts the target in the set features mode. The target stays in this mode until another command is issued. The EFh command is followed by a valid feature address as specified in Table 9. The host waits for tADL before the subfeature parameters are input. When the asynchronous interface is active, one subfeature parameter is latched per rising edge of WE#. When the synchronous interface is active, one subfeature parameter is latched per rising edge of DQS. The data on the falling edge of DQS should be identical to the subfeature parameter input on the previous rising edge of DQS. The device is not required to wait for the repeated data byte before beginning internal actions. After all four subfeature parameters are input, the target goes busy for tFEAT. The READ STATUS (70h) command can be used to monitor for command completion. Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to modify the interface type, the target will be busy for tITC. See Activating Interfaces (page 52) for details. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Configuration Operations Figure 48: SET FEATURES (EFh) Operation Cycle type Command Address DIN DIN DIN DIN P1 P2 P3 P4 tADL DQ[7:0] EFh FA tWB tFEAT R/B# GET FEATURES (EEh) The GET FEATURES (EEh) command reads the subfeature parameters (P1-P4) from the specified feature address. This command is accepted by the target only when all die (LUNs) on the target are idle. Writing EEh to the command register puts the target in get features mode. The target stays in this mode until another valid command is issued. When the EEh command is followed by a feature address, the target goes busy for tFEAT. If the READ STATUS (70h) command is used to monitor for command completion, the READ MODE (00h) command must be used to re-enable data output mode. During and prior to data output, use of the READ STATUS ENHANCED (78h) command is prohibited. After tFEAT completes, the host enables data output mode to read the subfeature parameters. When the asynchronous interface is active, one data byte is output per RE# toggle. When the synchronous interface is active, one subfeature parameter is output per DQS toggle on rising or falling edge of DQS. Figure 49: GET FEATURES (EEh) Operation Cycle type DQ[7:0] Command Address EEh FA tWB tFEAT DOUT DOUT DOUT DOUT P1 P2 P3 P4 tRR R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Configuration Operations Table 10: Feature Address 01h: Timing Mode Subfeature Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes Mode 0 (default) 0 0 0 0 x0h Mode 1 0 0 0 1 x1h Mode 2 0 0 1 0 x2h Mode 3 0 0 1 1 x3h Mode 4 0 1 0 0 x4h Mode 5 0 1 0 1 x5h P1 Timing mode Data interface Asynchronous (default) 0 0 0xh Synchronous DDR 0 1 1xh 1 x 2xh Reserved Program clear Program command clears all cache registers on a target (default) 0 0b Program command clears only addressed LUN cache register on a target 1 1b Reserved 0 1, 2 1 0b P2 Reserved 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h P3 Reserved P4 Reserved Notes: 1. Asynchronous timing mode 0 is the default, power-on value. 2. If the synchronous interface is active, a RESET (FFh) command will change the timing mode and data interface bits of feature address 01h to their default values. If the asynchronous interface is active, a RESET (FFh) command will not change the values of the timing mode or data interface bits to their default valued. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Configuration Operations Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength Subfeature Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes Overdrive 2 0 0 00h 1 Overdrive 1 0 1 01h Nominal (default) 1 0 02h Underdrive 1 1 03h P1 Output drive strength Reserved 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h DQ1 DQ0 Value Notes Full (default) 0 0 00h 1 Three-quarter 0 1 01h One-half 1 0 02h One-quarter 1 1 03h P2 Reserved P3 Reserved P4 Reserved Note: 1. See Output Drive Impedance section for details. Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength Subfeature Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 P1 R/B# pull-down strength Reserved 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h P2 Reserved P3 Reserved P4 Reserved Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength should be selected based on the expected loading of R/B#. Full strength is the default, power-on value. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Configuration Operations Table 13: Feature Addresses 90h: Array Operation Mode Subfeature Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Normal (default) 0 00h OTP Block 1 01h Notes P1 Array Operation Mode Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 0 0 0 0 0 0 0 0 00h 1 00h P2 Reserved P3 Reserved P4 Reserved Notes: 1. See One-Time Programmable (OTP) Operations for details. 2. A RESET (FFh) command will cause the bits of the array operation mode to change to their default values. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Status Operations Status Operations Each die (LUN) provides its status independently of other die (LUNs) on the same target through its 8-bit status register. After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued, status register output is enabled. The contents of the status register are returned on DQ[7:0] for each data output request. When the asynchronous interface is active and status register output is enabled, changes in the status register are seen on DQ[7:0] as long as CE# and RE# are LOW; it is not necessary to toggle RE# to see the status register update. When the synchronous interface is active and status register output is enabled, changes in the status register are seen on DQ[7:0] as long as CE# and W/R# are LOW and ALE and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH. While monitoring the status register to determine when a data transfer from the Flash array to the data register (tR) is complete, the host must issue the READ MODE (00h) command to disable the status register and enable data output (see READ MODE (00h) (page 88)). The READ STATUS (70h) command returns the status of the most recently selected die (LUN). To prevent data contention during or following an interleaved die (multi-LUN) operation, the host must enable only one die (LUN) for status output by using the READ STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations (page 113)). Table 14: Status Register Definition SR Bit Definition Independent per Plane1 7 WP# – Write Protect: 0 = Protected 1 = Not protected In the normal array mode, this bit indicates the value of the WP# signal. In OTP mode this bit is set to 0 if a PROGRAM OTP PAGE operation is attempted and the OTP area is protected. 6 RDY – Ready/Busy I/O: 0 = Busy 1 = Ready This bit indicates that the selected die (LUN) is not available to accept new commands, address, or data I/O cycles with the exception of RESET (FFh), SYNCHRONOUS RESET (FCh), READ STATUS (70h), and READ STATUS ENHANCED (78h). This bit applies only to the selected die (LUN). 5 ARDY – Ready/Busy Array: 0 = Busy 1 = Ready This bit goes LOW (busy) when an array operation is occurring on any plane of the selected die (LUN). It goes HIGH when all array operations on the selected die (LUN) finish. This bit applies only to the selected die (LUN). 4 – – Reserved (0) 3 – – Reserved (0) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Description 78 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Status Operations Table 14: Status Register Definition (Continued) SR Bit Definition Independent per Plane1 2 – – 1 FAILC Yes Pass/Fail (N–1): 0 = Pass 1 = Fail This bit is set if the previous operation on the selected die (LUN) failed. This bit is valid only when RDY (SR bit 6) is 1. It applies to PROGRAM-, and COPYBACK PROGRAM-series operations (80h-10h, 80h-15h, 85h-10h). This bit is not valid following an ERASE-series or READ-series operation. 0 FAIL Yes Pass/Fail (N): 0 = Pass 1 = Fail This bit is set if the most recently finished operation on the selected die (LUN) failed. This bit is valid only when ARDY (SR bit 5) is 1. It applies to PROGRAM-, ERASE-, and COPYBACK PROGRAM-series operations (80h-10h, 80h-15h, 60h-D0h, 85h-10h). This bit is not valid following a READ-series operation. Description Reserved (0) 1. After a multi-plane operation begins, the FAILC and FAIL bits are ORed together for the active planes when the READ STATUS (70h) command is issued. After the READ STATUS ENHANCED (78h) command is issued, the FAILC and FAIL bits reflect the status of the plane selected. Note: READ STATUS (70h) The READ STATUS (70h) command returns the status of the last-selected die (LUN) on a target. This command is accepted by the last-selected die (LUN) even when it is busy (RDY = 0). If there is only one die (LUN) per target, the READ STATUS (70h) command can be used to return status following any NAND command. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select the die (LUN) that should report status. In this situation, using the READ STATUS (70h) command will result in bus contention, as two or more die (LUNs) could respond until the next operation is issued. The READ STATUS (70h) command can be used following all single die (LUN) operations. If following a multi-plane operation, regardless of the number of LUNs per target, the READ STATUS (70h) command indicates an error occurred (FAIL = 1), use the READ STATUS ENHANCED (78h) command—once for each plane—to determine which plane operation failed. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Status Operations Figure 50: READ STATUS (70h) Operation Cycle type Command DOUT tWHR DQ[7:0] 70h SR READ STATUS ENHANCED (78h) The READ STATUS ENHANCED (78h) command returns the status of the addressed die (LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die (LUNs), even when they are BUSY (RDY = 0). Writing 78h to the command register, followed by three row address cycles containing the page, block, and LUN addresses, puts the selected die (LUN) into read status mode. The selected die (LUN) stays in this mode until another valid command is issued. Die (LUNs) that are not addressed are deselected to avoid bus contention. The selected LUN's status is returned when the host requests data output. The RDY and ARDY bits of the status register are shared for all of the planes of the selected die (LUN). The FAILC and FAIL bits are specific to the plane specified in the row address. The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for data output. To begin data output following a READ-series operation after the selected die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data output. If the host needs to change the cache register that will output data, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command after the die (LUN) is ready (see CHANGE READ COLUMN ENHANCED (06h-E0h)). Use of the READ STATUS ENHANCED (78h) command is prohibited during the poweron RESET (FFh) command and when OTP mode is enabled. It is also prohibited following some of the other reset, identification, and configuration operations. See individual operations for specific details. Figure 51: READ STATUS ENHANCED (78h) Operation Cycle type Command Address Address Address Dout tWHR DQx PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 78h R1 R2 80 R3 SR Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Column Address Operations Column Address Operations The column address operations affect how data is input to and output from the cache registers within the selected die (LUNs). These features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data bytes or words in the cache register. When the asynchronous interface is active, column address operations can address any byte in the selected cache register. When the synchronous interface is active, column address operations are aligned to word boundaries (CA0 is forced to 0), because as data is transferred on DQ[7:0] in twobyte units. CHANGE READ COLUMN (05h-E0h) The CHANGE READ COLUMN (05h-E0h) command changes the column address of the selected cache register and enables data output from the last selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during CACHE READ operations (RDY = 1; ARDY = 0). Writing 05h to the command register, followed by two column address cycles containing the column address, followed by the E0h command, puts the selected die (LUN) into data output mode. After the E0h command cycle is issued, the host must wait at least tCCS before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be issued prior to issuing the CHANGE READ COLUMN (05h-E0h). In this situation, using the CHANGE READ COLUMN (05h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention, as two or more die (LUNs) could output data. Figure 52: CHANGE READ COLUMN (05h-E0h) Operation Cycle type DOUT DOUT Command Address Address Command tRHW DQ[7:0] Dn Dn + 1 DOUT DOUT DOUT Dk Dk + 1 Dk + 2 tCCS 05h C1 C2 E0h SR[6] PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE READ COLUMN ENHANCED (06h-E0h) The CHANGE READ COLUMN ENHANCED (06h-E0h) command enables data output on the addressed die’s (LUN’s) cache register at the specified column address. This command is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1). Writing 06h to the command register, followed by two column address cycles and three row address cycles, followed by E0h, enables data output mode on the address LUN’s cache register at the specified column address. After the E0h command cycle is issued, the host must wait at least tCCS before requesting data output. The selected die (LUN) stays in data output mode until another valid command is issued. Following a multi-plane read page operation, the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select the cache register to be enabled for data output. After data output is complete on the selected plane, the command can be issued again to begin data output on another plane. In devices with more than one die (LUN) per target, after all of the die (LUNs) on the target are ready (RDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used following an interleaved die (multi-LUN) read operation. Die (LUNs) that are not addressed are deselected to avoid bus contention. In devices with more than one die (LUN) per target, during interleaved die (multi-LUN) operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to the die (LUN) to be selected prior to issuing the CHANGE READ COLUMN ENHANCED (06h-E0h). In this situation, using the CHANGE READ COLUMN ENHANCED (06h-E0h) command without the READ STATUS ENHANCED (78h) command will result in bus contention, as two or more die (LUNs) could output data. If there is a need to update the column address without selecting a new cache register or LUN, the CHANGE READ COLUMN (05h-E0h) command can be used instead. Figure 53: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation Cycle type DQ[7:0] Dout Dout Command Address Address Address Address Address Command Dn Dn + 1 Dout Dout Dout Dk Dk + 1 Dk + 2 tCCS tRHW 06h PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN C1 C2 R1 R2 82 R3 E0h Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE WRITE COLUMN (85h) The CHANGE WRITE COLUMN (85h) command changes the column address of the selected cache register and enables data input on the last-selected die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache program operations (RDY = 1; ARDY = 0). Writing 85h to the command register, followed by two column address cycles containing the column address, puts the selected die (LUN) into data input mode. After the second address cycle is issued, the host must wait at least tCCS before inputting data. The selected die (LUN) stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The CHANGE WRITE COLUMN (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). In devices that have more than one die (LUN) per target, the CHANGE WRITE COLUMN (85h) command can be used with other commands that support interleaved die (multiLUN) operations. Figure 54: CHANGE WRITE COLUMN (85h) Operation As defined for PAGE (CACHE) PROGRAM Cycle type DIN DIN As defined for PAGE (CACHE) PROGRAM Command Address Address DIN DIN DIN Dk Dk + 1 Dk + 2 tCCS DQ[7:0] Dn Dn + 1 85h C1 C2 RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Column Address Operations CHANGE ROW ADDRESS (85h) The CHANGE ROW ADDRESS (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and enables data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache programming operations (RDY = 1; ARDY = 0). Write 85h to the command register. Then write two column address cycles and three row address cycles. This updates the page and block destination of the selected plane for the addressed LUN and puts the cache register into data input mode. After the fifth address cycle is issued the host must wait at least tCCS before inputting data. The selected LUN stays in data input mode until another valid command is issued. Though data input mode is enabled, data input from the host is optional. Data input begins at the column address specified. The CHANGE ROW ADDRESS (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). When used with these commands, the LUN address and plane select bits are required to be identical to the LUN address and plane select bits originally specified. The CHANGE ROW ADDRESS (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page and block address. In devices that have more than one die (LUN) per target, the CHANGE ROW ADDRESS (85h) command can be used with other commands that support interleaved die (multiLUN) operations. The CHANGE ROW ADDRESS (85h) command can be used with the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) commands to read and modify cache register contents in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller. To modify the cache register contents in small sections, first issue a PAGE READ (00h-30h) or COPYBACK READ (00h-35h) operation. When data output is enabled, the host can output a portion of the cache register contents. To modify the cache register contents, issue the 85h command, the column and row addresses, and input the new data. The host can re-enable data output by issuing the 11h command, waiting tDBSY, and then issuing the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) command. It is possible toggle between data output and data input multiple times. After the final CHANGE ROW ADDRESS (85h) operation is complete, issue the 10h command to program the cache register to the NAND Flash array. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Column Address Operations Figure 55: CHANGE ROW ADDRESS (85h) Operation As defined for PAGE (CACHE) PROGRAM Cycle type DIN DIN As defined for PAGE (CACHE) PROGRAM Command Address Address Address Address Address DIN DIN DIN Dk Dk + 1 Dk + 2 tCCS DQ[7:0] Dn Dn + 1 85h C1 C2 R1 R2 R3 RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations Read Operations Read operations are used to copy data from the NAND Flash array of one or more of the planes to their respective cache registers and to enable data output from the cache registers to the host through the DQ bus. Read Operations The READ PAGE (00h-30h) command, when issued by itself, reads one page from the NAND Flash array to its cache register and enables data output for that cache register. During data output the following commands can be used to read and modify the data in the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). Read Cache Operations To increase data throughput, the READ PAGE CACHE-series (31h, 00h-31h) commands can be used to output data from the cache register while concurrently copying a page from the NAND Flash array to the data register. To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: • READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the NAND Flash array to the data register • READ PAGE CACHE RANDOM (00h-31h)—copies the page specified in this command from the NAND Flash array (any plane) to its corresponding data register After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next page begins copying data from the array to the data register. After tRCBSY, R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data output by the die (LUN). After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued. If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready. Data can then be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output. For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE-series (31h, 00h-31h) operations are status operatRCBSY, PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations tions (70h, 78h), READ MODE (00h), READ PAGE CACHE-series (31h, 00h-31h), CHANGE READ COLUMN (05h-E0h), and RESET (FFh, FCh). Multi-Plane Read Operations Multi-plane read page operations improve data throughput by copying data from more than one plane simultaneously to the specified cache registers. This is done by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the READ PAGE (00h-30h) command. When the die (LUN) is ready, the CHANGE READ COLUMN ENHANCED (06h-E0h) command determines which plane outputs data. During data output, the following commands can be used to read and modify the data in the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). See Multi-Plane Operations for details. Multi-Plane Read Cache Operations Multi-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the NAND Flash array to the data register. This is done by prepending READ PAGE MULTI-PLANE (00h-32h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command. To begin a multi-plane read page cache sequence, begin by issuing a MULTI-PLANE READ PAGE operation using the READ PAGE MULTI-PLANE (00h-32h) and READ PAGE (00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands: • READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the previously addressed planes from the NAND Flash array to the data registers. • READ PAGE MULTI-PLANE (00h-32h) commands, if desired, followed by the READ PAGE CACHE RANDOM (00h-31h) command—copies the pages specified from the NAND Flash array to the corresponding data registers. After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the next pages begin copying data from the array to the data registers. After tRCBSY, R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pages requested in the READ PAGE CACHE operation are transferred to the data registers. Issue the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which cache register will output data. After data is output, the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the CHANGE READ COLUMN (05hE0h) command can be used to change the column address of the data output. After outputting data from the cache registers, either an additional MULTI-PLANE READ CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE LAST (3Fh) command can be issued. If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are copied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1, indicating that the cache registers are available and that the die (LUN) is ready. Issue the PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which cache register will output data. After data is output, the CHANGE READ COLUMN ENHANCED (06h-E0h) command can be used to output data from other cache registers. After a cache register has been selected, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data output. For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during READ PAGE CACHE-series (31h, 00h-31h) operations are status operations (70h, 78h), READ MODE (00h), multi-plane read cache-series (31h, 00h-32h, 00h-31h), CHANGE READ COLUMN (05h-E0h, 06h-E0h), and RESET (FFh, FCh). tRCBSY, See Multi-Plane Operations for additional multi-plane addressing requirements. READ MODE (00h) The READ MODE (00h) command disables status output and enables data output for the last-selected die (LUN) and cache register after a READ operation (00h-30h, 00h-35h) has been monitored with a status operation (70h, 78h). This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 3Fh, 00h-31h) operations (RDY = 1 and ARDY = 0). In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to issuing the READ MODE (00h) command. This prevents bus contention. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 88 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations READ PAGE (00h-30h) The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its respective cache register and enables data output. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To read a page from the NAND Flash array, write the 00h command to the command register, the write five address cycles to the address registers, and conclude with the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. If the status operations are used to monitor the LUN's status, when the die (LUN) is ready (RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, output begins at the column address specified. During data output the CHANGE READ COLUMN (05h-E0h) command can be issued. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) prior to the issue of the READ MODE (00h) command. This prevents bus contention. The READ PAGE (00h-30h) command is used as the final command of a multi-plane read operation. It is preceded by one or more READ PAGE MULTI-PLANE (00h-32h) commands. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the last even plane addressed. When the host requests data output, output begins at the column address last specified in the READ PAGE (00h-30h) command. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to enable data output in the other cache registers. See Multi-Plane Operations for additional multi-plane addressing requirements. Figure 56: READ PAGE (00h-30h) Operation Cycle type DQ[7:0] Command Address Address Address Address Address Command DOUT DOUT DOUT 00h C1 C2 R1 R2 R3 30h Dn Dn+1 Dn+2 tWB tR tRR RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE SEQUENTIAL (31h) The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page within a block into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the last page of a block is read into the data register, the next page read will be the next logical block in the plane which the 31h command was issued. Do not issue the READ PAGE CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE CACHE LAST (3Fh) command. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after a MULTIPLANE READ PAGE operation (00h-32h, 00h-30h), the next sequential pages are read into the data registers while the previous pages can be output from the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. Figure 57: READ PAGE CACHE SEQUENTIAL (31h) Operation Cycle type Command DQ[7:0] 00h Address x5 Command Page Address M 30h tWB Command 31h tR tWB DOUT DOUT DOUT Command D0 … Dn 31h tRCBSY tRR tWB DOUT D0 tRCBSY tRR RDY Page M PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 90 Page M+1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE RANDOM (00h-31h) The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and page into the data register while the previous page is output from the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue this command, write 00h to the command register, then write five address cycles to the address register, and conclude by writing 31h to the command register. The column address in the address specified is ignored. The die (LUN) address must match the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applicable, the previous READ PAGE CACHE RANDOM (00h-31h) command. There is no restriction on the plane address. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. If a MULTI-PLANE CACHE RANDOM (00h-32h, 00h-31h) command is issued after a MULTI-PLANE READ PAGE operation (00h-32h, 00h-30h), then the addressed pages are read into the data registers while the previous pages can be output from the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations Figure 58: READ PAGE CACHE RANDOM (00h-31h) Operation Cycle type Command DQ[7:0] 00h Address x5 Command Page Address M 30h tWB Command Address x5 Command 00h Page Address N 31h tWB tR DOUT DOUT DOUT Command D0 … Dn 00h tRCBSY tRR RDY Page M 1 Cycle type DQ[7:0] DOUT Command Address x5 Command Dn 00h Page Address P 31h tWB DOUT D0 tRCBSY tRR RDY Page N 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations READ PAGE CACHE LAST (3Fh) The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and copies a page from the data register to the cache register. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0). To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, beginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address of the data being output from the cache register. In devices that have more than one LUN per target, during and following interleaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by the READ MODE (00h) command must be used to select only one die (LUN) and prevent bus contention. If the READ PAGE CACHE LAST (3Fh) command is issued after a MULTI-PLANE READ PAGE CACHE operation (31h; 00h-32h, 00h-30h), the die (LUN) goes busy until the pages are copied from the data registers to the cache registers. After the die (LUN) is ready (RDY = 1, ARDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to select which cache register outputs data. Figure 59: READ PAGE CACHE LAST (3Fh) Operation As defined for READ PAGE CACHE (SEQUENTIAL OR RANDOM) Cycle type DQ[7:0] Command DOUT DOUT DOUT Command DOUT DOUT DOUT 31h D0 … Dn 3Fh D0 … Dn tWB tRCBSY tRR tWB tRCBSY tRR RDY Page Address N PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Page N 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations READ PAGE MULTI-PLANE (00h-32h) The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data from the NAND flash array to its cache register. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for data transfer. The READ PAGE (00h-30h) command is issued to select the final plane and to begin the read operation for all previously queued planes. All queued planes will transfer data from the NAND Flash array to their cache registers. To issue the READ PAGE MULTI-PLANE (00h-32h) command, write 00h to the command register, then write five address cycles to the address register, and conclude by writing 32h to the command register. The column address in the address specified is ignored. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tDBSY. After tDBSY, R/B# goes HIGH and the die (LUN) is ready (RDY = 1, ARDY = 1). At this point, the die (LUN) and block are queued for data transfer from the array to the cache register for the addressed plane. During tDBSY, the only valid commands are status operations (70h, 78h) and reset commands (FFh, FCh). Following tDBSY, to continue the MULTI-PLANE READ operation, the only valid commands are status operations (70h, 78h), READ PAGE MULTI-PLANE (00h-32h), READ PAGE (00h-30h), and READ PAGE CACHE RANDOM (00h-31h). Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue additional planes for data transfer. If the READ PAGE (00h-30h) command is used as the final command of a MULTIPLANE READ operation, data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the last even plane addressed. When the host requests data output, it begins at the column address specified in the READ PAGE (00h-30h) command. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. If the READ PAGE CACHE SEQUENTIAL (31h) is used as the final command of a MULTI-PLANE READ CACHE operation, data is copied from the previously read operation from each plane to each cache register and then data is transferred from the NAND Flash array for all previously addressed planes to their respective data registers. When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to determine which cache register outputs data first. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. If the READ PAGE CACHE RANDOM (00h-31h) command is used as the final command of a MULTI-PLANE READ CACHE operation, data is copied from the previously read operation from the data register to the cache register and then data is transferred from the NAND Flash array for all of the addressed planes to their respective data registers. When the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to determine which cache register outputs data first. To enable data output in the other cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Read Operations COLUMN (05h-E0h) command can be used to change the column address within the currently selected plane. See Multi-Plane Operations for additional multi-plane addressing requirements. Figure 60: READ PAGE MULTI-PLANE (00h-32h) Operation Cycle type DQ[7:0] Command Address Address Address Address Address Command Command Address Address 00h C1 C2 R1 R2 R3 32h 00h C1 ... tWB tDBSY RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations Program Operations Program operations are used to move data from the cache or data registers to the NAND array of one or more planes. During a program operation the contents of the cache and/or data registers are modified by the internal control logic. Within a block, pages must be programmed sequentially from the least significant page address to the most significant page address (i.e. 0, 1, 2, 3, …). Programming pages out of order within a block is prohibited. Program Operations The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE MULTI-PLANE (80h-11h) command, programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. Program Cache Operations The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy (RDY = 0, ARDY = 0) while the cache register contents are copied to the data register, and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0). While the contents of the data register are moved to the NAND Flash array, the cache register is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) command. For PROGRAM PAGE CACHE-series (80h-15h) operations, during the die (LUN) busy times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are status operations (70h, 78h) and reset (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid commands during PROGRAM PAGE CACHE-series (80h-15h) operations are status operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), CHANGE WRITE COLUMN (85h), CHANGE ROW ADDRESS (85h), and reset (FFh, FCh). Multi-Plane Program Operations The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve program operation system performance by enabling multiple pages to be moved from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE (80h-10h) command. See Multi-Plane Operations for details. Multi-Plane Program Cache Operations The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve program cache operation system performance by enabling multiple pages to be moved from the cache registers to the data registers and, while the pages are being transferred from the data registers to different planes of the NAND Flash array, free the cache registers to receive data input from the host. This is done by prepending one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE CACHE (80h-15h) command. See Multi-Plane Operations for details. PROGRAM PAGE (80h-10h) The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page address in the array of the selected die (LUN). This command is accepted by the die (LUN) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register and move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write five address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands may be issued. When data input is complete, write 10h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tPROG as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) may be used. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE (80h-10h) command is used as the final command of a multiplane program operation. It is preceded by one or more PROGRAM PAGE MULTIPLANE (80h-11h) commands. Data is transferred from the cache registers for all of the addressed planes to the NAND array. The host should check the status of the operation by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements. Figure 61: PROGRAM PAGE (80h-10h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN DIN Command D0 D1 … Dn 10h Command DOUT 70h Status tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tPROG RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations PROGRAM PAGE CACHE (80h-15h) The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a cache register; copies the data from the cache register to the data register; then moves the data register contents to the specified block and page address in the array of the selected die (LUN). After the data is copied to the data register, the cache register is available for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h) commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die (LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0). To input a page to the cache register to move it to the NAND array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Then write five address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands may be issued. When data input is complete, write 15h to the command register. The selected LUN will go busy (RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data register, and then to begin moving the data register contents to the specified page and block address. To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN’s status shows that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check the status of the FAILC bit to see if a previous cache operation was successful. If, after tCBSY, the host wants to wait for the program cache operation to complete, without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY until it is 1. The host should then check the status of the FAIL and FAILC bits. In devices with more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a multi-plane program cache operation. It is preceded by one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations Figure 62: PROGRAM PAGE CACHE (80h–15h) Operation (Start) Cycle type Command Address Address Address Address Address Din Din Din Din Command D0 D1 … Dn 15h tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Cycle type Command Address Address Address Address Address Din Din Din Din Command D0 D1 … Dn 15h tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Figure 63: PROGRAM PAGE CACHE (80h–15h) Operation (End) As defined for PAGE CACHE PROGRAM Cycle type Command Address Address Address Address Address Din Din Din Din Command D0 D1 … Dn 15h tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tCBSY RDY 1 Cycle type Command Address Address Address Address Address Din Din Din Din Command D0 D1 … Dn 10h tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tLPROG RDY 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations PROGRAM PAGE MULTI-PLANE (80h-11h) The PROGRAM PAGE MULTI-PLANE (80h-11h) command enables the host to input data to the addressed plane's cache register and queue the cache register to ultimately be moved to the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified that plane is also queued for data transfer. To input data for the final plane and to begin the program operation for all previously queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1). To input a page to the cache register and queue it to be moved to the NAND Flash array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by an 11h command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Write five address cycles containing the column address and row address; data input cycles follow. Serial data is input beginning at the column address specified. At any time during the data input cycle, the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS (85h) commands can be issued. When data input is complete, write 11h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal or, alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1), additional PROGRAM PAGE MULTI-PLANE (80h-11h) commands can be issued to queue additional planes for data transfer. Alternatively, the PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be issued. When the PROGRAM PAGE (80h-10h) command is used as the final command of a multi-plane program operation, data is transferred from the cache registers to the NAND Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the planes to verify that programming completed successfully. When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a MULTI-PLANE PROGRAM CACHE operation, data is transferred from the cache registers to the data registers after the previous array operations finish. The data is then moved from the data registers to the NAND Flash array for all of the addressed planes. This occurs during tCBSY. After tCBSY, the host should check the status of the FAILC bit for each of the planes from the previous program cache operation, if any, to verify that programming completed successfully. For the PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and PROGRAM PAGE CACHE (80h-15h) commands, see Multi-Plane Operations for multiplane addressing requirements. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Program Operations Figure 64: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN Command Command Address D0 … Dn 11h 80h ... tADL DQ[7:0] 80h C1 C2 R1 R2 R3 tWB tDBSY RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Erase Operations Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK MULTI-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. MULTI-PLANE ERASE Operations The ERASE BLOCK MULTI-PLANE (60h-D1h) command can be used to further system performance of erase operations by allowing more than one block to be erased in the NAND array. This is done by prepending one or more ERASE BLOCK MULTI-PLANE (60h-D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See MultiPlane Operations for details. ERASE BLOCK (60h-D0h) The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To erase a block, write 60h to the command register. Then write three address cycles containing the row address; the page address is ignored. Conclude by writing D0h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS while the block is erased. To determine the progress of an ERASE operation, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die (LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit. In devices that have more than one die (LUN) per target, during and following interleaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be used to select only one die (LUN) for status output. Use of the READ STATUS (70h) command could cause more than one die (LUN) to respond, resulting in bus contention. The ERASE BLOCK (60h-D0h) command is used as the final command of a MULTIPLANE ERASE operation. It is preceded by one or more ERASE BLOCK MULTI-PLANE (60h-D1h) commands. All of blocks in the addressed planes are erased. The host should check the status of the operation by using the status operations (70h, 78h). See MultiPlane Operations for multi-plane addressing requirements. Figure 65: ERASE BLOCK (60h-D0h) Operation Cycle type DQ[7:0] Command Address Address Address Command 60h R1 R2 R3 D0h tWB tBERS SR[6] PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Erase Operations ERASE BLOCK MULTI-PLANE (60h-D1h) The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for a block to be erased. To specify the final block to be erased and to begin the ERASE operation for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). To queue a block to be erased, write 60h to the command register, then write three address cycles containing the row address; the page address is ignored. Conclude by writing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY. To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the LUN's status shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK MULTI-PLANE (60h-D1h) commands can be issued to queue additional planes for erase. Alternatively, the ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks. For multi-plane addressing requirements for the ERASE BLOCK MULTI-PLANE (60hD1h) and ERASE BLOCK (60h-D0h) commands, see Multi-Plane Operations. Figure 66: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation Cycle type DQ[7:0] Command Address Address Address Command 60h R1 R2 R3 D1h tWB Command Address 60h ... tDBSY RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Copyback Operations Copyback Operations COPYBACK operations make it possible to transfer data within a plane from one page to another using the cache register. This is particularly useful for block management and wear leveling. The COPYBACK operation is a two-step process consisting of a COPYBACK READ (00h-35h) and a COPYBACK PROGRAM (85h-10h) command. To move data from one page to another on the same plane, first issue the COPYBACK READ (00h-35h) command. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host can transfer the data to a new page by issuing the COPYBACK PROGRAM (85h-10h) command. When the die (LUN) is again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully. To prevent bit errors from accumulating over multiple COPYBACK operations, it is recommended that the host read the data out of the cache register after the COPYBACK READ (00h-35h) completes prior to issuing the COPYBACK PROGRAM (85h-10h) command. The CHANGE READ COLUMN (05h-E0h) command can be used to change the column address. The host should check the data for ECC errors and correct them. When the COPYBACK PROGRAM (85h-10h) command is issued, any corrected data can be input. The CHANGE ROW ADDRESS (85h) command can be used to change the column address. It is not possible to use the COPYBACK operation to move data from one plane to another or from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or COPYBACK READ (00h-35h) command to read the data out of the NAND, and then use a PROGRAM PAGE (80h-10h) command with data input to program the data to a new plane or die (LUN). Between the COPYBACK READ (00h-35h) and COPYBACK PROGRAM (85h-10h) commands, the following commands are supported: status operations (70h, 78h), and column address operations (05h-E0h, 06h-E0h, 85h). Reset operations (FFh, FCh) can be issued after COPYBACK READ (00h-35h), but the contents of the cache registers on the target are not valid. In devices which have more than one die (LUN) per target, once the COPYBACK READ (00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after the COPYBACK PROGRAM (85h-10h) command is issued. Multi-Plane Copyback Operations Multi-plane copyback read operations improve read data throughput by copying data simultaneously from more than one plane to the specified cache registers. This is done by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the COPYBACK READ (00h-35h) command. The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command can be used to further system performance of COPYBACK PROGRAM operations by enabling movement of multiple pages from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more COPYBACK PROGRAM (85h-11h) commands in front of the COPYBACK PROGRAM (85h-10h) command. See Multi-Plane Operations for details. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 104 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK READ (00h-35h) The COPYBACK READ (00h-35h) command is functionally identical to the READ PAGE (00h-30h) command, except that 35h is written to the command register instead of 30h. See READ PAGE (00h-30h) (page 89) for further details. Though it is not required, it is recommended that the host read the data out of the device to verify the data prior to issuing the COPYBACK PROGRAM (85h-10h) command to prevent the propagation of data errors. Figure 67: COPYBACK READ (00h-35h) Operation Cycle type Command Address Address Address Address Address Command DOUT DOUT DOUT 00h C1 C2 R1 R2 R3 35h Dn Dn+1 Dn+2 DQ[7:0] tWB tR tRR RDY Figure 68: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation Cycle type DQ[7:0] Command Address Address Address Address Address Command 00h C1 C2 R1 R2 R3 35h tWB tR DOUT DOUT DOUT D0 … Dj + n tRR RDY 1 Cycle type Command Address Address Command DOUT DOUT DOUT Dk Dk + 1 Dk + 2 tCCS DQ[7:0] 05h C1 C2 E0h RDY 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 105 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK PROGRAM (85h–10h) The COPYBACK PROGRAM (85h-10h) command is functionally identical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the command register, cache register contents are not cleared. See PROGRAM PAGE (80h-10h) for further details. Figure 69: COPYBACK PROGRAM (85h–10h) Operation Cycle type Command Address Address Address Address Address Command 85h C1 C2 R1 R2 R3 10h DQ[7:0] tWB tPROG RDY Figure 70: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation Cycle type Command Address Address Address Address Address DIN DIN Di Di + 1 tCCS DQ[7:0] 85h C1 C2 R1 R2 R3 RDY 1 Cycle type Command Address Address DIN DIN DIN Command Dj Dj + 1 Dj + 2 10h tCCS DQ[7:0] 85h C1 C2 tWB tPROG RDY 1 COPYBACK READ MULTI-PLANE (00h-32h) The COPYBACK READ MULTI-PLANE (00h-32h) command is functionally identical to the READ PAGE MULTI-PLANE (00h-32h) command, except that the 35h command is written as the final command. The complete command sequence for the COPYBACK READ PAGE MULTI-PLANE is 00h-32h-00h-35h. See READ PAGE MULTI-PLANE (00h-32h) (page 94) for further details. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Copyback Operations COPYBACK PROGRAM MULTI-PLANE (85h-11h) The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command is functionally identical to the PROGRAM PAGE MULTI-PLANE (80h-11h) command, except that when 85h is written to the command register, cache register contents are not cleared. See PROGRAM PAGE MULTI-PLANE (80h-11h) for further details. Figure 71: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation Cycle type Command Address Address Address Address Address DIN DIN DIN Command D0 … Dn 11h Command Address 85h ... tCCS DQ[7:0] 85h C1 C2 R1 R2 R3 tWB tDBSY RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Each target has a an OTP area with a range of OTP pages (see Table 15 (page 109)); the entire range is guaranteed to be good. Customers can use the OTP area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. The OTP area leaves the factory in an erased state (all bits are 1). Programming an OTP page changes bits that are 1 to 0, but cannot change bits that are 0 to 1. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area prevents further programming of the pages in the OTP area. Enabling the OTP Operation Mode The OTP area is accessible while the OTP operation mode is enabled. To enable OTP operation mode, issue the SET FEATURES (EFh) command to feature address 90h and write 01h to P1, followed by three cycles of 00h to P2 through P4. When the target is in OTP operation mode, all subsequent PAGE READ (00h-30h) and PROGRAM PAGE (80h-10h) commands are applied to the OTP area. ERASE commands are not valid while the target is in OTP operation mode. Programming OTP Pages Each page in the OTP area is programming using the PROGRAM OTP PAGE (80h-10h) command. Each page can be programmed more than once, in sections, up to the maximum number allowed (see NOP in Table 15 (page 109)). The pages in the OTP area must be programmed in ascending order. If the host issues a PAGE PROGRAM (80h-10h) command to an address beyond the maximum page-address range, the target will be busy for tOBSY and the WP# status register bit will be 0, meaning that the page is write-protected. Protecting the OTP Area To protect the OTP area, issue the OTP PROTECT (80h-10h) command to the OTP Protect Page. When the OTP area is protected it cannot be programmed further. It is not possible to unprotect the OTP area after it has been protected. Reading OTP Pages To read pages in the OTP area, whether the OTP area is protected or not, issue the PAGE READ (00h-30h) command. If the host issues the PAGE READ (00h-30h) command to an address beyond the maximum page-address range, the data output will not be valid. To determine whether the target is busy during an OTP operation, either monitor R/B# or use the READ STATUS (70h) command. Use of the READ STATUS ENHANCED (78h) command is prohibited while the OTP operation is in progress. Returning to Normal Array Operation Mode To exit OTP operation mode and return to normal array operation mode, issue the SET FEATURES (EFh) command to feature address 90h and write 00h to P1 through P4. If the RESET (FFh) command is issued while in OTP operation mode, the target will exit OTP operation mode and enter normal operating mode. If the synchronous interface is active, the target will exit OTP operation and enable the asynchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations If the SYNCHRONOUS RESET (FCh) command is issued while in the OTP operation mode, the target will exit OTP operation mode and the synchronous interface remains active. Table 15: OTP Area Details Description Value Number of OTP pages 30 OTP protect page address 01h OTP start page address 02h Number of partial page programs (NOP) to each OTP page 4 PROGRAM OTP PAGE (80h-10h) The PROGRAM OTP PAGE (80h-10h) command is used to write data to the pages within the OTP area. To program data in the OTP area, the target must be in OTP operation mode. To use the PROGRAM OTP PAGE (80h-10h) command, issue the 80h command. Issue five address cycles including the column address, the page address within the OTP page range, and a block address of 0. Next, write the data to the cache register using data input cycles. After data input is complete, issue the 10h command. R/B# goes LOW for the duration of the array programming time, tPROG. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ STATUS ENHANCED (78h) command is prohibited. When the target is ready, read the FAIL bit of the status register to determine whether the operation passed or failed (see Status Operations). The PROGRAM OTP PAGE (80h-10h) command also accepts the CHANGE WRITE COLUMN (85h) command during data input. If a PROGRAM PAGE command is issued to the OTP area after the area has been protected, then R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h. Figure 72: PROGRAM OTP PAGE (80h-10h) Operation Cycle type Command Address Address Address Address Address Din Din Din Command Command tADL DQ[7:0] 80h C1 C2 OTP Page 00h 00h Dout tWHR D1 … Dn 10h 70h tWB Status tPROG R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations Figure 73: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation Cycle type Command Address Address Address Address Address Din Din Din Command Dn … Dm 85h tADL DQ[7:0] 80h C1 C2 OTP Page 00h 00h R/B# 1 Cycle type Command Address Address Din Din Din Command Command tCCS DQ[7:0] 85h C1 C2 Dout tWHR Dp … Dr 10h 70h Status tWB tPROG R/B# 1 PROTECT OTP AREA (80h-10h) The PROTECT OTP AREA (80h-10h) command is used to prevent further programming of the pages in the OTP area. The protect the OTP area, the target must be in OTP operation mode. To protect all data in the OTP area, issue the 80h command. Issue five address cycles including the column address, OTP protect page address and block address; the column and block addresses are fixed to 0. Next, write 00h data for the first byte location and issue the 10h command. R/B# goes LOW for the duration of the array programming time, tPROG. The READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ STATUS ENHANCED (78h) command is prohibited. When the target is ready, read the FAIL bit of the status register to determine if the operation passed or failed (see Status Operations). If the PROTECT OTP AREA (80h-10h) command is issued after the OTP area has already been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND One-Time Programmable (OTP) Operations Figure 74: PROTECT OTP AREA (80h-10h) Operation Cycle type Command Address Address Address Address Address Din Command Command tADL DQ[7:0] 80h 00h 00h 01h 00h 00h Dout tWHR 00h 10h 70h tWB Status tPROG R/B# Note: 1. OTP data is protected following a status confirmation. READ OTP PAGE (00h-30h) The READ OTP PAGE (00h-30h) command is used to read data from the pages in the OTP area. To read data in the OTP area, the target must be in OTP operation mode. To use the READ OTP PAGE (00h-30h) command, issue the 00h command. Issue five address cycles including the column address, the page address within the OTP page range, and a block address of 0. Next, issue the 30h command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is transferred. To determine the progress of the data transfer, the host can monitor the target's R/B# signal, or alternatively the READ STATUS (70h) command can be used. If the status operations are used to monitor the die’s (LUN's) status, when the die (LUN) is ready (RDY = 1, ARDY = 1) the host disables status output and enables data output by issuing the READ MODE (00h) command. When the host requests data output, it begins at the column address specified. Additional pages within the OTP area can be read by repeating the READ OTP PAGE (00h-30h) command. The READ OTP PAGE (00h-30h) command is compatible with the CHANGE READ COLUMN (05h-E0h) command. Use of the READ STATUS ENHANCED (78h) and CHANGE READ COLUMN ENHANCED (06h-E0h) commands are prohibited. Figure 75: READ OTP PAGE (00h-30h) Operation Cycle type DQ[7:0] Command Address Address Address Address Address Command Dout Dout Dout 00h C1 C2 OTP Page 00h 00h 30h Dn Dn+1 Dn+2 tWB tR tRR R/B# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Multi-Plane Operations Multi-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific details are provided in Device and Array Organization. Multi-plane operations make better use of the NAND Flash arrays on these physical planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple planes, significantly improving system performance. Multi-plane operations must be of the same type across the planes; for example, it is not possible to perform a PROGRAM operation on one plane with an ERASE operation on another. When issuing MULTI-PLANE PROGRAM or ERASE operations, use the READ STATUS (70h) command and check whether the previous operation(s) failed. If the READ STATUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use the READ STATUS ENHANCED (78h) command—time for each plane—to determine which plane operation failed. Multi-Plane Addressing Multi-plane commands require an address per operational plane. For a given multiplane operation, these addresses are subject to the following requirements: • The LUN address bit(s) must be identical for all of the issued addresses. • The plane select bit, BA[7], must be different for each issued address. • The page address bits, PA[6:0], must be identical for each issued address. The READ STATUS (70h) command should be used following MULTI-PLANE PROGRAM PAGE and ERASE BLOCK operations on a single die (LUN). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Interleaved Die (Multi-LUN) Operations Interleaved Die (Multi-LUN) Operations In devices that have more than one die (LUN) per target, it is possible to improve performance by interleaving operations between the die (LUNs). An interleaved die (multiLUN) operation is one that individual die (LUNs) involved may be in any combination of busy or ready status during operations. Interleaved die (multi-LUN) operations are prohibited following RESET (FFh, FCh), identification (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1 for all of the die (LUNs) on the target. During an interleaved die (multi-LUN) operation, there are two methods to determine operation completion. The R/B# signal indicates when all of the die (LUNs) have finished their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the READ STATUS ENHANCED (78h) command can report the status of each die (LUN) individually. If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h), then the die (LUN) is able to accept the data for another cache operation when status register bit 6 is 1. All operations, including cache operations, are complete on a die when status register bit 5 is 1. Use the READ STATUS ENHANCED (78h) command to monitor status for the addressed die (LUN). When multi-plane commands are used with interleaved die (multi-LUN) operations, the multi-plane commands must also meet the requirements, see Multi-Plane Operations for details. After the READ STATUS ENHANCED (78h) command has been issued, the READ STATUS (70h) command may be issued for the previously addressed die (LUN). See Command Definitions for the list of commands that can be issued while other die (LUNs) are busy. During an interleaved die (multi-LUN) operation that involves a PROGRAM-series (80h-10h, 80h-15h, 80h-11h) operation and a READ operation, the PROGRAM-series operation must be issued before the READ-series operation. The data from the READseries operation must be output to the host before the next PROGRAM-series operation is issued. This is because the 80h command clears the cache register contents of all cache registers on all planes. When issuing combinations of commands to multiple die (LUNs) (e.g. Reads to one die (LUN) and Programs to another die (LUN)) or Reads to one die (LUN) and Reads to another die (LUN)), the host shall issue the READ STATUS ENHANCED (78h) command before reading data from any LUN. This ensures that only the LUN selected by the READ STATUS ENHANCED (78h) command responds to a data output cycle after being put into data output mode, and thus avoiding bus contention. After the READ STATUS ENHANCED (78h) command is issued to the selected die (LUN) a CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) command shall be issued prior to any data output from the selected die (LUN). PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Error Management Error Management Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks (NVB) of the total available blocks. This means the die (LUNs) could have blocks that are invalid when shipped from the factory. An invalid block is one that contains at least one page that has more bad bits than can be corrected by the minimum required ECC. Additional blocks can develop with use. However, the total number of available blocks per die (LUN) will not fall below NVB during the endurance life of the product. Although NAND Flash memory devices could contain bad blocks, they can be used quite reliably in systems that provide bad-block management and error-correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash array. NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks before shipping by attempting to program the bad-block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad-block mark. However, the first spare area location in each bad block is guaranteed to contain the bad-block mark. This method is compliant with ONFI Factory Defect Mapping requirements. See the following table for the first spare area location and the bad-block mark. System software should check the first spare area location on the first page of each block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because invalid blocks could be marginal, it may not be possible to recover this information if the block is erased. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: • Always check status after a PROGRAM or ERASE operation • Under typical conditions, use the minimum required ECC (see table below) • Use bad-block management and wear-leveling algorithms The first block (physical block address 00h) for each CE# is guaranteed to be valid with ECC when shipped from the factory. Table 16: Error Management Details Description Requirement Minimum number of valid blocks (NVB) per LUN 4016 Total available blocks per LUN 4096 First spare area location Byte 8192 Bad-block mark 00h Minimum required ECC 8-bit ECC per 540 bytes of data PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Output Drive Impedance Output Drive Impedance Because NAND Flash is designed for use in systems that are typically point-to-point connections, an option to control the drive strength of the output buffers is provided. Drive strength should be selected based on the expected loading of the memory bus. There are four supported settings for the output drivers: overdrive 2, overdrive 1, nominal, and underdrive. The nominal output drive strength setting is the power-on default value. The host can select a different drive strength setting using the SET FEATURES (EFh) command. The output impedance range from minimum to maximum covers process, voltage, and temperature variations. Devices are not guaranteed to be at the nominal line. Table 17: Output Drive Strength Conditions (VCCQ = 1.7–1.95V) Range Process Voltage Temperature Minimum Fast-Fast 1.95V TA (MIN) Nominal Typical-Typical 1.8V +25°C Maximum Slow-Slow 1.7V TA (MAX) Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) Output Strength Overdrive 2 Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit Rpd VCCQ × 0.2 7.5 13.5 34 ohms VCCQ × 0.5 9 18 31 ohms VCCQ × 0.8 11 23.5 44 ohms VCCQ × 0.2 11 23.5 44 ohms VCCQ × 0.5 9 18 31 ohms VCCQ × 0.8 7.5 13.5 34 ohms VCCQ × 0.2 10.5 19 47 ohms VCCQ × 0.5 13 25 44 ohms VCCQ × 0.8 16 32.5 61.5 ohms VCCQ × 0.2 16 32.5 61.5 ohms VCCQ × 0.5 13 25 44 ohms VCCQ × 0.8 10.5 19 47 ohms VCCQ × 0.2 15 27 66.5 ohms VCCQ × 0.5 18 35 62.5 ohms VCCQ × 0.8 22 52 88 ohms VCCQ × 0.2 22 52 88 ohms VCCQ × 0.5 18 35 62.5 ohms VCCQ × 0.8 15 27 66.5 ohms Rpu Overdrive 1 Rpd Rpu Nominal Rpd Rpu PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Output Drive Impedance Table 18: Output Drive Strength Impedance Values (VCCQ = 1.7–1.95V) (Continued) Output Strength Underdrive Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit Rpd VCCQ × 0.2 21.5 39 95 ohms VCCQ × 0.5 26 50 90 ohms VCCQ × 0.8 31.5 66.5 126.5 ohms VCCQ × 0.2 31.5 66.5 126.5 ohms VCCQ × 0.5 26 50 90 ohms VCCQ × 0.8 21.5 39 95 ohms Rpu Table 19: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) Range Process Voltage Temperature Minimum Fast-Fast 3.6V TA (MIN) Nominal Typical-Typical 3.3V +25°C Slow-Slow 2.7V TA (MAX) Maximum Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) Output Strength Overdrive 2 Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit Rpd VCCQ X 0.2 7.0 16.2 28.7 ohms VCCQ X 0.5 9.0 18.0 36.0 ohms VCCQ X 0.8 11.8 21.0 50.0 ohms VCCQ X 0.2 11.8 21.0 50.0 ohms VCCQ X 0.5 9.0 18.0 36.0 ohms VCCQ X 0.8 7.0 14.0 28.7 ohms VCCQ X 0.2 9.3 22.3 40.0 ohms VCCQ X 0.5 12.6 25.0 50.0 ohms VCCQ X 0.8 16.3 29.0 68.0 ohms VCCQ X 0.2 16.3 29.0 68.0 ohms VCCQ X 0.5 12.6 25.0 50.0 ohms VCCQ X 0.8 9.3 19.0 40.0 ohms VCCQ X 0.2 12.8 32.0 58.0 ohms VCCQ X 0.5 18.0 35.0 70.0 ohms VCCQ X 0.8 23.0 40.0 95.0 ohms VCCQ X 0.2 23.0 40.0 95.0 ohms VCCQ X 0.5 18.0 35.0 70.0 ohms VCCQ X 0.8 12.8 32.0 58.0 ohms Rpu Overdrive 1 Rpd Rpu Nominal Rpd Rpu PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Output Drive Impedance Table 20: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) (Continued) Output Strength Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit Rpd VCCQ X 0.2 18.4 45.0 80.0 ohms VCCQ X 0.5 25.0 50.0 100.0 ohms VCCQ X 0.8 32.0 57.0 136.0 ohms VCCQ X 0.2 32.0 57.0 136.0 ohms VCCQ X 0.5 25.0 50.0 100.0 ohms VCCQ X 0.8 18.4 45.0 80.0 ohms Underdrive Rpu Table 21: Pull-Up and Pull-Down Output Impedance Mismatch Drive Strength Notes: Minimum Maximum Unit Notes Overdrive 2 0 6.3 ohms 1, 2 Overdrive 1 0 8.8 ohms 1, 2 Nominal 0 12.3 ohms 1, 2 Underdrive 0 17.5 ohms 1, 2 1. Mismatch is the absolute value between pull-up and pull-down impedances. Both are measured at the same temperature and voltage. 2. Test conditions: VCCQ = VCCQ (MIN), VOUT = VCCQ × 0.5, TA = TOPER. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND AC Overshoot/Undershoot Specifications AC Overshoot/Undershoot Specifications The supported AC overshoot and undershoot area depends on the timing mode selected by the host. Table 22: Asynchronous Overshoot/Undershoot Parameters Timing Mode Parameter 0 1 2 3 4 5 Unit Maximum peak amplitude provided for overshoot area 1 1 1 1 1 1 V Maximum peak amplitude provided for undershoot area 1 1 1 1 1 1 V Maximum overshoot area above VCCQ 3 3 3 3 3 3 V-ns Maximum undershoot area below VSSQ 3 3 3 3 3 3 V-ns Table 23: Synchronous Overshoot/Undershoot Parameters Timing Mode Parameter 0 1 2 3 4 5 Unit Maximum peak amplitude provided for overshoot area 1 1 1 1 1 1 V Maximum peak amplitude provided for undershoot area 1 1 1 1 1 1 V Maximum overshoot area above VCCQ 3 3 3 2.25 1.8 1.5 V-ns Maximum undershoot area below VSSQ 3 3 3 2.25 1.8 1.5 V-ns Volts (V) Figure 76: Overshoot Maximum amplitude Overshoot area VCCQ Time (ns) Volts (V) Figure 77: Undershoot Maximum amplitude VSSQ Time (ns) PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 118 Undershoot area Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Input Slew Rate Synchronous Input Slew Rate Though all AC timing parameters are tested with a nominal input slew rate of 1 V/ns, it is possible to run the device at a slower slew rate. The input slew rates shown below are sampled, and not 100% tested. When using slew rates slower than the minimum values, timing must be derated by the host. Table 24: Test Conditions for Input Slew Rate Parameter Value Rising edge VIL(DC) To VIH(AC) Falling edge VIH(DC) To VIL(AC) Temperature range TA Table 25: Input Slew Rate (VCCQ = 1.7–1.95V) Command/ Address and DQ V/ns CLK/DQS Slew Rate Derating VIH(AC)/VIL(AC)= 540mV, VIH(DC)/VIL(DC)= 360mV 1 0.9 0.8 0.7 0.6 0.5 0.4 set hold set hold set hold set hold set hold set hold set 1 0 0 0 0 - - 0.9 0 0 0 0 0 0 0.8 - - 0 0 0 0 0.7 - - - - 0 0 0.6 - - - - - 0.5 - - - - 0.4 - - - - 0.3 - - - - PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN - 0.3 hold set hold Unit - - - - - - - - - ps - - - - - - - - - - ps 0 0 - - - - - - - - ps 0 0 0 0 - - - - - - ps - 0 0 0 0 0 0 - - - - ps - - - - 0 0 0 0 180 180 - - ps - - - - - - 180 180 360 360 660 660 ps - - - - - - - - 660 660 920 920 ps 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Output Slew Rate Output Slew Rate The output slew rate is tested using the following setup with only one die per DQ channel. Table 26: Test Conditions for Output Slew Rate Parameter Value VOL(DC) 0.3 × VCCQ VOH(DC) 0.7 × VCCQ VOL(AC) 0.2 × VCCQ VOH(AC) 0.8 × VCCQ Rising edge (tRISE) VOL(DC) to VOH(AC) Falling edge (tFALL) VOH(DC) to VOL(AC) Output capacitive load (CLOAD) 5pF Temperature range TA Table 27: Output Slew Rate (VCCQ = 1.7–1.95V) Output Drive Strength Min Max Unit Overdrive 2 1 5.5 V/ns Overdrive 1 0.85 5 V/ns Nominal 0.75 4 V/ns Underdrive 0.6 4 V/ns Min Max Unit Overdrive 2 1.5 10.0 V/ns Overdrive 1 1.5 9.0 V/ns Nominal 1.2 7.0 V/ns Underdrive 1.0 5.5 V/ns Table 28: Output Slew Rate (VCCQ = 2.7–3.6V) Output Drive Strength PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications Electrical Specifications Stresses greater than those listed can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability. Table 29: Absolute Maximum Ratings by Device Symbol Min1 Max1 Unit Voltage input VIN -0.6 4.6 V VCC supply voltage VCC -0.6 4.6 V VCCQ supply voltage VCCQ -0.6 4.6 V Storage temperature TSTG -65 150 °C Min Typ Max Unit °C Parameter Note: 1. Voltage on any pin relative to VSS. Table 30: Recommended Operating Conditions Parameter Symbol Operating temperature Commercial TA Industrial 0 – 70 –40 – +85 VCC supply voltage VCC 2.7 3.3 3.6 V VCCQ supply voltage (1.8V) VCCQ 1.7 1.8 1.95 V 2.7 3.3 3.6 V 0 0 0 V VCCQ supply voltage (3.3V) VSS ground voltage VSS Table 31: Valid Blocks per LUN Parameter Valid block number Note: Symbol Min Max Unit Notes NVB 4016 4096 Blocks 1 1. Invalid blocks are blocks that contain one or more bad bits beyond ECC. The device may contain bad blocks upon shipment. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked invalid from the factory. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications Table 32: Capacitance: 100-Ball BGA Package Notes 1 and 2 apply to entire table Single Die/Dual Die Package Description Quad Die Package Octal Die Package Symbol Min Typ Max Min Typ Max Min Typ Max Unit Notes Input capacitance (CLK) CCK 3.8 4.8 5.8 5.8 7.3 8.8 9.9 11.9 13.9 pF 3 Input capacitance (ALE, CLE, W/R#) CIN 2.7 3.7 4.7 4.9 6.4 7.9 8.9 10.9 12.9 pF 3 Input/output capacitance (DQ[7:0], DQS) CIO 3.4 4.4 5.4 6.1 7.6 9.1 11.4 13.4 15.4 pF 3 Input capacitance (CE#, WP#) COTHER – – 5.8 – – 8.8 – – 13.9 pF Delta clock capacitance DCCK – – 1.4 – – 1.7 – – 2 pF Delta input capacitance DCIN – – 1.4 – – 1.7 – – 2 pF Delta input/output capacitance DCIO – – 1.4 – – 1.7 – – 2 pF Notes: 1. Verified in device characterization; not 100% tested. 2. Test conditions: TA = 25ºC, ƒ = 100 MHz, VIN = 0V. 3. Values for CCK, CIN and CIO (TYP) are estimates. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications Table 33: Capacitance: 132-Ball BGA Package Notes 1 and 2 apply to entire table Die Package Description Quad Die Package Octal Die Package Symbol Min Typ Max Min Typ Max Min Typ Max Unit Notes Input capacitance (CLK) CCK 3.5 4.5 5.5 5.4 6.9 8.4 9.9 11.9 13.9 pF 3 Input capacitance (ALE, CLE, W/R#) CIN 3.4 4.4 5.4 5.3 6.8 8.3 9.8 11.8 13.8 pF 3 Input/output capacitance (DQ[7:0], DQS) CIO 3.9 4.9 5.9 6.4 7.9 9.4 12.0 14.0 16.0 pF 3 Input capacitance (CE#, WP#) COTHER – – 4.7 – – 7.3 – – 12.4 pF Delta clock capacitance DCCK – – 1.4 – – 1.7 – – 2 pF Delta input capacitance DCIN – – 1.4 – – 1.7 – – 2 pF Delta input/output capacitance DCIO – – 1.4 – – 1.7 – – 2 pF Notes: 1. Verified in device characterization; not 100% tested. 2. Test conditions: TA = 25ºC, ƒ = 100 MHz, VIN = 0V. 3. Values for CCK, CIN and CIO (TYP) are estimates. Table 34: Capacitance: 48-Pin TSOP Package Description Input capacitance – ALE, CE#, CLE, RE#, WE#, WP# Input/output capacitance – DQ[7:0] Note: Symbol Device Max Unit Notes CIN Single die package 8 pF 1 pF 1 CIO Dual die package 10 Quad die package 14 Single die package 6 Dual die package 10 Quad die package 18 1. These parameters are verified in device characterization and are not 100% tested. Test conditions: TC = 25°C; f = 1 MHz; Vin = 0V. Table 35: Capacitance: 52-Pad LGA Package Description Input capacitance – ALE, CE#, CLE, RE#, WE#, WP# PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Symbol Device Max Unit Notes CIN Quad die package 10 pF 1 Octal die package 14 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) Table 35: Capacitance: 52-Pad LGA Package (Continued) Description Symbol Device Max Unit Notes CIO Quad die package 10 pF 1 Octal die package 16 Input/output capacitance – DQ[7:0] Note: 1. These parameters are verified in device characterization and are not 100% tested. Test conditions: TC = 25°C; f = 1 MHz; Vin = 0V. Table 36: Test Conditions Parameter Value Notes Rising input transition VIL(DC) to VIH(AC) 1 Falling input transition VIH(DC) to VIL(AC) 1 Input rise and fall slew rates 1 V/ns – Input and output timing levels VCCQ/2 – CL = 5pF 2, 3 Output load: Nominal output drive strength Notes: 1. The receiver will effectively switch as a result of the signal crossing the AC input level; it will remain in that status as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 2. Transmission line delay is assumed to be very small. 3. This test setup applies to all package configurations. Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) Table 37: DC Characteristics and Operating Conditions (Asynchronous Interface) Conditions Symbol Min1 Typ1 Max1 Unit Array read current (active) – ICC1_A – 25 50 mA Array program current (active) – ICC2_A – 25 50 mA Parameter Erase current (active) – tRC I/O burst read current = tRC (MIN); IOUT= 0mA tWC I/O burst write current = tWC (MIN) ICC3_A – 25 50 mA ICC4R_A – 8 10 mA ICC4w_A – 8 10 mA Bus idle current – ICC5_A – 3 5 mA Current during first RESET command after power-on – ICC6 – – 10 mA Standby current - VCC CE# = VCCQ - 0.2V; WP# = 0V/VCCQ ISB – 10 50 µA Standby current - VCCQ CE# = VCCQ - 0.2V; WP# = 0V/VCCQ ISBQ – 3 10 µA IST – – 10 mA Staggered power-up current Note: tRISE = 1ms; CLINE = 0.1uF 1. All values are per die (LUN) unless otherwise specified. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) Table 38: DC Characteristics and Operating Conditions (Synchronous Interface) Parameter Conditions Array read current (active) CE# = VIL; Array program current (active) Erase current (active) tCK I/O burst read current = tCK = Min1 Typ1 Max1 Unit ICC1_S – 25 50 mA (MIN) tCK = (MIN) ICC2_S – 25 50 mA tCK = tCK (MIN) ICC3_S – 25 50 mA tCK (MIN); IOUT= 0mA ICC4R_S – 20 27 mA 20 27 mA I/O burst write current tCK Bus idle current tCK tCK tCK Symbol = tCK (MIN) ICC4W_S – = tCK (MIN) ICC5_S – 5 10 mA Standby current - VCC CE# = VCCQ - 0.2V; WP# = 0V/VCCQ ISB – 10 50 µA Standby Current - VCCQ CE# = VCCQ - 0.2V; WP# = 0V/VCCQ ISBQ – 3 10 µA Note: 1. All values are per die (LUN) unless otherwise specified. Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) Table 39: DC Characteristics and Operating Conditions (3.3V VCCQ) Parameter Condition Symbol Min Typ Max Unit CE#, DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (RE#), WP# VIH(AC) 0.8 × VCCQ – VCCQ + 0.3 V VIL(AC) –0.3 – 0.2 × VCCQ V DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (RE#) VIH(DC) 0.7 × VCCQ – VCCQ + 0.3 V VIL(DC) –0.3 – 0.3 × VCCQ V Input leakage current Any input VIN = 0V to VCCQ (all other pins under test = 0V) ILI – – ±10 µA Output leakage current DQ are disabled; VOUT = 0V to VCCQ ILO – – ±10 µA 1 Output low current (R/B#) VOL = 0.4V IOL (R/B#) 8 10 – mA 2 AC input high voltage AC input low voltage DC input high voltage DC input low voltage Notes: Notes 1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current of ±20µA and four die (LUNs) have a maximum leakage current of ±40µA in the asynchronous interface. 2. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full strength. See Table 12 (page 76) for additional details. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) Table 40: DC Characteristics and Operating Conditions (1.8V VCCQ) Parameter Condition Symbol Min Typ Max Unit CE#, DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (R/E#), WP# VIH(AC) 0.8 × VCCQ – VCCQ + 0.3 V VIL(AC) –0.3 – 0.2 × VCCQ V DQ[7:0], DQS, ALE, CLE, CLK (WE#), W/R# (R/E#) VIH(DC) 0.7 × VCCQ – VCCQ + 0.3 V VIL(DC) -0.3 – 0.3 × VCCQ V Input leakage current Any input VIN = 0V to VCCQ (all other pins under test = 0V) ILI – – ±10 µA 1 Output leakage current DQ are disabled; Vout = 0V to VCCQ ILO – – ±10 µA 1 VOL = 0.2V IOL (R/B#) 3 4 – mA AC input high voltage AC input low voltage DC input high voltage DC input low voltage Output low current (R/B#) Note: Notes 1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current of ±20µA and four die (LUNs) have a maximum leakage current of ±40µA in the asynchronous interface. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) Table 41: AC Characteristics: Asynchronous Command, Address, and Data Mode 0 Parameter Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes Clock period 100 50 35 30 25 20 ns Frequency ≈10 ≈20 ≈28 ≈33 ≈40 ≈50 MHz ALE to data start tADL 200 – 100 – 100 – 100 – 70 – 70 – ns ALE hold time tALH 20 – 10 – 10 – 5 – 5 – 5 – ns ALE setup time tALS 50 – 25 – 15 – 10 – 10 – 10 – ns ALE to RE# delay tAR 25 – 10 – 10 – 10 – 10 – 10 – ns tCEA – 100 – 45 – 30 – 25 – 25 – 25 ns tCH 20 – 10 – 10 – 5 – 5 – 5 – ns CE# HIGH to output High-Z tCHZ – 100 – 50 – 50 – 50 – 30 – 30 ns CLE hold time tCLH 20 – 10 – 10 – 5 – 5 – 5 – ns CLE to RE# delay tCLR 20 – 10 – 10 – 10 – 10 – 10 – ns CLE setup time tCLS 50 – 25 – 15 – 10 – 10 – 10 – ns tCOH 0 – 15 – 15 – 15 – 15 – 15 – ns CE# setup time tCS 70 – 35 – 25 – 25 – 20 – 15 – ns Data hold time tDH 20 – 10 – 5 – 5 – 5 – 5 – ns Data setup time tDS 40 – 20 – 15 – 10 – 10 – 7 – ns Output High-Z to RE# LOW tIR 10 – 0 – 0 – 0 – 0 – 0 – ns CE# access time CE# hold time CE# HIGH to output hold 1 2 tRC 100 – 50 – 35 – 30 – 25 – 20 – ns RE# access time tREA – 40 – 30 – 25 – 20 – 20 – 16 ns 3 RE# HIGH hold time tREH 30 – 15 – 15 – 10 – 10 – 7 – ns 3 RE# HIGH to output hold tRHOH 0 – 15 – 15 – 15 – 15 – 15 – ns 3 RE# HIGH to WE# LOW tRHW 200 – 100 – 100 – 100 – 100 – 100 – ns RE# HIGH to output High-Z tRHZ – 200 – 100 – 100 – 100 – 100 – 100 ns 2, 3 RE# LOW to output hold tRLOH 0 – 0 – 0 – 0 – 5 – 5 – ns 3 RE# pulse width tRP 50 – 25 – 17 – 15 – 12 – 10 – ns Ready to RE# LOW tRR 40 – 20 – 20 – 20 – 20 – 20 – ns WE# HIGH to R/B# LOW tWB – 200 – 100 – 100 – 100 – 100 – 100 ns WE# cycle time tWC 100 – 45 – 35 – 30 – 25 – 20 – ns RE# cycle time PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 127 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) Table 41: AC Characteristics: Asynchronous Command, Address, and Data (Continued) Mode 0 Parameter Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Symbol Min Max Min Max Min Max Min Max Min Max Min Max Unit Notes tWH 30 – 15 – 15 – 10 – 10 – 7 – ns WE# HIGH to RE# LOW tWHR 120 – 80 – 80 – 60 – 60 – 60 – ns WE# pulse width tWP 50 – 25 – 17 – 15 – 12 – 10 – ns WP# transition to WE# LOW tWW 100 – 100 – 100 – 100 – 100 – 100 – ns WE# HIGH hold time Notes: 1. Timing for tADL begins in the address cycle, on the final rising edge of WE# and ends with the first rising edge of WE# for data input. 2. Data transition is measured ±200mV from steady-steady voltage with load. This parameter is sampled and not 100 percent tested. 3. AC characteristics may need to be relaxed if output drive strength is not set to at least nominal. 4. Do not issue a new command during tWB, even if R/B# or RDY is ready. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) Table 42: AC Characteristics: Synchronous Command, Address, and Data Mode 0 Parameter Mode 1 Symbol Min Max Min Max Mode 2 Min Max Mode 3 Min Max Mode 4 Min Max Mode 5 Min Max Unit Clock period 50 30 20 15 12 10 ns Frequency ≈20 ≈33 ≈50 ≈67 ≈83 ≈100 MHz tAC 3 20 3 20 3 20 3 20 3 20 3 20 ns ALE to data loading time tADL 100 – 100 – 70 – 70 – 70 – 70 – ns Command, address data delay tCAD 25 – 25 – 25 – 25 – 25 – 25 – ns ALE, CLE, W/R# hold tCALH 10 – 5 – 4 – 3 – 2.5 – 2 – ns ALE, CLE, W/R# setup tCALS 10 – 5 – 4 – 3 – 2.5 – 2 – ns DQ hold – command, address tCAH 10 – 5 – 4 – 3 – 2.5 – 2 – ns DQ setup – command, address tCAS 10 – 5 – 4 – 3 – 2.5 – 2 – ns CE# hold tCH 10 – 5 – 4 – 3 – 2.5 – 2 – ns Average CLK cycle time tCK 50 100 30 50 20 30 15 20 12 15 10 12 ns Access window of DQ[7:0] from CLK 1 3 (avg) tCK (abs) Absolute CLK cycle time, from rising edge to rising edge CLK cycle HIGH Notes tCKH tCK tCK (abs) MIN = tCK (avg) + tJIT (per) MIN (abs) MAX = tCK (avg) + tJIT (per) MAX ns 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4 (abs) CLK cycle LOW Data output end to W/R# HIGH tCKL (abs) tCKWR tCKWR(MIN) CE# setup tCS 35 Data In hold tDH tDQSCK Access window of DQS from CLK – 25 5 – – 20 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN = RoundUp[(tDQSCK(MAX) + tCK)/tCK] – 15 – 15 2.5 – – 20 1.7 – – 20 129 – 15 1.3 – – 20 tCK – 15 – ns 1.1 – 0.8 – ns – 20 – 20 ns Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) Table 42: AC Characteristics: Synchronous Command, Address, and Data (Continued) Mode 0 Parameter Mode 1 Symbol Min Max Min Mode 2 Mode 3 Mode 4 Max Min Max Min Max Min Max Mode 5 Min Max Unit tDQSD – 18 – 18 – 18 – 18 – 18 – 18 ns DQS, DQ[7:0] to tri-state tDQSHZ – 20 – 20 – 20 – 20 – 20 – 20 ns DQS input high pulse width tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS input low pulse width tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQS-DQ skew tDQSQ – 5 – 2.5 – 1.7 – 1.3 – 1.0 – 0.85 ns Data input tDQSS tCK DQS, DQ[7:0] Driven by NAND 0.75 1.25 tDS 5 DQS falling edge from CLK rising – hold tDSH 0.2 DQS falling to CLK rising – setup tDSS 0.2 Data valid window tDVW Half clock period tHP Data In setup The deviation of a given tCK (abs) from a tCK (avg) tJIT 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 – 3 – 0.2 – 2 – 1.5 – 1.1 – 0.8 – ns – 0.2 – 0.2 – 0.2 – 0.2 – tCK – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – tCK tDVW tHP (per) –0.7 0.7 –0.7 0.7 –0.7 = tQH - tDQSQ ns = Min(tCKH, tCKL) ns 0.7 0.6 –0.6 0.6 –0.5 0.5 tQH Data hold skew factor tQHS – 6 – 3 – 2 – 1.5 – 1.2 – Data output to command, address, or data input tRHW 100 – 100 – 100 – 100 – 100 – 100 Ready to data output tRR 20 – 20 – 20 – 20 – 20 – 20 – ns CLK HIGH to R/B# LOW tWB – 100 – 100 – 100 – 100 – 100 – 100 ns tWHR 80 – 80 – 80 – 80 – 80 – 80 – ns PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN = tHP - tQHS 130 5 ns DQ-DQS hold, DQS to first DQ to go nonvalid, per access Command cycle to data output tQH –0.6 Notes ns 1 ns ns Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) Table 42: AC Characteristics: Synchronous Command, Address, and Data (Continued) Mode 0 Parameter Mode 1 Symbol Min Max Min Max Mode 2 Min Max Mode 3 Min Max Mode 4 Min Max Mode 5 Min Max Unit DQS write preamble tWPRE 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – tCK DQS write postamble tWPST 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – tCK W/R# LOW to data output cycle tWRCK 20 – 20 – 20 – 20 – 20 – 20 – ns WP# transition to command cycle tWW 100 – 100 – 100 – 100 – 100 – 100 – ns Notes: Notes 1. Delay is from start of command to next command, address, or data cycle; start of address to next command, address, or data cycle; and end of data to start of next command, address, or data cycle. 2. This value is specified in the parameter page. 3. tCK(avg) is the average clock period over any consecutive 200-cycle window. 4. tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter. 5. tDQSHZ begins when W/R# is latched HIGH by CLK. This parameter is not referenced to a specific voltage level; it specifies when the device outputs are no longer driving. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Electrical Specifications – Array Characteristics Electrical Specifications – Array Characteristics Table 43: Array Characteristics Parameter Number of partial page programs Symbol Typ Max Unit Notes 4 Cycles 1 NOP – tBERS 1.5 7 ms tCCS – 200 ns Cache busy tCBSY 12 560 µs Dummy busy time tDBSY 0.5 1 µs tRCBSY 9 35 µs tFEAT – 1 µs tITC – 1 µs 2 tLPROG – – µs 3 tOBSY – 40 µs tPOR – 1 ms tPROG 350 560 µs 6 tR – 35 µs 5 tRST – 5/10/500 µs 4 ERASE BLOCK operation time Change column setup time to data in/out or next command Cache read busy time Busy time for SET FEATURES and GET FEATURES operations Busy time for interface change LAST PAGE PROGRAM operation time Busy time for OTP DATA PROGRAM operation if OTP is protected Power-on reset time PROGRAM PAGE operation time READ PAGE operation time Device reset time (Read/Program/Erase) Notes: 1. The pages in the OTP Block have an NOP of 4. 2. tITC (MAX) is the busy time when the interface changes from asynchronous to synchronous using the SET FEATURES (EFh) command or synchronous to asynchronous using the RESET (FFh) command. During the tITC time, any command, including READ STATUS (70h) and READ STATUS ENHANCED (78h), is prohibited. 3. tLPROG = tPROG (last page) + tPROG (last page - 1) - command load time (last page) address load time (last page) - data load time (last page). 4. If RESET command is issued when the target is READY, the target goes busy for a maximum of 5µs. 5. tR for invaild facotry blocks could be up to 38µs. 6. tPROG for OTP operations could be up to 600µs. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Asynchronous Interface Timing Diagrams Figure 78: RESET Operation CLE CE# tWB WE# tRST R/B# FFh DQ[7:0] RESET command Figure 79: RESET LUN Operation tCS CE# tCLS tCLH CLE tWC tWP tWP tWH tCH WE# tALH tALS tALH ALE tDS DQ[7:0] tWB tDH FAh Row add 1 Row add 2 Row add 3 tRST R/B# Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 80: READ STATUS Cycle tCLR CLE tCLS tCLH tCS CE# tWP tCH WE# tCEA tWHR tCHZ tCOH tRP RE# tDS DQ[7:0] tDH tIR tREA tRHZ tRHOH Status output 70h Don’t Care Figure 81: READ STATUS ENHANCED Cycle tCS CE# tCLS tCLH CLE tWC tWP tWP tWH tCH WE# tALH tALS tALH tAR tCHZ tCEA tCOH ALE RE# tRHZ tDS DQ[7:0] tDH 78h tWHR Row add 1 Row add 2 Row add 3 tREA tRHOH Status output Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 82: READ PARAMETER PAGE CLE WE# tWB ALE tRC RE# tRR DQ[7:0] ECh 00h P00 tR R/B# tRP P10 P2550 P01 Figure 83: READ PAGE CLE tCLR CE# tWC WE# tWB tAR ALE tR tRC tRHZ RE# tRR DQx 00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 tRP DOUT N 30h DOUT N+1 DOUT M Busy RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 84: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE tR RDY WE# DQx 00h Address (5 cycles) 30h Data output tCEA CE# tREA tCOH RE# Don’t Care Out I/Ox PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN tCHZ 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 85: CHANGE READ COLUMN CLE tCLR CE# WE# tRHW tCCS ALE tRC tREA RE# DQx DOUT N–1 DOUT N 05h Col add 1 Col add 2 E0h DOUT M DOUT M+1 Column address M RDY PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 86: READ PAGE CACHE SEQUENTIAL CLE tCLS tCLS tCLH tCS tCH tCS tCLH tCH CE# tWC WE# tCEA tRHW ALE tRC RE# tDH tDS tR tWB DQx Col add 1 00h Col add 2 Row add 1 Column address 00h Row add 2 Row add 3 tRR 30h DOUT 0 31h Page address M tWB tREA tDS DOUT 1 DOUT tDH 31h Page address M tRCBSY RDY Column address 0 1 CLE tCLS tCLH tCS tCH CE# WE# tRHW tRHW tCEA ALE tRC tRC RE# tWB tREA DQx DOUT 0 DOUT 1 tDS DOUT Page address M tRR tDH tREA DOUT 0 31h tRCBSY DOUT 1 DOUT Page address M+1 DOUT 0 3Fh tRCBSY DOUT 1 DOUT Page address M+2 RDY Column address 0 Column address 0 Column address 0 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Don’t Care 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 87: READ PAGE CACHE RANDOM CLE tCLS tCLH tCH tCS CE# tWC WE# ALE RE# tDH tWB tDS DQx Col add 1 00h Row add 1 Col add 2 Column address 00h Row add 2 Row add 3 tR 30h Col add 1 00h Page address M Row add 1 Col add 2 Column address 00h Row add 2 Page address N RDY 1 CLE tCLS tCLH tCS tCH CE# WE# tCEA ALE tRC tWB RE# DQx tRHW tDS Col add 1 Row add 1 Col add 2 Column address 00h Row add 2 Row add 3 Page address N RDY tDH tRR tREA DOUT 0 31h DOUT 1 Page address M tRCBSY Column address 0 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN DOUT DOUT 0 3Fh tRCBSY DOUT 1 DOUT Page address N Column address 0 Don’t Care 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 88: READ ID Operation CLE CE# WE# tAR ALE RE# tWHR DQx 90h tREA Byte 1 Byte 0 00h or 20h Byte 2 Byte 3 Byte 4 Address, 1 cycle Figure 89: PROGRAM PAGE Operation CLE CE# tWC tADL WE# tWB tPROG tWHR ALE RE# DQx 80h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN N DIN M 10h 70h Status 1 up to m byte serial Input RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 90: PROGRAM PAGE Operation with CE# “Don’t Care” CLE CE# WE# ALE DQx Address (5 cycles) 80h Data Data input input 10h tCH tCS CE# tWP WE# Don’t Care Figure 91: PROGRAM PAGE Operation with CHANGE WRITE COLUMN CLE CE# tADL tWC tCCS WE# tWB tPROG tWHR ALE RE# DQx 80h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 DIN M DIN N Serial input 85h Col add 1 Col add 2 CHANGE WRITE Column address COLUMN command DIN P DIN Q Serial input 10h 70h Status READ STATUS command RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 92: PROGRAM PAGE CACHE CLE CE# tADL tWC WE# tWBtCBSY tWB tLPROG tWHR ALE RE# DQx 80h Row Row Row Col Col add 1 add 2 add 1 add 2 add 3 DIN DIN N M Serial input 15h 80h Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 DIN N DIN M 10h 70h Status RDY Last page - 1 Last page Don’t Care Figure 93: PROGRAM PAGE CACHE Ending on 15h CLE CE# tWC tADL tADL WE# tWHR tWHR ALE RE# DQx 80h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 DIN DIN M N Serial input 15h 70h Status 80h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 Last page – 1 DIN N DIN M 15h Status 70h Status Last page Poll status until: I/O6 = 1, Ready Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 70h 142 To verify successful completion of the last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page – 1 PROGRAM successful Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams Figure 94: COPYBACK CLE CE# tADL tWC WE# tWB tPROG tWB tWHR ALE RE# tR DQx 00h Col add 1 Col add 2 Row add 1 Row add 2 Row add 3 35h (or 30h) 85h Col Row Row Row Col add 1 add 2 add 1 add 2 add 3 Data 1 Data N 10h Busy RDY Status 70h READ STATUS Busy command Data Input Optional Don’t Care Figure 95: ERASE BLOCK Operation CLE CE# tWC WE# tWB tWHR ALE RE# tBERS DQ[7:0] 60h Row add 1 Row add 2 Row add 3 D0h 70h Row address RDY Status READ STATUS command Busy I/O0 = 0, Pass I/O0 = 1, Fail PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 143 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Synchronous Interface Timing Diagrams Figure 96: SET FEATURES Operation tCS CE# CLE tCALS tCALS ALE tCAD tCAD tWB tCAD tFEAT CLK tDQSS W/R# DQS DQx EFh Feat Addr P10 P11 P20 P21 P30 P31 P40 P41 R/B# Don’t Care Notes: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the last data byte is input for the subsequent command or data input cycle(s). 2. tDSH (MIN) generally occurs during tDQSS (MIN). 3. tDSS (MIN) generally occurs during tDQSS (MAX). 4. The cycle that tCAD is measured from may be an idle cycle (as shown), another command cycle, an address cycle, or a data cycle. The idle cycle is shown in this diagram for simplicity. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 97: READ ID Operation tCS CE# tCALS tCALS CLE ALE tCALH tCAD tWHR tCAD CLK tCKWR tCALS tRHW tCALH W/R# tDQSD tDQSCK tCALS tDQSHZ DQS DQ[7:0] 90h 00h or 20h Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 145 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 98: GET FEATURES Operation tCS CE# tCALS tCALS CLE ALE tCALH tCAD tCAD CLK tCALS tCKWR tWRCK tRHW tCALH W/R# tDQSD tDQSCK tDQSHZ tCALS DQS DQ[7:0] EEh Feat Addr P1 P2 P3 P4 tWB tFEAT RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 146 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 99: RESET (FCh) Operation tCS tCH CE# tCALS tCALH CLE tCALS tCALH tCAD tCALH ALE CLK W/R# tWB DQS tCAS DQ[7:0] tCAH FCh SYNCHRONOUS RESET command tRST R/B# Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 147 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 100: READ STATUS Cycle CE# CLE ALE tCKWR tWHR tRHW CLK W/R# tDQSHZ tDQSD DQS DQ[7:0] Status 70h Status READ STATUS command RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 148 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 101: READ STATUS ENHANCED Operation tCS CE# CLE ALE tCAD tCAD tCAD tWHR tCAD tCKWR tRHW CLK W/R# tDQSHZ tDQSD DQS DQ[7:0] 78h Row add 1 Row add 2 Row add 3 Status Status Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 149 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 102: READ PARAMETER PAGE Operation tCS CE# tCALS tCALS CLE ALE tCAD tCAD tCALH CLK tCKWR tWRCK tRHW tCALH W/R# tDQSD tDQSCK tDQSHZ tCALS DQS DQ[7:0] ECh P0 00h tWB P1 P2 Pn-3 Pn-2 Pn-1 Pn tR RDY Driven PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 150 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 103: READ PAGE Operation tCS CE# CLE ALE tCAD tCAD tCAD tCAD tCAD tCAD tCAD CLK tCALS W/R# DQS DQx Col add 1 00h Col add 2 Row add 1 Row add 2 Row add 3 30h tWB tR RDY 1 CE# tCALS tCALS CLE ALE tCALH tCAD tCAD CLK tCKWR tWRCK tCALS tRHW tCALH W/R# tDQSD tCALS tDQSCK tDQSHZ DQS DQx Row add 3 Dout 0 30h tWB Dout N-3 Dout N-2 Dout N-1 Dout N 1 up to m Byte serial input tR RDY 1 Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 151 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 104: CHANGE READ COLUMN CE# tCALS tCALS CLE ALE tCAD tRHW tCAD tCAD tCCS tRHW CLK tDQSD tDQSHZ W/R# tDQSCK DQS DQx 05h Col add 1 Col add 2 Dout C E0h Dout C+1 Dout D-2 Dout D-1 Dout D RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 152 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 105: READ PAGE CACHE SEQUENTIAL (1 of 2) CE# CLE ALE tRHW CLK tDQSHZ W/R# tDQSD tDQSD tDQSCK DQS Initial Read Data DQx 30h tWB 31h tR tWB Data tRCBSY Output 31h tWB tRCBSY RDY Initial Read Access Sequential Read Access A 1 Sequential Read Access B Driven PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 153 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 106: READ PAGE CACHE SEQUENTIAL (2 of 2) CE# CLE ALE tRHW tRHW CLK tDQSHZ tDQSHZ W/R# tDQSD tDQSCK tDQSD tDQSCK DQS Sequential Read Data A DQx Data tRCBSY Output Sequential Read Data B 3Fh tWB Data Output tRCBSY RDY 1 Driven PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 154 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 107: READ PAGE CACHE RANDOM (1 of 2) CE# CLE ALE tCAD tRHW tRHW tCAD x 4 tCAD tCAD x 4 CLK tDQSHZ W/R# tDQSCK tDQSD DQS Initial Read Data DQx 30h tWB 00h 5 Address Cycles 31h tR Data tWB Output 00h 5 Address Cycles 31h tRCBSY tWB tRCBSY RDY Initial Read Access Random Read Access B Random Read Access A 1 Don’t Care Driven Figure 108: READ PAGE CACHE RANDOM (2 of 2) CE# CLE ALE tRHW tCAD x 4 tRHW CLK tDQSHZ tDQSHZ W/R# tDQSD tDQSCK tDQSD tDQSCK DQS Random Read Data A DQx 31h tWB Data Random Read Data B 3Fh Output tRCBSY tWB Data Output tRCBSY RDY Random Read Access B 1 Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 155 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 109: Multi-Plane Read Page (1 of 2) CE# CLE tCALS tCALS ALE tCAD tCAD x 5 tCAD tCAD x 5 tCAD tRHW tCAD x 5 CLK tDQSHZ W/R# tDQSD tDQSCK DQS If data from a plane other than A is desired, a 06h-E0h command sequence is required after tR and prior to taking W/R# LOW. tWB DQx 00h Address A 5 Cycles Address B 5 Cycles 00h 32h Data A Output 30h tWB 06h Address B 5 Cycles E0h tR RDY tDBSY Don’t Care 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 156 Driven 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 110: Multi-Plane Read Page (2 of 2) CE# CLE ALE tRHW tCAD tCAD x 5 CLK tDQSHZ W/R# tCCS tDQSD tDQSD tDQSCK tDQSCK DQS DQx Data B Output E0h 06h Address A 5 Cycles E0h RDY 2 3 CE# CLE ALE tRHW tCAD tRHW tCAD x 5 CLK tDQSHZ tDQSHZ W/R# tCCS tDQSCK tDQSD tDQSCK DQS Data A Output DQx 06h Address B 5 Cycles E0h Data B Output RDY 3 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Undefined (driven by NAND) 157 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 111: PROGRAM PAGE Operation (1 of 2) tCS CE# CLE tCALS tCALS ALE tCAD tCAD tCAD tCAD tCAD tDQSS tADL tCAD CLK W/R# DQS DQx Col add 1 80h Col add 2 Row add 1 Row add 2 Din N Row add 3 Din N+1 Din M-2 Din M-1 Din M RDY 1 Don’t Care Driven Figure 112: PROGRAM PAGE Operation (2 of 2) CE# CLE tCALS ALE tDQSS tCAD tWB tWHR tPROG tRHW tCKWR CLK tCAD W/R# tDQSHZ tDQSD DQS DQx Din N Din N+1 Din M-2 Din M-1 Din M 10h 70h Status Status READ STATUS command RDY 1 Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 158 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 113: CHANGE WRITE COLUMN CE# CLE tCALS tCALS ALE tCAD tCAD tCAD tCCS tDQSS CLK W/R# DQS DQx Din N+1 Din M-2 Din M-1 Din M Col add 1 85h Din C Col add 2 Din C+1 RDY 1 CE# CLE tCALS tCALS ALE tCAD tCAD tCCS tCAD tDQSS tCAD CLK W/R# DQS DQx 85h Col add 1 Din C Col add 2 Din C+1 Din D-2 Din D-1 Din D RDY 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Don’t Care 159 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 114: Multi-Plane Program Page CE# CLE tCALS tCALS ALE tCAD tCAD x 4 + tADL tDQSS tCAD tWB tDBSY tCAD CLK W/R# DQS 80h DQx Address A 5 Cycles Data A 11h 80h Address B 5 Cycles RDY 1 CE# CLE ALE tCAD tCAD x 4 + tADL tDQSS tCAD tWB tRHW tWHR tPROG CLK tDQSHZ tCAD W/R# tDQSD DQS DQx Address B 5 Cycles Data B 10h 70h Status Status RDY 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 160 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 115: ERASE BLOCK tCS CE# CLE ALE tCAD tCAD tCAD tCAD tRHW tWHR tCAD CLK tCAD W/R# tDQSHZ tDQSD DQS DQ[7:0] 60h Row add 1 Row add 2 Row add 3 D0h tWB Status Status 70h tBERS READ STATUS command RDY Don’t Care Driven Figure 116: COPYBACK (1 of 3) CE# CLE ALE tCAD tCAD x 5 tRHW tCAD tCADx2 CLK tDQSHZ W/R# tDQSD tDQSCK DQS DQx 00h 5 Address Cycles 35h or 30h tWB Data Output 05h 2 Address Cycles E0h tR RDY Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 161 Driven 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 117: COPYBACK (2 of 3) CE# CLE tCALS tCALS ALE tCAD tRHW tCAD tCAD x 5 tCAD + tADL tDQSS CLK tDQSHZ W/R# tDQSD tDQSCK DQS DQx Data Output h 85h 5 Address Cycles 85h 2 Address Cycles Data RDY 1 Don’t Care Driven 2 Figure 118: COPYBACK (3 of 3) CE# CLE ALE tCAD tWB tWHR tPROG tRHW CLK tDQSHZ tCAD W/R# tDQSD DQS 10h DQx 70h Status Status RDY 2 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Don’t Care 162 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 119: READ OTP PAGE tCS CE# tCALS tCALS CLE ALE tCALH tCAD tCAD tCAD tCAD tCAD tCAD tCAD CLK tCALS tCKWR tWRCK tRHW tCALH W/R# tDQSD tDQSCK tCALS tDQSHZ DQS DQx 00h Col add 1 Col add 2 OTP page1 00h Dout 0 30h 00h Dout N-3 Dout N-2 Dout N-1 Dout N tWB tR R/B# Don’t Care PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 163 Driven Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 120: PROGRAM OTP PAGE (1 of 2) tCS CE# CLE tCALS tCALS ALE tCAD tCAD tCAD tCAD tCAD tADL tCAD tDQSS CLK W/R# DQS DQx 80h Col add 1 Col add 2 OTP page1 00h Din N 00h Din N+1 Din M-2 Din M-1 Din M RDY Don’t Care Driven 1 Figure 121: PROGRAM OTP PAGE (2 of 2) CE# CLE tCALS ALE tCAD tWB tPROG tWHR tCKWR tRHW CLK tCAD W/R# tDQSHZ tDQSD DQS DQx Din M-2 Din M-1 Din M 10h Status 70h Status READ STATUS command RDY OTP data written (following "pass" status confirmation) 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Don’t Care 164 Driven Transitioning Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Synchronous Interface Timing Diagrams Figure 122: PROTECT OTP AREA CE# CLE tCALS ALE tCAD tCAD tCAD tCAD tCAD tCAD tADL tDQSS CLK W/R# DQS DQ[7:0] Col 00h 80h Col 00h 01h 00h 00h 00h RDY 1 CE# CLE tCALS ALE tCAD tWB tPROG tWHR tRHW CLK tDQSHZ tCAD W/R# tDQSD DQS DQ[7:0] 10h 70h Status Status READ STATUS command RDY 1 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN Don’t Care 165 Driven Transitioning Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Revision History Revision History Rev. H Production – 2/14 • Corrected typo on features page - number of blocks on 256Gb device Rev. G Production – 1/14 • Updated Parameter Page Data Structure table for: – Byte 154 to 6Eh – Bytes 253 for revision and 254–255 for CRC Rev. F Production – 5/12 • Added polyimide wafer process option to part numbering • Updated the Output Drive Strength Conditions table so that range labels (min & max) match the ONFI definition • Changed the Output Drive Strength Conditions table to show minimum temperature as T A (MIN) and maximum temperature as T A (MAX) • Changed table heading from “Output Drive Strength Test Conditions” to “Output Drive Strength Conditions” Rev. E Production – 4/12 • Added 132-ball BGA package options and information regarding those devices Rev. D Production – 6/11 • Changed endurance to 60,000 P/E cycles • Updated Read Parameter Page values • Added further clarification on definitions for Interleaved Die (Multi-LUN) Operations section • • • • • • Updated ICC4R_S and ICC4W_S Max to 27mA Updated tBERS TYP to 1.5ms and Max to 7ms Updated tCBSY TYP to 12µs Updated tRCBSY TYP to 9µs Updated tPROG TYP to 350µs and Max to 560µs Added note in table Array Characteristics that tPROG for OTP operations could be up to 600µs • • • • • Updated Read Parameter Page values Updated values for Output Drive Impedance for V CCQ 3.3V Updated capacitance values for BGA/TSOP devices Changed Icc4r and Icc4w values for both Asynchronous and Synchronous operations Updated tWHR for Synchronous mode of operation to 80ns for all timing modes Rev. C – 12/10 PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved. Micron Confidential and Proprietary 32Gb, 64Gb, 128Gb, 256Gb Asynchronous/Synchronous NAND Revision History Rev. B – 7/10 • Changed Data Retention statement from '10 years' to 'JESD47G compliant; see 'Qualification Report' • Updated Read Parameter Page values • Added note in table Array Characteristics that tR for invalid factory blocks could be up to 38µs • Updated capacitance values for 52-Pad LGA devices • Changed tAC Min from 10ns to 3ns • Changed tDQSD Max from 20ns to 18ns • Changed tOBSY Max from 30µs to 40µs Rev. A – 2/10 • Initial release 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83e0bed4 M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_NAND.pdf Rev. H 2/14 EN 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2010 Micron Technology, Inc. All rights reserved.