Micron Confidential and Proprietary
Preliminary‡
1Gb x8, x16: NAND Flash Memory
Features
NAND Flash Memory
MT29F1G08ABAEAWP-IT, MT29F1G08ABAEAWP, MT29F1G08ABAEAH4-IT
MT29F1G08ABAEAH4, MT29F1G08ABBEAH4-IT, MT29F1G08ABBEAH4,
MT29F1G16ABBEAH4-IT, MT29F1G16ABBEAH4, MT29F1G08ABBEAHC-IT,
MT29F1G08ABBEAHC, MT29F1G16ABBEAHC-IT, MT29F1G16ABBEAHC
Features
• Ready/busy# (R/B#) signal provides a hardware
method for detecting operation completion
• WP# signal: write protect entire device
• First block (block address 00h) is valid when shipped from factory with ECC. For minimum required
ECC, see Error Management.
• Block 0 requires 1-bit ECC if PROGRAM/ERASE cycles are less than 1000
• RESET (FFh) required as first command after power-on
• Alternate method of device initialization (Nand_Init) after power up3 (contact factory)
• Quality and reliability
– Data retention: 10 years
– Endurance: 100,000 PROGRAM/ERASE cycles
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCC: 1.7–1.95V
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 48-pin TSOP type 1, CPL 2
– 63-ball VFBGA
• Open NAND Flash Interface (ONFI) 1.0-compliant1
• Single-level cell (SLC) technology
• Organization
– Page size x8: 2112 bytes (2048 + 64 bytes)
– Page size x16: 1056 words (1024 + 32 words)
– Block size: 64 pages (128K + 4K bytes)
– Device size: 1Gb: 1024 blocks
• Asynchronous I/O performance
– tRC/tWC: 20ns (3.3V), 25ns (1.8V)
• Array performance
– Read page: 25µs
– Program page: 200µs (TYP, 3.3V and 1.8V)
– Erase block: 700µs (TYP)
• Command set: ONFI NAND Flash Protocol
• Advanced command set
– Program page cache mode
– Read page cache mode
– One-time programmable (OTP) mode
– Read unique ID
– Internal data move
– Block lock (1.8V only)
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Internal data move operations supported within the
device from which data is read
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m68m_non_ecc.pdf – Rev. E 7/12 EN
Notes:
1
1. The ONFI 1.0 specification is available at
www.onfi.org.
2. CPL = Center parting line.
3. Available only in the 1.8V VFBGA package.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron’s production data sheet specifications.
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Marketing Part Number Chart
MT 29F 1G 08
A
B
B
E
A
HC xx
Micron Technology
xx
x
ES
:E
Design Revision (shrink)
Product Family
Production Status
29F = NAND Flash memory
Blank = Production
Density
MS = Mechanical sample
1G = 1Gb
QS = Qualification sample
Device Width
Reserved for Future Use
08 = 8-bit
Blank
ES = Engineering sample
16 = 16-bit
Operating Temperature Range
Level
Blank = Commercial (0°C to +70°C)
A= SLC
IT = Industrial (–40°C to +85°C)
Classification
Mark Die
B
1
Speed Grade
nCE
RnB
I/O Channels
1
1
1
Blank
Package Code
Operating Voltage Range
WP = 48-pin TSOP 1
A = 3.3V (2.7–3.6V)
HC = 63-ball VFBGA (10.5 x 13 x 1.0mm)
B = 1.8V (1.7–1.95V)
H4 = 63-ball VFBGA (9 x 11 x 1.0mm)
Feature Set
Interface
E = Feature set E
A = Async only
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2
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© 2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
Contents
General Description ......................................................................................................................................... 8
Signal Descriptions and Assignments ................................................................................................................ 8
Signal Assignments ........................................................................................................................................... 9
Package Dimensions ....................................................................................................................................... 12
Architecture ................................................................................................................................................... 15
Device and Array Organization ........................................................................................................................ 16
Asynchronous Interface Bus Operation ........................................................................................................... 18
Asynchronous Enable/Standby ................................................................................................................... 18
Asynchronous Commands .......................................................................................................................... 18
Asynchronous Addresses ............................................................................................................................ 20
Asynchronous Data Input ........................................................................................................................... 21
Asynchronous Data Output ......................................................................................................................... 22
Write Protect# ............................................................................................................................................ 23
Ready/Busy# .............................................................................................................................................. 23
Device Initialization ....................................................................................................................................... 28
Command Definitions .................................................................................................................................... 29
Reset Operations ............................................................................................................................................ 31
RESET (FFh) ............................................................................................................................................... 31
Identification Operations ................................................................................................................................ 32
READ ID (90h) ............................................................................................................................................ 32
READ ID Parameter Tables .............................................................................................................................. 33
READ PARAMETER PAGE (ECh) ...................................................................................................................... 35
Parameter Page Data Structure Tables ............................................................................................................. 36
READ UNIQUE ID (EDh) ................................................................................................................................ 39
Feature Operations ......................................................................................................................................... 40
SET FEATURES (EFh) .................................................................................................................................. 41
GET FEATURES (EEh) ................................................................................................................................. 42
Status Operations ........................................................................................................................................... 45
READ STATUS (70h) ................................................................................................................................... 46
Column Address Operations ........................................................................................................................... 47
RANDOM DATA READ (05h-E0h) ................................................................................................................ 47
RANDOM DATA INPUT (85h) ...................................................................................................................... 48
PROGRAM FOR INTERNAL DATA INPUT (85h) ........................................................................................... 48
Read Operations ............................................................................................................................................. 50
READ MODE (00h) ..................................................................................................................................... 51
READ PAGE (00h-30h) ................................................................................................................................ 51
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 52
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 53
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 53
Program Operations ....................................................................................................................................... 55
PROGRAM PAGE (80h-10h) ......................................................................................................................... 55
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 56
Erase Operations ............................................................................................................................................ 58
ERASE BLOCK (60h-D0h) ............................................................................................................................ 58
Internal Data Move Operations ....................................................................................................................... 59
READ FOR INTERNAL DATA MOVE (00h-35h) ............................................................................................. 59
PROGRAM FOR INTERNAL DATA MOVE (85h-10h) ..................................................................................... 61
Block Lock Feature ......................................................................................................................................... 62
WP# and Block Lock ................................................................................................................................... 62
UNLOCK (23h-24h) .................................................................................................................................... 62
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
LOCK (2Ah) ................................................................................................................................................
LOCK TIGHT (2Ch) .....................................................................................................................................
BLOCK LOCK READ STATUS (7Ah) ..............................................................................................................
One-Time Programmable (OTP) Operations ....................................................................................................
OTP DATA PROGRAM (80h-10h) .................................................................................................................
RANDOM DATA INPUT (85h) ......................................................................................................................
OTP DATA PROTECT (80h-10) .....................................................................................................................
OTP DATA READ (00h-30h) .........................................................................................................................
Error Management .........................................................................................................................................
Electrical Specifications ..................................................................................................................................
Electrical Specifications – AC Characteristics and Operating Conditions ...........................................................
Electrical Specifications – DC Characteristics and Operating Conditions ...........................................................
Electrical Specifications – Program/Erase Characteristics .................................................................................
Asynchronous Interface Timing Diagrams .......................................................................................................
Revision History .............................................................................................................................................
Rev. E, Preliminary – 7/12 ............................................................................................................................
Rev. D, Preliminary – 2/12 ...........................................................................................................................
Rev. C, Preliminary – 2/12 ...........................................................................................................................
Rev. B, Preliminary – 11/11 ..........................................................................................................................
Rev. A, Preliminary – 08/11 ..........................................................................................................................
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
List of Tables
Table 1: Asynchronous Signal Definitions ......................................................................................................... 8
Table 2: Array Addressing (x8) ........................................................................................................................ 16
Table 3: Array Addressing (x16) ...................................................................................................................... 17
Table 4: Asynchronous Interface Mode Selection ............................................................................................ 18
Table 5: Command Set .................................................................................................................................. 29
Table 6: READ ID Parameters for Address 00h ................................................................................................. 33
Table 7: READ ID Parameters for Address 20h ................................................................................................. 34
Table 8: Parameter Page Data Structure .......................................................................................................... 36
Table 9: Feature Address Definitions .............................................................................................................. 40
Table 10: Feature Address 90h – Array Operation Mode ................................................................................... 41
Table 11: Feature Addresses 01h: Timing Mode ............................................................................................... 43
Table 12: Feature Addresses 80h: Programmable I/O Drive Strength ................................................................ 44
Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 44
Table 14: Status Register Definition ................................................................................................................ 45
Table 15: Block Lock Address Cycle Assignments ............................................................................................ 64
Table 16: Block Lock Status Register Bit Definitions ........................................................................................ 67
Table 17: Error Management Details .............................................................................................................. 76
Table 18: Absolute Maximum Ratings ............................................................................................................. 77
Table 19: Recommended Operating Conditions .............................................................................................. 77
Table 20: Valid Blocks .................................................................................................................................... 77
Table 21: Capacitance .................................................................................................................................... 78
Table 22: Test Conditions ............................................................................................................................... 78
Table 23: AC Characteristics: Command, Data, and Address Input (3.3V) ......................................................... 79
Table 24: AC Characteristics: Command, Data, and Address Input (1.8V) ......................................................... 79
Table 25: AC Characteristics: Normal Operation (3.3V) ................................................................................... 80
Table 26: AC Characteristics: Normal Operation (1.8V) ................................................................................... 80
Table 27: DC Characteristics and Operating Conditions (3.3V) ........................................................................ 82
Table 28: DC Characteristics and Operating Conditions (1.8V) ........................................................................ 83
Table 29: ProgramErase Characteristics .......................................................................................................... 84
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View) ................................................................................................ 9
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View) ........................................................................................ 10
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View) ...................................................................................... 11
Figure 5: 48-Pin TSOP – Type 1, CPL ............................................................................................................... 12
Figure 6: 63-Ball VFBGA (HC) ........................................................................................................................ 13
Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm ................................................................................................... 14
Figure 8: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 9: Array Organization – x8 ................................................................................................................... 16
Figure 10: Array Organization – x16 ................................................................................................................ 17
Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19
Figure 12: Asynchronous Address Latch Cycle ................................................................................................ 20
Figure 13: Asynchronous Data Input Cycles .................................................................................................... 21
Figure 14: Asynchronous Data Output Cycles ................................................................................................. 22
Figure 15: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 23
Figure 16: READ/BUSY# Open Drain .............................................................................................................. 24
Figure 17: tFall and tRise (3.3V V CC) ................................................................................................................ 25
Figure 18: tFall and tRise (1.8V V CC) ................................................................................................................ 25
Figure 19: IOL vs. Rp (VCC = 3.3V V CC) .............................................................................................................. 26
Figure 20: IOL vs. Rp (1.8V V CC) ....................................................................................................................... 26
Figure 21: TC vs. Rp ....................................................................................................................................... 27
Figure 22: R/B# Power-On Behavior ............................................................................................................... 28
Figure 23: RESET (FFh) Operation .................................................................................................................. 31
Figure 24: READ ID (90h) with 00h Address Operation .................................................................................... 32
Figure 25: READ ID (90h) with 20h Address Operation .................................................................................... 32
Figure 26: READ PARAMETER (ECh) Operation .............................................................................................. 35
Figure 27: READ UNIQUE ID (EDh) Operation ............................................................................................... 39
Figure 28: SET FEATURES (EFh) Operation .................................................................................................... 41
Figure 29: GET FEATURES (EEh) Operation .................................................................................................... 42
Figure 30: READ STATUS (70h) Operation ...................................................................................................... 46
Figure 31: RANDOM DATA READ (05h-E0h) Operation ................................................................................... 47
Figure 32: RANDOM DATA INPUT (85h) Operation ........................................................................................ 48
Figure 33: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation .............................................................. 49
Figure 34: READ PAGE (00h-30h) Operation ................................................................................................... 51
Figure 35: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 52
Figure 36: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 53
Figure 37: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 54
Figure 38: PROGRAM PAGE (80h-10h) Operaton ............................................................................................. 56
Figure 39: PROGRAM PAGE CACHE (80h-15h) Operation (Start) ..................................................................... 57
Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (End) ...................................................................... 57
Figure 41: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 58
Figure 42: READ FOR INTERNAL DATA MOVE (00h-35h) Operation ................................................................ 60
Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) with RANDOM DATA READ (05h-E0h) ...................... 60
Figure 44: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) ........................................................................ 61
Figure 45: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................... 61
Figure 46: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 63
Figure 47: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 63
Figure 48: UNLOCK Operation ....................................................................................................................... 64
Figure 49: LOCK Operation ............................................................................................................................ 65
Figure 50: LOCK TIGHT Operation ................................................................................................................. 66
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6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Features
Figure 51:
Figure 52:
Figure 53:
Figure 54:
Figure 55:
Figure 56:
Figure 57:
Figure 58:
Figure 59:
Figure 60:
Figure 61:
Figure 62:
Figure 63:
Figure 64:
Figure 65:
Figure 66:
Figure 67:
Figure 68:
Figure 69:
Figure 70:
Figure 71:
Figure 72:
Figure 73:
Figure 74:
PROGRAM/ERASE Issued to Locked Block ......................................................................................
BLOCK LOCK READ STATUS ..........................................................................................................
BLOCK LOCK Flowchart ................................................................................................................
OTP DATA PROGRAM (After Entering OTP Operation Mode) ...........................................................
OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode)
OTP DATA PROTECT Operation (After Entering OTP Protect Mode) .................................................
OTP DATA READ ...........................................................................................................................
OTP DATA READ with RANDOM DATA READ Operation .................................................................
RESET Operation ...........................................................................................................................
READ STATUS Cycle ......................................................................................................................
READ PARAMETER PAGE ..............................................................................................................
READ PAGE ...................................................................................................................................
READ PAGE Operation with CE# “Don’t Care” ................................................................................
RANDOM DATA READ ...................................................................................................................
READ PAGE CACHE SEQUENTIAL .................................................................................................
READ PAGE CACHE RANDOM .......................................................................................................
READ ID Operation .......................................................................................................................
PROGRAM PAGE Operation ...........................................................................................................
PROGRAM PAGE Operation with CE# “Don’t Care” .........................................................................
PROGRAM PAGE Operation with RANDOM DATA INPUT ...............................................................
PROGRAM PAGE CACHE ...............................................................................................................
PROGRAM PAGE CACHE Ending on 15h .........................................................................................
INTERNAL DATA MOVE ................................................................................................................
ERASE BLOCK Operation ...............................................................................................................
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...
72
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75
85
85
86
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89
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91
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93
93
94
94
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
General Description
General Description
Micron NAND Flash devices include an asynchronous data interface for high-performance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that remains the same from one density to another, enabling future upgrades to higher densities with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
Signal Descriptions and Assignments
Table 1: Asynchronous Signal Definitions
Signal1
Type
Description2
ALE
Input
Address latch enable: Loads an address from I/O[7:0] into the address register.
CE#
Input
Chip enable: Enables or disables one or more die (LUNs) in a target.
CLE
Input
Command latch enable: Loads a command from I/O[7:0] into the command register.
RE#
Input
Read enable: Transfers serial data from the NAND Flash to the host system.
WE#
Input
Write enable: Transfers commands, addresses, and serial data from the host system to the
NAND Flash.
WP#
Input
Write protect: Enables or disables array PROGRAM and ERASE operations.
LOCK
Input
Lock: Enables the BLOCK LOCK function when LOCK is HIGH during power up. To disable
BLOCK LOCK, connect LOCK to VSS during power up or leave it disconnected (internal pulldown).
I/O[7:0] (x8)
I/O[15:0] (x16)
I/O
Data inputs/outputs: The bidirectional I/Os transfer address, data, and command information.
R/B#
Output
Ready/busy: An open-drain, active-low output that requires an external pull-up resistor.
This signal indicates target array activity.
VCC
Supply
VCC: Core power supply
VSS
Supply
VSS: Core ground connection
NC
–
No connect: NCs are not internally connected. They can be driven or left unconnected.
DNU
–
Do not use: DNUs must be left unconnected.
Notes:
PDF: 09005aef847d5585
m68m_non_ecc.pdf – Rev. E 7/12 EN
1. See Device and Array Organization for detailed signal connections.
2. See Asynchronous Interface Bus Operation for detailed asynchronous interface signal
descriptions.
8
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Signal Assignments
Signal Assignments
Figure 2: 48-Pin TSOP – Type 1, CPL (Top View)
x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
Vcc
Vss
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
Notes:
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m68m_non_ecc.pdf – Rev. E 7/12 EN
x8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Vss1
DNU
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
Vcc1
DNU
Vcc
Vss
NC
Vcc1
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
Vss1
1. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
2. For the 3V device, pin 38 is DNU. For the 1.8V device, pin 38 is LOCK.
9
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© 2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Signal Assignments
Figure 3: 63-Ball VFBGA, x8 (Balls Down, Top View)
1
2
A
NC
NC
B
NC
4
6
5
7
8
C
WP#
ALE
Vss
CE#
WE#
R/B#
D
Vcc2
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
Vss2
NC
G
DNU
Vcc2
LOCK1
NC
NC
DNU
H
NC
I/O0
NC
NC
NC
Vcc
J
NC
I/O1
NC
Vcc
I/O5
I/O7
K
Vss
I/O2
I/O3
I/O4
I/O6
Vss
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
Notes:
PDF: 09005aef847d5585
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3
1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
10
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© 2011 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Signal Assignments
Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View)
Notes:
PDF: 09005aef847d5585
m68m_non_ecc.pdf – Rev. E 7/12 EN
1
2
A
NC
NC
B
NC
3
4
6
5
7
8
C
WP#
ALE
VSS
CE#
WE#
R/B#
D
VCC
RE#
CLE
NC
NC
NC
E
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
NC
VSS2
NC
G
DNU
VCC2
LOCK1
I/O13
I/O15
DNU
H
I/O8
I/O0
I/O10
I/O12
I/O14
VCC
J
I/O9
I/O1
I/O11
VCC
I/O5
I/O7
K
VSS
I/O2
I/O3
I/O4
I/O6
VSS
9
10
NC
NC
NC
NC
L
NC
NC
NC
NC
M
NC
NC
NC
NC
1. For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device.
2. These pins might not be bonded in the package; however, Micron recommends that the
customer connect these pins to the designated external sources for ONFI compatibility.
11
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Preliminary
1Gb x8, x16: NAND Flash Memory
Package Dimensions
Package Dimensions
Figure 5: 48-Pin TSOP – Type 1, CPL
20.00 ±0.25
18.40 ±0.08
48
0.25
for reference only
0.50 TYP
for reference
only
1
Mold compound:
Epoxy novolac
Plated lead finish:
100% Sn
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
12.00 ±0.08
0.27 MAX
0.17 MIN
24
25
0.25
0.10
0.15
+0.03
-0.02
See detail A
1.20 MAX
0.10
Gage
plane
+0.10
-0.05
0.50 ±0.1
0.80
Detail A
Note:
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1. All dimensions are in millimeters.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Package Dimensions
Figure 6: 63-Ball VFBGA (HC)
0.65 ±0.05
Seating
plane
0.12 A
A
63X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls postreflow on Ø0.4 SMD
ball pads.
10
9
8
7
6
5
4
3
2
Ball A1 ID
1
Ball A1 ID
A
B
C
D
E
F
8.8 CTR
G
13 ±0.1
H
J
K
L
0.8 TYP
M
0.8 TYP
1.0 MAX
7.2 CTR
0.25 MIN
Bottom side saw fiducials may or
may not be covered with soldermask.
10.5 ±0.1
Note:
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1. All dimensions are in millimeters.
13
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Package Dimensions
Figure 7: 63-Ball VFBGA (H4) 9mm x 11mm
Seating
plane
0.1 A
A
63X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.4 SMD
ball pads.
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
10 9
8
7
6
5
4
3
2
Ball A1 ID
(covered by SR)
1
Ball A1 ID
A
B
C
D
E
F
8.8 CTR
G
11 ±0.1
H
J
K
L
0.8 TYP
M
1.0 MAX
0.8 TYP
0.25 MIN
7.2 CTR
9 ±0.1
Note:
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1. All dimensions are in millimeters.
14
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Micron Confidential and Proprietary
Preliminary
1Gb x8, x16: NAND Flash Memory
Architecture
Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control device operations. The addresses are latched by an address register and sent to a row decoder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word
by word (x16), through a data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput. The status register reports
the status of die operations.
Figure 8: NAND Flash Die (LUN) Functional Block Diagram
VCC
I/Ox
I/O
Control
VSS
Address Register
Status Register
Command Register
CE#
Column Decode
CLE
Control
Logic
Row Decode
ALE
WE#
RE#
WP#
LOCK1
Data Register
R/B#
Cache Register
Note:
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NAND Flash
Array
1. The LOCK pin is used on the 1.8V device.
15
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Preliminary
1Gb x8, x16: NAND Flash Memory
Device and Array Organization
Device and Array Organization
Figure 9: Array Organization – x8
2112 bytes
I/O0
Cache Register
2048
64
Data Register
2048
64
64 pages = 1 block
(128K + 4K) bytes
1 block
1024 blocks
per device
I/O7
1 page
= (2K + 64) bytes
1 block
= (2K + 64) bytes x 64 pages
= (128K + 4K) bytes
1 device = (2K + 64) bytes x 64 pages
x 1024 blocks
= 1056Mb
Table 2: Array Addressing (x8)
Cycle
I/O7
I/O6
I/O5
I/O4
I/OQ3
I/O2
I/O1
I/O0
First
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
Second
LOW
LOW
LOW
LOW
CA111
CA10
CA9
CA8
Third
BA7
BA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
Notes:
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1. If CA11 is 1, then CA[10:6] must be 0.
2. Block address concatenated with page address = actual page address; CAx = column address; PAx = page address; BAx = block address.
16
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Preliminary
1Gb x8, x16: NAND Flash Memory
Device and Array Organization
Figure 10: Array Organization – x16
1056 words
I/O0
Cache Register
1024
32
Data Register
1024
32
64 pages = 1 block
(64K + 2K) words
1 block
1024 blocks
per device
I/O15
1 page
= (1K + 32) words
1 block
= (1K + 32) words x 64 pages
= (64K + 2K) words
1 device = (1K + 32) words x 64 pages
x 1024 blocks
= 1056Mb
Table 3: Array Addressing (x16)
Cycle
First
I/O[15:8]
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
LOW
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
CA9
CA8
Second
LOW
LOW
LOW
LOW
LOW
LOW
CA101
Third
LOW
BA7
BA6
PA5
PA4
PA3
PA2
PA1
PA0
Fourth
LOW
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
Notes:
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1. If CA10 is 1, then CA[9:5] must be 0.
2. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
3. I/O[15:8] are not used during the addressing sequence and should be driven LOW.
17
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Asynchronous Interface Bus Operation
The bus on the device is multiplexed. Data I/O, addresses, and commands all share the
same pins. I/O[15:8] are used only for data in the x16 configuration. Addresses and
commands are always supplied on I/O[7:0].
The command sequence typically consists of a COMMAND LATCH cycle, address input
cycles, and one or more data cycles, either READ or WRITE.
Table 4: Asynchronous Interface Mode Selection
Mode1
CE#
CLE
ALE
WE#
RE#
I/Ox
WP#
Standby2
H
X
X
X
X
X
0V/VCC
Command input
L
H
L
H
X
H
Address input
L
L
H
H
X
H
Data input
L
L
L
H
X
H
Data output
L
L
L
H
X
X
Write protect
X
X
X
X
X
L
Notes:
X
1. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
2. WP# should be biased to CMOS LOW or HIGH for standby.
Asynchronous Enable/Standby
When the device is not performing an operation, the CE# pin is typically driven HIGH
and the device enters standby mode. The memory will enter standby if CE# goes HIGH
while data is being transferred and the device is not busy. This helps reduce power consumption.
The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory
bus can then be accessed while the NAND Flash is busy with internal operations. This
capability is important for designs that require multiple NAND Flash devices on the
same bus.
A HIGH CLE signal indicates that a command cycle is taking place. A HIGH ALE signal
signifies that an ADDRESS INPUT cycle is occurring.
Asynchronous Commands
An asynchronous command is written from I/O[7:0] to the command register on the rising edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h), are accepted by die (LUNs) even when they
are busy.
For devices with a x16 interface, I/O[15:8] must be written with zeros when a command
is issued.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Figure 11: Asynchronous Command Latch Cycle
CLE
tCLS
tCS
tCLH
tCH
CE#
tWP
WE#
tALS
tALH
tDS
tDH
ALE
I/Ox
COMMAND
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Asynchronous Addresses
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organization). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
Figure 12: Asynchronous Address Latch Cycle
CLE
tCLS
tCS
CE#
tWP
tWC
tWH
WE#
tALS
tALH
ALE
tDS tDH
I/Ox
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Don’t Care
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20
Row
add 3
Undefined
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Asynchronous Data Input
Data is written to the cache register of the selected die (LUN) on the rising edge of WE#
when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is
written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,
and the device is not busy.
Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
Figure 13: Asynchronous Data Input Cycles
CLE
tCLH
CE#
tALS
tCH
ALE
tWC
tWP
tWP
tWP
WE#
tWH
tDS
I/Ox
tDH
DIN M
tDS
tDH
DIN M+1
tDS
tDH
DIN N
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Asynchronous Data Output
Data can be output from a die (LUN) if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array. Data is output from the cache
register of the selected die (LUN) on the falling edge of RE# when CE# is LOW, ALE is
LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a tRC of 30ns or greater, the host can latch the data on the
rising edge of RE# (see the figure below for proper timing). If the host controller is using
a tRC of less than 30ns, the host can latch the data on the next falling edge of RE#.
Data is output on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
Figure 14: Asynchronous Data Output Cycles
tCEA
CE#
tREA
tREA
tRP
tCHZ
tREA
tREH
tCOH
RE#
tRHZ
tRHZ
tRHOH
DOUT
I/Ox
tRR
DOUT
DOUT
tRC
RDY
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Figure 15: Asynchronous Data Output Cycles (EDO Mode)
CE#
tRC
tRP
tCHZ
tREH
tCOH
RE#
tREA
tCEA
I/Ox
tREA
tRHZ
tRLOH
tRHOH
DOUT
DOUT
DOUT
tRR
RDY
Don’t Care
Write Protect#
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until V CC is stable to
prevent inadvertent PROGRAM and ERASE operations (see Device Initialization for additional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issuing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a target is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Status Operations for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing requirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%
and 90% points on the R/B# waveform, the rise time is approximately two time constants (TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 21 (page 27).
The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and V CC.
V (MAX) - VOL (MAX)
Rp = CC
IOL + ΣIL
Where ΣIL is the sum of the input currents of all devices tied to the R/B# pin.
Figure 16: READ/BUSY# Open Drain
Rp
VCC
R/B#
Open drain output
IOL
VSS
Device
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Figure 17: tFall and tRise (3.3V VCC)
3.50
3.00
2.50
V
tFall tRise
2.00
1.50
1.00
0.50
0.00
–1
0
2
4
0
2
4
TC
Notes:
6
VCC 3.3V
1. tFall and tRise calculated at 10% and 90% points.
2. tRise dependent on external capacitance and resistive loading and output transistor impedance.
3. tRise primarily dependent on external pull-up resistor and external capacitive loading.
4. tFall = 10ns at 3.3V.
5. See TC values in Figure 21 (page 27) for approximate Rp value and TC.
Figure 18: tFall and tRise (1.8V VCC)
3.50
3.00
2.50
V
tFall
2.00
tRise
1.50
1.00
0.50
0.00
-1
0
2
4
0
TC
Notes:
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1.
2.
3.
4.
2
4
6
VCC1.8V
tFall
and tRise are calculated at 10% and 90% points.
is primarily dependent on external pull-up resistor and external capacitive loading.
tFall ≈ 7ns at 1.8V.
See TC values in Figure 21 (page 27) for TC and approximate Rp value.
tRise
25
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Figure 19: IOL vs. Rp (VCC = 3.3V VCC)
3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0
2000
400 0
6000
8000
10,000
12,000
Rp (Ω)
IOL at VCC (MAX)
Figure 20: IOL vs. Rp (1.8V VCC)
3.50
3.00
2.50
2.00
I (mA)
1.50
1.00
0.50
0.00
0
2000
4000
6000
8000
10,000
12,000
Rp (Ω)
IOL at VCC (MAX)
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Bus Operation
Figure 21: TC vs. Rp
1200
1000
800
T(ns)
600
400
200
0
0
2000
4000
6000
8000
Rp (Ω)
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27
10,000
12,000
IOL at VCC (MAX)
RC = TC
C = 100pF
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Preliminary
1Gb x8, x16: NAND Flash Memory
Device Initialization
Device Initialization
Micron NAND Flash devices are designed to prevent data corruption during power
transitions. V CC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping V CC, use the following procedure
to initialize the device:
1. Ramp V CC.
2. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target. The R/B# signal becomes valid when 50µs has elapsed since the beginning the V CC ramp, and 10µs has elapsed since V CC reaches V CC (MIN).
3. If not monitoring R/B#, the host must wait at least 100µs after V CC reaches V CC
(MIN). If monitoring R/B#, the host must wait until R/B# is HIGH.
4. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of 10mA (IST) measured over intervals of 1ms until the RESET
(FFh) command is issued.
5. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for 1ms after a
RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
6. The device is now initialized and ready for normal operation.
Figure 22: R/B# Power-On Behavior
50µs (MIN)
VCC
VCC = VCC (MIN)
10µs
(MAX)
R/B#
100µs (MAX)
VCC ramp
starts
Reset (FFh)
is issued
Invalid
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Preliminary
1Gb x8, x16: NAND Flash Memory
Command Definitions
Command Definitions
Table 5: Command Set
Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
Command
Cycle #2
Valid While
Selected LUN is
Busy1
FFh
0
–
–
Yes
READ ID
90h
1
–
–
No
READ PARAMETER PAGE
ECh
1
–
–
No
READ UNIQUE ID
EDh
1
–
–
No
GET FEATURES
EEh
1
–
–
No
SET FEATURES
EFh
1
4
–
No
70h
0
–
–
Yes
RANDOM DATA READ
05h
2
–
E0h
No
RANDOM DATA INPUT
85h
2
Optional
–
No
PROGRAM FOR
INTERNAL DATA MOVE
85h
4
Optional
–
No
READ MODE
00h
0
–
–
No
READ PAGE
00h
4
–
30h
No
READ PAGE CACHE SEQUENTIAL
31h
0
–
–
No
4
READ PAGE CACHE
RANDOM
00h
4
–
31h
No
4
READ PAGE CACHE LAST
3Fh
0
–
–
No
4
PROGRAM PAGE
80h
4
Yes
10h
No
PROGRAM PAGE CACHE
80h
4
Yes
15h
No
60h
2
–
D0h
No
READ FOR INTERNAL
DATA MOVE
00h
4
–
35h
No
2
PROGRAM FOR INTERNAL
DATA MOVE
85h
Optional
10h
No
3
Command
Notes
Reset Operations
RESET
Identification Operation
Feature Operations
Status Operations
READ STATUS
Column Address Operations
2, 3
READ OPERATIONS
Program Operations
5
Erase Operations
ERASE BLOCK
Internal Data Move Operations
Block Lock Operations
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Preliminary
1Gb x8, x16: NAND Flash Memory
Command Definitions
Table 5: Command Set (Continued)
Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
Command
Cycle #2
Valid While
Selected LUN is
Busy1
BLOCK UNLOCK LOW
23h
2
–
–
No
BLOCK UNLOCK HIGH
24h
2
–
–
No
BLOCK LOCK
2Ah
–
–
–
No
Command
BLOCK LOCK-TIGHT
2Ch
–
–
–
No
BLOCK LOCK READ
STATUS
7Ah
2
–
–
No
Notes
One-Time Programmable (OTP) Operations
OTP DATA LOCK BY PAGE
(ONFI)
80h
4
No
10h
No
6
OTP DATA PROGRAM (ONFI)
80h
4
Yes
10h
No
6
OTP DATA READ (ONFI)
00h
4
No
30h
No
6
Notes:
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1. Busy means RDY = 0.
2. Do not cross plane address boundaries when using READ FOR INTERNAL DATA MOVE
and PROGRAM FOR INTERNAL DATA MOVE.
3. PROGRAM FOR INTERNAL DATA MOVE operation is prohibited between even and odd
blocks.
4. Issuing a READ PAGE CACHE series (31h, 00h-31h, 3Fh) command when the array is busy
(RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE (00h-30h)
or READ PAGE CACHE series command; otherwise, it is prohibited.
5. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
6. OTP commands can be entered only after issuing the SET FEATURES command with the
feature address.
30
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Preliminary
1Gb x8, x16: NAND Flash Memory
Reset Operations
Reset Operations
RESET (FFh)
The RESET command is used to put the memory device into a known condition and to
abort the command sequence in progress.
READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy
state. The contents of the memory location being programmed or the block being
erased are no longer valid. The data may be partially erased or programmed, and is invalid. The command register is cleared and is ready for the next command. The data
register and cache register contents are marked invalid.
The status register contains the value E0h when WP# is HIGH; otherwise it is written
with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the
command register.
The RESET command must be issued to all CE#s as the first command after power-on.
The device will be busy for a maximum of 1ms.
Figure 23: RESET (FFh) Operation
Cycle type
I/O[7:0]
Command
FF
tWB
tRST
R/B#
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Preliminary
1Gb x8, x16: NAND Flash Memory
Identification Operations
Identification Operations
READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the target. This command is accepted by the target only when all die (LUNs) on the target are
idle.
Writing 90h to the command register puts the target in read ID mode. The target stays in
this mode until another valid command is issued.
When the 90h command is followed by an 00h address cycle, the target returns a 5-byte
identifier code that includes the manufacturer ID, device configuration, and part-specific information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte
ONFI identifier code.
Figure 24: READ ID (90h) with 00h Address Operation
Cycle type
Command
Address
DOUT
DOUT
DOUT
DOUT
DOUT
Byte 0
Byte 1
Byte 2
Byte 3
Byte 4
tWHR
I/O[7:0]
Note:
90h
00h
1. See the READ ID Parameter tables for byte definitions.
Figure 25: READ ID (90h) with 20h Address Operation
Cycle type
Command
Address
DOUT
DOUT
DOUT
DOUT
4Fh
4Eh
46h
49h
tWHR
I/O[7:0]
Note:
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90h
20h
1. See READ ID Parameter tables for byte definitions.
32
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Preliminary
1Gb x8, x16: NAND Flash Memory
READ ID Parameter Tables
READ ID Parameter Tables
Table 6: READ ID Parameters for Address 00h
b = binary; h = hexadecimal
Options
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
Value
Micron
0
0
1
0
1
1
0
0
2Ch
MT29F1G08ABAEA
1Gb, x8, 3.3V
1
1
1
1
0
0
0
1
F1h
MT29F1G08ABBEA
1Gb, x8, 1.8V
1
0
1
0
0
0
0
1
A1h
MT29F1G16ABBEA
1Gb, x16, 1.8V
1
0
1
1
0
0
0
1
B1h
0
0
00b
Byte 0 – Manufacturer ID
Manufacturer
Byte 1 – Device ID
Byte 2
Number of die per CE
1
Cell type
SLC
Number of simultaneously
programmed pages
1
Interleaved operations between multiple die
Not supported
Cache programming
Supported
1
Byte value
MT29F1G08ABAEA
1
0
0
0
0
0
0
0
80h
MT29F1G08ABBEA
1
0
0
0
0
0
0
0
80h
MT29F1G16ABBEA
1
0
0
0
0
0
0
0
80h
0
1
01b
0
0
0
00b
0
00b
0
0b
1b
Byte 3
Page size
2KB
Spare area size (bytes)
64B
Block size (without spare)
128KB
Organization
x8
1
0
Byte value
1
01b
0
x16
Serial access
(MIN)
1b
0b
1
1b
1.8V
25ns
0
0
0xxx0b
3.3V
20ns
1
0
1xxx0b
MT29F1G08ABAEA
1
0
0
1
0
1
0
1
95h
MT29F1G08ABBEA
0
0
0
1
0
1
0
1
15h
MT29F1G16ABBEA
0
1
0
1
0
1
0
1
55h
0
0
00b
Byte 4
Reserved
Planes per CE#
1
Plane size
Reserved
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2
0
512Mb
0
0
0
0
1
01b
000b
0b
33
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Preliminary
1Gb x8, x16: NAND Flash Memory
READ ID Parameter Tables
Table 6: READ ID Parameters for Address 00h (Continued)
b = binary; h = hexadecimal
Options
Byte value
Note:
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
Value
MT29F1G08ABAEA
0
0
0
0
0
1
0
0
04h
MT29F1G08ABBEA
0
0
0
0
0
1
0
0
04h
MT29F1G16ABBEA
0
0
0
0
0
1
0
0
04h
1. Only single-plane operations are supported.
Table 7: READ ID Parameters for Address 20h
h = hexadecimal
Byte
Options
I/07
I/06
I/05
I/04
I/03
I/02
I/01
I/00
Value
0
“O”
0
1
0
0
1
1
1
1
4Fh
1
“N”
0
1
0
0
1
1
1
0
4Eh
2
“F”
0
1
0
0
0
1
1
0
46h
3
“I”
0
1
0
0
1
0
0
1
49h
4
Undefined
X
X
X
X
X
X
X
X
XXh
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Preliminary
1Gb x8, x16: NAND Flash Memory
READ PARAMETER PAGE (ECh)
READ PARAMETER PAGE (ECh)
The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page
programmed into the target. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing ECh to the command register puts the target in read parameter page mode. The
target stays in this mode until another valid command is issued.
When the ECh command is followed by an 00h address cycle, the target goes busy for tR.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode.
A minimum of three copies of the parameter page are stored in the device. Each parameter page is 256 bytes. If desired, the RANDOM DATA READ (05h-E0h) command can be
used to change the location of data output.
Figure 26: READ PARAMETER (ECh) Operation
Cycle type
I/O[7:0]
Command
Address
ECh
00h
tWB
tR
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
P00
P10
…
P01
P11
…
tRR
R/B#
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Preliminary
1Gb x8, x16: NAND Flash Memory
Parameter Page Data Structure Tables
Parameter Page Data Structure Tables
Table 8: Parameter Page Data Structure
h = hexadecimal
Byte
Description
Value
0–3
Parameter page signature
4Fh, 4Eh, 46h, 49h
4–5
Revision number
02h, 00h
6–7
Features supported
8–9
MT29F1G08ABAEAWP
10h, 00h
MT29F1G08ABBEAHC
10h, 00h
MT29F1G16ABBEAHC
11h, 00h
MT29F1G08ABBEAH4
10h, 00h
MT29F1G16ABBEAH4
11h, 00h
MT29F1G08ABAEAH4
10h, 00h
MT29F1G08ABAEA3W
10h, 00h
MT29F1G08ABBEA3W
10h, 00h
MT29F1G16ABBEA3W
11h, 00h
Optional commands supported
3Fh, 00h
10–31
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h
32–43
Device manufacturer
4Dh, 49h, 43h, 52h, 4Fh, 4Eh, 20h, 20h, 20h, 20h,
20h, 20h
44–63
Device model
64
MT29F1G08ABAEAWP
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 41h, 45h, 41h, 57h, 50h, 20h, 20h, 20h, 20h
MT29F1G08ABBEAHC
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 42h, 45h, 41h, 48h, 43h, 20h, 20h, 20h, 20h
MT29F1G16ABBEAHC
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,
42h, 42h, 45h, 41h, 48h, 43h, 20h, 20h, 20h, 20h
MT29F1G08ABBEAH4
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 42h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F1G16ABBEAH4
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,
42h, 42h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F1G08ABAEAH4
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 41h, 45h, 41h, 48h, 34h, 20h, 20h, 20h, 20h
MT29F1G08ABAEA3W
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 41h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F1G08ABBEA3W
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 30h, 38h, 41h,
42h, 42h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
MT29F1G16ABBEA3W
4Dh, 54h, 32h, 39h, 46h, 31h, 47h, 31h, 36h, 41h,
42h, 42h, 45h, 41h, 33h, 57h, 20h, 20h, 20h, 20h
Manufacturer ID
2Ch
65–66
Date code
00h, 00h
67–79
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h
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Preliminary
1Gb x8, x16: NAND Flash Memory
Parameter Page Data Structure Tables
Table 8: Parameter Page Data Structure (Continued)
h = hexadecimal
Byte
Description
Value
80–83
Number of data bytes per page
00h, 08h, 00h, 00h
84–85
Number of spare bytes per page
40h, 00h
86–89
Number of data bytes per partial page
00h, 02h, 00h, 00h
90–91
Number of spare bytes per partial page
10h, 00h
92–95
Number of pages per block
40h, 00h, 00h, 00h
96–99
Number of blocks per unit
00h, 04h, 00h, 00h
100
Number of logical units
01h
101
Number of address cycles
22h
102
Number of bits per cell
01h
103–104
Bad blocks maximum per unit
14h, 00h
105–106
Block endurance
01h, 05h
Guaranteed valid blocks at beginning of target
01h
Block endurance for guaranteed valid blocks
00h, 00h
110
Number of programs per page
04h
111
Partial programming attributes
00h
112
Number of bits ECC bits
04h
113
Number of interleaved address bits
00h
114
Interleaved operation attributes
00h
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h
I/O pin capacitance
0Ah
107
108–109
115–127
128
129–130
Timing mode support
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MT29F1G08ABAEAWP
3Fh, 00h
MT29F1G08ABBEAHC
1Fh, 00h
MT29F1G16ABBEAHC
1Fh, 00h
MT29F1G08ABBEAH4
1Fh, 00h
MT29F1G16ABBEAH4
1Fh, 00h
MT29F1G08ABAEAH4
3Fh, 00h
MT29F1G08ABAEA3W
3Fh, 00h
MT29F1G08ABBEA3W
1Fh, 00h
MT29F1G16ABBEA3W
1Fh, 00h
37
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Preliminary
1Gb x8, x16: NAND Flash Memory
Parameter Page Data Structure Tables
Table 8: Parameter Page Data Structure (Continued)
h = hexadecimal
Byte
Description
131–132
Program cache timing
mode support
Value
MT29F1G08ABAEAWP
3Fh, 00h
MT29F1G08ABBEAHC
1Fh, 00h
MT29F1G16ABBEAHC
1Fh, 00h
MT29F1G08ABBEAH4
1Fh, 00h
MT29F1G16ABBEAH4
1Fh, 00h
MT29F1G08ABAEAH4
3Fh, 00h
MT29F1G08ABAEA3W
3Fh, 00h
MT29F1G08ABBEA3W
1Fh, 00h
MT29F1G16ABBEA3W
1Fh, 00h
133–134
tPROG
135–136
tBERS
137–138
tR
139–140
tCCS
141–163
Reserved
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h
(MAX) page program time
58h, 02h
(MAX) block erase time
B8h, 0Bh
(MAX) page read time
19h, 00h
(MIN)
64h, 00h
164–165
Vendor-specific revision number
01h, 00h
166–253
Vendor-specific
01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h,
02h, 01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h,00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h,00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h,00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h,
00h, 00h, 00h, 00h,00h, 00h, 00h, 00h
254–255
Integrity CRC
Set at test
256–511
Value of bytes 0–255
512–767
Value of bytes 0–255
768+
Additional redundant parameter pages
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Preliminary
1Gb x8, x16: NAND Flash Memory
READ UNIQUE ID (EDh)
READ UNIQUE ID (EDh)
The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed
into the target. This command is accepted by the target only when all die (LUNs) on the
target are idle.
Writing EDh to the command register puts the target in read unique ID mode. The target stays in this mode until another valid command is issued.
When the EDh command is followed by an 00h address cycle, the target goes busy for
If the READ STATUS (70h) command is used to monitor for command completion,
the READ MODE (00h) command must be used to re-enable data output mode.
tR.
After tR completes, the host enables data output mode to read the unique ID. When the
asynchronous interface is active, one data byte is output per RE# toggle.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The
first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the complement of the first 16 bytes. The host should XOR the first 16 bytes with the second 16
bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In
the event that a non-FFh result is returned, the host can repeat the XOR operation on a
subsequent copy of the unique ID data. If desired, the RANDOM DATA READ (05h-E0h)
command can be used to change the data output location.
The upper eight I/Os on a x16 device are not used and are a “Don’t Care” for x16 devices.
Figure 27: READ UNIQUE ID (EDh) Operation
Cycle type
I/O[7:0]
Command
Address
EDh
00h
tWB
tR
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
U00
U10
…
U01
U11
…
tRR
R/B#
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Preliminary
1Gb x8, x16: NAND Flash Memory
Feature Operations
Feature Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the
target's default power-on behavior. These commands use a one-byte feature address to
determine which subfeature parameters will be read or modified. Each feature address
(in the 00h to FFh range) is defined below. The SET FEATURES (EFh) command writes
subfeature parameters (P1–P4) to the specified feature address. The GET FEATURES
command reads the subfeature parameters (P1–P4) at the specified feature address.
When a feature is set, by default it remains active until the device is power cycled. It is
volatile. Unless otherwise specified in the features table, once a device is set it remains
set, even if a RESET (FFh) command is issued. GET/SET FEATURES commands can be
used after required RESET to enable features before system BOOT ROM process.
Table 9: Feature Address Definitions
Feature Address
00h
Reserved
01h
Timing mode
02h–7Fh
Reserved
80h
Programmable output drive strength
81h
Programmable RB# pull-down strength
82h–FFh
90h
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Definition
Reserved
Array operation mode
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1Gb x8, x16: NAND Flash Memory
Feature Operations
Table 10: Feature Address 90h – Array Operation Mode
Subfeature
Parameter
Options
1/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
1
P1
Operation
mode option
Normal
Reserved (0)
0
00h
OTP
operation
Reserved (0)
1
01h
1
03h
OTP
protection
Reserved (0)
1
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P2
Reserved
P3
Reserved
P4
Reserved
1. These bits are reset to 00h on power cycle.
Note:
SET FEATURES (EFh)
The SET FEATURES (EFh) command writes the subfeature parameters (P1–P4) to the
specified feature address to enable or disable target-specific features. This command is
accepted by the target only when all die (LUNs) on the target are idle.
Writing EFh to the command register puts the target in the set features mode. The target
stays in this mode until another command is issued.
The EFh command is followed by a valid feature address. The host waits for tADL before
the subfeature parameters are input. When the asynchronous interface is active, one
subfeature parameter is latched per rising edge of WE#.
After all four subfeature parameters are input, the target goes busy for tFEAT. The READ
STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to
modify the interface type, the target will be busy for tITC.
Figure 28: SET FEATURES (EFh) Operation
Cycle type
Command
Address
DIN
DIN
DIN
DIN
P1
P2
P3
P4
tADL
I/O[7:0]
EFh
FA
tWB
tFEAT
R/B#
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Preliminary
1Gb x8, x16: NAND Flash Memory
Feature Operations
GET FEATURES (EEh)
The GET FEATURES (EEh) command reads the subfeature parameters (P1–P4) from the
specified feature address. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing EEh to the command register puts the target in get features mode. The target
stays in this mode until another valid command is issued.
When the EEh command is followed by a feature address, the target goes busy for tFEAT.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode.
After tFEAT completes, the host enables data output mode to read the subfeature parameters.
Figure 29: GET FEATURES (EEh) Operation
Cycle type
I/Ox
Command
Address
EEh
FA
tWB
tFEAT
DOUT
DOUT
DOUT
DOUT
P1
P2
P3
P4
tRR
R/B#
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Preliminary
1Gb x8, x16: NAND Flash Memory
Feature Operations
Table 11: Feature Addresses 01h: Timing Mode
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
P1
Timing mode
Mode 0
(default)
Reserved (0)
0
0
0
00h
1, 2
Mode 1
Reserved (0)
0
0
1
01h
2
Mode 2
Reserved (0)
0
1
0
02h
2
Mode 3
Reserved (0)
0
1
1
03h
3
Mode 4
Reserved (0)
1
0
0
04h
3
Mode 5
Reserved (0)
1
0
1
05h
4
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Notes:
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1. The timing mode feature address is used to change the default timing mode. The timing
mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. The five supported settings for the timing
mode are shown. The default timing mode is mode 0. The device returns to mode 0
when the device is power cycled. Supported timing modes are reported in the parameter page.
2. Supported for both 1.8V and 3.3V.
3. Supported for 3.3V only.
4. Not supported.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Feature Operations
Table 12: Feature Addresses 80h: Programmable I/O Drive Strength
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
1
P1
I/O drive strength
Full (default)
Reserved (0)
0
0
00h
Three-quarters
Reserved (0)
0
1
01h
One-half
Reserved (0)
1
0
02h
One-quarter
Reserved (0)
1
1
03h
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Note:
1. The programmable drive strength feature address is used to change the default I/O
drive strength. Drive strength should be selected based on expected loading of the
memory bus. This table shows the four supported output drive strength settings. The
default drive strength is full strength. The device returns to the default drive strength
mode when the device is power cycled. AC timing parameters may need to be relaxed if
I/O drive strength is not set to full.
Table 13: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
Subfeature
Parameter
Options
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
Value
Notes
Full (default)
0
0
00h
1
Three-quarters
0
1
01h
One-half
1
0
02h
One-quarter
1
1
03h
P1
R/B# pull-down
strength
P2
Reserved (0)
00h
Reserved (0)
00h
Reserved (0)
00h
P3
P4
Note:
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1. This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
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1Gb x8, x16: NAND Flash Memory
Status Operations
Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target
through its 8-bit status register.
After the READ STATUS (70h) command is issued, status register output is enabled. The
contents of the status register are returned on I/O[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on I/O[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see Read Operations).
Table 14: Status Register Definition
SR
Bit
Program
Page
Program Page
Cache Mode
Page Read
Page Read
Cache Mode
7
Write protect
Write protect
Write protect
Write protect
6
RDY
RDY1 cache
RDY
RDY1 cache
RDY
0 = Busy
1 = Ready
5
ARDY
ARDY2
ARDY
ARDY2
ARDY
Don't Care
4
–
–
–
–
–
Don't Care
3
–
–
–
–
–
Don't Care
Block Erase
Description
Write protect 0 = Protected
1 = Not protected
2
–
–
–
–
–
Don't Care
1
FAILC (N - 1)
FAILC (N - 1)
Reserved
–
–
Don't Care
0
FAIL
FAIL (N)
–
–
FAIL
Notes:
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0 = Successful PROGRAM/
ERASE
1 = Error in PROGRAM/
ERASE
1. Status register bit 6 is 1 when the cache is ready to accept new data. R/B# follows bit 6.
2. Status register bit 5 is 0 during the actual programming operation. If cache mode is
used, this bit will be 1 when all internal operations are complete.
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1Gb x8, x16: NAND Flash Memory
Status Operations
READ STATUS (70h)
The READ STATUS (70h) command returns the status of the last-selected die (LUN) on
a target. This command is accepted by the last-selected die (LUN) even when it is busy
(RDY = 0).
If there is only one die (LUN) per target, the READ STATUS (70h) command can be used
to return status following any NAND command.
Figure 30: READ STATUS (70h) Operation
Cycle type
Command
DOUT
tWHR
I/O[7:0]
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70h
SR
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1Gb x8, x16: NAND Flash Memory
Column Address Operations
Column Address Operations
The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for managing data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
RANDOM DATA READ (05h-E0h)
The RANDOM DATA READ (05h-E0h) command changes the column address of the selected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containing
the column address, followed by the E0h command, puts the selected die (LUN) into
data output mode. After the E0h command cycle is issued, the host must wait at least
tWHR before requesting data output. The selected die (LUN) stays in data output mode
until another valid command is issued.
Figure 31: RANDOM DATA READ (05h-E0h) Operation
Cycle type
DOUT
DOUT
Command
Address
Address
Command
tRHW
I/O[7:0]
Dn
Dn + 1
DOUT
DOUT
DOUT
Dk
Dk + 1
Dk + 2
tWHR
05h
C1
C2
E0h
SR[6]
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Preliminary
1Gb x8, x16: NAND Flash Memory
Column Address Operations
RANDOM DATA INPUT (85h)
The RANDOM DATA INPUT (85h) command changes the column address of the selected cache register and enables data input on the last-selected die (LUN). This command
is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing
the column address, puts the selected die (LUN) into data input mode. After the second
address cycle is issued, the host must wait at least tADL before inputting data. The selected die (LUN) stays in data input mode until another valid command is issued.
Though data input mode is enabled, data input from the host is optional. Data input
begins at the column address specified.
The RANDOM DATA INPUT (85h) command is allowed after the required address cycles
are specified, but prior to the final command cycle (10h, 11h, 15h) of the following commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
CACHE (80h-15h), and PROGRAM FOR INTERNAL DATA MOVE (85h-10h).
Figure 32: RANDOM DATA INPUT (85h) Operation
As defined for PAGE
(CACHE) PROGRAM
Cycle type
DIN
DIN
As defined for PAGE
(CACHE) PROGRAM
Command
Address
Address
DIN
DIN
DIN
Dk
Dk + 1
Dk + 2
tADL
I/O[7:0]
Dn
Dn + 1
85h
C1
C2
RDY
PROGRAM FOR INTERNAL DATA INPUT (85h)
The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address
(block and page) where the cache register contents will be programmed in the NAND
Flash array. It also changes the column address of the selected cache register and enables data input on the specified die (LUN). This command is accepted by the selected
die (LUN) when it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die
(LUN) during cache programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and three
row address cycles. This updates the page and block destination of the selected device
for the addressed LUN and puts the cache register into data input mode. After the fifth
address cycle is issued the host must wait at least tADL before inputting data. The selected LUN stays in data input mode until another valid command is issued. Though data
input mode is enabled, data input from the host is optional. Data input begins at the
column address specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command is allowed after the required address cycles are specified, but prior to the final command cycle (10h, 11h, 15h)
of the following commands while data input is permitted: PROGRAM PAGE (80h-10h),
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1Gb x8, x16: NAND Flash Memory
Column Address Operations
PROGRAM PAGE CACHE (80h-15h), and PROGRAM FOR INTERNAL DATA MOVE
(85h-10h). When used with these commands, the LUN address and plane select bits are
required to be identical to the LUN address and plane select bits originally specified.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command enables the host to modify the original page and block address for the data in the cache register to a new page
and block address.
In devices that have more than one die (LUN) per target, the PROGRAM FOR INTERNAL
DATA INPUT (85h) command can be used with other commands that support interleaved die (multi-LUN) operations.
The PROGRAM FOR INTERNAL DATA INPUT (85h) command can be used with the
RANDOM DATA READ (05h-E0h) command to read and modify cache register contents
in small sections prior to programming cache register contents to the NAND Flash array. This capability can reduce the amount of buffer memory used in the host controller.
The RANDOM DATA INPUT (85h) command can be used during the PROGRAM FOR
INTERNAL DATA MOVE command sequence to modify one or more bytes of the original data. First, data is copied into the cache register using the 00h-35h command sequence, then the RANDOM DATA INPUT (85h) command is written along with the address of the data to be modified next. New data is input on the external data pins. This
copies the new data into the cache register.
Figure 33: PROGRAM FOR INTERNAL DATA INPUT (85h) Operation
Cycle type
DIN
DIN
Command
Address
Address
Address
Address
Command
DIN
DIN
DIN
Dk
Dk + 1
Dk + 2
tADL
I/O[7:0]
Dn
Dn + 1
85h
C1
C2
R1
R2
10h
RDY
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Preliminary
1Gb x8, x16: NAND Flash Memory
Read Operations
Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data in
the cache registers: RANDOM DATA READ (05h-E0h) and RANDOM DATA INPUT (85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
• READ PAGE CACHE SEQUENTIAL (31h) – copies the next sequential page from the
NAND Flash array to the data register
• READ PAGE CACHE RANDOM (00h-31h) – copies the page specified in this command
from the NAND Flash array to its corresponding data register
After the READ PAGE CACHE series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next page begins copying data from the array to the data register. After tRCBSY,
R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data register. At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an additional READ PAGE CACHE series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied
into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
RANDOM DATA READ (05h-E0h) command can be used to change the column address
of the data being output.
For READ PAGE CACHE series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h) and RESET (FFh). When RDY = 1 and ARDY = 0, the only valid commands during
READ PAGE CACHE series (31h, 00h-31h) operations are status operations (70h), READ
MODE (00h), READ PAGE CACHE series (31h, 00h-31h), RANDOM DATA READ (05hE0h), and RESET (FFh).
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1Gb x8, x16: NAND Flash Memory
Read Operations
READ MODE (00h)
The READ MODE (00h) command disables status output and enables data output for
the last-selected die (LUN) and cache register after a READ operation (00h-30h,
00h-3Ah, 00h-35h) has been monitored with a status operation (70h). This command is
accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the
die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
READ PAGE (00h-30h)
The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its
respective cache register and enables data output. This command is accepted by the die
(LUN) when it is ready (RDY = 1, ARDY = 1).
To read a page from the NAND Flash array, write the 00h command to the command
register, then write n address cycles to the address registers, and conclude with the 30h
command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is
transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h) can be used. If the status operations
are used to monitor the LUN's status, when the die (LUN) is ready
(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing
the READ MODE (00h) command. When the host requests data output, output begins
at the column address specified.
During data output the RANDOM DATA READ (05h-E0h) command can be issued.
Figure 34: READ PAGE (00h-30h) Operation
Cycle type
I/O[7:0]
Command
Address
Address
Address
Address
Command
DOUT
00h
C1
C2
R1
R2
30h
Dn
tWB
tR
DOUT
DOUT
Dn + 1 Dn + 2
tRR
RDY
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1Gb x8, x16: NAND Flash Memory
Read Operations
READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page
within a block into the data register while the previous page is output from the cache
register. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE
(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After
tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point, data can
be output from the cache register beginning at column address 0. The RANDOM DATA
READ (05h-E0h) command can be used to change the column address of the data being
output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block
boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the
last page of a block is read into the data register, the next page read will be the next logical block in which the 31h command was issued. Do not issue the READ PAGE CACHE
SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ PAGE
CACHE LAST (3Fh) command.
Figure 35: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle type
I/O[7:0]
Command
Address x4
Command
00h
Page Address M
30h
tWB
Command
31h
tR
RR
tWB
tRCBSY
DOUT
DOUT
DOUT
Command
D0
…
Dn
31h
tWB
tRR
DOUT
D0
tRCBSY
tRR
RDY
Page M
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Preliminary
1Gb x8, x16: NAND Flash Memory
Read Operations
READ PAGE CACHE RANDOM (00h-31h)
The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and
page into the data register while the previous page is output from the cache register.
This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is
also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write n address cycles
to the address register, and conclude by writing 31h to the command register. The column address in the address specified is ignored. The die (LUN) address must match the
same die (LUN) address as the previous READ PAGE (00h-30h) command or, if applicable, the previous READ PAGE CACHE RANDOM (00h-31h) command.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy
with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register.
Figure 36: READ PAGE CACHE RANDOM (00h-31h) Operation
Cycle type
I/O[7:0]
Command
Address x4
Command
00h
Page Address M
30h
tWB
Command
Address x4
Command
00h
Page Address N
31h
tRR
tR
tWB
tRCBSY
DOUT
DOUT
DOUT
Command
D0
…
Dn
00h
tRR
RDY
Page M
1
Cycle type
I/O[7:0]
DOUT
Command
Address x4
Command
Dn
00h
Page Address P
31h
tWB
DOUT
D0
tRCBSY
tRR
RDY
Page N
1
READ PAGE CACHE LAST (3Fh)
The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and
copies a page from the data register to the cache register. This command is accepted by
the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN)
during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command register. After this command is issued, R/B# goes LOW and the die (LUN) is busy
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Preliminary
1Gb x8, x16: NAND Flash Memory
Read Operations
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is
ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be
used to change the column address of the data being output from the cache register.
Figure 37: READ PAGE CACHE LAST (3Fh) Operation
As defined for
READ PAGE CACHE
(SEQUENTIAL OR RANDOM)
Cycle type
I/O[7:0]
Command
31h
tWB
tRCBSY
DOUT
DOUT
DOUT
Command
D0
…
Dn
3Fh
tRR
tWB
tRCBSY
DOUT
DOUT
DOUT
D0
…
Dn
tRR
RDY
Page Address N
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1Gb x8, x16: NAND Flash Memory
Program Operations
Program Operations
Program operations are used to move data from the cache or data registers to the NAND
array. During a program operation the contents of the cache and/or data registers are
modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page
address to the most significant page address (0, 1, 2, ….., 63). During a program operation, the contents of the cache and/or data registers are modified by the internal control
logic.
Program Operations
The PROGRAM PAGE (80h-10h) command programs one page from the cache register
to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host
should check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program operation system performance. When this command is issued, the die (LUN) goes busy
(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,
and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0. While
the contents of the data register are moved to the NAND Flash array, the cache register
is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE
(80h-10h) command.
For PROGRAM PAGE CACHE series (80h-15h) operations, during the die (LUN) busy
times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are
status operation (70h) and reset (FFh). When RDY = 1 and ARDY = 0, the only valid commands during PROGRAM PAGE CACHE series (80h-15h) operations are status operation (70h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h), RANDOM
DATA INPUT (85h), PROGRAM FOR INTERNAL DATA INPUT (85h), and RESET (FFh).
PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache register, and moves the data from the cache register to the specified block and page address in the array of the selected die (LUN). This command is accepted by the die (LUN)
when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy
with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and
page address specified, write 80h to the command register. Issuing the 80h to the command register clears all of the cache registers' contents on the selected target. Write n
address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during
the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL
DATA INPUT (85h) commands may be issued. When data input is complete, write 10h
to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operation (70h) may be used. When the die (LUN) is
ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Program Operations
Figure 38: PROGRAM PAGE (80h-10h) Operaton
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
…
Dn
10h
Command
DOUT
70h
Status
tADL
I/O[7:0]
80h
C1
C2
R1
R2
tWB
tPROG
RDY
PROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the selected die (LUN). After the data is copied to the data register, the cache register is available for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Issuing the 80h to the command
register clears all of the cache registers' contents on the selected target. Then write n
address cycles containing the column address and row address. Data input cycles follow. Serial data is input beginning at the column address specified. At any time during
the data input cycle the RANDOM DATA INPUT (85h) and PROGRAM FOR INTERNAL
DATA INPUT (85h) commands may be issued. When data input is complete, write 15h
to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a previous program cache operation, to copy data from the cache register to the data register,
and then to begin moving the data register contents to the specified page and block address.
To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, alternatively, the status operation (70h) can be used. When the LUN’s status shows that it
is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should check
the status of the FAILC bit to see if a previous cache operation was successful.
If, after tCBSY, the host wants to wait for the program cache operation to complete,
without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor ARDY until it is 1. The host should then check the status of the FAIL and FAILC bits.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Program Operations
Figure 39: PROGRAM PAGE CACHE (80h-15h) Operation (Start)
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
…
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
tWB
tCBSY
RDY
1
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
…
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
tWB
tCBSY
RDY
1
Figure 40: PROGRAM PAGE CACHE (80h-15h) Operation (End)
As defined for
PAGE CACHE PROGRAM
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
…
Dn
15h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
tWB
tCBSY
RDY
1
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
DIN
DIN
Command
D0
D1
…
Dn
10h
tADL
I/O[7:0]
80h
C1
C2
R1
R2
tWB
tLPROG
RDY
1
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Preliminary
1Gb x8, x16: NAND Flash Memory
Erase Operations
Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to
prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command erases one block in the NAND Flash array.
When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to
verify that this operation completed successfully.
ERASE BLOCK (60h-D0h)
The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash
array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To erase a block, write 60h to the command register. Then write two address cycles containing the row address; the page address is ignored. Conclude by writing D0h to the
command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS
while the block is erased.
To determine the progress of an ERASE operation, the host can monitor the target's
R/B# signal, or alternatively, the status operation (70h) can be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.
Figure 41: ERASE BLOCK (60h-D0h) Operation
Cycle type
I/O[7:0]
Command
Address
Address
Command
60h
R1
R2
D0h
tWB
tBERS
RDY
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Preliminary
1Gb x8, x16: NAND Flash Memory
Internal Data Move Operations
Internal Data Move Operations
Internal data move operations make it possible to transfer data within a device from
one page to another using the cache register. This is particularly useful for block management and wear leveling. The INTERNAL DATA MOVE operation is restricted to only
within even blocks or only within odd blocks.
The INTERNAL DATA MOVE operation is a two-step process consisting of a READ FOR
INTERNAL DATA MOVE (00h-35h) and a PROGRAM FOR INTERNAL DATA MOVE
(85h-10h) command. To move data from one page to another, first issue the READ FOR
INTERNAL DATA MOVE (00h-35h) command. When the die (LUN) is ready (RDY = 1,
ARDY = 1), the host can transfer the data to a new page by issuing the PROGRAM FOR
INTERNAL DATA MOVE (85h-10h) command. When the die (LUN) is again ready (RDY
= 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully.
To prevent bit errors from accumulating over multiple INTERNAL DATA MOVE operations, it is recommended that the host read the data out of the cache register after the
READ FOR INTERNAL DATA MOVE (00h-35h) completes and prior to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command. The RANDOM DATA READ
(05h-E0h) command can be used to change the column address. The host should check
the data for ECC errors and correct them. When the PROGRAM FOR INTERNAL DATA
MOVE (85h-10h) command is issued, any corrected data can be input. The PROGRAM
FOR INTERNAL DATA INPUT (85h) command can be used to change the column address.
Between the READ FOR INTERNAL DATA MOVE (00h-35h) and PROGRAM FOR INTERNAL DATA MOVE (85h-10h) commands, the following commands are supported: status
operation (70h) and column address operations (05h-E0h, 85h). The RESET operation
(FFh) can be issued after READ FOR INTERNAL DATA MOVE (00h-35h), but the contents of the cache registers on the target are not valid.
READ FOR INTERNAL DATA MOVE (00h-35h)
The READ FOR INTERNAL DATA MOVE (00h-35h) command is functionally identical to
the READ PAGE (00h-30h) command, except that 35h is written to the command register instead of 30h.
It is recommended that the host read the data out of the device to verify the data prior
to issuing the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command to prevent
the propagation of data errors.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Internal Data Move Operations
Figure 42: READ FOR INTERNAL DATA MOVE (00h-35h) Operation
Cycle type
Command Address
I/O[7:0]
00h
Address
Address
Address
Address
Command
DOUT
C2
R1
R2
35h
Dn
C1
tWB
tR
DOUT
DOUT
Dn + 1 Dn + 2
tRR
RDY
Figure 43: READ FOR INTERNAL DATA MOVE (00h-35h) with RANDOM DATA READ (05h-E0h)
Cycle type
Command
Address
Address
Address
Address
Command
DOUT
DOUT
DOUT
00h
C1
C2
R1
R2
35h
D0
…
Dj + n
I/O[7:0]
tWB
tR
tRR
RDY
1
Cycle type
Command
Address
Address
Command
DOUT
DOUT
DOUT
Dk
Dk + 1
Dk + 2
tWHR
I/O[7:0]
05h
C1
C2
E0h
RDY
1
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Preliminary
1Gb x8, x16: NAND Flash Memory
Internal Data Move Operations
PROGRAM FOR INTERNAL DATA MOVE (85h-10h)
The PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command is functionally identical to the PROGRAM PAGE (80h-10h) command, except that when 85h is written to the
command register, cache register contents are not cleared.
Figure 44: PROGRAM FOR INTERNAL DATA MOVE (85h-10h)
Cycle type
Command
Address
Address
Address
Address
Command
85h
C1
C2
R1
R2
10h
I/O[7:0]
tWB
tPROG
RDY
Figure 45: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h)
Cycle type
Command
Address
Address
Address
Address
DIN
DIN
Di
Di + 1
tWHR
I/O[7:0]
85h
C1
C2
R1
R2
RDY
1
Cycle type
Command
Address
Address
DIN
DIN
DIN
Command
Dj
Dj + 1
Dj + 2
10h
tWHR
I/O[7:0]
85h
C1
C2
tWB
tPROG
RDY
1
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
Block Lock Feature
The block lock feature protects either the entire device or ranges of blocks from being
programmed and erased. Using the block lock feature is preferable to using WP# to prevent PROGRAM and ERASE operations.
Block lock is enabled and disabled at power-on through the LOCK pin. At power-on, if
LOCK is LOW, all BLOCK LOCK commands are disabled. However if LOCK is HIGH at
power-on, the BLOCK LOCK commands are enabled and, by default, all the blocks on
the device are protected, or locked, from PROGRAM and ERASE operations, even if WP#
is HIGH.
Before the contents of the device can be modified, the device must first be unlocked.
Either a range of blocks or the entire device may be unlocked. PROGRAM and ERASE
operations complete successfully only in the block ranges that have been unlocked.
Blocks, once unlocked, can be locked again to protect them from further PROGRAM
and ERASE operations.
Blocks that are locked can be protected further, or locked tight. When locked tight, the
device’s blocks can no longer be locked or unlocked until the device is power cycled.
WP# and Block Lock
The following is true when the block lock feature is enabled:
• Holding WP# LOW locks all blocks, provided the blocks are not locked tight.
• If WP# is held LOW to lock blocks, then returned to HIGH, a new UNLOCK command
must be issued to unlock blocks.
UNLOCK (23h-24h)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from
PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a
range of blocks. Unlocked blocks have no protection and can be programmed or erased.
The UNLOCK command uses two registers, a lower boundary block address register and
an upper boundary block address register, and the invert area bit to determine what
range of blocks are unlocked. When the invert area bit = 0, the range of blocks within
the lower and upper boundary address registers are unlocked. When the invert area bit
= 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the
upper boundary block address. The figures below show examples of how the lower and
upper boundary address registers work with the invert area bit.
To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate address cycles that indicate the lower boundary block address. Then issue the
24h command followed by the appropriate address cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to 1 if setting the invert area bit; otherwise, it should be 0. The other page address bits should be
0.
Only one range of blocks can be specified in the lower and upper boundary block address registers. If after unlocking a range of blocks the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous
unlocked block address range is not retained.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
Figure 46: Flash Array Protected: Invert Area Bit = 0
Block 1023
Block 1022
Block 1021
Block 1020
Block 1019
Block 1018
Block 1017
Block 1016
Block. 1015
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
Protected
area
3FCh
Upper block boundary
3F8h
Lower block boundary
Unprotected
area
Protected
area
Figure 47: Flash Array Protected: Invert Area Bit = 1
Block 1023
Block 1022
Block 1021
Block 1020
Block 1019
Block 1018
Block 1017
Block 1016
Block. 1015
..
..
..
..
..
..
.
Block 0002
Block 0001
Block 0000
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Unprotected
Area
3FCh
Upper block boundary
3F8h
Lower block boundary
Protected
area
Unprotected
area
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
Table 15: Block Lock Address Cycle Assignments
I/O[15:8]1
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
First
LOW
BA7
BA6
LOW
LOW
LOW
LOW
LOW
Invert area bit2
Second
LOW
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
ALE Cycle
Notes:
1. I/O[15:8] is applicable only for x16 devices.
2. Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command.
Figure 48: UNLOCK Operation
CLE
CE#
WE#
ALE
RE#
I/Ox
23h
UNLOCK
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Block
add 1
Block
add 2
Lower boundary
64
24h
Block
add 1
Block
add 2
Upper boundary
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
LOCK (2Ah)
By default at power-on, if LOCK is HIGH, all the blocks are locked and protected from
PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The
LOCK command locks all of the blocks in the device. Locked blocks are write-protected
from PROGRAM and ERASE operations.
To lock all of the blocks in the device, issue the LOCK (2Ah) command.
When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for
PROGRAM or ERASE operation does not complete. Any READ STATUS command reports bit 7 as 0, indicating that the block is protected.
tLBSY. The
The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is
locked tight.
Figure 49: LOCK Operation
CLE
CE#
WE#
I/Ox
2Ah
LOCK command
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1Gb x8, x16: NAND Flash Memory
Block Lock Feature
LOCK TIGHT (2Ch)
The LOCK TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level
of protection against inadvertent PROGRAM and ERASE operations to locked blocks.
To implement LOCK TIGHT in all of the locked blocks in the device, verify that WP# is
HIGH and then issue the LOCK TIGHT (2Ch) command.
When a PROGRAM or ERASE operation is issued to a locked block that has also been
locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not
complete. The READ STATUS (70h) command reports bit 7 as 0, indicating that the
block is protected. PROGRAM and ERASE operations complete successfully to blocks
that were not locked at the time the LOCK TIGHT command was issued.
After the LOCK TIGHT command is issued, the command cannot be disabled via a software command. The only ways to disable the lock tight status is to power cycle the device. When the lock tight status is disabled, all of the blocks become locked, the same as
if the LOCK (2Ah) command had been issued.
The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.
Figure 50: LOCK TIGHT Operation
LOCK
WP#
CLE
CE#
WE#
I/Ox
2Ch
LOCK TIGHT
command
R/B#
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
Figure 51: PROGRAM/ERASE Issued to Locked Block
LBSY
t
R/B#
I/Ox
PROGRAM or ERASE
CONFIRM
Add ress/data input
70h
Locked block
60h
READ STATUS
BLOCK LOCK READ STATUS (7Ah)
The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection
status of individual blocks. The address cycles have the same format, as shown below,
and the invert area bit should be set LOW. On the falling edge of RE# the I/O pins output
the block lock status register, which contains the information on the protection status
of the block.
Table 16: Block Lock Status Register Bit Definitions
Block Lock Status Register Definitions
I/O[7:3]
I/O2 (Lock#)
I/O1 (LT#)
I/O0 (LT)
Block is locked tight
X
0
0
1
Block is locked
X
0
1
0
Block is unlocked, and device is locked tight
X
1
0
1
Block is unlocked, and device is not locked tight
X
1
1
0
Figure 52: BLOCK LOCK READ STATUS
CLE
CE#
WE#
tWHRIO
ALE
RE#
I/Ox
7Ah
BLOCK LOCK
READ STATUS
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Add 1
Add 2
Status
Block address
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Preliminary
1Gb x8, x16: NAND Flash Memory
Block Lock Feature
Figure 53: BLOCK LOCK Flowchart
Power-up
Power-up with
LOCK HIGH
Power-up with
LOCK LOW
(default)
Entire NAND Flash
array locked
BLOCK LOCK function
disabled
LOCK TIGHT Cmd
with WP# and
LOCK HIGH
Entire NAND Flash
array locked tight
UNLOCK Cmd with
invert area bit = 1
UNLOCK Cmd with
invert area bit = 0
WP# LOW
>100ns or
LOCK Cmd
WP# LOW
>100ns or
LOCK Cmd
Unlocked range
Locked range
Locked range
Unlocked range
UNLOCK Cmd with
invert area bit = 0
UNLOCK Cmd with invert area bit = 1
Unlocked range
UNLOCK Cmd
with invert area
bit = 1
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UNLOCK Cmd with invert area bit = 0
LOCK TIGHT Cmd
with WP# and
LOCK HIGH
Locked range
LOCK TIGHT Cmd
with WP# and
LOCK HIGH
Unlocked range
Locked tight range
Locked tight range
Unlocked range
Unlocked range
Locked-tight range
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1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
One-Time Programmable (OTP) Operations
This Micron NAND Flash device offers a protected, one-time programmable NAND
Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on
the device, and the entire range is guaranteed to be good. The OTP area is accessible
only through the OTP commands. Customers can use the OTP area any way they
choose; typical uses include programming serial numbers or other data for permanent
storage.
The OTP area leaves the factory in an unwritten state (all bits are 1s). Programming or
partial-page programming enables the user to program only 0 bits in the OTP area. The
OTP area cannot be erased, whether it is protected or not. Protecting the OTP area prevents further programming of that area.
Micron provides a unique way to program and verify data before permanently protecting it and preventing future changes. The OTP area is only accessible while in OTP operation mode. To set the device to OTP operation mode, issue the SET FEATURE (EFh)
command to feature address 90h and write 01h to P1, followed by three cycles of 00h to
P2-P4. For parameters to enter OTP mode, see Features Operations.
When the device is in OTP operation mode, all subsequent PAGE READ (00h-30h) and
PROGRAM PAGE (80h-10h) commands are applied to the OTP area. The OTP area is assigned to page addresses 02h-1Fh. To program an OTP page, issue the PROGRAM PAGE
(80h-10h) command. The pages must be programmed in the ascending order. Similarly,
to read an OTP page, issue the PAGE READ (00h-30h) command.
Protecting the OTP is done by entering OTP protect mode. To set the device to OTP protect mode, issue the SET FEATURE (EFh) command to feature address 90h and write
03h to P1, followed by three cycles of 00h to P2-P4.
To determine whether the device is busy during an OTP operation, either monitor R/B#
or use the READ STATUS (70h) command.
To exit OTP operation or protect mode, write 00h to P1 at feature address 90h.
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1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
OTP DATA PROGRAM (80h-10h)
The OTP DATA PROGRAM (80h-10h) command is used to write data to the pages within
the OTP area. An entire page can be programmed at one time, or a page can be partially
programmed up to eight times. Only the OTP area allows up to eight partial-page programs. The rest of the blocks support only four partial-page programs. There is no
ERASE operation for OTP pages.
PROGRAM PAGE enables programming into an offset of an OTP page using two bytes of
the column address (CA[12:0]). The command is compatible with the RANDOM DATA
INPUT (85h) command. The PROGRAM PAGE command will not execute if the OTP
area has been protected.
To use the PROGRAM PAGE command, issue the 80h command. Issue n address cycles.
The first two address cycles are the column address. For the remaining cycles, select a
page in the range of 02h-00h through 1Fh-00h. Next, write from 1–2112 bytes of data.
After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification.
R/B# goes LOW for the duration of the array programming time (tPROG). The READ
STATUS (70h) command is the only valid command for reading status in OTP operation
mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready,
read bit 0 of the status register to determine whether the operation passed or failed (see
Status Operations). Each OTP page can be programmed to 8 partial-page programming.
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Preliminary
1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
RANDOM DATA INPUT (85h)
After the initial OTP data set is input, additional data can be written to a new column
address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT
command can be used any number of times in the same page prior to the OTP PAGE
WRITE (10h) command being issued.
Figure 54: OTP DATA PROGRAM (After Entering OTP Operation Mode)
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
Col
add 1
80h
OTP DATA INPUT
command
Col
add 2
OTP
page1
OTP address1
00h
DIN
n
DIN
m
1 up to m bytes
serial input
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
x8 device: m = 2112 bytes
x16 device: m = 1056 words
OTP data written
(following good status confirmation)
Don’t Care
Note:
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1. The OTP page must be within the 02h–1Fh range.
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1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
Figure 55: OTP DATA PROGRAM Operation with RANDOM DATA INPUT (After Entering OTP Operation Mode)
CLE
CE#
tWC
tADL
tADL
WE#
tWB
tPROG
ALE
RE#
I/Ox
80h
Col
add1
OTP
Col
add2 page1
00h
DIN
n
DIN
n+1
Serial input
SERIAL DATA
INPUT command
85h
Col
add1
DIN
n
Col
add2
RANDOM DATA Column address
INPUT command
DIN
n+1
Serial input
10h
70h
PROGRAM
command
READ STATUS
command
Status
R/B#
Don‘t Care
Note:
1. The OTP page must be within the 02h–1Fh range.
OTP DATA PROTECT (80h-10)
The OTP DATA PROTECT (80h-10h) command is used to prevent further programming
of the pages in the OTP area. To protect the OTP area, the target must be in OTP operation mode.
To protect all data in the OTP area, issue the 80h command. Issue n address cycles including the column address, OTP protect page address and block address; the column
and block addresses are fixed to 0. Next, write 00h data for the first byte location and
issue the 10h command. R/B# goes LOW for the duration of the array programming
time, tPROG.
After the data is protected, it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected.
The READ STATUS (70h) command is the only valid command for reading status in OTP
operation mode. The RDY bit of the status register will reflect the state of R/B#. Use of
the READ STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine if the operation passed or failed.
If the OTP DATA PROTECT (80h-10h) command is issued after the OTP area has already
been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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Preliminary
1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
Figure 56: OTP DATA PROTECT Operation (After Entering OTP Protect Mode)
CLE
CE#
tWC
WE#
tWB
tPROG
ALE
RE#
I/Ox
Col
00h
80h
OTP DATA
PROTECT command
Col
00h
OTP
page
00h
00h
OTP address
10h
70h
PROGRAM
command
READ STATUS
command
R/B#
Status
OTP data protected1
Don’t Care
Note:
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1. OTP data is protected following a good status confirmation.
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1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
OTP DATA READ (00h-30h)
To read data from the OTP area, set the device to OTP operation mode, then issue the
PAGE READ (00h-30h) command. Data can be read from OTP pages within the OTP area
whether the area is protected or not.
To use the PAGE READ command for reading data from the OTP area, issue the 00h
command, and then issue five address cycles: for the first two cycles, the column address; and for the remaining address cycles, select a page in the range of 02h-00h-00h
through 1Fh-00h-00h. Lastly, issue the 30h command. The PAGE READ CACHE MODE
command is not supported on OTP pages.
R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The
READ STATUS (70h) command is the only valid command for reading status in OTP operation mode. Bit 5 of the status register reflects the state of R/B# (see Status Operations).
Normal READ operation timings apply to OTP read accesses. Additional pages within
the OTP area can be selected by repeating the OTP DATA READ command.
The PAGE READ command is compatible with the RANDOM DATA OUTPUT (05h-E0h)
command.
Only data on the current page can be read. Pulsing RE# outputs data sequentially.
Figure 57: OTP DATA READ
CLE
CE#
WE#
ALE
tR
RE#
I/Ox
00h
Col
add 1
Col
add 2
OTP
page1
DOUT
n
30h
00h
OTP address
DOUT
n+1
DOUT
m
Busy
R/B#
Don’t Care
Note:
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1. The OTP page must be within the 02h–1Fh range.
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Preliminary
1Gb x8, x16: NAND Flash Memory
One-Time Programmable (OTP) Operations
Figure 58: OTP DATA READ with RANDOM DATA READ Operation
CLE
tCLR
CE#
WE#
tWB
tAR
tWHR
ALE
tREA
tRC
RE#
tRR
I/Ox
00h
Col
add 1
Col
add 2
Column addressn
R/B#
OTP
page1
00h
DOUT
n
30h
tR
DOUT
n+1
05h
Col
add 1
Col
add 2
E0h
DOUT
m
DOUT
m+1
Column addressm
Busy
Don’t Care
Note:
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1. The OTP page must be within the range 02h–1Fh.
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Preliminary
1Gb x8, x16: NAND Flash Memory
Error Management
Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad block management and error-correction algorithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad block mark into every location in the first page of each invalid block. It may not be possible to program every location with the bad block mark. However, the first spare area location in each bad block is
guaranteed to contain the bad block mark. This method is compliant with ONFI Factory
Defect Mapping requirements. See the following table for the first spare area location
and the bad block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash device. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Always check status after a PROGRAM or ERASE operation
• Under typical conditions, use the minimum required ECC (see table below)
• Use bad block management and wear-leveling algorithms
The first block (physical block address 00h) for each CE# is guaranteed to be valid
with ECC when shipped from the factory.
Table 17: Error Management Details
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Description
Requirement
Minimum number of valid blocks (NVB) per LUN
1004
Total available blocks per LUN
1024
First spare area location
x8: byte 2048 x16: word 1024
Bad-block mark
x8: 00h x16: 0000h
Minimum required ECC
4-bit ECC per 528 bytes of data
Minimum required ECC for block 0 if PROGRAM/
ERASE cycles are less than 1000
1-bit ECC per 528 bytes
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Preliminary
1Gb x8, x16: NAND Flash Memory
Electrical Specifications
Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods can affect reliability.
Table 18: Absolute Maximum Ratings
Voltage on any pin relative to VSS
Parameter/Condition
Voltage Input
3.3V
Symbol
Min
Max
Unit
VIN
–0.6
4.6
V
–0.6
2.4
V
–0.6
4.6
V
–0.6
2.4
V
TSTG
–65
150
°C
–
–
5
mA
1.8V
VCC supply voltage
3.3V
VCC
1.8V
Storage temperature
Short circuit output current, I/Os
Table 19: Recommended Operating Conditions
Parameter/Condition
Operating temperature Commercial
Symbol
Min
Typ
Max
Unit
TA
0
–
70
°C
Industrial
VCC supply voltage
3.3V
VCC
1.8V
Ground supply voltage
VSS
–40
–
85
°C
2.7
3.3
3.6
V
1.7
1.8
1.95
V
0
0
0
V
Table 20: Valid Blocks
Parameter
Valid block number
Note:
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Symbol
Device
Min
Max
Unit
Notes
NVB
3.3V/1.8V
1004
1024
blocks
1
1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad
blocks upon shipment. Additional bad blocks may develop over time; however, the total
number of available blocks will not drop below NVB during the endurance life of the
device. Do not erase or program blocks marked invalid by the factory.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications
Table 21: Capacitance
Description
Notes:
Symbol
Max
Unit
Notes
Input capacitance
CIN
10
pF
1, 2
Input/output capacitance (I/O)
CIO
10
pF
1, 2
1. These parameters are verified in device characterization and are not 100% tested.
2. Test conditions: TC = 25°C; f = 1 MHz; VIN = 0V.
Table 22: Test Conditions
Parameter
Value
Input pulse levels
0.0V to VCC
Input rise and fall times
5ns
Input and output timing levels
VCC/2
Output load
Note:
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Notes
3.3V
1 TTL GATE and CL = 30pF
1
1.8V
1 TTL GATE and CL = 30pF
1
1. These parameters are verified in device characterization and are not 100% tested.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – AC Characteristics and Operating
Conditions
Electrical Specifications – AC Characteristics and Operating Conditions
Table 23: AC Characteristics: Command, Data, and Address Input (3.3V)
Note 1 applies to all
Parameter
Symbol
Min
Max
Unit
Notes
ALE to data start
tADL
70
–
ns
2
ALE hold time
tALH
5
–
ns
ALE setup time
tALS
10
–
ns
CE# hold time
tCH
5
–
ns
CLE hold time
tCLH
5
–
ns
CLE setup time
tCLS
10
–
ns
CE# setup time
tCS
15
–
ns
Data hold time
tDH
5
–
ns
Data setup time
tDS
7
–
ns
WRITE cycle time
tWC
20
–
ns
2
WE# pulse width HIGH
tWH
7
–
ns
2
WE# pulse width
tWP
10
–
ns
2
WP# transition to WE# LOW
tWW
100
–
ns
Notes:
1. Operating mode timings meet ONFI timing mode 5 parameters.
2. Timing for tADL begins in the address cycle, on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
Table 24: AC Characteristics: Command, Data, and Address Input (1.8V)
Note 1 applies to all
Parameter
Symbol
Min
Max
Unit
Notes
ALE to data start
tADL
70
–
ns
2
ALE hold time
tALH
5
–
ns
ALE setup time
tALS
10
–
ns
CE# hold time
tCH
5
–
ns
CLE hold time
tCLH
5
–
ns
CLE setup time
tCLS
10
–
ns
CE# setup time
tCS
20
–
ns
Data hold time
tDH
5
–
ns
Data setup time
tDS
10
–
ns
WRITE cycle time
tWC
25
–
ns
2
WE# pulse width HIGH
tWH
10
–
ns
2
WE# pulse width
tWP
12
–
ns
2
WP# transition to WE# LOW
tWW
100
–
ns
Notes:
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1. Operating mode timings meet ONFI timing mode 4 parameters.
2. Timing for tADL begins in the address cycle on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – AC Characteristics and Operating
Conditions
Table 25: AC Characteristics: Normal Operation (3.3V)
Note 1 applies to all
Parameter
Symbol
Min
tAR
Max
Unit
CE# access time
tCEA
10
–
ns
–
25
ns
CE# HIGH to output High-Z
tCHZ
–
50
ns
CLE to RE# delay
tCLR
10
–
ns
CE# HIGH to output hold
tCOH
15
–
ns
Output High-Z to RE# LOW
tIR
0
–
ns
READ cycle time
tRC
20
–
ns
RE# access time
tREA
–
16
ns
RE# HIGH hold time
tREH
7
–
ns
tRHOH
15
–
ns
RE# HIGH to WE# LOW
tRHW
100
–
ns
RE# HIGH to output High-Z
tRHZ
ALE to RE# delay
RE# HIGH to output hold
–
100
ns
tRLOH
5
–
ns
RE# pulse width
tRP
10
–
ns
Ready to RE# LOW
tRR
20
–
ns
Reset time (READ/PROGRAM/ERASE)
tRST
–
5/10/500
µs
WE# HIGH to busy
tWB
–
100
ns
tWHR
60
–
ns
RE# LOW to output hold
WE# HIGH to RE# LOW
Notes:
Notes
2
2
3
1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
go busy for a maximum of 1ms. Thereafter, the device goes busy for a maximum of 5µs.
Table 26: AC Characteristics: Normal Operation (1.8V)
Note 1 applies to all
Parameter
Symbol
Min
tAR
10
–
ns
CE# access time
tCEA
–
25
ns
CE# HIGH to output High-Z
tCHZ
–
50
ns
CLE to RE# delay
tCLR
10
–
ns
CE# HIGH to output hold
tCOH
15
–
ns
Output High-Z to RE# LOW
tIR
0
–
ns
READ cycle time
tRC
25
–
ns
RE# access time
tREA
–
22
ns
RE# HIGH hold time
tREH
10
–
ns
tRHOH
15
–
ns
tRHW
100
–
ns
ALE to RE# delay
RE# HIGH to output hold
RE# HIGH to WE# LOW
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80
Max
Unit
Notes
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – AC Characteristics and Operating
Conditions
Table 26: AC Characteristics: Normal Operation (1.8V) (Continued)
Note 1 applies to all
Parameter
RE# HIGH to output High-Z
RE# LOW to output hold
Symbol
Min
Max
Unit
Notes
tRHZ
–
65
ns
2
tRLOH
3
–
ns
RE# pulse width
tRP
12
–
ns
Ready to RE# LOW
tRR
20
–
ns
Reset time (READ/PROGRAM/ERASE)
tRST
–
5/10/500
µs
WE# HIGH to busy
tWB
–
100
ns
tWHR
80
–
ns
WE# HIGH to RE# LOW
Notes:
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3
1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
2. Transition is measured ±200mV from steady-state voltage with load. This parameter is
sampled and not 100% tested.
3. The first time the RESET (FFh) command is issued while the device is idle, the device will
be busy for a maximum of 1ms. Thereafter, the device is busy for a maximum of 5µs.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – DC Characteristics and Operating
Conditions
Electrical Specifications – DC Characteristics and Operating Conditions
Table 27: DC Characteristics and Operating Conditions (3.3V)
Parameter
Conditions
Sequential READ current
tRC
=
tRC
(MIN); CE# = VIL;
IOUT = 0mA
Symbol
Min
Typ
Max
Unit
ICC1
–
25
35
mA
Notes
PROGRAM current
–
ICC2
–
25
35
mA
ERASE current
–
ICC3
–
25
35
mA
CE# = VIH;
WP# = 0V/VCC
ISB1
–
–
1
mA
Standby current (CMOS)
CE# = VCC - 0.2V;
WP# = 0V/VCC
ISB2
–
20
100
µA
Staggered power-up current
Rise time = 1ms
Line capacitance = 0.1µF
IST
–
–
10 per die
mA
VIN = 0V to VCC
ILI
–
–
±10
µA
VOUT = 0V to VCC
ILO
–
–
±10
µA
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#
VIH
0.8 x VCC
–
VCC + 0.3
V
–
VIL
–0.3
–
0.2 x VCC
V
Output high voltage
IOH = –400µA
VOH
0.67 x VCC
–
–
V
3
Output low voltage
IOL = 2.1mA
VOL
–
–
0.4
V
3
Output low current
VOL = 0.4V
IOL (R/B#)
8
10
–
mA
2
Standby current (TTL)
Input leakage current
Output leakage current
Input high voltage
Input low voltage, all inputs
Notes:
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1
1. Measurement is taken with 1ms averaging intervals and begins after VCC reaches
VCC(MIN).
2. IOL (RB#) may need to be relaxed if R/B pull-down strength is not set to full.
3. VOH and VOL may need to be relaxed if I/O drive strength is not set to full.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – DC Characteristics and Operating
Conditions
Table 28: DC Characteristics and Operating Conditions (1.8V)
Parameter
Conditions
Sequential READ current
tRC
=
tRC
(MIN); CE# = VIL;
IOUT = 0mA
Symbol
Min
Typ
Max
Unit
Notes
ICC1
–
13
20
mA
1, 2
PROGRAM current
–
ICC2
–
10
20
mA
1, 2
ERASE current
–
ICC3
–
10
20
mA
1, 2
CE# = VIH;
WP# = 0V/VCC
ISB1
–
–
1
mA
Standby current (CMOS)
CE# = VCC - 0.2V;
WP# = 0V/VCC
ISB2
–
10
50
µA
Staggered power-up current
Rise time = 1ms
Line capacitance = 0.1µF
IST
–
–
10 per die
mA
VIN = 0V to VCC
ILI
–
–
±10
µA
VOUT = 0V to VCC
ILO
–
–
±10
µA
I/O[7:0], I/O[15:0],
CE#, CLE, ALE, WE#, RE#,
WP#
VIH
0.8 x VCC
–
VCC + 0.3
V
–
VIL
–0.3
–
0.2 x VCC
V
Output high voltage
IOH = –100µA
VOH
VCC - 0.1
–
–
V
4
Output low voltage
IOL = +100µA
VOL
–
–
0.1
V
4
VOL = 0.2V
IOL (R/B#)
3
4
–
mA
5
Standby current (TTL)
Input leakage current
Output leakage current
Input high voltage
Input low voltage, all inputs
Output low current (R/B#)
Notes:
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3
1. Typical and maximum values are for single-plane operation only.
2. Values are for single-die operations. Values could be higher for interleaved-die operations.
3. Measurement is taken with 1ms averaging intervals and begins after VCC reaches
VCC(MIN).
4. Test conditions for VOH and VOL.
5. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.
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1Gb x8, x16: NAND Flash Memory
Electrical Specifications – Program/Erase Characteristics
Electrical Specifications – Program/Erase Characteristics
Table 29: ProgramErase Characteristics
Parameter
Number of partial-page programs
Symbol
Typ
Max
Unit
4
cycles
Notes
NOP
–
BLOCK ERASE operation time
tBERS
0.7
3
ms
Busy time for PROGRAM CACHE operation
tCBSY
3
600
µs
tRCBSY
3
25
µs
Busy time for SET FEATURES and GET FEATURES operations
tFEAT
–
1
µs
Busy time for OTP DATA PROGRAM operation if OTP is protected
tOBSY
–
30
µs
PROGRAM PAGE operation time
tPROG
200
600
µs
3
tR
–
25
µs
4
Cache read busy time
Data transfer from Flash array to data register
Notes:
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2
1. Applies to entire table: Typical is nominal voltage and room temperature.
2. tCBSY MAX time depends on timing between internal program completion and data-in.
3. Typical program time is defined as the time within which more than 50% of the pages
are programmed at nominal voltage and room temperature.
4. AC characteristics may need to be relaxed if I/O drive strength is not set to full.
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Asynchronous Interface Timing Diagrams
Asynchronous Interface Timing Diagrams
Figure 59: RESET Operation
CLE
CE#
tWB
WE#
tRST
R/B#
I/O[7:0]
FFh
RESET
command
Figure 60: READ STATUS Cycle
tCLR
CLE
CE#
tCLS
tCLH
tCS
tWP
tCH
WE#
tCEA
tWHR
tRP
tCOH
tCHZ
RE#
tRHZ
tDS
I/O[7:0]
tDH
tIR
tREA
tRHOH
Status
output
70h
Don’t Care
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Asynchronous Interface Timing Diagrams
Figure 61: READ PARAMETER PAGE
CLE
WE#
tWB
ALE
tRC
RE#
tRR
I/O[7:0]
ECh
00h
P00
tR
R/B#
tRP
P10
P2550
P01
Figure 62: READ PAGE
CLE
tCLR
CE#
tWC
WE#
tWB
tAR
ALE
tR
tRC
tRHZ
RE#
tRR
I/Ox
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
tRP
DOUT
N
30h
DOUT
N+1
DOUT
M
Busy
RDY
Don’t Care
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 63: READ PAGE Operation with CE# “Don’t Care”
CLE
CE#
RE#
ALE
tR
RDY
WE#
I/Ox
00h
Address (4 cycles)
30h
Data output
tCEA
CE#
tREA
tCOH
RE#
Don’t Care
Out
I/Ox
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tCHZ
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 64: RANDOM DATA READ
CLE
tCLR
CE#
WE#
tRHW
tWHR
ALE
tRC
tREA
RE#
I/Ox
DOUT
N-1
DOUT
N
05h
Col
add 1
Col
add 2
E0h
DOUT
M
DOUT
M+1
Column address M
RDY
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 65: READ PAGE CACHE SEQUENTIAL
CLE
tCLS
tCLS
tCLH
tCS
tCLH
tCS
tCH
tCH
CE#
tWC
WE#
tCEA
tRHW
ALE
tRC
RE#
tDH
tDS
tR
tWB
I/Ox
Col
add 1
00h
Col
add 2
Column address
00h
Row
add 1
Row
add 2
30h
tRR
DOUT
0
31h
Page address
M
tWB
tREA
tDS
DOUT
1
tDH
DOUT
31h
Page address
M
tRCBSY
RDY
Column address 0
1
CLE
tCLS
tCLH
tCS
tCH
CE#
WE#
tRHW
tRHW
tCEA
ALE
tRC
tRC
RE#
tWB
tREA
tDS
tRR
tDH
I/Ox
DOUT
0
DOUT
1
DOUT
Page address
M
tREA
DOUT
0
31h
tRCBSY
DOUT
1
Page address
M+1
DOUT
DOUT
0
3Fh
tRCBSY
DOUT
1
DOUT
Page address
M+2
RDY
Column address 0
Column address 0
Column address 0
1
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Don’t Care
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 66: READ PAGE CACHE RANDOM
CLE
tCLS
tCLH
tCH
tCS
CE#
tWC
WE#
ALE
RE#
tDH
tWB
tDS
I/Ox
Col
add 1
00h
Col
add 2
Column address
00h
Row
add 1
Row
add 2
tR
30h
Col
add 1
00h
Page address
M
Row
add 1
Col
add 2
Column address
00h
Row
add 2
Page address
N
RDY
1
CLE
tCLS
tCLH
tCS
tCH
CE#
WE#
tCEA
ALE
tRC
tWB
RE#
tDS
tDH
I/Ox
tRHW
Col
add 1
Row
add 1
Col
add 2
Column address
00h
RDY
Row
add 2
Page address
N
tRR
tREA
DOUT
0
31h
tRCBSY
DOUT
1
Page address
M
Column address 0
1
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DOUT
DOUT
0
3Fh
tRCBSY
DOUT
1
DOUT
Page address
N
Column address 0
Don’t Care
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 67: READ ID Operation
CLE
CE#
WE#
tAR
ALE
RE#
tWHR
I/Ox
90h
tREA
Byte 1
Byte 0
00h or 20h
Byte 2
Byte 3
Byte 4
Address, 1 cycle
Figure 68: PROGRAM PAGE Operation
CLE
CE#
tWC
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
I/Ox
80h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
DIN
N
DIN
M
10h
70h
Status
1 up to m byte
serial Input
RDY
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 69: PROGRAM PAGE Operation with CE# “Don’t Care”
CLE
CE#
WE#
ALE
I/Ox
80h
Address (4 cycles)
Data
input
Data
input
10h
tCH
tCS
CE#
tWP
WE#
Don’t Care
Figure 70: PROGRAM PAGE Operation with RANDOM DATA INPUT
CLE
CE#
tWC
tADL
tADL
WE#
tWB
tPROG
tWHR
ALE
RE#
i/Ox
80h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
DIN
M
DIN
N
Serial input
Col
add 1
85h
Col
add 2
CHANGE WRITE Column address
COLUMN command
DIN
P
DIN
Q
Serial input
10h
70h
Status
READ STATUS
command
RDY
Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 71: PROGRAM PAGE CACHE
CLE
CE#
tADL
tWC
WE#
tWB tCBSY
tWB tLPROG
tWHR
ALE
RE#
I/Ox
80h
Row Row
Col
Col
add 1 add 2 add 1 add 2
DIN
DIN
N
M
Serial input
15h
80h
DIN
N
Col
Col Row Row
add 1 add 2 add 1 add 2
DIN
M
10h
70h
Status
RDY
Last page - 1
Last page
Don’t Care
Figure 72: PROGRAM PAGE CACHE Ending on 15h
CLE
CE#
tADL
tADL
tWC
WE#
tWHR
tWHR
ALE
RE#
I/Ox
80h
Col Row Row
Col
add 1 add 2 add 1 add 2
DIN
DIN
N
M
Serial input
15h
70h
Status
80h
Col Row Row
Col
add 1 add 2 add 1 add 2
Last page – 1
DIN
N
DIN
M
15h
70h
Status
70h
Status
Last page
Poll status until:
I/O6 = 1, Ready
To verify successful completion of the last 2 pages:
I/O5 = 1, Ready
I/O0 = 0, Last page PROGRAM successful
I/O1 = 0, Last page – 1 PROGRAM successful
Don’t Care
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1Gb x8, x16: NAND Flash Memory
Asynchronous Interface Timing Diagrams
Figure 73: INTERNAL DATA MOVE
CLE
CE#
tADL
tWC
WE#
tWB tPROG
tWB
tWHR
ALE
RE#
I/Ox
tR
00h
Col
add 1
Col
add 2
Row
add 1
Row
add 2
35h
(or 30h)
Col
Row Row
Col
add 1 add 2 add 1 add 2
85h
Data
1
Data
N
10h
Status
70h
READ STATUS
Busy command
Busy
RDY
Data Input
Optional
Don’t Care
Figure 74: ERASE BLOCK Operation
CLE
CE#
WC
t
WE#
WB
WHR
t
t
ALE
RE#
BERS
t
I/O[7:0]
60h
Row
add 1
Row
add 2
D0h
70h
Row address
RDY
Status
READ STATUS
command
Busy
I/O0 = 0, Pass
I/O0 = 1, Fail
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Don’t Care
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Preliminary
1Gb x8, x16: NAND Flash Memory
Revision History
Revision History
Rev. E, Preliminary – 7/12
• Added LOCK pin description to Table 1
• Added note 2 to Figure 2
Rev. D, Preliminary – 2/12
• Updated ISB2 spec in 3.3V DC Characteristics and Operating Conditions table
Rev. C, Preliminary – 2/12
• Updated Parameter Page Data Structure Tables
• Updated 63-ball package drawing (H4)
Rev. B, Preliminary – 11/11
• Command Definitions topic, Command Set table: Changed OTP DATA LOCK BY
BLOCK (ONFI) to OTP DATA LOCK BY PAGE (ONFI).
• One-Time Programmable (OTP) Operations topic, OTP DATA PROTECT (80h-10) section: Updated content.
Rev. A, Preliminary – 08/11
• Initial release.
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices.
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