MT2LDT432HG-5XS

ADVANCE 4, 8 MEG x 32 DRAM SODIMMs SMALL-OUTLINE DRAM MODULE FEATURES • JEDEC pinout in a 72-pin, small-outline, dual inline memory module (SODIMM) • 16MB (4 Meg x 32) and 32MB (8 Meg x 32) • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All inputs, outputs and clocks are TTL-compatible • 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms • FAST PAGE MODE (FPM) or Extended Data-Out (EDO) PAGE MODE access cycles • Optional self refresh (S) for low-power data retention MT2LDT432H (X)(S), MT4LDT832H (X)(S) For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html PIN ASSIGNMENT (Front View) 72-Pin Small-Outline DIMM 1 OPTIONS • Package 72-pin SODIMM (gold) • Timing 50ns access 60ns access • Access Cycles FAST PAGE MODE EDO PAGE MODE • Refresh Rates Standard Refresh Self Refresh (128ms period) MARKING G -5 -6 None X None S PIN FRONT PIN 1 VSS 2 3 DQ1 4 5 DQ3 6 7 DQ5 8 9 DQ7 10 11 PRD1 12 13 A1 14 15 A3 16 17 A5 18 19 A10 20 21 DQ8 22 23 DQ10 24 25 DQ12 26 27 DQ14 28 29 A11 30 31 A8 32 33 NC/RAS3#* 34 35 DQ15 36 *32MB version only BACK DQ0 DQ2 DQ4 DQ6 VDD A0 A2 A4 A6 NC DQ9 DQ11 DQ13 A7 VDD A9 RAS2# NC PIN FRONT PIN 37 DQ16 38 39 VSS 40 41 CAS2# 42 43 CAS1# 44 45 NC/RAS1#* 46 47 WE# 48 49 DQ18 50 51 DQ20 52 53 DQ22 54 55 NC 56 57 DQ25 58 59 DQ28 60 61 VDD 62 63 DQ30 64 65 NC 66 67 PRD3 68 69 PRD5 70 71 PRD7 72 BACK DQ17 CAS0# CAS3# RAS0# NC (A12) NC (A13) DQ19 DQ21 DQ23 DQ24 DQ26 DQ27 DQ29 DQ31 PRD2 PRD4 PRD6 VSS PART NUMBERS EDO Operating Mode PART NUMBER MT2LDT432HG-x X MT2LDT432HG-x XS MT4LDT832HG-x X MT4LDT832HG-x XS x = speed CONFIGURATION 4 Meg x 32 4 Meg x 32 8 Meg x 32 8 Meg x 32 REFRESH Standard Self Standard Self NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. KEY TIMING PARAMETERS EDO Operating Mode SPEED -5 -6 tRC 84ns 104ns tRAC tPC 20ns 25ns tAA 25ns 30ns tCAC tCAS FPM Operating Mode PART NUMBER MT2LDT432HG-x MT2LDT432HG-x S MT4LDT832HG-x MT4LDT832HG-x S x = speed 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 50ns 60ns 13ns 15ns 8ns 10ns CONFIGURATION 4 Meg x 32 4 Meg x 32 8 Meg x 32 8 Meg x 32 REFRESH Standard Self Standard Self FPM Operating Mode SPEED -5 -6 tRC tRAC tPC tAA tCAC tRP 90ns 110ns 50ns 60ns 30ns 35ns 25ns 30ns 13ns 15ns 30ns 40ns 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs GENERAL DESCRIPTION The MT2LDT432H (X)(S) and MT4LDT832H (X)(S) are randomly accessed 16MB and 32MB memories organized in a small-outline x32 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the address bits, which are entered 12 bits (A0-A11) at a time. RAS# is used to latch the first 12 bits and CAS# the latter 10 bits. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. If WE# goes LOW prior to CAS# going LOW, the output pin(s) remain open (High-Z) until the next CAS# cycle. FAST-PAGE-MODE READ, except data will be held valid or become valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW. (Refer to the 4 Meg x 16 [MT4LC4M16R6] DRAM data sheet for additional information on EDO functionality.) REFRESH Memory cell data is retained in its correct state by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is also available. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms. The optional self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence, all rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. FAST PAGE MODE FAST-PAGE-MODE operations allow faster data operations (READ or WRITE) within a row-addressdefined page boundary. The FAST-PAGE-MODE cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGEMODE operation. EDO PAGE MODE EDO PAGE MODE, designated by the “X” version, is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO operates as any DRAM READ or STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FUNCTIONAL BLOCK DIAGRAM MT2LDT432H (X)(S) (16MB) 12 A0-A11 WE# U1 DQ0DQ15 CAS0# CAS1# RAS0# A0-A11 WE# CASL# CASH# RAS# OE# 16 12 32 DQ0-DQ31 12 A0-A11 WE# U2 DQ16DQ31 CAS2# CAS3# RAS2# CASL# CASH# RAS# OE# 16 VDD VSS U1-U2 U1-U2 U1-U2 = MT4LC4M16R6TG (S) EDO PAGE MODE U1-U2 = MT4LC4M16F5TG (S) FAST PAGE MODE 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FUNCTIONAL BLOCK DIAGRAM MT4LDT832H (X)(S) (32MB) 12 A0-A11 WE# U1 DQ0DQ15 CAS0# CAS1# RAS0# CASL# CASH# RAS# OE# 16 32 DQ0-DQ31 12 WE# CAS2# CAS3# RAS2# A0-A11 A0-A11 WE# U2 DQ16DQ31 CASL# CASH# RAS# 16 12 OE# 12 A0-A11 WE# CASL# CASH# U3 DQ0DQ15 16 RAS1# RAS# OE# 32 DQ0-DQ31 12 A0-A11 WE# U4 DQ16DQ31 CASL# CASH# RAS3# RAS# OE# 16 VDD VSS U1-U4 U1-U4 U1-U4 = MT4LC4M16R6TG (S) EDO PAGE MODE U1-U4 = MT4LC4M16F5TG (S) FAST PAGE MODE 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs JEDEC-DEFINED PRESENCE-DETECT – MT2LDT432H (X)(S) (16MB) SYMBOL PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 PIN 11 66 67 68 69 70 71 -5 NC NC V SS NC V SS V SS X* -6 NC NC VSS NC NC NC X* JEDEC-DEFINED PRESENCE-DETECT – MT4LDT832H (X)(S) (32MB) SYMBOL PRD1 PRD2 PRD3 PRD4 PRD5 PRD6 PRD7 PIN 11 66 67 68 69 70 71 -5 NC NC V SS V SS V SS V SS X* -6 NC NC VSS VSS NC NC X* *X = NC (Normal Refresh) or VSS (Self Refresh) 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS ..................................... -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ................................. -1V to +4.6V Operating Temperature, TA (ambient) .. 0°C to +70°C Storage Temperature (plastic) ........... -55°C to +125°C Power Dissipation ................................................... 4W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs INPUT LOW VOLTAGE: Valid Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input at VIN (0V £ VIN £ VDD + 0.3V); All other pins not under test = 0V CAS0#-CAS3# A0-A11, WE# RAS0#-RAS3# OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V £ VOUT £ VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) DQ0-DQ31 SYMBOL VDD VIH VIL IIL1 II2 II3 IOZ VOH VOL SIZE ALL ALL ALL 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB ALL ALL MIN 3 2 -0.3 -2 -4 -4 -8 -2 -2 -5 -10 2.4 – MAX 3.6 VDD + 0.3 0.8 2 4 4 8 2 2 5 10 – 0.4 UNITS NOTES V V V µA µA µA µA V V 26 26 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# • VDD - 0.2V; DQs may be left open; Other inputs: VIN • VDD - 0.2V or VIN £ 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) OPERATING CURRENT: EDO PAGE MODE (“X” version only) Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: SELF (“S” version only) Average power supply current: CBR with RAS# • tRASS (MIN) and CAS# held LOW; WE# = VDD - 0.2V; A0-A11, OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open) SYMBOL IDD1 SIZE 16MB 32MB 16MB 32MB 16MB 32MB 16MB 32MB -5 2 4 1 2 350 352 210 212 310 312 350 352 350 352 MAX -6 2 4 1 2 330 332 190 192 250 252 330 332 330 332 UNITS NOTES mA mA IDD2 mA 3, 22 IDD3 mA 3, 22 IDD4 IDD5 16MB (X only) 32MB 16MB 32MB 16MB 32MB mA 3, 22 mA 3, 22 IDD6 mA 3, 4 IDD7 IDD8 16MB (S only) 32MB 0.8 1.6 0.8 1.6 mA 3, 4 CAPACITANCE PARAMETER Input Capacitance: A0-A11 Input Capacitance: WE# Input Capacitance: RAS0#-RAS3# Input Capacitance: CAS0#-CAS3# Input/Output Capacitance: DQ0-DQ31 CI1 CI2 CI3 CI4 CIO 14 18 10 10 10 MAX SYMBOL 16MB 32MB UNITS NOTES 24 32 10 18 18 pF pF pF pF pF 2 2 2 2 2 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time (FAST PAGE MODE) Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) WRITE command to CAS# lead time Data-in hold time Data-in setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time Access time from RAS# RAS# to column-address delay time -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWL tDH tDS tOFF tORD tPC tRAC tRAD MIN 40 0 0 13 8 13 15 15 3 8 5 50 5 13 8 0 3 0 30 13 10,000 10 15 15 15 3 10 5 60 5 15 10 0 3 0 35 15 MAX 25 MIN 45 0 0 15 10,000 -6 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 25 4 21 13 30 35 4 18 18 17, 21, 23 13 15 50 60 15 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FAST PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS - FAST PAGE MODE OPTION PARAMETER Row-address hold time RAS# pulse width RAS# pulse width (Self Refresh) RAS# pulse width (FAST PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (4,096 cycles) Refresh period “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time (Self Refresh) READ command hold time (referenced to RAS#) RAS# hold time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRAH tRAS tRASS tRASP tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 8 50 100 50 90 18 0 0 MAX 10,000 125,000 MIN 10 60 100 60 110 20 0 0 -6 MAX 10,000 125,000 UNITS ns ns µs ns ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 25 14 16 64 128 30 0 90 0 13 13 2 8 40 0 8 10 10 40 0 105 0 15 15 2 10 45 0 10 10 10 64 128 25 25 16 50 50 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after next CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) WRITE command to CAS# lead time Data-in hold time Data-in setup time Output buffer turn-off delay EDO-PAGE-MODE READ or WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCHD tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWL tDH tDS tOFF tPC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD MIN 12 38 0 0 13 8 8 15 8 0 3 8 5 38 5 8 8 0 0 20 9 9 50 50 100 84 11 10,000 10 10 15 10 0 3 10 5 45 5 10 10 0 0 25 12 10 60 60 100 104 14 MAX 25 MIN 15 45 0 0 15 10,000 -6 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns ns NOTES 25 4 13 28 35 4 18 18 17, 23 12 50 15 60 15 10,000 125,000 10,000 125,000 25 14 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12, 19) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS - EDO PAGE MODE OPTION PARAMETER READ command hold time (referenced to CAS#) READ command setup time Refresh period (4,096 cycles) Refresh period “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP MIN 0 0 MAX MIN 0 0 -6 MAX UNITS ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 16 64 128 30 5 90 0 13 13 2 8 38 0 0 5 10 8 8 40 5 105 0 15 15 2 10 45 0 0 5 10 10 10 64 128 25 25 16 50 50 12 15 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns for FPM and tT = 2.5ns for EDO. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10.For FPM: If CAS# = VIH, data output is High-Z. For EDO: If CAS# and RAS# = VIH, data output is High-Z. 11.If CAS# = VIL, data output may contain data from the last valid READ cycle. 12.Measured with a load equivalent to two TTL gates and 100pF, VOL = 0.8V and VOH = 2V. 13.If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 14.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 15.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 16.Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 18.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles. 19.OE# is tied permanently LOW; LATE WRITE or READ-MODIFY-WRITE operations are not permissible and should not be attempted. 20.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21.The 3ns minimum is a parameter guaranteed by design. 22.Column address changed once each cycle. 23.With the FPM option, tOFF is determined by the first RAS# or CAS# signal to transition HIGH. In comparison, tOFF on an EDO option is determined by the latter of the RAS# and CAS# signals to transition HIGH. 24.Applies to both FPM and EDO operating modes. 25.“S” version only. 26.VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width £ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width £ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs READ CYCLE 24 tRC tRAS V IH V IL tCSH tRSH tCRP tRCD tCAS tRRH tRP RAS# CAS# ADDR WE# DQ FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tACH (EDO) tAR (EDO) tAR (FPM) tASC tASR tCAC tCAH tCAS tCAS ; ;;;; ;;;;; ; ;;; ; ; ; ;; ; ;; ; ;; ;; ;; ;; V IH V IL tASR tRAD tRAH tAR tASC tCAH tACH V IH V IL ROW COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tCLZ NOTE 1 tOFF V OH V OL OPEN VALID DATA OPEN DON’T CARE UNDEFINED -6 MAX 25 MIN 15 45 45 0 0 13 15 10 10 15 0 3 5 45 12 60 0 15 10,000 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF (FPM) tRAC tRAD (EDO) tRAD (FPM) tRAH tRAH tRAS tRC (EDO) tRC -5 MIN 3 9 13 9 8 50 84 90 11 18 0 0 30 0 13 10,000 MAX 13 50 MIN 3 12 15 10 10 60 104 110 14 20 0 0 40 0 15 -6 MAX 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns ns MIN 12 38 40 0 0 8 8 13 0 3 5 38 50 0 (EDO) (FPM) (EDO) 10,000 10,000 (FPM) (EDO) (FPM) (FPM) tCLZ (EDO) tCLZ (FPM) tCRP tCSH tCSH tRCD tRCD tRCH tRCS tRP tRRH tRSH (EDO) (FPM) tOFF (EDO) NOTE: 1. For EDO, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM, tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs first. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EARLY WRITE CYCLE 24 tRC tRAS V IH V IL tCSH tRSH tCAS tRP RAS# CAS# ADDR ;; ;; ;;;;; ;; ; ; ;;;;; ;;;;;;;;; ;;; ;; ;; ;; ; ; ;;;;;; ;; ; ; ;; tCRP tRCD V IH V IL tRAD tRAH tAR tASC tCAH tASR tACH V IH V IL ROW COLUMN ROW tCWL tRWL tWCS tWCR tWCH tWP WE# V IH V IL tDS tDH V DQ V IOH IOL VALID DATA FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tACH (EDO) tAR tAR ;; -6 MIN 12 10 10 60 110 104 20 14 40 15 15 10 45 45 0 10 5 DON’T CARE UNDEFINED -6 MAX MIN 15 45 45 0 0 10 10,000 10,000 15 10 5 60 45 15 10 10 0 15 10,000 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD (EDO) tRAH tRAH tRAS tRC -5 MIN 9 9 8 50 90 84 18 11 30 13 13 8 38 40 0 8 5 MAX MIN 12 38 40 0 0 8 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (EDO) (FPM) tASC tASR tCAH tCAS tCAS tCRP tCSH (EDO) (FPM) 10,000 10,000 (FPM) tRC (EDO) tRCD tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP (FPM) tWP (EDO) (FPM) (EDO) 13 8 5 50 38 13 8 8 0 13 (FPM) (EDO) (FPM) tCSH (EDO) tCWL tDH tDS tRAD (FPM) tCWL (EDO) (EDO) tWCR (FPM) (FPM) 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FAST-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ADDR WE# DQ ;;;; ;; ;;; ;;;; ;; ; ; ; ;; ; ; ;;;; ;;; ;; ; ;; ; ; ;; ; ; ;;; ; V IH V IL tAR tASR tRAD tRAH tASC tCAH tASC tCAH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRCS tRCH tRCS tRCH tRCS tRCH tRRH V IH V IL tAA tRAC tCAC tAA tCPA tAA tCPA tOFF tCAC tOFF tCAC tOFF tCLZ tCLZ tCLZ V IOH V IOL OPEN VALID DATA VALID DATA VALID DATA OPEN DON’T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH -6 MAX 25 MIN 45 0 0 13 15 10 15 3 10 30 35 5 60 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 3 30 50 13 8 50 18 0 0 30 0 13 15 10 60 20 0 0 40 0 15 MAX 13 MIN 3 35 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 3 8 5 50 125,000 125,000 10,000 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EDO-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ADDR WE# DQ ;; ; ;;; ;; ;;;; ;;;;; ; ; ; ; ;;; ;; ; ; ;;;; ;; V IH V IL tASR tRAD tRAH tAR tACH tASC tCAH tACH tASC tCAH tACH tASC tCAH V IH V IL ROW COLUMN COLUMN COLUMN ROW tRCS tRCH V IH V IL tAA tRAC tCAC tAA tCPA tAA tCPA tRRH tCAC tCAC tCLZ tCLZ tCOH tOFF V OH V OL OPEN VALID DATA VALID DATA VALID DATA OPEN DON’T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP -6 MAX 25 MIN 15 45 0 0 13 15 10 10 0 3 10 28 35 5 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tCSH tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 38 0 20 9 9 50 11 0 0 30 0 13 125,000 MAX 12 50 12 10 60 14 0 0 40 0 15 MIN 45 0 25 -6 MAX 15 60 UNITS ns ns ns ns ns 125,000 ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 0 3 8 5 10,000 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FAST/EDO-PAGE-MODE EARLY WRITE CYCLE 24 tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tACH tASC tCAH tACH tASC tCAH tASC tACH tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ROW COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP ROW tWCS tWCS tWCS WE# V IH V IL tWCR tDS tDH tDS tDH tDS tRWL tDH V DQ V IOH IOL VALID DATA VALID DATA VALID DATA DON’T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tACH (EDO) tAR tAR -6 MAX MIN 15 45 45 0 0 10 10,000 10,000 10 15 10 5 45 60 10 15 10 0 25 10,000 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC (FPM) tRAD (EDO) tRAD (FPM) tRAH tRAH tRASP tRCD tRCD tRP tRSH tRWL tWCH tWCR tWCR tWCS tWP (EDO) tWP (FPM) -5 MIN 30 9 13 9 8 50 11 18 30 13 13 8 (EDO) (FPM) 38 40 0 5 8 125,000 MAX MIN 35 12 15 10 10 60 14 20 40 15 15 10 45 45 0 5 10 -6 MAX UNITS ns ns ns ns 125,000 ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 40 0 0 8 8 13 8 5 38 50 8 13 8 0 20 (EDO) (FPM) tASC tASR tCAH tCAS (EDO) (FPM) (EDO) (FPM) (EDO) tCAS (FPM) tCP tCRP tCSH tCSH tCWL tDH tDS tPC (EDO) (EDO) (FPM) (FPM) tCWL (EDO) 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# V IH V IL t CSH tPC tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH ROW tASC tCAH t ASC t CAH tASC t ACH t CAH t RCD t CAS t CP t CAS tPC t CP t CAS tRSH t CP t RP COLUMN (A) tRCS COLUMN (B) tRCH COLUMN (N) tWCS tWCH ROW WE# V IH V IL tRAC tAA tCPA tCAC tAA tCAC tCOH t WHZ VALID DATA (B) t DS t DH DQ V IOH V IOL OPEN VALID DATA (A) VALID DATA IN DON’T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH -6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 3 10 28 35 5 45 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ -5 MIN 0 20 9 9 50 11 0 0 30 13 8 0 0 12 125,000 MAX MIN 0 25 12 10 60 14 0 0 40 15 10 0 0 -6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns MIN 12 38 0 0 8 8 3 8 5 38 8 50 60 125,000 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) tRASP V IH V IL tRSH tCSH tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tRCD tCAS tCP tPC tCAS tCP tRP RAS# ROW COLUMN COLUMN tCWL tRWL tWCS tWP tWCH ROW tRCS WE# V IH V IL tCAC t CLZ V OH V OL NOTE 1 t OFF tDS VALID DATA tAA tRAC tDH DQ OPEN VALID DATA DON’T CARE UNDEFINED FAST PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS -6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 3 10 5 60 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP -5 MIN 3 30 50 13 8 50 18 0 30 13 13 8 0 8 15 10 60 20 0 40 15 15 10 0 10 MAX 13 MIN 3 35 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 3 8 5 50 13 8 0 125,000 125,000 NOTE: 1. Do not drive input data prior to output data going High-Z. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs EDO READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCRP CAS# V IH V IL tAR tASR V IH V IL ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL tWHZ tCLZ tRAD tRAH tASC COLUMN tRCH tWPZ tRCS tCAH tASC COLUMN tRCD tCSH tCAS tCP ADDR OPEN VALID DATA OPEN DON’T CARE UNDEFINED EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP -6 MAX 25 MIN 45 0 0 13 15 10 10,000 10 0 10 5 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tCSH tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ -5 MIN 38 9 9 11 0 0 0 10 12 MAX 50 12 10 14 0 0 0 10 MIN 45 -6 MAX 60 UNITS ns ns ns ns ns ns 15 ns ns ns MIN 38 0 0 8 8 0 8 5 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs RAS#-ONLY REFRESH CYCLE24 (OE# and WE# = DON’T CARE) tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP RAS# CAS# ROW ROW V DQ V OH OL OPEN DON’T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tASR tCRP tCSR tRAH (EDO) tRAH (FPM) tRAS MIN 0 5 5 9 8 50 MAX MIN 0 5 5 10 10 60 -6 MAX UNITS ns ns ns ns ns ns SYMBOL tRC (FPM) tRC (EDO) tRP tRPC (FPM) tRPC (EDO) MIN 90 84 30 0 5 -5 MAX MIN 110 104 40 0 5 -6 MAX UNITS ns ns ns ns ns 10,000 10,000 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs SELF REFRESH CYCLE 24, 25 (Addresses = DON’T CARE) tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2 RAS# tRPC tCP tRPC tCP (( )) CAS# V IH V IL V DQ V OH OL V WE# V IH IL CBR REFRESH CYCLE 24 (Addresses = DON’T CARE) tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL OPEN tWRP WE# V IH V IL tWRH tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS tRP tRAS V OH DQ V OL DON’T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tCHD tCHR tCHR tCP tCSR tRAS tRASS tRP -6 MAX MIN 15 15 10 10 5 10,000 60 100 40 10,000 MAX UNITS ns ns ns ns ns ns µs ns SYMBOL tRPC tRPS tWRH -5 MIN 0 5 90 10 8 10 8 MAX MIN 0 5 105 10 10 10 10 (FPM) tRPC (EDO) (FPM) tWRH (EDO) tWRP (FPM) tWRP (EDO) -6 MAX UNITS ns ns ns ns ns ns ns MIN 15 15 8 8 5 50 100 30 (FPM) (EDO) NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs HIDDEN REFRESH CYCLE 20, 24 (WE# = HIGH) tRC tRAS RAS# V IH V IL tCRP CAS# V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS ADDR ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V OH OL OPEN VALID DATA OPEN DON’T CARE UNDEFINED FAST PAGE MODE AND EDO PAGE MODE TIMING PARAMETERS -5 SYMBOL tAA tAR (EDO) tAR -6 MAX 25 MIN 45 45 0 0 13 15 10 10 15 0 3 12 5 0 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF (FPM) tRAC tRAD (EDO) tRAD (FPM) tRAH tRAH tRAS tRC (EDO) tRC -5 MIN 3 9 13 9 8 50 84 90 11 18 30 13 10,000 MAX 13 50 MIN 3 12 15 10 10 60 104 110 14 20 40 15 -6 MAX 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns MIN 38 40 0 0 8 8 15 0 3 5 0 (FPM) tASC tASR tCAC tCAH tCHR tCHR (EDO) (FPM) (EDO) (FPM) (FPM) (EDO) (FPM) tCLZ (EDO) tCLZ (FPM) tCRP tOFF (EDO) tRCD tRCD tRP tRSH 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs 72-PIN SODIMM (4 Meg x 32) FRONT VIEW 2.355 (59.82) 2.345 (59.56) .100 (2.54) MAX .079 (2.00) R (3X) 1.005 (25.53) .995 (25.27) .071 (1.80) (2X) .700 (17.78) TYP .125 (3.18) .071 (1.80) TYP .079 (2.00) .197 (5.00) .043 (1.10) .035 (0.90) PIN 1 .040 (1.02) TYP 1.750 (44.45) 2.034 (51.66) .050 (1.27) TYP PIN 71 (PIN 72 on backside) 72-PIN SODIMM (8 Meg x 32) FRONT VIEW 2.355 (59.82) 2.345 (59.56) .150 (3.80) MAX .079 (2.00) R (3X) 1.005 (25.53) .995 (25.27) .071 (1.80) (2X) .700 (17.78) TYP .125 (3.18) .071 (1.80) TYP .079 (2.00) .197 (5.00) .043 (1.10) .035 (0.90) PIN 1 .040 (1.02) TYP 1.750 (44.45) 2.034 (51.66) .050 (1.27) TYP PIN 71 (PIN 72 on backside) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc. ADVANCE 4, 8 MEG x 32 DRAM SODIMMs 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 4, 8 Meg x 32 DRAM SODIMMs DM89.p65 – Rev. 12/98 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1998, Micron Technology, Inc.