MT32LD3264AG-6X

8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs DRAM MODULE FEATURES • Eight-CAS# ECC pinout in a 168-pin, dual in-line memory module (DIMM) • 64MB (8 Meg x 64), 128MB (16 Meg x 64), and 256MB (32 Meg x 64) • Nonbuffered • High-performance CMOS silicon-gate process • Single +3.3V ±0.3V power supply • All inputs, outputs and clocks are LVTTLcompatible • 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh distributed across 64ms • Extended Data-Out (EDO) PAGE MODE access cycle • Serial presence-detect (SPD) MT8LD864A X, MT16LD1664A X, MT32LD3264A X For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html PIN ASSIGNMENT (Front View) 168-Pin DIMM (H-14; 64MB) (H-17; 128MB) (H-30; 256MB) OPTIONS • Package 168-pin DIMM (gold) • Timing 50ns access 60ns access • Access Cycle EDO PAGE MODE MARKING G -5 -6 X KEY TIMING PARAMETERS SPEED -5 -6 tRC tRAC tPC tAA tCAC tCAS 84ns 104ns 50ns 60ns 20ns 25ns 25ns 30ns 13ns 15ns 8ns 10ns PART NUMBERS PART NUMBER MT8LD864AG-5 X MT8LD864AG-6 X MT16LD1664AG-5 X MT16LD1664AG-6 X MT32LD3264AG-5 X* MT32LD3264AG-6 X* CONFIGURATION 8 Meg x 64 8 Meg x 64 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 SPEED 50ns 60ns 50ns 60ns 50ns 60ns *Contact factory for availability NOTE: Pin symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. PIN SYMBOL PIN 1 VSS 43 2 DQ0 44 3 DQ1 45 4 DQ2 46 5 DQ3 47 6 VDD 48 7 DQ4 49 8 DQ5 50 9 DQ6 51 10 DQ7 52 11 DQ8 53 12 VSS 54 13 DQ9 55 14 DQ10 56 15 DQ11 57 16 DQ12 58 17 DQ13 59 18 VDD 60 19 DQ14 61 20 DQ15 62 21 NC 63 22 NC 64 23 VSS 65 24 NC 66 25 NC 67 26 VDD 68 27 WE0# 69 28 CAS0# 70 29 CAS1# 71 30 RAS0# 72 31 OE0# 73 32 VSS 74 33 A0 75 34 A2 76 35 A4 77 36 A6 78 37 A8 79 38 A10 80 39 NC (A12) 81 40 VDD 82 41 VDD 83 42 RFU 84 ** 256MB version only SYMBOL VSS OE2# RAS2# CAS2# CAS3# WE2# VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC RFU NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS NC NC NC SDA SCL VDD PIN SYMBOL PIN SYMBOL 85 VSS 127 VSS 86 DQ32 128 RFU 87 DQ33 129 NC/RAS3#** 88 DQ34 130 CAS6# 89 DQ35 131 CAS7# 90 VDD 132 RFU 91 DQ36 133 VDD 92 DQ37 134 NC 93 DQ38 135 NC 94 DQ39 136 NC 95 DQ40 137 NC 96 VSS 138 VSS 97 DQ41 139 DQ48 98 DQ42 140 DQ49 99 DQ43 141 DQ50 100 DQ44 142 DQ51 101 DQ45 143 VDD 102 VDD 144 DQ52 103 DQ46 145 NC 104 DQ47 146 RFU 105 NC 147 NC 106 NC 148 VSS 107 VSS 149 DQ53 108 NC 150 DQ54 109 NC 151 DQ55 110 VDD 152 VSS 111 RFU 153 DQ56 112 CAS4# 154 DQ57 113 CAS5# 155 DQ58 114 NC/RAS1#** 156 DQ59 115 RFU 157 VDD 116 VSS 158 DQ60 117 A1 159 DQ61 118 A3 160 DQ62 119 A5 161 DQ63 120 A7 162 VSS 121 A9 163 NC 122 A11 164 NC 123 NC (A13) 165 SA0 124 VDD 166 SA1 125 RFU 167 SA2 126 RFU 168 VDD 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. Micron is a registered trademark of Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs GENERAL DESCRIPTION The Micron® MT8LD864A X, MT16LD1664A X and MT32LD3264A X are randomly accessed 64MB, 128MB and 256MB memories organized in a x64 configuration. They are specially processed to operate from 3V to 3.6V for low-voltage memory systems. During READ or WRITE cycles, each bit is uniquely addressed through the 22/23 address bits, which are entered 12 bits (A0-A11) at RAS# time and 11/12 bits (A0-A11) at CAS# time. READ and WRITE cycles are selected with the WE# input. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# was taken LOW. During EARLY WRITE cycles, the data-outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data-outputs prior to applying input data. If a LATE WRITE or READMODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data-outputs will drive read data from the accessed location. toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z. During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also tristate the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. (Refer to the 16 Meg x 4 [MT4LC16M4H9] DRAM data sheet for additional information on EDO functionality.) REFRESH Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. Also, the chip is preconditioned for the next cycle during the RAS# HIGH time. Correct memory cell data is preserved by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (A0-A10/A11) are executed at least every tREF, regardless of sequence. The CBR REFRESH cycle will invoke the internal refresh counter for automatic RAS# addressing. EDO PAGE MODE EDO PAGE MODE is an accelerated FAST-PAGEMODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# goes back HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipeline READs. FAST-PAGE-MODE modules have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will SERIAL PRESENCE-DETECT OPERATION This module family incorporates serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various DRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide 8 unique DIMM/EEPROM addresses. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT8LD864A X (64MB) DQ0-DQ7 DQ8-DQ15 DQ16-DQ23 DQ24-DQ31 DQ0-DQ7 DQ0-DQ7 WE# WE# U2 OE# RAS# OE# RAS# A0ÐA11 CAS# DQ0-DQ7 WE# U3 OE# RAS# A0ÐA11 CAS# DQ0-DQ7 U4 WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# WE# U1 OE# RAS# CAS# A0ÐA11 CAS# A0ÐA11 12 12 12 12 A0-A11 DQ32-DQ39 DQ40-DQ47 DQ48-DQ55 DQ56-DQ63 DQ0-DQ7 DQ0-DQ7 WE# WE# U6 OE# RAS# OE# RAS# A0ÐA11 CAS# DQ0-DQ7 WE# U7 OE# RAS# A0ÐA11 CAS# DQ0-DQ7 U8 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# WE# U5 OE# RAS# CAS# A0ÐA11 CAS# A0ÐA11 12 12 12 12 SPD U1-U8 = MT4LC8M8C2 SCL A0 SA0 VDD VSS A1 SA1 A2 SA2 U1-U8 U1-U8 SDA 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT16LD1664A X (128MB) DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A11 WE# OE# RAS# CAS# A0ÐA11 U1 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U2 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U3 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U4 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U5 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U6 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U7 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U8 12 12 12 12 12 12 12 12 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# WE# OE# RAS# CAS# A0ÐA11 U9 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U10 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U11 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U12 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U13 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U14 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U15 DQ0-DQ3 WE# OE# RAS# CAS# A0ÐA11 U16 12 12 12 12 12 12 12 12 SPD SCL A0 SA0 VDD VSS A1 SA1 A2 SA2 U1-U16 U1-U16 SDA U1-U16 = MT4LC16M4H9 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT32LD3264A X (256MB) DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 DQ0-DQ3 WE# U2 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U3 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U4 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U5 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U6 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U7 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U8 OE# RAS# CAS# A0ÐA11 WE0# OE0# RAS0# CAS0# CAS1# CAS2# CAS3# A0-A11 WE# U1 OE# RAS# CAS# A0ÐA11 12 12 12 12 12 12 12 12 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 DQ0-DQ3 WE# U10 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U11 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U12 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U13 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U14 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U15 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U16 OE# RAS# CAS# A0ÐA11 WE2# OE2# RAS2# CAS4# CAS5# CAS6# CAS7# WE# U9 OE# RAS# CAS# A0ÐA11 12 12 12 12 12 12 12 12 DQ0-DQ3 DQ4-DQ7 DQ8-DQ11 DQ12-DQ15 DQ16-DQ19 DQ20-DQ23 DQ24-DQ27 DQ28-DQ31 DQ0-DQ3 WE# U17 OE# OE# DQ0-DQ3 WE# U18 DQ0-DQ3 WE# U19 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U20 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U21 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U22 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U23 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U24 OE# RAS# CAS# A0ÐA11 RAS1# RAS# CAS# A0ÐA11 RAS# CAS# A0ÐA11 12 12 12 12 12 12 12 12 DQ32-DQ35 DQ36-DQ39 DQ40-DQ43 DQ44-DQ47 DQ48-DQ51 DQ52-DQ55 DQ56-DQ59 DQ60-DQ63 DQ0-DQ3 WE# U25 OE# OE# DQ0-DQ3 WE# U26 DQ0-DQ3 WE# U27 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U28 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U29 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U30 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U31 OE# RAS# CAS# A0ÐA11 DQ0-DQ3 WE# U32 OE# RAS# CAS# A0ÐA11 RAS3# RAS# CAS# A0ÐA11 RAS# CAS# A0ÐA11 12 12 12 12 12 12 12 12 SPD SCL A0 SA0 VDD VSS U1-U32 = MT4LC16M4H9 SDA A2 SA2 U1-U32 U1-U32 A1 SA1 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS 30, 45, 114, 129 SYMBOL RAS0#-RAS3# TYPE Input DESCRIPTION Row-Address Strobe: RAS# is used to clock-in the row-address bits. Two RAS# inputs allow for one x64 bank or two x32 banks. Column-Address Strobe: CAS# is used to clock-in the column-address bits, enable the DRAM output buffers and strobe the data inputs on WRITE cycles. Eight CAS# inputs allow byte access control for any memory bank configuration. Write Enable: WE# is the READ/WRITE control for the DQ pins. WE0# controls DQ0-DQ31. WE2# controls DQ32-DQ63. If WE# is LOW prior to CAS# going LOW, the access is an EARLY WRITE cycle. If WE# is HIGH while CAS# is LOW, the access is a READ cycle, provided OE# is also LOW. If WE# goes LOW after CAS# goes LOW, then the cycle is a LATE WRITE cycle. A LATE WRITE cycle is generally used in conjunction with a READ cycle to form a READ-MODIFY-WRITE cycle. Output Enable: OE# is the input/output control for the DQ pins. OE0# controls DQ0-DQ31. OE2# controls DQ32-DQ63. These signals may be driven, allowing LATE WRITE cycles. Address Inputs: These inputs are multiplexed and clocked by RAS# and CAS#. Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to the addressed DRAM location. BYTE WRITEs may be performed by using the corresponding CAS# select (x64 mode only). For READ access cycles, DQ0-DQ63 act as outputs for the addressed DRAM location. Reserved for Future Use: These pins should be left unconnected. Power Supply: +3.3V ±0.3V. 28, 29, 46, 47, 112, 113, 130, 131 CAS0#-CAS7# Input 27, 48 WE0#, WE2# Input 31, 44 OE0#, OE2# Input 33-38, 117-122 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89,91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 42, 62, 111, 115, 125-126, 128, 132, 146 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 82 A0-A11 DQ0-DQ63 Input Input/ Output RFU VDD – Supply VSS Supply Ground. SDA Input/Output Serial Presence-Detect Data. SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. Serial Clock for Presence-Detect. SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs. These pins are used to configure the presence-detect device. 83 SCL Input 165-167 SA0-SA2 Input 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SCL SCL SDA DATA STABLE DATA CHANGE DATA STABLE SDA START BIT STOP BIT Figure 1 Data Validity Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response From Receiver 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15-61 62 63 DESCRIPTION ENTRY (VERSION) BIT7 NUMBER OF BYTES USED BY MICRON 128 1 TOTAL NUMBER OF SPD MEMORY BYTES 256 0 MEMORY TYPE EDO PAGE MODE 0 NUMBER OF ROW ADDRESSES 12 0 NUMBER OF COLUMN ADDRESSES 11 (64MB) 0 12 (128MB, 256MB) 0 NUMBER OF BANKS DATA WIDTH DATA WIDTH (continued) VOLTAGE INTERFACE RAS# ACCESS TIME (tRAC) CAS# ACCESS TIME (tCAC) MODULE CONFIGURATION TYPE REFRESH RATES DRAM WIDTH (PRIMARY DRAM) ERROR CHECKING DRAM DATA WIDTH RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 1 (64MB, 128MB) 2 (256MB) x64 NONE LVTTL 50ns (-5) 60ns (-6) 13ns (-5) 15ns (-6) NONPARITY 15.625µs/NORMAL x8 (64MB) x4 (128MB, 256MB) NONE REV. 0 64MB -5 64MB -6 128MB -5 128MB -6 256MB -5 256MB -6 MICRON 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x – BIT6 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 x 0 0 0 0 0 x x x – BIT5 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 x 0 0 0 0 0 x x x – BIT4 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 x 0 0 0 0 0 x x x – BIT3 0 1 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 x 0 0 0 0 0 x x x – BIT2 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 0 1 x 0 0 0 1 0 x x x – BIT1 0 0 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 1 0 x 0 1 1 0 0 x x x – BIT0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 x 1 0 1 0 0 x x x – HEX 80 08 02 0C 0B 0C 01 02 40 00 01 32 3C 0D 0F 00 00 08 10 00 00 00 2A 36 33 3F 34 40 2C FF 01 02 03 04 xx 01 02 03 04 00 xx xx xx – 64 65-71 72 MANUFACTURER’S JEDEC ID CODE MANUFACTURER’S JEDEC CODE (CONT.) MANUFACTURING LOCATION 73-90 91 MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE 92 93 94 95-98 99-125 IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURE SPECIFIC DATA (RSVD) 1 2 3 4 0 NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 2. x = Variable Data. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Pin Relative to VSS ........ -1V to +4.6V Voltage on Inputs or I/O Pins Relative to VSS ................................. -1V to +4.6V Operating Temperature, TA (ambient) .. 0°C to +70°C Storage Temperature (plastic) ........... -55°C to +125°C Power Dissipation ................................................... 8W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ VDD + 0.3V (All other pins not under test = 0V) CAS0#-CAS7# SYMBOL VDD VIH VIL II1 SIZE ALL ALL ALL 64MB 128MB 256MB 64MB 128MB 256MB 64MB 128MB 256MB 64MB 128MB 256MB 64MB 128MB 256MB ALL ALL MIN 3 2 -0.5 -2 -4 -8 -16 -32 -64 -8 -16 -32 -8 -16 -16 -5 -5 -10 2.4 – MAX 3.6 VDD + 0.3 0.8 2 4 8 16 32 64 8 16 32 8 16 16 5 5 10 – 0.4 UNITS NOTES V V V µA 30 30 A0-A11 II2 µA WE0#, WE2#, OE0#, OE2# RAS0#-RAS3# OUTPUT LEAKAGE CURRENT: DQ is disabled; 0V ≤ VOUT ≤ VDD + 0.3V OUTPUT LEVELS: Output High Voltage (IOUT = -2mA) Output Low Voltage (IOUT = 2mA) II3 µA II4 µA DQ0-DQ63 IOZ VOH VOL µA V V 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 5, 6) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# = VDD - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) SYMBOL SIZE ICC1 64MB 128MB 256MB 64MB 128MB 256MB -5 8 16 32 4 8 16 MAX -6 8 16 32 4 8 16 1,320 2,560 2,576 1,000 1,920 1,936 1,320 2,560 2,576 1,240 2,400 2,416 UNITS NOTES mA ICC2 mA ICC3 64MB 1,400 128MB 2,720 256MB 2,736 64MB 1,240 128MB 2,400 256MB 2,416 64MB 1,400 128MB 2,720 256MB 2,736 64MB 1,320 128MB 2,560 256MB 2,576 mA 3, 24 ICC4 mA 3, 24 ICC5 mA 3, 24 ICC6 mA 3, 4 CAPACITANCE PARAMETER Input Capacitance: A0-A11 Input Capacitance: WE0#, WE2#, OE0#, OE2# Input Capacitance: RAS0#-RAS3# Input Capacitance: CAS0#-CAS7# Input Capacitance: SCL, SA0-SA2 Input/Output Capacitance: DQ0-DQ63, SDA CI1 CI2 CI3 CI4 CI5 CIO 46 32 32 10 6 12 MAX SYMBOL 64MB 128MB 256MB UNITS NOTES 86 60 60 18 6 12 168 118 60 32 6 22 pF pF pF pF pF pF 2 2 2 2 2 2 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge during writes Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row-address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHR tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOEHC tOEP tOES tOFF tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRC tRCD tRCH tRCS -6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 10 0 3 10 5 45 5 35 10 10 0 0 10 10 5 5 0 0 25 56 50 60 12 10 60 60 104 14 0 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES MIN 12 38 0 0 42 8 8 8 0 3 8 5 38 5 30 8 8 0 0 8 5 5 4 0 0 20 47 9 9 50 50 84 11 0 0 23 14 10,000 4 15 28 35 4 23 22 22 12 12 15 15 12 15 19, 27 19 13 17 10,000 125,000 10,000 125,000 16 18 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO PAGE MODE AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 12, 29) (VDD = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Refresh period (4,096 cycles) RAS# precharge time RAS# to CAS# precharge time READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# (CAS# HIGH) WRITE command pulse width WE# pulse width for output disable when CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tREF tRP tRPC tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP -6 MAX 64 MIN 40 5 0 15 140 79 15 2 10 45 0 5 10 10 10 MAX 64 UNITS ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES MIN 30 5 0 13 116 67 13 2 8 38 0 5 10 8 8 18 23 50 50 12 15 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL VDD VIH V IL VOL I LI I LO I SB ICC MIN 3 MAX 3.6 UNITS V V V V µA µA µA mA NOTES VDD x 0.7 VDD + 0.5 -1 – – – – – VDD x 0.3 0.4 10 10 30 2 SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS (Notes: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWR MIN 0.3 4.7 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 MAX 3.5 UNITS µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms NOTES 300 28 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight RAS# REFRESH cycles (RAS#-ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 2ns for -5 and 2.5ns for -6. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10.If CAS# and RAS# = VIH, data output is High-Z. 11.If CAS# = VIL, data output may contain data from the last valid READ cycle. 12.Measured with a load equivalent to two TTL gates and 100pF and VOL = 0.8V and VOH = 2V. 13.Requires that tAA and tCAC are not violated. 14.Requires that tAA and tRAC are not violated. 15.If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. 16.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD (MAX) limit, tAA and tCAC must always be met. 17.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC and tCAC must always be met. 18.Either tRCH or tRRH must be satisfied for a READ cycle. 19. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 20.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 21.The maximum current ratings are based with the memory operating or being refreshed in the x64 mode. The stated maximums may be reduced by approximately one-half when used in the x32 mode. 22.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 23. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD and tCWD define READMODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 24.Column address changed once each cycle. 25.The 3ns minimum parameter guaranteed by design. 26.Measured with the specified current load and 100pF. 27. tOFF on an EDO module is determined by the latter of the RAS# and CAS# signals to transition HIGH. 28.The SPD EEPROM WRITE cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/ program cycle. During the WRITE cycle, the EEPROM bus interface circuit are disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 29.If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 30. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs READ CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP CAS# V IH V IL tRAD tRAH ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL tOFF tAR tASC tACH ROW tRCH tCAH tRCD tCAS tRRH tRP RAS# tASR V IH V IL ADDR COLUMN NOTE 1 OPEN tOE VALID DATA tOD OPEN OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE -6 MAX 25 MIN 15 45 0 0 13 15 10 10 0 5 12 12 45 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 0 9 9 50 84 11 0 0 30 0 13 10,000 MAX 12 50 MIN 0 12 10 60 104 14 0 0 40 0 15 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 0 5 38 0 10,000 10,000 NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EARLY WRITE CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tACH ROW tCWL tRWL tWCS tWCR tWCH tWP WE# V IH V IL tDS V DQ V IOH IOL V IH V IL tDH tRCD tCAS tRP RAS# ROW COLUMN VALID DATA OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD -6 MAX MIN 15 45 0 0 10 10 5 45 10 10 0 12 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 9 50 84 11 30 13 13 8 38 0 5 MAX 10,000 MIN 10 60 104 14 40 15 15 10 45 0 5 -6 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 38 8 8 0 9 10,000 10,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP CAS# V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tACH tASC tACH tCAH tASC tCAH tACH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# ROW tRCS COLUMN COLUMN COLUMN tRCH tRRH ROW WE# V IH V IL tAA tRAC tCAC tCLZ tAA tCPA tCAC tCOH VALID DATA tOE VALID DATA tOD tCLZ tOEHC tAA tCPA tCAC tOFF DQ V OH V OL OPEN VALID DATA tOE tOES tOEP tOD OPEN OE# V IH V IL tOES DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLZ tCOH tCP tCPA tCRP tCSH tOD tOE -6 MAX 25 MIN 15 45 0 0 13 15 10 10 0 3 10 28 35 5 12 12 45 0 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOEHC tOEP tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 5 5 4 0 20 50 9 9 50 11 0 0 30 0 13 12 10 60 14 0 0 40 0 15 MAX MIN 10 5 5 0 25 -6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 0 3 8 5 38 0 12 15 60 10,000 125,000 125,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE EARLY WRITE CYCLE tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tACH tCAH tASC tACH tCAH tASC tACH tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ROW COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP ROW tWCS tWCS tWCS WE# V IH V IL tWCR tDS tDH tDS tDH tDS tRWL tDH V DQ V IOH IOL V IH V IL VALID DATA VALID DATA VALID DATA OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS -6 MAX MIN 15 45 0 0 10 10 10 5 45 10 10 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 20 9 9 50 11 30 13 13 8 38 0 5 125,000 MAX MIN 25 12 10 60 14 40 15 15 10 45 0 5 -6 MAX UNITS ns ns 125,000 ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 8 5 38 8 8 0 10,000 10,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) t RWC t RAS V IH V IL t CSH t RSH t CRP V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC t CAH t ACH t RCD t CAS t RP RAS# CAS# ROW COLUMN t RWD t RCS t CWD t AWD t CWL t RWL t WP ROW WE# V IH V IL t AA t RAC t CAC t CLZ t DS VALID D OUT t OE V IH V IL t OD t DH V DQ V IOH IOL OPEN VALID D IN t OEH OPEN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS -6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 0 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP -5 MIN 0 8 50 9 9 50 11 0 30 13 116 67 13 5 10,000 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 10 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 42 8 8 0 5 38 30 8 8 0 10,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tRAH tRCD tCAS tCP tPC tPRWC NOTE 1 tCAS tCP tRSH tCAS tCP tRP RAS# CAS# tASR ADDR V IH V IL tASC tCAH tASC tCAH tASC tCAH ROW COLUMN tRWD tRCS tCWL tWP tAWD tCWD COLUMN COLUMN tRWL ROW tCWL tWP tAWD tCWD tAWD tCWD tCWL tWP WE# V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID D OUT VALID DIN VALID D OUT VALID D IN tAA tDH tDS tCPA tCAC tCLZ VALID D OUT VALID D IN tDH tDS DQ V IOH V IOL OPEN OPEN tOD tOE OE# V IH V IL tOE tOD tOE tOD tOEH DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS -6 MAX 25 MIN 45 0 0 49 13 15 10 10 0 10 28 35 5 45 35 10 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP -5 MIN 0 8 20 47 50 9 9 50 11 0 30 13 67 13 5 125,000 12 10 60 14 0 40 15 79 15 5 MAX 12 12 MIN 0 10 25 56 -6 MAX 15 15 UNITS ns ns ns ns ns 60 ns ns ns ns ns ns ns ns ns ns ns MIN 38 0 0 42 8 8 0 8 5 38 30 8 8 0 10,000 125,000 NOTE: 1. tPC is for LATE WRITE cycles only. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# V IH V IL t CSH tPC tCRP CAS# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH ROW tASC tCAH t ASC t CAH tASC t ACH t CAH t RCD t CAS t CP t CAS tPC t CP t CAS tRSH t CP t RP COLUMN (A) tRCS COLUMN (B) tRCH COLUMN (N) tWCS tWCH ROW WE# V IH V IL tRAC tAA tCPA tCAC tAA tCAC tCOH t WHZ VALID DATA (B) t DS t DH DQ V IOH V IOL V IH V IL OPEN tOE VALID DATA (A) VALID DATA IN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCOH tCP tCPA tCRP tCSH tDH tDS -6 MAX 25 MIN 15 45 0 0 13 15 10 10 3 10 28 35 5 45 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ -5 MIN 20 50 9 9 50 11 0 0 30 13 8 0 12 125,000 12 10 60 14 0 0 40 15 10 0 MAX 12 25 MIN -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns 15 ns MIN 12 38 0 0 8 8 3 8 5 38 8 0 125,000 10,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs EDO READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tCRP CAS# V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tASC tRCD tCAS tCP ADDR ROW tRCS COLUMN tRCH tWPZ tRCS COLUMN WE# V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ DQ V OH V OL OPEN tOE VALID DATA tOD OPEN OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH -6 MAX 25 MIN 45 0 0 13 15 10 10,000 10 0 10 5 45 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ -5 MIN 0 MAX 12 12 50 9 9 11 0 0 12 10 10 12 10 14 0 0 MIN 0 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns MIN 38 0 0 8 8 0 8 5 38 15 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs RAS#-ONLY REFRESH CYCLE tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP RAS# CAS# ROW ROW V DQ V OH OL V IH V IL OPEN WE# CBR REFRESH CYCLE (Addresses, OE# = DON’T CARE) tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS DQ DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH -6 MAX MIN 0 10 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC tRP tRPC tWRH tWRP -5 MIN 50 84 30 5 8 8 MAX 10,000 MIN 60 104 40 5 10 10 -6 MAX 10,000 UNITS ns ns ns ns ns ns MIN 0 8 8 5 5 9 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs HIDDEN REFRESH CYCLE 20 (WE# = HIGH; OE# = LOW) tRC tRAS RAS# V IH V IL tCRP CAS# V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS ADDR ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V IOH IOL OPEN VALID DATA OPEN DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD tOE -6 MAX 25 MIN 45 0 0 13 15 10 10 0 12 12 5 0 15 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tORD tRAC tRAD tRAH tRAS tRC tRCD tRP tRSH -5 MIN 0 0 50 9 9 50 84 11 30 13 12 10 60 104 14 40 15 MAX 12 MIN 0 0 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns MIN 38 0 0 8 8 0 5 0 10,000 10,000 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SPD EEPROM tF t LOW t HIGH tR SCL t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA MIN 0.3 4.7 300 0 4 MAX 3.5 UNITS µs µs ns ns µs µs SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO MIN 4 4.7 250 4.7 4.7 MAX UNITS µs µs µs ns µs µs 1 300 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs 168-PIN DIMM DF-16 (64MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .200 (5.08) MAX .079 (2.00) R (2X) 1.105 (28.07) 1.095 (27.81) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) TYP .050 (1.27) TYP .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78) TYP PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) PIN 84 (PIN 168 ON BACKSIDE) 168-PIN DIMM DF-27 (128MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX .079 (2.00) R (2X) 1.255 (31.88) 1.245 (31.62) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) TYP .050 (1.27) TYP .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) .700 (17.78) TYP PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) PIN 84 (PIN 168 ON BACKSIDE) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs 168-PIN DIMM DF-41 (256MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .350 (8.89) MAX .079 (2.00) R (2X) 2.005 (51.93) 1.995 (50.67) .118 (3.00) (2X) .118 (3.00) TYP .250 (6.35) TYP .118 (3.00) TYP 1.661 (42.18) 2.625 (66.68) .039 (1.00)R (2X) .039 (1.00) TYP .050 (1.27) TYP .700 (17.78) TYP .128 (3.25) (2X) .118 (3.00) .054 (1.37) .046 (1.17) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) PIN 84 (PIN 168 ON BACKSIDE) NOTE: All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs DM78.p65 – Rev. 2/99 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.