16Gb: x4, x8, x16 DDR4 SDRAM
Features
DDR4 SDRAM
MT40A4G4
MT40A2G8
MT40A1G16
Options1
Features
•
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•
•
•
•
•
•
•
•
•
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•
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•
Marking
• Configuration
– 4 Gig x 4
– 2 Gig x 8
– 1 Gig x 16
• 78-ball FBGA package (Pb-free) – x4, x8
– 10mm x 11mm – Rev. B
– 9mm x 11mm – Rev. E
• 96-ball FBGA package (Pb-free) – x16
– 10mm x 13mm – Rev. B
– 9mm x 13mm – Rev. E
• Timing – cycle time
– 0.625ns @ CL = 22 (DDR4-3200)
– 0.682ns @ CL = 21 (DDR4-2933)
• Operating temperature
– Commercial (0° ื T C ื 95°C)
– Industrial (–40° ื T C ื 95°C)
• Revision
VDD = V DDQ = 1.2V ±60mV
VPP = 2.5V, –125mV, +250mV
On-die, internal, adjustable V REFDQ generation
1.2V pseudo open-drain I/O
TC maximum up to 95°C
– 64ms, 8192-cycle refresh up to 85°C
– 32ms, 8192-cycle refresh at >85°C to 95°C
16 internal banks (x4, x8): 4 groups of 4 banks each
8 internal banks (x16): 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
JEDEC JESD-79-4 compliant
sPPR and hPPR capability
Note:
4G4
2G8
1G16
VA
JC
RC
KD
-062E
-068
None
IT
:B, :E
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade1
Data Rate (MT/s)
Target CL-nRCD-nRP
-062E
3200
22-22-22
13.75
13.75
13.75
-068
2933
21-21-21
14.32 (13.75)
14.32 (13.75)
14.32 (13.75)
Note:
tAA
(ns)
tRCD
(ns)
tRP
(ns)
1. Refer to the Speed Bin Tables for additional details.
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1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page
size1
Note:
4096 Meg x 4
2048 Meg x 8
1024 Meg x 16
4
4
2
BG[1:0]
BG[1:0]
BG0
4
4
4
BA[1:0]
BA[1:0]
BA[1:0]
256K (A[17:0])
128K (A[16:0])
128K (A[16:0])
1K (A[9:0])
1K (A[9:0])
1K (A[9:0])
512B
1KB
2KB
1. Page size is per bank, calculated as follows:
Page size = 2COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 1: Order Part Number Example
Example Part Number: MT40A2G8VA-068:B
Configuration
Package
Revision
Speed
{
MT40A
:
Revision
Configuration
4 Gig x 4
4G4
2 Gig x 8
2G8
1 Gig x 16
1G16
:B, :E
Case Temperature
Commercial
Package
VA
96-ball 10.0mm x 13.0mm FBGA
RC
78-ball 9.0mm x 11.0mm FBGA
JC
96-ball 9.0mm x 13.0mm FBGA
KD
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Industrial temperature
Mark
78-ball 10.0mm x 11.0mm FBGA
None
Speed Grade
-068
-062E
3
IT
Cycle Time, CAS Latency
t CK = 0.682ns, CL = 21
t CK = 0.625ns, CL = 22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Contents
Important Notes and Warnings .......................................................................................................................
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
Automotive Temperature ............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Functional Block Diagrams .............................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery (WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT RTT(NOM) Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
Rx CTLE Control .........................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Hard Post Package Repair Mode ..................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
WRITE Preamble ........................................................................................................................................
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60
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
READ Preamble .......................................................................................................................................... 60
READ Preamble Training ............................................................................................................................ 60
Temperature-Controlled Refresh ................................................................................................................. 60
Command Address Latency ........................................................................................................................ 60
Internal V REF Monitor ................................................................................................................................. 60
Maximum Power Savings Mode ................................................................................................................... 61
Mode Register 5 .............................................................................................................................................. 62
Data Bus Inversion ..................................................................................................................................... 63
Data Mask .................................................................................................................................................. 64
CA Parity Persistent Error Mode .................................................................................................................. 64
ODT Input Buffer for Power-Down .............................................................................................................. 64
CA Parity Error Status ................................................................................................................................. 64
CRC Error Status ......................................................................................................................................... 64
CA Parity Latency Mode .............................................................................................................................. 64
Mode Register 6 .............................................................................................................................................. 65
Data Rate Programming .............................................................................................................................. 66
VREFDQ Calibration Enable .......................................................................................................................... 66
VREFDQ Calibration Range ........................................................................................................................... 66
VREFDQ Calibration Value ............................................................................................................................ 66
Truth Tables ................................................................................................................................................... 67
NOP Command .............................................................................................................................................. 70
DESELECT Command .................................................................................................................................... 70
DLL-Off Mode ................................................................................................................................................ 70
DLL-On/Off Switching Procedures .................................................................................................................. 72
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 72
DLL-Off to DLL-On Procedure .................................................................................................................... 74
Input Clock Frequency Change ....................................................................................................................... 75
Write Leveling ................................................................................................................................................ 76
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 77
Procedure Description ................................................................................................................................ 78
Write Leveling Mode Exit ............................................................................................................................ 79
Command Address Latency ............................................................................................................................ 81
Low-Power Auto Self Refresh Mode ................................................................................................................. 86
Manual Self Refresh Mode .......................................................................................................................... 86
Multipurpose Register .................................................................................................................................... 88
MPR Reads ................................................................................................................................................. 89
MPR Readout Format ................................................................................................................................. 91
MPR Readout Serial Format ........................................................................................................................ 91
MPR Readout Parallel Format ..................................................................................................................... 92
MPR Readout Staggered Format .................................................................................................................. 93
MPR READ Waveforms ............................................................................................................................... 94
MPR Writes ................................................................................................................................................ 96
MPR WRITE Waveforms .............................................................................................................................. 97
MPR REFRESH Waveforms ......................................................................................................................... 98
Gear-Down Mode .......................................................................................................................................... 101
Maximum Power-Saving Mode ....................................................................................................................... 104
Maximum Power-Saving Mode Entry .......................................................................................................... 104
Maximum Power-Saving Mode Entry in PDA .............................................................................................. 105
CKE Transition During Maximum Power-Saving Mode ................................................................................ 105
Maximum Power-Saving Mode Exit ............................................................................................................ 105
Command/Address Parity .............................................................................................................................. 107
Per-DRAM Addressability .............................................................................................................................. 115
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16Gb: x4, x8, x16 DDR4 SDRAM
Features
VREFDQ Calibration ........................................................................................................................................ 118
VREFDQ Range and Levels ........................................................................................................................... 119
VREFDQ Step Size ........................................................................................................................................ 119
VREFDQ Increment and Decrement Timing .................................................................................................. 120
VREFDQ Target Settings ............................................................................................................................... 124
Connectivity Test Mode ................................................................................................................................. 126
Pin Mapping ............................................................................................................................................. 126
Minimum Terms Definition for Logic Equations ......................................................................................... 127
Logic Equations for a x4 Device .................................................................................................................. 127
Logic Equations for a x8 Device .................................................................................................................. 128
Logic Equations for a x16 Device ................................................................................................................ 128
CT Input Timing Requirements .................................................................................................................. 128
Excessive Row Activation ............................................................................................................................... 130
Post Package Repair ....................................................................................................................................... 131
Post Package Repair ................................................................................................................................... 131
Hard Post Package Repair .............................................................................................................................. 132
hPPR Row Repair - Entry ............................................................................................................................ 132
hPPR Row Repair – WRA Initiated (REF Commands Allowed) ...................................................................... 132
hPPR Row Repair – WR Initiated (REF Commands NOT Allowed) ................................................................. 134
sPPR Row Repair ........................................................................................................................................... 136
hPPR/sPPR Support Identifier ........................................................................................................................ 139
ACTIVATE Command .................................................................................................................................... 139
PRECHARGE Command ................................................................................................................................ 140
REFRESH Command ..................................................................................................................................... 140
Temperature-Controlled Refresh Mode .......................................................................................................... 143
Normal Temperature Mode ........................................................................................................................ 143
Extended Temperature Mode ..................................................................................................................... 143
Fine Granularity Refresh Mode ....................................................................................................................... 146
Mode Register and Command Truth Table .................................................................................................. 146
tREFI and tRFC Parameters ........................................................................................................................ 146
Changing Refresh Rate ............................................................................................................................... 149
Usage with TCR Mode ................................................................................................................................ 149
Self Refresh Entry and Exit ......................................................................................................................... 149
SELF REFRESH Operation .............................................................................................................................. 151
Self Refresh Abort ...................................................................................................................................... 153
Self Refresh Exit with NOP Command ......................................................................................................... 154
Power-Down Mode ........................................................................................................................................ 156
Power-Down Clarifications – Case 1 ........................................................................................................... 161
Power-Down Entry, Exit Timing with CAL ................................................................................................... 162
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 164
CRC Write Data Feature ................................................................................................................................. 166
CRC Write Data ......................................................................................................................................... 166
WRITE CRC DATA Operation ...................................................................................................................... 166
DBI_n and CRC Both Enabled .................................................................................................................... 167
DM_n and CRC Both Enabled .................................................................................................................... 167
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 167
CRC and Write Preamble Restrictions ......................................................................................................... 167
CRC Simultaneous Operation Restrictions .................................................................................................. 167
CRC Polynomial ........................................................................................................................................ 167
CRC Combinatorial Logic Equations .......................................................................................................... 168
Burst Ordering for BL8 ............................................................................................................................... 169
CRC Data Bit Mapping ............................................................................................................................... 169
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16Gb: x4, x8, x16 DDR4 SDRAM
Features
CRC Enabled With BC4 .............................................................................................................................. 170
CRC with BC4 Data Bit Mapping ................................................................................................................ 170
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 173
CRC Error Handling ................................................................................................................................... 174
CRC Write Data Flow Diagram ................................................................................................................... 176
Data Bus Inversion ........................................................................................................................................ 177
DBI During a WRITE Operation .................................................................................................................. 177
DBI During a READ Operation ................................................................................................................... 178
Data Mask ..................................................................................................................................................... 179
Programmable Preamble Modes and DQS Postambles .................................................................................... 181
WRITE Preamble Mode .............................................................................................................................. 181
READ Preamble Mode ............................................................................................................................... 184
READ Preamble Training ........................................................................................................................... 184
WRITE Postamble ...................................................................................................................................... 185
READ Postamble ....................................................................................................................................... 185
Bank Access Operation .................................................................................................................................. 187
READ Operation ............................................................................................................................................ 191
Read Timing Definitions ............................................................................................................................ 191
Read Timing – Clock-to-Data Strobe Relationship ....................................................................................... 192
Read Timing – Data Strobe-to-Data Relationship ........................................................................................ 194
tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations ............................................................................ 195
tRPRE Calculation ..................................................................................................................................... 196
tRPST Calculation ...................................................................................................................................... 197
READ Burst Operation ............................................................................................................................... 198
READ Operation Followed by Another READ Operation .............................................................................. 200
READ Operation Followed by WRITE Operation .......................................................................................... 205
READ Operation Followed by PRECHARGE Operation ................................................................................ 211
READ Operation with Read Data Bus Inversion (DBI) .................................................................................. 214
READ Operation with Command/Address Parity (CA Parity) ........................................................................ 215
READ Followed by WRITE with CRC Enabled .............................................................................................. 217
READ Operation with Command/Address Latency (CAL) Enabled ............................................................... 218
WRITE Operation .......................................................................................................................................... 220
Write Timing Definitions ........................................................................................................................... 220
Write Timing – Clock-to-Data Strobe Relationship ...................................................................................... 220
tWPRE Calculation .................................................................................................................................... 222
tWPST Calculation ..................................................................................................................................... 223
Write Timing – Data Strobe-to-Data Relationship ........................................................................................ 223
WRITE Burst Operation ............................................................................................................................. 227
WRITE Operation Followed by Another WRITE Operation ........................................................................... 229
WRITE Operation Followed by READ Operation .......................................................................................... 235
WRITE Operation Followed by PRECHARGE Operation ............................................................................... 239
WRITE Operation with WRITE DBI Enabled ................................................................................................ 242
WRITE Operation with CA Parity Enabled ................................................................................................... 244
WRITE Operation with Write CRC Enabled ................................................................................................. 245
Write Timing Violations ................................................................................................................................. 250
Motivation ................................................................................................................................................ 250
Data Setup and Hold Violations ................................................................................................................. 250
Strobe-to-Strobe and Strobe-to-Clock Violations ........................................................................................ 250
ZQ CALIBRATION Commands ....................................................................................................................... 251
On-Die Termination ...................................................................................................................................... 253
ODT Mode Register and ODT State Table ........................................................................................................ 253
ODT Read Disable State Table .................................................................................................................... 254
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Synchronous ODT Mode ................................................................................................................................ 255
ODT Latency and Posted ODT .................................................................................................................... 255
Timing Parameters .................................................................................................................................... 255
ODT During Reads .................................................................................................................................... 257
Dynamic ODT ............................................................................................................................................... 258
Functional Description .............................................................................................................................. 258
Asynchronous ODT Mode .............................................................................................................................. 261
Electrical Specifications ................................................................................................................................. 262
Absolute Ratings ........................................................................................................................................ 262
DRAM Component Operating Temperature Range ...................................................................................... 262
Electrical Characteristics – AC and DC Operating Conditions .......................................................................... 263
Supply Operating Conditions ..................................................................................................................... 263
Leakages ................................................................................................................................................... 264
VREFCA Supply ............................................................................................................................................ 264
VREFDQ Supply and Calibration Ranges ....................................................................................................... 265
VREFDQ Ranges ........................................................................................................................................... 266
Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels .............................................. 267
RESET_n Input Levels ................................................................................................................................ 267
Command/Address Input Levels ................................................................................................................ 267
Command, Control, and Address Setup, Hold, and Derating ........................................................................ 269
Data Receiver Input Requirements ............................................................................................................. 271
Connectivity Test (CT) Mode Input Levels .................................................................................................. 275
Electrical Characteristics – AC and DC Differential Input Measurement Levels ................................................. 279
Differential Inputs ..................................................................................................................................... 279
Single-Ended Requirements for CK Differential Signals ............................................................................... 280
Slew Rate Definitions for CK Differential Input Signals ................................................................................ 281
CK Differential Input Cross Point Voltage .................................................................................................... 282
DQS Differential Input Signal Definition and Swing Requirements .............................................................. 283
DQS Differential Input Cross Point Voltage ................................................................................................. 285
Slew Rate Definitions for DQS Differential Input Signals .............................................................................. 286
Electrical Characteristics – Overshoot and Undershoot Specifications ............................................................. 288
Address, Command, and Control Overshoot and Undershoot Specifications ................................................ 288
Clock Overshoot and Undershoot Specifications ......................................................................................... 289
Data, Strobe, and Mask Overshoot and Undershoot Specifications .............................................................. 290
Electrical Characteristics – AC and DC Output Measurement Levels ................................................................ 290
Single-Ended Outputs ............................................................................................................................... 290
Differential Outputs .................................................................................................................................. 292
Reference Load for AC Timing and Output Slew Rate ................................................................................... 293
Connectivity Test Mode Output Levels ........................................................................................................ 294
Electrical Characteristics – AC and DC Output Driver Characteristics ............................................................... 295
Connectivity Test Mode Output Driver Electrical Characteristics ................................................................. 295
Output Driver Electrical Characteristics ..................................................................................................... 297
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 300
Alert Driver ............................................................................................................................................... 300
Electrical Characteristics – On-Die Termination Characteristics ...................................................................... 301
ODT Levels and I-V Characteristics ............................................................................................................ 301
ODT Temperature and Voltage Sensitivity ................................................................................................... 303
ODT Timing DefinitionsODT Timing Definitions and Waveforms ................................................................ 303
DRAM Package Electrical Specifications ......................................................................................................... 307
Thermal Characteristics ................................................................................................................................. 311
Current Specifications – Measurement Conditions .......................................................................................... 312
IDD, IPP, and IDDQ Measurement Conditions ................................................................................................ 312
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
IDD Definitions .......................................................................................................................................... 314
Current Specifications – Patterns and Test Conditions ..................................................................................... 318
Current Test Definitions and Patterns ......................................................................................................... 318
IDD Specifications ...................................................................................................................................... 327
Current Specifications – Limits ....................................................................................................................... 328
Speed Bin Tables ........................................................................................................................................... 333
Backward Compatibility ............................................................................................................................ 333
Refresh Parameters By Device Density ............................................................................................................ 352
Electrical Characteristics and AC Timing Parameters ...................................................................................... 353
Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 ........................................................ 365
Converting Time-Based Specifications to Clock-Based Requirements .............................................................. 376
Options Tables .............................................................................................................................................. 378
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16Gb: x4, x8, x16 DDR4 SDRAM
Features
List of Figures
Figure 1: Order Part Number Example .............................................................................................................. 3
Figure 2: 4 Gig x 4 Functional Block Diagram .................................................................................................. 22
Figure 3: 2 Gig x 8 Functional Block Diagram .................................................................................................. 22
Figure 4: 1 Gig x 16 Functional Block Diagram ................................................................................................ 23
Figure 5: 78-Ball x4, x8 Ball Assignments ........................................................................................................ 24
Figure 6: 96-Ball x16 Ball Assignments ............................................................................................................ 25
Figure 7: 78-Ball FBGA – x4, x8 (VA) ................................................................................................................ 29
Figure 8: 78-Ball FBGA – x4, x8 (JC) ................................................................................................................ 30
Figure 9: 96-Ball FBGA – x16 (RC) ................................................................................................................... 31
Figure 10: 96-Ball FBGA – x16 (KD) ................................................................................................................. 32
Figure 11: Simplified State Diagram ............................................................................................................... 33
Figure 12: RESET and Initialization Sequence at Power-On Ramping ............................................................... 39
Figure 13: RESET Procedure at Power Stable Condition ................................................................................... 40
Figure 14: tMRD Timing ................................................................................................................................ 42
Figure 15: tMOD Timing ................................................................................................................................ 42
Figure 16: DLL-Off Mode Read Timing Operation ........................................................................................... 71
Figure 17: DLL Switch Sequence from DLL-On to DLL-Off .............................................................................. 73
Figure 18: DLL Switch Sequence from DLL-Off to DLL-On .............................................................................. 74
Figure 19: Write Leveling Concept, Example 1 ................................................................................................ 76
Figure 20: Write Leveling Concept, Example 2 ................................................................................................ 77
Figure 21: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) .................................. 79
Figure 22: Write Leveling Exit ......................................................................................................................... 80
Figure 23: CAL Timing Definition ................................................................................................................... 81
Figure 24: CAL Timing Example (Consecutive CS_n = LOW) ............................................................................ 81
Figure 25: CAL Enable Timing – tMOD_CAL ................................................................................................... 82
Figure 26: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled ....................................................... 82
Figure 27: CAL Enabling MRS to Next MRS Command, tMRD_CAL .................................................................. 83
Figure 28: tMRD_CAL, Mode Register Cycle Time With CAL Enabled ............................................................... 83
Figure 29: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group ............................................... 84
Figure 30: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group ............................................... 84
Figure 31: Auto Self Refresh Ranges ................................................................................................................ 87
Figure 32: MPR Block Diagram ....................................................................................................................... 88
Figure 33: MPR READ Timing ........................................................................................................................ 94
Figure 34: MPR Back-to-Back READ Timing ................................................................................................... 95
Figure 35: MPR READ-to-WRITE Timing ........................................................................................................ 96
Figure 36: MPR WRITE and WRITE-to-READ Timing ...................................................................................... 97
Figure 37: MPR Back-to-Back WRITE Timing .................................................................................................. 98
Figure 38: REFRESH Timing ........................................................................................................................... 98
Figure 39: READ-to-REFRESH Timing ............................................................................................................ 99
Figure 40: WRITE-to-REFRESH Timing .......................................................................................................... 99
Figure 41: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) ......................................................... 102
Figure 42: Clock Mode Change After Exiting Self Refresh ................................................................................ 102
Figure 43: Comparison Between Gear-Down Disable and Gear-Down Enable ................................................. 103
Figure 44: Maximum Power-Saving Mode Entry ............................................................................................. 104
Figure 45: Maximum Power-Saving Mode Entry with PDA .............................................................................. 105
Figure 46: Maintaining Maximum Power-Saving Mode with CKE Transition ................................................... 105
Figure 47: Maximum Power-Saving Mode Exit ............................................................................................... 106
Figure 48: Command/Address Parity Operation ............................................................................................. 107
Figure 49: Command/Address Parity During Normal Operation ..................................................................... 109
Figure 50: Persistent CA Parity Error Checking Operation ............................................................................... 110
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 51: CA Parity Error Checking – SRE Attempt ........................................................................................ 110
Figure 52: CA Parity Error Checking – SRX Attempt ........................................................................................ 111
Figure 53: CA Parity Error Checking – PDE/PDX ............................................................................................ 111
Figure 54: Parity Entry Timing Example – tMRD_PAR ..................................................................................... 112
Figure 55: Parity Entry Timing Example – tMOD_PAR ..................................................................................... 112
Figure 56: Parity Exit Timing Example – tMRD_PAR ....................................................................................... 112
Figure 57: Parity Exit Timing Example – tMOD_PAR ....................................................................................... 113
Figure 58: CA Parity Flow Diagram ................................................................................................................ 114
Figure 59: PDA Operation Enabled, BL8 ........................................................................................................ 116
Figure 60: PDA Operation Enabled, BC4 ........................................................................................................ 116
Figure 61: MRS PDA Exit ............................................................................................................................... 117
Figure 62: V REFDQ Voltage Range ................................................................................................................... 118
Figure 63: Example of V REF Set Tolerance and Step Size .................................................................................. 120
Figure 64: V REFDQ Timing Diagram for V REF,time Parameter .............................................................................. 121
Figure 65: V REFDQ Training Mode Entry and Exit Timing Diagram ................................................................... 122
Figure 66: V REF Step: Single Step Size Increment Case .................................................................................... 123
Figure 67: V REF Step: Single Step Size Decrement Case ................................................................................... 123
Figure 68: V REF Full Step: From V REF,min to V REF,maxCase .................................................................................. 124
Figure 69: V REF Full Step: From V REF,max to V REF,minCase .................................................................................. 124
Figure 70: V REFDQ Equivalent Circuit ............................................................................................................. 125
Figure 71: Connectivity Test Mode Entry ....................................................................................................... 129
Figure 72: hPPR WRA – Entry ........................................................................................................................ 134
Figure 73: hPPR WRA – Repair and Exit ......................................................................................................... 134
Figure 74: hPPR WR – Entry .......................................................................................................................... 135
Figure 75: hPPR WR – Repair and Exit ............................................................................................................ 135
Figure 76: sPPR – Entry ................................................................................................................................. 138
Figure 77: sPPR – Repair, and Exit ................................................................................................................. 138
Figure 78: tRRD Timing ................................................................................................................................ 139
Figure 79: tFAW Timing ................................................................................................................................. 140
Figure 80: REFRESH Command Timing ......................................................................................................... 141
Figure 81: Postponing REFRESH Commands (Example) ................................................................................. 142
Figure 82: Pulling In REFRESH Commands (Example) ................................................................................... 142
Figure 83: TCR Mode Example 1 ..................................................................................................................... 145
Figure 84: 4Gb with Fine Granularity Refresh Mode Example ......................................................................... 148
Figure 85: OTF REFRESH Command Timing ................................................................................................. 149
Figure 86: Self Refresh Entry/Exit Timing ...................................................................................................... 152
Figure 87: Self Refresh Entry/Exit Timing with CAL Mode ............................................................................... 153
Figure 88: Self Refresh Abort ......................................................................................................................... 154
Figure 89: Self Refresh Exit with NOP Command ............................................................................................ 155
Figure 90: Active Power-Down Entry and Exit ................................................................................................ 157
Figure 91: Power-Down Entry After Read and Read with Auto Precharge ......................................................... 158
Figure 92: Power-Down Entry After Write and Write with Auto Precharge ........................................................ 158
Figure 93: Power-Down Entry After Write ...................................................................................................... 159
Figure 94: Precharge Power-Down Entry and Exit .......................................................................................... 159
Figure 95: REFRESH Command to Power-Down Entry ................................................................................... 160
Figure 96: Active Command to Power-Down Entry ......................................................................................... 160
Figure 97: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry .................................................. 161
Figure 98: MRS Command to Power-Down Entry ........................................................................................... 161
Figure 99: Power-Down Entry/Exit Clarifications – Case 1 .............................................................................. 162
Figure 100: Active Power-Down Entry and Exit Timing with CAL .................................................................... 162
Figure 101: REFRESH Command to Power-Down Entry with CAL ................................................................... 163
Figure 102: ODT Power-Down Entry with ODT Buffer Disable Mode .............................................................. 164
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
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Figure 154:
ODT Power-Down Exit with ODT Buffer Disable Mode ................................................................. 165
CRC Write Data Operation .......................................................................................................... 166
CRC Error Reporting ................................................................................................................... 175
CA Parity Flow Diagram .............................................................................................................. 176
1tCK vs. 2tCK WRITE Preamble Mode ........................................................................................... 181
1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 ............................................................................ 182
1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 ............................................................................ 183
1tCK vs. 2 tCK WRITE Preamble Mode, tCCD = 6 ........................................................................... 183
1tCK vs. 2tCK READ Preamble Mode ............................................................................................ 184
READ Preamble Training ............................................................................................................. 185
WRITE Postamble ....................................................................................................................... 185
READ Postamble ........................................................................................................................ 186
Bank Group x4/x8 Block Diagram ................................................................................................ 187
READ Burst tCCD_S and tCCD_L Examples .................................................................................. 188
Write Burst tCCD_S and tCCD_L Examples ................................................................................... 188
tRRD Timing ............................................................................................................................... 189
tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) ......................... 189
tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) .............................. 190
Read Timing Definition ............................................................................................................... 192
Clock-to-Data Strobe Relationship .............................................................................................. 193
Data Strobe-to-Data Relationship ................................................................................................ 194
tLZ and tHZ Method for Calculating Transitions and Endpoints .................................................... 195
tRPRE Method for Calculating Transitions and Endpoints ............................................................. 196
tRPST Method for Calculating Transitions and Endpoints ............................................................. 197
READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) ................................................................... 198
READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) ................................................................. 199
Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group .......................................... 200
Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group .......................................... 200
Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group ....................... 201
Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group ....................... 201
READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group ...................................... 202
READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group ...................................... 202
READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group ............................... 203
READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group ............................... 203
READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group ............................... 204
READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group ............................... 204
READ (BL8) to WRITE (BL8) with 1 tCK Preamble in Same or Different Bank Group ........................ 205
READ (BL8) to WRITE (BL8) with 2 tCK Preamble in Same or Different Bank Group ........................ 205
READ (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Same or Different Bank Group ......... 206
READ (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Same or Different Bank Group ......... 207
READ (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Same or Different Bank Group ..... 207
READ (BC4) Fixed to WRITE (BC4) Fixed with 2 tCK Preamble in Same or Different Bank Group ..... 208
READ (BC4) to WRITE (BL8) OTF with 1 tCK Preamble in Same or Different Bank Group ................ 209
READ (BC4) to WRITE (BL8) OTF with 2 tCK Preamble in Same or Different Bank Group ................ 209
READ (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Same or Different Bank Group ................ 210
READ (BL8) to WRITE (BC4) OTF with 2 tCK Preamble in Same or Different Bank Group ................ 210
READ to PRECHARGE with 1tCK Preamble .................................................................................. 211
READ to PRECHARGE with 2tCK Preamble .................................................................................. 212
READ to PRECHARGE with Additive Latency and 1tCK Preamble .................................................. 212
READ with Auto Precharge and 1tCK Preamble ............................................................................ 213
READ with Auto Precharge, Additive Latency, and 1tCK Preamble ................................................. 214
Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group ............................ 214
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Figure 155: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group .................... 215
Figure 156: READ (BL8) to WRITE (BL8) with 1 tCK Preamble and CA Parity in Same or Different Bank Group ... 216
Figure 157: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 217
Figure 158: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 218
Figure 159: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group .................. 218
Figure 160: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group .................. 219
Figure 161: Write Timing Definition .............................................................................................................. 221
Figure 162: tWPRE Method for Calculating Transitions and Endpoints ............................................................ 222
Figure 163: tWPST Method for Calculating Transitions and Endpoints ............................................................ 223
Figure 164: Rx Compliance Mask .................................................................................................................. 224
Figure 165: V CENT_DQ VREFDQ Voltage Variation .............................................................................................. 224
Figure 166: Rx Mask DQ-to-DQS Timings ...................................................................................................... 225
Figure 167: Rx Mask DQ-to-DQS DRAM-Based Timings ................................................................................. 226
Figure 168: Example of Data Input Requirements Without Training ................................................................ 227
Figure 169: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) ................................................................. 228
Figure 170: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) ............................................................. 229
Figure 171: Consecutive WRITE (BL8) with 1 tCK Preamble in Different Bank Group ........................................ 229
Figure 172: Consecutive WRITE (BL8) with 2 tCK Preamble in Different Bank Group ........................................ 230
Figure 173: Nonconsecutive WRITE (BL8) with 1 tCK Preamble in Same or Different Bank Group ..................... 231
Figure 174: Nonconsecutive WRITE (BL8) with 2 tCK Preamble in Same or Different Bank Group ..................... 231
Figure 175: WRITE (BC4) OTF to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group .................... 232
Figure 176: WRITE (BC4) OTF to WRITE (BC4) OTF with 2 tCK Preamble in Different Bank Group .................... 233
Figure 177: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 233
Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1 tCK Preamble in Different Bank Group ............................ 234
Figure 179: WRITE (BC4) OTF to WRITE (BL8) with 1 tCK Preamble in Different Bank Group ............................ 235
Figure 180: WRITE (BL8) to READ (BL8) with 1 tCK Preamble in Different Bank Group ..................................... 235
Figure 181: WRITE (BL8) to READ (BL8) with 1 tCK Preamble in Same Bank Group .......................................... 236
Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1 tCK Preamble in Different Bank Group ...................... 237
Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1 tCK Preamble in Same Bank Group ........................... 237
Figure 184: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group ................. 238
Figure 185: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Same Bank Group ....................... 238
Figure 186: WRITE (BL8/BC4-OTF) to PRECHARGE with 1 tCK Preamble ........................................................ 239
Figure 187: WRITE (BC4-Fixed) to PRECHARGE with 1 tCK Preamble .............................................................. 240
Figure 188: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1 tCK Preamble ................................................ 240
Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1 tCK Preamble ...................................................... 241
Figure 190: WRITE (BL8/BC4-OTF) with 1 tCK Preamble and DBI ................................................................... 242
Figure 191: WRITE (BC4-Fixed) with 1 tCK Preamble and DBI ......................................................................... 243
Figure 192: Consecutive Write (BL8) with 1 tCK Preamble and CA Parity in Different Bank Group ..................... 244
Figure 193: Consecutive WRITE (BL8/BC4-OTF) with 1 tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 245
Figure 194: Consecutive WRITE (BC4-Fixed) with 1 tCK Preamble and Write CRC in Same or Different Bank
Group ....................................................................................................................................................... 246
Figure 195: Nonconsecutive WRITE (BL8/BC4-OTF) with 1 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 247
Figure 196: Nonconsecutive WRITE (BL8/BC4-OTF) with 2 tCK Preamble and Write CRC in Same or Different
Bank Group ............................................................................................................................................... 248
Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1 tCK Preamble and Write CRC in Same or Different Bank Group ...
249
Figure 198: ZQ Calibration Timing ................................................................................................................ 252
Figure 199: Functional Representation of ODT .............................................................................................. 253
Figure 200: Synchronous ODT Timing with BL8 ............................................................................................. 256
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
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Figure 243:
Synchronous ODT with BC4 ........................................................................................................ 256
ODT During Reads ...................................................................................................................... 257
Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......................... 259
Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) .......... 260
Asynchronous ODT Timings with DLL Off ................................................................................... 261
V REFDQ Voltage Range .................................................................................................................. 264
RESET_n Input Slew Rate Definition ............................................................................................ 267
Single-Ended Input Slew Rate Definition ..................................................................................... 269
DQ Slew Rate Definitions ............................................................................................................ 272
Rx Mask Relative to tDS/tDH ....................................................................................................... 274
Rx Mask Without Write Training .................................................................................................. 275
TEN Input Slew Rate Definition ................................................................................................... 276
CT Type-A Input Slew Rate Definition .......................................................................................... 276
CT Type-B Input Slew Rate Definition .......................................................................................... 277
CT Type-C Input Slew Rate Definition .......................................................................................... 278
CT Type-D Input Slew Rate Definition ......................................................................................... 278
Differential AC Swing and “Time Exceeding AC-Level” tDVAC ....................................................... 279
Single-Ended Requirements for CK .............................................................................................. 281
Differential Input Slew Rate Definition for CK_t, CK_c .................................................................. 282
V IX(CK) Definition ........................................................................................................................ 282
Differential Input Signal Definition for DQS_t, DQS_c .................................................................. 283
DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling ..... 284
V IXDQS Definition ........................................................................................................................ 285
Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c ..................................... 286
ADDR, CMD, CNTL Overshoot and Undershoot Definition ........................................................... 288
CK Overshoot and Undershoot Definition .................................................................................... 289
Data, Strobe, and Mask Overshoot and Undershoot Definition ..................................................... 290
Single-ended Output Slew Rate Definition ................................................................................... 291
Differential Output Slew Rate Definition ...................................................................................... 293
Reference Load For AC Timing and Output Slew Rate ................................................................... 294
Connectivity Test Mode Reference Test Load ................................................................................ 294
Connectivity Test Mode Output Slew Rate Definition .................................................................... 295
Output Driver During Connectivity Test Mode ............................................................................. 296
Output Driver: Definition of Voltages and Currents ...................................................................... 297
Alert Driver ................................................................................................................................ 301
ODT Definition of Voltages and Currents ..................................................................................... 302
ODT Timing Reference Load ....................................................................................................... 303
tADC Definition with Direct ODT Control .................................................................................... 305
tADC Definition with Dynamic ODT Control ................................................................................ 305
tAOFAS and tAONAS Definitions .................................................................................................. 306
Thermal Measurement Point ....................................................................................................... 312
Measurement Setup and Test Load for I DDx, IPPx, and IDDQx ........................................................... 313
Correlation: Simulated Channel I/O Power to Actual Channel I/O Power ....................................... 314
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: Ball Descriptions .............................................................................................................................. 26
Table 4: State Diagram Command Definitions ................................................................................................ 34
Table 5: Supply Power-up Slew Rate ............................................................................................................... 36
Table 6: Address Pin Mapping ........................................................................................................................ 44
Table 7: MR0 Register Definition .................................................................................................................... 44
Table 8: Burst Type and Burst Order ............................................................................................................... 46
Table 9: Address Pin Mapping ........................................................................................................................ 48
Table 10: MR1 Register Definition .................................................................................................................. 48
Table 11: Additive Latency (AL) Settings ......................................................................................................... 50
Table 12: TDQS Function Matrix .................................................................................................................... 51
Table 13: Address Pin Mapping ...................................................................................................................... 52
Table 14: MR2 Register Definition .................................................................................................................. 52
Table 15: Address Pin Mapping ...................................................................................................................... 55
Table 16: MR3 Register Definition .................................................................................................................. 55
Table 17: Address Pin Mapping ...................................................................................................................... 58
Table 18: MR4 Register Definition .................................................................................................................. 58
Table 19: Address Pin Mapping ...................................................................................................................... 62
Table 20: MR5 Register Definition .................................................................................................................. 62
Table 21: Address Pin Mapping ...................................................................................................................... 65
Table 22: MR6 Register Definition .................................................................................................................. 65
Table 23: Truth Table – Command .................................................................................................................. 67
Table 24: Truth Table – CKE ........................................................................................................................... 69
Table 25: MR Settings for Leveling Procedures ................................................................................................ 77
Table 26: DRAM TERMINATION Function in Leveling Mode ........................................................................... 77
Table 27: Auto Self Refresh Mode ................................................................................................................... 86
Table 28: MR3 Setting for the MPR Access Mode ............................................................................................. 88
Table 29: DRAM Address to MPR UI Translation ............................................................................................. 88
Table 30: MPR Page and MPRx Definitions ..................................................................................................... 89
Table 31: MPR Readout Serial Format ............................................................................................................. 91
Table 32: MPR Readout – Parallel Format ....................................................................................................... 92
Table 33: MPR Readout Staggered Format, x4 ................................................................................................. 93
Table 34: MPR Readout Staggered Format, x4 – Consecutive READs ................................................................ 93
Table 35: MPR Readout Staggered Format, x8 and x16 ..................................................................................... 94
Table 36: Mode Register Setting for CA Parity ................................................................................................. 109
Table 37: V REFDQ Range and Levels ................................................................................................................ 119
Table 38: V REFDQ Settings (VDDQ = 1.2V) ......................................................................................................... 125
Table 39: Connectivity Mode Pin Description and Switching Levels ................................................................ 127
Table 40: MAC Encoding of MPR Page 3 MPR3 ............................................................................................... 130
Table 41: PPR MR0 Guard Key Settings .......................................................................................................... 132
Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 136
Table 43: sPPR Associated Rows .................................................................................................................... 136
Table 44: PPR MR0 Guard Key Settings .......................................................................................................... 137
Table 45: DDR4 sPPR Timing Parameters DDR4-1600 through DDR4-3200 ..................................................... 138
Table 46: DDR4 Repair Mode Support Identifier ............................................................................................ 139
Table 47: Normal tREFI Refresh (TCR Enabled) .............................................................................................. 143
Table 48: MRS Definition .............................................................................................................................. 146
Table 49: REFRESH Command Truth Table .................................................................................................... 146
Table 50: tREFI and tRFC Parameters ............................................................................................................. 147
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 51: Power-Down Entry Definitions ....................................................................................................... 156
Table 52: CRC Error Detection Coverage ........................................................................................................ 167
Table 53: CRC Data Mapping for x4 Devices, BL8 ........................................................................................... 169
Table 54: CRC Data Mapping for x8 Devices, BL8 ........................................................................................... 169
Table 55: CRC Data Mapping for x16 Devices, BL8 ......................................................................................... 170
Table 56: CRC Data Mapping for x4 Devices, BC4 ........................................................................................... 170
Table 57: CRC Data Mapping for x8 Devices, BC4 ........................................................................................... 171
Table 58: CRC Data Mapping for x16 Devices, BC4 ......................................................................................... 172
Table 59: DBI vs. DM vs. TDQS Function Matrix ............................................................................................. 177
Table 60: DBI Write, DQ Frame Format (x8) ................................................................................................... 177
Table 61: DBI Write, DQ Frame Format (x16) ................................................................................................. 177
Table 62: DBI Read, DQ Frame Format (x8) .................................................................................................... 178
Table 63: DBI Read, DQ Frame Format (x16) .................................................................................................. 178
Table 64: DM vs. TDQS vs. DBI Function Matrix ............................................................................................. 179
Table 65: Data Mask, DQ Frame Format (x8) .................................................................................................. 179
Table 66: Data Mask, DQ Frame Format (x16) ................................................................................................ 179
Table 67: CWL Selection ............................................................................................................................... 182
Table 68: DDR4 Bank Group Timing Examples .............................................................................................. 187
Table 69: Read-to-Write and Write-to-Read Command Intervals .................................................................... 192
Table 70: Termination State Table ................................................................................................................. 254
Table 71: Read Termination Disable Window ................................................................................................. 254
Table 72: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 .......................................................... 255
Table 73: Dynamic ODT Latencies and Timing (1 tCK Preamble Mode and CRC Disabled) ................................ 258
Table 74: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix ............................ 259
Table 75: Absolute Maximum Ratings ............................................................................................................ 262
Table 76: Temperature Range ........................................................................................................................ 262
Table 77: Recommended Supply Operating Conditions .................................................................................. 263
Table 78: V DD Slew Rate ................................................................................................................................ 263
Table 79: Leakages ....................................................................................................................................... 264
Table 80: V REFDQ Specification ...................................................................................................................... 265
Table 81: V REFDQ Range and Levels ................................................................................................................ 266
Table 82: RESET_n Input Levels (CMOS) ....................................................................................................... 267
Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 ........................................... 267
Table 84: Command and Address Input Levels: DDR4-2666 ............................................................................ 268
Table 85: Command and Address Input Levels: DDR4-2933 and DDR4-3200 ................................................... 268
Table 86: Single-Ended Input Slew Rates ....................................................................................................... 269
Table 87: Command and Address Setup and Hold Values Referenced – AC/DC-Based ..................................... 270
Table 88: Derating Values for tIS/tIH – AC100DC75-Based .............................................................................. 270
Table 89: Derating Values for tIS/tIH – AC90/DC65-Based .............................................................................. 271
Table 90: DQ Input Receiver Specifications .................................................................................................... 272
Table 91: Rx Mask and tDS/tDH without Write Training .................................................................................. 275
Table 92: TEN Input Levels (CMOS) .............................................................................................................. 275
Table 93: CT Type-A Input Levels .................................................................................................................. 276
Table 94: CT Type-B Input Levels .................................................................................................................. 277
Table 95: CT Type-C Input Levels (CMOS) ..................................................................................................... 277
Table 96: CT Type-D Input Levels .................................................................................................................. 278
Table 97: Differential Input Swing Requirements for CK_t, CK_c ..................................................................... 279
Table 98: Minimum Time AC Time tDVAC for CK ........................................................................................... 280
Table 99: Single-Ended Requirements for CK ................................................................................................. 281
Table 100: CK Differential Input Slew Rate Definition ..................................................................................... 281
Table 101: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 ................ 283
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 ................ 283
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Features
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DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c ............. 283
DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c ............. 284
Cross Point Voltage For Differential Input Signals DQS ................................................................... 285
DQS Differential Input Slew Rate Definition .................................................................................. 286
DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 286
DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ... 287
ADDR, CMD, CNTL Overshoot and Undershoot/Specifications ...................................................... 288
CK Overshoot and Undershoot/ Specifications .............................................................................. 289
Data, Strobe, and Mask Overshoot and Undershoot/ Specifications ................................................ 290
Single-Ended Output Levels ......................................................................................................... 290
Single-Ended Output Slew Rate Definition .................................................................................... 291
Single-Ended Output Slew Rate .................................................................................................... 292
Differential Output Levels ............................................................................................................. 292
Differential Output Slew Rate Definition ....................................................................................... 292
Differential Output Slew Rate ....................................................................................................... 293
Connectivity Test Mode Output Levels .......................................................................................... 294
Connectivity Test Mode Output Slew Rate ..................................................................................... 295
Output Driver Electrical Characteristics During Connectivity Test Mode ......................................... 297
Strong Mode (34˖) Output Driver Electrical Characteristics ........................................................... 298
Weak Mode (48˖) Output Driver Electrical Characteristics ............................................................. 299
Output Driver Sensitivity Definitions ............................................................................................ 300
Output Driver Voltage and Temperature Sensitivity ....................................................................... 300
Alert Driver Voltage ...................................................................................................................... 301
ODT DC Characteristics ............................................................................................................... 302
ODT Sensitivity Definitions .......................................................................................................... 303
ODT Voltage and Temperature Sensitivity ..................................................................................... 303
ODT Timing Definitions ............................................................................................................... 304
Reference Settings for ODT Timing Measurements ........................................................................ 304
DRAM Package Electrical Specifications for x4 and x8 Devices ....................................................... 307
DRAM Package Electrical Specifications for x16 Devices ................................................................ 308
Pad Input/Output Capacitance ..................................................................................................... 310
Thermal Characteristics ............................................................................................................... 311
Basic IDD, IPP, and IDDQ Measurement Conditions .......................................................................... 314
IDD0 and IPP0 Measurement-Loop Pattern1 .................................................................................... 318
IDD1 Measurement – Loop Pattern1 ............................................................................................... 319
IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1 .................................................................... 320
IDD2NT Measurement – Loop Pattern1 ............................................................................................ 321
IDD4R Measurement – Loop Pattern1 .............................................................................................. 322
IDD4W Measurement – Loop Pattern1 ............................................................................................. 323
IDD4Wc Measurement – Loop Pattern1 ............................................................................................ 324
IDD5R Measurement – Loop Pattern1 .............................................................................................. 325
IDD7 Measurement – Loop Pattern1 ............................................................................................... 326
Timings used for I DD, IPP, and IDDQ Measurement – Loop Patterns .................................................. 327
IDD and IPP Current Limits; Die Rev. B (-40° ื T C ื 85°C) ................................................................. 328
IDD and IPP Current Limits; Die Rev. E (-40° ื T C ื 85°C) ................................................................. 330
Backward Compatibility ............................................................................................................... 334
DDR4-1600 Speed Bins and Operating Conditions ......................................................................... 336
DDR4-1866 Speed Bins and Operating Conditions ......................................................................... 338
DDR4-2133 Speed Bins and Operating Conditions ......................................................................... 340
DDR4-2400 Speed Bins and Operating Conditions ......................................................................... 342
DDR4-2666 Speed Bins and Operating Conditions ......................................................................... 344
DDR4-2933 Speed Bins and Operating Conditions ......................................................................... 347
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16Gb: x4, x8, x16 DDR4 SDRAM
Features
Table 155:
Table 156:
Table 157:
Table 158:
Table 159:
Table 160:
DDR4-3200 Speed Bins and Operating Conditions ......................................................................... 350
Refresh Parameters by Device Density ........................................................................................... 352
Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 ................... 353
Electrical Characteristics and AC Timing Parameters ..................................................................... 365
Options – Speed Based ................................................................................................................. 378
Options – Width Based ................................................................................................................. 379
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18
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Notes and Description
Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
General Notes and Description
x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface
designed to transfer two data words per clock cycle at the I/O pins.
A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit
wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit
wide, one-half-clock-cycle data transfers at the I/O pins.
Industrial Temperature
An industrial temperature (IT) device option requires that the case temperature not exceed below –40°C or above 95°C. JEDEC specifications require the refresh rate to double
when T C exceeds 85°C; this also requires use of the high-temperature self refresh option.
Additionally, ODT resistance and the input/output impedance must be derated when
operating outside of the commercial temperature range, when T C is between –40°C and
0°C.
Automotive Temperature
The automotive temperature (AT) device option requires that the case temperature not
exceed below –40°C or above 105°C. The specifications require the refresh rate to 2X
when T C exceeds 85°C; 4X when T C exceeds 95°C. Additionally, ODT resistance and the
input/output impedance must be derated when operating temperature Tc @
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CCM005-1406124318-10453
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22
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Functional Block Diagrams
Figure 4: 1 Gig x 16 Functional Block Diagram
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CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
23
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Ball Assignments
Ball Assignments
Figure 5: 78-Ball x4, x8 Ball Assignments
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CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1
$1)1&
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1. See Ball Descriptions.
2. A comma “,” separates the configuration; a slash “/” defines a mode register selectable
function, command/address function, density, or package dependence.
3. Address bits (including bank groups) are density- and configuration-dependent (see Addressing).
24
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16Gb: x4, x8, x16 DDR4 SDRAM
Ball Assignments
Figure 6: 96-Ball x16 Ball Assignments
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CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
7
1. See Ball Descriptions.
2. A slash “/” defines a mode register selectable function, command/address function, density, or package dependence.
3. Address bits (including bank groups) are density- and configuration-dependent (see Addressing).
25
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16Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Ball Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4 devices. All pins listed may not be supported on the device defined in this data sheet. See
the Ball Assignments section to review all pins used on this device.
Table 3: Ball Descriptions
Symbol
Type
Description
A[17:0]
Input
Address inputs: Provide the row address for ACTIVATE commands and the column
address for READ/WRITE commands to select one location out of the memory array in
the respective bank. (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, RAS_n/A16 have additional functions, see individual entries in this table.) The address inputs also provide
the op-code during the MODE REGISTER SET command. A16 is used on some 8Gb and
16Gb parts. A17 connection is part-number specific; Contact vendor for more information.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine
whether auto precharge should be performed to the accessed bank after a READ or
WRITE operation. (HIGH = auto precharge; LOW = no auto precharge.) A10 is sampled during a PRECHARGE command to determine whether the PRECHARGE applies
to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged,
the bank is selected by the bank group and bank addresses.
A12/BC_n
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if
burst chop (on-the-fly) will be performed. (HIGH = no burst chop; LOW = burst chopped). See the Command Truth Table.
ACT_n
Input
Command input: ACT_n indicates an ACTIVATE command. When ACT_n (along with
CS_n) is LOW, the input pins RAS_n/A16, CAS_n/A15, and WE_n/A14 are treated as
row address inputs for the ACTIVATE command. When ACT_n is HIGH (along with
CS_n LOW), the input pins RAS_n/ A16, CAS_n/A15, and WE_n/A14 are treated as normal commands that use the RAS_n, CAS_n, and WE_n signals. See the Command
Truth Table.
BA[1:0]
Input
Bank address inputs: Define the bank (within a bank group) to which an ACTIVATE,
READ, WRITE, or PRECHARGE command is being applied. Also determines which
mode register is to be accessed during a MODE REGISTER SET command.
BG[1:0]
Input
Bank group address inputs: Define the bank group to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determines which mode register is to be accessed during a MODE REGISTER SET command. BG[1:0] are used in the
x4 and x8 configurations. BG1 is not used in the x16 configuration.
C0/CKE1,
C1/CS1_n,
C2/ODT1
Input
Stack address inputs: These inputs are used only when devices are stacked; that is,
they are used in 2H, 4H, and 8H stacks for x4 and x8 configurations (these pins are
not used in the x16 configuration, and are NC on the x4/x8 SDP). DDR4 will support a
traditional DDP package, which uses these three signals for control of the second die
(CS1_n, CKE1, ODT1). DDR4 is not expected to support a traditional QDP package. For
all other stack configurations, such as a 4H or 8H, it is assumed to be a single-load
(master/slave) type of configuration where C0, C1, and C2 are used as chip ID selects
in conjunction with a single CS_n, CKE, and ODT signal.
CK_t,
CK_c
Input
Clock: Differential clock inputs. All address, command, and control input signals are
sampled on the crossing of the positive edge of CK_t and the negative edge of CK_c.
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16Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
CKE
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device input buffers, and output drivers. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operations (all banks idle), or active power-down
(row active in any bank). CKE is asynchronous for self refresh exit, however, timing
parameters such as tXS are still calculated from the first rising clock edge where CKE
HIGH satisfies tIS. After VREFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH).
CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t, CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input
buffers (excluding CKE and RESET_n) are disabled during self refresh.
CS_n
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides
for external rank selection on systems with multiple ranks. CS_n is considered part of
the command code.
DM_n,
UDM_n
LDM_n
Input
Input data mask: DM_n is an input mask signal for write data. Input data is masked
when DM is sampled LOW coincident with that input data during a write access. DM
is sampled on both edges of DQS. DM is not supported on x4 configurations. The
UDM_n and LDM_n pins are used in the x16 configuration: UDM_n is associated with
DQ[15:8]; LDM_n is associated with DQ[7:0]. The DM, DBI, and TDQS functions are enabled by mode register settings. See the Data Mask section.
ODT
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t,
DQS_c, DM_n/DBI_n/TDQS_t, and TDQS_c signal for the x4 and x8 configurations
(when the TDQS function is enabled via mode register). For the x16 configuration, RTT
is applied to each DQ, UDQS_t, UDQS_c, LDQS_t, LDQS_c, UDM_n, and LDM_n signal.
The ODT pin will be ignored if the mode registers are programmed to disable RTT.
PAR
Input
Parity for command and address: This function can be enabled or disabled via the
mode register. When enabled, the parity signal covers all command and address inputs, including ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, A[17:0], A10/AP, A12/BC_n,
BA[1:0], and BG[1:0] with C0, C1, and C2 on 3DS only devices. Control pins NOT covered by the parity signal are CS_n, CKE, and ODT. Unused address pins that are density- and configuration-specific should be treated internally as 0s by the DRAM parity
logic. Command and address inputs will have parity check performed when commands are latched via the rising edge of CK_t and when CS_n is LOW.
RAS_n/A16,
CAS_n/A15,
WE_n/A14
Input
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n and
ACT_n) define the command and/or address being entered. See the ACT_n description in this table.
RESET_n
Input
Active LOW asynchronous reset: Reset is active when RESET_n is LOW, and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation. RESET_n
is a CMOS rail-to-rail signal with DC HIGH and LOW at 80% and 20% of VDD (960 mV
for DC HIGH and 240 mV for DC LOW).
TEN
Input
Connectivity test mode: TEN is active when HIGH and inactive when LOW. TEN
must be LOW during normal operation. TEN is a CMOS rail-to-rail signal with DC
HIGH and LOW at 80% and 20% of VDD (960mV for DC HIGH and 240mV for DC
LOW). On Micron 3DS devices, connectivity test mode is not supported and the TEN
pin should be considered NF maintained LOW at all times.
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16Gb: x4, x8, x16 DDR4 SDRAM
Ball Descriptions
Table 3: Ball Descriptions (Continued)
Symbol
Type
Description
DQ
I/O
Data input/output: Bidirectional data bus. DQ represents DQ[3:0], DQ[7:0], and
DQ[15:0] for the x4, x8, and x16 configurations, respectively. If write CRC is enabled
via mode register, the write CRC code is added at the end of data burst. Any one or
all of DQ0, DQ1, DQ2, and DQ3 may be used to monitor the internal VREF level during
test via mode register setting MR[4] A[4] = HIGH, training times change when enabled. During this mode, the RTT value should be set to High-Z. This measurement is
for verification purposes and is NOT an external voltage supply pin.
DBI_n,
UDBI_n,
LDBI_n
I/O
DBI input/output: Data bus inversion. DBI_n is an input/output signal used for data
bus inversion in the x8 configuration. UDBI_n and LDBI_n are used in the x16 configuration; UDBI_n is associated with DQ[15:8], and LDBI_n is associated with DQ[7:0]. The
DBI feature is not supported on the x4 configuration. DBI is not supported for 3DS
devices and should be disabled in MR5. DBI can be configured for both READ (output) and WRITE (input) operations depending on the mode register settings. The DM,
DBI, and TDQS functions are enabled by mode register settings. See the Data Bus Inversion section.
DQS_t,
DQS_c,
UDQS_t,
UDQS_c,
LDQS_t,
LDQS_c
I/O
Data strobe: Output with READ data, input with WRITE data. Edge-aligned with
READ data, centered-aligned with WRITE data. For the x16, LDQS corresponds to the
data on DQ[7:0]; UDQS corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4
SDRAM supports a differential data strobe only and does not support a single-ended
data strobe.
ALERT_n
Output
Alert output: This signal allows the DRAM to indicate to the system's memory controller that a specific alert or event has occurred. Alerts will include the command/
address parity error and the CRC data error when either of these functions is enabled
in the mode register.
TDQS_t,
TDQS_c
Output
Termination data strobe: TDQS_t and TDQS_c are used by x8 DRAMs only. When
enabled via the mode register, the DRAM will enable the same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c. When the TDQS
function is disabled via the mode register, the DM/TDQS_t pin will provide the DATA
MASK (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in the mode register for both the x4 and x16 configurations. The DM function
is supported only in x8 and x16 configurations.
VDD
Supply
Power supply: 1.2V ±0.060V.
VDDQ
Supply
DQ power supply: 1.2V ±0.060V.
VPP
Supply
DRAM activating power supply: 2.5V –0.125V/+0.250V.
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground.
ZQ
Reference
RFU
–
Reserved for future use.
NC
–
No connect: No internal electrical connection is present.
NF
–
No function: Internal connection is present but has no function.
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Reference ball for ZQ calibration: This ball is tied to an external 240˖ resistor
(RZQ), which is tied to VSSQ.
28
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16Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Package Dimensions
Figure 7: 78-Ball FBGA – x4, x8 (VA)
0.155
Seating plane
A
1.8 CTR
Nonconductive
overmold
78X Ø0.47±0.05
Dimensions apply
to solder balls postreflow on Ø0.42
SMD ball pads.
0.1 A
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
11 ±0.1
9.6 CTR
0.8 TYP
1.1 ±0.1
0.8 TYP
6.4 CTR
0.34 ±0.05
10±0.1
Notes:
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16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
29
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16Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 8: 78-Ball FBGA – x4, x8 (JC)
0.155
Seating plane
A
1.8 CTR
nonconductive
overmold
78X Ø0.47 ±0.05
Dimensions apply to
solder balls postreflow on Ø0.42 SMD
ball pads.
0.12 A
Ball A1 ID
Ball A1 ID
9
8
7
3
2
1
A
B
C
D
E
11 ±0.1
F
9.6 CTR
G
H
J
K
L
M
0.8 TYP
N
1.1 ±0.1
0.8 TYP
0.34 ±0.05
6.4 CTR
9 ±0.1
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
30
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 9: 96-Ball FBGA – x16 (RC)
0.155
Seating plane
A
0.1 A
1.8 CTR
nonconductive
overmold
96X Ø0.47 ±0.05
Dimensions apply
to solder balls postreflow on Ø0.42 SMD
ball pads.
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
13 ±0.1
G
H
J
12 CTR
K
L
M
N
P
R
0.8 TYP
T
1.1 ±0.1
0.8 TYP
0.34 ±0.05
6.4 CTR
10 ±0.1
Notes:
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16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
31
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16Gb: x4, x8, x16 DDR4 SDRAM
Package Dimensions
Figure 10: 96-Ball FBGA – x16 (KD)
0.155
Seating plane
A
0.12 A
1.8 CTR
Nonconductive
overmold
96X Ø0.47 ±0.05
Dimensions apply to
solder balls post-reflow
on Ø0.42 SMD ball pads.
Ball A1 ID
9 8 7
3 2
Ball A1 ID
1
A
B
C
D
E
F
13 ±0.1
G
H
J
12 CTR
K
L
M
N
P
R
0.8 TYP
T
1.1 ±0.1
0.8 TYP
0.34 ±0.05
6.4 CTR
9 ±0.1
Notes:
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16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC302 (96.8% Sn, 3% Ag, 0.2% Cu).
32
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
State Diagram
State Diagram
This simplified state diagram provides an overview of the possible state transitions and
the commands to control them. Situations involving more than one bank, the enabling
or disabling of on-die termination, and some other events are not captured in full detail.
Figure 11: Simplified State Diagram
IVREFDQ,
RTT, and
so on
MPSM
From any state
RESET
SRX* = SRX with NOP
SRX*
CKE_L
MRS
Power
applied
Power-On
RESET
MRS
SRX*
Reset
procedure
TEN = 1
TEN = 1
MRS, MPR,
write leveling,
VREFDQ training
PDA
mode
Initialization
MRS
MRS
ZQCL
SRX
MRS
SRE
MRS
Connectivity
test
TEN = 0
ZQ
calibration
Self
refresh
ZQCL,ZQCS
REF
Idle
Refreshing
RESET
PDE
ACT
CKE_L
CKE_L
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
PDE
Bank
active
WRITE
WRITE
READ
WRITE A
READ
Writing
READ
READ A
WRITE
Reading
READ A
WRITE A
WRITE A
READ A
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Precharging
Reading
Automatic
sequence
Command
sequence
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16Gb: x4, x8, x16 DDR4 SDRAM
State Diagram
Table 4: State Diagram Command Definitions
Command
Description
ACT
Active
MPR
Multipurpose register
MRS
Mode register set
PDE
Enter power-down
PDX
Exit power-down
PRE
Precharge
PREA
Precharge all
READ
RD, RDS4, RDS8
READ A
RDA, RDAS4, RDAS8
REF
Refresh, fine granularity refresh
RESET
Start reset procedure
SRE
Self refresh entry
SRX
Self refresh exit
TEN
Boundary scan mode enable
WRITE
WR, WRS4, WRS8 with/without CRC
WRITE A
WRA, WRAS4, WRAS8 with/without CRC
ZQCL
ZQ calibration long
ZQCS
ZQ calibration short
Note:
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1. See the Command Truth Table for more details.
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16Gb: x4, x8, x16 DDR4 SDRAM
Functional Description
Functional Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devices, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16
devices. The device uses double data rate (DDR) architecture to achieve high-speed operation. DDR4 architecture is essentially an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for a device module effectively consists of a single 8n-bit-wide, four-clockcycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected location and continue for a burst length of eight or a chopped burst of four in a programmed sequence. Operation begins with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]
select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select
the bank, and A[17:0] select the row. See the Addressing section for more details). The
address bits registered coincident with the READ or WRITE command are used to select
the starting column location for the burst operation, determine if the auto PRECHARGE
command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via
A12) if enabled in the mode register.
Prior to normal operation, the device must be powered up and initialized in a predefined manner. The following sections provide detailed information covering device reset
and initialization, register definition, command descriptions, and device operation.
NOTE: The use of the NOP command is allowed only when exiting maximum power
saving mode or when entering gear-down mode.
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16Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
RESET and Initialization Procedure
To ensure proper device function, the power-up and reset initialization default values
for the following mode register (MR) settings are defined as:
•
•
•
•
•
•
•
Gear-down mode (MR3 A[3]): 0 = 1/2 rate
Per-DRAM addressability (MR3 A[4]): 0 = disable
Maximum power-saving mode (MR4 A[1]): 0 = disable
CS to command/address latency (MR4 A[8:6]): 000 = disable
CA parity latency mode (MR5 A[2:0]): 000 = disable
Hard post package repair mode (MR4 A[13]): 0 = disable
Soft post package repair mode (MR4 A[5]): 0 = disable
Power-Up and Initialization Sequence
The following sequence is required for power-up and initialization:
1. Apply power (RESET_n and TEN should be maintained below 0.2 × V DD while supplies ramp up; all other inputs may be undefined). When supplies have ramped to
a valid stable level, RESET_n must be maintained below 0.2 × V DD for a minimum
of tPW_RESET_L and TEN must be maintained below 0.2 × V DD for a minimum of
700μs. CKE is pulled LOW anytime before RESET_n is de-asserted (minimum time
of 10ns). The power voltage ramp time between 300mV to V DD,min must be no
greater than 200ms, and during the ramp, V DD must be greater than or equal to
VDDQ and (VDD - V DDQ) < 0.3V. V PP must ramp at the same time or up to 10 minutes
prior to V DD, and V PP must be equal to or higher than V DD at all times. The total
time for which V PP is powered and V DD is unpowered should not exceed 360 cumulative hours. After V DD has ramped and reached a stable level, RESET_n must
go high within 10 minutes. After RESET_n goes high, the initialization sequence
must be started within 3 seconds. For debug purposes, the 10 minute and 3 second delay limits may be extended to 60 minutes each provided the DRAM is operated in this debug mode for no more than 360 cumulative hours.
During power-up, the supply slew rate is governed by the limits stated in the table
below and either condition A or condition B listed below must be met.
Table 5: Supply Power-up Slew Rate
Note:
Symbol
Min
Max
Unit Comment
VDD_SL, VDDQ_SL,
VPP_SL
0.004
600
V/ms Measured between 300mV and 80% of
supply minimum
VDD_ona
N/A
200
ms
VDD maximum ramp time from 300mV to
VDD minimum
VDDQ_ona
N/A
200
ms
VDDQ maximum ramp time from 300mV to
VDDQ minimum
1. 20 MHz band-limited measurement.
• Condition A:
– Apply V PP without any slope reversal before or at the same time as V DD and
VDDQ.
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16Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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– VDD and V DDQ are driven from a single-power converter output and apply
VDD/VDDQ without any slope reversal before or at the same time as V TT and
VREFCA.
– The voltage levels on all balls other than V DD, V DDQ, V SS, and V SSQ must be less
than or equal to V DDQ and V DD on one side and must be greater than or equal
to V SSQ and V SS on the other side.
– VTT is limited to 0.76V MAX when the power ramp is complete.
– VREFCA tracks V DD/2.
• Condition B:
– Apply V PP without any slope reversal before or at the same time as V DD.
– Apply V DD without any slope reversal before or at the same time as V DDQ.
– Apply V DDQ without any slope reversal before or at the same time as V TT and
VREFCA.
– The voltage levels on all pins other than V PP, V DD, V DDQ, V SS, and V SSQ must be
less than or equal to V DDQ and V DD on one side and must be larger than or
equal to V SSQ and V SS on the other side.
After RESET_n is de-asserted, wait for a minimum of 500us, but no longer than 3
seconds, before allowing CKE to be registered HIGH at clock edge Td. During this
time, the device will start internal state initialization; this will be done independently of external clocks. A reasonable attempt was made in the design to power up
with the following default MR settings: gear-down mode (MR3 A[3]): 0 = 1/2 rate;
per-DRAM addressability (MR3 A[4]): 0 = disable; maximum power-down (MR4
A[1]): 0 = disable; CS to command/address latency (MR4 A[8:6]): 000 = disable; CA
parity latency mode (MR5 A[2:0]): 000 = disable. However, it should be assumed
that at power up the MR settings are undefined and should be programmed as
shown below.
Clocks (CK_t, CK_c) need to be started and stabilized for at least 10ns or 5 tCK
(whichever is larger) before CKE is registered HIGH at clock edge Td. Because CKE
is a synchronous signal, the corresponding setup time to clock (tIS) must be met.
Also, a DESELECT command must be registered (with tIS setup time to clock) at
clock edge Td. After the CKE is registered HIGH after RESET, CKE needs to be continuously registered HIGH until the initialization sequence is finished, including
expiration of tDLLK and tZQinit.
The device keeps its ODT in High-Z state as long as RESET_n is asserted. Further,
the SDRAM keeps its ODT in High-Z state after RESET_n de-assertion until CKE is
registered HIGH. The ODT input signal may be in an undefined state until tIS before CKE is registered HIGH. When CKE is registered HIGH, the ODT input signal
may be statically held either LOW or HIGH. If RTT(NOM) is to be enabled in MR1,
the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains static until the power-up initialization sequence is finished, including
the expiration of tDLLK and tZQinit.
After CKE is registered HIGH, wait a minimum of RESET CKE EXIT time, tXPR, before issuing the first MRS command to load mode register (tXPR = MAX (tXS, 5 ×
tCK).
Issue MRS command to load MR3 with all application settings, wait tMRD.
Issue MRS command to load MR6 with all application settings, wait tMRD.
Issue MRS command to load MR5 with all application settings, wait tMRD.
Issue MRS command to load MR4 with all application settings, wait tMRD.
Issue MRS command to load MR2 with all application settings, wait tMRD.
Issue MRS command to load MR1 with all application settings, wait tMRD.
37
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16Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
12.
13.
14.
15.
Issue MRS command to load MR0 with all application settings, wait tMOD.
Issue a ZQCL command to start ZQ calibration.
Wait for tDLLK and tZQinit to complete.
The device will be ready for normal operation. Once the DRAM has been initialized, if the DRAM is in an idle state longer than 960ms, then either (a) REF commands must be issued within tREFI constraints (specification for posting allowed)
or (b) CKE or CS_n must toggle once within every 960ms interval of idle time. For
debug purposes, the 960ms delay limit maybe extended to 60 minutes provided
the DRAM is operated in this debug mode for no more than 360 cumulative hours.
A stable valid V DD level is a set DC level (0Hz to 250 KHz) and must be no less than
VDD,min and no greater than V DD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DD provided the
noise doesn't alter V DD to less than V DD,min or greater than V DD,max.
A stable valid V DDQ level is a set DC level (0Hz to 250 KHz) and must be no less than
VDDQ,min and no greater than V DDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC
level is stable. AC noise of ±60mV (greater than 250 KHz) is allowed on V DDQ provided
the noise doesn't alter V DDQ to less than V DDQ,min or greater than V DDQ,max.
A stable valid V PP level is a set DC level (0Hz to 250 KHz) and must be no less than
VPP,min and no greater than V PP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is stable. AC noise of ±120mV (greater than 250KHz) is allowed on V PP provided the
noise doesn't alter V PP to less than V PP,min or greater than V PP,max.
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
Figure 12: RESET and Initialization Sequence at Power-On Ramping
Ta
Tb
Tc
Te
Td
Tf
Ti
Th
Tg
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD, VDDQ
tPW_RESET_L
T = 500μs
RESET_n
T (MIN) = 10ns
tIS
Valid
CKE
tDLLK
tIS
Command
Note 1
BG, BA
tXPR
tMRD
tMRD
tMRD
tZQinit
tMOD
MRS
MRS
MRS
MRS
MRx
MRx
MRx
MRx
ZQCL
Note 1
Valid
tIS
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
ODT
Valid
Valid
RTT
Time Break
Notes:
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
RESET Initialization with Stable Power Sequence
The following sequence is required for RESET at no power interruption initialization:
1. Assert RESET_n below 0.2 × V DD any time when reset is needed (all other inputs
may be undefined). RESET_n needs to be maintained for minimum tPW_RESET.
CKE is pulled LOW before RESET_n being de-asserted (minimum time 10ns).
2. Follow Steps 2 through 10 in the Reset and Initialization Sequence at Power-On
Ramping procedure.
When the reset sequence is complete, all counters except the refresh counters have
been reset and the device is ready for normal operation.
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
RESET and Initialization Procedure
Figure 13: RESET Procedure at Power Stable Condition
Ta
Tb
Tc
Te
Td
Tf
Ti
Th
Tg
Tj
Tk
CK_t, CK_c
tCKSRX
VPP
VDD , VDDQ
tPW_RESET_S
T = 500μs
RESET_n
T (MIN) = 10ns
tIS
Valid
CKE
tDLLK
tIS
Command
Note 1
BG, BA
tXPR
tMRD
tMRD
tMRD
tMOD
MRS
MRS
MRS
MRS
MRx
MRx
MRx
MRx
tZQinit
ZQCL
Note 1
Valid
tIS
tIS
Static LOW in case RTT(NOM) is enabled at time Tg, otherwise static HIGH or LOW
ODT
Valid
Valid
RTT
Time Break
Notes:
Don’t Care
1. From time point Td until Tk, a DES command must be applied between MRS and ZQCL
commands.
2. MRS commands must be issued to all mode registers that have defined settings.
3. In general, there is no specific sequence for setting the MRS locations (except for dependent or co-related features, such as ENABLE DLL in MR1 prior to RESET DLL in MR0,
for example).
4. TEN is not shown; however, it is assumed to be held LOW.
Uncontrolled Power-Down Sequence
In the event of an uncontrolled ramping down of V PP supply, V PP is allowed to be less
than V DD provided the following conditions are met:
• Condition A: V PP and V DD/VDDQ are ramping down (as part of turning off) from normal operating levels.
• Condition B: The amount that V PP may be less than V DD/VDDQ is less than or equal to
500mV.
• Condition C: The time V PP may be less than V DD is ื10ms per occurrence with a total
accumulated time in this state ื100ms.
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
Programming Mode Registers
• Condition D: The time V PP may be less than 2.0V and above V SS while turning off is
ื15ms per occurrence with a total accumulated time in this state ื150ms.
Programming Mode Registers
For application flexibility, various functions, features, and modes are programmable in
seven mode registers (MRn) provided by the device as user defined variables that must
be programmed via a MODE REGISTER SET (MRS) command. Because the default values of the mode registers are not defined, contents of mode registers must be fully initialized and/or re-initialized; that is, they must be written after power-up and/or reset
for proper operation. The contents of the mode registers can be altered by re-executing
the MRS command during normal operation. When programming the mode registers,
even if the user chooses to modify only a sub-set of the MRS fields, all address fields
within the accessed mode register must be redefined when the MRS command is issued. MRS and DLL RESET commands do not affect array contents, which means these
commands can be executed any time after power-up without affecting the array contents.
The MRS command cycle time, tMRD, is required to complete the WRITE operation to
the mode register and is the minimum time required between the two MRS commands
shown in the tMRD Timing figure.
Some of the mode register settings affect address/command/control input functionality. In these cases, the next MRS command can be allowed when the function being updated by the current MRS command is completed. These MRS commands don’t apply
tMRD timing to the next MRS command; however, the input cases have unique MR setting procedures, so refer to individual function descriptions:
•
•
•
•
•
•
•
Gear-down mode
Per-DRAM addressability
CMD address latency
CA parity latency mode
VREFDQ training value
VREFDQ training mode
VREFDQ training range
Some mode register settings may not be supported because they are not required by
certain speed bins.
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
Programming Mode Registers
Figure 14: tMRD Timing
T0
T1
T2
Ta0
Ta1
Tb0
Tb1
Tb2
Tc0
Tc1
Tc2
Command
Valid
Valid
Valid
MRS2
DES
DES
DES
DES
DES
MRS2
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CKE
tMRD
Updating settings
Old settings
Settings
Time Break
Don’t Care
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMRD applies to all MRS commands with the following exceptions:
Gear-down mode
CA parity latency mode
CMD address latency
Per-DRAM addressability mode
VREFDQ training value, VREFDQ training mode, and VREFDQ training range
Notes:
The MRS command to nonMRS command delay, tMOD, is required for the DRAM to
update features, except for those noted in note 2 in figure below where the individual
function descriptions may specify a different requirement. tMOD is the minimum time
required from an MRS command to a nonMRS command, excluding DES, as shown in
the tMOD Timing figure.
Figure 15: tMOD Timing
T0
T1
T2
Ta0
Ta1
Ta2
Ta3
Ta4
Tb0
Tb1
Tb2
Command
Valid
Valid
Valid
MRS2
DES
DES
DES
DES
DES
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
CKE
t
Settings
MOD
Updating settings
Old settings
New settings
Time Break
Notes:
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Don’t Care
1. This timing diagram depicts CA parity mode “disabled” case.
2. tMOD applies to all MRS commands with the following exceptions:
DLL enable, DLL RESET, Gear-down mode
VREFDQ training value, internal VREF training monitor, VREFDQ training mode, and VREFDQ
training range
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16Gb: x4, x8, x16 DDR4 SDRAM
Programming Mode Registers
Maximum power savings mode , Per-DRAM addressability mode, and CA parity latency
mode
The mode register contents can be changed using the same command and timing requirements during normal operation as long as the device is in idle state; that is, all
banks are in the precharged state with tRP satisfied, all data bursts are completed, and
CKE is HIGH prior to writing into the mode register. If the RTT(NOM) feature is enabled in
the mode register prior to and/or after an MRS command, the ODT signal must continuously be registered LOW, ensuring RTT is in an off state prior to the MRS command.
The ODT signal may be registered HIGH after tMOD has expired. If the RTT(NOM) feature
is disabled in the mode register prior to and after an MRS command, the ODT signal
can be registered either LOW or HIGH before, during, and after the MRS command. The
mode registers are divided into various fields depending on functionality and modes.
In some mode register setting cases, function updating takes longer than tMOD. This
type of MRS does not apply tMOD timing to the next valid command, excluding DES.
These MRS command input cases have unique MR setting procedures, so refer to individual function descriptions.
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Mode Register 0
Mode Register 0
Mode register 0 (MR0) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR0 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR0 Register
Definition table.
Table 6: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 7: MR0 Register Definition
Mode
Register
21
20:18
17
13,11:9
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
WR (WRITE recovery)/RTP (READ-to-PRECHARGE)
0000 = 10 / 5 clocks1
0001 = 12 / 6 clocks
0010 = 14 / 7 clocks1
0011 = 16 / 8 / clocks
0100 = 18 / 9 clocks1
0101 = 20 /10 clocks
0110 = 24 / 12 clocks
0111 = 22 / 11 clocks1
1000 = 26 / 13 clocks1
1001 = 28 / 14 clocks2
1010 through 1111 = Reserved
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Mode Register 0
Table 7: MR0 Register Definition (Continued)
Mode
Register
Description
8
DLL reset
0 = No
1 = Yes
7
Test mode (TM) – Manufacturer use only
0 = Normal operating mode, must be programmed to 0
12, 6:4, 2
3
1:0
CAS latency (CL) – Delay in clock cycles from the internal READ command to first data-out
00000 = 9 clocks1
00001 = 10 clocks
00010 = 11 clocks1
00011 = 12 clocks
00100 = 13 clocks1
00101 = 14 clocks
00110 = 15 clocks1
00111 = 16 clocks
01000 = 18 clocks
01001 = 20 clocks
01010 = 22 clocks
01011 = 24 clocks
01100 = 23 clocks1
01101 = 17 clocks1
01110 = 19 clocks1
01111 = 21 clocks 1
10000 = 25 clocks
10001 = 26 clocks
10011 = 28 clocks
10100 = 29 clocks1
10101 = 30 clocks
10110 = 31 clocks1
10111 = 32 clocks
Burst type (BT) – Data burst ordering within a READ or WRITE burst access
0 = Nibble sequential
1 = Interleave
Burst length (BL) – Data burst size associated with each read or write access
00 = BL8 (fixed)
01 = BC4 or BL8 (on-the-fly)
10 = BC4 (fixed)
11 = Reserved
Notes:
1. Not allowed when 1/4 rate gear-down mode is enabled.
2. If WR requirement exceeds 28 clocks or RTP exceeds 14 clocks, WR should be set to 28
clocks and RTP should be set to 14 clocks.
Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order.
The ordering of accesses within a burst is determined by the burst length, burst type,
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 0
and the starting column address as shown in the following table. Burst length options
include fixed BC4, fixed BL8, and on-the-fly (OTF), which allows BC4 or BL8 to be selected coincidentally with the registration of a READ or WRITE command via A12/BC_n.
Table 8: Burst Type and Burst Order
Note 1 applies to the entire table
Starting
Column Address
Burst
READ/
(A[2, 1, 0])
Length
WRITE
BC4
READ
WRITE
BL8
READ
WRITE
Notes:
Burst Type = Sequential
(Decimal)
Burst Type = Interleaved
(Decimal)
Notes
000
0, 1, 2, 3, T, T, T, T
0, 1, 2, 3, T, T, T, T
2, 3
001
1, 2, 3, 0, T, T, T, T
1, 0, 3, 2, T, T, T, T
2, 3
010
2, 3, 0, 1, T, T, T, T
2, 3, 0, 1, T, T, T, T
2, 3
011
3, 0, 1, 2, T, T, T, T
3, 2, 1, 0, T, T, T, T
2, 3
100
4, 5, 6, 7, T, T, T, T
4, 5, 6, 7, T, T, T, T
2, 3
101
5, 6, 7, 4, T, T, T, T
5, 4, 7, 6, T, T, T, T
2, 3
110
6, 7, 4, 5, T, T, T, T
6, 7, 4, 5, T, T, T, T
2, 3
111
7, 4, 5, 6, T, T, T, T
7, 6, 5, 4, T, T, T, T
2, 3
0, V, V
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
2, 3
1, V, V
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
2, 3
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
V, V, V
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
3
1. 0...7 bit number is the value of CA[2:0] that causes this bit to be the first read during a
burst.
2. When setting burst length to BC4 (fixed) in MR0, the internal WRITE operation starts
two clock cycles earlier than for the BL8 mode, meaning the starting point for tWR and
tWTR will be pulled in by two clocks. When setting burst length to OTF in MR0, the internal WRITE operation starts at the same time as a BL8 (even if BC4 was selected during
column time using A12/BC4_n) meaning that if the OTF MR0 setting is used, the starting
point for tWR and tWTR will not be pulled in by two clocks as described in the BC4
(fixed) case.
3. T = Output driver for data and strobes are in High-Z.
V = Valid logic level (0 or 1), but respective buffer input ignores level on input pins.
X = “Don’t Care.”
CAS Latency
The CAS latency (CL) setting is defined in the MR0 Register Definition table. CAS latency is the delay, in clock cycles, between the internal READ command and the availability
of the first bit of output data. The device does not support half-clock latencies. The
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Mode Register 0
overall read latency (RL) is defined as additive latency (AL) + CAS latency (CL): RL = AL +
CL.
Test Mode
The normal operating mode is selected by MR0[7] and all other bits set to the desired
values shown in the MR0 Register Definition table. Programming MR0[7] to a value of 1
places the device into a DRAM manufacturer-defined test mode to be used only by the
manufacturer, not by the end user. No operations or functionality is specified if MR0[7]
= 1.
Write Recovery (WR)/READ-to-PRECHARGE
The programmed write recovery (WR) value is used for the auto precharge feature along
with tRP to determine tDAL. WR for auto precharge (MIN) in clock cycles is calculated
by dividing tWR (in ns) by tCK (in ns) and rounding to the next integer using the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section. The WR value must be programmed to be equal to or larger than
tWR (MIN). When both DM and write CRC are enabled in the mode register, the device
calculates CRC before sending the write data into the array; tWR values will change
when enabled. If there is a CRC error, the device blocks the WRITE operation and discards the data.
Internal READ-to-PRECHARGE (RTP) command delay for auto precharge (MIN) in
clock cycles is calculated by dividing tRTP (in ns) by tCK (in ns) and rounding to the next
integer using the rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section. The RTP value in the mode register must be
programmed to be equal to or larger than RTP (MIN). The programmed RTP value is
used with tRP to determine the ACT timing to the same bank.
DLL RESET
The DLL reset bit is self-clearing, meaning that it returns to the value of 0 after the DLL
RESET function has been issued. After the DLL is enabled, a subsequent DLL RESET
should be applied. Any time the DLL RESET function is used, tDLLK must be met before
functions requiring the DLL can be used. Such as READ commands or synchronous
ODT operations, for example.
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Mode Register 1
Mode Register 1
Mode register 1 (MR1) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR1 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR1 Register
Definition table.
Table 9: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 10: MR1 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
12
Data output disable (Qoff) – Output buffer disable
0 = Enabled (normal operation)
1 = Disabled (both ODI and RTT)
11
Termination data strobe (TDQS) – Additional termination pins (x8 configuration only)
0 = TDQS disabled
1 = TDQS enabled
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Mode Register 1
Table 10: MR1 Register Definition (Continued)
Mode
Register
10, 9, 8
7
13, 6, 5
Description
Nominal ODT (RTT(NOM) – Data bus termination setting
000 = RTT(NOM) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
Write leveling (WL) – Write leveling mode
0 = Disabled (normal operation)
1 = Enabled (enter WL mode)
Rx CTLE Control
000 = Vendor Default
001 = Vendor Defined
010 = Vendor Defined
011 = Vendor Defined
100 = Vendor Defined
101 = Vendor Defined
110 = Vendor Defined
111 = Vendor Defined
4, 3
Additive latency (AL) – Command additive latency setting
00 = 0 (AL disabled)
01 = CL - 11
10 = CL - 2
11 = Reserved
2, 1
Output driver impedance (ODI) – Output driver impedance setting
00 = RZQ/7 (34 ohm)
01 = RZQ/5 (48 ohm)
10 = Reserved (Although not JEDEC-defined and not tested, this setting will provide RZQ/6 or 40 ohm)
11 = Reserved
0
DLL enable – DLL enable feature
0 = DLL disabled
1 = DLL enabled (normal operation)
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
DLL Enable/DLL Disable
The DLL must be enabled for normal operation and is required during power-up initialization and upon returning to normal operation after having the DLL disabled. During
normal operation (DLL enabled with MR1[0]) the DLL is automatically disabled when
entering the SELF REFRESH operation and is automatically re-enabled upon exit of the
SELF REFRESH operation. Any time the DLL is enabled and subsequently reset, tDLLK
clock cycles must occur before a READ or SYNCHRONOUS ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Fail-
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 1
ing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON,
or tAOF parameters.
During tDLLK, CKE must continuously be registered HIGH. The device does not require
DLL for any WRITE operation, except when R TT(WR) is enabled and the DLL is required
for proper ODT operation.
The direct ODT feature is not supported during DLL off mode. The ODT resistors must
be disabled by continuously registering the ODT pin LOW and/or by programming the
RTT(NOM) bits MR1[9,6,2] = 000 via an MRS command during DLL off mode.
The dynamic ODT feature is not supported in DLL off mode; to disable dynamic ODT
externally, use the MRS command to set RTT(WR), MR2[10:9] = 00.
Output Driver Impedance Control
The output driver impedance of the device is selected by MR1[2,1], as shown in the MR1
Register Definition table.
ODT RTT(NOM) Values
The device is capable of providing three different termination values: RTT(Park), RTT(NOM),
and RTT(WR). The nominal termination value, R TT(NOM), is programmed in MR1. A separate value, RTT(WR), may be programmed in MR2 to enable a unique RTT value when
ODT is enabled during WRITE operations. The R TT(WR) value can be applied during
WRITE commands even when RTT(NOM) is disabled. A third RTT value, RTT(Park), is programed in MR5. RTT(Park) provides a termination value when the ODT signal is LOW.
Additive Latency
The ADDITIVE LATENCY (AL) operation is supported to make command and data
buses efficient for sustainable bandwidths in the device. In this operation, the device allows a READ or WRITE command (either with or without auto precharge) to be issued
immediately after the ACTIVATE command. The command is held for the time of AL before it is issued inside the device. READ latency (RL) is controlled by the sum of the AL
and CAS latency (CL) register settings. WRITE latency (WL) is controlled by the sum of
the AL and CAS WRITE latency (CWL) register settings.
Table 11: Additive Latency (AL) Settings
A4
A3
AL
0
0
0 (AL disabled)
0
1
CL - 1
1
0
CL - 2
1
1
Reserved
Note:
1. AL has a value of CL - 1 or CL - 2 based on the CL values programmed in the MR0 register.
Rx CTLE Control
The Mode Register for Rx CTLE Control MR1[A13,A6,A5] is vendor specific. Since CTLE
circuits can not be typically bypassed a disable option is not provided. Instead, a vendor
optimized setting is given. It should be noted that the settings are not specifically linear
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 1
in relationship to the vendor optimized setting, so the host may opt to instead walk
through all the provided options and use the setting that works best in their environment.
Write Leveling
For better signal integrity, the device uses fly-by topology for the commands, addresses,
control signals, and clocks. Fly-by topology benefits from a reduced number of stubs
and their lengths, but it causes flight-time skew between clock and strobe at every
DRAM on the DIMM. This makes it difficult for the controller to maintain tDQSS, tDSS,
and tDSH specifications. Therefore, the device supports a write leveling feature that allows the controller to compensate for skew.
Output Disable
The device outputs may be enabled/disabled by MR1[12] as shown in the MR1 Register
Definition table. When MR1[12] is enabled (MR1[12] = 1) all output pins (such as DQ
and DQS) are disconnected from the device, which removes any loading of the output
drivers. For example, this feature may be useful when measuring module power. For
normal operation, set MR1[12] to 0.
Termination Data Strobe
Termination data strobe (TDQS) is a feature of the x8 device and provides additional
termination resistance outputs that may be useful in some system configurations. Because this function is available only in a x8 configuration, it must be disabled for x4 and
x16 configurations.
While TDQS is not supported in x4 or x16 configurations, the same termination resistance function that is applied to the TDQS pins is applied to the DQS pins when enabled
via the mode register.
The TDQS, DBI, and DATA MASK (DM) functions share the same pin. When the TDQS
function is enabled via the mode register, the DM and DBI functions are not supported.
When the TDQS function is disabled, the DM and DBI functions can be enabled separately.
Table 12: TDQS Function Matrix
TDQS
Data Mask (DM)
WRITE DBI
READ DBI
Disabled
Enabled
Disabled
Enabled or disabled
Enabled
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Disabled
Enabled
Enabled or disabled
Disabled
Disabled
Enabled or disabled
Disabled
Disabled
Disabled
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 2
Mode Register 2
Mode register 2 (MR2) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR2 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR2 Register
Definition table.
Table 13: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 14: MR2 Register Definition
Mode
Register Description
21
20:18
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12
WRITE data bus CRC
0 = Disabled
1 = Enabled
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Mode Register 2
Table 14: MR2 Register Definition (Continued)
Mode
Register Description
11:9
Dynamic ODT (RTT(WR)) – Data bus termination setting during WRITEs
000 = RTT(WR) disabled (WRITE does not affect RTT value)
001 = RZQ/2 (120 ohm)
010 = RZQ/1 (240 ohm)
011 = High-Z
100 = RZQ/3 (80 ohm)
101 = Reserved
110 = Reserved
111 = Reserved
7:6
Low-power auto self refresh (LPASR) – Mode summary
00 = Manual mode - Normal operating temperature range (TC: -40°C–85°C)
01 = Manual mode - Reduced operating temperature range (TC: -40°C–45°C)
10 = Manual mode - Extended operating temperature range (TC: -40°C–105°C)
11 = ASR mode - Automatically switching among all modes
5:3
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
1tCK WRITE preamble
000 = 9 (DDR4-1600)1
001 = 10 (DDR4-1866)
010 = 11 (DDR4-2133/1600)1
011 = 12 (DDR4-2400/1866)
100 = 14 (DDR4-2666/2133)
101 = 16 (DDR4-2933,3200/2400)
110 = 18 (DDR4-2666)
111 = 20 (DDR4-2933, 3200)
CAS WRITE latency (CWL) – Delay in clock cycles from the internal WRITE command to first data-in
2tCK WRITE preamble
000 = N/A
001 = N/A
010 = N/A
011 = N/A
100 = 14 (DDR4-2400)
101 = 16 (DDR4-2666/2400)
110 = 18 (DDR4-2933, 3200/2666)
111 = 20 (DDR4-2933, 3200)
8, 2
RFU
0 = Must be programmed to 0
1 = Reserved
1:0
RFU
0 = Must be programmed to 0
1 = Reserved
Note:
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Mode Register 2
CAS WRITE Latency
CAS WRITE latency (CWL) is defined by MR2[5:3] as shown in the MR2 Register Definition table. CWL is the delay, in clock cycles, between the internal WRITE command and
the availability of the first bit of input data. The device does not support any half-clock
latencies. The overall WRITE latency (WL) is defined as additive latency (AL) + parity latency (PL) + CAS WRITE latency (CWL): WL = AL +PL + CWL.
Low-Power Auto Self Refresh
Low-power auto self refresh (LPASR) is supported in the device. Applications requiring
SELF REFRESH operation over different temperature ranges can use this feature to optimize the IDD6 current for a given temperature range as specified in the MR2 Register
Definition table.
Dynamic ODT
In certain applications and to further enhance signal integrity on the data bus, it is desirable to change the termination strength of the device without issuing an MRS command. This may be done by configuring the dynamic ODT (R TT(WR)) settings in
MR2[11:9]. In write leveling mode, only RTT(NOM) is available.
Write Cyclic Redundancy Check Data Bus
The write cyclic redundancy check (CRC) data bus feature during writes has been added
to the device. When enabled via the mode register, the data transfer size goes from the
normal 8-bit (BL8) frame to a larger 10-bit UI frame, and the extra two UIs are used for
the CRC information.
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Mode Register 3
Mode Register 3
Mode register 3 (MR3) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR3 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR3 Register
Definition table.
Table 15: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 16: MR3 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12:11
Multipurpose register (MPR) – Read format
00 = Serial
01 = Parallel
10 = Staggered
11 = Reserved
10:9
WRITE CMD latency when CRC/DM enabled
00 = 4CK (DDR4-1600)
01 = 5CK (DDR4-1866/2133/2400/2666)
10 = 6CK (DDR4-2933/3200)
11 = Reserved
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Mode Register 3
Table 16: MR3 Register Definition (Continued)
Mode
Register
8:6
Description
Fine granularity refresh mode
000 = Normal mode (fixed 1x)
001 = Fixed 2x
010 = Fixed 4x
011 = Reserved
100 = Reserved
101 = On-the-fly 1x/2x
110 = On-the-fly 1x/4x
111 = Reserved
5
Temperature sensor status
0 = Disabled
1 = Enabled
4
Per-DRAM addressability
0 = Normal operation (disabled)
1 = Enable
3
Gear-down mode – Ratio of internal clock to external data rate
0 = [1:1]; (1/2 rate data)
1 = [2:1]; (1/4 rate data)
2
Multipurpose register (MPR) access
0 = Normal operation
1 = Data flow from MPR
1:0
MPR page select
00 = Page 0
01 = Page 1
10 = Page 2
11 = Page 3 (restricted for DRAM manufacturer use only)
Multipurpose Register
The multipurpose register (MPR) is used for several features:
• Readout of the contents of the MRn registers
• WRITE and READ system patterns used for data bus calibration
• Readout of the error frame when the command address parity feature is enabled
To enable MPR, issue an MRS command to MR3[2] = 1. MR3[12:11] define the format of
read data from the MPR. Prior to issuing the MRS command, all banks must be in the
idle state (all banks precharged and tRP met). After MPR is enabled, any subsequent RD
or RDA commands will be redirected to a specific mode register.
The mode register location is specified with the READ command using address bits. The
MR is split into upper and lower halves to align with a burst length limitation of 8. Power-down mode, SELF REFRESH, and any other nonRD/RDA or nonWR/WRA commands are not allowed during MPR mode. The RESET function is supported during
MPR mode, which requires device re-initialization.
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 3
WRITE Command Latency When CRC/DM is Enabled
The WRITE command latency (WCL) must be set when both write CRC and DM are enabled for write CRC persistent mode. This provides the extra time required when completing a WRITE burst when write CRC and DM are enabled. This means at data rates
less than or equal to 1600 MT/s then 4nCK is used, 5nCK or 6nCK are not allowed; at
data rates greater than 1600 MT/s and less than or equal to 2666 MT/s then 5nCK is
used, 4nCK or 6nCK are not allowed; and at data rates greater than 2666 MT/s and less
than or equal to 3200 MT/s then 6nCK is used; 4nCK or 5nCK are not allowed.
Fine Granularity Refresh Mode
This mode had been added to DDR4 to help combat the performance penalty due to
refresh lockout at high densities. Shortening tRFC and decreasing cycle time allows
more accesses to the chip and allows for increased scheduling flexibility.
Temperature Sensor Status
This mode directs the DRAM to update the temperature sensor status at MPR Page 2,
MPR0 [4,3]. The temperature sensor setting should be updated within 32ms; when an
MPR read of the temperature sensor status bits occurs, the temperature sensor status
should be no older than 32ms.
Per-DRAM Addressability
This mode allows commands to be masked on a per device basis providing any device
in a rank (devices sharing the same command and address signals) to be programmed
individually. As an example, this feature can be used to program different ODT or V REF
values on DRAM devices within a given rank.
Gear-Down Mode
The device defaults in 1/2 rate (1N) clock mode and uses a low frequency MRS command followed by a sync pulse to align the proper clock edge for operating the control
lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. For operation in 1/2 rate mode,
no MRS command or sync pulse is required.
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Mode Register 4
Mode Register 4
Mode register 4 (MR4) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR4 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR4 Register
Definition table.
Table 17: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET (MRS) command.
Table 18: MR4 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
Hard Post Package Repair (hPPR mode)
0 = Disabled
1 = Enabled
12
WRITE preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle (When operating in 2tCK WRITE preamble mode, CWL must be programmed to a value at
least 1 clock greater than the lowest CWL setting supported in the applicable tCK range.)
11
READ preamble setting
0 = 1tCK toggle1
1 = 2tCK toggle
10
READ preamble training
0 = Disabled
1 = Enabled
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 4
Table 18: MR4 Register Definition (Continued)
Mode
Register
9
8:6
Description
Self refresh abort mode
0 = Disabled
1 = Enabled
CMD (CAL) address latency
000 = 0 clocks (disabled)
001 =3 clocks1
010 = 4 clocks
011 = 5 clocks1
100 = 6 clocks
101 = 8 clocks
110 = Reserved
111 = Reserved
5
soft Post Package Repair (sPPR mode)
0 = Disabled
1 = Enabled
4
Internal VREF monitor
0 = Disabled
1 = Enabled
3
Temperature controlled refresh mode
0 = Disabled
1 = Enabled
2
Temperature controlled refresh range
0 = Normal temperature mode
1 = Extended temperature mode
1
Maximum power savings mode
0 = Normal operation
1 = Enabled
0
RFU
0 = Must be programmed to 0
1 = Reserved
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
Hard Post Package Repair Mode
The hard post package repair (hPPR) mode feature is JEDEC optional for 4Gb DDR4
memories. Performing an MPR read to page 2 MPR0 [7] indicates whether hPPR mode is
available (A7 = 1) or not available (A7 = 0). hPPR mode provides a simple and easy repair
method of the device after placed in the system. One row per bank can be repaired. The
repair process is irrevocable so great care should be exercised when using.
Soft Post Package Repair Mode
The soft post package repair (sPPR) mode feature is JEDEC optional for 4Gb and 8Gb
DDR4 memories. Performing an MPR read to page 2 MPR0 [6] indicates whether sPPR
mode is available (A6 = 1) or not available (A6 = 0). sPPR mode provides a simple and
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 4
easy repair method of the device after placed in the system. One row per bank can be
repaired. The repair process is revocable by either doing a reset or power-down or by
rewriting a new address in the same bank.
WRITE Preamble
Programmable WRITE preamble, tWPRE, can be set to 1tCK or 2tCK via the MR4 register.
The 1tCK setting is similar to DDR3. However, when operating in 2tCK WRITE preamble
mode, CWL must be programmed to a value at least 1 clock greater than the lowest CWL
setting supported in the applicable tCK range.
Some even settings will require addition of 2 clocks. If the alternate longer CWL was
used, the additional clocks will not be required.
READ Preamble
Programmable READ preamble tRPRE can be set to 1tCK or 2tCK via the MR4 register.
Both the 1tCK and 2tCK DDR4 preamble settings are different from that defined for the
DDR3 SDRAM. Both DDR4 READ preamble settings may require the memory controller
to train (or read level) its data strobe receivers using the READ preamble training.
READ Preamble Training
Programmable READ preamble training can be set to 1tCK or 2tCK. This mode can be
used by the memory controller to train or READ level its data strobe receivers.
Temperature-Controlled Refresh
When temperature-controlled refresh mode is enabled, the device may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping
external REFRESH commands with the proper gear ratio. For example, the DRAM temperature sensor detected less than 45°C. Normal temperature mode covers the range of
-40°C to 85°C, while the extended temperature range covers -40°C to 105°C.
Command Address Latency
COMMAND ADDRESS LATENCY (CAL) is a power savings feature and can be enabled
or disabled via the MRS setting. CAL is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address.
The value of CAL (in clocks) must be programmed into the mode register according to
the tCAL(ns)/tCK(ns) rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section.
Internal VREF Monitor
This mode enables output of internally generated V REFDQ for monitoring on DQ0, DQ1,
DQ2, and DQ3. May be used during V REFDQ training and test. While in this mode, R TT
should be set to High-Z. V REF_time must be increased by 10ns if DQ load is 0pF, plus an
additional 15ns per pF of loading. This measurement is for verification purposes and is
NOT an external voltage supply pin.
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 4
Maximum Power Savings Mode
This mode provides the lowest power mode where data retention is not required. When
the device is in the maximum power saving mode, it does not need to guarantee data
retention or respond to any external command (except the MAXIMUM POWER SAVING
MODE EXIT command and during the assertion of RESET_n signal LOW).
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 5
Mode Register 5
Mode register 5 (MR5) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR5 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR5 Register
Definition table.
Table 19: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 20: MR5 Register Definition
Mode
Register
21
20:18
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
17
N/A on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
13
RFU
0 = Must be programmed to 0
1 = Reserved
12
Data bus inversion (DBI) – READ DBI enable
0 = Disabled
1 = Enabled
11
Data bus inversion (DBI) – WRITE DBI enable
0 = Disabled
1 = Enabled
10
Data mask (DM)
0 = Disabled
1 = Enabled
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Mode Register 5
Table 20: MR5 Register Definition (Continued)
Mode
Register
9
8:6
Description
CA parity persistent error mode
0 = Disabled
1 = Enabled
Parked ODT value (RTT(Park))
000 = RTT(Park) disabled
001 = RZQ/4 (60 ohm)
010 = RZQ/2 (120 ohm)
011 = RZQ/6 (40 ohm)
100 = RZQ/1 (240 ohm)
101 = RZQ/5 (48 ohm)
110 = RZQ/3 (80 ohm)
111 = RZQ/7 (34 ohm)
5
ODT input buffer for power-down
0 = Buffer enabled
1 = Buffer disabled
4
CA parity error status
0 = Clear
1 = Error
3
CRC error status
0 = Clear
1 = Error
2:0
CA parity latency mode
000 = Disable
001 = 4 clocks (DDR4-1600/1866/2133)
010 = 5 clocks (DDR4-2400/2666)1
011 = 6 clocks (DDR4-2933/3200)
100 = Reserved
101 = Reserved
110 = Reserved
111 = Reserved
Note:
1. Not allowed when 1/4 rate gear-down mode is enabled.
Data Bus Inversion
The DATA BUS INVERSION (DBI) function has been added to the device and is supported only for x8 and x16 configurations (x4 is not supported). The DBI function shares a
common pin with the DM and TDQS functions. The DBI function applies to both READ
and WRITE operations; Write DBI cannot be enabled at the same time the DM function
is enabled. Refer to the TDQS Function Matrix table for valid configurations for all three
functions (TDQS/DM/DBI). DBI is not allowed during MPR READ operation; during an
MPR read, the DRAM ignores the read DBI enable setting in MR5 bit A12.
DBI is not supported for 3DS devices and should be disabled in MR5.
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16Gb: x4, x8, x16 DDR4 SDRAM
Mode Register 5
Data Mask
The DATA MASK (DM) function, also described as a partial write, has been added to the
device and is supported only for x8 and x16 configurations (x4 is not supported). The
DM function shares a common pin with the DBI and TDQS functions. The DM function
applies only to WRITE operations and cannot be enabled at the same time the write DBI
function is enabled. Refer to the TDQS Function Matrix table for valid configurations for
all three functions (TDQS/DM/DBI).
CA Parity Persistent Error Mode
Normal CA parity mode (CA parity persistent mode disabled) no longer performs CA
parity checking while the parity error status bit remains set at 1. However, with CA parity persistent mode enabled, CA parity checking continues to be performed when the
parity error status bit is set to a 1.
ODT Input Buffer for Power-Down
This feature determines whether the ODT input buffer is on or off during power-down.
If the input buffer is configured to be on (enabled during power-down), the ODT input
signal must be at a valid logic level. If the input buffer is configured to be off (disabled
during power-down), the ODT input signal may be floating and the device does not provide RTT(NOM) termination. However, the device may provide RTT(Park) termination depending on the MR settings. This is primarily for additional power savings.
CA Parity Error Status
The device will set the error status bit to 1 upon detecting a parity error. The parity error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CRC Error Status
The device will set the error status bit to 1 upon detecting a CRC error. The CRC error
status bit remains set at 1 until the device controller clears it explicitly using an MRS
command.
CA Parity Latency Mode
CA parity is enabled when a latency value, dependent on tCK, is programmed; this accounts for parity calculation delay internal to the device. The normal state of CA parity
is to be disabled. If CA parity is enabled, the device must ensure there are no parity errors before executing the command. CA parity signal (PAR) covers ACT_n, RAS_n/A16 ,
CAS_n/A15, WE_n/A14, and the address bus including bank address and bank group
bits. The control signals CKE, ODT, and CS_n are not included in the parity calculation.
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Mode Register 6
Mode Register 6
Mode register 6 (MR6) controls various device operating modes as shown in the following register definition table. Not all settings listed may be available on a die; only settings required for speed bin support are available. MR6 is written by issuing the MRS
command while controlling the states of the BGx, BAx, and Ax address pins. The mapping of address pins during the MRS command is shown in the following MR6 Register
Definition table.
Table 21: Address Pin Mapping
Address BG1 BG0 BA1 BA0 A17 RAS CAS WE A13 A12 A11 A10 A9
bus
_n _n _n
Mode
register
21
20
19
18
Note:
17
–
–
–
13
12
11
10
9
A8
A7
A6
A5
A4
A3
A2
A1
A0
8
7
6
5
4
3
2
1
0
1. RAS_n, CAS_n, and WE_n must be LOW during MODE REGISTER SET command.
Table 22: MR6 Register Definition
Mode
Register
21
20:18
17
12:10
Description
RFU
0 = Must be programmed to 0
1 = Reserved
MR select
000 = MR0
001 = MR1
010 = MR2
011 = MR3
100 = MR4
101 = MR5
110 = MR6
111 = DNU
NA on 4Gb and 8Gb, RFU
0 = Must be programmed to 0
1 = Reserved
Data Rate
000 = Data rateื 1333 Mb/s (1333 Mb/s)
001 = 1333 Mb/s *Skew).
DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew).
t
3. DS/tDH are traditional data-eye setup/hold edges at DC levels.
tDS and tDH are not specified; tDH and tDS may be any value provided the pulse width
and Rx mask limits are not violated.
tDH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ.
The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx
mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller
will have to train the data input buffer to utilize the Rx mask specifications to this maxi-
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
mum benefit. If the DRAM controller does not train the data input buffers, then the
worst case limits have to be used for the Rx mask (TdiVW + 2 × tDQS2DQ), which will
generally be the classical minimum ( tDS and tDH) and is required as well.
Figure 168: Example of Data Input Requirements Without Training
TdiVW + 2 × tDQS2DQ
VdiVW
VIH(DC)
0.5 × VdiVW
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW
VIL(DC)
tDS
tDH
0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ
DQS_c
DQS_t
WRITE Burst Operation
The following write timing diagrams are intended to help understand each write parameter's meaning and are only examples. Each parameter will be defined in detail separately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and
DQ are shown center-aligned for the purpose of illustration.
DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 onthe-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled:
• A12 = 0, BC4 (BC4 = burst chop)
• A12 = 1, BL8
WRITE commands can issue precharge automatically with a WRITE with auto precharge (WRA) command, which is enabled by A10 HIGH.
• WRITE command with A10 = 0 (WR) performs standard write, bank remains active after WRITE burst
• WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes
into precharge after WRITE burst
The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the
DM function is not supported on x4 devices). The DM function shares a common pin
with the DBI_n and TDQS functions. The DM function only applies to WRITE operations and cannot be enabled at the same time the DBI function is enabled.
• If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs.
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
• If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and
writes this data into the DRAM core.
• If CRC write is enabled, then DM enabled (via MRS) will be selected between write
CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM enabled).
Figure 169: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)
T0
T1
T2
T7
T8
T9
WRITE
DES
DES
DES
DES
DES
T10
T11
T12
T13
T14
T15
T16
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Address
Bank
Col n
DES
tWPST
tWPRE
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
WL = AL + CWL = 9
Time Break
Notes:
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Transitioning Data
Don’t Care
1. BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n = Data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA Latency = Disable, Read DBI = Disable.
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 170: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)
T0
T1
T2
T9
T10
T11
T17
T18
T19
T20
T21
T22
T23
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
Bank Group
Address
BGa
Bank
Col n
Address
tWPST
tWPRE
DQS_t,
DQS_c
DI
n
DQ
AL = 10
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CWL = 9
WL = AL + CWL = 19
Time Break
Notes:
Don’t Care
Transitioning Data
1. BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
WRITE Operation Followed by Another WRITE Operation
Figure 171: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
229
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
Figure 172: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 10
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
230
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 173: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=5
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Notes:
Don’t Care
Transitioning Data
1. BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
Figure 174: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
WRITE
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=6
BGa
BGa
or BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 10
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
231
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. tCCD_S/L = 5 isn’t allowed in 2tCK preamble mode.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T20.
8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
Figure 175: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
232
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 176: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 10
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and
T4.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode.
Figure 177: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
Address
2 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
233
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 (fixed) setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T15.
Figure 178: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
t
4 Clocks
t
CCD_S = 4
Bank Group
Address
Address
BGa
BGb
Bank
Col n
Bank
Col b
t
t
WPRE
WR
t
WTR
WPST
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
WL = AL + CWL = 9
Time Break
Notes:
Transitioning Data
Don’t Care
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
234
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 179: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T2
T3
T4
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S
Bank Group
Address
Address
4 Clocks
=4
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = AL + CWL = 9
Time Break
Don’t Care
Transitioning Data
1. BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
Notes:
BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T17.
WRITE Operation Followed by READ Operation
Figure 180: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_S
BGa
=2
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
DI
b+4
DI
b+5
DI
b+6
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
235
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 181: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_L
BGa
=4
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
DI
b+1
DI
b+2
Don’t Care
1. BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0 and READ command at T17.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
236
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 182: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
T10
WRITE
DES
DES
DES
DES
DES
T11
T12
T13
DES
DES
DES
T14
T15
T16
T24
T25
T26
T27
T28
T29
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_S
=2
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T15.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T13.
Notes:
Figure 183: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
WRITE
DES
DES
DES
DES
DES
T11
T12
T13
T14
DES
DES
DES
DES
T15
T16
T17
T18
T26
T27
T28
T29
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
4 Clocks
Bank Group
Address
Address
tWTR_L
BGa
=4
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
DI
b+1
DI
b+2
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and
READ command at T17.
237
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T13.
Figure 184: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group
T0
T1
T7
T8
T9
WRITE
DES
DES
DES
DES
T10
T11
DES
DES
T12
T13
T14
T22
T23
T24
T25
T26
T27
T28
T29
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
CK_c
CK_t
Command
2 Clocks
Bank Group
Address
Address
tWTR_S
=2
BGa
BGb
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
DI
b+1
DI
b+2
DI
b+3
Time Break
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after
the last write data shown at T11.
Notes:
Figure 185: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T24
T25
T26
T27
T28
T29
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
READ
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
2 Clocks
Bank Group
Address
Address
tWTR_L
=4
BGa
BGa
Bank
Col n
Bank
Col b
tWPST
tWPRE
tRPST
tRPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
RL = AL + CL = 11
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
b
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
DI
b+1
DI
b+2
DI
b+3
Transitioning Data
Don’t Care
1. BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble =
1tCK.
2. DI b = data-in from column b.
238
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable,
Write CRC = Disable.
6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after
the last write data shown at T11.
WRITE Operation Followed by PRECHARGE Operation
The minimum external WRITE command to PRECHARGE command spacing is equal to
WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The minimum ACT to PRE timing, tRAS, must be satisfied as well.
Figure 186: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
T22
DES
DES
DES
DES
DES
T23
T24
T25
DES
DES
PRE
T26
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
BGa, Bank b
Col n
DES
tRP
= 12
BGa, Bank b
(or all)
Address
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n
DI
n+1
DI
n+2
DI
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8
setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command
at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
239
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 187: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
DES
DES
DES
DES
DES
T10
T11
T12
T13
DES
DES
DES
DES
T14
T22
T23
DES
DES
PRE
T24
T25
T26
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tRP
= 12
BGa, Bank b
Col n
BGa, Bank b
(or all)
Address
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Time Break
Notes:
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 188: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
T22
DES
DES
DES
DES
DES
T23
T24
T25
DES
DES
DES
T26
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
DES
tRP
= 12
BGa, Bank b
Col n
Address
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n
DI
n+1
DI
n+2
DI
n+3
BL8 Opertaion
DQS_t,
DQS_c
DQ
DI
n+4
DI
n+5
DI
n+6
DI
n+7
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
240
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
Figure 189: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble
T0
T1
T2
WRITE
DES
DES
T3
T4
T7
T8
T9
DES
DES
DES
DES
DES
T10
T11
T12
T13
DES
DES
DES
DES
T14
T22
T23
T24
DES
DES
DES
DES
T25
T26
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tRP
= 12
BGa, Bank b
Col n
Address
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable.
6. The write recovery time (tWR) is referenced from the first rising clock edge after the last
write data shown at T11. tWR specifies the last burst WRITE cycle until the PRECHARGE
command can be issued to the same bank.
241
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with WRITE DBI Enabled
Figure 190: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI
T0
T1
T2
WRITE
DES
DES
T3
T4
T5
T6
T7
T8
T9
T10
DES
DES
DES
DES
DES
DES
DES
DES
T11
T12
T13
T14
DES
DES
DES
DES
T15
T16
T17
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
4 Clocks
tWTR
Address
BGa
Address
Bank,
Col n
BC4 (OTF) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
BL8 Opertaion
DQS_t,
DQS_c
Transitioning Data
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Don’t Care
1. BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled.
6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the
last write data shown at T13.
242
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 191: WRITE (BC4-Fixed) with 1tCK Preamble and DBI
T0
T1
T2
WRITE
DES
DES
T3
T4
T5
T6
T7
T8
T9
DES
DES
DES
DES
DES
DES
DES
T10
T11
T12
T13
T14
DES
DES
DES
DES
DES
T15
T16
T17
DES
DES
DES
CK_c
CK_t
Command
WL = AL + CWL = 9
tWR
2 Clocks
tWTR
Address
BGa
Address
Bank,
Col n
BC4 (Fixed) Opertaion
DQS_t,
DQS_c
DQ
DI
n
DI
n+1
DI
n+2
DI
n+3
DBI_n
DI
n
DI
n+1
DI
n+2
DI
n+3
Transitioning Data
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Don’t Care
1. BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled.
243
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with CA Parity Enabled
Figure 192: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group
T0
T1
T2
T3
T4
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
WRITE
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S
Bank Group
Address
4 Clocks
=4
BGa
BGb
Address
Bank
Col n
Bank
Col b
Parity
Valid
Valid
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = PL + AL + CWL = 13
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = PL + AL + CWL = 13
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK.
2. DI n = data-in from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4.
5. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
244
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
WRITE Operation with Write CRC Enabled
Figure 193: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T19
CK_c
CK_t
Command
DES
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=5
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x4,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x4,
BL = 8
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 9
DQ x8/X16,
BL = 8
CRC
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
CRC
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T5.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
245
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 194: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different
Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
WRITE
DES
DES
DES
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T18
T19
DES
DES
CK_c
CK_t
Command
tWR
tCCD_S/L
Bank Group
Address
Address
2 Clocks
=5
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DQ x4,
BC = 4 (Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 9
DQ x8/X16,
BC = 4 (Fixed)
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T16.
246
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 195: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group
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CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
7UDQVLWLRQLQJ'DWD
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1. BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 6tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T6.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T19.
247
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 196: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group
T0
T1
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
WRITE
DES
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T22
CK_c
CK_t
Command
DES
tWR
tCCD_S/L
Bank Group
Address
Address
4 Clocks
=7
BGa
BGa or
BGb
Bank
Col n
Bank
Col b
tWPRE
tWTR
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 10
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x4,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x4,
BL = 8
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
DI
b
DI
b+1
DI
b+2
DI
b+3
CRC
CRC
WL = AL + CWL = 10
DQ x8/X16,
BL = 8
CRC
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
CRC
Don’t Care
1. BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCCD_S/L = 7tCK
(see Note 7).
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T7.
5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and
T7.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Disable.
7. tCCD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCCD_S/L allowed in
1tCK preamble mode would have been 6 clocks.
8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from
the first rising clock edge after the last write data shown at T21.
9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a
value at least 1 clock greater than the lowest CWL setting supported in the applicable
tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble
mode.
248
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16Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 197: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank
Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
WRITE
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
T15
T16
T17
T18
T19
T20
DES
DES
DES
DES
DES
DES
CK_c
CK_t
Command
tWR_CRC_DM
4 Clocks
Bank Group
Address
Address
tWTR_S_CRC_DM/tWTR_L_CRC_DM
BGa
Bank
Col n
tWPST
tWPRE
DQS_t,
DQS_c
WL = AL + CWL = 9
DQ x4,
BL = 8
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DQ x8/X16,
BL = 8
DI
n
DI
n+1
DI
n+2
DI
n+3
DI
n+4
DI
n+5
DI
n+6
DI
n+7
CRC
DM
n
DM
n+1
DM
n+2
DM
n+3
DM
n+4
DM
n+5
DM
n+6
DM
n+7
DQ x4,
BC = 4 (OTF/Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DQ x8/X16,
BC = 4 (OTF/Fixed)
DI
n
DI
n+1
DI
n+2
DI
n+3
CRC
DM
n
DM
n+1
DM
n+2
DM
n+3
DMx4/x8/x16
BL = 8
DM x4/x8/x16
BC = 4 (OTF / Fixed)
CRC
CRC
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Transitioning Data
Don’t Care
1. BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE command at T0.
5. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during
WRITE command at T0.
6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable,
DM = Enable.
7. The write recovery time (tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/
tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write data shown at T13.
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16Gb: x4, x8, x16 DDR4 SDRAM
Write Timing Violations
Write Timing Violations
Motivation
Generally, if timing parameters are violated, a complete reset/initialization procedure
has to be initiated to make sure that the device works properly. However, for certain minor violations, it is desirable that the device is guaranteed not to "hang up" and that errors are limited to that specific operation. A minor violation does not include a major
timing violation (for example, when a DQS strobe misses in the tDQSCK window).
For the following, it will be assumed that there are no timing violations with regard to
the WRITE command itself (including ODT, and so on) and that it does satisfy all timing
requirements not mentioned below.
Data Setup and Hold Violations
If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe
edges associated with a WRITE burst, then wrong data might be written to the memory
location addressed with this WRITE command.
In the example, the relevant strobe edges for WRITE Burst A are associated with the
clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5.
Subsequent reads from that location might result in unpredictable read data; however,
the device will work properly otherwise.
Strobe-to-Strobe and Strobe-to-Clock Violations
If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock
timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location
addressed with the offending WRITE command. Subsequent reads from that location
might result in unpredictable read data; however, the device will work properly otherwise with the following constraints:
• Both write CRC and data burst OTF are disabled; timing specifications other than
tDQSH, tDQSL, tWPRE, tWPST, tDSS, tDSH, tDQSS are not violated.
• The offending write strobe (and preamble) arrive no earlier or later than six DQS transition edges from the WRITE latency position.
• A READ command following an offending WRITE command from any open bank is
allowed.
• One or more subsequent WR or a subsequent WRA (to same bank as offending WR)
may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and
WRA can be either offending or non-offending writes. Reads from these writes may
provide incorrect data.
• One or more subsequent WR or a subsequent WRA (to a different bank group) may be
issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA
can be either offending or non-offending writes. Reads from these writes may provide
incorrect data.
• After one or more precharge commands (PRE or PREA) are issued to the device after
an offending WRITE command and all banks are in precharged state (idle state), a
subsequent, non-offending WR or WRA to any open bank will be able to write correct
data.
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
ZQ CALIBRATION Commands
ZQ CALIBRATION Commands
A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The device needs a longer time to calibrate the output driver and on-die termination circuits
at initialization and a relatively smaller time to perform periodic calibrations.
The ZQCL command is used to perform the initial calibration during the power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM and, after calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM I/O, which is reflected as an updated output driver and ODT values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except
the first ZQCL command issued after reset are allowed a timing period of tZQoper.
The ZQCS command is used to perform periodic calibrations to account for voltage and
temperature variations. A shorter timing window is provided to perform the calibration
and transfer of values as defined by timing parameter tZQCS. One ZQCS command can
effectively correct a minimum of 0.5% (ZQ correction) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the
Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS
commands, given the temperature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the
device is subjected to in the application, is illustrated. The interval could be defined by
the following formula:
ZQcorrection
(Tsense x Tdrift_rate) + (Vsense x Tdrift_rate)
Where T sense = MAX(dRTTdT, dRONdTM) and V sense = MAX(dRTTdV, dRONdVM) define
the temperature and voltage sensitivities.
For example, if T sens = 1.5%/°C, V sens = 0.15%/mV, T driftrate = 1 °C/sec and V driftrate = 15
mV/sec, then the interval between ZQCS commands is calculated as:
0.5
= 0.133 §128ms
(1.5 × 1) + (0.15 × 15)
No other activities should be performed on the DRAM channel by the controller for the
duration of tZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output driver and on-die termination values. After DRAM calibration is achieved, the device should disable the ZQ current consumption path to reduce
power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued
by the controller.
ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when
coming out of self refresh. Upon self refresh exit, the device will not perform an I/O caliCCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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16Gb: x4, x8, x16 DDR4 SDRAM
ZQ CALIBRATION Commands
bration without an explicit ZQ CALIBRATION command. The earliest possible time for a
ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or
tXS_FAST depending on operation mode.
In systems that share the ZQ resistor between devices, the controller must not allow any
overlap of tZQoper, tZQinit, or tZQCS between the devices.
Figure 198: ZQ Calibration Timing
T0
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tc0
Tc1
Tc2
ZQCL
DES
DES
DES
Valid
Valid
ZQCS
DES
DES
DES
Valid
Address
Valid
Valid
Valid
A10
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CK_c
CK_t
Command
CKE
Note 1
Note 2
ODT
DQ Bus
High-Z or RTT(Park)
Activities
High-Z or RTT(Park)
Activities
Note 3
tZQinit_tZQoper
tZQCS
Time Break
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Don’t Care
1. CKE must be continuously registered HIGH during the calibration procedure.
2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to provide RTT_PARK.
3. All devices connected to the DQ bus should be High-Z during the calibration procedure.
252
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16Gb: x4, x8, x16 DDR4 SDRAM
On-Die Termination
On-Die Termination
The on-die termination (ODT) feature enables the device to change termination resistance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and
TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control
pin, WRITE command, or default parking value with MR setting. For the x16 configuration, ODT is applied to each UDQ, LDQ, UDQS, LDQS, UDM_n/UDBI_n, and LDM_n/
LDBI_n signal. The ODT feature is designed to improve the signal integrity of the memory channel by allowing the DRAM controller to independently change termination resistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in
standby, either DM mode or DBI write mode must also be enabled if RTT(NOM) or
RTT(Park) is desired. More details about ODT control modes and ODT timing modes can
be found further along in this document.
The ODT feature is turned off and not supported in self refresh mode.
Figure 199: Functional Representation of ODT
ODT
To other
circuitry
such as
RCV,
...
VDDQ
RTT
Switch
DQ, DQS, DM, TDQS
The switch is enabled by the internal ODT control logic, which uses the external ODT
pin and other control information. The value of R TT is determined by the settings of
mode register bits (see Mode Register). The ODT pin will be ignored if the mode register
MR1 is programmed to disable RTT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode.
ODT Mode Register and ODT State Table
The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM),
RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (R TT(NOM)),
MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of
RTT is determined by the settings of these bits.
RTT control of each RTT condition is possible with a WR or RD command and ODT pin.
• RTT(WR): The DRAM (rank) that is being written to provide termination regardless of
ODT pin status (either HIGH or LOW).
• RTT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT
is disabled by MR1).
• RTT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned
on.
• The Termination State Table that follows shows various interactions.
The RTT values have the following priority:
•
•
•
•
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Data termination disable
RTT(WR)
RTT(NOM)
RTT(Park)
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16Gb: x4, x8, x16 DDR4 SDRAM
ODT Mode Register and ODT State Table
Table 70: Termination State Table
Case
RTT(Park)
RTT(NOM)1
RTT(WR)2
ODT Pin
ODT READS3
ODT Standby7
ODT WRITES
A4
Disabled
Disabled
Disabled
Don't Care
Off (High-Z)
Off (High-Z)
Off (High-Z)
Enabled
Don't Care
Off (High-Z)
Off (High-Z)
RTT(WR)
RTT(Park)
RTT(Park)
B5
Enabled
Disabled
Disabled
Don't Care
Off (High-Z)
Enabled
Don't Care
Off (High-Z)
RTT(Park)
RTT(WR)
C6
Disabled
Enabled
Disabled
Low
Off (High-Z)
Off (High-Z)
Off (High-Z)
High
Off (High-Z)
RTT(NOM)
RTT(NOM)
Low
Off (High-Z)
Off (High-Z)
RTT(WR)
High
Off (High-Z)
RTT(NOM)
RTT(WR)
Low
Off (High-Z)
RTT(Park)
RTT(Park)
High
Off (High-Z)
RTT(NOM)
RTT(NOM)
Low
Off (High-Z)
RTT(Park)
RTT(WR)
High
Off (High-Z)
RTT(NOM)
RTT(WR)
Enabled
D6
Enabled
Enabled
Disabled
Enabled
Notes:
1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power.
2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period
time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in
the Dynamic ODT section.
3. When a READ command is executed, the DRAM termination state will be High-Z for a
defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is
described in the ODT During Read section.
4. Case A is generally best for single-rank memories.
5. Case B is generally best for dual-rank, single-slotted memories.
6. Case C and Case D are generally best for multi-slotted memories.
7. The ODT feature is turned off and not supported in self refresh mode.
ODT Read Disable State Table
Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or
3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays
off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble
mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled.
Table 71: Read Termination Disable Window
Preamble
CRC
Start ODT Disable After
Read
Duration of ODT Disable
1tCK
Disabled
RL - 2
BL/2 + 2
Enabled
RL - 2
BL/2 + 3
Disabled
RL - 3
BL/2 + 3
Enabled
RL - 3
BL/2 + 4
2tCK
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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16Gb: x4, x8, x16 DDR4 SDRAM
Synchronous ODT Mode
Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based
on the power-down definition, these modes include the following:
•
•
•
•
•
Any bank active with CKE HIGH
Refresh with CKE HIGH
Idle mode with CKE HIGH
Active power-down mode
Precharge power-down mode
In synchronous ODT mode, RTT(NOM) will be turned on DODTLon clock cycles after
ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after
ODT is registered LOW by a rising clock edge. The ODT latency is determined by the
programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity latency (PL), as well as the programmed state of the preamble.
ODT Latency and Posted ODT
The ODT latencies for synchronous ODT mode are summarized in the table below. For
details, refer to the latency definitions.
Table 72: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200
Applicable when write CRC is disabled
Symbol
Parameter
1tCK Preamble
2tCK Preamble
Unit
tCK
DODTLon
Direct ODT turn-on latency
CWL + AL + PL - 2
CWL + AL + PL - 3
DODTLoff
Direct ODT turn-off latency
CWL + AL + PL - 2
CWL + AL + PL - 3
RODTLoff
READ command to internal ODT turn-off
latency
CL + AL + PL - 2
CL + AL + PL - 3
RODTLon4
READ command to RTT(Park) turn-on latency in BC4-fixed
RODTLoff + 4
RODTLoff + 5
RODTLon8
READ command to RTT(Park) turn-on latency in BL8/BC4-OTF
RODTLoff + 6
RODTLoff + 7
ODTH4
ODT Assertion time, BC4 mode
4
5
ODTH8
ODT Assertion time, BL8 mode
6
7
Timing Parameters
In synchronous ODT mode, the following parameters apply:
• DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX).
• tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew
between different termination values. These timing parameters apply to both the synchronous ODT mode and the data termination disable mode.
When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or
ODTH8 (BL = 8) is satisfied. If write CRC mode or 2tCK preamble mode is enabled,
ODTH should be adjusted to account for it. ODTHx is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of a WRITE command.
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
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16Gb: x4, x8, x16 DDR4 SDRAM
Synchronous ODT Mode
Figure 200: Synchronous ODT Timing with BL8
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
diff_CK
Command
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
t ADC
DRAM_RTT
tADC
(MAX)
tADC
tADC
(MIN)
RTT(Park)
RTT(NOM)
(MAX)
(MIN)
RTT(Park)
Transitioning
Notes:
1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL +
PL + CWL - 2 = 7.
2. ODT must be held HIGH for at least ODTH8 after assertion (T1).
Figure 201: Synchronous ODT with BC4
T0
T1
T2
T3
T4
T5
T18
T19
T20
T21
T22
T23
T36
T37
T38
T39
T40
T41
42
diff_CK
WRS4
Command
ODTH4
ODT
DODTLoff = WL - 2
ODTLcnw= WL - 2
ODTLcwn4 = ODTLcnw + 4
DODTLon = CWL - 2
tADC
(MAX)
tADC
RTT(Park)
(MIN)
tADC
(MAX)
tADC
(MIN)
RTT(NOM)
RTT(Park)
tADC
(MAX)
tADC
(MIN)
RTT(WR)
tADC
tADC
(MAX)
(MIN)
RTT(Park)
DRAM_RTT
Transitioning
Notes:
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1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw =
AL + PL+ CWL - 2 = 17.
2. ODT must be held HIGH for at least ODTH4 after assertion (T1).
256
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16Gb: x4, x8, x16 DDR4 SDRAM
Synchronous ODT Mode
ODT During Reads
Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT
may nominally not be enabled until the end of the postamble as shown in the example
below. At cycle T26 the device turns on the termination when it stops driving, which is
determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), then tADC
(MIN) timing may apply. If the DRAM stops driving late (that is, tHZ is late), then the
DRAM complies with tADC (MAX) timing.
Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL +
CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK
preamble.
Figure 202: ODT During Reads
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
GLIIB&.
&RPPDQG
$GGUHVV
5'
$
5/ $/&/3/
2'7
52'7/RII 5/
'2'7/RQ :/
W $'& 0$;
W $'& 0$;
W $'& 0,1
'46B2'7
W &.3UHDPEOH
W $'& 0,1
577 120
577 3DUN
W $'& 0$;
W $'& 0$;
W $'& 0,1
'46B2'7
W &.3UHDPEOH
W $'& 0,1
577 120
577 3DUN
'46GLII
W $'& 0$; Q&.
W $'& 0,1
'4B2'7
W &.3UHDPEOH
577 120
577 3DUN
'4
4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$
W $'& 0$; Q&.
W $'& 0,1
'4B2'7
W &.3UHDPEOH
W $'& 0$;
W $'& 0,1
W $'& 0$;
W $'& 0,1
577 120
577 3DUN
'4
4$ 4$ 4$ 4$ 4$ 4$ 4$ 4$
7UDQVLWLRQLQJ
CCM005-1406124318-10453
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16Gb: x4, x8, x16 DDR4 SDRAM
Dynamic ODT
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is
desirable that the termination strength of the device can be changed without issuing an
MRS command. This requirement is supported by the dynamic ODT feature.
Functional Description
Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1.
• Three RTT values are available: RTT(NOM), RTT(WR), and RTT(Park).
– The value for RTT(NOM) is preselected via bits MR1[10:8].
– The value for RTT(WR) is preselected via bits MR2[11:9].
– The value for RTT(Park) is preselected via bits MR5[8:6].
• During operation without WRITE commands, the termination is controlled as follows:
– Nominal termination strength RTT(NOM) or RTT(Park) is selected.
– RTT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and
DODTLoff, and RTT(Park) is on when ODT is LOW.
• When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is registered, and if dynamic ODT is enabled, the termination is controlled as follows:
– Latency ODTLcnw after the WRITE command, termination strength R TT(WR) is selected.
– Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for
BC4, fixed by MRS or selected OTF) after the WRITE command, termination
strength RTT(WR) is de-selected.
One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4,
depending on write CRC mode and/or 2tCK preamble enablement.
The following table shows latencies and timing parameters relevant to the on-die termination control in dynamic ODT mode. The dynamic ODT feature is not supported in
DLL-off mode. An MRS command must be used to set RTT(WR) to disable dynamic ODT
externally (MR2[11:9] = 000).
Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled)
Name and Description
Abbr. Defined from
Defined to
1600/1866/
2133/2400
2666
2933/3200
Unit
ODT latency for
change from RTT(Park)/
RTT(NOM) to RTT(WR)
Change RTT
ODTLc Registering exnw
ternal WRITE strength from
command
RTT(Park)/
RTT(NOM) to
RTT(WR)
ODTLcnw = WL - 2
tCK
ODT latency for
change from RTT(WR) to
RTT(Park)/RTT(NOM) (BC =
4)
Change RTT
ODTLc Registering exwn4
ternal WRITE strength from
command
RTT(WR) to
RTT(Park)/
RTT(NOM)
ODTLcwn4 = 4 + ODTLcnw
tCK
ODT latency for
change from RTT(WR) to
RTT(Park)/RTT(NOM) (BL =
8)
Change RTT
ODTLc Registering exwn8
ternal WRITE strength from
command
RTT(NOM) to
RTT(WR)
ODTLcwn8 = 6 + ODTLcnw
tCK
(AVG)
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16Gb: x4, x8, x16 DDR4 SDRAM
Dynamic ODT
Table 73: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) (Continued)
Name and Description
Abbr. Defined from
RTT change skew
tADC
1600/1866/
2133/2400
Defined to
ODTLcnw
ODTLcwn
RTT valid
2666
tADC
2933/3200
tADC
(MIN) =
0.30
tADC (MAX) =
0.70
Unit
tADC
tCK
(MIN) =
0.26
(AVG)
tADC (MAX) =
0.74
(MIN) =
0.28
tADC (MAX) =
0.72
Table 74: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix
1tCK Parameter
2tCK Parameter
Symbol
CRC Off
CRC On
CRC Off
CRC On
Unit
ODTLcnw1
WL - 2
WL - 2
WL - 3
WL - 3
tCK
ODTLcwn4
ODTLcnw + 4
ODTLcnw + 7
ODTLcnw + 5
ODTLcnw + 8
ODTLcwn8
ODTLcnw + 6
ODTLcnw + 7
ODTLcnw + 7
ODTLcnw + 8
1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
Note:
Figure 203: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T8
T9
T10
T11
T14
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
diff_CK
Command
WR
ODT
DODTLon = WL - 2
DODTLoff = WL - 2
tADC
tADC
(MAX)
RTT(Park)
RTT
tADC
(MAX)
RTT(Park)
RTT(WR)
tADC
tADC
(MIN)
(MIN)
tADC
tADC
(MAX)
RTT(NOM)
(MIN)
(MAX)
RTT(Park)
tADC
(MIN)
ODTLcnw
ODTLcwn
Transitioning
Notes:
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1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble).
2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then
ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled.
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Dynamic ODT
Figure 204: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)
T0
T1
T2
T5
T6
T7
T9
T10
T11
T12
T15
T16
T17
T18
T19
T20
T21
T22
T23
T24
T25
diff_CK
Command
WR
ODT
ODTLcnw
ODTLcwn8
tADC
RTT
tADC
(MAX)
RTT_NOM
tADC
(MAX)
RTT_WR
tADC
RTT_NOM
tADC
(MIN)
(MIN)
(MAX)
RTT_PARK
tADC
(MIN)
DODTLoff = CWL -2
Note:
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1. Behavior with WR command issued while ODT is registered HIGH.
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16Gb: x4, x8, x16 DDR4 SDRAM
Asynchronous ODT Mode
Asynchronous ODT Mode
Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asynchronous ODT timing mode, the internal ODT command is not delayed by either additive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)).
In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and
tAOFAS (MIN/MAX).
RTT(NOM) Turn-on Time
• Minimum RTT(NOM) turn-on time (tAONAS [MIN]) is when the device termination circuit leaves RTT(Park) and ODT resistance begins to turn on.
• Maximum RTT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has
reached RTT(NOM).
• tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH.
RTT(NOM) Turn-off Time
• Minimum RTT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination
circuit starts to leave RTT(NOM).
• Maximum RTT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has
reached RTT(Park).
• tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW.
Figure 205: Asynchronous ODT Timings with DLL Off
T0
T1
T2
T3
T4
T5
T6
Ti
Ti + 1
Ti + 2
Ti + 3
Ti + 4
Ti + 5
Ti + 6
Ta
Tb
diff_CK
CKE
tIH
tIS
tIH
tIS
ODT
tAONAS
RTT
(MAX)
tAONAS
RTT(Park)
(MIN)
RTT(NOM)
tAONAS
(MIN)
tAONAS
(MAX)
Transitioning
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Although "unlimited" row accesses to the same row is allowed
within the refresh period; excessive row accesses to the same row over a long term can
result in degraded operation.
Table 75: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
V
1
VDD
Voltage on VDD pin relative to VSS
–0.4
1.5
VDDQ
Voltage on VDDQ pin relative to VSS
–0.4
1.5
V
1
VPP
Voltage on VPP pin relative to VSS
–0.4
3.0
V
3
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.5
V
Storage temperature
–55
150
°C
TSTG
2
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are 85
105
°C
2
Notes:
1. The normal temperature range specifies the temperatures at which all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0°C to 85°C under all operating conditions for the commercial offering;
The industrial and automotive temperature offerings allow the case temperature to go
below 0°C to -40°C.
2. Some applications require operation of the commercial, industrial, and automotive temperature DRAMs in the extended temperature range (between 85°C and 105°C case
temperature). Full specifications are supported in this range, but the following additional conditions apply:
• Refer to tREFI and tRFC parameters table for tREFI requirements when operating
above 85°C
• If SELF REFRESH operation is required in the extended temperature range, it is mandatory to use either the manual self refresh mode with extended temperature range ca-
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Operating Conditions
pability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode
(MR2 [6] = 1 and MR2 [7] = 1).
Electrical Characteristics – AC and DC Operating Conditions
Supply Operating Conditions
Table 77: Recommended Supply Operating Conditions
Rating
Symbol
Parameter
Min
Typ
Max
VDD
Supply voltage
1.14
1.2
VDDQ
Supply voltage for output
1.14
1.2
Wordline supply voltage
2.375
2.5
VPP
Notes:
Unit
Notes
1.26
V
1, 2, 3, 4, 5
1.26
V
1, 2, 6
2.750
V
7
1. Under all conditions VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600
V/ms, 20 MHz band-limited measurement.
4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms.
5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than
VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDD provided the noise
doesn't alter VDD to less than VDD,min or greater than VDD,max.
6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than
VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC
level is final. AC noise of ±60mV (greater than 250 KHz) is allowed on VDDQ provided the
noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max.
7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than
VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level
is final. AC noise of ±120mV (greater than 250 KHz) is allowed on VPP provided the noise
doesn't alter VPP to less than VPP,min or greater than VPP,max.
Table 78: VDD Slew Rate
Symbol
Min
Max
Unit
Notes
VDD_sl
0.004
600
V/ms
1, 2
VDD_on
–
200
ms
3
Notes:
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1. Measurement made between 300mV and 80% VDD (minimum level).
2. The DC bandwidth is limited to 20 MHz.
3. Maximum time to ramp VDD from 300 mV to VDD minimum.
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Electrical Characteristics – AC and DC Operating Conditions
Leakages
Table 79: Leakages
Condition
Symbol
Min
Max
Unit
Notes
Input leakage (excluding ZQ and TEN)
IIN
–2
2
μA
1
ZQ leakage
IZQ
–50
10
μA
1
TEN leakage
ITEN
–6
10
μA
1, 2
VREFCA leakage
IVREFCA
–2
2
μA
3
Output leakage: VOUT = VDDQ
IOZpd
–
10
μA
4
Output leakage: VOUT = VSSQ
IOZpu
–50
–
μA
4, 5
Notes:
1.
2.
3.
4.
5.
Input under test 0V < VIN < 1.1V.
Additional leakage due to weak pull-down.
VREFCA = VDD/2, VDD at valid level after initialization.
DQs are disabled.
ODT is disabled with the ODT input HIGH.
VREFCA Supply
VREFCA is to be supplied to the DRAM and equal to V DD/2. The V REFCA is a reference supply input and therefore does not draw biasing current.
The DC-tolerance limits and AC-noise limits for the reference voltages V REFCA are illustrated in the figure below. The figure shows a valid reference voltage V REF(t) as a function
of time (VREF stands for V REFCA). V REF(DC) is the linear average of V REF(t) over a very long
period of time (1 second). This average has to meet the MIN/MAX requirements. Furthermore, V REF(t) may temporarily deviate from V REF(DC) by no more than ±1% V DD for
the AC-noise limit.
Figure 206: VREFDQ Voltage Range
Voltage
VDD
VREF(t)
VREF AC-noise
VREF(DC) MAX
VREF(DC)
VDD/2
VREF(DC) MIN
VSS
Time
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Electrical Characteristics – AC and DC Operating Conditions
The voltage levels for setup and hold time measurements are dependent on V REF. V REF is
understood as V REF(DC), as defined in the above figure. This clarifies that DC-variations
of V REF affect the absolute voltage a signal has to reach to achieve a valid HIGH or LOW
level, and therefore, the time to which setup and hold is measured. System timing and
voltage budgets need to account for V REF(DC) deviations from the optimum position
within the data-eye of the input signals. This also clarifies that the DRAM setup/hold
specification and derating values need to include time and voltage associated with V REF
AC-noise. Timing and voltage effects due to AC-noise on V REF up to the specified limit
(±1% of V DD) are included in DRAM timings and their associated deratings.
VREFDQ Supply and Calibration Ranges
The device internally generates its own V REFDQ. DRAM internal V REFDQ specification parameters: voltage range, step size, V REF step time, V REF full step time, and V REF valid level
are used to help provide estimated values for the internal V REFDQ and are not pass/fail
limits. The voltage operating range specifies the minimum required range for DDR4
SDRAM devices. The minimum range is defined by V REFDQ,min and V REFDQ,max. A calibration sequence should be performed by the DRAM controller to adjust V REFDQ and
optimize the timing and voltage margin of the DRAM data input receivers.
Table 80: VREFDQ Specification
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Range 1 VREFDQ operating points
VREFDQ R1
60%
–
92%
VDDQ
1, 2
Range 2 VREFDQ operating points
VREFDQ R2
45%
–
77%
VDDQ
1, 2
VREF,step
0.5%
0.65%
0.8%
VDDQ
3
VREF,set_tol
–1.625%
0%
1.625%
VDDQ
4, 5, 6
–0.15%
0%
0.15%
VDDQ
4, 7, 8
VREF step size
VREF set tolerance
VREF step time
VREF valid tolerance
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
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VREF,time
–
–
150
ns
9, 10, 11
VREF_val_tol
–0.15%
0%
0.15%
VDDQ
12
VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V.
DRAM range 1 or range 2 is set by the MRS6[6]6.
VREF step size increment/decrement range. VREF at DC level.
VREF,new = VREF,old ±n × VREF,step; n = number of steps. If increment, use “+,” if decrement,
use “-.”
For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 1.625% × VDDQ.
Measured by recording the MIN and MAX values of the VREF output over the range,
drawing a straight line between those points, and comparing all other VREF output settings to that line.
For n ื4, the minimum value of VREF setting tolerance = VREF,new - 0.15% × VDDQ. The
maximum value of VREF setting tolerance = VREF,new + 0.15% × VDDQ.
Measured by recording the MIN and MAX values of the VREF output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all VREF
output settings to that line.
Time from MRS command to increment or decrement one step size for VREF.
Time from MRS command to increment or decrement more than one step size up to the
full range of VREF.
If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and
an additional +15 ns/pF of DQ bus loading.
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Operating Conditions
12. Only applicable for DRAM component-level test/characterization purposes. Not applicable for normal mode of operation. VREF valid qualifies the step times, which will be characterized at the component level.
VREFDQ Ranges
MR6[6] selects range 1 (60% to 92.5% of V DDQ) or range 2 (45% to 77.5% of V DDQ), and
MR6[5:0] sets the V REFDQ level, as listed in the following table. The values in MR6[6:0]
will update the V DDQ range and level independent of MR6[7] setting. It is recommended
MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommended MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a
calibration routine.
Table 81: VREFDQ Range and Levels
MR6[5:0]
MR6[6] 0 =
Range 1
MR6[6] 1 =
Range 2
MR6[5:0]
MR6[6] 0 =
Range 1
MR6[6] 1 =
Range 2
00 0000
60.00%
45.00%
01 1010
76.90%
61.90%
00 0001
60.65%
45.65%
01 1011
77.55%
62.55%
00 0010
61.30%
46.30%
01 1100
78.20%
63.20%
00 0011
61.95%
46.95%
01 1101
78.85%
63.85%
00 0100
62.60%
47.60%
01 1110
79.50%
64.50%
00 0101
63.25%
48.25%
01 1111
80.15%
65.15%
00 0110
63.90%
48.90%
10 0000
80.80%
65.80%
00 0111
64.55%
49.55%
10 0001
81.45%
66.45%
00 1000
65.20%
50.20%
10 0010
82.10%
67.10%
00 1001
65.85%
50.85%
10 0011
82.75%
67.75%
00 1010
66.50%
51.50%
10 0100
83.40%
68.40%
00 1011
67.15%
52.15%
10 0101
84.05%
69.05%
00 1100
67.80%
52.80%
10 0110
84.70%
69.70%
00 1101
68.45%
53.45%
10 0111
85.35%
70.35%
00 1110
69.10%
54.10%
10 1000
86.00%
71.00%
00 1111
69.75%
54.75%
10 1001
86.65%
71.65%
01 0000
70.40%
55.40%
10 1010
87.30%
72.30%
01 0001
71.05%
56.05%
10 1011
87.95%
72.95%
01 0010
71.70%
56.70%
10 1100
88.60%
73.60%
01 0011
72.35%
57.35%
10 1101
89.25%
74.25%
01 0100
73.00%
58.00%
10 1110
89.90%
74.90%
01 0101
73.65%
58.65%
10 1111
90.55%
75.55%
01 0110
74.30%
59.30%
11 0000
91.20%
76.20%
01 0111
74.95%
59.95%
11 0001
91.85%
76.85%
01 1000
75.60%
60.60%
11 0010
92.50%
77.50%
01 1001
76.25%
61.25%
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11 0011 to 11 1111 are reserved
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Electrical Characteristics – AC and DC Single-Ended Input Measurement
Levels
RESET_n Input Levels
Table 82: RESET_n Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)_RESET
0.8 × VDD
VDD
V
1
DC input high voltage
VIH(DC)_RESET
0.7 × VDD
VDD
V
2
DC input low voltage
VIL(DC)_RESET
VSS
0.3 × VDD
V
3
AC input low voltage
VIL(AC)_RESET
VSS
0.2 × VDD
V
4
tR_RESET
–
1
μs
5
RESET pulse width after power-up
tPW_RESET_S
1
–
μs
6, 7
RESET pulse width during power-up
tPW_RESET_L
200
–
μs
6
Rising time
Notes:
1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_REt
SET during PW_RESET, otherwise the DRAM may not be reset.
4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table.
5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible.
6. RESET is destructive to data contents.
7. See RESET Procedure at Power Stable Condition figure.
Figure 207: RESET_n Input Slew Rate Definition
tPW_RESET
VIH(AC)_RESET,min
VIH(DC)_RESET,min
VIL(DC)_RESET,max
VIL(AC)_RESET,max
tR_RESET
Command/Address Input Levels
Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 100
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 75
VDD
mV
1, 2
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 83: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued)
Parameter
Symbol
Min
Max
Unit
Note
DC input low voltage
VIL(DC)
VSS
VREF - 75
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 100
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 84: Command and Address Input Levels: DDR4-2666
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 90
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 65
VDD
mV
1, 2
DC input low voltage
VIL(DC)
VSS
VREF - 65
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 90
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
Table 85: Command and Address Input Levels: DDR4-2933 and DDR4-3200
Parameter
Symbol
Min
Max
Unit
Note
AC input high voltage
VIH(AC)
VREF + 90
VDD5
mV
1, 2, 3
DC input high voltage
VIH(DC)
VREF + 65
VDD
mV
1, 2
DC input low voltage
VIL(DC)
VSS
VREF - 65
mV
1, 2
AC input low voltage
VIL(AC)
VSS5
VREF - 90
mV
1, 2, 3
VREFFCA(DC)
0.49 × VDD
0.51 × VDD
V
4
Reference voltage for CMD/ADDR inputs
Notes:
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1.
2.
3.
4.
For input except RESET_n. VREF = VREFCA(DC).
VREF = VREFCA(DC).
Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings.
The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than
±1% VDD (for reference: approximately ±12mV).
5. Refer to “Overshoot and Undershoot Specifications.”
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 86: Single-Ended Input Slew Rates
Parameter
Single-ended input slew rate – CA
Notes:
1.
2.
3.
4.
Symbol
Min
Max
Unit
Note
SRCA
1.0
7.0
V/ns
1, 2, 3, 4
For input except RESET_n.
VREF = VREFCA(DC).
tIS/tIH timings assume SR
CA = 1V/ns.
Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC)
for rising edges
Figure 208: Single-Ended Input Slew Rate Definition
TRse
TFse
VIH(AC)
VIH(DC)
VREFCA
VIL(DC)
VIL(AC)
Command, Control, and Address Setup, Hold, and Derating
The total tIS (setup time) and tIH (hold time) required is calculated to account for slew
rate variation by adding the data sheet tIS (base) values, the V IL(AC)/VIH(AC) points, and
tIH (base) values, the V
t
t
IL(DC)/VIH(DC) points; to the ˂ IS and ˂ IH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential
clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + ˂tIS. For a valid transition,
the input signal has to remain above/below V IH(AC)/VIL(AC) for the time defined by tVAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V IH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach
VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the
derating values may be obtained by linear interpolation.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V IH(AC)min that does not ring back below V IH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
rate between the last crossing of V IH(DC)min and the first crossing of V IL(AC)max that does
not ring back above V IL(DC)max.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V IL(DC)max and the first crossing of V IH(AC)min that does not ring back below V IH(DC)min. Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate
between the last crossing of V IH(DC)min and the first crossing of V IL(AC)minthat does not
ring back above V IL(DC)max.
Table 87: Command and Address Setup and Hold Values Referenced – AC/DC-Based
Symbol
tIS(base,
1600
1866
2133
2400
2666
2933
3200
Unit
Reference
115
100
80
62
–
–
–
ps
VIH(AC)/VIL(AC)
AC100)
tIH(base,
DC75)
140
125
105
87
–
–
–
ps
VIH(DC)/VIL(DC)
tIS(base,
AC90)
–
–
–
–
55
48
40
ps
VIH(AC)/VIL(AC)
tIH(base,
DC65)
tIS/tIH(Vref)
–
–
–
–
80
73
65
ps
VIH(DC)/VIL(DC)
215
200
180
162
145
138
130
ps
VIH(DC)/VIL(DC)
Table 88: Derating Values for tIS/tIH – AC100DC75-Based
˂tIS with AC100 Threshold, ˂tIH with DC75 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIH
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
7.0
76
54
76
55
77
56
79
58
82
60
86
64
94
73
111
89
6.0
73
53
74
53
75
54
77
56
79
58
83
63
92
71
108
88
5.0
70
50
71
51
72
52
74
54
76
56
80
60
88
68
105
85
4.0
65
46
66
47
67
48
69
50
71
52
75
56
83
65
100
81
3.0
57
40
57
41
58
42
60
44
63
46
67
50
75
58
92
75
2.0
40
28
41
28
42
29
44
31
46
33
50
38
58
46
75
63
1.5
23
15
24
16
25
17
27
19
29
21
33
25
42
33
58
50
1.0
–10
–10
–9
–9
–8
–8
–6
–6
–4
–4
0
0
8
8
25
25
0.9
–17
–14
–16
–14
–15
–13
–13
–10
–11
–8
–7
–4
1
4
18
21
0.8
–26
–19
–25
–19
–24
–18
–22
–16
–20
–14
–16
–9
–7
–1
9
16
0.7
–37
–26
–36
–25
–35
–24
–33
–22
–31
–20
–27
–16
–18
–8
–2
9
0.6
–52
–35
–51
–34
–50
–33
–48
–31
–46
–29
–42
–25
–33
–17
–17
0
0.5
–73
–48
–72
–47
–71
–46
–69
–44
–67
–42
–63
–38
–54
–29
–38
–13
0.4
–104
–66
–103
–66
–102
–65
–100
–63
–98
–60
–94
–56
–85
–48
–69
–31
10.0 V/ns
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8.0 V/ns
6.0 V/ns
4.0 V/ns
270
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 89: Derating Values for tIS/tIH – AC90/DC65-Based
˂tIS with AC90 Threshold, ˂tIH with DC65 Threshold Derating (ps) – AC/DC-Based
CMD/
ADDR
Slew Rate
V/ns
CK, CK# Differential Slew Rate
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
˂tIH
˂tIH
˂tIS
˂tIH
˂tIS
˂tIH
7.0
68
47
69
47
70
48
72
50
73
52
77
56
85
63
100
78
6.0
66
45
67
46
68
47
69
49
71
50
75
54
83
62
98
77
5.0
63
43
64
44
65
45
66
46
68
48
72
52
80
60
95
75
4.0
59
40
59
40
60
41
62
43
64
45
68
49
75
56
90
71
3.0
51
34
52
35
53
36
54
38
56
40
60
43
68
51
83
66
2.0
36
24
37
24
38
25
39
27
41
29
45
33
53
40
68
55
1.5
21
13
22
13
23
14
24
16
26
18
30
22
38
29
53
44
1.0
–9
–9
–8
–8
–8
–8
–6
–6
–4
–4
0
0
8
8
23
23
0.9
–15
–13
–15
–12
–14
–11
–12
–9
–10
–7
–6
–4
1
4
16
19
0.8
–23
–17
–23
–17
–22
–16
–20
–14
–18
–12
–14
–8
–7
–1
8
14
0.7
–34
–23
–33
–22
–32
–21
–30
–20
–28
–18
–25
–14
–17
–6
–2
9
0.6
–47
–31
–47
–30
–46
–29
–44
–27
–42
–25
–38
–22
–31
–14
–16
1
0.5
–67
–42
–66
–41
–65
–40
–63
–38
–61
–36
–58
–33
–50
–25
–35
–10
0.4
–95
–58
–95
–57
–94
–56
–92
–54
–90
–53
–86
–49
–79
–41
–64
–26
10.0 V/ns
8.0 V/ns
6.0 V/ns
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.5 V/ns
1.0 V/ns
Data Receiver Input Requirements
The following parameters apply to the data receiver Rx MASK operation detailed in the
Write Timing section, Data Strobe-to-Data Relationship.
The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement
points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time,
tr1, is measured from 0.5 × V diVW,max below V CENTDQ,midpoint to the last transition
through 0.5 × V diVW,max above V CENTDQ,midpoint; tr2 is measured from the last transition
through 0.5 × V diVW,max above V CENTDQ,midpoint to the first transition through the 0.5 ×
VIHL(AC)min above V CENTDQ,midpoint.
The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement
points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time,
tf1, is measured from 0.5 × V diVW,max above V CENTDQ,midpoint to the last transition
through 0.5 × V diVW,max below V CENTDQ,midpoint; tf2 is measured from the last transition
through 0.5 × V diVW,max below V CENTDQ,midpoint to the first transition through the 0.5 ×
VIHL(AC)min below V CENTDQ,midpoint.
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 209: DQ Slew Rate Definitions
VCENTDQ,midpoint
0.5 × VdiVW,max
VdiVW,max
0.5 ×
VIHL(AC)min
0.5 ×
VIHL(AC)min
tr1
tf1
0.5 × VdiVW,max
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW,max
VdiVW,max
0.5 ×
VIHL(AC)min
0.5 × VdiVW,max
Rx Mask
0.5 ×
VIHL(AC)min
VIHL(AC)min
VIHL(AC)min
tr2
tf2
Notes:
1.
2.
3.
4.
Rising edge slew rate equation srr1 = VdiVW,max/(tr1).
Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 × tr2).
Falling edge slew rate equation srf1 = VdiVW,max/(tf1).
Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 × tf2).
Table 90: DQ Input Receiver Specifications
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Not
es
VIN Rx mask input
peak-to-peak
VdiVW
–
136
–
130
–
120
–
115
–
110
mV
2, 3
DQ Rx input timing window
TdiVW
–
0.2
–
0.2
–
0.22
–
0.23
–
0.23
UI
2, 3
DQ AC input
swing peak-topeak
VIHL(AC)
186
–
160
–
150
–
145
–
140
–
mV
4, 5
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 90: DQ Input Receiver Specifications (Continued)
Note 1 applies to the entire table
DDR4-1600,
1866, 2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Not
es
DQ input pulse
width
TdiPW
0.58
–
0.58
–
0.58
–
0.58
–
0.58
–
UI
6
DQS-to-DQ Rx
mask offset
tDQS2D
–0.17
0.17
–0.17
0.17
–0.19
0.19
–0.22
0.22
–0.22
0.22
UI
7
DQ-to-DQ Rx mask
offset
tDQ2DQ
–
0.1
–
0.1
–
0.105
–
0.115
–
0.125
UI
8
srr1, srf1
Input slew rate
over VdiVW if tCK ุ
0.937ns
1
9
1
9
1
9
1
9
1
9
V/ns
9
Input slew rate
over VdiVW if
0.937ns > tCK ุ
0.625ns
srr1, srf1
–
–
1.25
9
1.25
9
1.25
9
1.25
9
V/ns
9
Rising input slew
rate over 1/2
VIHL(AC)
srr2
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
0.2 ×
srr1
9
V/ns
10
Falling input slew
rate over 1/2
VIHL(AC)
srf2
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
0.2 ×
srf1
9
V/ns
10
Q
Notes:
1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew
rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased
to the point where the minimum input pulse width would no longer be violated.
2. Data Rx mask voltage and timing total input valid window where VdiVW is centered
around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied
per bit and should include voltage and temperature drift terms. The input buffer design
specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated.
3. Defined over the DQ internal VREF range 1.
4. Overshoot and undershoot specifications apply.
5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min
is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a
valid TdiPW).
6. DQ minimum input pulse width defined at the VCENTDQ,midpoint.
7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word
(x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM
balls over process, voltage, and temperature.
8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at
the SDRAM balls for a given component over process, voltage, and temperature.
9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to
fastest DQ slew rate per transition edge must be within 1.7V/ns of each other.
10. Input slew rate between VdiVW mask edge and VIHL(AC)min points.
The following figure shows the Rx mask relationship to the input timing specifications
relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; however, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the
input pulse width specification is satisfied and the Rx mask is not violated.
Figure 210: Rx Mask Relative to tDS/tDH
TdiPW
VIH(DC)
VdiVW
0.5 × VdiVW
VCENTDQ,pin mean
Rx
Mask
0.5 × VdiVW
VIL(DC)
tf1
tr1
TdiVW
tDS
tDH
= Greater of 0.5 × TdiVW
or
0.5 × (TdiPW + VdiVW/tf1)
= Greater of 0.5 × TdiVW
or
0.5 × (TdiPW + VdiVW/tr1)
DQS_c
DQS_t
The following figure and table show an example of the worst case Rx mask required if
the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The
figure and table show that without DRAM write DQ training, the Rx mask would increase from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH
required as well.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 211: Rx Mask Without Write Training
TdiVW + 2 × tDQS2DQ
VdiVW
VIH(DC)
0.5 × VdiVW
Rx Mask
VCENTDQ,midpoint
0.5 × VdiVW
VIL(DC)
tDS
tDH
0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ
DQS_c
DQS_t
Table 91: Rx Mask and tDS/tDH without Write Training
Rx Mask
with Write
Train
(ps)
DDR4
VIHL(AC)
(mV)
TdiPW
(UI)
VdiVW
(mV)
TdiVW
(UI)
tDQS2DQ
tDQ2DQ
(UI)
(UI)
1600
186
0.58
136
0.2
±0.17
0.1
125
1866
186
0.58
136
0.2
±0.17
0.1
107.1
289
2133
186
0.58
136
0.2
±0.17
0.1
94
253
2400
160
0.58
130
0.2
±0.17
0.1
83.3
225
2666
150
0.58
120
0.22
±0.19
0.105
82.5
225
2933
145
0.58
115
0.23
±0.22
0.115
78.4
228
3200
140
0.58
110
0.23
±0.22
0.125
71.8
209
Note:
tDS
+ tDH
(ps)
338
1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint.
Connectivity Test (CT) Mode Input Levels
Table 92: TEN Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
TEN AC input high voltage
VIH(AC)_TEN
0.8 × VDD
VDD
V
1
TEN DC input high voltage
VIH(DC)_TEN
0.7 × VDD
VDD
V
TEN DC input low voltage
VIL(DC)_TEN
VSS
0.3 × VDD
V
TEN AC input low voltage
VIL(AC)_TEN
VSS
0.2 × VDD
V
tF_TEN
–
10
ns
TEN falling time
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 92: TEN Input Levels (CMOS) (Continued)
Parameter
TEN rising time
Symbol
Min
Max
Unit
tR_TEN
–
10
ns
Note
1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
Notes:
Figure 212: TEN Input Slew Rate Definition
VIH(AC)_TENmin
VIH(DC)_TENmin
VIL(DC)_TENmin
VIL(AC)_TENmin
tF_TEN
tR_TEN
Table 93: CT Type-A Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipA AC input high voltage
VIH(AC)
VREF + 200
VDD11
V
2, 3
CTipA DC input high voltage
VIH(DC)
VREF + 150
VDD
V
2, 3
CTipA DC input low voltage
VIL(DC)
VSS
VREF - 150
V
2, 3
1
VIL(AC)
VSS1
VREF - 200
V
2, 3
CTipA falling time
tF_CTipA
–
5
ns
2
CTipA rising time
tR_CTipA
–
5
ns
2
CTipA AC input low voltage
Notes:
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14,
CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR.
3. VREFCA = 0.5 × VDD.
Figure 213: CT Type-A Input Slew Rate Definition
VIH(AC)_CTipAmin
VIH(DC)_CTipAmin
VREFCA
VIL(DC)_CTipAmax
VIL(AC)_CTipAmax
tR_CTipA
tF_CTipA
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Table 94: CT Type-B Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipB AC input high voltage
VIH(AC)
VREF + 300
VDD11
V
2, 3
CTipB DC input high voltage
VIH(DC)
VREF + 200
VDD
V
2, 3
CTipB DC input low voltage
VIL(DC)
VSS
VREF - 200
V
2, 3
1
VIL(AC)
VSS1
VREF - 300
V
2, 3
CTipB falling time
tF_CTipB
–
5
ns
2
CTipB rising time
tR_CTipB
–
5
ns
2
CTipB AC input low voltage
Notes:
1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n.
3. VREFDQ should be 0.5 × VDD
Figure 214: CT Type-B Input Slew Rate Definition
VIH(AC)_CTipBmin
VIH(DC)_CTipBmin
VREFDQ
VIL(DC)_CTipBmax
VIL(AC)_CTipBmax
tF_CTipB
tR_CTipB
Table 95: CT Type-C Input Levels (CMOS)
Parameter
Symbol
Min
Max
Unit
Note
1
V
2
CTipC AC input high voltage
VIH(AC)_CTipC
0.8 × VDD
VDD
CTipC DC input high voltage
VIH(DC)_CTipC
0.7 × VDD
VDD
V
2
CTipC DC input low voltage
VIL(DC)_CTipC
VSS
0.3 × VDD
V
2
CTipC AC input low voltage
VIL(AC)_CTipC
VSS1
0.2 × VDD
V
2
CTipC falling time
tF_CTipC
–
10
ns
2
CTipC rising time
tR_CTipC
–
10
ns
2
Notes:
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1. Refer to Overshoot and Undershoot Specifications.
2. CT Type-C inputs: Alert_n.
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Electrical Characteristics – AC and DC Single-Ended Input
Measurement Levels
Figure 215: CT Type-C Input Slew Rate Definition
VIH(AC)_TENmin
VIH(DC)_TENmin
VIL(DC)_TENmin
VIL(AC)_TENmin
tF_TEN
tR_TEN
Table 96: CT Type-D Input Levels
Parameter
Symbol
Min
Max
Unit
Note
CTipD AC input high voltage
VIH(AC)_CTipD
0.8 × VDD
VDD
V
4
CTipD DC input high voltage
VIH(DC)_CTipD
0.7 × VDD
VDD
V
2
CTipD DC input low voltage
VIL(DC)_CTipD
VSS
0.3 × VDD
V
1
CTipD AC input low voltage
VIL(AC)_CTipD
VSS
0.2 × VDD
V
5
tR_RESET
–
1
μs
3
RESET pulse width - after power-up
tPW_RESET_S
1
–
μs
RESET pulse width - during power-up
tPW_RESET_L
200
–
μs
Rising time
Notes:
1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_REt
SET during PW_RESET, otherwise, the DRAM may not be reset.
2. After RESET_n is registered HIGH, the RESET_n level must be maintained above
VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n
signal LOW.
3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible.
4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table.
5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table.
6. CT Type-D inputs: RESET_n; same requirements as in normal mode.
Figure 216: CT Type-D Input Slew Rate Definition
tPW_RESET
VIH(AC)_RESETmin
VIH(DC)_RESETmin
VIL(DC)_RESETmax
VIL(AC)_RESETmax
tR_RESET
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Electrical Characteristics – AC and DC Differential Input Measurement
Levels
Differential Inputs
Figure 217: Differential AC Swing and “Time Exceeding AC-Level” tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK_t, CK_c
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Notes:
1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope.
2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope.
Table 97: Differential Input Swing Requirements for CK_t, CK_c
DDR4-2400 /
2666
Parameter
Symbol
DDR4-1600 /
1866 / 2133
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Note
s
Differential input high
VIHdiff
150
Note 3
135
Note 3
125
Note 3
110
Note 3
mV
1
Differential input low
VILdiff
Note 3
–150
Note 3
-135
Note 3
-125
Note 3
-110
mV
1
Differential input high
(AC)
VIH-
2×
(VIH(AC)
- VREF)
Note 3
2×
(VIH(AC)
- VREF)
Note 3
2×
(VIH(AC)
- VREF)
Note 3
2×
(VIH(AC)
- VREF)
Note 3
V
2
diff(AC)
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DDR4-2933
DDR4-3200
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 97: Differential Input Swing Requirements for CK_t, CK_c (Continued)
Parameter
Differential input low
(AC)
Symbol
DDR4-1600 /
1866 / 2133
DDR4-2400 /
2666
Min
Min
VIL-
Note 3
diff(AC)
Notes:
Max
Max
DDR4-2933
Min
Max
DDR4-3200
Min
Max
Unit
Note
s
V
2
Note 3
2×
Note 3
2×
Note 3
2×
2×
(VIL(AC) (VIL(AC) (VIL(AC) (VIL(AC) VREF)
VREF)
VREF)
VREF)
1. Used to define a differential signal slew-rate.
2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA.
3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be
within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as
the limitations for overshoot and undershoot.
Table 98: Minimum Time AC Time tDVAC for CK
tDVAC
Note:
(ps) at |VIH,diff(AC) to VIL,diff(AC)|
Slew Rate (V/ns)
200mV
TBDmV
>4.0
120
TBD
4.0
115
TBD
3.0
110
TBD
2.0
105
TBD
1.9
100
TBD
1.6
95
TBD
1.4
90
TBD
1.2
85
TBD
1.0
80
TBD
VDD/2 + 145mV
N/A
120mV
VDD/2 + 100mV ื VSEH ื VDD/2 + 145mV
N/A
(VSEH - VDD/2) - 25mV
VDD/2 - 145mV ื VSEL ื VDD/2 - 100mV
–(VDD/2 - VSEL) + 25mV
N/A
VSEL < VDD/2 - 145mV
–120mV
N/A
Table 102: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200
DDR4-2666, 2933, 3200
Parameter
Differential input
cross point voltage relative to
VDD/2 for CK_t,
CK_c
Sym
Input Level
Min
Max
VIX(CK)
VSEH > VDD/2 + 145mV
N/A
110mV
VDD/2 + 90mV ื VSEH ื VDD/2 + 145mV
N/A
(VSEH - VDD/2) - 30mV
VDD/2 - 145mV ื VSEL ื VDD/2 - 90mV
–(VDD/2 - VSEL) + 30mV
N/A
VSEL < VDD/2 - 145mV
–110mV
N/A
DQS Differential Input Signal Definition and Swing Requirements
DQS_t, DQS_c: Differential Input Voltage
Figure 221: Differential Input Signal Definition for DQS_t, DQS_c
VIH,diff,peak
Half cycle
0.0V
Half cycle
VIL,diff,peak
Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c
DDR4-1600, 1866,
2133
Parameter
Peak differential input high voltage
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DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
VIH,diff,peak
186
VDDQ
160
VDDQ
mV
1,2
283
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 103: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c
(Continued)
DDR4-1600, 1866,
2133
Parameter
Peak differential input low voltage
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
VIL,diff,peak
VSSQ
–186
VSSQ
–160
mV
1,2
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.
Notes:
Table 104: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c
Parameter
DDR4-2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Peak differential input high voltage
VIH,diff,peak
150
VDDQ
145
VDDQ
140
VDDQ
mV
1,2
Peak differential input low voltage
VIL,diff,peak
VSSQ
–150
VSSQ
–145
VSSQ
–140
mV
1,2
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Minimum value point is used to determine differential signal slew-rate.
Notes:
The peak voltage of the DQS signals are calculated using the following equations:
VIH,dif,Peak voltage = MAX(ft)
VIL,dif,Peak voltage = MIN(ft)
(ft) = DQS_t, DQS_c.
The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the
±35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all UIs.
DQS_t, DQS_c: Single-Ended Input Voltages
Figure 222: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling
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DQS_t
+35%
+50%
MIN(ft)
MAX(ft)
–35%
–50%
DQS_c
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
DQS Differential Input Cross Point Voltage
To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must
meet V IX_DQS,ratio in the table below. The differential input cross point voltage V IX_DQS
(VIX_DQS_FR and V IX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c
relative to the V DQS,mid of the DQS_t and DQS_c signals.
VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t
and DQS_c signals, and noted by V DQS_trans. V DQS_trans is the difference between the lowest horizontal tangent above V DQS,mid of the transitioning DQS signals and the highest
horizontal tangent below V DQS,mid of the transitioning DQS signals. A non-monotonic
transitioning signal’s ledge is exempt or not used in determination of a horizontal tangent provided the said ledge occurs within ±35% of the midpoint of either V IH.DIFF.Peak
voltage (DQS_t rising) or V IL.DIFF.Peak voltage (DQS_c rising), as shown in the figure below.
A secondary horizontal tangent resulting from a ring-back transition is also exempt in
determination of a horizontal tangent. That is, a falling transition’s horizontal tangent is
derived from its negative slope to zero slope transition (point A in the figure below), and
a ring-back’s horizontal tangent is derived from its positive slope to zero slope transition (point B in the figure below) and is not a valid horizontal tangent; a rising transition’s horizontal tangent is derived from its positive slope to zero slope transition (point
C in the figure below), and a ring-back’s horizontal tangent derived from its negative
slope to zero slope transition (point D in the figure below) and is not a valid horizontal
tangent.
Figure 223: VIXDQS Definition
Lowest horizontal tanget above VDQS,mid
of the transitioning signals
VIX_DQS,FR
VIX_DQS,RF
VDQS,mid
VIX_DQS,FR
VIX_DQS,RF
B
VDQS_trans
D
VDQS_trans/2
DQS_t, DQS_c: Single-Ended Input Voltages
C
DQS_t
DQS_c
A
Highest horizontal tanget below VDQS,mid
of the transitioning signals
VSSQ
Table 105: Cross Point Voltage For Differential Input Signals DQS
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
DQS_t and DQS_c crossing relative to the
midpoint of the DQS_t and DQS_c signal
swings
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Symbol
Min
Max
Unit
Notes
VIX_DQS,ratio
–
25
%
1, 2
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 105: Cross Point Voltage For Differential Input Signals DQS (Continued)
DDR4-1600, 1866, 2133, 2400,
2666, 2933, 3200
Parameter
VDQS,mid to Vcent(midpoint) offset
Symbol
Min
Max
Unit
Notes
VDQS,mid_to_Vcent
–
Note 3
mV
2
1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is
the difference between the lowest horizontal tangent above VDQS,midd of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning
DQS signals.
2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) obtained during VREF Training if the DQS and DQs drivers and paths are matched.
3. The maximum limit shall not exceed the smaller of VIH,diff,DQS minimum limit or 50mV.
Notes:
Slew Rate Definitions for DQS Differential Input Signals
Table 106: DQS Differential Input Slew Rate Definition
Measured
Description
From
To
Defined by
Differential input slew rate for rising edge
V IL,diff,DQS
V IH,diff,DQS
|VIH,diff,DQS - VIL,diff,DQS_˂TRdiff
Differential input slew rate for falling edge
V IH,diff,DQS
V IL,diff,DQS
|VIHdiffDQS - VIL,diff,DQS_˂TFdiff
1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds.
Note:
DQS_t, DQS_c: Differential Input Voltage
Figure 224: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c
VIH,diff,peak
VIH,diff,DQS
0.0V
VIL,diff,DQS
TRdiff
TFdiff
VIL,diff,peak
Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-1600, 1866, 2133
Parameter
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
Peak differential input high voltage
VIH,diff,peak
186
VDDQ
160
VDDQ
mV
1
Differential input high voltage
VIH,diff,DQS
136
–
130
–
mV
2, 3
Differential input low voltage
VIL,diff,DQS
–
–136
–
–130
mV
2, 3
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Electrical Characteristics – AC and DC Differential Input Measurement Levels
Table 107: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c (Continued)
DDR4-1600, 1866, 2133
Parameter
Peak differential input low voltage
DQS differential input slew rate
Notes:
DDR4-2400
Symbol
Min
Max
Min
Max
Unit
Notes
VIL,diff,peak
VSSQ
–186
VSSQ
–160
mV
1
SRIdiff
3.0
18
3.0
18
V/ns
4, 5
1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_˂TRdiff.
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_˂TFdiff.
Table 108: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t,
DQS_c
DDR4-2666
Parameter
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Peak differential input
high voltage
VIH,diff,peak
150
VDDQ
145
VDDQ
140
VDDQ
mV
1
Differential input high
voltage
VIH,diff,DQS
130
–
115
–
110
–
mV
2, 3
Differential input low
voltage
VIL,diff,DQS
–
–130
–
–115
–
–110
mV
2, 3
Peak differential input
low voltage
VIL,diff,peak
VSSQ
–150
VSSQ
–145
VSSQ
–140
mV
1
DQS differential input
slew rate
SRIdiff
2.5
18
2.5
18
2.5
18
V/ns
4, 5
Notes:
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1. Minimum and maximum limits are relative to single-ended portion and can be exceeded
within allowed overshoot and undershoot limits.
2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope.
3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope.
4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_˂TRdiff.
5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |
VIL,diff,min - VIH,diff,max_˂TFdiff.
287
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Electrical Characteristics – Overshoot and Undershoot Specifications
Electrical Characteristics – Overshoot and Undershoot Specifications
Address, Command, and Control Overshoot and Undershoot Specifications
Table 109: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications
DDR41600
Description
DDR41866
DDR42133
DDR42400
DDR42666
DDR4- DDR42933 3200
Unit
Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0)
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.06
0.06
0.06
0.06
0.06
0.06
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSS
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area A maximum overshoot area per 1tCK
0.0083
0.0071
0.0062
0.0055
0.0055
0.0055
0.0055
V/ns
1tCK
0.2550
0.2185
0.1914
0.1699
0.1699
0.1699
0.1699
V/ns
0.2644
0.2265
0.1984
0.1762
0.1762
0.1762
0.1762
V/ns
Area B maximum overshoot area per
Area C maximum undershoot area per
1tCK
Figure 225: ADDR, CMD, CNTL Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDD absolute MAX
VDD
A
Overshoot area above VDD absolute MAX
B
Overshoot area below VDD absolute MAX
and above VDD MAX
1tCK
VSS
C
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Electrical Characteristics – Overshoot and Undershoot Specifications
Clock Overshoot and Undershoot Specifications
Table 110: CK Overshoot and Undershoot/ Specifications
DDR41600
DDR41866
DDR42133
DDR42400
DDR42666
Area A: Maximum peak amplitude above VDD
absolute MAX
0.06
0.06
0.06
0.06
0.06
0.06
0.06
V
Area B: Amplitude allowed between VDD and
VDD absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSS
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area A maximum overshoot area per 1UI
0.0038
0.0032
0.0028
0.0025
0.0025
0.0025
0.0025
V/ns
Area B maximum overshoot area per 1UI
0.1125
0.0964
0.0844
0.0750
0.0750
0.0750
0.0750
V/ns
Area C maximum undershoot area per 1UI
0.1144
0.0980
0.0858
0.0762
0.0762
0.0762
0.0762
V/ns
Description
DDR4- DDR42933 3200
Unit
CLK_t, CLK_n
Figure 226: CK Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDD absolute MAX
A
Overshoot area above VDD absolute MAX
B
Overshoot area below VDD absolute MAX
and above VDD MAX
VDD
1UI
VSS
C
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Electrical Characteristics – AC and DC Output Measurement
Levels
Data, Strobe, and Mask Overshoot and Undershoot Specifications
Table 111: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications
DDR41600
Description
DDR41866
DDR42133
DDR42400
DDR42666
DDR4- DDR42933 3200
Unit
DQS_t, DQS_n, LDQS_t, LDQS_n, UDQS_t, UDQS_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI,
Area A: Maximum peak amplitude above VDDQ
absolute MAX
0.16
0.16
0.16
0.16
0.16
0.16
0.16
V
Area B: Amplitude allowed between VDDQ and
VDDQ absolute MAX
0.24
0.24
0.24
0.24
0.24
0.24
0.24
V
Area C: Maximum peak amplitude allowed for
undershoot below VSSQ
0.30
0.30
0.30
0.30
0.30
0.30
0.30
V
Area D: Maximum peak amplitude below VSSQ
absolute MIN
0.10
0.10
0.10
0.10
0.10
0.10
0.10
V
Area A maximum overshoot area per 1UI
0.0150
0.0129
0.0113
0.0100
0.0100
0.0100
0.0100
V/ns
Area B maximum overshoot area per 1UI
0.1050
0.0900
0.0788
0.0700
0.0700
0.0700
0.0700
V/ns
Area C maximum undershoot area per 1UI
0.1050
0.0900
0.0788
0.0700
0.0700
0.0700
0.0700
V/ns
Area D maximum undershoot area per 1UI
0.0150
0.0129
0.0113
0.0100
0.0100
0.0100
0.0100
V/ns
Figure 227: Data, Strobe, and Mask Overshoot and Undershoot Definition
Absolute MAX overshoot
Volts (V)
VDDQ absolute MAX
A
Overshoot area above VDDQ absolute MAX
B
Overshoot area below VDDQ absolute MAX
and above VDDQ MAX
VDDQ
1UI
VSSQ
C
VSSQ absolute MIN
Undershoot area below VSSQ MIN and
above VSSQ absolute MIN
D
Undershoot area below VSSQ absolute MIN
Absolute MAX undershoot
Electrical Characteristics – AC and DC Output Measurement Levels
Single-Ended Outputs
Table 112: Single-Ended Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
DC output high measurement level (for IV curve linearity)
VOH(DC)
1.1 × VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.8 × VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.5 × VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
(0.7 + 0.15) × VDDQ
V
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 112: Single-Ended Output Levels (Continued)
Parameter
AC output low measurement level (for output slew rate)
Symbol
DDR4-1600 to DDR4-3200
Unit
VOL(AC)
(0.7 - 0.15) × VDDQ
V
1. The swing of ±0.15 × VDDQ is based on approximately 50% of the static single-ended
output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load
of 50˖ to VTT = VDDQ.
Note:
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL(AC) and V OH(AC) for singleended signals.
Table 113: Single-Ended Output Slew Rate Definition
Measured
Description
From
To
Defined by
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)@˂TRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)@˂TFse
Figure 228: Single-ended Output Slew Rate Definition
TRse
Single-Ended Output Voltage (DQ)
VOH(AC)
VOL(AC)
TFse
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Electrical Characteristics – AC and DC Output Measurement
Levels
Table 114: Single-Ended Output Slew Rate
For RON = RZQ/7
DDR4-1600/ 1866 / 2133 /
2400
Parameter
DDR4-2666
DDR4-2933 / 3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
SRQse
4
9
4
9
4
9
V/ns
Single-ended output
slew rate
1. SR = slew rate; Q = query output; se = single-ended signals.
2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte
lane:
Notes:
• Case 1 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are static (they stay at either HIGH or LOW).
• Case 2 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are switching into the opposite direction (from LOW-toHIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the
opposite direction, the standard maximum limit of 9 V/ns applies.
Differential Outputs
Table 115: Differential Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
AC differential output high measurement level (for output slew
rate)
VOH,diff(AC)
0.3 × VDDQ
V
AC differential output low measurement level (for output slew
rate)
VOL,diff(AC)
–0.3 × VDDQ
V
Note:
1. The swing of ±0.3 × VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of
50˖ to VTT = VDDQ at each differential output.
Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between V OL,diff(AC) and V OH,diff(AC) for differential signals.
Table 116: Differential Output Slew Rate Definition
Measured
Description
From
To
Defined by
Differential output slew rate for rising edge
VOL,diff(AC)
VOH,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)@˂TRdiff
Differential output slew rate for falling edge
VOH,diff(AC)
VOL,diff(AC)
[VOH,diff(AC) - VOL,diff(AC)@˂TFdiff
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 229: Differential Output Slew Rate Definition
Differential Input Voltage (DQS_t, DQS_c)
TRdiff
VOH,diff(AC)
VOL,diff(AC)
TFdiff
Table 117: Differential Output Slew Rate
For RON = RZQ/7
DDR4-1600 / 1866 /
2133 / 2400
Parameter
Differential output slew
rate
Note:
DDR4-2666
DDR4-2933 / 3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
SRQdiff
8
18
8
18
8
18
V/ns
1. SR = slew rate; Q = query output; diff = differential signals.
Reference Load for AC Timing and Output Slew Rate
The effective reference load of 50˖ to V TT = V DDQ and driver impedance of RZQ/7 for
each output was used in defining the relevant AC timing parameters of the device as
well as output slew rate measurements.
RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC
timing parameter values of the device. The maximum DC high level of output signal =
1.0 × V DDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } × V DDQ = 0.4 ×
VDDQ.
The nominal reference level of an output signal can be approximated by the following:
The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } × V DDQ = 0.7 ×
VDDQ. The actual reference level of output signal might vary with driver R ON and reference load tolerances. Thus, the actual reference level or midpoint of an output signal is
at the widest part of the output signal’s eye.
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Electrical Characteristics – AC and DC Output Measurement
Levels
Figure 230: Reference Load For AC Timing and Output Slew Rate
VDDQ
VTT = VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
RTT = 50ȍ
VSSQ
Timing reference point
Connectivity Test Mode Output Levels
Table 118: Connectivity Test Mode Output Levels
Parameter
Symbol
DDR4-1600 to DDR4-3200
Unit
DC output high measurement level (for IV curve linearity)
VOH(DC)
1.1 × VDDQ
V
DC output mid measurement level (for IV curve linearity)
VOM(DC)
0.8 × VDDQ
V
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.5 × VDDQ
V
DC output below measurement level (for IV curve linearity)
VOB(DC)
0.2 × VDDQ
V
AC output high measurement level (for output slew rate)
VOH(AC)
VTT + (0.1 × VDDQ)
V
AC output low measurement level (for output slew rate)
VOL(AC)
VTT - (0.1 × VDDQ)
V
Note:
1. Driver impedance of RZQ/7 and an effective test load of 50˖ to VTT = VDDQ.
Figure 231: Connectivity Test Mode Reference Test Load
VDDQ
CT_Inputs
DUT
DQ, DQS_t, DQS_c,
LDQS_t, LDQS_c, UDQS_t, UDQS_c,
DM, LDM, HDM, TDQS_t, TDQS_c
0.5 × VDDQ
RTT = 50 ȍ
VSSQ
Timing reference point
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Electrical Characteristics – AC and DC Output Driver Characteristics
Figure 232: Connectivity Test Mode Output Slew Rate Definition
VOH(AC)
VTT
0.5 x VDD
VOL(AC)
TFoutput_CT
TRoutput_CT
Table 119: Connectivity Test Mode Output Slew Rate
DDR4-1600 / 1866 /
2133 / 2400
Parameter
DDR4-2666
DDR4-2933 /
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Output signal falling time
TF_output_CT
–
10
–
10
–
10
ns/V
Output signal rising time
TR_output_CT
–
10
–
10
–
10
ns/V
Electrical Characteristics – AC and DC Output Driver Characteristics
Connectivity Test Mode Output Driver Electrical Characteristics
The DDR4 driver supports special values during connectivity test mode. These R ON values are referenced in this section. A functional representation of the output buffer is
shown in the figure below.
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Electrical Characteristics – AC and DC Output Driver Characteristics
Figure 233: Output Driver During Connectivity Test Mode
Chip in drive mode
Output driver
VDDQ
IPU_CT
To
other
circuitry
like
RCV,
...
RONPU_CT
DQ
RONPD_CT
IPD_CT
IOUT
VOUT
VSSQ
The output driver impedance, RON, is determined by the value of the external reference
resistor RZQ as follows: RON = RZQ/7. This targets 34˖ with nominal RZQ ˖; however,
connectivity test mode uses uncalibrated drivers and only a maximum target is defined.
Mismatch between pull up and pull down is undefined.
The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as
follows:
RONPu_CT when RONPd_CT is off:
52138B&7
9''49287
,287
RONPD_CT when RONPU_CT is off:
5213'B&7
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,287
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Electrical Characteristics – AC and DC Output Driver Characteristics
Table 120: Output Driver Electrical Characteristics During Connectivity Test Mode
Assumes RZQ ˖; ZQ calibration not required
RON,nom_CT
Resistor
RONPD_CT
˖
RONPU_CT
VOUT
Min
Nom
Max
Unit
VOB(DC) = 0.2 × VDDQ
N/A
N/A
1.9
RZQ/7
VOL(DC) = 0.5 × VDDQ
N/A
N/A
2.0
RZQ/7
VOM(DC) = 0.8 × VDDQ
N/A
N/A
2.2
RZQ/7
VOH(DC) = 1.1 × VDDQ
N/A
N/A
2.5
RZQ/7
VOB(DC) = 0.2 × VDDQ
N/A
N/A
1.9
RZQ/7
VOL(DC) = 0.5 × VDDQ
N/A
N/A
2.0
RZQ/7
VOM(DC) = 0.8 × VDDQ
N/A
N/A
2.2
RZQ/7
VOH(DC) = 1.1 × VDDQ
N/A
N/A
2.5
RZQ/7
Output Driver Electrical Characteristics
The DDR4 driver supports two RON values. These R ON values are referred to as strong
mode (low RON ˖) and weak mode (high RON ˖). A functional representation of
the output buffer is shown in the figure below.
Figure 234: Output Driver: Definition of Voltages and Currents
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
like
RCV,
...
RONPU
DQ
IOUT
RONPD
VOUT
IPD
VSSQ
The output driver impedance, RON, is determined by the value of the external reference
resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nominal 34.3˖±10% or 48˖±10% with nominal RZQ ˖
The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows:
RONPu when RONPd is off:
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Electrical Characteristics – AC and DC Output Driver Characteristics
RONPU =
VDDQ - VOUT
IOUT
RONPD when RONPU is off:
RONPD =
VOUT
IOUT
Table 121: Strong Mode (34˖
˖) Output Driver Electrical Characteristics
Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
Nom
RON34PD
˖
RON34PU
Max
Unit
Notes
VOL(DC) = 0.5 × VDDQ
0.73
1.00
1.10
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.83
1.00
1.10
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.83
1.00
1.25
RZQ/7
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.90
1.00
1.25
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.90
1.00
1.10
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.80
1.00
1.10
RZQ/7
1, 2, 3
Mismatch between pull-up and pulldown, MMPUPD
VOM(DC) = 0.8 × VDDQ
10
–
23
%
1, 2, 3, 4,
6, 7
Mismatch between DQ to DQ within
byte variation pull-up, MMPUdd
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
5
Mismatch between DQ to DQ within
byte variation pull-down, MMPDdd
VOM(DC) = 0.8 × VDDQ
-
–
10
%
1, 2, 3, 4,
6, 7
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =
VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:
MMPUPD =
RONPU - RONPD
RON,nom
× 100
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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Electrical Characteristics – AC and DC Output Driver Characteristics
MMPUDD =
MMPDDD =
RONPU,max - RONPU,min
RON,nom
RONPD,max - RONPD,min
RON,nom
× 100
× 100
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. The minimum values are derated by 9% when the device operates between –40°C and
0°C (TC).
Table 122: Weak Mode (48˖
˖) Output Driver Electrical Characteristics
Assumes RZQ ˖; Entire operating temperature range after proper ZQ calibration
RON,nom
Resistor
VOUT
Min
Nom
˖
Max
Unit
Notes
VOL(DC) = 0.5 × VDDQ
0.73
1.00
1.10
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.83
1.00
1.10
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.83
1.00
1.25
RZQ/5
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.90
1.00
1.25
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.90
1.00
1.10
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.80
1.00
1.10
RZQ/5
1, 2, 3
Mismatch between pull-up and
pull-down, MMPUPD
VOM(DC) = 0.8 × VDDQ
10
–
23
%
1, 2, 3, 4,
6, 7
Mismatch between DQ to DQ
within byte variation pull-up,
MMPUdd
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4, 5
Mismatch between DQ to DQ
within byte variation pull-down,
MMPDdd
VOM(DC) = 0.8 × VDDQ
–
–
10
%
1, 2, 3, 4,
6, 7
RON48PD
RON48PU
Notes:
1. The tolerance limits are specified after calibration with stable voltage and temperature.
For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity.
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ =
VSS.
3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8
× VDDQ. Other calibration schemes may be used to achieve the linearity specification
shown above; for example, calibration at 0.5 × VDDQ and 1.1 VDDQ.
4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and
DQS_c (characterized).
5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD:
Measure both RONPU and RONPD at 0.8 × VDDQ separately; RON,nom is the nominal RON value:
MMPUPD =
RONPU - RONPD
× 100
RON,nom
6. RON variance range ratio to RON nominal value in a given component, including DQS_t
and DQS_c:
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – AC and DC Output Driver Characteristics
MMPUDD =
MMPDDD =
RONPU,max - RONPU,min
RON,nom
RONPD,max - RONPD,min
RON,nom
× 100
× 100
7. The lower and upper bytes of a x16 are each treated on a per byte basis.
8. The minimum values are derated by 9% when the device operates between –40°C and
0°C (TC).
Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the equations and tables below.
˂T = T - T(@calibration); ˂V = V DDQ - V DDQ(@ calibration); V DD = V DDQ
Table 123: Output Driver Sensitivity Definitions
Symbol
Min
Max
Unit
RONPU@ VOH(DC)
0.6 - dRONdTH × |˂T| - dRONdVH × |˂V|
1.1 _ dRONdTH × |˂T| + dRONdVH × |˂V|
RZQ/6
RON@ VOM(DC)
0.9 - dRONdTM × |˂T| - dRONdVM × |˂V|
1.1 + dRONdTM × |˂T| + dRONdVM × |˂V|
RZQ/6
RONPD@ VOL(DC)
0.6 - dRONdTL × |˂T| - dRONdVL × |˂V|
1.1 + dRONdTL × |˂T| + dRONdVL × |˂V|
RZQ/6
Table 124: Output Driver Voltage and Temperature Sensitivity
Voltage and Temperature Range
Symbol
Min
Max
Unit
dRONdTM
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
dRONdTL
0
1.5
%/°C
dRONdVL
0
0.15
%/mV
dRONdTH
0
1.5
%/°C
dRONdVM
0
0.15
%/mV
Alert Driver
A functional representation of the alert output buffer is shown in the figure below. Output driver impedance, RON, is defined as follows.
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 235: Alert Driver
Alert driver
'5$0
Alert
RONPD
IOUT
IPD
VOUT
VSSQ
RONPD when RONPU is off:
VOUT
RONPD =
IOUT
Table 125: Alert Driver Voltage
RON,nom
Register
N/A
RONPD
Note:
VOUT
Min
Nom
Max
Unit
VOL(DC) = 0.1 × VDDQ
0.3
N/A
1.2
RZQ/7
VOM(DC) = 0.8 × VDDQ
0.4
N/A
1.2
RZQ/7
VOH(DC) = 1.1 × VDDQ
0.4
N/A
1.4
RZQ/7
1. VDDQ voltage is at VDDQ(DC).
Electrical Characteristics – On-Die Termination Characteristics
ODT Levels and I-V Characteristics
On-die termination (ODT) effective resistance settings are defined and can be selected
by any or all of the following options:
• MR1[10:8] (RTT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40
ohms, and 34 ohms.
• MR2[11:9] (RTT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms.
• MR5[8:6] (RTT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40
ohms, and 34 ohms.
ODT is applied to the following inputs:
• x4: DQ, DM_n, DQS_t, and DQS_c inputs.
• x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs.
• x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs.
A functional representation of ODT is shown in the figure below.
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 236: ODT Definition of Voltages and Currents
Chip in termination mode
ODT
To other
circuitry
like RCV,
...
VDDQ
RTT
DQ
IOUT
VOUT
VSSQ
Table 126: ODT DC Characteristics
RTT
VOUT
Min
Nom
Max
Unit
Notes
240 ohm
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ
1, 2, 3
120 ohm
80 ohm
60 ohm
48 ohm
40 ohm
34 ohm
DQ-to-DQ mismatch
within byte
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/2
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/2
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/2
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/3
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/3
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/3
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/4
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/4
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/4
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/5
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/5
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/5
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/6
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/6
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/6
1, 2, 3
VOL(DC) = 0.5 × VDDQ
0.9
1
1.25
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0.9
1
1.1
RZQ/7
1, 2, 3
VOH(DC) = 1.1 × VDDQ
0.8
1
1.1
RZQ/7
1, 2, 3
VOM(DC) = 0.8 × VDDQ
0
–
10
%
1, 2, 4, 5, 6
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. The tolerance limits are specified after calibration to 240 ohm ±1% resistor with stable
voltage and temperature. For the behavior of the tolerance limits if temperature or
voltage changes after calibration, see ODT Temperature and Voltage Sensitivity.
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
2. Micron recommends calibrating pull-up ODT resistors at 0.8 × VDDQ. Other calibration
schemes may be used to achieve the linearity specification shown here.
3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS.
4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t
and DQS_c.
5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t
and DQS_c.
DQ-to-DQ mismatch =
RTT(MAX) - RTT(MIN)
RTT(NOM)
× 100
6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes.
7. For IT, AT, and UT devices, the minimum values are derated by 9% when the device operates between –40°C and 0°C (TC).
ODT Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the following equations and tables.
˂T = T - T(@ calibration); ˂V = V DDQ - V DDQ(@ calibration); V DD = V DDQ
Table 127: ODT Sensitivity Definitions
Parameter
Min
Max
Unit
RTT@
0.9 - dRTTdT × |˂T| - dRTTdV × |˂V|
1.6 + dRTTdTH × |˂T| + dRTTdVH × |˂V|
RZQ/n
Table 128: ODT Voltage and Temperature Sensitivity
Parameter
Min
Max
Unit
dRTTdT
0
1.5
%/°C
dRTTdV
0
0.15
%/mV
ODT Timing Definitions
The reference load for ODT timings is different than the reference load used for timing
measurements.
Figure 237: ODT Timing Reference Load
VDDQ
DQ, DQS_t, DQS_c,
DM, TDQS_t, TDQS_c
CK_t, CK_c
DUT
VSSQ
RTT = 50ȍ
VTT = VSSQ
Timing reference point
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
ODT Timing Definitions
Definitions for tADC, tAONAS, and tAOFAS are provided in the Table 129 (page 304) and
shown in Figure 238 (page 305) and Figure 240 (page 306). Measurement reference settings are provided in the subsequent Table 130 (page 304).
The tADC for the dynamic ODT case and read disable ODT cases are represented by
tADC of Direct ODT Control case.
Table 129: ODT Timing Definitions
Parameter
tADC
Begin Point Definition
End Point Definition
Figure
Rising edge of CK_t, CK_c defined by the end point of
DODTLoff
Extrapolated point at VRTT,nom
Figure 238
(page 305)
Rising edge of CK_t, CK_c defined by the end point of
DODTLon
Extrapolated point at VSSQ
Figure 238
(page 305)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcnw
Extrapolated point at VRTT,nom
Figure 239
(page 305)
Rising edge of CK_t, CK_c defined by the end point of
ODTLcwn4 or ODTLcwn8
Extrapolated point at VSSQ
Figure 239
(page 305)
tAONAS
Rising edge of CK_t, CK_c with ODT being first registered
HIGH
Extrapolated point at VSSQ
Figure 240
(page 306)
tAOFAS
Rising edge of CK_t, CK_c with ODT being first registered
LOW
Extrapolated point at VRTT,nom
Figure 240
(page 306)
Table 130: Reference Settings for ODT Timing Measurements
Measure
Parameter
RTT(Park)
RTT(NOM)
RTT(WR)
VSW1
VSW2
Note
tADC
Disable
RZQ ˖
–
0.20V
0.40V
1, 2, 4
–
RZQ ˖
High-Z
0.20V
0.40V
1, 3, 5
tAONAS
Disable
RZQ ˖
–
0.20V
0.40V
1, 2, 6
tAOFAS
Disable
RZQ ˖
–
0.20V
0.40V
1, 2, 6
Notes:
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16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has
A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for
RTT(WR) setting.
2. ODT state change is controlled by ODT pin.
3. ODT state change is controlled by a WRITE command.
4. Refer to Figure 238 (page 305).
5. Refer to Figure 239 (page 305).
6. Refer to Figure 240 (page 306).
304
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 238: tADC Definition with Direct ODT Control
DODTLoff
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
DODTLoff
DODTLon
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
DODTLon
CK_c
CK_t
tADC
VRTT,nom
tADC
End point: Extrapolated
point at VRTT,nom
VRTT,nom
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
Vsw1
VSSQ
VSSQ
End point: Extrapolated
point at VSSQ
Figure 239: tADC Definition with Dynamic ODT Control
ODTLcnw
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw
ODTLcnw4/8
Begin point: Rising edge
of CK_t, CK_c defined
by the end point of
ODTLcnw4 or ODTLcnw8
CK_c
CK_t
tADC
VRTT,nom
tADC
End point: Extrapolated
point at VRTT,nom
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
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VRTT,nom
Vsw1
VSSQ
305
VSSQ
End point: Extrapolated
point at VSSQ
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16Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics – On-Die Termination Characteristics
Figure 240: tAOFAS and tAONAS Definitions
Rising edge of CK_t, CK_c
with ODT being first
registered LOW
Rising edge of CK_t, CK_c
with ODT being first
registered HIGH
CK_c
CK_t
tAOFAS
VRTT,nom
tAONAS
End point: Extrapolated
point at VRTT_NOM
Vsw2
DQ, DM
DQS_t, DQS_c
TDQS_t, TDQS_c
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VRTT,nom
Vsw1
VSSQ
306
VSSQ
End point: Extrapolated
point at VSSQ
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16Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
DRAM Package Electrical Specifications
Table 131: DRAM Package Electrical Specifications for x4 and x8 Devices
1600/1866/2133/
2400/2666
Parameter
Input/
output
DQS_t,
DQS_c
Input CTRL
pins
Input CMD
ADD pins
CK_t, CK_c
2933
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
ZIO
45
85
48
85
48
85
ohm
1, 2, 4
TdIO
14
42
14
40
14
40
ps
1, 3, 4
Lpkg
LIO
–
3.3
–
3.3
–
3.3
nH
10
Cpkg
CIO
–
0.78
–
0.78
–
0.78
pF
11
Zpkg
Package delay
ZIO DQS
45
85
48
85
48
85
ohm
1, 2
Package delay
TdIO DQS
14
42
14
40
14
40
ps
1, 3
Delta Zpkg
DZIO DQS
–
10
–
10
–
10
ohm
1, 2, 6
Delta delay
DTdIO DQS
–
5
–
5
–
5
ps
1, 3, 6
Zpkg
Lpkg
LIO DQS
–
3.3
–
3.3
–
3.3
nH
10
Cpkg
CIO DQS
–
0.78
–
0.78
–
0.78
pF
11
Zpkg
ZI CTRL
50
90
50
90
50
90
ohm
1, 2, 8
TdI CTRL
14
42
14
40
14
40
ps
1, 3, 8
Package delay
Lpkg
LI CTRL
–
3.4
–
3.4
–
3.4
nH
10
Cpkg
CI CTRL
–
0.7
–
0.7
–
0.7
pF
11
Zpkg
ZI ADD CMD
50
90
50
90
50
90
ohm
1, 2, 7
TdI ADD CMD
14
45
14
40
14
40
ps
1, 3, 7
Package delay
Lpkg
LI ADD CMD
–
3.6
–
3.6
–
3.6
nH
10
Cpkg
CI ADD CMD
–
0.74
–
0.74
–
0.74
pF
11
Zpkg
ZCK
50
90
50
90
50
90
ohm
1, 2
TdCK
14
42
14
42
14
42
ps
1, 3
Delta Zpkg
DZDCK
–
10
–
10
–
10
ohm
1, 2, 5
Delta delay
DTdDCK
–
5
–
5
–
5
ps
1, 3, 5
Lpkg
LI CLK
–
3.4
–
3.4
–
3.4
nH
10
Cpkg
CI CLK
–
0.7
–
0.7
–
0.7
pF
11
Package delay
ZQ Zpkg
ZO ZQ
–
100
–
100
–
100
ohm
1, 2
ZQ delay
TdO ZQ
20
90
20
90
20
90
ps
1, 3
ALERT Zpkg
ZO ALERT
40
100
40
100
40
100
ohm
1, 2
ALERT delay
TdO ALERT
20
55
20
55
20
55
ps
1, 3
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these
values but use the Micron package model. The package parasitic (L and C) are validated
using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ
shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ,
VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
307
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16Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c.
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n,
ACT_n, and PAR.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
Table 132: DRAM Package Electrical Specifications for x16 Devices
1600/1866/2133/
2400/2666
Parameter
Input/
output
LDQS_t/
LDQS_c/
UDQS_t/
UDQS_c
LDQS_t/
LDQS_c,
UDQS_t/
UDQS_c,
Input CTRL
pins
Input CMD
ADD pins
CK_t, CK_c
Zpkg
2933
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
ZIO
45
85
45
85
45
85
ohm
1, 2, 4
TdIO
14
45
14
45
14
45
ps
1, 3, 4
Lpkg
LIO
–
3.4
–
3.4
–
3.4
nH
11
Cpkg
CIO
–
0.82
–
0.82
–
0.82
pF
11
Zpkg
ZIO DQS
45
85
45
85
45
85
ohm
1, 2
Package delay
TdIO DQS
14
45
14
45
14
45
ps
1, 3
Lpkg
LIO DQS
–
3.4
–
3.4
–
3.4
nH
11
Cpkg
CIO DQS
–
0.82
–
0.82
–
0.82
pF
11
Delta Zpkg
DZIO DQS
–
10.5
–
10.5
–
10.5
ohm
1, 2, 6
Delta delay
DTdIO DQS
–
5
–
5
–
5
ps
1, 3, 6
Package delay
Zpkg
ZI CTRL
50
90
50
90
50
90
ohm
1, 2, 8
TdI CTRL
14
42
14
42
14
42
ps
1, 3, 8
Lpkg
LI CTRL
–
3.4
–
3.4
–
3.4
nH
11
Cpkg
CI CTRL
–
0.7
–
0.7
–
0.7
pF
11
Package delay
ZI ADD CMD
50
90
50
90
50
90
ohm
1, 2, 7
TdI ADD CMD
14
52
14
52
14
52
ps
1, 3, 7
Lpkg
LI ADD CMD
–
3.9
–
3.9
–
3.9
nH
11
Cpkg
CI ADD CMD
–
0.86
–
0.86
–
0.86
pF
11
Zpkg
Package delay
ZCK
50
90
50
90
50
90
ohm
1, 2
TdCK
14
42
14
42
14
42
ps
1, 3
Delta Zpkg
DZDCK
–
10.5
–
10.5
–
10.5
ohm
1, 2, 5
Delta delay
DTdDCK
–
5
–
5
–
5
ps
1, 3, 5
Zpkg
Package delay
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16Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
Table 132: DRAM Package Electrical Specifications for x16 Devices (Continued)
1600/1866/2133/
2400/2666
Parameter
Input CLK
2933
3200
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Lpkg
LI CLK
–
3.4
–
3.4
–
3.4
nH
11
Cpkg
CI CLK
–
0.7
–
0.7
–
0.7
pF
11
ZQ Zpkg
ZO ZQ
–
100
–
100
–
100
ohm
1, 2
ZQ delay
TdO ZQ
20
90
20
90
20
90
ps
1, 3
ALERT Zpkg
ZO ALERT
40
100
40
100
40
100
ohm
1, 2
ALERT delay
TdO ALERT
20
55
20
55
20
55
ps
1, 3
Notes:
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1. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these
values but use the Micron package model. The package parasitic (L and C) are validated
using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ
shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ,
VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side.
2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a
given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg).
3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin
where: Tdpkg (total per pin) = SQRT (Lpkg × Cpkg).
4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c.
5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c
for delay (Td).
6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO
(DQS_t), TdIO (DQS_c) for delay (Td).
7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n,
ACT_n, and PAR.
8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE.
9. Package implementations will meet specification if the Zpkg and package delay fall
within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown.
10. It is assumed that Lpkg can be approximated as Lpkg = ZO × Td.
11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO.
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16Gb: x4, x8, x16 DDR4 SDRAM
DRAM Package Electrical Specifications
Table 133: Pad Input/Output Capacitance
DDR4-1600,
1866, 2133
DDR4-2400,
2666
DDR4-2933
DDR4-3200
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Input/output capacitance:
DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
CIO
0.55
1.4
0.55
1.15
0.55
1.00
0.55
1.00
pF
1, 2, 3
Input capacitance: CK_t and
CK_c
CCK
0.2
0.8
0.2
0.7
0.2
0.7
0.15
0.7
pF
2, 3
Input capacitance delta: CK_t
and CK_c
CDCK
-
0.05
-
0.05
-
0.05
-
0.05
pF
2, 3, 6
Input/output capacitance delta: DQS_t and DQS_c
CDDQS
-
0.05
-
0.05
-
0.05
-
0.05
pF
2, 3, 5
Input capacitance: CTRL,
ADD, CMD input-only pins
CI
0.2
0.8
0.2
0.7
0.2
0.6
0.15
0.55
pF
2, 3, 4
Input capacitance delta: All
CTRL input-only pins
CDI_CTRL
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
2, 3, 8,
9
Input capacitance delta: All
ADD/CMD input-only pins
CDI_ADD_CM
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
1, 2, 10,
11
CDIO
–0.1
0.1
–0.1
0.1
–0.1
0.1
–0.1
0.1
pF
1, 2, 3,
4
CALERT
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
pF
2, 3
Input/output capacitance: ZQ
pin
CZQ
–
2.3
–
2.3
–
2.3
–
2.3
pF
2, 3, 12
Input/output capacitance:
TEN pin
CTEN
0.2
2.3
0.2
2.3
0.2
2.3
0.15
2.3
pF
2, 3, 13
Parameter
Input/output capacitance delta: DQ, DM, DQS_t, DQS_c,
TDQS_t, TDQS_c
Input/output capacitance:
ALERT pin
Notes:
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D
1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading
matches DQ and DQS.
2. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these
values but use the Micron package model. The capacitance, if and when, is measured according to the JEP147 specification, “Procedure for Measuring Input Capacitance Using
a Vector Network Analyzer (VNA),” with VDD, VDDQ, VSS, and VSSQ applied and all other
pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD =
VDDQ = 1.2V, VBIAS = VDD/2 and on-die termination off. Measured data is rounded using
industry standard half-rounded up methodology to the nearest hundredth of the MSB.
3. This parameter applies to monolithic die, obtained by de-embedding the package L and
C parasitics.
4. CDIO = CIO(DQ, DM) - 0.5 × (CIO(DQS_t) + CIO(DQS_c)).
5. Absolute value of CIO (DQS_t), CIO (DQS_c)
6. Absolute value of CCK_t, CCK_c
7. CI applies to ODT, CS_n, CKE, A[17:0], BA[1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and
WE_n.
8. CDI_CTRL applies to ODT, CS_n, and CKE.
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16Gb: x4, x8, x16 DDR4 SDRAM
Thermal Characteristics
9.
10.
11.
12.
13.
CDI_CTRL = CI(CTRL) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
CDI_ADD_CMD applies to A[17:0], BA1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n.
CDI_ADD_CMD = CI(ADD_CMD) - 0.5 × (CI(CLK_t) + CI(CLK_c)).
Maximum external load capacitance on ZQ pin: 5pF.
Only applicable if TEN pin does not have an internal pull-up.
Thermal Characteristics
Table 134: Thermal Characteristics
Parameter/Condition
Value
Units
Symbol
Notes
Operating case temperature:
Commercial
0 to +85
°C
TC
1, 2, 3
0 to +95
°C
TC
1, 2, 3, 4
Operating case temperature:
Industrial
–40 to +85
°C
TC
1, 2, 3
–40 to +95
°C
TC
1, 2, 3, 4
Operating case temperature:
Automotive
–40 to +85
°C
TC
1, 2, 3
–40 to +105
°C
TC
1, 2, 3, 4
5
78-ball “VA”
REV B
96-ball “RC”
78-ball “JC”
REV E
96-ball
“KD”
Junction-to-case (TOP)
3.6
°C/W
ˆJC
Junction-to-board
13.6
°C/W
ˆJB
Junction-to-case (TOP)
3.5
°C/W
ˆJC
Junction-to-board
12.7
°C/W
ˆJB
Junction-to-case (TOP)
4.2
°C/W
ˆJC
Junction-to-board
13
°C/W
ˆJB
Junction-to-case (TOP)
4.1
°C/W
ˆJC
Junction-to-board
12.3
°C/W
ˆJB
Notes:
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5
5
5
1. MAX operating case temperature. TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2x refresh, which is a 3.9μs
interval refresh rate.
5. The thermal resistance data is based off of a typical number.
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
Figure 241: Thermal Measurement Point
TC test point
(L/2)
L
(W/2)
W
Current Specifications – Measurement Conditions
IDD, IPP, and IDDQ Measurement Conditions
IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined
in this section.
• IDD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R,
IDD6N, IDD6E, IDD6R, IDD6A, IDD7, and IDD8) are measured as time-averaged currents
with all V DD balls of the device under test grouped together.
• IPP currents are IPP3N for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8),
IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W), IPP5R for the distributed refresh case
(IDD5R), IPP6x for self refresh cases (IDD6N, IDD6E, IDD6R, IDD6A) and IPP7 for the operating
bank interleave read case (IDD7). These have the same definitions as the I DD currents
referenced but are measured on the V PP supply.
• IDDQ currents are measured as time-averaged currents with V DDQ balls of the device
under test grouped together. Micron does not specify IDDQ currents.
• IPP and IDDQ currents are not included in IDD currents, IDD and IDDQ currents are not
included in IPP currents, and IDD and IPP currents are not included in IDDQ currents.
Note: IDDQ values cannot be directly used to calculate the I/O power of the device. They
can be used to support correlation of simulated I/O power to actual I/O power. In
DRAM module application, IDDQ cannot be measured separately because V DD and V DDQ
are using a merged-power layer in the module PCB.
The following definitions apply for IDD, IPP and IDDQ measurements.
•
•
•
•
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“0” and “LOW” are defined as V IN ืVIL(AC)max
“1” and “HIGH” are defined as V IN ุVIH(AC)min
“Midlevel” is defined as inputs V REF = V DD/2
Timings used for IDD, IPP and IDDQ measurement-loop patterns are provided in the
Current Test Definition and Patterns section.
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
• Basic IDD, IPP, and IDDQ measurement conditions are described in the Current Test
Definition and Patterns section.
• Detailed IDD, IPP, and IDDQ measurement-loop patterns are described in the Current
Test Definition and Patterns section.
• Current measurements are done after properly initializing the device. This includes,
but is not limited to, setting:
RON = RZQ/7 (34 ohm in MR1);
Qoff = 0B (output buffer enabled in MR1);
RTT(NOM) = RZQ/6 (40 ohm in MR1);
RTT(WR) = RZQ/2 (120 ohm in MR2);
RTT(Park) = disabled;
TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in
MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disabled in MR5
• Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA
changes when directed.
• Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply invert of BG/BA changes when directed above.
Note: The measurement-loop patterns must be executed at least once before actual current measurements can be taken.
Figure 242: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx
IDD
VDD
RESET_n
CK_t/CK_c
IPP
IDDQ
VPP
VDDQ
DDR4
SDRAM
CKE
CS_n
C
ACT_n, RAS_n, CAS_n, WE_n
A, BG, BA
ODT
ZQ
V
DQ
DM_n
VSSQ
SS
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DQS_t, DQS_c
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
Figure 243: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power
Applic ation-s pe c ific
memory c ha nne l
env ironmen t
C hanne l I/O
pow er simulation
I DD Q
tes t loa d
I DD Q
simulation
IDD Q
meas ure ment
C or relation
C orre c tion
C hanne l I/O
pow er n umber
Note:
1. Supported by IDDQ measurement.
IDD Definitions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions
Symbol
Description
IDD0
Operating One Bank Active-Precharge Current (AL = 0)
CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between
ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the
next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2,
2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT
signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table
IPP0
Operating One Bank Active-Precharge IPP Current (AL = 0)
Same conditions as IDD0 above
IDD1
Operating One Bank Active-Read-Precharge Current (AL = 0)
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;1, 5 AL: 0; CS_n: HIGH
between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially
toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with
one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode
registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table
IDD2N
Precharge Standby Current (AL = 0)
CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and
RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol
Description
IDD2NT
Precharge Standby ODT Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop
Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled
in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see the IDD2NT Measurement-Loop Pattern table
IDD2P
Precharge Power-Down Current
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD2Q
Precharge Quiet Standby Current
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD3N
Active Standby Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and
RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N MeasurementLoop Pattern table
IPP3N
Active Standby IPP3N Current (AL = 0)
Same conditions as IDD3N above
IDD3P
Active Power-Down Current (AL = 0)
CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all
banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
IDD4R
Operating Burst Read Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;15 AL: 0; CS_n: HIGH between RD; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measurement-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the
next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks
open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table);
Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Measurement-Loop Pattern table
IDD4W
Operating Burst Write Current (AL = 0)
CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measurement-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the
next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks
open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table);
Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see
the IDD4W Measurement-Loop Pattern table
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
Table 135: Basic IDD, IPP, and IDDQ Measurement Conditions (Continued)
Symbol
Description
IDD5R
Distributed Refresh Current (1X REF)
CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF;
Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see
the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal:
stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table
IPP5R
Distributed Refresh Current (1X REF)
Same conditions as IDD5R above
IDD6N
Self Refresh Current: Normal Temperature Range
TC: 0–85°C; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group
address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer
and RTT: enabled in mode registers;2 ODT signal: midlevel
IDD6E
Self Refresh Current: Extended Temperature Range 4
TC: 0–95°C; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group
bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
IPP6x
Self Refresh IPP Current
Same conditions as IDD6E above
IDD6R
Self Refresh Current: Reduced Temperature Range
TC: 0–45°C; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank
group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF
REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel
IDD7
Operating Bank Interleave Read Current
CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;15 AL: CL 1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially
toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data
between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1;
Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7
Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0;
Pattern details: see the IDD7 Measurement-Loop Pattern table
IPP7
Operating Bank Interleave Read IPP Current
Same conditions as IDD7 above
IDD8
Maximum Power Down Current
Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n:
stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n:
stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0
Notes:
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1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00.
2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON =
RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001
(RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled).
3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature.
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended
temperature range.
5. READ burst type: Nibble sequential, set MR0[3] 0.
6. In the dual-rank DDP case, note the following IDD measurement considerations:
• For all IDD measurements except IDD6, the unselected rank should be in an IDD2P
condition.
• For all IPP measurements except IPP6, the unselected rank should be in an IDD3N condition.
• For all IDD6/IPP6 measurements, both ranks should be in the same IDD6 condition.
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
317
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Current Specifications – Patterns and Test Conditions
Current Test Definitions and Patterns
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_t, CK_c
Table 136: IDD0 and IPP0 Measurement-Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3, 4
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
PRE
0
1
0
...
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
Static High
Toggling
nRAS
1
0
0
0
0
0
0
0
0
0
0
...
Repeat pattern 1...4 until nRC - 1; truncate if necessary
1
1 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
2 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
5 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
6 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
7 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
8 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
9 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
10 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
11 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
12 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
13 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
14 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
15 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1.
2.
3.
4.
–
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
318
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 137: IDD1 Measurement – Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1, 2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3, 4
D_n, D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
RD
0
...
Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary
nRCD - AL
...
PRE
...
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
D5 = 00, D7 = FF
1 × nRC + 0
ACT
0
0
0
1
1
0
1
1
0
0
0
0
0
0
–
1 × nRC + 1,
2
D, D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
...
Repeat pattern nRC + 1...4 until 1 × nRC + nRAS - 1; truncate if necessary
1 × nRC
+nRCD - AL
Static High
0
Repeat pattern 1...4 until nRC - 1; truncate if necessary
1 × nRC + 3, D_n, D_n
4
Toggling
1
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
nRAS
1
1
RD
...
0
1
1
0
1
0
1
1
0
0
0
0
0
0
0
0
Repeat pattern 1...4 until nRAS - 1; truncate if necessary
1 × nRC +
nRAS
...
PRE
0
1
0
1
0
0
1
1
0
0
0
0
Repeat pattern nRC + 1...4 until 2 × nRC - 1; truncate if necessary
2
2 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
5 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
6 × nRC
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
7 × nRC
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
9 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
10 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
11 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
12 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
13 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
14 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
15 × nRC
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
16 × nRC
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
D0 = FF, D1 =
00,
D2 = 00, D3 =
FF,
D4 = 00, D5 =
FF,
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
319
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command.
4. For x4 and x8 only.
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
Static High
Toggling
CK_c, CK_t,
Table 138: IDD2N, IDD3N, and IPP3P Measurement – Loop Pattern1
Data3
0
0
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
1
4–7
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
320
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
Static High
Toggling
CK_c, CK_t,
Table 139: IDD2NT Measurement – Loop Pattern1
Data3
0
0
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
1
4–7
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead
2
8–11
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1.
2.
3.
4.
DQS_t, DQS_c are VSSQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VSSQ.
For x4 and x8 only.
321
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 140: IDD4R Measurement – Loop Pattern1
0
0
RD
0
1
1
0
1
0
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
2, 3
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
4
RD
0
1
1
0
1
0
1
1
0
0
0
7
F
0
5
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
6, 7
D_n,
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
Static High
Toggling
1
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Data3
D0 = 00, D1 =
FF,
D2 = FF, D3 =
00,
D4 = FF, D5 =
00,
D5 = 00, D7 =
FF
D0 = FF, D1 = 00
D2 = 00, D3 =
FF
D4 = 00, D5 =
FF
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by a READ command. Outside burst operation,
DQ signals are VDDQ.
4. For x4 and x8 only.
322
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Cycle
Number
Command
CS_n
ACT_n
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,1
1]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
0
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1
D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
2, 3
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
4
WR
0
1
1
0
0
1
1
1
0
0
0
7
F
0
Static High
Toggling
1
RAS_n/A1
6
CAS_n/A1
5
Sub-Loop
CKE
CK_c,
CK_t,
Table 141: IDD4W Measurement – Loop Pattern1
5
D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
6, 7
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
2
8–11
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
12–15
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
16–19
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
20–23
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
24–27
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
28–31
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
32–35
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
36–39
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
40–43
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
44–47
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
48–51
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
52–55
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
56–59
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
60–63
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Data3
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D5 = 00, D7 = FF
D0 = FF, D1 = 00
D2 = 00, D3 = FF
D4 = 00, D5 = FF
D5 = FF, D7 = 00
1. DQS_t, DQS_c are VDDQ when not toggling.
2. BG1 is a "Don't Care" for x16 devices.
3. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ.
4. For x4 and x8 only.
323
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]3
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_c, CK_t,
Table 142: IDD4Wc Measurement – Loop Pattern1
0
0
WR
0
1
1
0
0
1
0
0
0
0
0
0
0
0
1, 2
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
3, 4
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
Static High
Toggling
1
5
WR
0
1
1
0
0
1
1
1
0
0
0
7
F
0
6, 7
D, D
1
0
0
0
0
1
0
0
0
0
0
0
0
0
8, 9
D_n,
D_n
1
1
1
1
0
1
3
3
0
0
0
7
F
0
2
10–14
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
15–19
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
20–24
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
5
25–29
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
6
30–34
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
7
35–39
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
8
40–44
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4
9
45–49
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4
10
50–54
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4
11
55–59
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4
12
60–64
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4
13
65–69
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4
14
70–74
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4
15
75–79
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Data4
D0 = 00, D1 = FF,
D2 = FF, D3 = 00,
D4 = FF, D5 = 00,
D8 = CRC
D0 = FF, D1 = 00,
D2 = 00, D3 = FF,
D4 = 00, D5 = FF,
D5 = FF, D7 = 00
D8 = CRC
1.
2.
3.
4.
Pattern provided for reference only.
DQS_t, DQS_c are VDDQ when not toggling.
BG1 is a "Don't Care" for x16 devices.
Burst sequence driven on each DQ signal by WRITE command. Outside burst operation,
DQ signals are VDDQ.
5. For x4 and x8 only.
324
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
Data3
0
0
REF
0
1
0
0
1
0
0
0
0
0
0
0
0
0
–
1
1
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
2
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
4
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
Static High
Toggling
CK_c, CK_t,
Table 143: IDD5R Measurement – Loop Pattern1
2
5–8
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead
9–12
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead
13–16
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead
17–20
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead
21–24
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead
25–28
Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead
29–32
Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead
33–36
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead4
37–40
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead4
41–44
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead4
45–48
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead4
49–52
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead4
53–56
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead4
57–60
Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead4
61–64
Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead4
65...nREFI 1
Repeat sub-loop 1; truncate if necessary
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1.
2.
3.
4.
DQS_t, DQS_c are VDDQ.
BG1 is a "Don't Care" for x16 devices.
DQ signals are VDDQ.
For x4 and x8 only.
325
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
Sub-Loop
Cycle
Number
Command
CS_n
ACT_n
RAS_n/A16
CAS_n/A15
WE_n/A14
ODT
BG[1:0]2
BA[1:0]
A12/BC_n
A[17,13,11]]
A[10]/AP
A[9:7]
A[6:3]
A[2:0]
CKE
CK_t, CK_c
Table 144: IDD7 Measurement – Loop Pattern1
Data3
0
0
ACT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
1
RDA
0
1
1
0
1
0
0
0
0
0
1
0
0
0
2
D
1
0
0
0
0
0
0
0
0
0
0
0
0
0
–
3
D_n
1
1
1
1
1
0
3
3
0
0
0
7
F
0
–
...
Static High
Toggling
1
Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary
nRRD
ACT
0
0
0
0
0
0
1
1
0
0
0
0
0
0
nRRD+1
RDA
0
1
1
0
1
0
1
1
0
0
1
0
0
0
–
...
Repeat pattern 2...3 until 2 × nRRD - 1, if nRRD > 4. Truncate if necessary
2
2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead
3
3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead
4
4 × nRRD
Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 × nRRD. Truncate if necessary
5
nFAW
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead
6
nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead
7
nFAW + 2 × nRRD
Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead
8
nFAW + 3 × nRRD
Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead
9
nFAW + 4 × nRRD
Repeat sub-loop 4
10
2 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead
11
2 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead
12
2 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead
13
2 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead
14
2 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
15
3 × nFAW
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead
16
3 × nFAW + nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead
17
3 × nFAW + 2 ×
nRRD
Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead
18
3 × nFAW + 3 ×
nRRD
Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead
19
3 × nFAW + 4 ×
nRRD
Repeat sub-loop 4
20
4 × nFAW
Repeat pattern 2...3 until nRC - 1, if nRC > 4 × nFAW. Truncate if necessary
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. DQS_t, DQS_c are VDDQ.
2. BG1 is a "Don't Care" for x16 devices.
3. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command.
326
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Patterns and Test Conditions
4. For x4 and x8 only.
IDD Specifications
20-20-20
20-20-20
22-22-22
20-20-20
24-24-24
12
12
13
14
14
15
16
16
17
18
18
19
20
20
21
22
20
22
24
CK
CWL
9
11
11
10
12
12
11
14
14
16
16
16
18
18
18
14
18
18
16
20
20
CK
nRCD
10
11
12
12
13
14
14
15
16
16
17
18
18
19
20
19
20
21
20
22
24
CK
nRC
38
39
40
44
45
46
50
51
52
55
56
57
61
62
63
66
67
68
72
74
76
CK
nRP
10
11
12
12
13
14
14
15
16
16
17
18
18
19
20
19
20
21
20
22
24
CK
nRAS
0.937
0.833
0.75
0.682
22-22-22
18-18-18
11
1.071
21-21-21
18-18-18
10
1.25
19-19-19
16-16-16
CL
tCK
17-17-17
16-16-16
Uni
t
Symbol
15-15-15
DDR4-3200
14-14-14
DDR4-2933
14-14-14
DDR4-2666
13-13-13
DDR4-2400
12-12-12
DDR4-2133
12-12-12
DDR4-1866
11-11-11
DDR4-1600
10-10-10
Table 145: Timings used for IDD, IPP, and IDDQ Measurement – Loop Patterns
0.625
ns
28
32
36
39
43
47
52
CK
x41
16
16
16
16
16
16
16
CK
x8
20
22
23
26
28
31
34
CK
x1
6
28
28
32
36
40
44
48
CK
nRRD x4
_S
x8
4
4
4
4
4
4
4
CK
4
4
4
4
4
4
4
CK
x1
6
5
6
6
7
8
8
9
CK
nRRD x4
_L
x8
5
5
6
6
7
8
8
CK
5
5
6
6
7
8
8
CK
x1
6
6
6
7
8
9
10
11
CK
nCCD_S
4
4
4
4
4
4
4
CK
nCCD_L
5
5
6
6
7
8
8
CK
nWTR_S
2
3
3
3
4
4
4
CK
nWTR_L
6
7
8
9
10
11
12
CK
nFA
W
nREFI
6,240
7,283
8,325
9,364
10,400
11,437
12,480
CK
nRFC 2Gb
128
150
171
193
214
235
256
CK
nRFC 4Gb
208
243
278
313
347
382
416
CK
nRFC 8Gb
280
327
374
421
467
514
560
CK
nRFC
16Gb
280
327
374
421
467
514
560
CK
Note:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. 1KB based x4 use same numbers of clocks for nFAW as the x8.
327
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
Current Specifications – Limits
Table 146: IDD and IPP Current Limits; Die Rev. B (-40° ื TC ื 85°C)
Symbol
Width
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Unit
IDD0: One bank ACTIVATE-toPRECHARGE current
x4
56
57
58
59
60
mA
x8
59
60
61
62
63
mA
x16
74
75
76
77
78
mA
IPP0: One bank ACTIVATE-toPRECHARGE IPP current
x4, x8
4
4
4
4
4
mA
x16
5
5
5
5
5
mA
IDD1: One bank ACTIVATE-toREAD-to- PRECHARGE current
x4
66
67
68
69
70
mA
x8
70
71
72
73
74
mA
x16
95
96
97
98
99
mA
IDD2N: Precharge standby
current
ALL
48
49
50
51
52
mA
IDD2NT: Precharge standby
ODT current
x4, x8
52
53
54
55
56
mA
x16
61
62
63
64
65
mA
IDD2P: Precharge powerdown current
ALL
43
43
43
43
43
mA
IDD2Q: Precharge quiet
standby current
ALL
47
47
47
47
47
mA
IDD3N: Active standby current
IPP3N: Active standby IPP current
IDD3P: Active power-down
current
IDD4R: Burst read current
IDD4W: Burst write current
x4
74
75
76
77
78
mA
x8
76
77
78
79
80
mA
x16
77
78
79
80
81
mA
ALL
3
3
3
3
3
mA
x4
65
66
67
68
69
mA
x8
66
67
68
69
69
mA
x16
68
69
70
71
72
mA
x4
138
147
155
164
172
mA
x8
162
172
182
192
202
mA
x16
242
262
284
305
326
mA
x4
135
142
149
157
164
mA
x8
150
158
166
175
183
mA
x16
209
223
240
257
274
mA
IDD5R: Distributed refresh
current (1X REF)
ALL
81
81
81
81
81
mA
IPP5R: Distributed refresh IPP
current (1X REF)
ALL
5
5
5
5
5
mA
IDD6N: Self refresh current;
-40–85°C 1
ALL
74
74
74
74
74
mA
IDD6E: Self refresh current;
-40–95°C 2,4
ALL
129
129
129
129
129
mA
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
328
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
Table 146: IDD and IPP Current Limits; Die Rev. B (-40° ื TC ื 85°C) (Continued)
Width
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Unit
IDD6R: Self refresh current;
-40–45C 3,4
Symbol
ALL
26
26
26
26
26
mA
IDD6A: Auto self refresh current (25°C)4
ALL
15
15
15
15
15
mA
IDD6A: Auto self refresh current (45°C)4
ALL
26
26
26
26
26
mA
IDD6A: Auto self refresh current (75°C)4
ALL
73
73
73
73
73
mA
IDD6A: Auto self refresh current (95°C)4
ALL
129
129
129
129
129
mA
IPP6x: Auto self refresh IPP
current; -40–95°C27
ALL
9
9
9
9
9
mA
IDD7: Bank interleave read
current
x4
187
196
208
220
234
mA
x8
183
185
190
193
196
mA
x16
255
260
260
267
268
mA
IPP7: Bank interleave read IPP
current
x4
11
11
11
11
11
mA
x8
10
10
10
10
10
mA
x16
11
11
11
11
11
mA
IDD8: Maximum power-down
current
ALL
40
40
40
40
40
mA
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (-40–85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (-40–95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (-40–45°C).
4. IDD6R, IDD6A, and IDD6E values are verified by design and characterization, and may not be
subject to production test.
5. When additive latency is enabled for IDD0, current changes by approximately +1%.
6. When additive latency is enabled for IDD1, current changes by approximately +8%.
7. When additive latency is enabled for IDD2N, current changes by approximately +1%.
8. When DLL is disabled for IDD2N, current changes by approximately –6%.
9. When CAL is enabled for IDD2N, current changes by approximately –20%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +13%.
12. When additive latency is enabled for IDD3N, current changes by approximately +1%.
13. When additive latency is enabled for IDD4R, current changes by approximately +4%(x4/
x8), +3%(X16).
14. When read DBI is enabled for IDD4R, current changes by approximately -12%(x4/x8),
-20%(x16).
15. When additive latency is enabled for IDD4W, current changes by approximately +4%(x4/
x8), +3%(x16).
16. When write DBI is enabled for IDD4W, current changes by approximately 0%.
17. When write CRC is enabled for IDD4W, current changes by approximately -5%.
329
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
18.
19.
20.
21.
22.
23.
24.
When CA parity is enabled for IDD4W, current changes by approximately +12%.
When 2X REF is enabled for IDD5R, current changes by approximately 0%.
When 4X REF is enabled for IDD5R, current changes by approximately 0%.
When 2X REF is enabled for IPP5R, current changes by approximately 0%.
When 4X REF is enabled for IPP5R, current changes by approximately 0%.
IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests.
25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133.
26. The IDD values must be derated (increased) when operated between 85°C < TC ื 95°C:
When TC > 85°C: IDD0 and IDD1 must be derated by 10%; IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N
and IDD3P must be derated by 15%; IDD4R, IDD4W and IDD7 must be derated by 4%; IDD5R
must be derated by 56%; IPP5R must be derated by 81%; IPP0, IPP3N and IPP7 must be derated by 3%. These values are verified by design and characterization, and may not be
subject to production test.
27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.
Table 147: IDD and IPP Current Limits; Die Rev. E (-40° ื TC ื 85°C)
Symbol
Width
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Unit
IDD0: One bank ACTIVATE-toPRECHARGE current
x4
51
52
53
54
55
mA
x8
56
57
58
59
60
mA
x16
66
67
68
69
70
mA
IPP0: One bank ACTIVATE-toPRECHARGE IPP current
x4, x8
3
3
3
3
3
mA
x16
4
4
4
4
4
mA
IDD1: One bank ACTIVATE-toREAD-to- PRECHARGE current
x4
62
63
64
65
66
mA
x8
67
68
69
70
71
mA
x16
80
81
82
83
84
mA
IDD2N: Precharge standby
current
ALL
41
42
43
44
45
mA
IDD2NT: Precharge standby
ODT current
x4, x8
47
48
49
50
51
mA
x16
54
55
56
57
58
mA
IDD2P: Precharge powerdown current
ALL
38
38
38
38
38
mA
IDD2Q: Precharge quiet
standby current
ALL
42
42
42
42
42
mA
x4
56
57
58
59
60
mA
IDD3N: Active standby current
IPP3N: Active standby IPP current
IDD3P: Active power-down
current
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x8
57
58
59
60
61
mA
x16
58
59
60
61
62
mA
ALL
2
2
2
2
2
mA
x4
44
45
46
47
48
mA
x8
46
47
48
49
50
mA
x16
47
48
49
50
51
mA
330
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
Table 147: IDD and IPP Current Limits; Die Rev. E (-40° ื TC ื 85°C) (Continued)
Symbol
IDD4R: Burst read current
IDD4W: Burst write current
Width
DDR4-2133
DDR4-2400
DDR4-2666
DDR4-2933
DDR4-3200
Unit
x4
101
106
112
119
127
mA
x8
131
138
146
154
162
mA
x16
231
243
263
282
299
mA
x4
89
93
97
101
105
mA
x8
107
112
117
123
128
mA
x16
189
200
213
226
236
mA
IDD5R: Distributed refresh
current (1X REF)
ALL
68
68
68
68
68
mA
IPP5R: Distributed refresh IPP
current (1X REF)
ALL
4
4
4
4
4
mA
IDD6N: Self refresh current;
-40–85°C 1
ALL
53
53
53
53
53
mA
IDD6E: Self refresh current;
-40–95°C 2,4
ALL
113
113
113
113
113
mA
IDD6R: Self refresh current;
-40–45C 3,4
ALL
20
20
20
20
20
mA
IDD6A: Auto self refresh current (25°C)4
ALL
11
11
11
11
11
mA
IDD6A: Auto self refresh current (45°C)4
ALL
20
20
20
20
20
mA
IDD6A: Auto self refresh current (75°C)4
ALL
51
51
51
51
51
mA
IDD6A: Auto self refresh current (95°C)4
ALL
113
113
113
113
113
mA
IPP6x: Auto self refresh IPP
current; -40–95°C27
ALL
6
6
6
6
6
mA
IDD7: Bank interleave read
current
x4
189
191
193
195
197
mA
x8
177
179
181
183
185
mA
x16
234
240
236
242
245
mA
x4
9
9
9
9
9
mA
x8
8
8
8
8
8
mA
x16
9
9
9
9
9
mA
ALL
36
36
36
36
36
mA
IPP7: Bank interleave read IPP
current
IDD8: Maximum power-down
current
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature
range of operation (-40–85°C).
2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation (-40–95°C).
3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature
range of operation (-40–45°C).
4. IDD6R, IDD6A, and IDD6E values are verified by design and characterization, and may not be
subject to production test.
331
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16Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Limits
5. When additive latency is enabled for IDD0, current changes by approximately +1%.
6. When additive latency is enabled for IDD1, current changes by approximately +3%(x4/x8),
+ 2%(x16).
7. When additive latency is enabled for IDD2N, current changes by approximately +1%.
8. When DLL is disabled for IDD2N, current changes by approximately -4%.
9. When CAL is enabled for IDD2N, current changes by approximately -18%.
10. When gear-down is enabled for IDD2N, current changes by approximately 0%.
11. When CA parity is enabled for IDD2N, current changes by approximately +8%.
12. When additive latency is enabled for IDD3N, current changes by approximately +1%.
13. When additive latency is enabled for IDD4R, current changes by approximately +4%(x4/
x8), +1%(x16).
14. When read DBI is enabled for IDD4R, current changes by approximately -9%.
15. When additive latency is enabled for IDD4W, current changes by approximately +5%(x4/
x8), +2%(x16).
16. When write DBI is enabled for IDD4W, current changes by approximately +1%.
17. When write CRC is enabled for IDD4W, current changes by approximately -5%(x4/x8), -8%
(x16).
18. When CA parity is enabled for IDD4W, current changes by approximately +13%(x4/x8),
+6%(x16).
19. When 2X REF is enabled for IDD5R, current changes by approximately 0%.
20. When 4X REF is enabled for IDD5R, current changes by approximately 0%.
21. When 2X REF is enabled for IPP5R, current changes by approximately 0%.
22. When 4X REF is enabled for IPP5R, current changes by approximately 0%.
23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions.
24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests.
25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133.
26. The IDD values must be derated (increased) when operated between 85°C < TC ื 95°C:
IDD0 and IDD1must be derated by 10%; IDD2N, IDD2NT, IDD2Q, and IDD3N must be derated by
18%; IDD2P and IDD3P must be derated by 23%; IDD4R and IDD4W must be derated by 6%;
IDD5R must be derated by 58%; IDD7, IPP7 and IPP0 must be derated by 3%; IDD8 must be
derated by 28%; IPP5R must be derated by 97%
27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions.
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2018 Micron Technology, Inc. All rights reserved.
16Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Speed Bin Tables
DDR4 DRAM timing is primarily covered by two types of tables: the Speed Bin tables in
this section and the tables found in the Electrical Characteristics and AC Timing Parameters section. The timing parameter tables define the applicable timing specifications
based on the speed rating. The Speed Bin tables on the following pages list the tAA,
tRCD, tRP, tRAS, and tRC limits of a given speed mark and are applicable to the CL settings in the lower half of the table provided they are applied in the correct clock range,
which is noted.
Backward Compatibility
Although the speed bin tables list the slower data rates, tAA, CL, and CWL, it is difficult
to determine whether a faster speed bin supports all of the tAA, CL, and CWL combinations across all the data rates of a slower speed bin. To assist in this process, please refer
to the Backward Compatibility table.
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Note 1 applies to the entire table.
Component
Speed Bin
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Table 148: Backward Compatibility
Speed Bin Supported
-125
-125
yes
-125E
yes2
-125E
-107
-107E
-093
-093E -083D
-083
-083E -075D
-075
-075E -068D
-068
-068E
-062
-062E -062Y
yes
-107
yes
-107E
yes2
yes
-093
yes
yes
-093E
yes2
yes2
-083D
yes
yes
yes
yes2
yes
yes
yes
yes
yes2
yes
yes
yes
yes
334
yes
-083E
yes2
-075D
yes
-075
yes
-075E
yes
-068D
yes
yes
yes
yes
-068
yes
yes
yes
yes
yes
yes
yes
yes
yes
-068E
yes
yes
yes
yes
yes
yes
yes
yes
yes
-062
yes
yes
yes
yes
-062E
yes
yes
yes
yes
yes
-062Y
yes
yes
yes
yes
yes2
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes2
yes
yes
yes
yes
yes2
yes
yes
yes
yes
yes
yes2
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
16Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2018 Micron Technology, Inc. All rights reserved.
-083
16Gb: x4, x8, x16 DDR4 SDRAM
Speed Bin Tables
Notes:
CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
1. The backward compatibility table is not meant to guarantee that any new device will be
a drop in replacement for an existing part number. Customers should review the operating conditions for any device to determine its suitability for use in their design.
2. This condition exceeds the JEDEC requirement in order to allow additional flexibility for
components. However, JEDEC SPD compliance may force modules to only support the JEDEC-defined value. Refer to the SPD documentation for further clarification.
335
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CCM005-1406124318-10453
16gb_ddr4_dram.pdf - Rev. G 08/2020 EN
Table 149: DDR4-1600 Speed Bins and Operating Conditions
Notes 1–3 apply to the entire table
DDR4-1600 Speed Bin
-125E
CL-nRCD-nRP
-125
11-11-11
Parameter
Symbol
Internal READ command to first data
Internal READ command to first data with read DBI enabled
ACTIVATE-to-internal READ or WRITE delay time
PRECHARGE command period
12-12-12
Min
Max
Min
tAA
Max
Unit
13.75
(13.50)4
19.006
15.00
19.006
ns
tAA_DBI
tAA
tAA
tAA
tAA
ns
(MIN) +
2nCK
(MAX) +
2nCK
(MIN) +
2nCK
(MAX) +
2nCK
tRCD
13.75
(13.50)4
–
15.00
–
ns
tRP
13.75
(13.50)4
–
15.00
–
ns
9 × tREFI
35
9 × tREFI
ns
–
ns
Max
Unit
ACTIVATE-to-PRECHARGE command period
tRAS
35
ACTIVATE-to-ACTIVATE or REFRESH command period
tRC5
tRAS
+
–
tRP
336
Data Rate
Max (MT/s)
Equivalent
Speed Bin
tAAmin(ns):
non-DB
READ CL:
nonDBI
READ
CL: DBI
WRITE
CWL
1333
-
13.50
9
11
9
-
10
Max
(AVG)
1.500
1.9006
1.9006
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