MT40A512M16LY-075:E

8Gb: x4, x8, x16 DDR4 SDRAM Features DDR4 SDRAM MT40A2G4 MT40A1G8 MT40A512M16 Features s s s s s s s s s s s s s s s s s s s s s s s s s s s s s Options1 VDD = VDDQ = 1.2V ά60mV VPP6nM6M6 On-die, internal, adjustable VREFDQ generation 1.2V pseudo open-drain I/O Refresh time of 8192-cycle at TC temperature range: n 64ms at -40ιC to 85ιC n 32ms at >85ιC to 95ιC n 16ms at >95ιC to 105ιC 16 internal banks (x4, x8): 4 groups of 4 banks each 8 internal banks (x16): 2 groups of 4 banks each 8n-bit prefetch architecture Programmable data strobe preambles Data strobe preamble training Command/Address latency (CAL) Multipurpose register READ and WRITE capability Write leveling Self refresh mode Low-power auto self refresh (LPASR) Temperature controlled refresh (TCR) Fine granularity refresh Self refresh abort Maximum power saving Output driver calibration Nominal, park, and dynamic on-die termination (ODT) Data bus inversion (DBI) for data bus Command/Address (CA) parity Databus write cyclic redundancy check (CRC) Per-DRAM addressability Connectivity test JEDEC JESD-79-4 compliant sPPR and hPPR capability MBIST-PPR support (Die Revision R only) Marking s Configuration 2G4 n 2 Gig x 4 1G8 n 1 Gig x 8 512M16 n 512 Meg x 16 s  BALL&"'!PACKAGE0B FREE nXX PM n MMXMMn2EV! WE n MMXMMn2EV"$' SA n MMXMMn2EV%(*2 s  BALL&"'!PACKAGE0B FREE nX HA n MMXMMn2EV! JY n MMXMMn2EV" LY n MMXMMn2EV$%( TB n MMXMMn2EV*2 s 4IMINGnCYCLETIME -062E n 0.625ns @ CL = 22 (DDR4-3200) -068 n 0.682ns @ CL = 21 (DDR4-2933) -075 n 0.750ns @ CL = 19 (DDR4-2666) -075E n 0.750ns @ CL = 18 (DDR4-2666) -083 n 0.833ns @ CL = 17 (DDR4-2400) -083E n 0.833ns @ CL = 16 (DDR4-2400) -093E n 0.937ns @ CL = 15 (DDR4-2133) -107E n 1.071ns @ CL = 13 (DDR4-1866) s Operating temperature None n Commercial (0ι ζ TC ζ 95ιC) IT n )NDUSTRIALnι ζ TC ζ 95ιC) AT n !UTOMOTIVEnι ζ TC ζ 105ιC) :A, :B, :D, :E, s Revision :G, :H, :J, :R Notes: 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. Table 1: Key Timing Parameters Speed Grade1 Data Rate (MT/s) Target CL-nRCD-nRP -062Y 3200 22-22-22 13.75 (13.32) 13.75 (13.32) 13.75 (13.32) -062E 3200 22-22-22 13.75 13.75 13.75 -068 2933 21-21-21 14.32 (13.75) 14.32 (13.75) 14.32 (13.75) -075E 2666 18-18-18 13.50 13.50 13.50 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 1 t AA (ns) t RCD (ns) t RP (ns) Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 8Gb: x4, x8, x16 DDR4 SDRAM Features Table 1: Key Timing Parameters (Continued) Speed Grade1 Data Rate (MT/s) Target CL-nRCD-nRP tAA -075 2666 19-19-19 14.25 (13.75) 14.25 (13.75) 14.25 (13.75) -083E 2400 16-16-16 13.32 13.32 13.32 -083 2400 17-17-17 14.16 (13.75) 14.16 (13.75) 14.16 (13.75) -093E 2133 15-15-15 14.06 (13.50) 14.06 (13.50) 14.06 (13.50) -093 2133 16-16-16 15.00 15.00 15.00 -107E 1866 13-13-13 13.92 (13.50) 13.92 (13.50) 13.92 (13.50) (ns) tRCD tRP (ns) (ns) Notes: 1. Refer to the Speed Bin Tables for additional details. Table 2: Addressing Parameter Number of bank groups Bank group address Bank count per group Bank address in bank group Row addressing Column addressing Page size1 2048 Meg x 4 1024 Meg x 8 512 Meg x 16 4 4 2 BG[1:0] BG[1:0] BG0 4 4 4 BA[1:0] BA[1:0] BA[1:0] 128K (A[16:0]) 64K (A[15:0]) 64K (A[15:0]) 1K (A[9:0]) 1K (A[9:0]) 1K (A[9:0]) 512B 1KB 2KB Notes: 1. Page size is per bank, calculated as follows: Page size = 2COLBITS έ ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Features Figure 1: Order Part Number Example Example Part Number: MT40A1G8SA-062E:R Configuration Package Revision Speed { MT40A : Die Revision Configuration 2 Gig x 4 2G4 1 Gig x 8 1G8 512 Meg x 16 :A, :B, :D, :G, :E, :H, :J, :R 512M16 Case Temperature Mark Commercial None Mark Industrial IT 78-ball 9.0mm x 13.2mm FBGA PM Extended AT 78-ball 8.0mm x 12.0mm FBGA WE 78-ball 7.5mm x 11.0mm FBGA SA 96-ball 9.0mm x 14.0mm FBGA HA 96-ball 8.0mm x 14.0mm FBGA JY 96-ball 7.5mm x 13.5mm FBGA LY 96-ball 7.5mm x 13.0mm FBGA TB Package Speed Grade Cycle Time, CAS Latency -107E tCK = 1.071ns, CL = 13 tCK = 0.937ns, CL = 15 -093E -083E -083 -075E -075 -068 -062E CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 3 tCK = 0.833ns, CL = 16 tCK = 0.833ns, CL = 17 tCK = 0.750ns, CL = 18 tCK = 0.750ns, CL = 19 tCK = 0.682ns, CL = 21 tCK = 0.625ns, CL = 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Contents Important Notes and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General Notes and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Industrial Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Automotive Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Definitions of the Device-Pin Signal Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Definitions of the Bus Signal Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Functional Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 RESET and Initialization Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power-Up and Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 RESET Initialization with Stable Power Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Uncontrolled Power-Down Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Programming Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Burst Length, Type, and Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Write Recovery (WR)/READ-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 DLL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 DLL Enable/DLL Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Output Driver Impedance Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 ODT RTT(NOM) Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Additive Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Rx CTLE Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Termination Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 CAS WRITE Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Low-Power Auto Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Write Cyclic Redundancy Check Data Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Mode Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Multipurpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 WRITE Command Latency When CRC/DM is Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Fine Granularity Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Temperature Sensor Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Per-DRAM Addressability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Gear-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Mode Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Hard Post Package Repair Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Soft Post Package Repair Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 WRITE Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 READ Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Preamble Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Temperature-Controlled Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Command Address Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Internal VREF Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Maximum Power Savings Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 MBIST-PPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Mode Register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Data Bus Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 CA Parity Persistent Error Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ODT Input Buffer for Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CA Parity Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CRC Error Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 CA Parity Latency Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Mode Register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Data Rate Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 VREFDQ Calibration Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 VREFDQ Calibration Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 VREFDQ Calibration Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 NOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DESELECT Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DLL-Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 DLL-On/Off Switching Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DLL Switch Sequence from DLL-On to DLL-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DLL-Off to DLL-On Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Input Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Write Leveling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode . . . . . . . . . . . . . . . . . . . . . . . 81 Procedure Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Write Leveling Mode Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Command Address Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Low-Power Auto Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Manual Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Multipurpose Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 MPR Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MPR Readout Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MPR Readout Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 MPR Readout Parallel Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 MPR Readout Staggered Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 MPR READ Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 MPR Writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 MPR WRITE Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 MPR REFRESH Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Gear-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Maximum Power-Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Power-Saving Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Maximum Power-Saving Mode Entry in PDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 CKE Transition During Maximum Power-Saving Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Maximum Power-Saving Mode Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Command/Address Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Per-DRAM Addressability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 VREFDQ Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Range and Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 VREFDQ Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 VREFDQ Increment and Decrement Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 VREFDQ Target Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Connectivity Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Minimum Terms Definition for Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Logic Equations for a x4 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Logic Equations for a x8 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Logic Equations for a x16 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 CT Input Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Excessive Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Post Package Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Post Package Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Hard Post Package Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 hPPR Row Repair - Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 H0022OW2EPAIRn72!)NITIATED2%&#OMMANDS!LLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 H0022OW2EPAIRn72)NITIATED2%&#OMMANDS./4!LLOWED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sPPR Row Repair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 MBIST-PPR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 MBIST-PPR Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 hPPR/sPPR/MBIST-PPR Support Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ACTIVATE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Temperature-Controlled Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Normal Temperature Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Extended Temperature Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Fine Granularity Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Mode Register and Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 t REFI and tRFC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Changing Refresh Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Usage with TCR Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Self Refresh Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 SELF REFRESH Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Self Refresh Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Self Refresh Exit with NOP Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 0OWER $OWN#LARIFICATIONSn#ASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Power-Down Entry, Exit Timing with CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 ODT Input Buffer Disable Mode for Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 CRC Write Data Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 CRC Write Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 WRITE CRC DATA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 DBI_n and CRC Both Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DM_n and CRC Both Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 DM_n and DBI_n Conflict During Writes with CRC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CRC and Write Preamble Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CRC Simultaneous Operation Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CRC Polynomial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 CRC Combinatorial Logic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Burst Ordering for BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 CRC Data Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Enabled With BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 CRC with BC4 Data Bit Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 CRC Error Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 CRC Write Data Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Data Bus Inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DBI During a WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 DBI During a READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Programmable Preamble Modes and DQS Postambles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 WRITE Preamble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 READ Preamble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 READ Preamble Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 WRITE Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 READ Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Bank Access Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Read Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 2EAD4IMINGn#LOCK TO $ATA3TROBE2ELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 2EAD4IMINGn$ATA3TROBE TO $ATA2ELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 t LZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 t RPRE Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 tRPST Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 READ Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 READ Operation Followed by Another READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 READ Operation Followed by WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 READ Operation Followed by PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 READ Operation with Read Data Bus Inversion (DBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 READ Operation with Command/Address Parity (CA Parity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 READ Followed by WRITE with CRC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 READ Operation with Command/Address Latency (CAL) Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Write Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 7RITE4IMINGn#LOCK TO $ATA3TROBE2ELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 t WPRE Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 t WPST Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 7RITE4IMINGn$ATA3TROBE TO $ATA2ELATIONSHIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 WRITE Burst Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 WRITE Operation Followed by Another WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 WRITE Operation Followed by READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 WRITE Operation Followed by PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 WRITE Operation with WRITE DBI Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 WRITE Operation with CA Parity Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 WRITE Operation with Write CRC Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Write Timing Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Data Setup and Hold Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 Strobe-to-Strobe and Strobe-to-Clock Violations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 ZQ CALIBRATION Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 ODT Mode Register and ODT State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 ODT Read Disable State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Synchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ODT Latency and Posted ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 ODT During Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Dynamic ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 Asynchronous ODT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Absolute Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Supply Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Leakages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 VREFCA Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 VREFDQ Supply and Calibration Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 VREFDQ Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT-EASUREMENT,EVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 RESET_n Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Command/Address Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Command, Control, and Address Setup, Hold, and Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Data Receiver Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Connectivity Test (CT) Mode Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT-EASUREMENT,EVELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Differential Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Single-Ended Requirements for CK Differential Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Slew Rate Definitions for CK Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 CK Differential Input Cross Point Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 DQS Differential Input Signal Definition and Swing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 DQS Differential Input Cross Point Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Slew Rate Definitions for DQS Differential Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 %LECTRICAL#HARACTERISTICSn/VERSHOOTAND5NDERSHOOT3PECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Address, Command, and Control Overshoot and Undershoot Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Clock Overshoot and Undershoot Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Data, Strobe, and Mask Overshoot and Undershoot Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT,EVELS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Single-Ended Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Reference Load for AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Connectivity Test Mode Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER#HARACTERISTICS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Connectivity Test Mode Output Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Output Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Output Driver Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Alert Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 ODT Levels and I-V Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 ODT Temperature and Voltage Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 ODT Timing Definitions and Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 DRAM Package Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 IDD, IPP, and IDDQ Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 IDD Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Current Test Definitions and Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 #URRENT3PECIFICATIONSn,IMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Speed Bin Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 Refresh Parameters By Device Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 AC Electrical Characteristics and AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Electrical Characteristics and AC Timing Parameters: 2666 Through 3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Clock Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tCK(AVG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tCK(ABS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tCH(AVG) and tCL(AVG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tJIT(per) and tJIT(per,lck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tJIT(cc) and tJIT(cc,lck) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Definition for tERR(nper) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Jitter Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Converting Time-Based Specifications to Clock-Based Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Options Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM List of Figures Figure 1: Order Part Number Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 2: 2 Gig x 4 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 3: 1 Gig x 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 4: 512 Meg x 16 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 5: 78-Ball x4, x8 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 6: 96-Ball x16 Ball Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 7:  "ALL&"'!nXX0- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8:  "ALL&"'!nXX7% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 9:  "ALL&"'!nXX3! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 10:  "ALL&"'!nX(! . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 11:  "ALL&"'!nX*9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 12:  "ALL&"'!nX,9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 13:  "ALL&"'!nX4" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 14: Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 15: RESET and Initialization Sequence at Power-On Ramping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 16: RESET Procedure at Power Stable Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 17: tMRD Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 18: tMOD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 19: DLL-Off Mode Read Timing Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 20: DLL Switch Sequence from DLL-On to DLL-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figure 21: DLL Switch Sequence from DLL-Off to DLL-On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figure 22: Write Leveling Concept, Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Figure 23: Write Leveling Concept, Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Figure 24: Write Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2) . . . . . . . . . . . . . . . . . . . . . . . 82 Figure 25: Write Leveling Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Figure 26: CAL Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 27: CAL Timing Example (Consecutive CS_n = LOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Figure 28: #!,%NABLE4IMINGntMOD_CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 29: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 30: CAL Enabling MRS to Next MRS Command, tMRD_CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Figure 31: tMRD_CAL, Mode Register Cycle Time With CAL Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Figure 32: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 33: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Figure 34: Auto Self Refresh Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Figure 35: MPR Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Figure 36: MPR READ Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Figure 37: MPR Back-to-Back READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 38: MPR READ-to-WRITE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Figure 39: MPR WRITE and WRITE-to-READ Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 40: MPR Back-to-Back WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Figure 41: REFRESH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 42: READ-to-REFRESH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Figure 43: WRITE-to-REFRESH Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Figure 44: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 45: Clock Mode Change After Exiting Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Figure 46: Comparison Between Gear-Down Disable and Gear-Down Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Figure 47: Maximum Power-Saving Mode Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Figure 48: Maximum Power-Saving Mode Entry with PDA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 49: Maintaining Maximum Power-Saving Mode with CKE Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Figure 50: Maximum Power-Saving Mode Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Figure 51: Command/Address Parity Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Figure 52: Command/Address Parity During Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 53: Persistent CA Parity Error Checking Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Figure 54: #!0ARITY%RROR#HECKINGn32%!TTEMPT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 55: #!0ARITY%RROR#HECKINGn328!TTEMPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Figure 56: #!0ARITY%RROR#HECKINGn0$%0$8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 57: 0ARITY%NTRY4IMING%XAMPLEntMRD_PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 58: 0ARITY%NTRY4IMING%XAMPLEntMOD_PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Figure 59: 0ARITY%XIT4IMING%XAMPLEntMRD_PAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 60: 0ARITY%XIT4IMING%XAMPLEntMOD_PAR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Figure 61: CA Parity Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Figure 62: PDA Operation Enabled, BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 63: PDA Operation Enabled, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Figure 64: MRS PDA Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Figure 65: VREFDQ Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Figure 66: Example of VREF Set Tolerance and Step Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Figure 67: VREFDQ Timing Diagram for VREF,time Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Figure 68: VREFDQ Training Mode Entry and Exit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Figure 69: VREF Step: Single Step Size Increment Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 70: VREF Step: Single Step Size Decrement Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Figure 71: VREF Full Step: From VREF,min to VREF,maxCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 72: VREF Full Step: From VREF,max to VREF,minCase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Figure 73: VREFDQ Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Figure 74: Connectivity Test Mode Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Figure 75: H00272!n%NTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Figure 76: H00272!n2EPAIRAND%XIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Figure 77: H00272n%NTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 78: H00272n2EPAIRAND%XIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Figure 79: S002n%NTRY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Figure 80: S002n2EPAIRAND%XIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Figure 81: MBIST-PPR Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Figure 82: tRRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Figure 83: tFAW Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Figure 84: REFRESH Command Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 85: Postponing REFRESH Commands (Example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Figure 86: Pulling In REFRESH Commands (Example). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Figure 87: TCR Mode Example1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Figure 88: 4Gb with Fine Granularity Refresh Mode Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Figure 89: OTF REFRESH Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Figure 90: Self Refresh Entry/Exit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Figure 91: Self Refresh Entry/Exit Timing with CAL Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Figure 92: Self Refresh Abort. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 Figure 93: Self Refresh Exit with NOP Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Figure 94: Active Power-Down Entry and Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Figure 95: Power-Down Entry After Read and Read with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Figure 96: Power-Down Entry After Write and Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Figure 97: Power-Down Entry After Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 98: Precharge Power-Down Entry and Exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Figure 99: REFRESH Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 100: Active Command to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Figure 102: MRS Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Figure 103: 0OWER $OWN%NTRY%XIT#LARIFICATIONSn#ASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Figure 104: Active Power-Down Entry and Exit Timing with CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Figure 105: REFRESH Command to Power-Down Entry with CAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Figure 108: CRC Write Data Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Figure 109: CRC Error Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Figure 110: CA Parity Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 114: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Figure 115: 1tCK vs. 2tCK READ Preamble Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 Figure 116: READ Preamble Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Figure 117: WRITE Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Figure 118: READ Postamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Figure 119: Bank Group x4/x8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Figure 120: READ Burst tCCD_S and tCCD_L Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Figure 121: Write Burst tCCD_S and tCCD_L Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Figure 122: tRRD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) . . . . . . . . . . . . . . . . . 190 Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) . . . . . . . . . . . . . . . . . . . . 190 Figure 125: Read Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Figure 126: Clock-to-Data Strobe Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 Figure 127: Data Strobe-to-Data Relationship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Figure 129: tRPRE Method for Calculating Transitions and Endpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Figure 130: tRPST Method for Calculating Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . . 201 Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . . 201 Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group. . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group. . . . . . . . . . . . . . . . . . . . . . . . . 202 Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . 203 Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . 203 Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . 204 Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . 204 Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . . . 205 Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . . . 205 Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group. . . . . . . 206 Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group. . . . . . . 206 Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group. . . . . 207 Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group. . . . . 207 Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group . . . . . . . . . . . 208 Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group . . . . . . . . . . . 208 Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group . . . . . . . . . . . 209 Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group . . . . . . . . . . . 209 Figure 153: READ to PRECHARGE with 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 154: READ to PRECHARGE with 2tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Figure 156: READ with Auto Precharge and 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group . . . . . . . . . . . . . . . . . . . 213 Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group . . . . . . . . . . . . . . 213 Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group . . . 214 Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group . . . . . . . . . . . . 216 Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group . . . . . . . . . . . . 217 Figure 165: Write Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Figure 166: tWPRE Method for Calculating Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Figure 167: tWPST Method for Calculating Transitions and Endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Figure 168: Rx Compliance Mask. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 169: VCENT_DQ VREFDQ Voltage Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 Figure 170: Rx Mask DQ-to-DQS Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Figure 172: Example of Data Input Requirements Without Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . 228 Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group . . . . . . . . . . . . . . 228 Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group. . . . . . . . . . . . . . 229 Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group. . . . . . . . . . . . . . 229 Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group. . . . . . . . . . . . 230 Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . 230 Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . 231 Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . 231 Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group. . . . . . . . . . . . . . . 232 Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group . . . . . . . . . . . . . . . . . . 233 Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group . . . . . . . . . . . . 233 Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group . . . . . . . . . . . . . . . . 234 Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group . . . . . . . . . . . . . . 238 Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group. 239 Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group 242 Figure 202: ZQ Calibration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Figure 203: Functional Representation of ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 Figure 204: Synchronous ODT Timing with BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Figure 205: Synchronous ODT with BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 Figure 206: ODT During Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) . . . . . . . . . . . . . . . . . 252 Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) . . . . . . . 252 Figure 209: Asynchronous ODT Timings with DLL Off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 Figure 210: VREFDQ Voltage Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Figure 211: RESET_n Input Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Figure 212: Single-Ended Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 Figure 213: DQ Slew Rate Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Figure 214: Rx Mask Relative to tDS/tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Figure 215: Rx Mask Without Write Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Figure 216: TEN Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Figure 217: CT Type-A Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Figure 218: CT Type-B Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Figure 219: CT Type-C Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Figure 220: CT Type-D Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Figure 221: $IFFERENTIAL!#3WINGANDh4IME%XCEEDING!# ,EVELvtDVAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Figure 222: Single-Ended Requirements for CK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Figure 223: Differential Input Slew Rate Definition for CK_t, CK_c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Figure 224: VIX(CK) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Figure 225: Differential Input Signal Definition for DQS_t, DQS_c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling . . . . 278 Figure 227: VIXDQS Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c . . . . . . . . . . . . . . . . . . . . . . . . 280 Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Figure 230: CK Overshoot and Undershoot Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Figure 232: Single-ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Figure 233: Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Figure 234: Reference Load For AC Timing and Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Figure 235: Connectivity Test Mode Reference Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 236: Connectivity Test Mode Output Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Figure 237: Output Driver During Connectivity Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Figure 238: Output Driver: Definition of Voltages and Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Figure 239: Alert Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Figure 240: ODT Definition of Voltages and Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Figure 241: ODT Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Figure 242: tADC Definition with Direct ODT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Figure 243: tADC Definition with Dynamic ODT Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Figure 244: tAOFAS and tAONAS Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Figure 245: Thermal Measurement Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power . . . . . . . . . . . . . . . . . . . . . . . . . 308 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM List of Tables Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table 2: Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 3: Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4: State Diagram Command Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 5: Supply Power-up Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Table 6: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 7: MR0 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Table 8: Burst Type and Burst Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Table 9: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 10: MR1 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 11: Additive Latency (AL) Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 12: TDQS Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 13: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 14: MR2 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 15: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 16: MR3 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 17: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 18: MR4 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 19: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 20: MR5 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Table 21: Address Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 22: MR6 Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 23: 4RUTH4ABLEn#OMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 24: 4RUTH4ABLEn#+% . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 25: MR Settings for Leveling Procedures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 26: DRAM TERMINATION Function in Leveling Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 27: Auto Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 28: MR3 Setting for the MPR Access Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 29: DRAM Address to MPR UI Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Table 30: MPR Page and MPRx Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Table 31: MPR Readout Serial Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Table 32: -022EADOUTn0ARALLEL&ORMAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table 33: MPR Readout Staggered Format, x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 34: -022EADOUT3TAGGERED&ORMATXn#ONSECUTIVE2%!$S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Table 35: MPR Readout Staggered Format, x8 and x16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table 36: Mode Register Setting for CA Parity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 37: VREFDQ Range and Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 38: VREFDQ Settings (VDDQ = 1.2V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Table 39: Connectivity Mode Pin Description and Switching Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 40: MAC Encoding of MPR Page 3 MPR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table 41: PPR MR0 Guard Key Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Table 43: sPPR Associated Rows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 44: PPR MR0 Guard Key Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Table 45: DDR4 sPPR Timing Parameters DDR4-1600 Through DDR4-3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Table 46: MBIST-PPR Timing Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Table 47: MPR Page3 Configuration for MBIST-PPR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table 48: DDR4 Repair Mode Support Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Table 49: Normal tREFI Refresh (TCR Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Table 50: MRS Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Table 51: REFRESH Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Table 52: tREFI and tRFC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Table 53: Power-Down Entry Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 54: CRC Error Detection Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Table 55: CRC Data Mapping for x4 Devices, BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 56: CRC Data Mapping for x8 Devices, BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Table 57: CRC Data Mapping for x16 Devices, BL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Table 58: CRC Data Mapping for x4 Devices, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 59: CRC Data Mapping for x8 Devices, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 60: CRC Data Mapping for x16 Devices, BC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Table 61: DBI vs. DM vs. TDQS Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 62: DBI Write, DQ Frame Format (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 63: DBI Write, DQ Frame Format (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Table 64: DBI Read, DQ Frame Format (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 65: DBI Read, DQ Frame Format (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Table 66: DM vs. TDQS vs. DBI Function Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 67: Data Mask, DQ Frame Format (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 68: Data Mask, DQ Frame Format (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Table 69: CWL Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 Table 70: DDR4 Bank Group Timing Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Table 71: Read-to-Write and Write-to-Read Command Intervals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Table 72: Termination State Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 73: Read Termination Disable Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Table 74: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Table 75: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled). . . . . . . . . . . . . . . . . . . . . 251 Table 76: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix. . . . . . . . . . . . . . . . . . . 252 Table 77: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 78: Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Table 79: Recommended Supply Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Table 80: VDD Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Table 81: Leakages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Table 82: VREFDQ Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 Table 83: VREFDQ Range and Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Table 84: RESET_n Input Levels (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 Table 86: Command and Address Input Levels: DDR4-2666. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 87: Command and Address Input Levels: DDR4-2933 and DDR4-3200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 88: Single-Ended Input Slew Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Table 89: #OMMANDAND!DDRESS3ETUPAND(OLD6ALUES2EFERENCEDn!#$# "ASED . . . . . . . . . . . . . . . . . . . . . . . . 263 Table 90: Derating Values for tIS/t)(n!#$# "ASED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Table 91: Derating Values for tIS/t)(n!#$# "ASED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Table 92: DQ Input Receiver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Table 93: Rx Mask and tDS/tDH without Write Training . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Table 94: TEN Input Levels (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Table 95: CT Type-A Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Table 96: CT Type-B Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Table 97: CT Type-C Input Levels (CMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Table 98: CT Type-D Input Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Table 99: Differential Input Swing Requirements for CK_t, CK_c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 100: Minimum Time AC Time tDVAC for CK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 101: Single-Ended Requirements for CK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Table 102: CK Differential Input Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Table 103: Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 . . . . . . . . . . . 276 Table 104: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 . . . . . . . . . . . 276 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Table 105: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c . . . . . . . . . 277 Table 106: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c . . . . . . . . . 277 Table 107: Cross Point Voltage For Differential Input Signals DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Table 108: DQS Differential Input Slew Rate Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 Table 109: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c . . . 280 Table 110: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c . . . 281 Table 111: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Table 112: CK Overshoot and Undershoot/ Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Table 113: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 114: Single-Ended Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table 115: Single-Ended Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Table 116: Single-Ended Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 117: Differential Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Table 118: Differential Output Slew Rate Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Table 119: Differential Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Table 120: Connectivity Test Mode Output Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 Table 121: Connectivity Test Mode Output Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Table 122: Output Driver Electrical Characteristics During Connectivity Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 291 Table 123: Strong Mode (34?) Output Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Table 124: Weak Mode (48?) Output Driver Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Table 125: Output Driver Sensitivity Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Table 126: Output Driver Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Table 127: Alert Driver Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Table 128: ODT DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 Table 129: ODT Sensitivity Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Table 130: ODT Voltage and Temperature Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Table 131: ODT Timing Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Table 132: Reference Settings for ODT Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 Table 133: DRAM Package Electrical Specifications for x4 and x8 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 Table 134: DRAM Package Electrical Specifications for x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 Table 135: Pad Input/Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Table 136: Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308 Table 138: IDD0 and IPP0 Measurement-Loop Pattern1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Table 139: IDD1-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 Table 140: IDD2N, IDD3N, and IPP3P-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Table 141: IDD2NT-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 Table 142: IDD4R-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 Table 143: IDD4W-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 Table 144: IDD4Wc-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Table 145: IDD5R-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Table 146: IDD7-EASUREMENTn,OOP0ATTERN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 Table 147: Timings used for IDD, IPP, and IDDQ-EASUREMENTn,OOP0ATTERNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. A (0— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 Table 149: IDD, IPP, and IDDQ Current Limits; Die Rev. B (0— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Table 150: IDD, IPP, and IDDQ Current Limits; Die Rev. D (0— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Table 151: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Table 152: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40— ? TC ? 105—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Table 153: IDD, IPP, and IDDQ Current Limits; Die Rev. G (0— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Table 154: IDD, IPP, and IDDQ Current Limits; Die Rev. H (0— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 Table 155: IDD, IPP, and IDDQ Current Limits; Die Rev. J (-40— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Table 156: IDD, IPP, and IDDQ Current Limits; Die Rev. R (-40— ? TC ? 85—C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Table 157: Backward Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Table 158: DDR4-1600 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 Table 159: DDR4-1866 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 Table 160: DDR4-2133 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 Table 161: DDR4-2400 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Table 162: DDR4-2666 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Table 163: DDR4-2933 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 Table 164: DDR4-3200 Speed Bins and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Table 165: Refresh Parameters by Device Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 Table 166: Electrical Characteristics and AC Timing Parameters: DDR4-1600 through DDR4-2400 . . . . . . . . . . . . . 361 Table 167: Electrical Characteristics and AC Timing Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Table 168: /PTIONSn3PEED"ASED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Table 169: /PTIONSn7IDTH"ASED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM General Notes and Description General Notes and Description Description The DDR4 SDRAM is a high-speed dynamic random-access memory internally configured as an eight-bank DRAM for the x16 configuration and as a 16-bank DRAM for the x4 and x8 configurations. The DDR4 SDRAM uses an 8n-prefetch architecture to achieve high-speed operation. The 8n-prefetch architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE operation for the DDR4 SDRAM consists of a single 8n-bit wide, four-clock data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. Industrial Temperature An industrial temperature (IT) device option requires that the case temperature not exceed below nιC or above 95ιC. JEDEC specifications require the refresh rate to double when TC exceeds 85ιC; this also requires use of the high-temperature self refresh option. Additionally, ODT resistance and the input/output impedance must be derated when operating outside of the commercial temperature range, when TCISBETWEENnιC and 0ιC. Automotive Temperature The automotive temperature (AT) device option requires that the case temperature not exceed below nιC or above 105ιC. The specifications require the refresh rate to 2X when TC exceeds 85ιC; 4X when TC exceeds 95ιC. Additionally, ODT resistance and the input/output impedance must be derated when operating temperature Tc tMOD (MIN) + DODTLon + tADC s DLL = Disable, then tWLDQSEN > tMOD (MIN) + tAONAS CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Write Leveling Write Leveling Mode Exit Write leveling mode should be exited as follows: 1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note that from this point on, DQ pins are in undefined driving mode and will remain undefined, until tMOD after the respective MR command (Te1). 2. Drive ODT pin LOW (tIS must be satisfied) and continue registering LOW (see Tb0). 3. After RTT is switched off, disable write leveling mode via the MRS command (see Tc2). 4. After tMOD is satisfied (Te1), any valid command can be registered. (MR commands can be issued after tMRD [Td1]). Figure 25: Write Leveling Exit CK_c CK_t Command T0 T1 T2 DES DES DES Ta0 Tb0 DES DES Tc0 Tc1 Tc2 DES DES DES Td0 DES Td1 Valid Te0 DES Te1 Valid tMRD MR1 Address Valid tIS Valid tMOD ODT tADC ODTL (OFF) RTT(DQS_t) RTT(DQS_c) RTT(Park) tADC DQS_t, DQS_c RTT(DQ) DQ1 (MIN) RTT(NON) (MAX) tWLO result = 1 Undefined Driving Mode Transitioning Time Break Don’t Care Notes: 1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS signals capturing CK_t HIGH just after the T0 state. 2. See previous figure for specific tWLO timing. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 83 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency Command Address Latency DDR4 supports the command address latency (CAL) function as a power savings feature. This feature can be enabled or disabled via the MRS setting. CAL timing is defined as the delay in clock cycles (tCAL) between a CS_n registered LOW and its corresponding registered command and address. The value of CAL in clocks must be programmed into the mode register (see MR1 Register Definition table) and is based on the tCAL(ns)/tCK(ns) rounding algorithms found in the Converting Time-Based Specifications to Clock-Based Requirements section. Figure 26: CAL Timing Definition 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CLK CS_n CMD/ADDR tCAL CAL gives the DRAM time to enable the command and address receivers before a command is issued. After the command and the address are latched, the receivers can be disabled if CS_n returns to HIGH. For consecutive commands, the DRAM will keep the command and address input receivers enabled for the duration of the command sequence. Figure 27: CAL Timing Example (Consecutive CS_n = LOW) 1 2 3 4 5 6 7 8 9 10 11 12 CLK CS_n CMD/ADDR When the CAL mode is enabled, additional time is required for the MRS command to complete. The earliest the next valid command can be issued is tMOD_CAL, which should be equal to tMOD + tCAL. The two following figures are examples. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency Figure 28: #!,%NABLE4IMINGntMOD_CAL T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1 Tb2 Tb3 Command Valid MRS DES DES DES DES DES DES DES Valid Valid Address Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t CS_n tCAL tMOD_CAL Settings Old settings Updating settings New settings Time Break Don’t Care Note: 1. CAL mode is enabled at T1. Figure 29: tMOD_CAL, MRS to Valid Command Timing with CAL Enabled T0 T1 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 Valid DES DES MRS DES DES DES DES DES Valid Valid Valid Valid Valid CK_c CK_t Command tCAL Address Valid Valid tCAL Valid Valid Valid Valid Valid Valid CS_n tMOD_CAL Settings Old settings Updating settings New settings Time Break Don’t Care Note: 1. MRS at Ta1 may or may not modify CAL, tMOD_CAL is computed based on new tCAL setting if modified. When the CAL mode is enabled or being enabled, the earliest the next MRS command can be issued is t MRD_CAL is equal to tMOD + tCAL. The two following figures are examples. Figure 30: CAL Enabling MRS to Next MRS Command, tMRD_CAL T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Valid MRS DES DES DES DES DES DES Tb1 Tb2 Tb3 DES MRS DES Valid Valid Valid CK_c CK_t Command tCAL Address Valid Valid Valid Valid Valid Valid Valid Valid CS_n tMRD_CAL Settings Old settings Updating settings Updating settings Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 85 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency Note: 1. Command address latency mode is enabled at T1. Figure 31: tMRD_CAL, Mode Register Cycle Time With CAL Enabled T0 T1 Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 Tc0 Tc1 Tc2 DES DES MRS DES DES DES DES DES MRS DES Valid Valid Valid Valid CK_c CK_t Command Valid t CAL Address Valid t CAL Valid Valid Valid Valid Valid Valid CS_n t MRD_CAL Settings Old settings Updating settings New settings Time Break Don’t Care Note: 1. MRS at Ta1 may or may not modify CAL, tMRD_CAL is computed based on new tCAL setting if modified. CAL Examples: Consecutive READ BL8 with two different CALs and 1tCK preamble in different bank group shown in the following figures. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 86 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Figure 32: Consecutive READ BL8, CAL3, 1tCK Preamble, Different Bank Group T0 T1 T2 T3 DES READ T4 T5 T6 T7 T13 T14 T15 DES DES READ DES DES DES T16 T17 T18 T19 T20 DES DES T21 T22 CK_c CK_t CS_n t DES Command t CAL = 3 CAL = 3 DES DES DES DES DES t CCD_S = 4 Bank Group Address Address BG a BG b Bank, Col n Bank, Col b tRPRE tRPST (1nCK) DQS_t, DQS_c DQ DOUT n RL = 11 DOUT n+1 DOUT n+2 DOUT n+4 DOUT n+3 DOUT n+5 DOUT n+6 DOUT n+7 DOUT b DOUT b+7 DOUT b+2 DOUT b+3 DOUT b+4 DOUT b+5 DOUT b+6 DOUT b+7 RL = 11 Transitioning Data Notes: 1. 2. 3. 4. 5. 6. Don’t Care BL = 8, AL = 0, CL = 11, CAL = 3, Preamble = 1tCK. DOUT n = data-out from column n; DOUT b = data-out from column b. DES commands are shown for ease of illustration, other commands may be valid at these times. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T3 and T7. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the same timing relationship relative to the command/address bus as when CAL is disabled. Figure 33: Consecutive READ BL8, CAL4, 1tCK Preamble, Different Bank Group 87 T0 T1 T2 T3 T4 T5 DES DES READ DES T6 T7 T8 T14 T15 T16 T17 T18 T19 DES DES READ DES DES DES DES DES DES T20 T21 T22 T23 DES DES DES CK_c CK_t CS_n t Command DES CAL = 4 CAL = 4 t CCD_S = 4 Bank Group Address BG a BG b Address Bank, Col n Bank, Col b t RPRE DES t RPST (1nCK) DQS_t, DQS_c DQ DOUT n RL = 11 DOUT n+1 DOUT n+2 DOUT n+3 DOUT n+4 DOUT n+5 DOUT n+6 DOUT n+7 DOUT b DOUT b+7 DOUT b+2 DOUT b+3 DOUT b+4 DOUT b+5 DOUT b+6 DOUT b+7 RL = 11 Transitioning Data Notes: 1. 2. 3. 4. 5. 6. Don’t Care BL = 8, AL = 0, CL = 11, CAL = 4, Preamble = 1tCK. DOUT n = data-out from column n; DOUT b = data-out from column b. DES commands are shown for ease of illustration, other commands may be valid at these times. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T4 and T8. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable. Enabling CAL mode does not impact ODT control timings. ODT control timings should be maintained with the same timing relationship relative to the command/address bus as when CAL is disabled. 8Gb: x4, x8, x16 DDR4 SDRAM Command Address Latency Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. t 8Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode Low-Power Auto Self Refresh Mode An auto self refresh mode is provided for application ease. Auto self refresh mode is enabled by setting MR2[6] = 1 and MR2[7] = 1. The device will manage self refresh entry over the supported temperature range of the DRAM. In this mode, the device will change its self refresh rate as the DRAM operating temperature changes, going lower at low temperatures and higher at high temperatures. Manual Self Refresh Mode If auto self refresh mode is not enabled, the low-power auto self refresh mode register must be manually programmed to one of the three self refresh operating modes. This mode provides the flexibility to select a fixed self refresh operating mode at the entry of the self refresh, according to the system memory temperature conditions. The user is responsible for maintaining the required memory temperature condition for the mode selected during the SELF REFRESH operation. The user may change the selected mode after exiting self refresh and before entering the next self refresh. If the temperature condition is exceeded for the mode selected, there is a risk to data retention resulting in loss of data. Table 27: Auto Self Refresh Mode MR2[7] MR2[6] Low-Power Auto Self Refresh Mode SELF REFRESH Operation 0 0 Normal 1 0 Extended temperature Variable or fixed high self refresh rate optimizes data retention to support the extended temperature range. -40ιC to 105ιC 0 1 Reduced temperature Variable or fixed self refresh rate or any other DRAM power consumption reduction control for the reduced temperature range. User is required to ensure 45ιC DRAM TCASE (MAX) is not exceeded to avoid any risk of data loss. -40ιC to 45ιC 1 1 Auto self refresh Auto self refresh mode enabled. Self refresh power consumption and data retention are optimized for any given operating temperature condition. All of the above CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Variable or fixed normal self refresh rate maintains data retention at the normal operating temperature. User is required to ensure that 85ιC DRAM TCASE (MAX) is not exceeded to avoid any risk of data loss. Operating Temperature Range for Self Refresh Mode (DRAM TCASE) 88 -40ιC to 85ιC Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Low-Power Auto Self Refresh Mode Figure 34: Auto Self Refresh Ranges IDD6 2x refresh rate 1x refresh rate Extended temperature range 1/2x refresh rate Reduced temperature range -40°C CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Normal temperature range 85°C 45°C 89 105°C Tc Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Multipurpose Register The MULTIPURPOSE REGISTER (MPR) function, MPR access mode, is used to write/read specialized data to/from the DRAM. The MPR consists of four logical pages, MPR Page 0 through MPR Page 3, with each page having four 8-bit registers, MPR0 through MPR3. Page 0 can be read by any of three readout modes (serial, parallel, or staggered) while Pages 1, 2, and 3 can be read by only the serial readout mode. Page 3 is for DRAM vendor use only. MPR mode enable and page selection is done with MRS commands. Data bus inversion (DBI) is not allowed during MPR READ operation. Once the MPR access mode is enabled (MR3[2] = 1), only the following commands are allowed: MRS, RD, RDA WR, WRA, DES, REF, and RESET; RDA/WRA have the same functionality as RD/WR which means the auto precharge part of RDA/WRA is ignored. Power-down mode and SELF REFRESH command are not allowed during MPR enable mode. No other command can be issued within tRFC after a REF command has been issued; 1x refresh (only) is to be used during MPR access mode. While in MPR access mode, MPR read or write sequences must be completed prior to a REFRESH command. Figure 35: MPR Block Diagram Memory core (all banks precharged) Four multipurpose registers (pages), each with four 8-bit registers: MR3 [2] = 1 Data patterns (RD/WR) Error log (RD) Mode registers (RD) flow data PR M DRAM manufacture only (RD) DQ,s DM_n/DBI_n, DQS_t, DQS_c Table 28: MR3 Setting for the MPR Access Mode Address Operation Mode A[12:11] MPR data read format A2 MPR access A[1:0] MPR page selection Description 00 = Serial ........... 01 = Parallel 10 = Staggered .... 11 = Reserved 0 = Standard operation (MPR not enabled) 1 = MPR data flow enabled 00 = Page 0 .... 01 = Page 1 10 = Page 2 .... 11 = Page 3 Table 29: DRAM Address to MPR UI Translation MPR Location [7] [6] [5] [4] [3] [2] [1] [0] $2!-ADDRESSn!x A7 A6 A5 A4 A3 A2 A1 A0 -025)n5)x UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 90 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Table 30: MPR Page and MPRx Definitions Address MPR Location [7] [6] [5] [4] [3] [2] [1] [0] Note Read/ Write (default value listed) -020AGEn2EADOR7RITE$ATA0ATTERNS BA[1:0] 00 = MPR0 0 1 0 1 0 1 0 1 01 = MPR1 0 0 1 1 0 0 1 1 10 = MPR2 0 0 0 0 1 1 1 1 11 = MPR3 0 0 0 0 0 0 0 0 A6 A5 A4 A3 A2 A1 A0 A13 A12 A11 A10 A9 A8 BG1 BG0 BA1 BA0 A17 RAS_n/A 16 C2 C1 C0 -020AGEn2EAD ONLY%RROR,OG BA[1:0] 00 = MPR0 01 = MPR1 A7 CAS_n/A WE_n/A 15 14 10 = MPR2 PAR 11 = MPR3 CRC error status ACT_n CA parity error status CA parity latency: [5] = MR5[2], [4] = MR5[1], [3] = MR5[0] Readonly -020AGEn2EAD ONLY-232EADOUT BA[1:0] 00 = MPR0 hPPR support sPPR RTT(WR) Temperature sen- CRC write enable support MR2[11] sor status2 MR2[12] RTT(WR) MR2[10:9] 01 = MPR1 VREFDQ trainging range MR6[6]VREFDQ training value: [6:1] = MR6[5:0] Geardown enable MR3[3] 10 = MPR2CAS latency: [7:3] = MR0[6:4,2,12] 11 = MPR3RTT(NOM): [7:5] = MR1[10:8] Readonly CAS write latency [2:0] = MR2[5:3] RTT(Park): [4:2] = MR5[8:6] RON: [1:0] = MR1[2:1] -020AGEn2EAD ONLY2ESTRICTEDEXCEPTFOR-02;= BA[1:0] 00 = MPR0 DC DC DC DC DC DC DC DC 01 = MPR1 DC DC DC DC DC DC DC DC 10 = MPR2 DC DC DC DC DC DC DC DC 11 = MPR3 MBIST-P PR Support MAC MAC MAC MAC DCMBIST-PPR Transparency Readonly Notes: 1. DC = "Don't Care" 2. MPR[4:3] 00 = Sub 1X refresh; MPR[4:3] 01 = 1X refresh; MPR[4:3] 10 = 2X refresh; MPR[4:3] 11 = Reserved MPR Reads MPR reads are supported using BL8 and BC4 modes. Burst length on-the-fly is not supported for MPR reads. Data bus inversion (DBI) is not allowed during MPR READ operation; the device will ignore the Read DBI enable setting in MR5 [12] when in MPR mode. READ commands for BC4 are supported with a starting column address of A[2:0] = 000 or 100. After power-up, the content of MPR Page 0 has the default values, which are defined in . MPR page 0 can be rewritten via an MPR WRITE command. The CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register device maintains the default values unless it is rewritten by the DRAM controller. If the DRAM controller does overwrite the default values (Page 0 only), the device will maintain the new values unless re-initialized or there is power loss. Timing in MPR mode: s Reads (back-to-back) from Page 0 may use tCCD_S or tCCD_L timing between READ commands s Reads (back-to-back) from Pages 1, 2, or 3 may not use tCCD_S timing between READ commands; t CCD_L must be used for timing between READ commands The following steps are required to use the MPR to read out the contents of a mode register (MPR Page x, MPRy). 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (Enable MPR data flow), MR3[12:11] = MPR read format, and MR3[1:0] MPR page. a) MR3[12:11] MPR read format: i) 00 = Serial read format ii) 01 = Parallel read format iii) 10 = staggered read format iv) 11 = RFU b) MR3[1:0] MPR page: i) 00 = MPR Page 0 ii) 01 = MPR Page 1 iii) 10 = MPR Page 2 iv) 11 = MPR Page 3 4. tMRD and tMOD must be satisfied. 5. Redirect all subsequent READ commands to specific MPRx location. 6. Issue RD or RDA command. a) BA1 and BA0 indicate MPRx location: i) 00 = MPR0 ii) 01 = MPR1 iii) 10 = MPR2 iv) 11 = MPR3 b) A12/BC = 0 or 1; BL8 or BC4 fixed-only, BC4 OTF not supported. i) If BL = 8 and MR0 A[1:0] = 01, A12/BC must be set to 1 during MPR READ commands. c) A2 = burst-type dependant: i) BL8: A2 = 0 with burst order fixed at 0, 1, 2, 3, 4, 5, 6, 7 ii) BL8: A2 = 1 not allowed iii) BC4: A2 = 0 with burst order fixed at 0, 1, 2, 3, T, T, T, T iv) BC4: A2 = 1 with burst order fixed at 4, 5, 6, 7, T, T, T, T d) A[1:0] = 00, data burst is fixed nibble start at 00. e) 2EMAININGADDRESSINPUTSINCLUDING!AND"'AND"'ARE$ONT#ARE 7. After RL = AL + CL, DRAM bursts data from MPRx location; MPR readout format determined by MR3[A12,11,1,0]. 8. Steps 5 through 7 may be repeated to read additional MPRx locations. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register 9. After the last MPRx READ burst, tMPRR must be satisfied prior to exiting. 10.Issue MRS command to exit MPR mode; MR3[2] = 0. 11.After the tMOD sequence is completed, the DRAM is ready for normal operation from the core (such as ACT). MPR Readout Format The MPR read data format can be set to three different settings: serial, parallel, and staggered. MPR Readout Serial Format The serial format is required when enabling the MPR function to read out the contents of an MRx, temperature sensor status, and the command address parity error frame. However, data bus calibration locations (four 8-bit registers) can be programmed to read out any of the three formats. The DRAM is required to drive associated strobes with the read data similar to normal operation (such as using MRS preamble settings). Serial format implies that the same pattern is returned on all DQ lanes, as shown the table below, which uses values programmed into the MPR via [7:0] as 0111 1111. Table 31: MPR Readout Serial Format Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQ0 0 1 1 1 1 1 1 1 DQ1 0 1 1 1 1 1 1 1 DQ2 0 1 1 1 1 1 1 1 DQ3 0 1 1 1 1 1 1 1 DQ0 0 1 1 1 1 1 1 1 DQ1 0 1 1 1 1 1 1 1 DQ2 0 1 1 1 1 1 1 1 DQ3 0 1 1 1 1 1 1 1 DQ4 0 1 1 1 1 1 1 1 DQ5 0 1 1 1 1 1 1 1 DQ6 0 1 1 1 1 1 1 1 DQ7 0 1 1 1 1 1 1 1 DQ0 0 1 1 1 1 1 1 1 DQ1 0 1 1 1 1 1 1 1 DQ2 0 1 1 1 1 1 1 1 DQ3 0 1 1 1 1 1 1 1 DQ4 0 1 1 1 1 1 1 1 DQ5 0 1 1 1 1 1 1 1 DQ6 0 1 1 1 1 1 1 1 DQ7 0 1 1 1 1 1 1 1 x4 Device x8 Device x16 Device CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Table 31: MPR Readout Serial Format (Continued) Serial UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQ8 0 1 1 1 1 1 1 1 DQ9 0 1 1 1 1 1 1 1 DQ10 0 1 1 1 1 1 1 1 DQ11 0 1 1 1 1 1 1 1 DQ12 0 1 1 1 1 1 1 1 DQ13 0 1 1 1 1 1 1 1 DQ14 0 1 1 1 1 1 1 1 DQ15 0 1 1 1 1 1 1 1 MPR Readout Parallel Format Parallel format implies that the MPR data is returned in the first data UI and then repeated in the remaining UIs of the burst, as shown in the table below. Data pattern location 0 is the only location used for the parallel format. RD/RDA from data pattern locations 1, 2, and 3 are not allowed with parallel data return mode. In this example, the pattern programmed in the data pattern location 0 is 0111 1111. The x4 configuration only outputs the first four bits (0111 in this example). For the x16 configuration, the same pattern is repeated on both the upper and lower bytes. Table 32: -022EADOUTn0ARALLEL&ORMAT Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQ0 0 0 0 0 0 0 0 0 DQ1 1 1 1 1 1 1 1 1 DQ2 1 1 1 1 1 1 1 1 DQ3 1 1 1 1 1 1 1 1 DQ0 0 0 0 0 0 0 0 0 DQ1 1 1 1 1 1 1 1 1 DQ2 1 1 1 1 1 1 1 1 DQ3 1 1 1 1 1 1 1 1 DQ4 1 1 1 1 1 1 1 1 DQ5 1 1 1 1 1 1 1 1 DQ6 1 1 1 1 1 1 1 1 DQ7 1 1 1 1 1 1 1 1 DQ0 0 0 0 0 0 0 0 0 DQ1 1 1 1 1 1 1 1 1 DQ2 1 1 1 1 1 1 1 1 DQ3 1 1 1 1 1 1 1 1 DQ4 1 1 1 1 1 1 1 1 x4 Device x8 Device x16 Device CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 94 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Table 32: -022EADOUTn0ARALLEL&ORMAT Parallel UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQ5 1 1 1 1 1 1 1 1 DQ6 1 1 1 1 1 1 1 1 DQ7 1 1 1 1 1 1 1 1 DQ8 0 0 0 0 0 0 0 0 DQ9 1 1 1 1 1 1 1 1 DQ10 1 1 1 1 1 1 1 1 DQ11 1 1 1 1 1 1 1 1 DQ12 1 1 1 1 1 1 1 1 DQ13 1 1 1 1 1 1 1 1 DQ14 1 1 1 1 1 1 1 1 DQ15 1 1 1 1 1 1 1 1 MPR Readout Staggered Format Staggered format of data return is defined as the staggering of the MPR data across the lanes. In this mode, an RD/RDA command is issued to a specific data pattern location and then the data is returned on the DQ from each of the different data pattern locations. For the x4 configuration, an RD/RDA to data pattern location 0 will result in data from location 0 being driven on DQ0, data from location 1 being driven on DQ1, data from location 2 being driven on DQ2, and so on, as shown below. Similarly, an RD/RDA command to data pattern location 1 will result in data from location 1 being driven on DQ0, data from location 2 being driven on DQ1, data from location 3 being driven on DQ2, and so on. Examples of different starting locations are also shown. Table 33: MPR Readout Staggered Format, x4 x4 READ MPR0 Command x4 READ MPR1 Command x4 READ MPR2 Command x4 READ MPR3 Command Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] DQ0 MPR0 DQ0 MPR1 DQ0 MPR2 DQ0 MPR3 DQ1 MPR1 DQ1 MPR2 DQ1 MPR3 DQ1 MPR0 DQ2 MPR2 DQ2 MPR3 DQ2 MPR0 DQ2 MPR1 DQ3 MPR3 DQ3 MPR0 DQ3 MPR1 DQ3 MPR2 It is expected that the DRAM can respond to back-to-back RD/RDA commands to the MPR for all DDR4 frequencies so that a sequence (such as the one that follows) can be created on the data bus with no bubbles or clocks between read data. In this case, the system memory controller issues a sequence of RD(MPR0), RD(MPR1), RD(MPR2), RD(MPR3), RD(MPR0), RD(MPR1), RD(MPR2), and RD(MPR3). Table 34: -022EADOUT3TAGGERED&ORMATXn#ONSECUTIVE2%!$S Stagger UI[7:0] UI[15:8] UI[23:16] UI[31:24] UI[39:32] UI[47:40] UI[55:48] UI[63:56] DQ0 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 DQ1 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 DQ2 MPR2 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 DQ3 MPR3 MPR0 MPR1 MPR2 MPR3 MPR0 MPR1 MPR2 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register For the x8 configuration, the same pattern is repeated on the lower nibble as on the upper nibble. READs to other MPR data pattern locations follow the same format as the x4 case. A read example to MPR0 for x8 and x16 configurations is shown below. Table 35: MPR Readout Staggered Format, x8 and x16 x8 READ MPR0 Command x16 READ MPR0 Command x16 READ MPR0 Command Stagger UI[7:0] Stagger UI[7:0] Stagger UI[7:0] DQ0 MPR0 DQ0 MPR0 DQ8 MPR0 DQ1 MPR1 DQ1 MPR1 DQ9 MPR1 DQ2 MPR2 DQ2 MPR2 DQ10 MPR2 DQ3 MPR3 DQ3 MPR3 DQ11 MPR3 DQ4 MPR0 DQ4 MPR0 DQ12 MPR0 DQ5 MPR1 DQ5 MPR1 DQ13 MPR1 DQ6 MPR2 DQ6 MPR2 DQ14 MPR2 DQ7 MPR3 DQ7 MPR3 DQ15 MPR3 MPR READ Waveforms The following waveforms show MPR read accesses. Figure 36: MPR READ Timing T0 Ta0 Ta1 Tb0 Tc0 Tc1 Tc2 Tc3 Td0 Td1 DES READ DES DES DES DES DES DES Te0 Tf0 Tf1 Valid 4 DES Valid Valid CK_c CK_t MPE Enable Command MRS1 PREA tRP Address Valid MPE Disable Valid Valid MRS3 tMPRR tMOD Add2 Valid Valid Valid Valid Valid Valid tMOD Valid CKE PL5 + AL + CL DQS_t, DQS_c DQ UI0 UI1 UI2 UI5 UI6 UI7 Time Break Don’t Care Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK. 2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#AREINCLUDING"'AND"'!IS$ONT#AREWHEN-2!;= or 10 and must be 1b when MR0 A[1:0] = 01 3. Multipurpose registers read/write disable (MR3 A2 = 0). 4. Continue with regular DRAM command. 5. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Figure 37: MPR Back-to-Back READ Timing T0 T1 T2 DES READ DES T3 T4 T5 T6 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 DES DES READ DES DES DES DES DES DES DES DES DES DES DES DES Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t Command tCCD_S1 Address Add2 Valid Valid Add2 CKE PL3 + AL + CL DQS_t, DQS_c DQ UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 DQS_t, DQS_c DQ Time Break Don’t Care Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK. 2. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7; for BC = 4, burst order is fixed at 0, 1, 2, 3, T, T, T, T) BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#AREINCLUDING"'AND"'!IS$ONT#AREWHEN-2!;= or 10 and must be 1b when MR0 A[1:0] = 01 3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled. Figure 38: MPR READ-to-WRITE Timing T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 READ DES DES DES DES DES DES DES DES DES Tb0 Tb1 Tb2 WRITE DES DES Add2 Valid Valid CK_c CK_t Command tMPRR Address Add1 Valid Valid Valid Valid Valid Valid Valid Valid Valid CKE PL3 + AL + CL DQS_t, DQS_c DQ UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 Time Break Don’t Care Notes: 1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#AREINCLUDING"'AND"'!IS$ONT#AREWHEN-2!;= and must be 1b when MR0 A[1:0] = 01 2. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#ARE CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register 3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled. MPR Writes MPR access mode allows 8-bit writes to the MPR Page 0 using the address bus A[7:0]. Data bus inversion (DBI) is not allowed during MPR WRITE operation. The DRAM will maintain the new written values unless re-initialized or there is power loss. The following steps are required to use the MPR to write to mode register MPR Page 0. 1. The DLL must be locked if enabled. 2. Precharge all; wait until tRP is satisfied. 3. MRS command to MR3[2] = 1 (enable MPR data flow) and MR3[1:0] = 00 (MPR Page 0); writes to 01, 10, and 11 are not allowed. 4. tMRD and tMOD must be satisfied. 5. Redirect all subsequent WRITE commands to specific MPRx location. 6. Issue WR or WRA command: a) BA1 and BA0 indicate MPRx location i) 00 = MPR0 ii) 01 = MPR1 iii) 10 = MPR2 iv) 11 = MPR3 b) A[7:0] = data for MPR Page 0, mapped A[7:0] to UI[7:0]. c) 2EMAININGADDRESSINPUTSINCLUDING!AND"'AND"'ARE$ONT#ARE 7. tWR_MPR must be satisfied to complete MPR WRITE. 8. Steps 5 through 7 may be repeated to write additional MPRx locations. 9. After the last MPRx WRITE, tMPRR must be satisfied prior to exiting. 10.Issue MRS command to exit MPR mode; MR3[2] = 0. 11.When the tMOD sequence is completed, the DRAM is ready for normal operation from the core (such as ACT). MPR WRITE Waveforms The following waveforms show MPR write accesses. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Figure 39: MPR WRITE and WRITE-to-READ Timing T0 Ta0 Ta1 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Td2 Td3 Td4 Td5 DES WRITE DES DES READ DES DES DES DES DES DES Valid Add Valid Valid Valid Add2 Valid Valid CK_c CK_t MPR Enable Command MRS1 PREA tRP Address Valid tMOD Valid tWR_MPR Valid Add2 Valid CKE PL3 + AL + CL DQS_t, DQS_c DQ UI0 UI1 UI2 UI3 UI4 UI5 UI6 Time Break UI7 Don’t Care Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). 2. Address setting: BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#ARE 3. Parity latency (PL) is added to data output delay when CA parity latency mode is enabled. Figure 40: MPR Back-to-Back WRITE Timing T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Ta10 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES Valid Valid Add Valid Valid Valid Valid Valid Valid CK_c CK_t Command tWR_MPR Address Add1 Valid Valid Add1 CKE DQS_t, DQS_c DQ Time Break Don’t Care Note: 1. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR !ANDOTHERADDRESSPINSARE$ONT#ARE CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register MPR REFRESH Waveforms The following waveforms show MPR accesses interaction with refreshes. Figure 41: REFRESH Timing T0 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 DES REF2 DES DES DES Tb4 Tc0 Tc1 Tc2 Tc3 Tc4 DES DES DES Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t MPR Enable Command MRS1 PREA tRP Address Valid tMOD Valid tRFC Valid Valid Valid Valid Valid Time Break Don’t Care Notes: 1. Multipurpose registers read/write enable (MR3 A2 = 1). Redirect all subsequent read and writes to MPR locations. 2. 1x refresh is only allowed when MPR mode is enabled. Figure 42: READ-to-REFRESH Timing T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 Command READ DES DES DES DES DES DES DES DES DES REF2 DES DES Address Add1 Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t CKE PL + AL + CL tRFC (4 + 1) Clocks BL = 8 DQS_t, DQS_c DQ UI0 UI1 UI2 UI3 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 BC = 4 DQS_t, DQS_c DQ Time Break Don’t Care Notes: 1. Address setting: A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here) A2 = 0b (for BL = 8, burst order is fixed at 0, 1, 2, 3, 4, 5, 6, 7) BA1 and BA0 indicate the MPR location !ANDOTHERADDRESSPINSARE$ONT#AREINCLUDING"'AND"'!IS$ONT#AREWHEN-2!;= or 10, and must be 1b when MR0 A[1:0] = 01 2. 1x refresh is only allowed when MPR mode is enabled. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 100 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Multipurpose Register Figure 43: WRITE-to-REFRESH Timing T0 T1 WRITE DES Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 DES DES REF2 DES DES DES Ta6 Ta7 Ta8 Ta9 Ta10 DES DES DES DES DES Valid Valid Valid Valid Valid CK_c CK_t Command tWR_MPR Address Add1 Valid Valid tRFC Valid Valid Valid Valid Valid CKE DQS_t, DQS_c DQ Time Break Don’t Care Notes: 1. Address setting: BA1 and BA0 indicate the MPR location A[7:0] = data for MPR !ANDOTHERADDRESSPINSARE$ONT#ARE 2. 1x refresh is only allowed when MPR mode is enabled. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 101 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode Gear-Down Mode The DDR4 SDRAM defaults in 1/2 rate (1N) clock mode and uses a low-frequency MRS command (the MRS command has relaxed setup and hold) followed by a sync pulse (first CS pulse after MRS setting) to align the proper clock edge for operating the control lines CS_n, CKE, and ODT when in 1/4 rate (2N) mode. Gear-down mode is only supported at DDR4-2666 and faster. For operation in 1/2 rate mode, neither an MRS command or a sync pulse is required. Gear-down mode may only be entered during initialization or self refresh exit and may only be exited during self refresh exit. CAL mode and CA parity mode must be disabled prior to gear-down mode entry. The two modes may be enabled after tSYNC_GEAR and tCMD_GEAR periods have been satisfied. The general sequence for operation in 1/4 rate during initialization is as follows: 1. The device defaults to a 1N mode internal clock at power-up/reset. 2. Assertion of reset. 3. Assertion of CKE enables the DRAM. 4. MRS is accessed with a low-frequency N έ tCK gear-down MRS command. (NtCK static MRS command is qualified by 1N CS_n. ) 5. The memory controller will send a 1N sync pulse with a low-frequency N έ tCK NOP command. t SYNC_GEAR is an even number of clocks. The sync pulse is on an even edge clock boundary from the MRS command. 6. Initialization sequence, including the expiration of tDLLK and tZQinit, starts in 2N mode after t CMD_GEAR from 1N sync pulse. The device resets to 1N gear-down mode after entering self refresh. The general sequence for operation in gear-down after self refresh exit is as follows: 1. MRS is set to 1, via MR3[3], with a low-frequency N έ tCK gear-down MRS command. a) The NtCK static MRS command is qualified by 1N CS_n, which meets tXS or tXS_ABORT. b) Only a REFRESH command may be issued to the DRAM before the NtCK static MRS command. 2. The DRAM controller sends a 1N sync pulse with a low-frequency N έ tCK NOP command. a) tSYNC_GEAR is an even number of clocks. b) The sync pulse is on even edge clock boundary from the MRS command. 3. A valid command not requiring locked DLL is available in 2N mode after tCMD_GEAR from the 1N sync pulse. a) A valid command requiring locked DLL is available in 2N mode after tXSDLL or tDLLK from the 1N sync pulse. 4. If operation is in 1N mode after self refresh exit, N έ tCK MRS command or sync pulse is not required during self refresh exit. The minimum exit delay to the first valid command is tXS, or tXS_ABORT. The DRAM may be changed from 2N to 1N by entering self refresh mode, which will reset to 1N mode. Changing from 2N to by any other means can result in loss of data and make operation of the DRAM uncertain. When operating in 2N gear-down mode, the following MR settings apply: s CAS latency (MR0[6:4,2]): Even number of clocks s Write recovery and read to precharge (MR0[11:9]): Even number of clocks s Additive latency (MR1[4:3]): CL - 2 s CAS WRITE latency (MR2 A[5:3]): Even number of clocks s CS to command/address latency mode (MR4[8:6]): Even number of clocks CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 102 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode s CA parity latency mode (MR5[2:0]): Even number of clocks Figure 44: Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization) TdkN + Neven2 TdkN1 CK_c CK_t tCKSRX DRAM internal CLK RESET_n CKE tCMD_GEAR tSYNC_GEAR tXPR_GEAR 1N sync pulse 2N mode CS_n tGEAR_setup Command tGEAR_hold tGEAR_setup MRS tGEAR_hold NOP Valid Configure DRAM to 1/4 rate Time Break Don’t Care Notes: 1. After tSYNC_GEAR from GEAR-DOWN command, internal clock rate is changed at TdkN. 2. After tSYNC_GEAR + tCMD_GEAR from GEAR-DOWN command, both internal clock rate and command cycle are changed at TdkN + Neven. Figure 45: Clock Mode Change After Exiting Self Refresh TdkN + Neven2 TdkN1 L CK_c CK_t DRAM internal CLK CKE tCMD_GEAR tSYNC_GEAR tXPR_GEAR 1N sync pulse 2N mode CS_n tGEAR_setup Command tGEAR_hold tGEAR_setup MRS tGEAR_hold NOP Configure DRAM to 1/4 rate Valid Time Break Don’t Care Notes: 1. After tSYNC_GEAR from GEAR-DOWN command, internal clock rate is changed at TdkN. 2. After tSYNC_GEAR + tCMD_GEAR from GEAR-DOWN command, both internal clock rate and command cycle are changed at TdkN + Neven. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 103 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Figure 46: Comparison Between Gear-Down Disable and Gear-Down Enable T0 T1 T2 T3 T15 T16 T17 T18 T19 T30 T31 T32 T33 T34 T35 T36 T37 T38 DES DES DES DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t AL = 0 (geardown = disable) Command ACT DO n DQ tRCD = 16 AL = CL - 1 (geardown = disable) Command ACT READ DO n+ 1 DO n+ 2 DO n+ 3 DO n+ 4 DO n+ 5 DO n+ 6 DO n+ 7 RL =CL= 16 (AL = 0) READ DES DES DES DES DES DES DES DES DES DES DO n DQ DES DO n+ 1 DO n+ 2 DES DO n+ 3 DO n+ 4 DES DO n+ 5 DO n+ 6 DES DO n+ 7 RL = AL + CL = 31 (AL = CL - 1 = 15) READ Command ACT READ DES DES DES DES DO n DQ DES DO n+ 1 DO n+ 2 DO n+ 3 DO n+ 4 DES DO n+ 5 DO n+ 6 DES DO n+ 7 AL + CL = RL = 30 (AL = CL - 2 = 14) Time Break Transitioning Data Don’t Care 104 8Gb: x4, x8, x16 DDR4 SDRAM Gear-Down Mode Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode Maximum Power-Saving Mode Maximum power-saving mode provides the lowest power mode where data retention is not required. When the device is in the maximum power-saving mode, it does not maintain data retention or respond to any external command, except the MAXIMUM POWER SAVING MODE EXIT command ANDDURINGTHEASSERTIONOF2%3%4?NSIGNAL,/74HISMODEISMORELIKEAhHIBERNATEMODEvTHANA typical power-saving mode. The intent is to be able to park the DRAM at a very low-power state; the device can be switched to an active state via the per-DRAM addressability (PDA) mode. Maximum Power-Saving Mode Entry Maximum power-saving mode is entered through an MRS command. For devices with shared control/address signals, a single DRAM device can be entered into the maximum power-saving mode using the per-DRAM addressability MRS command. Large CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result, CA parity, CAL, and gear-down modes must be disabled prior to the maximum power-saving mode entry MRS command. The MRS command may use both address and DQ information, as defined in the Per-DRAM Addressability section. As illustrated in the figure below, after tMPED from the mode entry MRS command, the DRAM is not responsive to any input signals except CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may become High-Z). The system will provide a valid clock until t CKMPE expires, at which time clock inputs (CK) should be disabled (external clock signals may become High-Z). Figure 47: Maximum Power-Saving Mode Entry Ta0 Ta1 Ta2 Tb0 Tb1 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8 Tc9 Tc10 Tc11 CK_c CK_t tCKMPE MR4[A1=1] MPSM Enable) Command DES MRS DES DES DES tMPED Address Valid CS_n CKE CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode RESET_n Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 105 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode Maximum Power-Saving Mode Entry in PDA The sequence and timing required for the maximum power-saving mode with the per-DRAM addressability enabled is illustrated in the figure below. Figure 48: Maximum Power-Saving Mode Entry with PDA Ta0 Ta1 Ta2 Tb0 Tb1 Tb3 Tb4 Tb5 Tb6 Tb7 Tb8 Tb9 Tc0 DES DES DES DES DES DES DES DES DES DES DES Tc1 Tc2 Td0 Td1 Td2 CK_c CK_t MR4[A1 = 1] MPSM Enable) Command DES MRS DES tCKMPE CS_n CKE tMPED AL + CWL DQS_t DQS_c tPDA_S tPDA_H DQ0 RESET_n Time Break Don’t Care CKE Transition During Maximum Power-Saving Mode The following figure shows how to maintain maximum power-saving mode even though the CKE input may toggle. To prevent the device from exiting the mode, CS_n should be HIGH at the CKE LOW-to-HIGH edge, with appropriate setup (tMPX_S) and hold (tMPX_H) timings. Figure 49: Maintaining Maximum Power-Saving Mode with CKE Transition CLK CMD CS_n tMPX_S tMPX_HH CKE RESET_n Don’t Care Maximum Power-Saving Mode Exit To exit the maximum power-saving mode, CS_n should be LOW at the CKE LOW-to-HIGH transition, with appropriate setup (tMPX_S) and hold (tMPX_LH) timings, as shown in the figure below. Because the clock receivers (CK_t, CK_c) are disabled during this mode, CS_n = LOW is captured by the rising edge of the CKE signal. If the CS_n signal level is detected LOW, the DRAM clears the maximum power-saving mode MRS bit and begins the exit procedure from this mode. The external clock must be restarted and be stable by tCKMPX before the device can exit the maximum power-saving mode. During the exit time (tXMP), only NOP and DES commands are allowed: NOP during tMPX_LH and CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Maximum Power-Saving Mode DES the remainder of tXMP. After tXMP expires, valid commands not requiring a locked DLL are allowed; after tXMP_DLL expires, valid commands requiring a locked DLL are allowed. Figure 50: Maximum Power-Saving Mode Exit Ta0 Ta1 Ta2 Ta3 Tb1 Tb0 Tb2 Tb3 Tc0 NOP NOP NOP Tc1 Tc2 Tc4 Td0 Td1 Td2 Td3 Te0 Te1 NOP NOP DES DES DES DES Valid DES DES CK_c CK_t tCKMPX Command tMPX_LH CS_n tMPX_S CKE tXMP tXMP_DLL RESET_n Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 107 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Command/Address Parity Command/address (CA) parity takes the CA parity signal (PAR) input carrying the parity bit for the generated address and commands signals and matches it to the internally generated parity from the captured address and commands signals. CA parity is supported in the DLL enabled state only; if the DLL is disabled, CA parity is not supported. Figure 51: Command/Address Parity Operation DRAM Controller DRAM CMD/ADDR Even parity GEN CMD/ADDR Even parity GEN CMD/ADDR Even parity bit Even parity bit Compare parity bit CA parity is disabled or enabled via an MRS command. If CA parity is enabled by programming a non-zero value to CA parity latency in the MR, the DRAM will ensure that there is no parity error before executing commands. There is an additional delay required for executing the commands versus when parity is disabled. The delay is programmed in the MR when CA parity is enabled (parity latency) and applied to all commands which are registered by CS_n (rising edge of CK_t and falling CS_n). The command is held for the time of the parity latency (PL) before it is executed inside the device. The command captured by the input clock has an internal delay before executing and is determined with PL. ALERT_n will go active when the DRAM detects a CA parity error. CA parity covers ACT_n, RAS_n/A16, CAS_n/A15, WE_n/A14, the address bus including bank address and bank group bits, and C[2:0] on 3DS devices; the control signals CKE, ODT, and CS_n are not covered. For example, for a 4Gb x4 monolithic device, parity is computed across BG[1:0], BA[1:0], A16/RAS_n, A15/CAS_n, A14/ WE_n, A[13:0], and ACT_n. The DRAM treats any unused address pins internally as zeros; for example, if a common die has stacked pins but the device is used in a monolithic application, then the address pins used for stacking and not connected are treated internally as zeros. The convention for parity is even parity; for example, valid parity is defined as an even number of ones across the inputs used for parity computation combined with the parity signal. In other words, the parity bit is chosen so that the total number of ones in the transmitted signal, including the parity bit, is even. If a DRAM device detects a CA parity error in any command qualified by CS_n, it will perform the following steps: 1. Ignore the erroneous command. Commands in the MAX NnCK window (tPAR_UNKNOWN) prior to the erroneous command are not guaranteed to be executed. When a READ command in this NnCK window is not executed, the device does not activate DQS outputs. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. When CA Parity and WRITE CRC are both enabled and a CA Parity occurs, the WRITE CRC Error Status Bit should be reset. 2. Log the error by storing the erroneous command and address bits in the MPR error log. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity 3. Set the parity error status bit in the mode register to 1. The parity error status bit must be set before the ALERT_n signal is released by the DRAM (that is, tPAR_ALERT_ON + tPAR_ALERT_PW (MIN)). 4. Assert the ALERT_n signal to the host (ALERT_n is active LOW) within tPAR_ALERT_ON time. 5. Wait for all in-progress commands to complete. These commands were received tPAR_UNKOWN before the erroneous command. 6. Wait for tRAS (MIN) before closing all the open pages. The DRAM is not executing any commands during the window defined by (tPAR_ALERT_ON + tPAR_ALERT_PW). 7. After tPAR_ALERT_PW (MIN) has been satisfied, the device may de-assert ALERT_n. a) When the device is returned to a known precharged state, ALERT_n is allowed to be de-asserted. 8. After (tPAR_ALERT_PW (MAX)) the DRAM is ready to accept commands for normal operation. Parity latency will be in effect; however, parity checking will not resume until the memory controller has cleared the parity error status bit by writing a zero. The DRAM will execute any erroneous commands until the bit is cleared; unless persistent mode is enabled. s It is possible that the device might have ignored a REFRESH command during tPAR_ALERT_PW or the REFRESH command is the first erroneous frame, so it is recommended that extra REFRESH cycles be issued, as needed. s The parity error status bit may be read anytime after tPAR_ALERT_ON + tPAR_ALERT_PW to determine which DRAM had the error. The device maintains the error log for the first erroneous command until the parity error status bit is reset to a zero or a second CA parity occurs prior to resetting. The mode register for the CA parity error is defined as follows: CA parity latency bits are write only, the parity error status bit is read/write, and error logs are read-only bits. The DRAM controller can only program the parity error status bit to zero. If the DRAM controller illegally attempts to write a 1 to the parity error status bit, the DRAM can not be certain that parity will be checked; the DRAM may opt to block the DRAM controller from writing a 1 to the parity error status bit. The device supports persistent parity error mode. This mode is enabled by setting MR5[9] = 1; when enabled, CA parity resumes checking after the ALERT_n is de-asserted, even if the parity error status bit remains a 1. If multiple errors occur before the error status bit is cleared the error log in MPR Page SHOULDBETREATEDAS$ONT#ARE)NPERSISTENTPARITYERRORMODETHE!,%24?NPULSEWILLBEASSERTED and de-asserted by the DRAM as defined with the MIN and MAX value tPAR_ALERT_PW. The DRAM controller must issue DESELECT commands once it detects the ALERT_n signal, this response time is defined as tPAR_ALERT_RSP. The following figures capture the flow of events on the CA bus and the ALERT_n signal. Table 36: Mode Register Setting for CA Parity CA Parity Latency MR5[2:0]1 Applicable Speed Bin 000 = Disabled N/A 001 = 4 clocks 1600, 1866, 2133 010 = 5 clocks 2400, 2666 011 = 6 clocks 2933, 3200 100 = 8 clocks RFU 101 = Reserved RFU 110 = Reserved RFU 111 = Reserved RFU CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Parity Error Status Parity Persistent Mode MR5 [4] 0 = Clear MR5 [4] 1 = Error 109 MR5 [9] 0 = DisabledMR5 [9] 1 = Enabled Erroneous CA Frame C[2:0], ACT_n, BG1, BG0, BA[1:0], PAR, A17, A16/RAS_n, A15/CAS_n, A14/WE_n, A[13:0] Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Notes: 1. Parity latency is applied to all commands. 2. Parity latency can be changed only from a CA parity disabled state; for example, a direct change from PL = 3 to PL = 4 is not allowed. The correct sequence is PL = 3 to disabled to PL = 4. 3. Parity latency is applied to WRITE and READ latency. WRITE latency = AL + CWL + PL. READ latency = AL + CL + PL. Figure 52: Command/Address Parity During Normal Operation T0 T1 Valid 2 Valid 2 Ta0 Ta1 Ta2 Tb0 Tc0 Tc1 Td0 Valid 2 Error Valid Valid Valid DES2 DES2 Te0 Te1 Valid 3 Valid 3 CK_c CK_t Command/ Address tRP t > 2nCK tPAR_UNKNOWN 2 tPAR_ALERT_ON tPAR_ALERT_PW 1 ALERT_n Valid 2 DES2 Command execution unknown Error Valid Command not executed Valid 3 Don’t Care Time Break Command executed Notes: 1. DRAM is emptying queues. Precharge all and parity checking are off until parity error status bit is cleared. 2. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking is off until parity error status bit is cleared. Figure 53: Persistent CA Parity Error Checking Operation CK_c T0 T1 Valid 2 Valid 2 Ta0 Ta1 Ta2 Tb0 Valid 2 Error Valid Valid Tc0 Tc1 Td0 Te0 Valid DES DES DES Te1 CK_t Command/ Address tPAR_ALERT_RSP tPAR_UNKNOWN 2 tPAR_ALERT_ON t > 2nCK Valid 3 tRP tPAR_ALERT_PW 1 ALERT_n Valid 2 DES Command execution unknown Error Valid Command not executed Valid 3 Don’t Care Command executed Time Break Notes: 1. DRAM is emptying queues. Precharge all and parity check re-enable finished by tPAR_ALERT_PW. 2. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. If WRITE CRC is enabled and a WRITE CRC occurs during the tPAR_UNKNOWN window, the WRITE CRC Error Status Bit located at MR5[3] may or may not get set 3. Normal operation with parity latency and parity checking (CA parity persistent error mode enabled). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Figure 54: #!0ARITY%RROR#HECKINGn32%!TTEMPT T1 T0 CK_c Ta0 Tb0 Ta1 Tb1 Tc0 Td1 Td0 Tc1 Td2 Td3 Te0 Te1 DES5 Valid 3 CK_t tCPDED Command/ Address DES1, 5 tXP + PL DES1 Error2 DES6 tIS + PL DES6 tIS CKE tRP t > 2nCK tIH Note 4 tPAR_ALERT_ON tPAR_ALERT_PW 1 ALERT_n DES1, 5 DES6 Error2 DES1 Valid 3 DES5 Command execution unknown Command not executed Don’t Care Command executed Time Break Notes: 1. Only DESELECT command is allowed. 2. SELF REFRESH command error. The DRAM masks the intended SRE command and enters precharge power-down. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking is off until the parity error status bit cleared. 4. The controller cannot disable the clock until it has been capable of detecting a possible CA parity error. 5. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. 6. Only a DESELECT command is allowed; CKE may go HIGH prior to Tc2 as long as DES commands are issued. Figure 55: #!0ARITY%RROR#HECKINGn328!TTEMPT T0 Ta0 SRX1 DES Ta1 Tb0 Tb1 Tc0 Tc1 Tc2 Td0 Td1 Te0 Tf0 Error2 Valid 2 Valid 2 Valid 2 DES2, 3 DES2, 3 Valid 2, 4, 5 Valid 2, 4, 6 Valid 2, 4, 7 CK_c CK_t Command/ Address DES t > 2nCK tIS tRP CKE tPAR_UNKNOWN tPAR_ALERT_ON tPAR_ALERT_PW ALERT_n tXS_FAST 8 tXS tXSDLL SRX1 DES Error Valid Valid 4,5,6,7 Valid 3, 5 Command execution unknown Command not executed Time Break Don’t Care Command executed Notes: 1. Self refresh abort = disable: MR4 [9] = 0. 2. Input commands are bounded by tXSDLL, tXS, tXS_ABORT, and tXS_FAST timing. 3. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. 4. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking off until parity error status bit cleared. 5. Only an MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL command is allowed. 6. Valid commands not requiring a locked DLL. 7. Valid commands requiring a locked DLL. 8. This figure shows the case from which the error occurred after tXS_FAST. An error may also occur after tXS_ABORT and tXS. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 111 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Figure 56: #!0ARITY%RROR#HECKINGn0$%0$8 T1 T0 CK_c Ta0 Tb0 Ta1 Tb1 Tc0 Td1 Td0 Tc1 Td2 Td3 Te0 Te1 DES4 Valid 3 CK_t tCPDED Command/ Address DES1 Error2 tXP + PL DES1 DES5 tIS + PL DES5 tIS CKE t > 2nCK tIH tRP tPAR_ALERT_PW 1 tPAR_ALERT_ON ALERT_n DES4 DES5 Command execution unknown Error2 DES1 Command not executed Valid 3 Don’t Care Command executed Time Break Notes: 1. Only DESELECT command is allowed. 2. Error could be precharge or activate. 3. Normal operation with parity latency (CA parity persistent error mode disabled). Parity checking is off until parity error status bit cleared. 4. Command execution is unknown; the corresponding DRAM internal state change may or may not occur. The DRAM controller should consider both cases and make sure that the command sequence meets the specifications. 5. Only a DESELECT command is allowed; CKE may go HIGH prior to Td2 as long as DES commands are issued. Figure 57: 0ARITY%NTRY4IMING%XAMPLEntMRD_PAR Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 DES MRS DES DES MRS DES CK_c CK_t Command Parity latency PL = 0 Updating setting PL = N tMRD_PAR Enable parity Don’t Care Time Break Note: 1. tMRD_PAR = tMOD + N; where N is the programmed parity latency. Figure 58: 0ARITY%NTRY4IMING%XAMPLEntMOD_PAR Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 DES MRS DES DES Valid DES CK_c CK_t Command Parity latency PL = 0 Updating setting PL = N tMOD_PAR Enable parity Time Break Note: 1. Don’t Care t MOD_PAR = tMOD + N; where N is the programmed parity latency. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Figure 59: 0ARITY%XIT4IMING%XAMPLEntMRD_PAR Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 DES MRS DES DES MRS DES CK_c CK_t Command Parity latency PL = N Updating setting tMRD_PAR Disable parity Time Break Note: 1. Don’t Care t MRD_PAR = tMOD + N; where N is the programmed parity latency. Figure 60: 0ARITY%XIT4IMING%XAMPLEntMOD_PAR Ta0 Ta1 Ta2 Tb0 Tb1 Tb2 DES MRS DES DES Valid DES CK_c CK_t Command Parity latency PL = N Updating setting tMOD_PAR Disable parity Time Break Note: 1. Don’t Care t MOD_PAR = tMOD + N; where N is the programmed parity latency. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Figure 61: CA Parity Flow Diagram CA process start MR5[2:0] set parity latency (PL) MR5[4] set parity error status to 0 MR5[9] enable/disable persistent mode CA latched in Yes CA parity enabled Persistent mode enabled Yes CA parity error No No No MR5[4] = 0 @ ADDR/CMD latched No Yes Yes CA parity error Good CA processed Yes Ignore bad CMD Command execution unknown No Good CA processed Ignore bad CMD Command execution unknown ALERT_n LOW 44 to 144 CKs MR5[4] = 0 Yes @ ADDR/CMD latched Log error/ set parity status No Yes CA error ALERT_n LOW 44 to 144 CKs Log error/ set parity status Internal precharge all Internal precharge all ALERT_n HIGH ALERT_n HIGH Command execution unknown No 114 Good CA processed Operation ready? Command execution unknown Normal operation ready MR5[4] reset to 0 if desired Normal operation ready MR5[4] reset to 0 if desired 8Gb: x4, x8, x16 DDR4 SDRAM Command/Address Parity Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. Normal operation ready Bad CA processed 8Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability Per-DRAM Addressability DDR4 allows programmability of a single, specific DRAM on a rank. As an example, this feature can be used to program different ODT or VREF values on each DRAM on a given rank. Because per-DRAM addressability (PDA) mode may be used to program optimal VREF for the DRAM, the data set up for first DQ0 transfer or the hold time for the last DQ0 transfer cannot be guaranteed. The DRAM may sample DQ0 on either the first falling or second rising DQS transfer edge. This supports a common implementation between BC4 and BL8 modes on the DRAM. The DRAM controller is required to drive DQ0 to a stable LOW or HIGH state during the length of the data transfer for BC4 and BL8 cases. Note, both fixed and on-the-fly (OTF) modes are supported for BC4 and BL8 during PDA mode. 1. Before entering PDA mode, write leveling is required. n BL8 or BC4 may be used. 2. Before entering PDA mode, the following MR settings are possible: n RTT(Park) MR5 A[8:6] = Enable n RTT(NOM) MR1 A[10:8] = Enable 3. Enable PDA mode using MR3 [4] = 1. (The default programed value of MR3[4] = 0.) 4. In PDA mode, all MRS commands are qualified with DQ0. The device captures DQ0 by using DQS signals. If the value on DQ0 is LOW, the DRAM executes the MRS command. If the value on DQ0 is HIGH, the DRAM ignores the MRS command. The controller can choose to drive all the DQ bits. 5. Program the desired DRAM and mode registers using the MRS command and DQ0. 6. In PDA mode, only MRS commands are allowed. 7. The MODE REGISTER SET command cycle time in PDA mode, AL + CWL + BL/2 - 0.5tCK + t MRD_PDA + PL, is required to complete the WRITE operation to the mode register and is the minimum time required between two MRS commands. 8. Remove the device from PDA mode by setting MR3[4] = 0. (This command requires DQ0 = 0.) Note: Removing the device from PDA mode will require programming the entire MR3 when the MRS command is issued. This may impact some PDA values programmed within a rank as the EXIT command is sent to the rank. To avoid such a case, the PDA enable/disable control bit is located in a mode register that does not have any PDA mode controls. In PDA mode, the device captures DQ0 using DQS signals the same as in a normal WRITE operation; however, dynamic ODT is not supported. Extra care is required for the ODT setting. If RTT(NOM) MR1 [10:8] = enable, device data termination needs to be controlled by the ODT pin, and applies the same timing parameters (defined below). Symbol Parameter DODTLon Direct ODT turnon latency DODTLoff Direct ODT turn off latency t RTT change timing skew t Asynchronous RTT(NOM) turn-on delay t Asynchronous RTT(NOM) turn-off delay ADC AONAS AOFAS CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 115 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability Figure 62: PDA Operation Enabled, BL8 CK_c CK_t MR3 A4 = 1 (PDA enable) MRS MRS t MOD MRS t MRD_PDA CWL+AL+PL DQS_t DQS_c DQ0 t PDA_S t PDA_H DODTLoff = WL-3 ODT DODTLon = WL-3 RTT RTT(Park) RTT(NOM) RTT(Park) Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On. Figure 63: PDA Operation Enabled, BC4 CK_c CK_t MR3 A4 = 1 (PDA enable) MRS MRS MRS tMOD tMRD_PDA CWL+AL+PL DQS_t DQS_c DQ0 tPDA_S tPDA_H DODTLoff = WL-3 ODT DODTLon = WL-3 RTT RTT(Park) RTT(NOM) RTT(Park) Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Per-DRAM Addressability Figure 64: MRS PDA Exit CK_c CK_t MR3 A4 = 0 (PDA disable) MRS Valid CWL+AL+PL t MOD_PDA DQS_t DQS_c DQ0 t PDA_S t PDA_H DODTLoff = WL - 3 ODT DODTLon = WL - 3 RTT RTT(Park) RTT(NOM) RTT(Park) Note: 1. RTT(Park) = Enable; RTT(NOM) = Enable; WRITE preamble set = 2tCK; and DLL = On. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration VREFDQ Calibration The VREFDQ level, which is used by the DRAM DQ input receivers, is internally generated. The DRAM VREFDQ does not have a default value upon power-up and must be set to the desired value, usually via VREFDQ calibration mode. If PDA or PPR modes (hPPR or sPPR) are used prior to VREFDQ calibration, VREFDQ should initially be set at the midpoint between the VDD,max, and the LOW as determined by the driver and ODT termination selected with wide voltage swing on the input levels and setup and hold times of approximately 0.75UI. The memory controller is responsible for VREFDQ calibration to determine the best internal VREFDQ level. The VREFDQ calibration is enabled/disabled via MR6[7], MR6[6] selects Range 1 (60% to 92.5% of VDDQ) or Range 2 (45% to 77.5% of VDDQ), and an MRS protocol using MR6[5:0] to adjust the VREFDQ level up and down. MR6[6:0] bits can be altered using the MRS command if MR6[7] is enabled. The DRAM controller will likely use a series of writes and reads in conjunction with VREFDQ adjustments to obtain the best VREFDQ, which in turn optimizes the data eye. The internal VREFDQ specification parameters are voltage range, step size, VREF step time, VREF full step time, and VREF valid level. The voltage operating range specifies the minimum required VREF setting range for DDR4 SDRAM devices. The minimum range is defined by VREFDQ,min and VREFDQ,max. As noted, a calibration sequence, determined by the DRAM controller, should be performed to adjust VREFDQand optimize the timing and voltage margin of the DRAM data input receivers. The internal VREFDQ voltage value may not be exactly within the voltage range setting coupled with the VREF set tolerance; the device must be calibrated to the correct internal VREFDQ voltage. Figure 65: VREFDQ Voltage Range VDDQ VREF,max VREF range VREF,min CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 118 VSWING small System variance VSWING large Total range Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration VREFDQ Range and Levels Table 37: VREFDQ Range and Levels MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1 MR6[5:0] Range 1 MR6[6] 0 Range 2 MR6[6] 1 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% 11 0011 to 11 1111 = Reserved VREFDQ Step Size The VREF step size is defined as the step size between adjacent steps. VREF step size ranges from 0.5% VDDQ to 0.8% VDDQ. However, for a given design, the device has one value for VREF step size that falls within the range. The VREF set tolerance is the variation in the VREF voltage from the ideal setting. This accounts for accumulated error over multiple steps. There are two ranges for VREF set tolerance uncertainty. The range of VREF set tolerance uncertainty is a function of number of steps n. The VREF set tolerance is measured with respect to the ideal line, which is based on the MIN and MAX VREF value endpoints for a specified range. The internal VREFDQ voltage value may not be exactly within CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration the voltage range setting coupled with the VREF set tolerance; the device must be calibrated to the correct internal VREFDQ voltage. Figure 66: Example of VREF Set Tolerance and Step Size Actual VREF output Straight line (endpoint fit) VREF VREF set tolerance VREF set tolerance VREF step size Digital Code Note: 1. Maximum case shown. VREFDQ Increment and Decrement Timing The VREF increment/decrement step times are defined by VREF,time. VREF,time is defined from t0 to t1, where t1 is referenced to the VREF voltage at the final DC level within the VREF valid tolerance (VREF,val_tol). The VREF valid level is defined by VREF,val tolerance to qualify the step time t1. This parameter is used to insure an adequate RC time constant behavior of the voltage level change after any VREF increment/decrement adjustment. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration Figure 67: VREFDQ Timing Diagram for VREF,time Parameter CK_c CK_t MRS Command VREF setting adjustment DQ VREF Old VREF setting Updating VREF setting New VREF setting VREF_time t0 t1 Don’t Care Note: 1. t0 is referenced to the MRS command clock t1 is referenced to VREF,tol VREFDQ calibration mode is entered via an MRS command, setting MR6[7] to 1 (0 disables VREFDQ calibration mode) and setting MR6[6] to either 0 or 1 to select the desired range (MR6[5:0] are "Don't Care"). After VREFDQ calibration mode has been entered, VREFDQ calibration mode legal commands may be issued once tVREFDQE has been satisfied. Legal commands for VREFDQ calibration mode are ACT, WR, WRA, RD, RDA, PRE, DES, and MRS to set VREFDQ values, and MRS to exit VREFDQ calibration mode. Also, after VREFDQCALIBRATIONMODEHASBEENENTEREDhDUMMYv72)4%COMMANDSAREALLOWED prior to adjusting the VREFDQ value the first time VREFDQ calibration is performed after initialization. Setting VREFDQ values requires MR6[7] be set to 1 and MR6[6] be unchanged from the initial range selection; MR6[5:0] may be set to the desired VREFDQ values. If MR6[7] is set to 0, MR6[6:0] are not written. VREF,time-short or VREF,time-long must be satisfied after each MR6 command to set VREFDQ value before the internal VREFDQ value is valid. If PDA mode is used in conjunction with VREFDQ calibration, the PDA mode requirement that only MRS commands are allowed while PDA mode is enabled is not waived. That is, the only VREFDQ calibration mode legal commands noted above that may be used are the MRS commands: MRS to set VREFDQ values and MRS to exit VREFDQ calibration mode. The last MR6[6:0] setting written to MR6 prior to exiting VREFDQ calibration mode is the range and value used for the internal VREFDQ setting. VREFDQ calibration mode may be exited when the DRAM is in idle state. After the MRS command to exit VREFDQ calibration mode has been issued, DES must be issued until tVREFDQX has been satisfied where any legal command may then be issued. VREFDQ setting should be updated if the die temperature changes too much from the calibration temperature. The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 1: s MR6[7:6]10 [5:0]XXXXXXX. n Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode). s All subsequent VREFDQ calibration MR setting commands are MR6[7:6]10 [5:0]VVVVVV. n "VVVVVV" are desired settings for VREFDQ. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration s Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed. s To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are: n MR6[7:6]10 [5:0]VVVVVV* where VVVVVV* = desired value for VREFDQ. n MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode. The following are typical script when applying the above rules for VREFDQ calibration routine when performing VREFDQ calibration in Range 2: s MR6[7:6]11 [5:0]XXXXXXX. n Subsequent legal commands while in VREFDQ calibration mode: ACT, WR, WRA, RD, RDA, PRE, DES, and MRS (to set VREFDQ values and exit VREFDQ calibration mode). s All subsequent VREFDQ calibration MR setting commands are MR6[7:6]11 [5:0]VVVVVV. n "VVVVVV" are desired settings for VREFDQ. s Issue ACT/WR/RD looking for pass/fail to determine VCENT (midpoint) as needed. s To exit VREFDQ calibration, the last two VREFDQ calibration MR commands are: n MR6[7:6]11 [5:0]VVVVVV* where VVVVVV* = desired value for VREFDQ. n MR6[7]0 [6:0]XXXXXXX to exit VREFDQ calibration mode. Note: Range may only be set or changed when entering VREFDQ calibration mode; changing range while in or exiting VREFDQ calibration mode is illegal. Figure 68: VREFDQ Training Mode Entry and Exit Timing Diagram T0 T1 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 DES MRS DES CMD DES CMD DES MRS1,2 Td0 Td1 Td2 DES WR DES CK_c CK_t Command tVREFDQE VREFDQ training on tVREFDQX New VREFDQ value or write New VREFDQ value or write VREFDQ training off Don’t Care Notes: 1. New VREFDQ values are not allowed with an MRS command during calibration mode entry. 2. Depending on the step size of the latest programmed VREF value, VREF must be satisfied before disabling VREFDQ training mode. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration Figure 69: VREF Step: Single Step Size Increment Case VREF Voltage VREF (VDDQ(DC)) VREF,val_tol Step size t1 Time Figure 70: VREF Step: Single Step Size Decrement Case VREF Voltage t1 Step size VREF,val_tol VREF (VDDQ(DC)) Time CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration Figure 71: VREF Full Step: From VREF,min to VREF,maxCase VREF Voltage VREF,max VREF,val_tol Full range step VREF (VDDQ(DC)) t1 VREF,min Time Figure 72: VREF Full Step: From VREF,max to VREF,minCase VREF Voltage VREF,max Full range step t1 VREF,val_tol VREF,min VREF (VDDQ(DC)) Time VREFDQ Target Settings The VREFDQ initial settings are largely dependant on the ODT termination settings. The table below shows all of the possible initial settings available for VREFDQ training; it is unlikely the lower ODT settings would be used in most cases. Table 38: VREFDQ Settings (VDDQ = 1.2V) RON 34 ohm ODT 6Xn6IN LOW (mV) VREFDQ (mv) VREFDQ (%VDDQ) 34 ohm 600 900 75% 40 ohm 550 875 73% 48 ohm 500 850 71% 60 ohm 435 815 68% 80 ohm 360 780 65% 120 ohm 265 732 61% 240 ohm 150 675 56% CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 124 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM VREFDQ Calibration Table 38: VREFDQ Settings (VDDQ = 1.2V) RON 48 ohm ODT 6Xn6IN LOW (mV) VREFDQ (mv) VREFDQ (%VDDQ) 34 ohm 700 950 79% 40 ohm 655 925 77% 48 ohm 600 900 75% 60 ohm 535 865 72% 80 ohm 450 825 69% 120 ohm 345 770 64% 240 ohm 200 700 58% Figure 73: VREFDQ Equivalent Circuit VDDQ VDDQ ODT RXer Vx VREFDQ (internal) RON CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode Connectivity Test Mode Connectivity test (CT) mode is similar to boundary scan testing but is designed to significantly speed up the testing of electrical continuity of pin interconnections between the device and the memory controller on the PC boards. Designed to work seamlessly with any boundary scan device, CT mode is supported in all έ4, έ8, and έ16 non-3DS devices (JEDEC states CT mode for έ4 and έ8 is not required on 4Gb and is an optional feature on 8Gb and above). 3DS devices do not support CT mode and the TEN pin should be considered RFU maintained LOW at all times. Contrary to other conventional shift-register-based test modes, where test patterns are shifted in and out of the memory devices serially during each clock, the CT mode allows test patterns to be entered on the test input pins in parallel and the test results to be extracted from the test output pins of the device in parallel. These two functions are also performed at the same time, significantly increasing the speed of the connectivity check. When placed in CT mode, the device appears as an asynchronous device to the external controlling agent. After the input test pattern is applied, the connectivity test results are available for extraction in parallel at the test output pins after a fixed propagation delay time. Note: A reset of the device is required after exiting CT mode (see RESET and Initialization Procedure). Pin Mapping Only digital pins can be tested using the CT mode. For the purposes of a connectivity check, all the pins used for digital logic in the device are classified as one of the following types: s Test enable (TEN): When asserted HIGH, this pin causes the device to enter CT mode. In CT mode, the normal memory function inside the device is bypassed and the I/O pins appear as a set of test input and output pins to the external controlling agent. Additionally, the device will set the internal VREFDQ to VDDQ έ 0.5 during CT mode (this is the only time the DRAM takes direct control over setting the internal VREFDQ). The TEN pin is dedicated to the connectivity check function and will not be used during normal device operation. s Chip select (CS_n): When asserted LOW, this pin enables the test output pins in the device. When de-asserted, these output pins will be High-Z. The CS_n pin in the device serves as the CS_n pin in CT mode. s Test input: A group of pins used during normal device operation designated as test input pins. These pins are used to enter the test pattern in CT mode. s Test output: A group of pins used during normal device operation designated as test output pins. These pins are used for extraction of the connectivity test results in CT mode. s RESET_n: This pin must be fixed high level during CT mode, as in normal function. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 126 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode Table 39: Connectivity Mode Pin Description and Switching Levels CT Mode Pins Pin Name During Normal Memory Operation Switching Level Test enable TEN CMOS (20%/80% VDD) Chip select CS_n VREFCA ά200mV 3 A BA[1:0], BG[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14, CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_c, PAR VREFCA ά200mV 3 B LDM_n/LDBI_n, UDM_n/UDBI_n; DM_n/DBI_n VREFDQ ά200mV 4 Test input Test output Notes 1, 2 C ALERT_n CMOS (20%/80% VDD) 2, 5 D RESET_n CMOS (20%/80% VDD) 2 VTT ά100mV 6 DQ[15:0], UDQS_t, UDQS_c, LDQS_t, LDQS_c; DQS_t, DQS_c Notes: 1. TEN: Connectivity test mode is active when TEN is HIGH and inactive when TEN is LOW. TEN must be LOW during normal operation. 2. CMOS is a rail-to-rail signal with DC HIGH at 80% and DC LOW at 20% of VDD (960mV for DC HIGH and 240mV for DC LOW.) 3. VREFCA should be VDD/2. 4. VREFDQ should be VDDQ/2. 5. ALERT_n switching level is not a final setting. 6. VTT should be set to VDD/2. Minimum Terms Definition for Logic Equations The test input and output pins are related by the following equations, where INV denotes a logical inversion operation and XOR a logical exclusive OR operation: MT0 = XOR (A1, A6, PAR) MT1 = XOR (A8, ALERT_n, A9) MT2 = XOR (A2, A5, A13) or XOR (A2, A5, A13, A17) MT3 = XOR (A0, A7, A11) MT4 = XOR (CK_c, ODT, CAS_n/A15) MT5 = XOR (CKE, RAS_n/A16, A10/AP) MT6 = XOR (ACT_n, A4, BA1) MT7 = έ16: XOR (DMU_n/DBIU_n, DML_n/DBIL_n, CK_t) = x8: XOR (BG1, DML_n/DBIL_n, CK_t) = x4: XOR (BG1, CK_t) MT8 = XOR (WE_n/A14, A12 / BC, BA0) MT9 = XOR (BG0, A3, RESET_n and TEN) Logic Equations for a x4 Device DQ0 = XOR (MT0, MT1) DQ1 = XOR (MT2, MT3) DQ2 = XOR (MT4, MT5) DQ3 = XOR (MT6, MT7) DQS_t = MT8 DQS_c = MT9 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 127 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode Logic Equations for a x8 Device DQ0 = MT0 DQ1 = MT1 DQ2 = MT2 DQ3 = MT3 DQ4 = MT4 DQ5 = MT5 DQ6 = MT6 DQ7 = MT7 DQS_t = MT8 DQS_c = MT9 Logic Equations for a x16 Device DQ0 = MT0 DQ1 = MT1 DQ2 = MT2 DQ3 = MT3 DQ4 = MT4 DQ5 = MT5 DQ6 = MT6 DQ7 = MT7 DQ8 = INV DQ0 DQ9 = INV DQ1 DQ10 = INV DQ2 DQ11 = INV DQ3 DQ12 = INV DQ4 DQ13 = INV DQ5 DQ14 = INV DQ6 DQ15 = INV DQ7 LDQS_t = MT8 LDQS_c = MT9 UDQS_t = INV LDQS_t UDQS_c = INV LDQS_c CT Input Timing Requirements Prior to the assertion of the TEN pin, all voltage supplies, including VREFCA, must be valid and stable and RESET_n registered high prior to entering CT mode. Upon the assertion of the TEN pin HIGH with RESET_n, CKE, and CS_n held HIGH; CLK_t, CLK_c, and CKE signals become test inputs within tCTECT_Valid. The remaining CT inputs become valid tCT_Enable after TEN goes HIGH when CS_n allows input to begin sampling, provided inputs were valid for at least tCT_Valid. While in CT mode, refresh activities in the memory arrays are not allowed; they are initiated either externally (auto refresh) or internally (self refresh). The TEN pin may be asserted after the DRAM has completed power-on. After the DRAM is initialized and VREFDQ is calibrated, CT mode may no longer be used. The TEN pin may be de-asserted at any time in CT mode. Upon exiting CT mode, the states and the integrity of the original content of the memory array are unknown. A full reset of the memory device is required. After CT mode has been entered, the output signals will be stable within tCT_Valid after the test inputs have been applied as long as TEN is maintained HIGH and CS_n is maintained LOW. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 128 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Connectivity Test Mode Figure 74: Connectivity Test Mode Entry Ta Tb Tc Td CK_t Valid input CK_c tCKSRX tCT_IS tIS T = 10ns Valid input tCT_IS CKE Valid input Valid input tCTCKE_Valid T = 200μs T = 500μs RESET_n tCT_IS TEN tCTCKE_Valid>10ns tCT_Enable tCT_IS >0ns CS_n tCT_IS CT Inputs Valid input Valid input tCT_Valid tCT_Valid tCT_Valid CT Outputs Valid Valid Don’t Care CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 129 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Excessive Row Activation Excessive Row Activation Rows can be accessed a limited number of times within a certain time period before adjacent rows require refresh. The maximum activate count (MAC) is the maximum number of activates that a single row can sustain within a time interval of equal to or less than the maximum activate window (tMAW) before the adjacent rows need to be refreshed, regardless of how the activates are distributed over t MAW. Micron's DDR4 devices automatically perform a type of TRR mode in the background and provide an MPR Page 3 MPR3[3:0] of 1000, indicating there is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM timing specifications are not violated. However, specific attempts to by-pass TRR may result in data disturb. Table 40: MAC Encoding of MPR Page 3 MPR3 [7] [6] [5] [4] [3] [2] [1] [0] MAC Comments x x x x 0 0 0 0 Untested The device has not been tested for MAC. x x x x 0 0 0 1 t x x x x 0 0 1 0 t x x x x 0 0 1 1 t x x x x 0 1 0 0 t x x x x 0 1 0 1 t x x x x 0 1 1 0 x x x x 0 1 1 1 x x x x 1 0 0 0 Unlimited x x x x 1 0 0 1 Reserved x x x x : : : : Reserved x x x x 1 1 1 1 Reserved MAC = 700K MAC = 600K MAC = 500K MAC = 400K MAC = 300K Reserved t MAC = 200K There is no restriction to the number of ACTIVATE commands to a given row in a refresh period provided DRAM timing specifications are not violated. Notes: 1. MAC encoding in MPR Page 3 MPR3. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 130 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Post Package Repair Post Package Repair Post Package Repair JEDEC defines two modes of Post Package Repair (PPR): soft Post Package Repair (sPPR) and hard Post Package Repair (hPPR). sPPR is non-persistent so the repair row maybe altered; that is, sPPR is NOT a permanent repair and even though it will repair a row, the repair can be reversed, reassigned via another sPPR, or made permanent via hPPR. Hard Post Package Repair is persistent so once the repair row is assigned for a hPPR address, further PPR commands to a previous hPPR section should not be performed, that is, hPPR is a permanent repair; once repaired, it cannot be reversed. The controller provides the failing row address in the hPPR/sPPR sequence to the device to perform the row repair. hPPR Mode and sPPR Mode may not be enabled at the same time. JEDEC states hPPR is optional for 4Gb and sPPR is optional for 4Gb and 8Gb parts however Micron 4Gb and 8Gb DDR4 DRAMs should have both sPPR and hPPR support. The hPPR support is identified via an MPR read from MPR Page 2, MPR0[7] and sPPR support is identified via an MPR read from MPR Page 2, MPR0[6]. The JEDEC minimum support requirement for DDR4 PPR (hPPR or sPPR) is to provide one row of repair per bank group (BG), x4/x8 have 4 BG and x16 has 2 BG; this is a total of 4 repair rows available on x4/x8 and 2 repair rows available on x16. Micron PPR support exceeds the JEDEC minimum requirements; Micron DDR4 DRAMs have at least one row of repair for each bank which is essentially 4 row repairs per BG for a total of 16 repair rows for x4 and x8 and 8 repair rows for x16; a 4x increase in repair rows. JEDEC requires the user to have all sPPR row repair addresses reset and cleared prior to enabling hPPR Mode. Micron DDR4 PPR does not have this restriction, the existing sPPR row repair addresses are not required to be cleared prior to entering hPPR mode. Each bank in a BG is PPR independent: sPPR or hPPR issued to a bank will not alter a sPPR row repair existing in a different bank. sPPR followed by sPPR to same bank When PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent sPPR is issued to the same bank, the previous sPPR repair row will be cleared and used for the subsequent sPPR address as the sPPR operation is non-persistent. sPPR followed by hPPR to same bank When a PPR is issued to a bank for the first time and is a sPPR command, the repair row will be a sPPR. When a subsequent hPPR is issued to the same bank, the initial sPPR repair row will be cleared and used for the hPPR address1. If a further subsequent PPR (hPPR or sPPR) is issued to the same bank, the further subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the previous hPPR address as the hPPR operation is persistent. hPPR followed by hPPR or sPPR to same bank When a PPR is issued to a bank for the first time and is a hPPR command, the repair row will be a hPPR. When a subsequent PPR (hPPR or sPPR) is issued to the same bank, the subsequent PPR ( hPPR or sPPR) repair row will not clear or overwrite the initial hPPR address as the initial hPPR is persistent. Note: Newer Micron DDR4 designs may not guarantee that an sPPR followed by an hPPR to the same bank will result the same repair row being used. Contact factory for more information. Hard Post Package Repair All banks must be precharged and idle. DBI and CRC modes must be disabled. Both sPPR and hPPR must be disabled. sPPR is disabled with MR4[5] = 0. hPPR is disabled with MR4[13] = 0, which is the CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 131 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair normal state, and hPPR is enabled with MR4 [13]= 1, which is the hPPR enabled state. There are two forms of hPPR mode. Both forms of hPPR have the same entry requirement as defined in the sections below. The first command sequence uses a WRA command and supports data retention with a REFRESH operation except for the bank containing the row that is being repaired; JEDEC has relaxed this requirement and allows BA[0] to be a Don't Care regarding the banks which are not required to maintain data a REFRESH operation during hPPR. The second command sequence uses a WR command (a REFRESH operation can't be performed in this command sequence). The second command sequence doesn't support data retention for the target DRAM. hPPR Row Repair - Entry As stated above, all banks must be precharged and idle. DBI and CRC modes must be disabled, and all timings must be followed as shown in the timing diagram that follows. All other commands except those listed in the following sequences are illegal. 1. Issue MR4[13] 1 to enter hPPR mode enable. a) All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. The PPR guard key settings are the same whether performing sPPR or hPPR mode. a) Any interruption of the key sequence by other commands, such as ACT, WR, RD, PRE, REF, ZQ, and NOP, are not allowed. b) If the guard key bits are not entered in the required order or interrupted with other MR commands, hPPR will not be enabled, and the programming cycle will result in a NOP. c) When the hPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM commands. d) JEDEC allows A6:0 to be Don't Care on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet. Table 41: PPR MR0 Guard Key Settings MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0 First guard key 0 0 xxxxxx 1 1 0 0 1 1111111 Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 Third Guard key 0 0 xxxxxx 1 0 1 1 1 1111111 Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 H0022OW2EPAIRn72!)NITIATED2%&#OMMANDS!LLOWED 1. Issue an ACT command with failing BG and BA with the row address to be repaired. 2. Issue a WRA command with BG and BA of failing row address. a) The address must be at valid levels, but the address is Don't Care. 3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair. a) Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. The bank under repair does not get the REFRESH command applied to it. b) Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. i) JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than 2tCK, then DRAM does not conduct hPPR CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 132 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than 2tCK, then hPPR mode execution is unknown. c) DQS should function normally. 4. REF command may be issued anytime after the WRA command followed by WL + 4nCK + tWR + tRP. a) Multiple REF commands are issued at a rate of tREFI or tREFI/2, however back-to-back REF commands must be separated by at least tREFI/4 when the DRAM is in hPPR mode. b) All banks except the bank under repair will perform refresh. 5. Issue PRE after tPGM time so that the device can repair the target row during tPGM time. a) Wait tPGM_Exit after PRE to allow the device to recognize the repaired target row address. 6. Issue MR4[13] 0 command to hPPR mode disable. a) Wait tPGMPST for hPPR mode exit to complete. b) After tPGMPST has expired, any valid command may be issued. The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done. After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed. After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. Figure 75: H00272!n%NTRY T0 T1 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Td0 CMD MRS4 DES MRS0 DES MRS0 DES MRS0 DES MRS0 BG Valid N/A 00 N/A 00 N/A 00 N/A 00 Td1 Te0 Tf0 Tg0 DES ACT WRA DES N/A BGf BGf N/A CK_c CK_t BA Valid N/A 00 N/A 00 N/A 00 N/A 00 N/A BAf BAf N/A ADDR Valid (A13=1) N/A 1st Key N/A 2nd Key N/A 3rd Key N/A 4th Key N/A Valid Valid N/A CKE DQS_t DQS_c DQs1 All Banks Precharged and idle state Normal Mode t MOD t MOD t MOD t MOD t MOD hPPR Entry 1st Guard Key Validate 2nd Guard Key Validate 3rd Guard Key Validate 4th Guard Key Validate t RCD hPPR Repair Don’t Care CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 133 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Hard Post Package Repair Figure 76: H00272!n2EPAIRAND%XIT Te0 Tf0 CMD ACT BG BGf BA ADDR CK_c Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 WRA DES DES DES BGf N/A N/A N/A BAf BAf N/A N/A Valid Valid N/A N/A Tk0 DES DES REF/DES REF/DES PRE N/A N/A N/A N/A Valid N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Tk1 Tm0 Tm1 Tn0 REF/DES MRSx DES Valid N/A Valid N/A Valid Valid N/A Valid N/A Valid Valid N/A Valid (A13 = 0) N/A Valid CK_t CKE WL = CWL+AL+PL tWR +tRP + 1nCK 4nCK DQS_t DQS_c DQs1 bit 0 All Banks Precharged and idle state bit 1 bit 6 bit 7 tPGM tRCD hPPR Repair tPGM_Exit hPPR Repair hPPR Repair hPPR Recognition tPGMPST Normal mode hPPR Exit Don’t Care H0022OW2EPAIRn72)NITIATED2%&#OMMANDS./4!LLOWED 1. Issue an ACT command with failing BG and BA with the row address to be repaired. 2. Issue a WR command with BG and BA of failing row address. a) The address must be at valid levels, but the address is Don't Care. 3. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for hPPR to initiate repair. a) Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. b) Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. i) JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than 2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than 2tCK, then hPPR mode execution is unknown. c) DQS should function normally. 4. REF commands may NOT be issued at anytime while in PPT mode. 5. Issue PRE after tPGM time so that the device can repair the target row during tPGM time. a) Wait tPGM_Exit after PRE to allow the device to recognize the repaired target row address. 6. Issue MR4[13] 0 command to hPPR mode disable. a) Wait tPGMPST for hPPR mode exit to complete. b) After tPGMPST has expired, any valid command may be issued. The entire sequence from hPPR mode enable through hPPR mode disable may be repeated if more than one repair is to be done. After completing hPPR mode, MR0 must be re-programmed to a prehPPR mode state if the device is to be accessed. After hPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 134 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM sPPR Row Repair Figure 77: H00272n%NTRY T0 T1 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Td0 CMD MRS4 DES MRS0 DES MRS0 DES MRS0 DES MRS0 BG Valid N/A 00 N/A 00 N/A 00 N/A 00 Td1 Te0 Tf0 Tg0 DES ACT WR DES N/A BGf BGf N/A CK_c CK_t BA Valid N/A 00 N/A 00 N/A 00 N/A 00 N/A BAf BAf N/A ADDR Valid (A13 = 1) N/A 1st Key N/A 2nd Key N/A 3rd Key N/A 4th Key N/A Valid Valid N/A CKE WL = CWL + DQS_t DQS_c DQs1 Normal Mode t RCD t MOD t MOD t MOD t MOD t MOD hPPR Entry 1st Guard Key Validate 2nd Guard Key Validate 3rd Guard Key Validate 4th Guard Key Validate All Banks Precharged and idle state hPPR Repair Don’t Care Figure 78: H00272n2EPAIRAND%XIT Te0 Tf0 CMD ACT BG BGf BA ADDR CK_c Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 WR DES DES DES BGf N/A N/A N/A BAf BAf N/A N/A Valid Valid N/A N/A Tk0 DES DES DES DES PRE N/A N/A N/A N/A Valid N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A Tk1 Tm0 Tm1 Tn0 DES MRSx DES Valid N/A Valid N/A Valid Valid N/A Valid N/A Valid Valid N/A Valid (A13 = 0) N/A Valid CK_t CKE WL = CWL + AL + PL 4nCK DQS_t DQS_c DQs1 bit 0 All Banks Precharged and idle state bit 1 bit 6 bit 7 tPGM tRCD hPPR Repair tPGM_Exit hPPR Repair tPGMPST hPPR Recognition hPPR Repair Normal mode hPPR Exit Don’t Care Table 42: DDR4 hPPR Timing Parameters DDR4-1600 through DDR4-3200 Parameter Symbol hPPR programming time t PGM Min Max Unit έ4, έ8 1000 n ms έ16 2000 n ms hPPR precharge exit time t 15 n ns hPPR exit time t 50 n ρs PGM_Exit PGMPST sPPR Row Repair Soft post package repair (sPPR) is a way to quickly, but temporarily, repair a row element in a bank on a DRAM device, where hPPR takes longer but permanently repairs a row element. sPPR mode is entered in a similar fashion as hPPR, sPPR uses MR4[5] while hPPR uses MR4[13]. sPPR is disabled with MR4[5] = 0, which is the normal state, and sPPR is enabled with MR4[5] = 1, which is the sPPR enabled state. sPPR requires the same guard key sequence as hPPR to qualify the MR4 PPR entry. After sPPR entry, an ACT command will capture the target bank and target row, herein seed row, where the row repair will be made. After tRCD time, a WR command is used to select the individual DRAM, through the DQ bits, CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 135 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM sPPR Row Repair to transfer the repair address into an internal register in the DRAM. After a write recovery time and PRE command, the sPPR mode can be exited and normal operation can resume. The DRAM will retain the soft repair information as long as VDD remains within the operating region unless rewritten by a subsequent sPPR entry to the same bank. If DRAM power is removed or the DRAM is reset, the soft repair will revert to the unrepaired state. hPPR and sPPR should not be enabled at the same time; Micron sPPR does not have to be disabled and cleared prior to entering hPPR mode, but sPPR must be disabled and cleared prior to entering MBIST-PPR mode. With sPPR, Micron DDR4 can repair one row per bank. When a subsequent sPPR request is made to the same bank, the subsequently issued sPPR address will replace the previous sPPR address. When the hPPR resource for a bank is used up, the bank should be assumed to not have available resources for sPPR. If a repair sequence is issued to a bank with no repair resource available, the DRAM will ignore the programming sequence. The bank receiving sPPR change is expected to retain memory array data in all rows except for the seed row and its associated row addresses. If the data in the memory array in the bank under sPPR repair is NOTREQUIREDTOBERETAINEDTHENTHEHANDLINGOFTHESEEDROWSASSOCIATEDROWADDRESSESISNOTOF interest and can be ignored. If the data in the memory array is required to be retained in the bank under sPPR mode, then prior to executing the sPPR mode, the seed row and its associated row addresses should be backed up and subsequently restored after sPPR has been completed. sPPR associated seed row addresses are specified in the Table below; BA0 is not required by Micron DRAMs however it is JEDEC reserved. Table 43: sPPR Associated Rows sPPR Associated Row Address BA0* A17 A16 A15 A14 A13 A1 A0 All banks must be precharged and idle. DBI and CRC modes must be disabled, and all sPPR timings must be followed as shown in the timing diagram that follows. All other commands except those listed in the following sequences are illegal. 1. Issue MR4[5] 1 to enter sPPR mode enable. a) All DQ are driven HIGH. 2. Issue four consecutive guard key commands (shown in the table below) to MR0 with each command separated by tMOD. Please note that JEDEC recently added the four guard key entry used for hPPR to sPPR entry; early DRAMs may not require four guard key entry code. A prudent controller design should accommodate either option in case an earlier DRAM is used. a) Any interruption of the key sequence by other commands, such as ACT, WR, RD, PRE, REF, ZQ, and NOP, are not allowed. b) If the guard key bits are not entered in the required order or interrupted with other MR commands, sPPR will not be enabled, and the programming cycle will result in a NOP. c) When the sPPR entry sequence is interrupted and followed by ACT and WR commands, these commands will be conducted as normal DRAM commands. d) JEDEC allows A6:0 to be "Don't Care" on 4Gb and 8Gb devices from a supplier perspective and the user should rely on vendor datasheet. Table 44: PPR MR0 Guard Key Settings MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0 First guard key 0 0 xxxxxx 1 1 0 0 1 1111111 Second guard key 0 0 xxxxxx 0 1 1 1 1 1111111 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 136 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM sPPR Row Repair Table 44: PPR MR0 Guard Key Settings (Continued) MR0 BG1:0 BA1:0 A17:12 A11 A10 A9 A8 A7 A6:0 Third guard key 0 0 xxxxxx 1 0 1 1 1 1111111 Fourth guard key 0 0 xxxxxx 0 0 1 1 1 1111111 3. After tMOD, issue an ACT command with failing BG and BA with the row address to be repaired. 4. After tRCD, issue a WR command with BG and BA of failing row address. a) The address must be at valid levels, but the address is a "Don't Care." 5. All DQ of the target DRAM should be driven LOW for 4nCK (bit 0 through bit 7) after WL (WL = CWL + AL + PL) in order for sPPR to initiate repair. a) Repair will be initiated to the target DRAM only if all DQ during bit 0 through bit 7 are LOW. b) Repair will not be initiated to the target DRAM if any DQ during bit 0 through bit 7 is HIGH. i) JEDEC states: All DQs of target DRAM should be LOW for 4tCK. If HIGH is driven to all DQs of a DRAM consecutively for equal to or longer than the first 2tCK, then DRAM does not conduct hPPR and retains data if REF command is properly issued; if all DQs are neither LOW for 4tCK nor HIGH for equal to or longer than the first 2tCK, then hPPR mode execution is unknown. c) DQS should function normally. 6. REF command may NOT be issued at anytime while in sPPR mode. 7. Issue PRE after tWR time so that the device can repair the target row during tWR time. a) Wait tPGM_Exit_s after PRE to allow the device to recognize the repaired target row address. 8. Issue MR4[5] 0 command to sPPR mode disable. a) Wait tPGMPST_s for sPPR mode exit to complete. b) After tPGMPST_s has expired, any valid command may be issued. The entire sequence from sPPR mode enable through sPPR mode disable may be repeated if more than one repair is to be done. After sPPR mode has been exited, the DRAM controller can confirm if the target row was repaired correctly by writing data into the target row and reading it back. Figure 79: S002n%NTRY T0 T1 Ta0 Ta1 Tb0 Tb1 Tc0 Tc1 Td0 CMD MRS4 DES MRS0 DES MRS0 DES MRS0 DES MRS0 BG Valid N/A 00 N/A 00 N/A 00 N/A 00 Td1 Te0 Tf0 DES ACT WR N/A BGf Tg0 CK_c CK_t BGf DES N/A BA Valid N/A 00 N/A 00 N/A 00 N/A 00 N/A BAf BAf N/A ADDR Valid (A5=1) N/A 1st Key N/A 2nd Key N/A 3rd Key N/A 4th Key N/A Valid Valid N/A CKE DQS_t DQS_c DQs1 All Banks Precharged and idle state Normal Mode t MOD t MOD t MOD t MOD t MOD sPPR Entry 1st Guard Key Validate 2nd Guard Key Validate 3rd Guard Key Validate 4th Guard Key Validate t RCD sPPR Repair Don’t Care CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 137 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM MBIST-PPR Figure 80: S002n2EPAIRAND%XIT Te0 Tf0 CMD ACT BG BGf BA ADDR CK_c Tg0 Tg1 Th0 Th1 Tj0 Tj1 Tj2 Tk0 WR DES DES DES DES DES DES DES PRE BGf N/A N/A N/A N/A N/A N/A N/A Valid BAf BAf N/A N/A N/A N/A N/A N/A N/A Valid Valid Valid N/A N/A N/A N/A N/A N/A N/A Valid Tk1 Tm0 Tm1 Tn0 DES MRS4 DES Valid N/A Valid N/A Valid N/A Valid N/A Valid N/A Valid (A5=0) N/A Valid CK_t CKE WL = CWL + AL + PL tWR 4nCK DQS_t DQS_c DQs1 bit 0 All Banks Precharged and idle state bit 1 bit 6 bit 7 tPGM_s tRCD sPPR Repair sPPR Repair tPGM_Exit_s sPPR Repair sPPR Recognition sPPR Repair tPGMPST_s Normal Mode sPPR Exit Don’t Care Table 45: DDR4 sPPR Timing Parameters DDR4-1600 Through DDR4-3200 Parameter Symbol sPPR programming time tPGM_s sPPR precharge exit time tPGM_Exit_s sPPR exit time t PGMPST_s Min tRCD(MIN)+ Max Unit n ns 20 n ns MOD n ns WL + 4nCK + t tWR(MIN) MBIST-PPR DDR4 devices can support optional memory built-in self-test post-package repair (MBIST-PPR) to help with hard failures such as single-bit or multi-bit failures in a single device so that weak cells can be scanned and repaired during the initialization phase. The DRAM will use vendor-specific patterns to investigate the status of all cell arrays and automatically perform PPR for weak bits during this operation. This operation introduces proactive, automated PPR by the DRAM, and it is recommended to be DONEFORAVERYFIRSTBOOT UPATLEAST!FTERTHATITISATTHECONTROLLERSDISCRETIONWHETHERTOACTIVATE MBIST. MBIST mode can only be entered from the all banks idle state. The DLL is required to be enabled and locked prior to MBIST-PPR execution. MBIST-PPR resources are separated from normal hPPR/sPPR resources. MBIST-PPR resources are typically used for initial scan and repair, and hPPR/sPPR resources must still satisfy the number of repair elements, one per BG, specified in the DDR4 Bank Group Timing Examples 1. Once the MBIST-PPR is completed, the DRAM will update the status flag in MPR3[7] of MPR page 3. Detailed status is described in the MPR Page and MPRx Definitions . The test time of MBIST-PPR will not exceed 10 seconds for all mono-die DRAM densities. For DDP devices, test time will be 20 seconds. The controller is required to inject an MRS command to enter this operation. The controller sets MR4:A0 to 1, followed by MR0 commands for the guard key. Then the DRAM enters MBIST-PPR operation. The ALERT_n signal notifies the host of the status of this operation. When the controller sets MR4:A0 to 1, followed by the MR0 guard key sequence, the DRAM drives ALERT_n to 0. Once the CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 138 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM MBIST-PPR MBIST-PPR is completed, the DRAM drives ALERT_n to 1 to notify the controller that this operation is completed. DRAM data will not be guaranteed after the MBIST-PPR operation. Table 46: MBIST-PPR Timing Parameter Value Parameter tSELFHEAL Min Max Unit Monolithic n 10 s DDP n 20 MBIST-PPR Procedure The following sequences are required for MBIST-PPR and are shown in the figure below. 1. The DRAM needs to finalize initialization, MR training, and ZQ calibration prior to entering MBIST-PPR. 2. Four consecutive guard key commands must be issued to MR0, with each command separated by t MOD. The PPR guard key settings are the same whether performing sPPR, hPPR, or MBIST-PPR mode. 3. Anytime after Tk in the Read Termination Disable Window 15, the host must set MR4:A0 to 1, followed by subsequent MR0 guard key sequences (which is identical to typical hPPR/sPPR guard key sequences and specified in Table 73) to start MBIST-PPR operation, and the DRAM drives the ALERT_n signal to 0. 4. During MBIST-PPR mode, only DESELECT commands are allowed. 5. The ODT pin must be driven LOW during MBIST-PPR to satisfy DODTLoff from time Tb0 until Tc2. The DRAM may or may not provide RTT_PARK termination during MBIST-PPR regardless of whether RTT_PARK is enabled in MR5. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 139 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM MBIST-PPR Figure 81: MBIST-PPR Sequence T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 CMD MRS4 DES MRS0 DES DES Valid DES BG Valid N/A 00 N/A N/A Valid N/A BA Valid N/A 00 N/A N/A Valid N/A ADDR Valid (A0=1) N/A 4th Key N/A N/A Valid N/A CK_c CK_t CKE t IS ALERT_N 5 x t MOD Follow Guard Key Entry Sequence All Banks Precharged and idle state Normal Mode t SELFHEAL MBIST-PPR Entry MBIST-PPR Normal Normal Operation Operation Table 47: MPR Page3 Configuration for MBIST-PPR Address MPR Location [7] [6] [5] [4] [3] [2] [1] [0] Note BA[1:0] 00 = MPR0 DC DC DC DC DC DC DC DC 01 = MPR1 DC DC DC DC DC DC DC DC Readonly 10 = MPR2 DC DC DC DC DC DC DC DC 11 = MPR3 MBISTPPR Support DC MBIST-PPR Transparency MAC MAC MAC MAC MPR Location Address Bit Function 11 = MPR3 7 MBIST-PPR Support Data Notes 0: Don't Support 1: Support 00B: MBIST-PPR hasn't run since init OR no fails found during most recent MBIST-PPR 11 = MPR3 5:4 MBIST-PPR Transparency 1 1, 2 01B: Repaired all found fails during most recent run 1 10B: Unrepairable fails found during most recent run 1 11B: MBIST-PPR should be run again 1, 3 Notes: 1. MPR bits are cleared either by a power-up sequence or re-initialization by RESET_n signal 2. The host should track whether MBIST-PPR has run since INIT. If MBIST-PPR is performed and it finds no fails, this transparency state will remain set to 00B 3. This state does not imply that MBIST-PPR is required to run again. This implies that additional repairable fails were found during the most recent MBIST-PPR beyond what could be repaired in the tSELFHEAL window. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 140 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM hPPR/sPPR/MBIST-PPR Support Identifier hPPR/sPPR/MBIST-PPR Support Identifier Table 48: DDR4 Repair Mode Support Identifier MPR Page 2 MPR0 MPR Page 3 A6 A5 A4 A3 A2 A1 A0 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 hPPR1 sPPR2 RTT_WR A7 A6 A5 A4 A3 A2 A1 A0 UI0 UI1 UI2 UI3 UI4 UI5 UI6 UI7 MAC MAC MAC MAC MBIST-PPR Support3 MPR3 Notes: 1. 2. 3. 4. A7 Temp sensor Don't Care MBIST-PPR Transparency RTT_WR CRC 0 = hPPR mode is not available, 1 = hPPR mode is available. 0 = sPPR mode is not available, 1 = sPPR mode is available. 0 = MBIST-PPR mode is not available, 1 = MBIST-PPR mode is available. Gray shaded areas are for reference only. ACTIVATE Command The ACTIVATE command is used to open (activate) a row in a particular bank for subsequent access. The values on the BG[1:0] inputs select the bank group, the BA[1:0] inputs select the bank within the bank group, and the address provided on inputs A[17:0] selects the row within the bank. This row remains active (open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Bank-to-bank command timing for ACTIVATE commands uses two different timing parameters, depending on whether the banks are in the same or different bank group. tRRD_S (short) is used for timing between banks located in different bank groups. tRRD_L (long) is used for timing between banks located in the same bank group. Another timing restriction for consecutive ACTIVATE commands [issued at tRRD (MIN)] is tFAW (four activate window). Because there is a maximum of four banks in a bank group, the tFAW parameter applies across different bank groups (five ACTIVATE commands issued at tRRD_L (MIN) to the same bank group would be limited by tRC). Figure 82: tRRD Timing CK_c CK_t Command T0 T1 ACT DES T2 T3 T4 T5 T6 DES DES ACT DES DES T8 T9 T10 T11 DES DES DES ACT DES tRRD_L tRRD_S Bank Group (BG) T7 BG a BG b BG b Bank Bank c Bank c Bank d Address Row n Row n Row n Don’t Care tRRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (that is, T0 and T4). 2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (that is, T4 and T10). Notes: 1. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 141 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM PRECHARGE Command Figure 83: tFAW Timing T0 CK_c CK_t Command ACT Ta0 Valid ACT tRRD Tb0 Valid ACT tRRD Valid Tc0 Tc1 Tc2 ACT Valid Valid tRRD Valid Td0 Td1 ACT NOP tFAW Bank Group (BG) Valid Valid Valid Valid Valid Bank Valid Valid Valid Valid Valid Address Valid Valid Valid Valid Valid Don’t Care Note: 1. Time Break t FAW; four activate windows. PRECHARGE Command The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row activation for a specified time (tRP) after the PRECHARGE command is issued. An exception to this is the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. After a bank is precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row in that bank (idle state) or if the previously open row is already in the process of precharging. However, the precharge period will be determined by the last PRECHARGE command issued to the bank. The auto precharge feature is engaged when a READ or WRITE command is issued with A10 HIGH. The auto precharge feature uses the RAS lockout circuit to internally delay the PRECHARGE operation until the ARRAY RESTORE operation has completed. The RAS lockout circuit feature allows the PRECHARGE operation to be partially or completely hidden during burst READ cycles when the auto precharge feature is engaged. The PRECHARGE operation will not begin until after the last data of the burst write sequence is properly stored in the memory array. REFRESH Command The REFRESH command (REF) is used during normal operation of the device. This command is nonpersistent, so it must be issued each time a refresh is required. The device requires REFRESH cycles at an average periodic interval of tREFI. When CS_n, RAS_n/A16, and CAS_n/A15 are held LOW and WE_n/A14 HIGH at the rising edge of the clock, the device enters a REFRESH cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time, tRP (MIN), before the REFRESH command can be applied. The refresh addressing is generated by the internal DRAM refresh CONTROLLER4HISMAKESTHEADDRESSBITSh$ONT#AREvDURINGA2%&2%3(COMMAND!NINTERNALADDRESS counter supplies the addresses during the REFRESH cycle. No control of the external address bus is required once this cycle has started. When the REFRESH cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the REFRESH command and the next valid command, except DES, must be greater than or equal to the minimum REFRESH cycle time tRFC (MIN), as shown in . NOTE: The tRFC timing parameter depends on memory density. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 142 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command In general, a REFRESH command needs to be issued to the device regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided for postponing and pulling-in the REFRESH command. A limited number REFRESH commands can be postponed depending on refresh mode: a maximum of 8 REFRESH commands can be postponed when the device is in 1X refresh mode; a maximum of 16 REFRESH commands can be postponed when the device is in 2X refresh mode; and a maximum of 32 REFRESH commands can be postponed when the device is in 4X refresh mode. When 8 consecutive REFRESH commands are postponed, the resulting maximum interval between the surrounding REFRESH commands is limited to 9 έ tREFI (see ). For both the 2X and 4X refresh modes, the maximum interval between surrounding REFRESH commands allowed is limited to 17 έ tREFI2 and 33 έ tREFI4, respectively. A limited number REFRESH commands can be pulled-in as well. A maximum of 8 additional REFRESH COMMANDSCANBEISSUEDINADVANCEORhPULLED INvIN8REFRESHMODEAMAXIMUMOFADDITIONAL REFRESH commands can be issued when in advance in 2X refresh mode, and a maximum of 32 additional REFRESH commands can be issued in advance when in 4X refresh mode. Each of these REFRESH commands reduces the number of regular REFRESH commands required later by one. The resulting maximum interval between two surrounding REFRESH commands is limited to 9 έ tREFI ( ), 17 έ tRFEI2, or 33 έ tREFI4. At any given time, a maximum of 16 REF commands can be issued within 2 έ tREFI, 32 REF2 commands can be issued within 4 έ tREFI2, and 64 REF4 commands can be issued within 8 έ tREFI4 (larger densities are limited by tRFC1, tRFC2, and tRFC4, respectively, which must still be met). Figure 84: REFRESH Command Timing CK_c T0 T1 REF DES Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Valid Valid Valid Valid Tc0 Tc1 Tc2 Tc3 REF Valid Valid Valid CK_t Command DES REF tRFC DES tRFC DES Valid (MIN) tREFI (MAX 9 × tREFI) DRAM must be idle DRAM must be idle Time Break Don’t Care Notes: 1. Only DES commands are allowed after a REFRESH command is registered until tRFC (MIN) expires. 2. Time interval between two REFRESH commands may be extended to a maximum of 9 έ tREFI. Figure 85: Postponing REFRESH Commands (Example) tREFI 9 × tREFI t tRFC 8 REF-Commands postponed CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 143 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM REFRESH Command Figure 86: Pulling In REFRESH Commands (Example) 9 × tREFI tREFI t tRFC 8 REF-Commands pulled-in CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode Temperature-Controlled Refresh Mode During normal operation, temperature-controlled refresh (TCR) mode disabled, the device must have a REFRESH command issued once every tREFI, except for what is allowed by posting (see REFRESH Command section). This means a REFRESH command must be issued once every 7.8ρs if TC is less than or equal to 85ιC, once every 3.9ρs if TC is greater than 85ιC, once every 1.95ρs if TC is greater than 95ιC, regardless of which Temperature Mode is selected (MR4[2]). TCR mode is disabled by setting MR4[3] = 0 while TCR mode is enabled by setting MR4[3] = 1. When TCR mode is enabled (MR4[3] = 1), the Temperature Mode must be selected where MR4[2] = 0 enables the Normal Temperature Mode while MR4[2] = 1 enables the Extended Temperature Mode. When TCR mode is enabled, the device will register the externally supplied REFRESH command and adjust the internal refresh period to be longer than tREFI of the normal temperature range, when allowed, by skipping REFRESH commands with the proper gear ratio. TCR mode has two Temperature Modes to select between the normal temperature range and the extended temperature range; the correct Temperature Mode must be selected so the internal control operates correctly. The DRAM must have the correct refresh rate applied externally; the internal refresh rate is determined by the DRAM based upon the temperature. Normal Temperature Mode REFRESH commands should be issued to the device with the refresh period equal to tREFI of normal temperature range (-40ιC to 85ιC). The system must guarantee that the TC does not exceed 85ιC when t REFI of the normal temperature range is used. The device may adjust the internal refresh period to be longer than tREFI of the normal temperature range by skipping external REFRESH commands with the proper gear ratio when TC is below 85ιC. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control. Extended Temperature Mode REFRESH commands should be issued to the device with the refresh period equal to tREFI of extended temperature range (85ιC to 95ιC, or 95ιC to 105ιC) . The system must guarantee that the TC does not exceed 95ιC, or 105ιC. Even though the external refresh supports the extended temperature range, the device may adjust its internal refresh period to be equal to or longer than tREFI of the normal temperature range (-40ιC to 85ιC) by skipping external REFRESH commands with the proper gear ratio when TC is equal to or below 85ιC. The internal refresh period is automatically adjusted inside the DRAM, and the DRAM controller does not need to provide any additional control. Table 49: Normal tREFI Refresh (TCR Enabled) Normal Temperature Mode Extended Temperature Mode Temperature External Refresh Period Internal Refresh Period External Refresh Period Internal Refresh Period TC ζ 85ιC 7.8ρs η7.8ρs 3.9ρs1 η7.8ρs 85ιC < TC ζ 95ιC 3.9ρs 95ιC < TC ζ 105ιC 1.95ρs Notes: 1. If the external refresh period is slower than 3.9ρs, the device will refresh internally at too slow of a refresh rate and will violate refresh specifications. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Temperature-Controlled Refresh Mode Figure 87: TCR Mode Example1 Controller External tREFI 3.9μs REFRESH REFRESH 85°C < TC ” 95°C TC ” 85°C REFRESH REFRESH Internal tREFI 3.9μs REFRESH Internal tREFI •7.8μs REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH REFRESH Controller issues REFRESH commands at extended temperature rate External REFRESH commands are not ignored At least every other external REFRESH ignored REFRESH Note: 1. TCR enabled with Extended Temperature Mode selected. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode Fine Granularity Refresh Mode Mode Register and Command Truth Table The REFRESH cycle time (tRFC) and the average refresh interval (tREFI) can be programmed by the MRS command. The appropriate setting in the mode register will set a single set of REFRESH cycle times and average refresh interval for the device (fixed mode), or allow the dynamic selection of one of two sets of REFRESH cycle times and average refresh interval for the device (on-the-fly mode [OTF]). OTF mode must be enabled by MRS before any OTF REFRESH command can be issued. Table 50: MRS Definition MR3[ 8] MR3[7] MR3[6] Refresh Rate Mode 0 0 0 Normal mode (fixed 1x) 0 0 1 Fixed 2x 0 1 0 Fixed 4x 0 1 1 Reserved 1 0 0 Reserved 1 0 1 On-the-fly 1x/2x 1 1 0 On-the-fly 1x/4x 1 1 1 Reserved There are two types of OTF modes (1x/2x and 1x/4x modes) that are selectable by programming the appropriate values into the mode register MR3 [8:6]. When either of the two OTF modes is selected, the device evaluates the BG0 bit when a REFRESH command is issued, and depending on the status of BG0, it dynamically switches its internal refresh configuration between 1x and 2x (or 1x and 4x) modes, and then executes the corresponding REFRESH operation. Table 51: REFRESH Command Truth Table RAS_n/A CAS_n/A 15 14 WE_n/ A13 BG1 BG0 A10/ AP A[9:0], A[12:11], A[20:16] MR3[8:6 ] Refresh CS_n ACT_n Fixed rate L H L L H V V V V 0vv OTF: 1x L H L L H V L V V 1vv OTF: 2x L H L L H V H V V 101 OTF: 4x L H L L H V H V V 110 t REFI and tRFC Parameters The default refresh rate mode is fixed 1x mode where REFRESH commands should be issued with the normal rate; that is, tREFI1 = tREFI(base) (for TC ζ 85ιC), and the duration of each REFRESH command is the normal REFRESH cycle time (tRFC1). In 2x mode (either fixed 2x or OTF 2x mode), REFRESH commands should be issued to the device at the double frequency (tREFI2 = tREFI(base)/2) of the normal refresh rate. In 4x mode, the REFRESH command rate should be quadrupled (tREFI4 = t REFI(base)/4). Per each mode and command type, the tRFC parameter has different values as defined in the following table. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 147 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode For discussion purposes, the REFRESH command that should be issued at the normal refresh rate and has the normal REFRESH cycle duration may be referred to as an REF1x command. The REFRESH command that should be issued at the double frequency (tREFI2 = tREFI(base)/2) may be referred to as a REF2x command. Finally, the REFRESH command that should be issued at the quadruple rate (tREFI4 = tREFI(base)/4) may be referred to as a REF4x command. In the fixed 1x refresh rate mode, only REF1x commands are permitted. In the fixed 2x refresh rate mode, only REF2x commands are permitted. In the fixed 4x refresh rate mode, only REF4x commands are permitted. When the on-the-fly 1x/2x refresh rate mode is enabled, both REF1x and REF2x commands are permitted. When the OTF 1x/4x refresh rate mode is enabled, both REF1x and REF4x commands are permitted. Table 52: tREFI and tRFC Parameters Refresh Mode Parameter t REFI (base) 1x mode tREFI1 -40ιC ζ TC ζ 85ιC REFI2 REFI4 t RFC4 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Units 7.8 ρs tREFI(base) tREFI(base) tREFI(base) tREFI(base) ρs REFI(base)/2 t t t ρs 95ιC ζ TC ζ 105ιC t t t t REFI(base)/4 ρs 350 ns REFI(base)/2 REFI(base)/4 REFI(base)/2 REFI(base)/4 160 REFI(base)/2 REFI(base)/4 260 350 -40ιC ζ TC ζ 85ιC t t t t ρs 85ιC ζ TC ζ 95ιC t t t t REFI(base)/4 ρs 95ιC ζ TC ζ 105ιC tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 tREFI(base)/8 ρs 110 160 260 260 ns REFI(base)/4 REFI(base)/2 REFI(base)/4 RFC2 t 16Gb 7.8 REFI(base)/2 t 4x mode 8Gb 7.8 t RFC1 t 4Gb 7.8 85ιC ζ TC ζ 95ιC t 2x mode 2Gb REFI(base)/2 REFI(base)/4 REFI(base)/2 REFI(base)/4 -40ιC ζ TC ζ 85ιC t t t t ρs 85ιC ζ TC ζ 95ιC t t t t ρs 95ιC ζ TC ζ 105ιC t t t t REFI(base)/1 6 ρs 160 ns REFI(base)/4 REFI(base)/8 REFI(base)/1 6 90 148 REFI(base)/4 REFI(base)/8 REFI(base)/1 6 110 REFI(base)/4 REFI(base)/8 REFI(base)/1 6 160 REFI(base)/8 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. Extended Temperature Operation – -40°C to 105°C Normal Temperature Operation – -40°C to 85°C 2x Mode (-40°C to 85°C) 4x Mode (-40°C to 85°C) 1x Mode (-40°C to 105°C) 2x Mode (-40°C to 105°C) 4x Mode (-40°C to 105°C) REF@260ns REF@160ns REF@110ns REF@260ns REF@160ns REF@110ns 5μ FI 5μ s Rt E 97 0. = s s 0. = μs s Rt E FI 95 1. = 5μ FI Rt E REF@260ns REF@160ns s 5μ REF@110ns REF@110ns = μs 5μ 97 0. = s FI 9μ 5μ = FI 5μ s Rt E 95 1. = 97 FI REF@110ns REF@260ns REF@160ns 5μ REF@110ns REF@110ns 97 REF@160ns = FI μs 5μ 97 0. = FI 5μ s Rt E = s 97 REF@160ns 5μ REF@260ns REF@110ns 97 REF@110ns = FI μs 5μ s Rt E 95 1. = 97 s 5μ 3. Rt E FI 9μ s = Rt E 0. FI REF@110ns = 97 REF@110ns = 0. REF@160ns FI 5μ s Rt E 95 1. 97 0. = FI REF@110ns Rt E FI = Rt E Rt E FI = 1. 95 μs Rt E FI REF@110ns μs Rt E FI = 3. 9μ s Rt E FI = 1. 95 μs 0. REF@160ns s Rt E Rt E FI FI = Rt E 0. FI = FI Rt E 5μ 1. Rt E 95 FI μs = 0. 97 FI μs 95 1. s 8μ 7. REF@110ns REF@260ns REF@160ns REF@110ns REF@260ns REF@160ns REF@110ns 8Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. = s Rt E 95 1. = FI Rt E s 9μ 3. REF@110ns REF@160ns Rt E FI REF@110ns Rt E REF@110ns = = 3. 9μ s Rt E FI = 1. 149 95 μs 0. REF@260ns s Rt E FI = 0. Rt E Rt E FI = 1. 95 μs 0. 97 FI Rt E s Rt E 3. REF@110ns REF@160ns μs Rt E FI REF@110ns s Rt E FI 95 1. = Rt E FI REF@110ns = = 3. 9μ s Rt E FI = 1. 95 Rt E μs FI 0. 97 REF@160ns = 7. 8μ s Rt E FI = 0. 97 FI REF@110ns Rt E FI = 1. 95 μs 97 REF@110ns REF@160ns Rt E 5μ = Rt E 3. FI 9μ s 9μ 3. = FI REF@110ns Rt E 0. 97 = μs 95 1. = FI REF@110ns Rt E FI = 1. 95 μs s 1x Mode (-40°C to 85°C) Rt E CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Figure 88: 4Gb with Fine Granularity Refresh Mode Example 8Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode Changing Refresh Rate If the refresh rate is changed by either MRS or OTF. New tREFI and tRFC parameters will be applied from the moment of the rate change. When the REF1x command is issued to the DRAM, tREF1 and t RFC1 are applied from the time that the command was issued; when the REF2x command is issued, tREF2 and tRFC2 should be satisfied. Figure 89: OTF REFRESH Command Timing CK_c CK_t Command DES REF1 DES DES tRFC1 DES Valid Valid REF2 DES tRFC2 (MIN) tREFI1 DES Valid DES REF2 DES (MIN) tREFI2 Don’t Care The following conditions must be satisfied before the refresh rate can be changed. Otherwise, data retention cannot be guaranteed. s In the fixed 2x refresh rate mode or the OTF 1x/2x refresh mode, an even number of REF2x commands must be issued because the last change of the refresh rate mode with an MRS command before the refresh rate can be changed by another MRS command. s In the OTF1x/2x refresh rate mode, an even number of REF2x commands must be issued between any two REF1x commands. s In the fixed 4x refresh rate mode or the OTF 1x/4x refresh mode, a multiple-of-four number of REF4x commands must be issued because the last change of the refresh rate with an MRS command before the refresh rate can be changed by another MRS command. s In the OTF1x/4x refresh rate mode, a multiple-of-four number of REF4x commands must be issued between any two REF1x commands. There are no special restrictions for the fixed 1x refresh rate mode. Switching between fixed and OTF modes keeping the same rate is not regarded as a refresh rate change. Usage with TCR Mode If the temperature controlled refresh mode is enabled, only the normal mode (fixed 1x mode, MR3[8:6] = 000) is allowed. If any other refresh mode than the normal mode is selected, the temperature controlled refresh mode must be disabled. Self Refresh Entry and Exit The device can enter self refresh mode anytime in 1x, 2x, and 4x mode without any restriction on the number of REFRESH commands that have been issued during the mode before the self refresh entry. However, upon self refresh exit, extra REFRESH command(s) may be required, depending on the condition of the self refresh entry. The conditions and requirements for the extra REFRESH command(s) are defined as follows: s In the fixed 2x refresh rate mode or the enable-OTF 1x/2x refresh rate mode, it is recommended there be an even number of REF2x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that set the refresh mode. If this condition is met, no additional REFRESH commands are required upon self refresh exit. In the case that this condition is not met, either one extra REF1x command or two extra REF2x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval (tREFI). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 150 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Fine Granularity Refresh Mode s In the fixed 4x refresh rate mode or the enable-OTF 1x/4x refresh rate mode, it is recommended there be a multiple-of-four number of REF4x commands before entry into self refresh after the last self refresh exit, REF1x command, or MRS command that set the refresh mode. If this condition is met, no additional refresh commands are required upon self refresh exit. When this condition is not met, either one extra REF1x command or four extra REF4x commands must be issued upon self refresh exit. These extra REFRESH commands are not counted toward the computation of the average refresh interval (tREFI). There are no special restrictions on the fixed 1x refresh rate mode. This section does not change the requirement regarding postponed REFRESH commands. The requirement for the additional REFRESH command(s) described above is independent of the requirement for the postponed REFRESH commands. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 151 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation SELF REFRESH Operation The SELF REFRESH command can be used to retain data in the device, even if the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The device has a built-in timer to accommodate SELF REFRESH operation. The SELF REFRESH command is defined by having CS_n, RAS_n, CAS_n, and CKE held LOW with WE_n and ACT_n HIGH at the rising edge of the clock. Before issuing the SELF REFRESH ENTRY command, the device must be idle with all banks in the precharge state and tRP satisfied. Idle state is defined as: All banks are closed (tRP, tDAL, and so on, satisfied), no data bursts are in progress, CKE is HIGH, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, and so on). After the SELF REFRESH ENTRY command is registered, CKE must be held LOW to keep the device in self refresh mode. The DRAM automatically disables ODT termination, regardless of the ODT pin, when it enters self refresh mode and automatically enables ODT upon exiting self refresh. During normal operation (DLL_on), the DLL is automatically disabled upon entering self refresh and is automatically enabled (including a DLL reset) upon exiting self refresh. When the device has entered self refresh mode, all of the external control signals, except CKE and 2%3%4?NAREh$ONT#AREv&ORPROPER3%,&2%&2%3(OPERATIONALLPOWERSUPPLYANDREFERENCEPINS (VDD, VDDQ, VSS, VSSQ, VPP, and VREFCA) must be at valid levels. The DRAM internal VREFDQ generator circuitry may remain on or be turned off depending on the MR6 bit 7 setting. If the internal VREFDQ circuit is on in self refresh, the first WRITE operation or first write-leveling activity may occur after tXS time after self refresh exit. If the DRAM internal VREFDQ circuitry is turned off in self refresh, it ensures that the VREFDQ generator circuitry is powered up and stable within the tXSDLL period when the DRAM exits the self refresh state. The first WRITE operation or first write-leveling activity may not occur earlier than tXSDLL after exiting self refresh. The device initiates a minimum of one REFRESH command internally within the tCKE period once it enters self refresh mode. The clock is internally disabled during a SELF REFRESH operation to save power. The minimum time that the device must remain in self refresh mode is tCKESR/tCKESR_PAR. The user may change the external clock frequency or halt the external clock tCKSRE/tCKSRE_PAR after self refresh entry is registered; however, the clock must be restarted and tCKSRX must be stable before the device can exit SELF REFRESH operation. The procedure for exiting self refresh requires a sequence of events. First, the clock must be stable prior to CKE going back HIGH. Once a SELF REFRESH EXIT command (SRX, combination of CKE going HIGH and DESELECT on the command bus) is registered, the following timing delay must be satisfied: Commands that do not require locked DLL: s tXS = ACT, PRE, PREA, REF, SRE, and PDE. s tXS_FAST = ZQCL, ZQCS, and MRS commands. For an MRS command, only DRAM CL, WR/RTP register, and DLL reset in MR0; RTT(NOM) register in MR1; the CWL and RTT(WR) registers in MR2; and gear-down mode register in MR3; WRITE and READ preamble registers in MR4; RTT(PARK) register in MR5; Data rate and VREFDQ calibration value registers in MR6 may be accessed provided the DRAM is not in per-DRAM mode. Access to other DRAM mode registers must satisfy tXS timing. WRITE commands (WR, WRS4, WRS8, WRA, WRAS4, and WRAS8) that require synchronous ODT and dynamic ODT controlled by the WRITE command require a locked DLL. Commands that require locked DLL in the normal operating range: CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 152 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation s t83$,,n2$2$32$32$!2$!3AND2$!3UNLIKE$$27272372372!72!3 and WRAS8 because synchronous ODT is required). Depending on the system environment and the amount of time spent in self refresh, ZQ CALIBRATION commands may be required to compensate for the voltage and temperature drift described in the ZQ CALIBRATION Commands section. To issue ZQ CALIBRATION commands, applicable timing requirements must be satisfied (see the ZQ Calibration Timing figure). CKE must remain HIGH for the entire self refresh exit period tXSDLL for proper operation except for self refresh re-entry. Upon exit from self refresh, the device can be put back into self refresh mode or power-down mode after waiting at least tXS period and issuing one REFRESH command (refresh period of tRFC). The DESELECT command must be registered on each positive clock edge during the self refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of self refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self refresh mode. Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. Figure 90: Self Refresh Entry/Exit Timing T0 T1 Ta0 Tb0 Tc0 Td0 Td1 Te0 Tf0 Tg0 Valid Valid Valid CK_c CK_t tCKSRX tCKSRE/tCKSRE_PAR tIS tCPDED CKE tCKESR/tCKESR_PAR Valid ODT tXS_FAST Command DES SRE SRX DES ADDR Valid 1 Valid 2 Valid 3 Valid Valid Valid tXS tRP tXSDLL Enter Self Refresh Exit Self Refresh Don’t Care Time Break Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed. 2. Valid commands not requiring a locked DLL. 3. Valid commands requiring a locked DLL. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 153 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation Figure 91: Self Refresh Entry/Exit Timing with CAL Mode T0 T1 T3 T4 T7 T8 T11 Ta0 Ta7 Ta8 Ta9 Ta10 Tb0 Tb1 DES DES DES Tb3 CK_c CK_t t t CKSRE CKSRX CS_n Note 2 Command w/o CS_n DES DES ADDR SRE DES DES SRX Note 3 DES Valid Valid t CAL Valid t t CPDED XS_FAST t CAL CKE Don’t Care Notes: 1. tCAL = 3nCK, tCPDED = 4nCK, tCKSRE/tCKSRE_PAR = 8nCK, tCKSRX = 8nCK, tXS_FAST = tREFC4 (MIN) + 10ns. 2. CS_n = HIGH, ACT_n = "Don't Care," RAS_n/A16 = "Don't Care," CAS_n/A15 = "Don't Care," WE_n/A14 = "Don't Care." 3. Only MRS (limited to those described in the SELF REFRESH Operations section), ZQCS, or ZQCL commands are allowed. 4. The figure only displays tXS_FAST timing, but tCAL must also be added to any tXS and tXSDLL associated commands during CAL mode. Self Refresh Abort The exit timing from self refresh exit to the first valid command not requiring a locked DLL is tXS. The value of tXS is (tRFC1 + 10ns). This delay allows any refreshes started by the device time to complete. t RFC continues to grow with higher density devices, so tXS will grow as well. An MRS bit enables the self refresh abort mode. If the bit is disabled, the controller uses tXS timings (location MR4, bit 9). If the bit is enabled, the device aborts any ongoing refresh and does not increment the refresh counter. The controller can issue a valid command not requiring a locked DLL after a delay of tXS_ABORT. Upon exit from self refresh, the device requires a minimum of one extra REFRESH command before it is put back into self refresh mode. This requirement remains the same irrespective of the setting of the MRS bit for self refresh abort. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 154 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation Figure 92: Self Refresh Abort T0 T1 Ta0 Tb0 Tc0 Td0 Td1 Te0 Tf0 Tg0 Valid Valid Valid CK_c CK_t tCKSRX tCKSRE/tCKSRE_PAR tIS tCPDED CKE tCKESR/tCKESR_PAR ODT Valid tXS_FAST Command DES SRE SRX DES ADDR Valid 1 Valid 2 Valid 3 Valid Valid Valid tXS_ABORT tRP tXSDLL Enter Self Refresh Exit Self Refresh Don’t Care Time Break Notes: 1. Only MRS (limited to those described in the SELF REFRESH Operation section), ZQCS, or ZQCL commands are allowed. 2. Valid commands not requiring a locked DLL with self refresh abort mode enabled in the mode register. 3. Valid commands requiring a locked DLL. Self Refresh Exit with NOP Command Exiting self refresh mode using the NO OPERATION command (NOP) is allowed under a specific system application. This special use of NOP allows for a common command/address bus between active DRAM devices and DRAM(s) in maximum power saving mode. Self refresh mode may exit with NOP commands provided: s The device entered self refresh mode with CA parity, CAL, and gear-down disabled. s tMPX_S and tMPX_LH are satisfied. s NOP commands are only issued during tMPX_LH window. No other command is allowed during the tMPX_LH window after an SELF REFRESH EXIT (SRX) command is issued. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 155 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM SELF REFRESH Operation Figure 93: Self Refresh Exit with NOP Command Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tc0 Tc1 Tc2 Tc3 Tc4 Td0 Td1 Td2 Td3 Te0 Te1 CK_c CK_t t CKSRX CKE ODT Valid t t MPX_S MPX_LH CS_n Note 1, 2 Note 3 Command SRX NOP NOP NOP NOP ADDR Valid Valid Valid Valid Valid DES DES DES DES DES Valid Valid t t DES Valid Valid XS XS + t XSDLL Don’t Care CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 156 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Power-Down Mode Power-down is synchronously entered when CKE is registered LOW (along with a DESELECT command). CKE is not allowed to go LOW when the following operations are in progress: MRS command, MPR operations, ZQCAL operations, DLL locking, or READ/WRITE operations. CKE is allowed to go LOW while any other operations, such as ROW ACTIVATION, PRECHARGE or auto precharge, or REFRESH, are in progress, but the power-down IDD specification will not be applied until those operations are complete. The timing diagrams that follow illustrate power-down entry and exit. For the fastest power-down exit timing, the DLL should be in a locked state when power-down is entered. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper READ operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well as proper DLL operation with any CKE intensive operations as long as the controller complies with DRAM specifications. During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in active power-down mode. Entering power-down deactivates the input and output buffers, excluding CK, CKE, and RESET_n. In power-down mode, DRAM ODT input buffer deactivation is based on Mode Register 5, bit 5 (MR5[5]). If it is configured to 0b, the ODT input buffer remains on and the ODT input signal must be at valid logic level. If it is configured to 1b, the ODT input buffer is deactivated and the DRAM ODT input signal may be floating and the device does not provide RTT(NOM) termination. Note that the device continues to provide RTT(Park) termination if it is enabled in MR5[8:6]. To protect internal delay on the CKE line to block the input signals, multiple DES commands are needed during the CKE switch off and on cycle(s); this timing period is defined as tCPDED. CKE LOW will result in deactivation of command and address receivers after tCPDED has expired. Table 53: Power-Down Entry Definitions DRAM Status DLL Power-Down Exit Active (a bank or more open) On Fast Precharged (all banks precharged) On Fast Relevant Parameters t XP to any valid command. t XP to any valid command. The DLL is kept enabled during precharge power-down or active power-down. In power-down mode, CKE is LOW, RESET_n is HIGH, and a stable clock signal must be maintained at the inputs of the device. ODT should be in a valid state, but all other input signals are "Don't Care." (If RESET_n goes LOW during power-down, the device will be out of power-down mode and in the reset state.) CKE LOW must be maintained until tCKE has been satisfied. Power-down duration is limited by 9 έ tREFI. The power-down state is synchronously exited when CKE is registered HIGH (along with DES command). CKE HIGH must be maintained until tCKE has been satisfied. The ODT input signal must be at a valid level when the device exits from power-down mode, independent of MR1 bit [10:8] if RTT(NOM) is enabled in the mode register. If RTT(NOM) is disabled, the ODT input signal may remain floating. A valid, executable command can be applied with power-down exit latency, tXP, after CKE goes HIGH. Power-down exit latency is defined in the AC Specifications table. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 157 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 94: Active Power-Down Entry and Exit T0 T1 T2 Valid DES DES Ta0 Ta1 Tb0 Tb1 Tc0 CK_c CK_t Command DES DES DES Valid Valid Valid tPD tIS tIH CKE tIH tCKE tIS ODT (ODT buffer enabled - MR5[5] = 0)2 Refer to ODT Power-Down Entry/Exit with ODT Buffer Disable Mode figures ODT (ODT buffer disabled - MR5[5] = 1)3 Address Valid Valid tCPDED tXP Enter power-down mode Exit power-down mode Time Break Don’t Care Notes: 1. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command. 2. ODT pin driven to a valid state; MR5[5] = 0 (normal setting). 3. ODT pin drive/float timing requirements for the ODT input buffer disable option (for additional power savings during active power-down) is described in the section for ODT Input Buffer Disable Mode for Power-Down; MR5[5] = 1. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 158 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 95: Power-Down Entry After Read and Read with Auto Precharge CK_c T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 RD or RDA DES DES DES DES DES DES DES DES Ta7 Ta8 Tb0 Tb1 DES DES Valid CK_t Command DES tIS tCPDED Valid CKE Valid Address Valid RL = AL + CL tPD DQS_t, DQS_c DQ BL8 DI b DI b+1 DI b+2 DI b+3 DQ BC4 DI n DI n+1 DI n+2 DI n+3 DI b+4 DI b+5 DI b+6 DI b+7 tRDPDEN Power-Down entry Transitioning Data Don’t Care Time Break Note: 1. DI n (or b) = data-in from column n (or b). Figure 96: Power-Down Entry After Write and Write with Auto Precharge CK_c T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE DES DES DES DES DES DES DES DES DES DES Tb1 Tb2 Tc0 Tc1 DES DES Valid CK_t Command DES tIS tCPDED Valid CKE Address Bank, Col n Valid A10 WL = AL + CWL tPD WR DQS_t, DQS_c DQ BL8 DI b DI b+1 DI b+2 DI b+3 DQ BC4 DI n DI n+1 DI n+2 DI n+3 DI b+4 DI b+5 DI b+6 DI b+7 Start internal precharge tWRAPDEN Power-Down entry Transitioning Data Time Break Don’t Care Notes: 1. DI n (or b) = data-in from column n (or b). 2. Valid commands at T0 are ACT, DES, or PRE with one bank remaining open after completion of the PRECHARGE command. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 159 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 97: Power-Down Entry After Write CK_c T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE DES DES DES DES DES DES DES DES DES DES Tb1 Tb2 Tc0 Tc1 DES DES Valid CK_t Command DES tIS tCPDED Valid CKE Address Bank, Col n Valid A10 WL = AL + CWL tPD tWR DQS_t, DQS_c DQ BL8 DI b DI b+1 DI b+2 DI b+3 DQ BC4 DI n DI n+1 DI n+2 DI n+3 DI b+4 DI b+5 DI b+6 DI b+7 tWRPDEN Power-Down entry Transitioning Data Time Break Don’t Care Note: 1. DI n (or b) = data-in from column n (or b). Figure 98: Precharge Power-Down Entry and Exit T0 T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0 DES DES DES DES DES DES Valid Valid Valid CK_c CK_t Command tCPDED tCKE tIS tIH CKE tIS tPD Enter power-down mode tXP Exit power-down mode Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 160 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 99: REFRESH Command to Power-Down Entry T0 T1 T2 Ta0 Tb0 Tb1 REF DES DES DES DES CK_c CK_t Command Address Valid tCPDED tIS tPD tCKE CKE Valid tREFPDEN Time Break Don’t Care Figure 100: Active Command to Power-Down Entry T0 T1 T2 Ta0 Tb0 Tb1 ACT DES DES DES DES CK_c CK_t Command Address Valid tCPDED tIS tPD tCKE CKE Valid tACTPDEN Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 161 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 101: PRECHARGE/PRECHARGE ALL Command to Power-Down Entry T0 T1 T2 Ta0 Tb0 Tb1 PRE or PREA DES DES DES Valid CK_c CK_t Command Address Valid tCPDED tIS tPD tCKE CKE tPREPDEN Time Break Don’t Care Figure 102: MRS Command to Power-Down Entry T0 T1 Ta0 Ta1 Command MRS DES DES DES Address Valid Tb0 Tb1 CK_c CK_t DES tCPDED tIS tPD tCKE CKE Valid tMRSPDEN Time Break Don’t Care 0OWER $OWN#LARIFICATIONSn#ASE When CKE is registered LOW for power-down entry, tPD (MIN) must be satisfied before CKE can be registered HIGH for power-down exit. The minimum value of parameter tPD (MIN) is equal to the minimum value of parameter tCKE (MIN) as shown in the Timing Parameters by Speed Bin table. A detailed example of Case 1 follows. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 162 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 103: 0OWER $OWN%NTRY%XIT#LARIFICATIONSn#ASE T0 T1 T2 Ta0 Valid DES DES Ta1 Tb0 Tb1 Tb2 CK_c CK_t Command DES DES DES DES tPD tPD tIH tIS tIS CKE tIS tIH Address tCKE Valid tCPDED tCPDED Enter power-down mode Exit power-down mode Enter power-down mode Time Break Don’t Care Power-Down Entry, Exit Timing with CAL Command/Address latency is used and additional timing restrictions are required when entering power-down, as noted in the following figures. Figure 104: Active Power-Down Entry and Exit Timing with CAL T0 T1 Ta0 Ta1 Ta2 DES DES Valid DES DES Tb0 Tb1 Tc0 Tc1 Td0 Td1 Te0 DES DES DES Valid CK_c CK_t CS_n Command Address DES DES Valid t CAL Valid tIH t CPDED t IS t XP t IH t PD t CAL t IS CKE Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 163 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Power-Down Mode Figure 105: REFRESH Command to Power-Down Entry with CAL T0 T1 Ta0 Tb0 Tb1 Tc0 DES DES REF DES DES DES Tc1 Td0 Td1 Te0 Te1 Tf0 DES DES DES Valid CK_c CK_t CS_n Command Address DES Valid t CAL Valid t CPDED t REFPDEN t IS CKE t XP t PD t IH t CAL t IS tIH Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 164 Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down ODT Input Buffer Disable Mode for Power-Down DRAM does not provide RTT_NOM termination during power-down when ODT input buffer deactivation mode is enabled in MR5 bit A5. To account for DRAM internal delay on CKE line to disable the ODT buffer and block the sampled output, the host controller must continuously drive ODT to either low or high when entering power down (from tDODTLoff+1 prior to CKE low till tCPDED after CKE low). The ODT signal is allowed to float after tCPDEDmin has expired. In this mode, RTT_NOM termination corresponding to sampled ODT at the input when CKE is registered low (and tANPD before that) may be either RTT_NOM or RTT_PARK. tANPD is equal to (WL-1) and is counted backwards from PDE. Figure 106: ODT Power-Down Entry with ODT Buffer Disable Mode diff_CK CKE tDODTLoff tCPDED +1 (MIN) Floating ODT tADC DRAM_RTT_sync (DLL enabled) CA parity disabled RTT(NOM) DRAM_RTT_async (DLL disabled) RTT(NOM) RTT(Park) tCPDED DODTLoff (MIN) + tADC (MAX) RTT(Park) tAONAS (MIN) tCPDED CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN (MIN) 165 (MIN) + tAOFAS (MAX) Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ODT Input Buffer Disable Mode for Power-Down Figure 107: ODT Power-Down Exit with ODT Buffer Disable Mode diff_CK CKE ODT_A (DLL enabled) Floating tADC tXP RTT(Park) DRAM_RTT_A RTT(NOM) DODTLon ODT_B (DLL disabled) (MAX) tADC (MIN) Floating tXP DRAM_RTT_B RTT(Park) tAONAS RTT(NOM) (MIN) tAOFAS CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN (MAX) 166 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CRC Write Data Feature CRC Write Data The CRC write data feature takes the CRC generated data from the DRAM controller and compares it to the internally CRC generated data and determines whether the two match (no CRC error) or do not match (CRC error). Figure 108: CRC Write Data Operation DRAM DRAM Controller Data CRC engine Data CRC engine CRC Code Data CRC Code CRC Code Compare CRC WRITE CRC DATA Operation A DRAM controller generates a CRC checksum using a 72-bit CRC tree and forms the write data frames, as shown in the following CRC data mapping tables for the x4, x8, and x16 configurations. A x4 device has a CRC tree with 32 input data bits used, and the remaining upper 40 bits D[71:32] being 1s. A x8 device has a CRC tree with 64 input data bits used, and the remaining upper 8 bits dependant upon whether DM_n/DBI_n is used (1s are sent when not used). A x16 device has two identical CRC trees each, one for the lower byte and one for the upper byte, with 64 input data bits used by each, and the remaining upper 8 bits on each byte dependant upon whether DM_n/DBI_n is used (1s are sent when not used). For a x8 and x16 DRAMs, the DRAM memory controller must send 1s in transfer 9 location whether or not DM_n/DBI_n is used. The DRAM checks for an error in a received code word D[71:0] by comparing the received checksum against the computed checksum and reports errors using the ALERT_n signal if there is a mismatch. The DRAM can write data to the DRAM core without waiting for the CRC check for full writes when DM is disabled. If bad data is written to the DRAM core, the DRAM memory controller will try to overwrite the bad data with good data; this means the DRAM controller is responsible for data coherency when DM is disabled. However, in the case where both CRC and DM are enabled via MRS (that is, persistent mode), the DRAM will not write bad data to the core when a CRC error is detected. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 167 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature DBI_n and CRC Both Enabled The DRAM computes the CRC for received written data D[71:0]. Data is not inverted back based on DBI before it is used for computing CRC. The data is inverted back based on DBI before it is written to the DRAM core. DM_n and CRC Both Enabled When both DM and write CRC are enabled in the DRAM mode register, the DRAM calculates CRC before sending the write data into the array. If there is a CRC error, the DRAM blocks the WRITE operation and discards the data. If a CRC error is encountered from a WRITE with auto precharge (WRA), the DRAM will not block the precharge. The Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group and the WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different BankGroup figures in the WRITE Operation section show timing differences when DM is enabled. DM_n and DBI_n Conflict During Writes with CRC Enabled Both write DBI_n and DM_n can not be enabled at the same time; read DBI_n and DM_n can be enabled at the same time. CRC and Write Preamble Restrictions When write CRC is enabled: s And 1tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 4 clocks is not allowed. s And 2tCK WRITE preamble mode is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed. CRC Simultaneous Operation Restrictions When write CRC is enabled, neither MPR writes nor per-DRAM mode is allowed. CRC Polynomial The CRC polynomial used by DDR4 is the ATM-8 HEC, X8 + X2 + X1 + 1. A combinatorial logic block implementation of this 8-bit CRC for 72 bits of data includes 272 two-input XOR gates contained in eight 6-XOR-gate-deep trees. The CRC polynomial and combinatorial logic used by DDR4 is the same as used on GDDR5. The error coverage from the DDR4 polynomial used is shown in the following table. Table 54: CRC Error Detection Coverage Error Type Detection Capability Random single-bit errors 100% Random double-bit errors 100% Random odd count errors 100% Random multibit UI vertical column error detection excluding DBI bits 100% CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 168 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CRC Combinatorial Logic Equations module CRC8_D72; // polynomial: (0 1 2 8) // data width: 72 // convention: the first serial data bit is D[71] //initial condition all 0 implied // "^" = XOR function [7:0] nextCRC8_D72; input [71:0] Data; input [71:0] D; reg [7:0] CRC; begin D = Data; CRC[0] = D[69]^D[68]^D[67]^D[66]^D[64]^D[63]^D[60]^D[56]^D[54]^D[53]^D[52]^D[50]^D[49]^D[48]^D[45] ^D[43]^D[40]^D[39]^D[35]^D[34]^D[31]^D[30]^D[28]^D[23]^D[21]^D[19]^D[18]^D[16]^D[14]^D[1 2]^D[8]^D[7]^D[6]^D[0]; CRC[1] = D[70]^D[66]^D[65]^D[63]^D[61]^D[60]^D[57]^D[56]^D[55]^D[52]^D[51]^D[48]^D[46]^D[45]^D[44] ^D[43]^D[41]^D[39]^D[36]^D[34]^D[32]^D[30]^D[29]^D[28]^D[24]^D[23]^D[22]^D[21]^D[20]^D[1 8]^D[17]^D[16]^D[15]^D[14]^D[13]^D[12]^D[9]^D[6]^D[1]^D[0]; CRC[2] = D[71]^D[69]^D[68]^D[63]^D[62]^D[61]^D[60]^D[58]^D[57]^D[54]^D[50]^D[48]^D[47]^D[46]^D[44] ^D[43]^D[42]^D[39]^D[37]^D[34]^D[33]^D[29]^D[28]^D[25]^D[24]^D[22]^D[17]^D[15]^D[13]^D[1 2]^D[10]^D[8]^D[6]^D[2]^D[1]^D[0]; CRC[3] = D[70]^D[69]^D[64]^D[63]^D[62]^D[61]^D[59]^D[58]^D[55]^D[51]^D[49]^D[48]^D[47]^D[45]^D[44] ^D[43]^D[40]^D[38]^D[35]^D[34]^D[30]^D[29]^D[26]^D[25]^D[23]^D[18]^D[16]^D[14]^D[13]^D[1 1]^D[9]^D[7]^D[3]^D[2]^D[1]; CRC[4] = D[71]^D[70]^D[65]^D[64]^D[63]^D[62]^D[60]^D[59]^D[56]^D[52]^D[50]^D[49]^D[48]^D[46]^D[45] ^D[44]^D[41]^D[39]^D[36]^D[35]^D[31]^D[30]^D[27]^D[26]^D[24]^D[19]^D[17]^D[15]^D[14]^D[1 2]^D[10]^D[8]^D[4]^D[3]^D[2]; CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 169 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CRC[5] = D[71]^D[66]^D[65]^D[64]^D[63]^D[61]^D[60]^D[57]^D[53]^D[51]^D[50]^D[49]^D[47]^D[46]^D[45] ^D[42]^D[40]^D[37]^D[36]^D[32]^D[31]^D[28]^D[27]^D[25]^D[20]^D[18]^D[16]^D[15]^D[13]^D[1 1]^D[9]^D[5]^D[4]^D[3]; CRC[6] = D[67]^D[66]^D[65]^D[64]^D[62]^D[61]^D[58]^D[54]^D[52]^D[51]^D[50]^D[48]^D[47]^D[46]^D[43] ^D[41]^D[38]^D[37]^D[33]^D[32]^D[29]^D[28]^D[26]^D[21]^D[19]^D[17]^D[16]^D[14]^D[12]^D[1 0]^D[6]^D[5]^D[4]; CRC[7] = D[68]^D[67]^D[66]^D[65]^D[63]^D[62]^D[59]^D[55]^D[53]^D[52]^D[51]^D[49]^D[48]^D[47]^D[44] ^D[42]^D[39]^D[38]^D[34]^D[33]^D[30]^D[29]^D[27]^D[22]^D[20]^D[18]^D[17]^D[15]^D[13]^D[1 1]^D[7]^D[6]^D[5]; nextCRC8_D72 = CRC; Burst Ordering for BL8 DDR4 supports fixed WRITE burst ordering [A2:A1:A0 = 0:0:0] when write CRC is enabled in BL8 (fixed). CRC Data Bit Mapping Table 55: CRC Data Mapping for x4 Devices, BL8 Transfer Function 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 CRC4 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 CRC5 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 CRC6 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 CRC7 Table 56: CRC Data Mapping for x8 Devices, BL8 Transfer Function 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 170 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature Table 56: CRC Data Mapping for x8 Devices, BL8 (Continued) Transfer Function 0 1 2 3 4 5 6 7 8 9 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 DM_n/DB I_n D64 D65 D66 D67 D68 D69 D70 D71 1 1 A x16 device is treated as two x8 devices; a x16 device will have two identical CRC trees implemented. CRC[7:0] covers data bits D[71:0], and CRC[15:8] covers data bits D[143:72]. Table 57: CRC Data Mapping for x16 Devices, BL8 Transfer Function 0 1 2 3 4 5 6 7 8 9 DQ0 D0 D1 D2 D3 D4 D5 D6 D7 CRC0 1 DQ1 D8 D9 D10 D11 D12 D13 D14 D15 CRC1 1 DQ2 D16 D17 D18 D19 D20 D21 D22 D23 CRC2 1 DQ3 D24 D25 D26 D27 D28 D29 D30 D31 CRC3 1 DQ4 D32 D33 D34 D35 D36 D37 D38 D39 CRC4 1 DQ5 D40 D41 D42 D43 D44 D45 D46 D47 CRC5 1 DQ6 D48 D49 D50 D51 D52 D53 D54 D55 CRC6 1 DQ7 D56 D57 D58 D59 D60 D61 D62 D63 CRC7 1 LDM_n/LD BI_n D64 D65 D66 D67 D68 D69 D70 D71 1 1 DQ8 D72 D73 D74 D75 D76 D77 D78 D79 CRC8 1 DQ9 D80 D81 D82 D83 D84 D85 D86 D87 CRC9 1 DQ10 D88 D89 D90 D91 D92 D93 D94 D95 CRC10 1 DQ11 D96 D97 D98 D99 D100 D101 D102 D103 CRC11 1 DQ12 D104 D105 D106 D107 D108 D109 D110 D111 CRC12 1 DQ13 D112 D113 D114 D115 D116 D117 D118 D119 CRC13 1 DQ14 D120 D121 D122 D123 D124 D125 D126 D127 CRC14 1 DQ15 D128 D129 D130 D131 D132 D133 D134 D135 CRC15 1 UDM_n/U DBI_n D136 D137 D138 D139 D140 D141 D142 D143 1 1 CRC Enabled With BC4 If CRC and BC4 are both enabled, then address bit A2 is used to transfer critical data first for BC4 writes. CRC with BC4 Data Bit Mapping For a x4 device, the CRC tree inputs are 16 data bits, and the inputs for the remaining bits are 1. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 171 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree. Table 58: CRC Data Mapping for x4 Devices, BC4 Transfer Function 0 1 2 3 4 5 6 7 8 9 A2 = 0 DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 CRC4 DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 CRC5 DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 CRC6 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 CRC7 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 CRC4 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 CRC5 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 CRC6 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 CRC7 For a x8 device, the CRC tree inputs are 36 data bits. When A2 = 0, the input bits D[67:64]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64]) are 1. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs to D[11:8], and so forth, for the CRC tree. The input bits D[71:68]) are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68]) are 1. Table 59: CRC Data Mapping for x8 Devices, BC4 Transfer Function 0 1 2 3 4 5 6 7 8 9 A2 = 0 DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1 DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1 DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1 DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1 DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1 DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1 DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1 DM_n/DBI_n D64 D65 D66 D67 1 1 1 1 1 1 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 172 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature Table 59: CRC Data Mapping for x8 Devices, BC4 (Continued) Transfer Function 0 1 2 3 4 5 6 7 8 9 DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1 DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1 DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1 DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1 DM_n/DBI_n D68 D69 D70 D71 1 1 1 1 1 1 There are two identical CRC trees for x16 devices, each have CRC tree inputs of 36 bits. When A2 = 0, input bits D[67:64] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[67:64] are 1s. The input bits D[139:136] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[139:136] are 1s. When A2 = 1, data bits D[7:4] are used as inputs for D[3:0], D[15:12] are used as inputs for D[11:8], and so forth, for the CRC tree. Input bits D[71:68] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[71:68] are 1s. The input bits D[143:140] are used if DBI_n or DM_n functions are enabled; if DBI_n and DM_n are disabled, then D[143:140] are 1s. Table 60: CRC Data Mapping for x16 Devices, BC4 Transfer Function 0 1 2 3 4 5 6 7 8 9 A2 = 0 DQ0 D0 D1 D2 D3 1 1 1 1 CRC0 1 DQ1 D8 D9 D10 D11 1 1 1 1 CRC1 1 DQ2 D16 D17 D18 D19 1 1 1 1 CRC2 1 DQ3 D24 D25 D26 D27 1 1 1 1 CRC3 1 DQ4 D32 D33 D34 D35 1 1 1 1 CRC4 1 DQ5 D40 D41 D42 D43 1 1 1 1 CRC5 1 DQ6 D48 D49 D50 D51 1 1 1 1 CRC6 1 DQ7 D56 D57 D58 D59 1 1 1 1 CRC7 1 LDM_n/LDBI_ n D64 D65 D66 D67 1 1 1 1 1 1 DQ8 D72 D73 D74 D75 1 1 1 1 CRC8 1 DQ9 D80 D81 D82 D83 1 1 1 1 CRC9 1 DQ10 D88 D89 D90 D91 1 1 1 1 CRC10 1 DQ11 D96 D97 D98 D99 1 1 1 1 CRC11 1 DQ12 D104 D105 D106 D107 1 1 1 1 CRC12 1 DQ13 D112 D113 D114 D115 1 1 1 1 CRC13 1 DQ14 D120 D121 D122 D123 1 1 1 1 CRC14 1 DQ15 D128 D129 D130 D131 1 1 1 1 CRC15 1 UDM_n/UDBI _n D136 D137 D138 D139 1 1 1 1 1 1 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 173 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature Table 60: CRC Data Mapping for x16 Devices, BC4 (Continued) Transfer Function 0 1 2 3 4 5 6 7 8 9 A2 = 1 DQ0 D4 D5 D6 D7 1 1 1 1 CRC0 1 DQ1 D12 D13 D14 D15 1 1 1 1 CRC1 1 DQ2 D20 D21 D22 D23 1 1 1 1 CRC2 1 DQ3 D28 D29 D30 D31 1 1 1 1 CRC3 1 DQ4 D36 D37 D38 D39 1 1 1 1 CRC4 1 DQ5 D44 D45 D46 D47 1 1 1 1 CRC5 1 DQ6 D52 D53 D54 D55 1 1 1 1 CRC6 1 DQ7 D60 D61 D62 D63 1 1 1 1 CRC7 1 LDM_n/LDBI_ n D68 D69 D70 D71 1 1 1 1 1 1 DQ8 D76 D77 D78 D79 1 1 1 1 CRC8 1 DQ9 D84 D85 D86 D87 1 1 1 1 CRC9 1 DQ10 D92 D93 D94 D95 1 1 1 1 CRC10 1 DQ11 D100 D101 D102 D103 1 1 1 1 CRC11 1 DQ12 D108 D109 D110 D111 1 1 1 1 CRC12 1 DQ13 D116 D117 D118 D119 1 1 1 1 CRC13 1 DQ14 D124 D125 D126 D127 1 1 1 1 CRC14 1 DQ15 D132 D133 D134 D135 1 1 1 1 CRC15 1 UDM_n/UDBI _n D140 D141 D142 D143 1 1 1 1 1 1 CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 The following example is of a CRC tree when x8 is used in BC4 mode (x4 and x16 CRC trees have similar differences). CRC[0], A2=0 = 1^1^D[67]^D[66]^D[64]^1^1^D[56]^1^1^1^D[50]^D[49]^D[48]^1^D[43]^D[40]^1^D[35]^D[34]^1^1^1^1^1^ D[19]^D[18]^D[16]^1^1^D[8] ^1^1^ D[0] ; CRC[0], A2=1= 1^1^D[71]^D[70]^D[68]^1^1^D[60]^1^1^1^D[54]^D[53]^D[52]^1^D[47]^D[44]^1^D[39]^D[38]^1^1^1^1^1^ D[23]^D[22]^D[20]^1^1^D[12]^1^1^D[4] ; CRC[1], A2=0 = 1^D[66]^D[65]^1^1^1^D[57]^D[56]^1^1^D[51]^D[48]^1^1^1^D[43]^D[41]^1^1^D[34]^D[32]^1^1^1^D[24]^ 1^1^1^1^D[18]^D[17]^D[16]^1^1^1^1^D[9] ^1^ D[1]^D[0]; CRC[1], A2=1 = 1^D[70]^D[69]^1^1^1^D[61]^D[60]^1^1^D[55]^D[52]^1^1^1^D[47]^D[45]^1^1^D[38]^D[36]^1^1^1^D[28]^ 1^1^1^1^D[22]^D[21]^D[20]^1^1^1^1^D[13]^1^D[5]^D[4]; CRC[2], A2=0= 1^1^1^1^1^1^1^D[58]^D[57]^1^D[50]^D[48]^1^1^1^D[43]^D[42]^1^1^D[34]^D[33]^1^1^D[25]^D[24]^1^D[ 17]^1^1^1^D[10]^D[8] ^1^D[2]^D[1]^D[0]; CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 174 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature CRC[2], A2=1= 1^1^1^1^1^1^1^D[62]^D[61]^1^D[54]^D[52]^1^1^1^D[47]^D[46]^1^1^D[38]^D[37]^1^1^D[29]^D[28]^1^D[ 21]^1^1^1^D[14]^D12]^1^D[6]^D[5]^D[4]; CRC[3], A2=0 = 1^1^D[64]^1^1^1^D[59]^D[58]^1^D[51]^D[49]^D[48]^1^1^1^D[43]^D[40]^1^D[35]^D[34]^1^1^D[26]^D[25] ^1^D[18]^D[16]^1^1^D[11]^D[9] ^1^D[3]^D[2]^D[1]; CRC[3], A2=1 = 1^1^D[68]^1^1^1^D[63]^D[62]^1^D[55]^D[53]^D[52]^1^1^1^D[47]^D[44]^1^D[39]^D[38]^1^1^D[30]^D[29] ^1^D[22]^D[20]^1^1^D[15]^D[13]^1^D[7]^D[6]^D[5]; CRC[4], A2=0 = 1^1^D[65]^D[64]^1^1^1^D[59]^D[56]^1^D[50]^D[49]^D[48]^1^1^1^D[41]^1^1^D[35]^1^1^D[27]^D[26]^D[2 4]^D[19]^D[17]^1^1^1^D[10]^D[8] ^1^D[3]^D[2]; CRC[4], A2=1 = 1^1^D[69]^D[68]^1^1^1^D[63]^D[60]^1^D[54]^D[53]^D[52]^1^1^1^D[45]^1^1^D[39]^1^1^D[31]^D[30]^D[2 8]^D[23]^D[21]^1^1^1^D[14]^D[12]^1^D[7]^D[6]; CRC[5], A2=0 = 1^D[66]^D[65]^D[64]^1^1^1^D[57]^1^D[51]^D[50]^D[49]^1^1^1^D[42]^D[40]^1^1^D[32]^1^1^D[27]^D[25]^1 ^D[18]^D[16]^1^1^D[11]^D[9] ^1^1^D[3]; CRC[5], A2=1 = 1^D[70]^D[69]^D[68]^1^1^1^D[61]^1^D[55]^D[54]^D[53]^1^1^1^D[46]^D[44]^1^1^D[36]^1^1^D[31]^D[29] ^1^D[22]^D[20]^1^1^D[15]^D[13]^1^1^D[7]; CRC[6], A2=0 = D[67]^D[66]^D[65]^D[64]^1^1^D[58]^1^1^D[51]^D[50]^D[48]^1^1^D[43]^D[41]^1^1^D[33]^D[32]^1^1^D[2 6]^1^D[19]^D[17]^D[16]^1^1^D[10]^1^1^1; CRC[6], A2=1 = D[71]^D[70]^D[69]^D[68]^1^1^D[62]^1^1^D[55]^D[54]^D[52]^1^1^D[47]^D[45]^1^1^D[37]^D[36]^1^1^D[3 0]^1^D[23]^D[21]^D[20]^1^1^D[14]^1^1^1; CRC[7], A2=0= 1^D[67]^D[66]^D[65]^1^1^D[59]^1^1^1^D[51]^D[49]^D[48]^1^1^D[42]^1^1^D[34]^D[33]^1^1^D[27]^1^1^ D[18]^D[17]^1^1^D[11]^1^1^1; CRC[7], A2=1 = 1^D[71]^D[70]^D[69]^1^1^D[63]^1^1^1^D[55]^D[53]^D[52]^1^1^D[46]^1^1^D[38]^D[37]^1^1^D[31]^1^1^ D[22]^D[21]^1^1^D[15]^1^1^1; CRC Error Handling The CRC error mechanism shares the same ALERT_n signal as CA parity for reporting write errors to the DRAM. The controller has two ways to distinguish between CRC errors and CA parity errors: 1) Read DRAM mode/MPR registers, and 2) Measure time ALERT_n is LOW. To speed up recovery for CRC errors, CRC errors are only sent back as a "short" pulse; the maximum pulse width is roughly ten clocks (unlike CA parity where ALERT_n is LOW longer than 45 clocks). The ALERT_n LOW could be longer than the maximum limit at the controller if there are multiple CRC errors as the ALERT_n signals are connected by a daisy chain bus. The latency to ALERT_n signal is defined as tCRC_ALERT in the following figure. The DRAM will set the error status bit located at MR5[3] to a 1 upon detecting a CRC error, which will subsequently set the CRC error status flag in the MPR error log HIGH (MPR Page1, MPR3[7]). The CRC error status bit (and CRC error status flag) remains set at 1 until the DRAM controller clears the CRC error status bit using an MRS command to set MR5[3] to a 0. The DRAM controller, upon seeing an error as a pulse width, will retry the write transactions. The controller should consider the worst-case CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 175 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature delay for ALERT_n (during initialization) and backup the transactions accordingly. The DRAM controller may also be made more intelligent and correlate the write CRC error to a specific rank or a transaction. Figure 109: CRC Error Reporting CK_c CK_t DQIN T0 T1 Dx T2 Dx+1 Dx+2 Dx+3 T3 Dx+4 T4 Dx+5 Dx+6 T5 Dx+7 CRCy T6 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 1 CRC ALERT_PW (MAX) tCRC_ALERT ALERT_n CRC ALERT_PW (MIN) Transition Data Don’t Care Notes: 1. D[71:1] CRC computed by DRAM did not match CRC[7:0] at T5 and started error generating process at T6. 2. CRC ALERT_PW is specified from the point where the DRAM starts to drive the signal LOW to the point where the DRAM driver releases and the controller starts to pull the signal up. 3. Timing diagram applies to x4, x8, and x16 devices. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 176 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN CRC Write Data Flow Diagram Figure 110: CA Parity Flow Diagram DRAM write process start MR2 12 enable CRC MR5 3 set CRC error clear to 0 MR5 10 enable/disable DM MR3[10:9] WCL if DM enabled Capture data CRC enabled Persistent mode enabled Yes DRAM CRC same as controller CRC Yes Yes No No Transfer data internally Transfer data internally Transfer Data Internally DRAM CRC same as controller CRC Yes CA error Yes No No No MR5[3] = 0 at WRITE ALERT_n LOW 6 to 10 CKs ALERT_n HIGH No MR5[A3] and PAGE1 MPR3[7] remain set to 1 Yes MR5[3] = 0 at WRITE Set error flag MR5[A3] = 1 ALERT_n LOW 6 to 10 CKs Set error status PAGE1 MPR3[7] = 1 ALERT_n HIGH No MR5[A3] and PAGE1 MPR3[7] remain set to 1 Yes Set error flag MR5[A3] = 1 Set error status PAGE1 MPR3[7] = 1 177 WRITE burst completed WRITE burst completed WRITE burst completed WRITE burst completed WRITE burst rejected Bad data not written MR5 3 reset to 0 if desired 8Gb: x4, x8, x16 DDR4 SDRAM CRC Write Data Feature Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. Bad data written MR5 3 reset to 0 if desired WRITE burst completed 8Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion Data Bus Inversion The DATA BUS INVERSION (DBI) function is supported only for x8 and x16 configurations (it is not supported on x4 devices). DBI opportunistically inverts data bits, and in conjunction with the DBI_n I/O, less than half of the DQs will switch LOW for a given DQS strobe edge. The DBI function shares a common pin with the DATA MASK (DM) and TDQS functions. The DBI function applies to either or both READ and WRITE operations: Write DBI cannot be enabled at the same time the DM function is enabled, and DBI is not allowed during MPR READ operation. Valid configurations for TDQS, DM, and DBI functions are shown below. Table 61: DBI vs. DM vs. TDQS Function Matrix Read DBI Write DBI Data Mask (DM) TDQS (x8 only) Enabled (or Disabled) MR5[12]=1 (or MR5[12] = 0) Disabled MR5[11] = 0 Disabled MR5[10] = 0 Disabled MR1[11] = 0 Enabled MR5[11] = 1 Disabled MR5[10] = 0 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled MR5[10] = 1 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Disabled MR5[10] = 0 Enabled MR1[11] = 1 Disabled MR5[12] = 0 DBI During a WRITE Operation If DBI_n is sampled LOW on a given byte lane during a WRITE operation, the DRAM inverts write data received on the DQ inputs prior to writing the internal memory array. If DBI_n is sampled HIGH on a given byte lane, the DRAM leaves the data received on the DQ inputs noninverted. The write DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function). Table 62: DBI Write, DQ Frame Format (x8) Transfer 0 1 2 3 4 5 6 7 DQ[7:0] Function Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DM_n or DBI_n DM0 or DBI0 DM1 or DBI1 DM2 or DBI2 DM3 or DBI3 DM4 or DBI4 DM5 or DBI5 DM6 or DBI6 DM7 or DBI7 Table 63: DBI Write, DQ Frame Format (x16) Transfer, Lower (L) and Upper(U) Function 0 1 2 3 4 5 6 7 LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 LDM_n or LDBI_n LDM0 or LDBI0 LDM1 or LDBI1 LDM2 or LDBI2 LDM3 or LDBI3 LDM4 or LDBI4 LDM5 or LDBI5 LDM6 or LDBI6 LDM7 or LDBI7 DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 UDM0 or UDBI0 UDM1 or UDBI1 UDM2 or UDBI2 UDM3 or UDBI3 UDM4 or UDBI4 UDM5 or UDBI5 UDM6 or UDBI6 UDM7 or UDBI7 DQ[7:0] UDM_n or UDBI_n CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 178 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Data Bus Inversion DBI During a READ Operation If the number of 0 data bits within a given byte lane is greater than four during a READ operation, the DRAM inverts read data on its DQ outputs and drives the DBI_n pin LOW; otherwise, the DRAM does not invert the read data and drives the DBI_n pin HIGH. The read DQ frame format is shown below for x8 and x16 configurations (the x4 configuration does not support the DBI function). Table 64: DBI Read, DQ Frame Format (x8) Transfer Byte Function DQ[7:0] DBI_n 0 1 2 3 4 5 6 7 Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DBI0 DBI1 DBI2 DBI3 DBI4 DBI5 DBI6 DBI7 Table 65: DBI Read, DQ Frame Format (x16) Transfer Byte, Lower (L) and Upper(U) Function 0 1 2 3 4 5 6 7 DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 LDBI_n LDBI0 LDBI1 LDBI2 LDBI3 LDBI4 LDBI5 LDBI6 LDBI7 UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 UDBI0 UDBI1 UDBI2 UDBI3 UDBI4 UDBI5 UDBI6 UDBI7 DQ[15:8] UDBI_n CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 179 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Data Mask Data Mask The DATA MASK (DM) function, also described as PARTIAL WRITE, is supported only for x8 and x16 configurations (it is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function applies only to WRITE operations and cannot be enabled at the same time the WRITE DBI function is enabled. The valid configurations for the TDQS, DM, and DBI functions are shown here. Table 66: DM vs. TDQS vs. DBI Function Matrix Data Mask (DM) TDQS (x8 only) Write DBI Read DBI Enabled MR5[10] = 1 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled or Disabled MR5[12] = 1 or MR5[12] = 0 Disabled MR5[10] = 0 Enabled MR1[11] = 1 Disabled MR5[11] = 0 Disabled MR5[12] = 0 Disabled MR1[11] = 0 Enabled MR5[11] = 1 Enabled or Disabled MR5[12] = 1 or MR5[12] = 0 Disabled MR1[11] = 0 Disabled MR5[11] = 0 Enabled (or Disabled) MR5[12] = 1 (or MR5[12] = 0) When enabled, the DM function applies during a WRITE operation. If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core. The DQ frame format for x8 and x16 configurations is shown below. If both CRC write and DM are enabled (via MRS), the CRC will be checked and valid prior to the DRAM writing data into the DRAM core. If a CRC error occurs while the DM feature is enabled, CRC write persistent mode will be enabled and data will not be written into the DRAM core. In the case of CRC write enabled and DM disabled (via MRS), that is, CRC write nonpersistent mode, data is written to the DRAM core even if a CRC error occurs. Table 67: Data Mask, DQ Frame Format (x8) Transfer Function 0 1 2 3 4 5 6 7 DQ[7:0] Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 DM_n or DBI_n DM0 or DBI0 DM1 or DBI1 DM2 or DBI2 DM3 or DBI3 DM4 or DBI4 DM5 or DBI5 DM6 or DBI6 DM7 or DBI7 Table 68: Data Mask, DQ Frame Format (x16) Transfer, Lower (L) and Upper (U) Function 0 1 2 3 4 5 6 7 DQ[7:0] LByte 0 LByte 1 LByte 2 LByte 3 LByte 4 LByte 5 LByte 6 LByte 7 LDM_n or LDBI_n LDM0 or LDBI0 LDM1 or LDBI1 LDM2 or LDBI2 LDM3 or LDBI3 LDM4 or LDBI4 LDM5 or LDBI5 LDM6 or LDBI6 LDM7 or LDBI7 DQ[15:8] UByte 0 UByte 1 UByte 2 UByte 3 UByte 4 UByte 5 UByte 6 UByte 7 UDM_n or UDBI_n UDM0 or UDBI0 UDM1 or UDBI1 UDM2 or UDBI2 UDM3 or UDBI3 UDM4 or UDBI4 UDM5 or UDBI5 UDM6 or UDBI6 UDM7 or UDBI7 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 180 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles Programmable Preamble Modes and DQS Postambles The device supports programmable WRITE and READ preamble modes, either the normal 1tCK preamble mode or special 2tCK preamble mode. The 2tCK preamble mode places special timing constraints on many operational features as well as being supported for data rates of DDR4-2400 and faster. The WRITE preamble 1tCK or 2tCK mode can be selected independently from READ preamble 1tCK or 2tCK mode. READ preamble training is also supported; this mode can be used by the DRAM controller to train or "read level" the DQS receivers. There are tCCD restrictions under some circumstances: s When 2tCK READ preamble mode is enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed. s When 2tCK WRITE preamble mode is enabled and write CRC is not enabled, a tCCD_S or tCCD_L of 5 clocks is not allowed. s When 2tCK WRITE preamble mode is enabled and write CRC is enabled, a tCCD_S or tCCD_L of 6 clocks is not allowed. WRITE Preamble Mode MR4[12] = 0 selects 1tCK WRITE preamble mode while MR4[12] = 1 selects 2tCK WRITE preamble mode. Examples are shown in the figures below. Figure 111: 1tCK vs. 2tCK WRITE Preamble Mode 1tCK Mode WR WL CK_c CK_t Preamble DQS_t, DQS_c DQ D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2tCK Mode WR WL CK_c CK_t Preamble DQS_t, DQS_c DQ CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 181 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles CWL has special considerations when in the 2tCK WRITE preamble mode. The CWL value selected in MR2[5:3], as seen in table below, requires at least one additional clock when the primary CWL value and 2tCK WRITE preamble mode are used; no additional clocks are required when the alternate CWL value and 2tCK WRITE preamble mode are used. Table 69: CWL Selection CWL - Primary Choice CWL - Alternate Choice Speed Bin 1tCK Preamble 2tCK Preamble 1tCK Preamble 2tCK Preamble DDR4-1600 9 N/A 11 N/A DDR4-1866 10 N/A 12 N/A DDR4-2133 11 N/A 14 N/A DDR4-2400 12 14 16 16 DDR4-2666 14 16 18 18 DDR4-2933 16 18 20 20 DDR4-3200 16 18 20 20 Note: 1. CWL programmable requirement for MR2[5:3]. When operating in 2tCK WRITE preamble mode, tWTR (command based) and tWR (MR0[11:9]) must be programmed to a value 1 clock greater than the tWTR and tWR setting normally required for the applicable speed bin to be JEDEC compliant; however, Micron's DDR4 DRAMs do not require these additional tWTR and tWR clocks. The CAS_n-to-CAS_n command delay to either a different bank group (tCCD_S) or the same bank group (tCCD_L) have minimum timing requirements that must be satisfied between WRITE commands and are stated in the Timing Parameters by Speed Bin tables. Figure 112: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 4 1tCK Mode CMD WRITE WRITE CK_c CK_t tCCD =4 WL DQS_t, DQS_c Preamble D0 DQ 2tCK D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D1 D2 D3 D4 D5 D6 D7 D0 D1 Mode CMD WRITE WRITE CK_c CK_t tCCD DQS_t, DQS_c =4 WL Preamble D0 DQ CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 182 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles Figure 113: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 5 1tCK Mode CMD WRITE WRITE CK_c CK_t tCCD =5 WL DQS_t, DQS_c Preamble Preamble D0 DQ D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 2tCK Mode: tCCD = 5 is not allowed in 2tCK mode. Note: 1. t CCD_S and tCCD_L = 5 tCKs is not allowed when in 2tCK WRITE preamble mode. Figure 114: 1tCK vs. 2tCK WRITE Preamble Mode, tCCD = 6 1tCK Mode CMD WRITE WRITE CK_c CK_t tCCD =6 WL DQS_t, DQS_c Preamble Preamble D0 DQ D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D0 D1 D2 D3 2tCK Mode CMD WRITE WRITE CK_c CK_t tCCD DQS_t, DQS_c =6 WL Preamble Preamble D0 DQ CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 183 D1 D2 D3 D4 D5 D6 D7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles READ Preamble Mode MR4[11] = 0 selects 1tCK READ preamble mode and MR4[11] = 1 selects 2tCK READ preamble mode. Examples are shown in the following figure. Figure 115: 1tCK vs. 2tCK READ Preamble Mode 1tCK Mode RD CL CK_c CK_t Preamble DQS_t, DQS_c DQ D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 2tCK Mode RD CL CK_c CK_t Preamble DQS_t, DQS_c DQ READ Preamble Training DDR4 supports READ preamble training via MPR reads; that is, READ preamble training is allowed only when the DRAM is in the MPR access mode. The READ preamble training mode can be used by the DRAM controller to train or "read level" its DQS receivers. READ preamble training is entered via an MRS command (MR4[10] = 1 is enabled and MR4[10] = 0 is disabled). After the MRS command is issued to enable READ preamble training, the DRAM DQS signals are driven to a valid level by the time t SDO is satisfied. During this time, the data bus DQ signals are held quiet, that is, driven HIGH. The DQS_t signal remains driven LOW and the DQS_c signal remains driven HIGH until an MPR Page0 READ command is issued (MPR0 through MPR3 determine which pattern is used), and when CAS latency (CL) has expired, the DQS signals will toggle normally depending on the burst length setting. To exit READ preamble training mode, an MRS command must be issued, MR4[10] = 0. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 184 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles Figure 116: READ Preamble Training CMD MRS MPR RD tSDO CL DQS_t DQS_c, DQs (Quiet/Driven HIGH) D0 D1 D2 D3 D4 D5 D6 D7 WRITE Postamble Whether the 1tCK or 2tCK WRITE preamble mode is selected, the WRITE postamble remains the same AT tCK. Figure 117: WRITE Postamble 1tCK Mode WR WL CK_c CK_t Postamble DQS_t, DQS_c D0 DQ D1 D2 D3 D4 D5 D6 D7 2tCK Mode WR WL CK_c CK_t Postamble DQS_t, DQS_c D0 DQ D1 D2 D3 D4 D5 D6 D7 READ Postamble Whether the 1tCK or 2tCK READ preamble mode is selected, the READ postamble remains the same at  tCK. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 185 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Programmable Preamble Modes and DQS Postambles Figure 118: READ Postamble 1tCK Mode RD CL CK_c CK_t Postamble DQS_t, DQS_c D0 DQ D1 D2 D3 D4 D5 D6 D7 2tCK Mode RD CL CK_c CK_t Postamble DQS_t, DQS_c DQ CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN D0 186 D1 D2 D3 D4 D5 D6 D7 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation Bank Access Operation DDR4 supports bank grouping: x4/x8 DRAMs have four bank groups (BG[1:0]), and each bank group is comprised of four subbanks (BA[1:0]); x16 DRAMs have two bank groups (BG[0]), and each bank group is comprised of four subbanks. Bank accesses to different banks' groups require less time delay between accesses than bank accesses to within the same bank's group. Bank accesses to different bank groups require tCCD_S (or short) delay between commands while bank accesses within the same bank group require tCCD_L (or long) delay between commands. Figure 119: Bank Group x4/x8 Block Diagram Bank 3 Bank 2 Bank 1 Bank 0 Memory Array Bank Group 0 Bank 3 Bank 2 Bank 1 Bank 0 Memory Array Bank 3 Bank 2 Bank 1 Bank 0 Memory Array Bank Group 1 Bank Group 2 Bank 3 Bank 2 Bank 1 Bank 0 Memory Array Bank Group 3 CMD/ADDR register CMD/ADDR Sense amplifiers Sense amplifiers Sense amplifiers Sense amplifiers Local I/O gating Local I/O gating Local I/O gating Local I/O gating Global I/O gating Data I/O Notes: 1. Bank accesses to different bank groups require tCCD_S. 2. Bank accesses within the same bank group require tCCD_L. Splitting the banks into bank groups with subbanks improved some bank access timings and increased others. However, considering DDR4 did not increase the prefetch from 8n to 16n, the penalty for staying 8n prefetch was significantly mitigated by using bank groups. The table below summarizes the timings affected (values listed as xnCK or yns means the larger of the two values). Table 70: DDR4 Bank Group Timing Examples Parameter DDR4-1600 DDR4-2133 DDR4-2400 CCD_S 4nCK 4nCK 4nCK tCCD_L 4nCK or 6.25ns 4nCK or 5.355ns 4nCK or 5ns t 22$?3ž+ 4nCK or 5ns 4nCK or 3.7ns 4nCK or 3.3ns t 22$?,ž+ 4nCK or 6ns 4nCK or 5.3ns 4nCK or 4.9ns t 4nCK or 5ns 4nCK or 3.7ns 4nCK or 3.3ns 4nCK or 6ns 4nCK or 5.3ns 4nCK or 4.9ns t RRD_S (1K) tRRD_L (1K) CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 187 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation Table 70: DDR4 Bank Group Timing Examples (Continued) Parameter DDR4-1600 DDR4-2133 DDR4-2400 tRRD_S 4nCK or 6ns 4nCK or 5.3ns 4nCK or 5.3ns 4nCK or 7.5ns 4nCK or 6.4ns 4nCK or 6.4ns t 2nCK or 2.5ns 2nCK or 2.5ns 2nCK or 2.5ns t 4nCK or 7.5ns 4nCK or 7.5ns 4nCK or 7.5ns (2K) t RRD_L (2K) WTR_S WTR_L Notes: 1. Refer to Timing Tables for actual specification values, these values are shown for reference only and are not verified for accuracy. 2. Timings with both nCK and ns require both to be satisfied; that is, the larger time of the two cases must be satisfied. Figure 120: READ Burst tCCD_S and tCCD_L Examples CK_c CK_t Command T0 T1 READ DES T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 DES DES READ DES DES DES DES DES READ DES tCCD_L tCCD_S Bank Group (BG) BG a BG b BG b Bank Bank c Bank c Bank c Address Col n Col n Col n Don’t Care Notes: 1. 2. tCCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank groups (T0 to T4). CCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank group (T4 to T10). t Figure 121: Write Burst tCCD_S and tCCD_L Examples CK_c CK_t Command T0 T1 WRITE DES T2 T3 T4 T5 T6 DES DES WRITE DES DES T7 T8 T9 T10 T11 DES DES DES WRITE DES tCCD_L tCCD_S Bank Group (BG) BG a BG b BG b Bank Bank c Bank c Bank c Coln Coln Coln Address Don’t Care Notes: 1. 2. t CCD_S; CAS_n-to-CAS_n delay (short). Applies to consecutive CAS_n to different bank groups (T0 to T4). CCD_L; CAS_n-to-CAS_n delay (long). Applies to consecutive CAS_n to the same bank group (T4 to T10). t CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 188 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation Figure 122: tRRD Timing CK_c CK_t Command T0 T1 ACT DES T2 T3 T4 T5 T6 DES DES ACT DES DES T8 T9 T10 T11 DES DES DES ACT DES tRRD_L tRRD_S Bank Group (BG) T7 BG a BG b BG b Bank Bank c Bank c Bank d Address Row n Row n Row n Don’t Care t RRD_S; ACTIVATE-to-ACTIVATE command period (short); applies to consecutive ACTIVATE commands to different bank groups (T0 and T4). 2. tRRD_L; ACTIVATE-to-ACTIVATE command period (long); applies to consecutive ACTIVATE commands to the different banks in the same bank group (T4 and T10). Notes: 1. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 189 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Bank Access Operation Figure 123: tWTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled) T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 WRITE Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid READ Valid CK_c CK_t Command tWTR_S Bank Group Bank BGa BGb Bank c Bank c Col n Address Col n tWPRE tWPST DQS, DQS_c DI n DQ DI n+ 1 DI n+ 2 DI n+ 3 DI n+ 4 DI n+ 5 DI n+ 6 DI n+ 7 RL WL Time Break Note: 1. Transitioning Data Don’t Care t WTR_S: delay from start of internal write transaction to internal READ command to a different bank group. Figure 124: tWTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled) T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 WRITE Valid Valid Valid Valid Valid Valid Valid Valid Valid Valid READ Valid CK_c CK_t Command tWTR_L Bank Group Bank BGa BGa Bank c Bank c Col n Address Col n tWPRE tWPST DQS, DQS_c DI n DQ DI n+ 1 DI n+ 2 DI n+ 3 DI n+ 4 DI n+ 5 DI n+ 6 DI n+ 7 RL WL Time Break Note: 1. Transitioning Data Don’t Care t WTR_L: delay from start of internal write transaction to internal READ command to the same bank group. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 190 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ Operation Read Timing Definitions The read timings shown below are applicable in normal operation mode, that is, when the DLL is enabled and locked. Note:tDQSQ = both rising/falling edges of DQS; no tAC defined. Rising data strobe edge parameters: s tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge relative to CK. s tDQSCK is the actual position of a rising strobe edge relative to CK. s tQSH describes the DQS differential output HIGH time. s tDQSQ describes the latest valid transition of the associated DQ pins. s tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: s tQSL describes the DQS differential output LOW time. s tDQSQ describes the latest valid transition of the associated DQ pins. s tQH describes the earliest invalid transition of the associated DQ pins. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 191 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 125: Read Timing Definition CK_c CK_t tDQSCK tDQSCK tDQSCK (MIN) tDQSCK (MAX) MAX center tDQSCK MIN tDQSCK (MIN) tDQSCK (MAX) tDQSCKi tDQSCKi Rising strobe region window Rising strobe region window tDQSCKi tDQSCKi Rising strobe region window Rising strobe region window tDQSCKi tDQSCKi Rising strobe region window Rising strobe region window tDQSCK tDQSCK tQSH/DQS_c tQSH/DQS_t DQS_c DQS_t tQH tQH tDQSQ tDQSQ Associated DQ Pins Table 71: Read-to-Write and Write-to-Read Command Intervals Access Type Read-to-Write, minimum Write-to-Read, minimum Bank Group Timing Parameters Note Same CL - CWL + RBL/2 + 1tCK + tWPRE 1, 2 Different CL - CWL + RBL/2 + 1tCK + tWPRE 1, 2 Same CWL + WBL/2 + tWTR_L 1, 3 Different CWL + WBL/2 + tWTR_S 1, 3 Notes: 1. These timings require extended calibrations times tZQinit and tZQCS. 2. RBL: READ burst length associated with READ command, RBL = 8 for fixed 8 and on-the-fly mode 8 and RBL = 4 for fixed BC4 and on-the-fly mode BC4. 3. WBL: WRITE burst length associated with WRITE command, WBL = 8 for fixed 8 and on-the-fly mode 8 or BC4 and WBL = 4 for fixed BC4 only. 2EAD4IMINGn#LOCK TO $ATA3TROBE2ELATIONSHIP The clock-to-data strobe relationship shown below is applicable in normal operation mode, that is, when the DLL is enabled and locked. Rising data strobe edge parameters: CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 192 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation s tDQSCK (MIN)/(MAX) describes the allowed range for a rising data strobe edge relative to CK. s tDQSCK is the actual position of a rising strobe edge relative to CK. s tQSH describes the data strobe high pulse width. s tHZ(DQS) DQS strobe going to high, nondrive level (shown in the postamble section of the figure below). Falling data strobe edge parameters: s tQSL describes the data strobe low pulse width. s tLZ(DQS) DQS strobe going to low, initial drive level (shown in the preamble section of the figure below). Figure 126: Clock-to-Data Strobe Relationship RL measured to this point CK_t CK_c tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) tDQSCK (MIN) tHZ(DQS) MIN tLZ(DQS) MIN DQS_t, DQS_c Early Strobe tQSH tQSL tQSH tQSL tQSH tQSL Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 tRPRE Bit 7 tRPST tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tDQSCK (MAX) tLZ(DQS) MAX DQS_t, DQS_c Late Strobe Bit 0 tRPRE tQSH Bit 1 tQSL Bit 2 tQSH Bit 3 Bit 4 Bit 5 Bit 6 tHZ(DQS) MAX tRPST Bit 7 tQSL Notes: 1. Within a burst, the rising strobe edge will vary within tDQSCKi while at the same voltage and temperature. However, when the device, voltage, and temperature variations are incorporated, the rising strobe edge variance window can shift between tDQSCK (MIN) and tDQSCK (MAX). A timing of this window's right edge (latest) from rising CK_t, CK_c is limited by a device's actual tDQSCK (MAX). A timing of this window's left inside edge (earliest) from rising CK_t, CK_c is limited by tDQSCK (MIN). 2. Notwithstanding Note 1, a rising strobe edge with tDQSCK (MAX) at T(n) can not be immediately followed by a rising strobe edge with tDQSCK (MIN) at T(n + 1) because other timing relationships (tQSH, tQSL) exist: if tDQSCK(n + 1) < 0: tDQSCK(n) < 1.0 tCK - (tQSH (MIN) + tQSL (MIN)) - |tDQSCK(n + 1) |. 3. The DQS_t, DQS_c differential output HIGH time is defined by tQSH, and the DQS_t, DQS_c differential output LOW time is defined by tQSL. 4. tLZ(DQS) MIN and tHZ(DQS) MIN are not tied to tDQSCK (MIN) (early strobe case), and tLZ(DQS) MAX and tHZ(DQS) MAX are not tied to tDQSCK (MAX) (late strobe case). 5. The minimum pulse width of READ preamble is defined by tRPRE (MIN). 6. The maximum READ postamble is bound by tDQSCK (MIN) plus tQSH (MIN) on the left side and tHZDSQ (MAX) on the right side. 7. The minimum pulse width of READ postamble is defined by tRPST (MIN). 8. The maximum READ preamble is bound by tLZDQS (MIN) on the left side and tDQSCK (MAX) on the right side. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 193 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation 2EAD4IMINGn$ATA3TROBE TO $ATA2ELATIONSHIP The data strobe-to-data relationship is shown below and is applied when the DLL is enabled and locked. Note:tDQSQ: both rising/falling edges of DQS; no tAC defined. Rising data strobe edge parameters: s tDQSQ describes the latest valid transition of the associated DQ pins. s tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: s tDQSQ describes the latest valid transition of the associated DQ pins. s tQH describes the earliest invalid transition of the associated DQ pins. Data valid window parameters: s tDVWd is the Data Valid Window per device per UI and is derived from [tQH - tDQSQ] of each UI on a given DRAM s tDVWp is the Data Valid Window per pin per UI and is derived [tQH - tDQSQ] of each UI on a pin of a given DRAM Figure 127: Data Strobe-to-Data Relationship T0 T1 T2 T9 T10 T11 T12 T13 T14 T15 T16 Command3 READ DES DES DES DES DES DES DES DES DES DES Address4 Bank, Col n CK_c CK_t RL = AL + CL tDQSQ tRPRE tDQSQ (MAX) (MAX) tRPST (1nCK) DQS_t, DQS_c tQH DQ2 (Last data ) DOUT n tQH DOUT n+1 DOUT n+2 DOUT n+3 DOUT n+4 DOUT n+5 DOUT n+6 DOUT n+7 tDVWp DQ2 (First data no longer) DOUT n+1 DOUT n DOUT n+2 DOUT n+3 DOUT n+4 DOUT n+5 DOUT n+6 DOUT n+7 tDVWp DOUT n All DQ collectively DOUT n+1 DOUT n+2 DOUT n+3 DOUT n+4 DOUT n+5 tDVWd Notes: 1. 2. 3. 4. 5. DOUT n+6 DOUT n+7 tDVWd Don’t Care BL = 8, RL = 11 (AL = 0, CL = 1), Premable = 1tCK. DOUT n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0. Output timings are referenced to VDDQ, and DLL on for locking. 6. tDQSQ defines the skew between DQS to data and does not define DQS to clock. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 194 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation t LZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) Calculations t HZ and tLZ transitions occur in the same time window as valid data transitions. These parameters are referenced to a specific voltage level that specifies when the device output is no longer driving t HZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS) and tLZ(DQ). The figure below shows a method to calculate the point when the device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving t LZ(DQS) and tLZ(DQ), by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. tLZ(DQS), tLZ(DQ), tHZ(DQS), and t HZ(DQ) are defined as singled-ended parameters. Figure 128: tLZ and tHZ Method for Calculating Transitions and Endpoints tLZ(DQ): CK_t, CK_c rising crossing at RL tHZ(DQ) tHZ(DQ) with BL8: CK_t, CK_c rising crossing at RL + 4CK with BC4: CK_t, CK_c rising crossing at RL + 2CK CK_t CK_c Begin point: Extrapolated point at VDDQ DQ tLZ tHZ VDDQ VDDQ DQ VSW2 VSW2 0.7 × VDDQ 0.7 × VDDQ VSW1 VSW1 0.4 × VDDQ 0.4 × VDDQ Begin point: Extrapolated point (low level) Notes: 1. Vsw1 = (0.70 - 0.04) έ VDDQ for both tLZ and tHZ. 2. Vsw2 = (0.70 + 0.04) έ VDDQ for both tLZ and tHZ. 3. Extrapolated point (low level) = VDDQ/(50 + 34) έ 34 = 0.4 έ VDDQ Driver impedance = RZQ/7 = 34ȳ VTT test load = 50ȳ to VDDQ. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 195 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation t RPRE Calculation Figure 129: tRPRE Method for Calculating Transitions and Endpoints CK_t VDD /2 CK_c Single-ended signal provided as background information VDDQ DQS_t 0.7 × VDDQ 0.4 × VDDQ DQS_c VDDQ 0.7 × VDDQ 0.4 × VDDQ DQS_t DQS_t DQS_c VDDQ 0.7 × VDDQ DQS_c 0.4 × VDD Resulting differential signal relevant for tRPRE specification 0.6 × VDDQ VSW2 0.3 × VDDQ VSW1 DQS_t, DQS_c t t t RPRE ends (t2) RPRE begins ( 1) 0V Notes: 1. Vsw1 = (0.3 - 0.04) έ VDDQ. 2. Vsw2 = (0.30 + 0.04) έ VDDQ. 3. DQS_t and DQS_c low level = VDDQ/(50 + 34) έ 34 = 0.4 έ VDDQ Driver impedance = RZQ/7 = 34ȳ VTT test load = 50ȳ to VDDQ. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 196 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation t RPST Calculation Figure 130: tRPST Method for Calculating Transitions and Endpoints CK_t VDD /2 CK_c Single-ended signal provided as background information VDDQ 0.7 × VDDQ 0.4 × VDDQ DQS_t VDDQ DQS_c 0.7 × VDDQ 0.4 × VDDQ DQS_c VDDQ 0.7 × VDDQ DQS_t Resulting differential signal relevant fortRPST specification tRPST beginst(1) 0V VSW2 –0.3 × VDDQ VSW1 –0.6 × VDDQ DQS_t, DQS_c tRPST ends t(2) Notes: 1. Vsw1n  έ VDDQ. 2. Vsw2n έ VDDQ. 3. DQS_t and DQS_c low level = VDDQ/(50 + 34) έ 34 = 0.4 έ VDDQ Driver impedance = RZQ/7 = 34ȳ VTT test load = 50ȳ to VDDQ. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 197 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ Burst Operation DDR4 READ commands support bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled: s A12 = 0, BC4 (BC4 = burst chop) s A12 = 1, BL8 READ commands can issue precharge automatically with a READ with auto precharge command (RDA), and is enabled by A10 HIGH: s READ command with A10 = 0 (RD) performs standard read, bank remains active after READ burst. s READ command with A10 = 1 (RDA) performs read with auto precharge, bank goes in to precharge after READ burst. Figure 131: READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8) T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Ta9 READ DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command Bank Group Address BGa Address Bank col n tRPRE tRPST DQS_t DQS_c DO n DQ DO n+ 1 DO n+ 2 DO n+ 3 DO n+ 4 DO n+ 5 DO n+ 6 DO n+ 7 CL = 11 RL = AL + CL Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, RL = 0, AL = 0, CL = 11, Preamble = 1tCK. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 198 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 132: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tb2 Tb3 Tb4 Tb5 Tb6 READ DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command Bank Group Address BGa Address Bank col n tRPRE tRPST DQS_t DQS_c DO n DQ AL = 10 DO n+ 1 DO n+ 2 DO n+ 3 DO n+ 4 DO n+ 5 DO n+ 6 DO n+ 7 CL = 11 RL = AL + CL Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1tCK. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 199 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ Operation Followed by Another READ Operation Figure 133: Consecutive READ (BL8) with 1tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, AL = 0, CL = 11, Preamble = 1tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Figure 134: Consecutive READ (BL8) with 2tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, AL = 0, CL = 11, Preamble = 2tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 200 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 135: Nonconsecutive READ (BL8) with 1tCK Preamble in Same or Different Bank Group T0 T1 READ DES T2 T3 T4 DES DES T5 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S/L =5 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. Don’t Care Transitioning Data BL8, AL = 0, CL = 11, Preamble = 1tCK, tCCD_S/L = 5. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Figure 136: Nonconsecutive READ (BL8) with 2tCK Preamble in Same or Different Bank Group T0 T1 READ DES T2 T5 T6 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S/L =6 Bank Group Address BGa BGa or BGb Address Bank Col n Bank Col b tRPRE tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL8, AL = 0, CL = 11, Preamble = 2tCK, tCCD_S/L = 6. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0 and T6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. 6 t##$?3,ISNTALLOWEDINtCK preamble mode. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 201 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 137: READ (BC4) to READ (BC4) with 1tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, AL = 0, CL = 11, Preamble = 1tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Figure 138: READ (BC4) to READ (BC4) with 2tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, AL = 0, CL = 11, Preamble = 2tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 202 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 139: READ (BL8) to READ (BC4) OTF with 1tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b t RPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 RL = 11 Time Break Transitioning Data Don’t Care BL = 8, AL = 0, CL = 11, Preamble = 1tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. Figure 140: READ (BL8) to READ (BC4) OTF with 2tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO b+3 RL = 11 Time Break Transitioning Data Don’t Care BL = 8, AL =0, CL = 11, Preamble = 2tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 203 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 141: READ (BC4) to READ (BL8) OTF with 1tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tCCD_S Bank Group Address Address =4 BGa BGb Bank Col n Bank Col b tRPST tRPRE tRPST tRPRE DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Transitioning Data Don’t Care BL = 8, AL =0, CL = 11, Preamble = 1tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. Figure 142: READ (BC4) to READ (BL8) OTF with 2tCK Preamble in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S Bank Group Address Address =4 BGa BGb Bank Col n Bank Col b tRPST tRPRE DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO b DO b+1 DO b+2 DO b+3 DO b+4 DO b+5 DO b+6 DO b+7 RL = 11 Time Break Transitioning Data Don’t Care BL = 8, AL = 0, CL = 11, Preamble = 2tCK. DO n (or b) = data-out from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 204 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ Operation Followed by WRITE Operation Figure 143: READ (BL8) to WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T22 CK_c CK_t Command DES tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tWPST tWPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 9 Time Break Transitioning Data Don’t Care BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n; DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Notes: 1. 2. 3. 4. Figure 144: READ (BL8) to WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command READ to WRITE command delay = RL +BL/2 - WL + 3 tCK Bank Group Address Address 4 Clocks BGa BGa or BGb Bank Col n Bank Col b t t RPRE RPST t t WPRE t WR t WTR WPST DQS_t, DQS_c RL = 11 DQ DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 10 Time Break Transitioning Data Don’t Care Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9+1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8. 5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 205 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 145: READ (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tWPST tWPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 WL = 9 Time Break Transitioning Data Don’t Care BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n; DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Notes: 1. 2. 3. 4. Figure 146: READ (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 3 tCK Bank Group Address Address 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tRPST tWTR tWPST tWPRE DQS_t, DQS_c RL = 11 DQ DO n DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 WL = 10 Time Break Transitioning Data Don’t Care Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (OTF) setting activated by MR0[1:0] = 01 and A12 = 0 during READ commands at T0 and WRITE commands at T6. 5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 206 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 147: READ (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES T19 T20 DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 2 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tWPST tWPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 WL = 9 Time Break Transitioning Data Don’t Care BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n; DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 (fixed) setting activated by MR0[1:0] = 01. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Notes: 1. 2. 3. 4. 5. Figure 148: READ (BC4) Fixed to WRITE (BC4) Fixed with 2tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command READ tWR READ to WRITE command delay = RL +BL/2 - WL + 3 tCK Bank Group Address Address tWTR 2 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tRPST tWPST tWPRE DQS_t, DQS_c RL = 11 DQ DO n DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 WL = 10 Time Break Transitioning Data Don’t Care Notes: 1. BC = 4, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 9 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 (fixed) setting activated by MR0[1:0] = 10. 5. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 207 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 149: READ (BC4) to WRITE (BL8) OTF with 1tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T20 CK_c CK_t Command DES tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPST tRPRE tWPST tWPRE DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 9 Time Break Transitioning Data Don’t Care BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n; DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Notes: 1. 2. 3. 4. Figure 150: READ (BC4) to WRITE (BL8) OTF with 2tCK Preamble in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 3 tCK Bank Group Address Address tWTR 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPST tRPRE tWPST tWPRE DQS_t, DQS_c RL = 11 DQ DO n DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 10 Time Break Transitioning Data Don’t Care Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T6. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 208 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 151: READ (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T22 CK_c CK_t Command DES tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tWPST tWPRE tRPST DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 WL = 9 Time Break Transitioning Data Don’t Care BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n; DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Notes: 1. 2. 3. 4. Figure 152: READ (BL8) to WRITE (BC4) OTF with 2tCK Preamble in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 3 tCK Bank Group Address Address 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tRPST tWTR tWPST tWPRE DQS_t, DQS_c RL = 11 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 WL = 10 Time Break Transitioning Data Don’t Care Notes: 1. BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 2tCK, WL = 10 (CWL = 9 + 1 [see Note 5], AL = 0), WRITE preamble = 2tCK. 2. DO n = data-out from column n; DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during READ commands at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. READ Operation Followed by PRECHARGE Operation The minimum external READ command to PRECHARGE command spacing to the same bank is equal to AL + tRTP with tRTP being the internal READ command to PRECHARGE command delay. Note that the minimum ACT to PRE timing, tRAS, must be satisfied as well. The minimum value for the internal CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 209 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ command to PRECHARGE command delay is given by tRTP (MIN) = MAX (4 έ nCK, 7.5ns). A new bank ACTIVATE command may be issued to the same bank if the following two conditions are satisfied simultaneously: s The minimum RAS precharge time (tRP [MIN]) has been satisfied from the clock at which the precharge begins. s The minimum RAS cycle time (tRC [MIN]) from the previous bank activation has been satisfied. Figure 153: READ to PRECHARGE with 1tCK Preamble T0 T1 T2 T3 T6 T7 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES PRE DES DES DES DES DES DES DES DES ACT DES DES DES CK_c CK_t Command Bank Group Address BGa or BGb BGa Bank a Col n Address BGa Bank a (or all) tRTP Bank a Row b tRP RL = AL + CL BC4 Opertaion DQS_t, DQS_c DQ DO n DO n+1 DO n+2 DO n+3 DO n DO n+1 DO n+2 DO n+3 BL8 Opertaion DQS_t, DQS_c DQ DO n+4 DO n+5 DO n+6 DO n+7 Time Break Transitioning Data Don’t Care RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18). 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 210 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 154: READ to PRECHARGE with 2tCK Preamble T0 T1 T2 T3 T6 T7 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES PRE DES DES DES DES DES DES DES DES ACT DES DES DES CK_c CK_t Command Bank Group Address BGa or BGb BGa Bank a Col n Address BGa Bank a (or all) Bank a Row b tRTP tRP RL = AL + CL BC4 Opertaion DQS_t, DQS_c DQ DO n DO n+1 DO n+2 DO n+3 DO n DO n+1 DO n+2 DO n+3 BL8 Opertaion DQS_t, DQS_c DQ DO n+4 DO n+5 DO n+6 DO n+7 Time Break Transitioning Data Don’t Care RL = 11 (CL = 11, AL = 0 ), Preamble = 2tCK, tRTP = 6, tRP = 11. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T7) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T18). 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. Figure 155: READ to PRECHARGE with Additive Latency and 1tCK Preamble T0 T1 T2 T3 T10 T11 T12 T13 T16 T19 T20 T21 T22 T23 T24 T25 T26 T27 DES READ DES DES DES DES DES DES PRE DES DES DES DES DES DES DES DES ACT CK_c CK_t Command Bank Group Address BGa or BGb BGa Bank a Col n Address BGa Bank a (or all) AL = CL - 2 = 9 tRTP Bank a Row b tRP CL = 11 BC4 Opertaion DQS_t, DQS_c DQ DO n DO n+1 DO n+2 DO n+3 DO n DO n+1 DO n+2 DO n+3 BL8 Opertaion DQS_t, DQS_c DQ DO n+4 DO n+5 Time Break DO n+6 DO n+7 Transitioning Data Don’t Care RL =20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. The example assumes that tRAS (MIN) is satisfied at the PRECHARGE command time (T16) and that tRC (MIN) is satisfied at the next ACTIVATE command time (T27). 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 211 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 156: READ with Auto Precharge and 1tCK Preamble T0 T1 T2 T3 T6 T7 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES RDA DES DES DES PRE DES DES DES DES DES DES DES DES ACT DES DES DES CK_c CK_t Command Bank Group Address BGa or BGb BGa Bank a Col n Address BGa Bank a Col n Bank a Row b tRTP tRP RL = AL + CL BC4 Opertaion DQS_t, DQS_c DQ DO n DO n+1 DO n+2 DO n+3 DO n DO n+1 DO n+2 DO n+3 BL8 Opertaion DQS_t, DQS_c DQ DO n+4 DO n+5 DO n+6 DO n+7 Time Break Transitioning Data Don’t Care RL = 11 (CL = 11, AL = 0 ), Preamble = 1tCK, tRTP = 6, tRP = 11. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. t RTP = 6 setting activated by MR0[A11:9 = 001]. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time (T18). CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. 5. 6. Figure 157: READ with Auto Precharge, Additive Latency, and 1tCK Preamble T0 T1 T2 T3 T10 T11 T12 T13 T16 T19 T20 T21 T22 T23 T24 T25 T26 T27 DES RDA DES DES DES DES DES DES DES DES DES DES DES DES DES DES DES ACT CK_c CK_t Command Bank Group Address BGa BGa Bank a Col n Address Bank a Row b AL = CL - 2 = 9 tRTP tRP CL = 11 BC4 Opertaion DQS_t, DQS_c DQ DO n DO n+1 DO n+2 DO n+3 DO n DO n+1 DO n+2 DO n+3 BL8 Opertaion DQS_t, DQS_c DQ DO n+4 DO n+5 Time Break Notes: 1. 2. 3. 4. 5. 6. DO n+6 DO n+7 Transitioning Data Don’t Care RL = 20 (CL = 11, AL = CL - 2), Preamble = 1tCK, tRTP = 6, tRP = 11. DO n = data-out from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. t RTP = 6 setting activated by MR0[11:9] = 001. The example assumes that tRC (MIN) is satisfied at the next ACTIVATE command time (T27). CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 212 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation READ Operation with Read Data Bus Inversion (DBI) Figure 158: Consecutive READ (BL8) with 1tCK Preamble and DBI in Different Bank Group T0 T1 READ DES T2 T3 T4 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S =4 Bank Group Address BGa BGb Address Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 11 + 2 (Read DBI adder) DQ DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO DO DO b + 3 b +4 _ b + 5 DO b+6 DO b+7 DBI n DBI n+1 DBI n+2 DBI n+3 DBI n+4 DBI n+5 DBI n+6 DBI n+7 DBI b DBI b+1 DBI b+2 DBI b+3 DBI b+6 DBI b+7 RL = 11 + 2 (Read DBI adder) DBI_n Time Break DBI DBI b+4 b+5 Don’t Care Transitioning Data BL = 8, AL = 0, CL = 11, Preamble = 1tCK, RL = 11 + 2 (Read DBI adder). DO n (or b) = data-out from column n (or b); DBI n (or b) = data bus inversion from column n (or b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Read DBI = Enable. Notes: 1. 2. 3. 4. 5. READ Operation with Command/Address Parity (CA Parity) Figure 159: Consecutive READ (BL8) with 1tCK Preamble and CA Parity in Different Bank Group T0 T1 READ DES T2 T3 T4 T7 T8 T13 T14 T15 T16 T17 T18 T19 T20 T21 T20 T21 DES READ DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command DES tCCD_S Bank Group Address Address Parity =4 BGa BGb Bank Col n Bank Col b tRPRE tRPST DQS_t, DQS_c RL = 15 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DO b DO b+1 DO b+2 DO DO DO b + 3 b +4 _ b + 5 DO b+6 DO b+7 RL = 15 Time Break Transitioning Data Don’t Care BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), Preamble = 1tCK. DO n (or b) = data-out from column n (or b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[A1:A0 = 00] or MR0[A1:A0 = 01] and A12 = 1 during READ commands at T0 and T4. 5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 213 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 160: READ (BL8) to WRITE (BL8) with 1tCK Preamble and CA Parity in Same or Different Bank Group T0 T1 T7 T8 T9 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T26 CK_c CK_t Command DES tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address Parity 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tRPST tWTR tWPST tWPRE DQS_t, DQS_c RL = 15 DO n DQ DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 13 Time Break Transitioning Data Don’t Care Notes: 1. BL = 8, AL = 0, CL = 11, PL = 4, (RL = CL + AL + PL = 15), READ preamble = 1tCK, CWL = 9, AL = 0, PL = 4, (WL = CL + AL + PL = 13), WRITE preamble = 1tCK. 2. DO n = data-out from column n, DI b = data-in from column b. 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE command at T8. 5. CA parity = Enable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. READ Followed by WRITE with CRC Enabled Figure 161: READ (BL8) to WRITE (BL8 or BC4: OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T22 CK_c CK_t Command DES tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address 4 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tRPST tWTR tWPST tWPRE DQS_t, DQS_c RL = 11 DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DQ x4, READ: BL = 8, WRITE: BC = 4 (OTF) DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 CRC DQ x8/X16, READ: BL = 8, WRITE: BC = 4 (OTF) DO n DO n+1 DO n+2 DO n+3 DO n+4 DO n+5 DO n+6 DO n+7 DI b DI b+1 DI b+2 DI b+3 CRC DQ x4, BL = 8 CRC WL = 9 DQ x8/X16, BL = 8 Time Break Transitioning Data CRC Don’t Care Notes: 1. BL = 8 (or BC = 4: OTF for Write), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. 2. DO n = data-out from column n, DI b = data-in from column b. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 214 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation 3. DES commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T0 and WRITE commands at T8. 5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T8. 6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Enable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 215 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 162: READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 READ DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR READ to WRITE command delay = RL +BL/2 - WL + 2 tCK Bank Group Address Address tWTR 2 Clocks BGa BGa or BGb Bank Col n Bank Col b tRPRE tWPST tWPRE tRPST DQS_t, DQS_c RL = 11 DQ x4, BC = 4 (Fixed) DO n DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 CRC DO n DO n+1 DO n+2 DO n+3 DI b DI b+1 DI b+2 DI b+3 CRC CRC WL = 9 DQ x8/X16, BC = 4 (Fixed) Time Break Transitioning Data Don’t Care BC = 4 (Fixed), RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK, WL = 9 (CWL = 9, AL = 0), WRITE preamble = 1tCK. DO n = data-out from column n, DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Enable. Notes: 1. 2. 3. 4. 5. READ Operation with Command/Address Latency (CAL) Enabled Figure 163: Consecutive READ (BL8) with CAL (3tCK) and 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T5 T6 T7 T8 T13 T14 T15 T17 T18 T19 T21 T22 T23 DES READ DES DES DES DES DES DES DES DES DES DES CK_c CK_t tCAL Command w/o CS_n DES tCAL =3 DES READ DES DES =3 CS_n tCCD_S Bank Group Address Address =4 BGa BGb Bank Col n Bank Col b tRPST tRPRE DQS_t, DQS_c RL = 11 DI n DQ DI n+1 DI n+2 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+5 DI b+6 DI b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK. DI n (or b) = data-in from column n (or b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T3 and T7. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Enabling CAL mode does not impact ODT control timings. The same timing relationship relative to the command/address bus as when CAL is disabled should be maintained. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 216 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM READ Operation Figure 164: Consecutive READ (BL8) with CAL (4tCK) and 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T5 READ DES DES T6 T7 T8 T14 T15 T16 T18 T19 T21 T22 T23 T24 READ DES DES DES DES DES DES DES DES DES DES CK_c CK_t tCAL Command w/o CS_n DES tCAL =4 DES =4 DES CS_n tCCD_S Bank Group Address Address =4 BGa BGb Bank Col n Bank Col b tRPST tRPRE DQS_t, DQS_c RL = 11 DI n DQ DI n+1 DI n+2 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+5 DI b+6 DI b+7 RL = 11 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL = 8, RL = 11 (CL = 11, AL = 0), READ preamble = 1tCK. DI n (or b) = data-in from column n (or b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ commands at T3 and T8. CA parity = Disable, CS to CA latency = Enable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. Enabling CAL mode does not impact ODT control timings. The same timing relationship relative to the command/address bus as when CAL is disabled should be maintained. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 217 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation WRITE Operation Write Timing Definitions The write timings shown in the following figures are applicable in normal operation mode, that is, when the DLL is enabled and locked. 7RITE4IMINGn#LOCK TO $ATA3TROBE2ELATIONSHIP The clock-to-data strobe relationship is shown below and is applicable in normal operation mode, that is, when the DLL is enabled and locked. Rising data strobe edge parameters: s tDQSS (MIN) to tDQSS (MAX) describes the allowed range for a rising data strobe edge relative to CK. s tDQSS is the actual position of a rising strobe edge relative to CK. s tDQSH describes the data strobe high pulse width. s tWPST strobe going to HIGH, nondrive level (shown in the postamble section of the graphic below). Falling data strobe edge parameters: s tDQSL describes the data strobe low pulse width. s tWPRE strobe going to LOW, initial drive level (shown in the preamble section of the graphic below). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 218 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 165: Write Timing Definition CK_c CK_t Command3 T0 T1 T2 T7 T8 T9 T10 WRITE DES DES DES DES DES DES T11 T12 T13 T14 DES DES DES DES WL = AL + CWL Address4 Bank, Col n tDQSS tDSH tDQSS (MIN) tDSH tDSH tDSH tWPSTaa tWPRE(1nCK) DQS_t, DQS_c tDQSL tDQSH tDQSH tDQSL tDQSH tDQSH tDQSL tDQSH tDQSL tDSS DQ2 tDSS tDSS DIN n+ 2 DIN n DIN n+ 3 tDSH tDQSS tDQSL (MIN) tDSS DIN n+ 6 DIN n+ 4 tDSH DIN n+ 7 tDSH tDSH tWPST tWPRE(1nCK) (nominal) (MIN) tDSS (MIN) DQS_t, DQS_c tDQSL tDQSH tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL (MIN) tDSS DQ2 tDSS tDSS DIN n+ 2 DIN n DIN n+ 3 tDSS DIN n+ 4 (MIN) tDSS DIN n+ 6 DIN n+ 7 tDQSS tDSH tDQSS (MAX) tDSH tDSH tDSH tWPRE(1nCK) tWPST (MIN) tDQSL (MIN) DQS_t, DQS_c tDQSL tDQSH tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH (MIN) tDSS tDSS DIN n DQ2 tDSS DIN n+ 2 DIN n+ 3 tDSS DIN n+ 4 tDSS DIN n+ 6 DIN n+ 7 DM_n Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, WL = 9 (AL = 0, CWL = 9). DIN n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. t DQSS must be met at each rising clock edge. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 219 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation t WPRE Calculation Figure 166: tWPRE Method for Calculating Transitions and Endpoints CK_t VDD /2 CK_c Single-ended signal provided as background information DQS_t VREFDQ DQS_c VREFDQ DQS_t DQS_t DQS_c VREFDQ DQS_c Resulting differential signal relevant for t WPRE specification VIH,DIFF,Peak VIH,DIFF,DQS VSW2 VSW1 DQS_t, DQS_c 0V t WPRE begins ( t 1) t WPRE ends ( t 2) Notes: 1. Vsw1 = (0.1) έ VIH,diff,DQS. 2. Vsw2 = (0.9) έ VIH,diff,DQS. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 220 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation t WPST Calculation Figure 167: tWPST Method for Calculating Transitions and Endpoints CK_t VDD /2 CK_c Single-ended signal provided as background information VREFDQ DQS_t DQS_c VREFDQ DQS_c VREFDQ DQS_t Resulting differential signal relevant for t WPST specification t WPST begins ( t 1) 0V VSW2 VSW1 DQS_t, DQS_c t WPST VIL,DIFF,DQS VIL,DIFF,Peak ends ( t 2) Notes: 1. Vsw1 =(0.9) έ VIL,diff,DQS. 2. Vsw2 = (0.1) έ VIL,diff,DQS. 7RITE4IMINGn$ATA3TROBE TO $ATA2ELATIONSHIP The DQ input receiver uses a compliance mask (Rx) for voltage and timing as shown in the figure below. The receiver mask (Rx mask) defines the area where the input signal must not encroach in order for the DRAM input receiver to be able to successfully capture a valid input signal. The Rx mask is not the valid data-eye. TdiVW and VdiVW define the absolute maximum Rx mask. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 221 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 168: Rx Compliance Mask VDIVW Rx Mask VCENTDQ,midpoint TdiVW VCENTDQ,midpoint is defined as the midpoint between the largest VREFDQ voltage level and the smallest VREFDQ voltage level across all DQ pins for a given DRAM. Each DQ pin's VREFDQ is defined by the center (widest opening) of the cumulative data input eye as depicted in the following figure. This means a DRAM's level variation is accounted for within the DRAM Rx mask. The DRAM VREFDQ level will be set by the system to account for RON and ODT settings. Figure 169: VCENT_DQ VREFDQ Voltage Variation DQx DQy (smallest VREFDQ Level) DQz (largest VREFDQ Level) VCENTDQz VCENTDQx VCENTDQ,midpoint VCENTDQy VREF variation (component) The following figure shows the Rx mask requirements both from a midpoint-to-midpoint reference (left side) and from an edge-to-edge reference. The intent is not to add any new requirement or specification between the two but rather how to convert the relationship between the two methodologies. The minimum data-eye shown in the composite view is not actually obtainable due to the minimum pulse width requirement. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 222 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 170: Rx Mask DQ-to-DQS Timings DQS, DQs Data-In at DRAM Ball DQS, DQs Data-In at DRAM Ball Rx Mask Rx Mask – Alternative View DQS_c DQS_c DQS_t DQS_t VdiVW DRAMa DQx–z Rx Mask DRAMa DQx–z VdiVW 0.5 × TdiVW 0.5 × TdiVW 0.5 × TdiVW 0.5 × TdiVW Rx Mask TdiVW TdiVW tDQS2DQ +0.5 × TdiVW DRAMb DQy Rx Mask VdiVW Rx Mask TdiVW tDQ2DQ VdiVW DRAMb DQz tDQ2DQ Rx Mask DRAMb DQz Rx Mask VdiVW DRAMb DQy VdiVW tDQS2DQ TdiVW tDQ2DQ tDQ2DQ Rx Mask TdiVW tDQ2DQ VdiVW DRAMc DQy Rx Mask DRAMc DQz DRAMc DQy Rx Mask TdiVW VdiVW Rx Mask VdiVW DRAMc DQz +0.5 × TdiVW VdiVW tDQS2DQ tDQS2DQ tDQ2DQ Notes: 1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask. 2. DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with early skews (negative tDQS2DQ). DRAMc represents a DRAM with delayed skews (positive tDQS2DQ). 3. This figure shows the skew allowed between DRAM-to-DRAM and between DQ-to-DQ for a DRAM. Signals assume data is center-aligned at DRAM latch. TdiPW is not shown; composite data-eyes shown would violate TdiPW. VCENTDQ,midpoint is not shown but is assumed to be midpoint of VdiVW. The previous figure shows the basic Rx mask requirements. Converting the Rx mask requirements to a classical DQ-to-DQS relationship is shown in the following figure. It should become apparent that DRAM write training is required to take full advantage of the Rx mask. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 223 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 171: Rx Mask DQ-to-DQS DRAM-Based Timings DQS, DQs Data-In at DRAM Ball DQS, DQs Data-In at DRAM Ball Rx Mask vs. Composite Data-Eye Rx Mask vs. UI Data-Eye DQS_c DQS_c DQS_t tDSx DRAMa DQx , y, z Rx Mask TdiVW VdiVW TdiPW DRAMa DQx–z TdiPW tDHx Rx Mask VdiVW DQS_t TdiVW TdiPW tDSy tDHy DRAMb DQz Rx Mask TdiVW tDQ2DQ Rx Mask tDQ2DQ TdiVW VdiVW DRAMb DQy VdiVW *Skew TdiPW tDSz tDHz DRAMc DQz tDQ2DQ Rx Mask Rx Mask TdiVW TdiVW tDQ2DQ VdiVW DRAMc DQy VdiVW *Skew TdiPW Notes: 1. DQx represents an optimally centered mask. DQy represents earliest valid mask. DQz represents latest valid mask. 2. *Skew = tDQS2DQ + 0.5 έ TdiVW DRAMa represents a DRAM without any DQS/DQ skews. DRAMb represents a DRAM with the earliest skews (negative tDQS2DQ, tDQSy > *Skew). DRAMc represents a DRAM with the latest skews (positive tDQS2DQ, tDQHz > *Skew). t 3. DS/tDH are traditional data-eye setup/hold edges at DC levels. t DS and tDH are not specified; tDH and tDS may be any value provided the pulse width and Rx mask limits are not violated. t DH (MIN) > TdiVW + tDS (MIN) + tDQ2DQ. The DDR4 SDRAM's input receivers are expected to capture the input data with an Rx mask of TdiVW provided the minimum pulse width is satisfied. The DRAM controller will have to train the data input buffer to utilize the Rx mask specifications to this maximum benefit. If the DRAM controller does not CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 224 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation train the data input buffers, then the worst case limits have to be used for the Rx mask (TdiVW + 2 έ t DQS2DQ), which will generally be the classical minimum (tDS and tDH) and is required as well. Figure 172: Example of Data Input Requirements Without Training TdiVW + 2 × tDQS2DQ VdiVW VIH(DC) 0.5 × VdiVW Rx Mask VCENTDQ,midpoint 0.5 × VdiVW VIL(DC) tDS tDH 0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ DQS_c DQS_t WRITE Burst Operation The following write timing diagrams are intended to help understand each write parameter's meaning and are only examples. Each parameter will be defined in detail separately. In these write timing diagrams, CK and DQS are shown aligned, and DQS and DQ are shown center-aligned for the purpose of illustration. DDR4 WRITE command supports bursts of BL8 (fixed), BC4 (fixed), and BL8/BC4 on-the-fly (OTF); OTF uses address A12 to control OTF when OTF is enabled: s A12 = 0, BC4 (BC4 = burst chop) s A12 = 1, BL8 WRITE commands can issue precharge automatically with a WRITE with auto precharge (WRA) command, which is enabled by A10 HIGH. s WRITE command with A10 = 0 (WR) performs standard write, bank remains active after WRITE burst s WRITE command with A10 = 1 (WRA) performs write with auto precharge, bank goes into precharge after WRITE burst The DATA MASK (DM) function is supported for the x8 and x16 configurations only (the DM function is not supported on x4 devices). The DM function shares a common pin with the DBI_n and TDQS functions. The DM function only applies to WRITE operations and cannot be enabled at the same time the DBI function is enabled. s If DM_n is sampled LOW on a given byte lane, the DRAM masks the write data received on the DQ inputs. s If DM_n is sampled HIGH on a given byte lane, the DRAM does not mask the data and writes this data into the DRAM core. s If CRC write is enabled, then DM enabled (via MRS) will be selected between write CRC nonpersistent mode (DM disabled) and write CRC persistent mode (DM enabled). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 225 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 173: WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8) T0 T1 T2 T7 T8 T9 WRITE DES DES DES DES DES T10 T11 T12 T13 T14 T15 T16 DES DES DES DES DES DES CK_c CK_t Command Bank Group Address BGa Address Bank Col n DES tWPST tWPRE DQS_t, DQS_c DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. 5. Don’t Care Transitioning Data BL8, WL = 0, AL = 0, CWL = 9, Preamble = 1tCK. DI n = Data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. CA parity = Disable, CS to CA Latency = Disable, Read DBI = Disable. Figure 174: WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8) T0 T1 T2 T9 T10 T11 T17 T18 T19 T20 T21 T22 T23 WRITE DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command Bank Group Address Address BGa Bank Col n tWPST tWPRE DQS_t, DQS_c DI n DQ AL = 10 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CWL = 9 WL = AL + CWL = 19 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BL8, WL = 19, AL = 10 (CL - 1), CWL = 9, Preamble = 1tCK. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 226 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation WRITE Operation Followed by Another WRITE Operation Figure 175: Consecutive WRITE (BL8) with 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S Bank Group Address Address 4 Clocks =4 BGa BGb Bank Col n Bank Col b tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL8, AL = 0, CWL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Figure 176: Consecutive WRITE (BL8) with 2tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S Bank Group Address Address 4 Clocks =4 BGa BGb Bank Col n Bank Col b tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 10 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = AL + CWL = 10 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 227 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode. Figure 177: Nonconsecutive WRITE (BL8) with 1tCK Preamble in Same or Different Bank Group T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S/L Bank Group Address Address 4 Clocks =5 BGa BGa or BGb Bank Col n Bank Col b tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL8, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T18. Figure 178: Nonconsecutive WRITE (BL8) with 2tCK Preamble in Same or Different Bank Group T0 T1 T2 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 WRITE DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S/L Bank Group Address Address 4 Clocks =6 BGa BGa or BGb Bank Col n Bank Col b tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 10 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = AL + CWL = 10 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2tCK, tCCD_S/L = 6tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T6. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. t##$?3,ISNTALLOWEDINtCK preamble mode. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 228 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 7. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T20. 8. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode. Figure 179: WRITE (BC4) OTF to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S Bank Group Address Address 4 Clocks =4 BGa BGb Bank Col n Bank Col b tWPST tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BC4, AL = 0, CWL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Figure 180: WRITE (BC4) OTF to WRITE (BC4) OTF with 2tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES T19 CK_c CK_t Command DES tWR tCCD_S Bank Group Address Address 4 Clocks =4 BGa BGb Bank Col n Bank Col b tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 10 DI n DQ DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = AL + CWL = 10 Time Break Notes: 1. 2. 3. 4. 5. Transitioning Data Don’t Care BC4, AL = 0, CWL = 9 + 1 = 10 (see Note 7), Preamble = 2tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 229 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T18. 7. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range, which means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode. Figure 181: WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S Bank Group Address Address 2 Clocks =4 BGa BGb Bank Col n Bank Col b tWPST tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. 5. 6. Don’t Care Transitioning Data BC4, AL = 0, CWL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 (fixed) setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T15. Figure 182: WRITE (BL8) to WRITE (BC4) OTF with 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES T19 CK_c CK_t Command DES t 4 Clocks t CCD_S = 4 Bank Group Address Address BGa BGb Bank Col n Bank Col b WR t WTR t WPST t WPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 WL = AL + CWL = 9 Time Break Notes: 1. 2. 3. 4. Transitioning Data Don’t Care BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 230 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Figure 183: WRITE (BC4) OTF to WRITE (BL8) with 1tCK Preamble in Different Bank Group T0 T1 T2 T3 T4 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES T19 CK_c CK_t Command DES tWR tCCD_S Bank Group Address Address 4 Clocks =4 BGa BGb Bank Col n Bank Col b tWPST tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DQ DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = AL + CWL = 9 Time Break Don’t Care Transitioning Data BL = 8/BC = 4, AL = 0, CL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 01 and A12 = 1 during WRITE command at T4. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Disable. 6. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T17. Notes: 1. 2. 3. 4. WRITE Operation Followed by READ Operation Figure 184: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T24 T25 T26 T27 T28 T29 WRITE DES DES DES DES DES DES DES DES DES READ DES DES DES DES DES DES DES CK_c CK_t Command 4 Clocks Bank Group Address Address tWTR_S BGa =2 BGb Bank Col n Bank Col b tWPST tWPRE tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b Time Break Notes: 1. 2. 3. 4. DI b+1 DI b+2 DI b+3 Transitioning Data DI b+4 DI b+5 DI b+6 Don’t Care BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T15. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 231 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13. Figure 185: WRITE (BL8) to READ (BL8) with 1tCK Preamble in Same Bank Group T0 T1 T7 T8 T9 T10 WRITE DES DES DES DES DES T11 T12 T13 T14 DES DES DES DES T15 T16 T17 T18 T26 T27 T28 T29 DES DES READ DES DES DES DES DES CK_c CK_t Command 4 Clocks Bank Group Address Address tWTR_L =4 BGa BGa Bank Col n Bank Col b tWPST tWPRE tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b Time Break Transitioning Data DI b+1 DI b+2 Don’t Care BL = 8, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0 and READ command at T17. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. 6. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13. Notes: 1. 2. 3. 4. Figure 186: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 WRITE DES DES DES DES DES DES DES DES T14 T15 T16 T24 T25 T26 T27 T28 T29 DES READ DES DES DES DES DES DES DES CK_c CK_t Command 4 Clocks Bank Group Address Address tWTR_S BGa =2 BGb Bank Col n Bank Col b tWPST tWPRE tRPST tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI b Time Break Notes: 1. 2. 3. 4. 5. 6. DI b+1 DI b+2 DI b+3 Transitioning Data Don’t Care BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T15. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T13. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 232 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 187: WRITE (BC4) OTF to READ (BC4) OTF with 1tCK Preamble in Same Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 WRITE DES DES DES DES DES DES DES DES DES T15 T16 T17 T18 T26 T27 T28 T29 DES DES READ DES DES DES DES DES CK_c CK_t Command 4 Clocks Bank Group Address Address tWTR_L =4 BGa BGa Bank Col n Bank Col b tWPST tWPRE tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI b Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data DI b+1 DI b+2 Don’t Care BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0 and READ command at T17. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after the last write data shown at T13. Figure 188: WRITE (BC4) Fixed to READ (BC4) Fixed with 1 tCK Preamble in Different Bank Group T0 T1 T7 T8 T9 WRITE DES DES DES DES T10 T11 DES DES T12 T13 T14 T22 T23 T24 T25 T26 T27 T28 T29 DES DES DES DES DES READ DES DES DES DES DES CK_c CK_t Command 2 Clocks Bank Group Address Address tWTR_S =2 BGa BGb Bank Col n Bank Col b tWPST tWPRE tRPST tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BC = 4, WL = 9 (CWL = 9, AL = 0), CL = 11, READ preamble = 1 tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. The write timing parameter (tWTR_S) is referenced from the first rising clock edge after the last write data shown at T11. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 233 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 189: WRITE (BC4) Fixed to READ (BC4) Fixed with 1tCK Preamble in Same Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T24 T25 T26 T27 T28 T29 WRITE DES DES DES DES DES DES DES DES DES READ DES DES DES DES DES DES DES CK_c CK_t Command 2 Clocks Bank Group Address Address tWTR_L =4 BGa BGa Bank Col n Bank Col b tWPST tWPRE tRPST tRPRE DQS_t, DQS_c WL = AL + CWL = 9 RL = AL + CL = 11 DI n DQ DI n+1 DI n+2 DI n+3 DI b Time Break Notes: 1. 2. 3. 4. 5. 6. DI b+1 DI b+2 DI b+3 Transitioning Data Don’t Care BC = 4, WL = 9 (CWL = 9, AL = 0), C L = 11, READ preamble = 1tCK, WRITE preamble = 1tCK. DI b = data-in from column b. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write DBI = Disable, Write CRC = Disable. The write timing parameter (tWTR_L) is referenced from the first rising clock edge after the last write data shown at T11. WRITE Operation Followed by PRECHARGE Operation The minimum external WRITE command to PRECHARGE command spacing is equal to WL (AL + CWL) plus either 4tCK (BL8/BC4-OTF) or 2tCK (BC4-fixed) plus tWR. The minimum ACT to PRE timing, t RAS, must be satisfied as well. Figure 190: WRITE (BL8/BC4-OTF) to PRECHARGE with 1tCK Preamble T0 T1 T2 WRITE DES DES T3 T4 T7 T8 T9 T10 DES DES DES DES DES DES T11 T12 T13 T14 T22 DES DES DES DES DES T23 T24 T25 DES DES PRE T26 CK_c CK_t Command WL = AL + CWL = 9 tWR 4 Clocks BGa, Bank b Col n DES tRP = 12 BGa, Bank b (or all) Address BC4 (OTF) Opertaion DQS_t, DQS_c DQ DI n DI n+1 DI n+2 DI n+3 DI n DI n+1 DI n+2 DI n+3 BL8 Opertaion DQS_t, DQS_c DQ DI n+4 DI n+5 DI n+6 DI n+7 Time Break Notes: 1. 2. 3. 4. Transitioning Data Don’t Care BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 234 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time (tWR) is referenced from the first rising clock edge after the last write data shown at T13. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. Figure 191: WRITE (BC4-Fixed) to PRECHARGE with 1tCK Preamble T0 T1 T2 WRITE DES DES T3 T4 T7 T8 T9 DES DES DES DES DES T10 T11 T12 T13 DES DES DES DES T14 T22 T23 DES DES PRE T24 T25 T26 DES DES DES CK_c CK_t Command WL = AL + CWL = 9 tWR 2 Clocks tRP = 12 BGa, Bank b Col n BGa, Bank b (or all) Address BC4 (Fixed) Opertaion DQS_t, DQS_c DI n DQ DI n+1 DI n+2 DI n+3 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T11. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. Figure 192: WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1tCK Preamble T0 T1 T2 WRITE DES DES T3 T4 T7 T8 T9 T10 DES DES DES DES DES DES T11 T12 T13 T14 T22 DES DES DES DES DES T23 T24 T25 DES DES DES T26 CK_c CK_t Command WL = AL + CWL = 9 tWR 4 Clocks DES tRP = 12 BGa, Bank b Col n Address BC4 (OTF) Opertaion DQS_t, DQS_c DQ DI n DI n+1 DI n+2 DI n+3 DI n DI n+1 DI n+2 DI n+3 BL8 Opertaion DQS_t, DQS_c DQ DI n+4 DI n+5 DI n+6 DI n+7 Time Break Transitioning Data Don’t Care BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. 6. The write recovery time ( tWR) is referenced from the first rising clock edge after the last write data shown at T13. tWR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 235 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 193: WRITE (BC4-Fixed) to Auto PRECHARGE with 1tCK Preamble T0 T1 T2 WRITE DES DES T3 T4 T7 T8 T9 DES DES DES DES DES T10 T11 T12 T13 DES DES DES DES T14 T22 T23 T24 DES DES DES DES T25 T26 DES DES CK_c CK_t Command WL = AL + CWL = 9 tWR 2 Clocks tRP = 12 BGa, Bank b Col n Address BC4 (Fixed) Opertaion DQS_t, DQS_c DI n DQ DI n+1 DI n+2 DI n+3 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK, tWR = 12. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, CRC = Disable. The write recovery time (tWR) is referenced from the first rising clock edge after the last write data shown at T11. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. WRITE Operation with WRITE DBI Enabled Figure 194: WRITE (BL8/BC4-OTF) with 1tCK Preamble and DBI T0 T1 T2 WRITE DES DES T3 T4 T5 T6 T7 T8 T9 T10 DES DES DES DES DES DES DES DES T11 T12 T13 T14 DES DES DES DES T15 T16 T17 DES DES DES CK_c CK_t Command WL = AL + CWL = 9 tWR 4 Clocks tWTR Address BGa Address Bank, Col n BC4 (OTF) Opertaion DQS_t, DQS_c DQ DI n DI n+1 DI n+2 DI n+3 DBI_n DI n DI n+1 DI n+2 DI n+3 DQ DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DBI_n DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 BL8 Opertaion DQS_t, DQS_c Transitioning Data Don’t Care BL = 8 with BC4-OTF, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. 5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled. Notes: 1. 2. 3. 4. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 236 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation 6. The write recovery time (tWR_DBI) is referenced from the first rising clock edge after the last write data shown at T13. Figure 195: WRITE (BC4-Fixed) with 1tCK Preamble and DBI T0 T1 T2 WRITE DES DES T3 T4 T5 T6 T7 T8 T9 DES DES DES DES DES DES DES T10 T11 T12 T13 T14 DES DES DES DES DES T15 T16 T17 DES DES DES CK_c CK_t Command WL = AL + CWL = 9 tWR 2 Clocks tWTR Address BGa Address Bank, Col n BC4 (Fixed) Opertaion DQS_t, DQS_c DQ DI n DI n+1 DI n+2 DI n+3 DBI_n DI n DI n+1 DI n+2 DI n+3 Transitioning Data Notes: 1. 2. 3. 4. 5. Don’t Care BC4 = fixed, WL = 9 (CWL = 9, AL = 0 ), Preamble = 1tCK. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10. CA parity = Disable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disabled. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 237 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation WRITE Operation with CA Parity Enabled Figure 196: Consecutive Write (BL8) with 1tCK Preamble and CA Parity in Different Bank Group T0 T1 T2 T3 T4 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 WRITE DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES CK_c CK_t Command tWR tCCD_S Bank Group Address 4 Clocks =4 BGa BGb Address Bank Col n Bank Col b Parity Valid Valid tWTR tWPST tWPRE DQS_t, DQS_c WL = PL + AL + CWL = 13 DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = PL + AL + CWL = 13 Time Break Notes: 1. 2. 3. 4. 5. 6. Transitioning Data Don’t Care BL = 8, WL = 9 (CWL = 13, AL = 0 ), Preamble = 1tCK. DI n = data-in from column n. DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T4. CA parity = Enable, CS to CA latency = Disable, Write DBI = Enabled, Write CRC = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 238 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation WRITE Operation with Write CRC Enabled Figure 197: Consecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 WRITE DES DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES T19 CK_c CK_t Command DES tWR tCCD_S/L Bank Group Address Address 4 Clocks =5 BGa BGa or BGb Bank Col n Bank Col b tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DQ x4, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x8/X16, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x4, BL = 8 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 CRC DI b DI b+1 DI b+2 DI b+3 CRC CRC WL = AL + CWL = 9 DQ x8/X16, BL = 8 CRC Time Break Notes: 1. 2. 3. 4. 5. 6. 7. CRC Transitioning Data Don’t Care BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T5. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T18. Figure 198: Consecutive WRITE (BC4-Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 WRITE DES DES DES DES WRITE DES DES DES DES DES DES DES DES DES DES T18 T19 DES DES CK_c CK_t Command tWR tCCD_S/L Bank Group Address Address 2 Clocks =5 BGa BGa or BGb Bank Col n Bank Col b tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DQ x4, BC = 4 (Fixed) DI n DI n+1 DI n+2 DI n+3 CRC DI n DI n+1 DI n+2 DI n+3 CRC CRC DI b DI b+1 DI b+2 DI b+3 CRC DI b DI b+1 DI b+2 DI b+3 CRC CRC WL = AL + CWL = 9 DQ x8/X16, BC = 4 (Fixed) Time Break CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 239 Transitioning Data Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Notes: 1. 2. 3. 4. 5. 6. BC4-fixed, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 5tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BC4 setting activated by MR0[1:0] = 10 during WRITE commands at T0 and T5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T16. Figure 199: Nonconsecutive WRITE (BL8/BC4-OTF) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 WRITE DES DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES T20 CK_c CK_t Command DES t WR t CCD_S/L 4 Clocks =6 Bank Group Address BGa BGa or BGb Address Bank Col n Bank Col b t WTR t WPST t WPRE DQS_t, DQS_c WL = AL + CWL = 9 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DQ x4, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x8/X16, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x4, BL = 8 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 CRC DI b DI b+1 DI b+2 DI b+3 CRC CRC WL = AL + CWL = 9 DQ x8/X16, BL = 8 CRC Time Break Notes: 1. 2. 3. 4. 5. 6. 7. Transitioning Data CRC Don’t Care BL8/BC4-OTF, AL = 0, CWL = 9, Preamble = 1tCK, tCCD_S/L = 6tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T6. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T6. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T19. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 240 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 200: Nonconsecutive WRITE (BL8/BC4-OTF) with 2tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 WRITE DES WRITE DES DES DES DES DES DES DES DES DES DES DES DES DES DES T22 CK_c CK_t Command DES tWR tCCD_S/L Bank Group Address Address 4 Clocks =7 BGa BGa or BGb Bank Col n Bank Col b tWPRE tWTR tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 10 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DQ x4, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x8/X16, BC = 4 (OTF) DI n DI n+1 DI n+2 DI n+3 CRC DQ x4, BL = 8 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 CRC DI b DI b+1 DI b+2 DI b+3 CRC DI b DI b+1 DI b+2 DI b+3 CRC CRC WL = AL + CWL = 10 DQ x8/X16, BL = 8 CRC Time Break Transitioning Data CRC Don’t Care BL8/BC4-OTF, AL = 0, CWL = 9 + 1 = 10 (see Note 9), Preamble = 2tCK, tCCD_S/L = 7tCK (see Note 7). DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE commands at T0 and T7. BC4 setting activated by MR0[1:0] = 01 and A12 = 0 during WRITE commands at T0 and T7. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Disable. tCCD_S/L = 6tCK is not allowed in 2tCK preamble mode if minimum tCCD_S/L allowed in 1tCK preamble mode would have been 6 clocks. 8. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T21. 9. When operating in 2tCK WRITE preamble mode, CWL may need to be programmed to a value at least 1 clock greater than the lowest CWL setting supported in the applicable tCK range. That means CWL = 9 is not allowed when operating in 2tCK WRITE preamble mode. Notes: 1. 2. 3. 4. 5. 6. 7. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 241 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM WRITE Operation Figure 201: WRITE (BL8/BC4-OTF/Fixed) with 1tCK Preamble and Write CRC in Same or Different Bank Group T0 T1 T2 T6 T7 T8 T9 T10 T11 T12 T13 T14 WRITE DES DES DES DES DES DES DES DES DES DES DES T15 T16 T17 T18 T19 T20 DES DES DES DES DES DES CK_c CK_t Command tWR_CRC_DM 4 Clocks Bank Group Address Address tWTR_S_CRC_DM/tWTR_L_CRC_DM BGa Bank Col n tWPST tWPRE DQS_t, DQS_c WL = AL + CWL = 9 DQ x4, BL = 8 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DQ x8/X16, BL = 8 DI n DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 CRC DM n DM n+1 DM n+2 DM n+3 DM n+4 DM n+5 DM n+6 DM n+7 DQ x4, BC = 4 (OTF/Fixed) DI n DI n+1 DI n+2 DI n+3 CRC DQ x8/X16, BC = 4 (OTF/Fixed) DI n DI n+1 DI n+2 DI n+3 CRC DM n DM n+1 DM n+2 DM n+3 DMx4/x8/x16 BL = 8 DM x4/x8/x16 BC = 4 (OTF / Fixed) CRC CRC Time Break Notes: 1. 2. 3. 4. 5. 6. 7. Transitioning Data Don’t Care BL8/BC4, AL = 0, CWL = 9, Preamble = 1tCK. DI n (or b) = data-in from column n (or column b). DES commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during WRITE command at T0. BC4 setting activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during WRITE command at T0. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable, Write CRC = Enable, DM = Enable. The write recovery time ( tWR_CRC_DM) and write timing parameter (tWTR_S_CRC_DM/tWTR_L_CRC_DM) are referenced from the first rising clock edge after the last write data shown at T13. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 242 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Write Timing Violations Write Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure that the device works properly. However, for certain minor violations, it is desirable that the device is guaranteed not to "hang up" and that errors are limited to that specific operation. A minor violation does not include a major timing violation (for example, when a DQS strobe misses in the tDQSCK window). For the following, it will be assumed that there are no timing violations with regard to the WRITE command itself (including ODT, and so on) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations If the data-to-strobe timing requirements (tDS, tDH) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location addressed with this WRITE command. In the example, the relevant strobe edges for WRITE Burst A are associated with the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, and T8.5. Subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise. Strobe-to-Strobe and Strobe-to-Clock Violations If the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH, tDQSS) are violated, for any of the strobe edges associated with a WRITE burst, then wrong data might be written to the memory location addressed with the offending WRITE command. Subsequent reads from that location might result in unpredictable read data; however, the device will work properly otherwise with the following constraints: s Both write CRC and data burst OTF are disabled; timing specifications other than tDQSH, tDQSL, t WPRE, tWPST, tDSS, tDSH, tDQSS are not violated. s The offending write strobe (and preamble) arrive no earlier or later than six DQS transition edges from the WRITE latency position. s A READ command following an offending WRITE command from any open bank is allowed. s One or more subsequent WR or a subsequent WRA (to same bank as offending WR) may be issued tCCD_L later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data. s One or more subsequent WR or a subsequent WRA (to a different bank group) may be issued tCCD_S later, but incorrect data could be written. Subsequent WR and WRA can be either offending or non-offending writes. Reads from these writes may provide incorrect data. s After one or more precharge commands (PRE or PREA) are issued to the device after an offending WRITE command and all banks are in precharged state (idle state), a subsequent, non-offending WR or WRA to any open bank will be able to write correct data. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 243 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands ZQ CALIBRATION Commands A ZQ CALIBRATION command is used to calibrate DRAM RON and ODT values. The device needs a longer time to calibrate the output driver and on-die termination circuits at initialization and a relatively smaller time to perform periodic calibrations. The ZQCL command is used to perform the initial calibration during the power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. The ZQCL command triggers the calibration engine inside the DRAM and, after calibration is achieved, the calibrated values are transferred from the calibration engine to DRAM I/O, which is reflected as an updated output driver and ODT values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after reset are allowed a timing period of tZQoper. The ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQ correction) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the Output Driver and ODT Voltage and Temperature Sensitivity tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdrift_rate) and voltage (Vdrift_rate) drift rates that the device is subjected to in the application, is illustrated. The interval could be defined by the following formula: ZQcorrection (Tsense x Tdrift_rate) + (Vsense x Tdrift_rate) Where Tsense = MAX(dRTTdT, dRONdTM) and Vsense = MAX(dRTTdV, dRONdVM) define the temperature and voltage sensitivities. For example, if Tsens = 1.5%/ιC, Vsens = 0.15%/mV, Tdriftrate = 1 ιC/sec and Vdriftrate = 15 mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 §128ms (1.5 × 1) + (0.15 × 15) No other activities should be performed on the DRAM channel by the controller for the duration of ZQinit, tZQoper, or tZQCS. The quiet time on the DRAM channel allows accurate calibration of output driver and on-die termination values. After DRAM calibration is achieved, the device should disable the ZQ current consumption path to reduce power. t All banks must be precharged andtRP met before ZQCL or ZQCS commands are issued by the controller. ZQ CALIBRATION commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self refresh exit, the device will not perform an I/O calibration without an explicit ZQ CALIBRATION command. The earliest possible time for a ZQ CALIBRATION command (short or long) after self refresh exit is tXS, tXS_Abort, or tXS_FAST depending on operation mode. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of ZQoper, tZQinit, or tZQCS between the devices. t CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 244 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ZQ CALIBRATION Commands Figure 202: ZQ Calibration Timing T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL DES DES DES Valid Valid ZQCS DES DES DES Valid Address Valid Valid Valid A10 Valid Valid Valid Valid Valid Valid Valid Valid Valid CK_c CK_t Command CKE Note 1 Note 2 ODT DQ Bus High-Z or RTT(Park) Activities High-Z or RTT(Park) Activities Note 3 tZQinit_tZQoper tZQCS Time Break Don’t Care Notes: 1. CKE must be continuously registered HIGH during the calibration procedure. 2. During ZQ calibration, the ODT signal must be held LOW and DRAM continues to provide RTT_PARK. 3. All devices connected to the DQ bus should be High-Z during the calibration procedure. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 245 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM On-Die Termination On-Die Termination The on-die termination (ODT) feature enables the device to change termination resistance for each DQ, DQS, and DM_n/DBI_n signal for x4 and x8 configurations (and TDQS for the x8 configuration when enabled via A11 = 1 in MR1) via the ODT control pin, WRITE command, or default parking value with MR setting. For the x16 configuration, ODT is applied to each UDQ, LDQ, UDQS, LDQS, UDM_n/UDBI_n, and LDM_n/LDBI_n signal. The ODT feature is designed to improve the signal integrity of the memory channel by allowing the DRAM controller to independently change termination resistance for any or all DRAM devices. If DBI read mode is enabled while the DRAM is in standby, either DM mode or DBI write mode must also be enabled if RTT(NOM) or RTT(Park) is desired. More details about ODT control modes and ODT timing modes can be found further along in this document. The ODT feature is turned off and not supported in self refresh mode. Figure 203: Functional Representation of ODT ODT To other circuitry such as RCV, ... VDDQ RTT Switch DQ, DQS, DM, TDQS The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information. The value of RTT is determined by the settings of mode register bits (see Mode Register). The ODT pin will be ignored if the mode register MR1 is programmed to disable RTT(NOM) [MR1[10,9,8] = 0,0,0] and in self refresh mode. ODT Mode Register and ODT State Table The ODT mode of the DDR4 device has four states: data termination disable, RTT(NOM), RTT(WR), and RTT(Park). The ODT mode is enabled if any of MR1[10:8] (RTT(NOM)), MR2[11:9] (RTT(WR)), or MR5[8:6] (RTT(Park)) are non-zero. When enabled, the value of RTT is determined by the settings of these bits. RTT control of each RTT condition is possible with a WR or RD command and ODT pin. s RTT(WR): The DRAM (rank) that is being written to provide termination regardless of ODT pin status (either HIGH or LOW). s RTT(NOM): DRAM turns ON RTT(NOM) if it sees ODT asserted HIGH (except when ODT is disabled by MR1). s RTT(Park): Default parked value set via MR5 to be enabled and RTT(NOM) is not turned on. s The Termination State Table that follows shows various interactions. The RTT values have the following priority: s Data termination disable s RTT(WR) s RTT(NOM) s RTT(Park) CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 246 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM ODT Mode Register and ODT State Table Table 72: Termination State Table Case RTT(Park) A4 Disabled B5 C6 Enabled Disabled RTT(NOM) 1 Disabled Disabled Enabled ODT READS ODT Standby7 ODT WRITES Off (High-Z) Off (High-Z) Off (High-Z) Don't Care Off (High-Z) Off (High-Z) RTT(WR) Disabled Don't Care Off (High-Z) RTT(Park) RTT(Park) Enabled Don't Care Off (High-Z) RTT(Park) RTT(WR) Disabled Low Off (High-Z) Off (High-Z) Off (High-Z) High Off (High-Z) RTT(NOM) RTT(NOM) Low Off (High-Z) Off (High-Z) RTT(WR) High Off (High-Z) RTT(NOM) RTT(WR) Low Off (High-Z) RTT(Park) RTT(Park) High Off (High-Z) RTT(NOM) RTT(NOM) Low Off (High-Z) RTT(Park) RTT(WR) High Off (High-Z) RTT(NOM) RTT(WR) RTT(WR)2 ODT Pin Disabled Don't Care Enabled Enabled D6 Enabled Enabled Disabled Enabled 3 Notes: 1. If RTT(NOM) MR is disabled, power to the ODT receiver will be turned off to save power. 2. If RTT(WR) is enabled, RTT(WR) will be activated by a WRITE command for a defined period time independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the Dynamic ODT section. 3. When a READ command is executed, the DRAM termination state will be High-Z for a defined period independent of the ODT pin and MR setting of RTT(Park)/RTT(NOM). This is described in the ODT During Read section. 4. Case A is generally best for single-rank memories. 5. Case B is generally best for dual-rank, single-slotted memories. 6. Case C and Case D are generally best for multi-slotted memories. 7. The ODT feature is turned off and not supported in self refresh mode. ODT Read Disable State Table Upon receiving a READ command, the DRAM driving data disables ODT after RL - (2 or 3) clock cycles, where 2 = 1tCK preamble mode and 3 = 2tCK preamble mode. ODT stays off for a duration of BL/2 + (2 or 3) + (0 or 1) clock cycles, where 2 = 1tCK preamble mode, 3 = 2tCK preamble mode, 0 = CRC disabled, and 1 = CRC enabled. Table 73: Read Termination Disable Window Preamble 1t CK 2tCK CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN CRC Start ODT Disable After Read Duration of ODT Disable Disabled RL - 2 BL/2 + 2 Enabled RL - 2 BL/2 + 3 Disabled RL - 3 BL/2 + 3 Enabled RL - 3 BL/2 + 4 247 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes include the following: s Any bank active with CKE HIGH s Refresh with CKE HIGH s Idle mode with CKE HIGH s Active power-down mode s Precharge power-down mode In synchronous ODT mode, RTT(NOM) will be turned on DODTLon clock cycles after ODT is sampled HIGH by a rising clock edge and turned off DODTLoff clock cycles after ODT is registered LOW by a rising clock edge. The ODT latency is determined by the programmed values for: CAS WRITE latency (CWL), additive latency (AL), and parity latency (PL), as well as the programmed state of the preamble. ODT Latency and Posted ODT The ODT latencies for synchronous ODT mode are summarized in the table below. For details, refer to the latency definitions. Table 74: ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200 Applicable when write CRC is disabled Symbol Parameter 1tCK Preamble 2tCK Preamble DODTLon Direct ODT turn-on latency CWL + AL + PL - 2 CWL + AL + PL - 3 DODTLoff Direct ODT turn-off latency CWL + AL + PL - 2 CWL + AL + PL - 3 RODTLoff READ command to internal ODT turn-off latency CL + AL + PL - 2 CL + AL + PL - 3 RODTLon4 READ command to RTT(Park) turn-on latency in BC4-fixed RODTLoff + 4 RODTLoff + 5 RODTLon8 READ command to RTT(Park) turn-on latency in BL8/BC4-OTF RODTLoff + 6 RODTLoff + 7 ODTH4 ODT Assertion time, BC4 mode 4 5 ODTH8 ODT Assertion time, BL8 mode 6 7 Unit t CK Timing Parameters In synchronous ODT mode, the following parameters apply: s DODTLon, DODTLoff, RODTLoff, RODTLon4, RODTLon8, and tADC (MIN)/(MAX). s tADC (MIN) and tADC (MAX) are minimum and maximum RTT change timing skew between different termination values. These timing parameters apply to both the synchronous ODT mode and the data termination disable mode. When ODT is asserted, it must remain HIGH until minimum ODTH4 (BC = 4) or ODTH8 (BL = 8) is satisfied. If write CRC mode or 2tCK preamble mode is enabled, ODTH should be adjusted to account for it. ODTHx is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of a WRITE command. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 248 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode Figure 204: Synchronous ODT Timing with BL8 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T1 8 diff_CK Command ODT DODTLon = WL - 2 DODTLoff = WL - 2 t ADC tADC DRAM_RTT tADC (MAX) tADC (MIN) RTT(Park) RTT(NOM) (MAX) (MIN) RTT(Park) Transitioning Notes: 1. Example for CWL = 9, AL = 0, PL = 0; DODTLon = AL + PL + CWL - 2 = 7; DODTLoff = AL + PL + CWL - 2 = 7. 2. ODT must be held HIGH for at least ODTH8 after assertion (T1). Figure 205: Synchronous ODT with BC4 T0 T1 T2 T3 T4 T5 T18 T19 T20 T21 T22 T23 T36 T37 T38 T39 T40 T41 42 diff_CK WRS4 Command ODTH4 ODT DODTLoff = WL - 2 ODTLcnw= WL - 2 ODTLcwn4 = ODTLcnw + 4 DODTLon = CWL - 2 tADC (MAX) tADC RTT(Park) (MIN) tADC (MAX) tADC (MIN) RTT(NOM) RTT(Park) tADC (MAX) tADC (MIN) RTT(WR) tADC tADC (MAX) (MIN) RTT(Park) DRAM_RTT Transitioning Notes: 1. Example for CWL = 9, AL = 10, PL = 0; DODTLon/off = AL + PL+ CWL - 2 = 17; ODTcnw = AL + PL+ CWL - 2 = 17. 2. ODT must be held HIGH for at least ODTH4 after assertion (T1). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 249 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Synchronous ODT Mode ODT During Reads Because the DRAM cannot terminate with RTT and drive with RON at the same time, RTT may nominally not be enabled until the end of the postamble as shown in the example below. At cycle T26 the device turns on the termination when it stops driving, which is determined by tHZ. If the DRAM stops driving early (that is, tHZ is early), thentADC (MIN) timing may apply. If the DRAM stops driving late (that is, t HZ is late), then the DRAM complies with tADC (MAX) timing. Using CL = 11 as an example for the figure below: PL = 0, AL = CL - 1 = 10, RL = PL + AL + CL = 21, CWL= 9; RODTLoff = RL - 2 = 19, DODTLon = PL + AL + CWL - 2 = 17, 1tCK preamble. Figure 206: ODT During Reads T0 T1 T2 T3 T4 T8 T9 T10 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 diff_CK Command Address RD A RL = AL + CL + PL ODT RODTLoff = RL- 2 DODTLon = WL - 2 t ADC DQS_ODT 1t CK Preamble t ADC (MIN) (MAX) (MIN) RTT(NOM) RTT(Park) t ADC t ADC (MAX) t ADC DQS_ODT 2t CK Preamble t ADC (MAX) t ADC t ADC (MIN) (MAX) (MIN) RTT(NOM) RTT(Park) DQSdiff t ADC t ADC DQ_ODT 1t CK Preamble t ADC t ADC (MIN) (MAX) (MIN) RTT(NOM) RTT(Park) DQ QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 t ADC t ADC DQ_ODT 2t CK Preamble (MAX) + 1nCK (MAX) + 2nCK t ADC t ADC (MIN) (MAX) (MIN) RTT(NOM) RTT(Park) DQ QA0 QA1 QA2 QA3 QA4 QA5 QA6 QA7 Transitioning CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 250 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the device can be changed without issuing an MRS command. This requirement is supported by the dynamic ODT feature. Functional Description Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to 1. s Three RTTvalues are available: RTT(NOM), RTT(WR), and RTT(Park). n The value for RTT(NOM) is preselected via bits MR1[10:8]. n The value for RTT(WR) is preselected via bits MR2[11:9]. n The value for RTT(Park) is preselected via bits MR5[8:6]. s During operation without WRITE commands, the termination is controlled as follows: n Nominal termination strength RTT(NOM) or RTT(Park) is selected. n RTT(NOM) on/off timing is controlled via ODT pin and latencies DODTLon and DODTLoff, and RTT(Park) is on when ODT is LOW. s When a WRITE command (WR, WRA, WRS4, WRS8, WRAS4, and WRAS8) is registered, and if dynamic ODT is enabled, the termination is controlled as follows: n Latency ODTLcnw after the WRITE command, termination strength RTT(WR) is selected. n Latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the WRITE command, termination strength RTT(WR) is de-selected. One or two clocks will be added into or subtracted from ODTLcwn8 and ODTLcwn4, depending on write CRC mode and/or 2tCK preamble enablement. The following table shows latencies and timing parameters relevant to the on-die termination control in dynamic ODT mode. The dynamic ODT feature is not supported in DLL-off mode. An MRS command must be used to set RTT(WR) to disable dynamic ODT externally (MR2[11:9] = 000). Table 75: Dynamic ODT Latencies and Timing (1tCK Preamble Mode and CRC Disabled) Name and Description Abbr. Defined from Defined to 1600/1866/ 2133/2400 2666 2933/3200 Unit ODT latency for change from RTT(Park)/RTT(NOM) to RTT(WR) ODTLc nw Registering external WRITE command Change RTT strength from RTT(Park)/RTT(NO M) to RTT(WR) ODTLcnw = WL - 2 ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BC = 4) ODTLcwn4 Registering external WRITE command Change RTT strength from RTT(WR) to RTT(Park)/RTT(NO ODTLcwn4 = 4 + ODTLcnw tCK ODTLcwn8 = 6 + ODTLcnw t t CK M) ODT latency for change from RTT(WR) to RTT(Park)/RTT(NOM) (BL = 8) RTT change skew CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN ODTLcwn8 t ADC Registering external WRITE command Change RTT strength from RTT(NOM) to RTT(WR) ODTLcnw ODTLcwn RTT valid 251 t ADC (MIN) = 0.30 t ADC (MAX) = 0.70 t ADC (MIN) = 0.28 t ADC (MAX) = 0.72 CK (AVG) t t ADC (MIN) = CK 0.26 (AVG) t ADC (MAX) = 0.74 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT Table 76: Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix 1tCK Parameter 2tCK Parameter Symbol CRC Off CRC On CRC Off CRC On Unit ODTLcnw1 WL - 2 WL - 2 WL - 3 WL - 3 ODTLcwn4 ODTLcnw + 4 ODTLcnw + 7 ODTLcnw + 5 ODTLcnw + 8 ODTLcwn8 ODTLcnw + 6 ODTLcnw + 7 ODTLcnw + 7 ODTLcnw + 8 t CK Notes: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble). Figure 207: Dynamic ODT (1t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) T0 T1 T2 T5 T6 T7 T8 T9 T10 T11 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 diff_CK Command WR ODT DODTLon = WL - 2 DODTLoff = WL - 2 tADC tADC (MAX) RTT(Park) RTT tADC (MAX) RTT(WR) tADC tADC (MAX) RTT(NOM) RTT(Park) tADC (MIN) tADC (MIN) (MAX) RTT(Park) tADC (MIN) (MIN) ODTLcnw ODTLcwn Transitioning Notes: 1. ODTLcnw = WL - 2 (1tCK preamble) or WL - 3 (2tCK preamble). 2. If BC4, then ODTLcwn = WL + 4 if CRC disabled or WL + 5 if CRC enabled; If BL8, then ODTLcwn = WL + 6 if CRC disabled or WL + 7 if CRC enabled. Figure 208: Dynamic ODT Overlapped with RTT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled) T0 T1 T2 T5 T6 T7 T9 T10 T11 T12 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T25 diff_CK Command WR ODT ODTLcnw ODTLcwn8 tADC RTT tADC (MAX) RTT_NOM tADC (MAX) RTT_WR tADC RTT_NOM tADC (MIN) (MIN) (MAX) RTT_PARK tADC (MIN) DODTLoff = CWL -2 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 252 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Dynamic ODT Note: 1. Behavior with WR command issued while ODT is registered HIGH. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 253 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Asynchronous ODT Mode Asynchronous ODT Mode Asynchronous ODT mode is selected when the DRAM runs in DLL-off mode. In asynchronous ODT timing mode, the internal ODT command is not delayed by either additive latency (AL) or the parity latency (PL) relative to the external ODT signal (RTT(NOM)). In asynchronous ODT mode, two timing parameters apply: tAONAS (MIN/MAX), and tAOFAS (MIN/MAX). RTT(NOM) Turn-on Time s Minimum RTT(NOM) turn-on time (tAONAS [MIN]) is when the device termination circuit leaves RTT(Park) and ODT resistance begins to turn on. s Maximum RTT(NOM) turn-on time (tAONAS [MAX]) is when the ODT resistance has reached RTT(NOM). s tAONAS (MIN) and tAONAS (MAX) are measured from ODT being sampled HIGH. RTT(NOM) Turn-off Time s Minimum RTT(NOM) turn-off time (tAOFAS [MIN]) is when the device's termination circuit starts to leave RTT(NOM). s Maximum RTT(NOM) turn-off time (tAOFAS [MAX]) is when the on-die termination has reached RTT(Park). s tAOFAS (MIN) and tAOFAS (MAX) are measured from ODT being sampled LOW. Figure 209: Asynchronous ODT Timings with DLL Off T0 T1 T2 T3 T4 T5 T6 Ti Ti + 1 Ti + 2 Ti + 3 Ti + 4 Ti + 5 Ti + 6 Ta Tb diff_CK CKE tIH tIS tIH tIS ODT tAONAS RTT (MAX) tAONAS RTT(Park) (MIN) RTT(NOM) tAONAS (MIN) tAONAS (MAX) Transitioning CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 254 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Electrical Specifications Electrical Specifications Absolute Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Although "unlimited" row accesses to the same row is allowed within the refresh period; excessive row accesses to the same row over a long term can result in degraded operation. Table 77: Absolute Maximum Ratings Symbol Parameter Min Max Unit Notes Voltage on VDD pin relative to VSS n 1.5 V 1 Voltage on VDDQ pin relative to VSS n 1.5 V 1 Voltage on VPP pin relative to VSS n 3.0 V 3 Voltage on any pin relative to VSS n 1.5 V Storage temperature n 150 ιC VDD VDDQ VPP VIN, VOUT TSTG 2 Notes: 1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be greater than 0.6 έ VDDQ. When VDD and VDDQ are 85 105 ιC 2 Notes: 1. The normal temperature range specifies the temperatures at which all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0ιC to 85ιC under all operating conditions for the commercial offering; The industrial and automotive temperature offerings allow the case temperature to go below 0ιC to -40ιC. 2. Some applications require operation of the commercial, industrial, and automotive temperature DRAMs in the extended temperature range (between 85ιC and 105ιC case temperature). Full specifications are supported in this range, but the following additional conditions apply: s Refer to tREFI and tRFC parameters table for tREFI requirements when operating above 85ιC s If SELF REFRESH operation is required in the extended temperature range, it is mandatory to use either the manual self refresh mode with extended temperature range capability (MR2[6] = 0 and MR2 [7] = 1) or enable the optional auto self refresh mode (MR2 [6] = 1 and MR2 [7] = 1). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 255 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS Supply Operating Conditions Table 79: Recommended Supply Operating Conditions Rating Symbol Parameter Min Typ VDD Supply voltage 1.14 VDDQ Supply voltage for output VPP Wordline supply voltage Max Unit Notes 1.2 1.26V 1, 2, 3, 4, 5 1.14 1.2 1.26V 1, 2, 6 2.375 2.5 2.750V 7 Notes: 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. 3. VDD slew rate between 300mV and 80% of VDD,min shall be between 0.004 V/ms and 600 V/ms, 20 MHz band-limited measurement. 4. VDD ramp time from 300mV to VDD,min shall be no longer than 200ms. 5. A stable valid VDD level is a set DC level (0 Hz to 250 KHz) and must be no less than VDD,min and no greater than VDD,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ά60mV (greater than 250 KHz) is allowed on VDD provided the noise doesn't alter VDD to less than VDD,min or greater than VDD,max. 6. A stable valid VDDQ level is a set DC level (0 Hz to 250 KHz) and must be no less than VDDQ,min and no greater than VDDQ,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ά60mV (greater than 250 KHz) is allowed on VDDQ provided the noise doesn't alter VDDQ to less than VDDQ,min or greater than VDDQ,max. 7. A stable valid VPP level is a set DC level (0 Hz to 250 KHz) and must be no less than VPP,min and no greater than VPP,max. If the set DC level is altered anytime after initialization, the DLL reset and calibrations must be performed again after the new set DC level is final. AC noise of ά120mV (greater than 250 KHz) is allowed on VPP provided the noise doesn't alter VPP to less than VPP,min or greater than VPP,max. Table 80: VDD Slew Rate Symbol Min Max Unit Notes VDD_sl 0.004 600 V/ms 1, 2 VDD_on n 200 ms 3 Notes: 1. Measurement made between 300mV and 80% VDD (minimum level). 2. The DC bandwidth is limited to 20 MHz. 3. Maximum time to ramp VDD from 300 mV to VDD minimum. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 256 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS Leakages Table 81: Leakages Condition Symbol Min Max Unit Notes Input leakage (excluding ZQ and TEN) IIN n 2 ρA 1 ZQ leakage IZQ n 10 ρA 1 TEN leakage ITEN n 10 ρA 1, 2 VREFCA leakage IVREFCA n 2 ρA 3 Output leakage: VOUT = VDDQ IOZpd n 10 ρA 4 Output leakage: VOUT = VSSQ IOZpu n n ρA 4, 5 Notes: 1. 2. 3. 4. 5. Input under test 0V < VIN < 1.1V. Additional leakage due to weak pull-down. VREFCA = VDD/2, VDD at valid level after initialization. DQs are disabled. ODT is disabled with the ODT input HIGH. VREFCA Supply VREFCA is to be supplied to the DRAM and equal to VDD/2. The VREFCA is a reference supply input and therefore does not draw biasing current. The DC-tolerance limits and AC-noise limits for the reference voltages VREFCA are illustrated in the figure below. The figure shows a valid reference voltage VREF(t) as a function of time (VREF stands for VREFCA). VREF(DC) is the linear average of VREF(t) over a very long period of time (1 second). This average has to meet the MIN/MAX requirements. Furthermore, VREF(t) may temporarily deviate from VREF(DC) by no more than ά1% VDD for the AC-noise limit. Figure 210: VREFDQ Voltage Range Voltage VDD VREF(t) VREF AC-noise VREF(DC) MAX VREF(DC) VDD/2 VREF(DC) MIN VSS Time The voltage levels for setup and hold time measurements are dependent on VREF. VREF is understood as VREF(DC), as defined in the above figure. This clarifies that DC-variations of VREF affect the absolute CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 257 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS voltage a signal has to reach to achieve a valid HIGH or LOW level, and therefore, the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the specified limit (ά1% of VDD) are included in DRAM timings and their associated deratings. VREFDQ Supply and Calibration Ranges The device internally generates its own VREFDQ. DRAM internal VREFDQ specification parameters: voltage range, step size, VREF step time, VREF full step time, and VREF valid level are used to help provide estimated values for the internal VREFDQ and are not pass/fail limits. The voltage operating range specifies the minimum required range for DDR4 SDRAM devices. The minimum range is defined by VREFDQ,min and VREFDQ,max. A calibration sequence should be performed by the DRAM controller to adjust VREFDQ and optimize the timing and voltage margin of the DRAM data input receivers. Table 82: VREFDQ Specification Parameter Symbol Min Typ Max Unit Notes Range 1 VREFDQ operating points VREFDQ R1 60% n 92% VDDQ 1, 2 Range 2 VREFDQ operating points VREFDQ R2 45% n 77% VDDQ 1, 2 VREF,step 0.5% 0.65% 0.8% VDDQ 3 VREF,set_tol n 0% 1.625% VDDQ 4, 5, 6 n 0% 0.15% VDDQ 4, 7, 8 VREF,time n n 150 ns 9, 10, 11 VREF_val_tol n 0% 0.15% VDDQ 12 VREF step size VREF set tolerance VREF step time VREF valid tolerance Notes: 1. 2. 3. 4. 5. VREF(DC) voltage is referenced to VDDQ(DC). VDDQ(DC) is 1.2V. DRAM range 1 or range 2 is set by the MRS6[6]6. VREF step size increment/decrement range. VREF at DC level. VREF,new = VREF,old άn έ VREF,stepNNUMBEROFSTEPS)FINCREMENTUSEhvIFDECREMENTUSEh v For n >4, the minimum value of VREF setting tolerance = VREF,new - 1.625% έ VDDQ. The maximum value of VREF setting tolerance = VREF,new + 1.625% έ VDDQ. 6. Measured by recording the MIN and MAX values of the VREF output over the range, drawing a straight line between those points, and comparing all other VREF output settings to that line. 7. For n ζ4, the minimum value of VREF setting tolerance = VREF,new - 0.15% έ VDDQ. The maximum value of VREF setting tolerance = VREF,new + 0.15% έ VDDQ. 8. Measured by recording the MIN and MAX values of the VREF output across four consecutive steps (n = 4), drawing a straight line between those points, and comparing all VREF output settings to that line. 9. Time from MRS command to increment or decrement one step size for VREF. 10. Time from MRS command to increment or decrement more than one step size up to the full range of VREF. 11. If the VREF monitor is enabled, VREF must be derated by +10ns if DQ bus load is 0pF and an additional +15 ns/pF of DQ bus loading. 12. Only applicable for DRAM component-level test/characterization purposes. Not applicable for normal mode of operation. VREF valid qualifies the step times, which will be characterized at the component level. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 258 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/PERATING#ONDITIONS VREFDQ Ranges MR6[6] selects range 1 (60% to 92.5% of VDDQ) or range 2 (45% to 77.5% of VDDQ), and MR6[5:0] sets the VREFDQ level, as listed in the following table. The values in MR6[6:0] will update the VDDQ range and level independent of MR6[7] setting. It is recommended MR6[7] be enabled when changing the settings in MR6[6:0], and it is highly recommended MR6[7] be enabled when changing the settings in MR6[6:0] multiple times during a calibration routine. Table 83: VREFDQ Range and Levels MR6[5:0] MR6[6] 0 = Range 1 MR6[6] 1 = Range 2 MR6[5:0] MR6[6] 0 = Range 1 MR6[6] 1 = Range 2 00 0000 60.00% 45.00% 01 1010 76.90% 61.90% 00 0001 60.65% 45.65% 01 1011 77.55% 62.55% 00 0010 61.30% 46.30% 01 1100 78.20% 63.20% 00 0011 61.95% 46.95% 01 1101 78.85% 63.85% 00 0100 62.60% 47.60% 01 1110 79.50% 64.50% 00 0101 63.25% 48.25% 01 1111 80.15% 65.15% 00 0110 63.90% 48.90% 10 0000 80.80% 65.80% 00 0111 64.55% 49.55% 10 0001 81.45% 66.45% 00 1000 65.20% 50.20% 10 0010 82.10% 67.10% 00 1001 65.85% 50.85% 10 0011 82.75% 67.75% 00 1010 66.50% 51.50% 10 0100 83.40% 68.40% 00 1011 67.15% 52.15% 10 0101 84.05% 69.05% 00 1100 67.80% 52.80% 10 0110 84.70% 69.70% 00 1101 68.45% 53.45% 10 0111 85.35% 70.35% 00 1110 69.10% 54.10% 10 1000 86.00% 71.00% 00 1111 69.75% 54.75% 10 1001 86.65% 71.65% 01 0000 70.40% 55.40% 10 1010 87.30% 72.30% 01 0001 71.05% 56.05% 10 1011 87.95% 72.95% 01 0010 71.70% 56.70% 10 1100 88.60% 73.60% 01 0011 72.35% 57.35% 10 1101 89.25% 74.25% 01 0100 73.00% 58.00% 10 1110 89.90% 74.90% 01 0101 73.65% 58.65% 10 1111 90.55% 75.55% 01 0110 74.30% 59.30% 11 0000 91.20% 76.20% 01 0111 74.95% 59.95% 11 0001 91.85% 76.85% 01 1000 75.60% 60.60% 11 0010 92.50% 77.50% 01 1001 76.25% 61.25% CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 11 0011 to 11 1111 are reserved 259 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT-EASUREMENT Levels RESET_n Input Levels Table 84: RESET_n Input Levels (CMOS) Symbol Min Max Unit Note AC input high voltage Parameter VIH(AC)_RESET 0.8 έ VDD VDD V 1 DC input high voltage VIH(DC)_RESET 0.7 έ VDD VDD V 2 DC input low voltage VIL(DC)_RESET VSS 0.3 έ VDD V 3 AC input low voltage VIL(AC)_RESET VSS 0.2 έ VDD V 4 R_RESET n 1 ρs 5 PW_RESET_S Rising time t RESET pulse width after power-up t 1 n ρs 6, 7 RESET pulse width during power-up t 200 n ρs 6 PW_RESET_L Notes: 1. Overshoot should not exceed the VIN shown in the Absolute Maximum Ratings table. 2. After RESET_n is registered HIGH, the RESET_n level must be maintained above VIH(DC)_RESET, otherwise operation will be uncertain until it is reset by asserting RESET_n signal LOW. 3. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RESET during tPW_RESET, otherwise the DRAM may not be reset. 4. Undershoot should not exceed the VIN shown in the Absolute Maximum Ratings table. 5. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible. 6. RESET is destructive to data contents. 7. See RESET Procedure at Power Stable Condition figure. Figure 211: RESET_n Input Slew Rate Definition tPW_RESET VIH(AC)_RESET,min VIH(DC)_RESET,min VIL(DC)_RESET,max VIL(AC)_RESET,max tR_RESET Command/Address Input Levels Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 Parameter Symbol Min Max Unit Note AC input high voltage VIH(AC) VREF + 100 VDD5 mV 1, 2, 3 DC input high voltage VIH(DC) VREF + 75 VDD mV 1, 2 DC input low voltage VIL(DC) VSS VREF - 75 mV 1, 2 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 260 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Table 85: Command and Address Input Levels: DDR4-1600 Through DDR4-2400 (Continued) Parameter Symbol Min Max Unit Note VIL(AC) VSS5 VREF - 100 mV 1, 2, 3 VREFFCA(DC) 0.49 έ VDD 0.51 έ VDD V 4 AC input low voltage Reference voltage for CMD/ADDR inputs Notes: 1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ά1% VDD (for reference: approximately ά12mV). 5. 2EFERTOh/VERSHOOTAND5NDERSHOOT3PECIFICATIONSv Table 86: Command and Address Input Levels: DDR4-2666 Parameter Symbol Min Max Unit Note AC input high voltage VIH(AC) VREF + 90 VDD5 mV 1, 2, 3 DC input high voltage VIH(DC) VREF + 65 VDD mV 1, 2 DC input low voltage VIL(DC) VSS VREF - 65 mV 1, 2 AC input low voltage VIL(AC) VSS5 VREF - 90 mV 1, 2, 3 VREFFCA(DC) 0.49 έ VDD 0.51 έ VDD V 4 Reference voltage for CMD/ADDR inputs Notes: 1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ά1% VDD (for reference: approximately ά12mV). 5. 2EFERTOh/VERSHOOTAND5NDERSHOOT3PECIFICATIONSv Table 87: Command and Address Input Levels: DDR4-2933 and DDR4-3200 Parameter Symbol Min Max Unit Note AC input high voltage VIH(AC) VREF + 90 VDD5 mV 1, 2, 3 DC input high voltage VIH(DC) VREF + 65 VDD mV 1, 2 DC input low voltage VIL(DC) VSS VREF - 65 mV 1, 2 AC input low voltage VIL(AC) VSS5 VREF - 90 mV 1, 2, 3 VREFFCA(DC) 0.49 έ VDD 0.51 έ VDD V 4 Reference voltage for CMD/ADDR inputs Notes: 1. For input except RESET_n. VREF = VREFCA(DC). 2. VREF = VREFCA(DC). 3. Input signal must meet VIL/VIH(AC) to meet tIS timings and VIL/VIH(DC) to meet tIH timings. 4. The AC peak noise on VREF may not allow VREF to deviate from VREFCA(DC) by more than ά1% VDD (for reference: approximately ά12mV). 5. 2EFERTOh/VERSHOOTAND5NDERSHOOT3PECIFICATIONSv Table 88: Single-Ended Input Slew Rates Parameter 3INGLE ENDEDINPUTSLEWRATEn#! CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Symbol Min Max Unit Note SRCA 1.0 7.0 V/ns 1, 2, 3, 4 261 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Notes: 1. For input except RESET_n. 2. VREF = VREFCA(DC). 3. tIS/tIH timings assume SRCA = 1V/ns. 4. Measured between VIH(AC) and VIL(AC) for falling edges and between VIL(AC) and VIH(AC) for rising edges Figure 212: Single-Ended Input Slew Rate Definition Command, Control, and Address Setup, Hold, and Derating The total tIS (setup time) and tIH (hold time) required is calculated to account for slew rate variation by adding the data sheet tIS (base) values, the VIL(AC)/VIH(AC) points, and tIH (base) values, the VIL(DC)/VIH(DC) points; to the ȟtIS and ȟtIH derating values, respectively. The base values are derived with single-end signals at 1V/ns and differential clock at 2 V/ns. Example: tIS (total setup time) = tIS (base) + ȟtIS. For a valid transition, the input signal has to remain above/below VIH(AC)/VIL(AC) for the time defined by tVAC. Although the total setup time for slow slew rates might be negative (for example, a valid input signal will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input signal is still required to complete the transition and to reach VIH(AC)/VIL(AC). For slew rates that fall between the values listed in derating tables, the derating values may be obtained by linear interpolation. Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min . Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)max that does not ring back above VIL(DC)max. Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VIH(AC)min that does not ring back below VIH(DC)min. Hold (tIH) CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 262 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VIL(AC)minthat does not ring back above VIL(DC)max. Table 89: #OMMANDAND!DDRESS3ETUPAND(OLD6ALUES2EFERENCEDn!#$# "ASED Symbol 1600 1866 2133 2400 2666 2933 3200 Unit Reference IS(base, AC100) 115 100 80 62 n n n ps VIH(AC)/VIL(AC) t IH(base, DC75) 140 125 105 87 n n n ps VIH(DC)/VIL(DC) t IS(base, AC90) n n n n 55 48 40 ps VIH(AC)/VIL(AC) IH(base, DC65) n n n n 80 73 65 ps VIH(DC)/VIL(DC) tIS/tIH(Vref) 215 200 180 162 145 138 130 ps VIH(DC)/VIL(DC) t t Table 90: Derating Values for tIS/t)(n!#$# "ASED ȟtIS with AC100 Threshold, ȟt)(WITH$#4HRESHOLD$ERATINGPS n!#$# "ASED CK, CK# Differential Slew Rate 10.0 V/ns 8.0 V/ns 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.5 V/ns 1.0 V/ns CMD/ADD R Slew Rate V/ns ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIH 7.0 76 54 76 55 77 56 79 58 82 60 86 64 94 73 111 89 6.0 73 53 74 53 75 54 77 56 79 58 83 63 92 71 108 88 5.0 70 50 71 51 72 52 74 54 76 56 80 60 88 68 105 85 4.0 65 46 66 47 67 48 69 50 71 52 75 56 83 65 100 81 3.0 57 40 57 41 58 42 60 44 63 46 67 50 75 58 92 75 2.0 40 28 41 28 42 29 44 31 46 33 50 38 58 46 75 63 1.5 23 15 24 16 25 17 27 19 29 21 33 25 42 33 58 50 1.0 n n n n n n n n n n 0 0 8 8 25 25 0.9 n n n n n n n n n n n n 1 4 18 21 0.8 n n n n n n n n n n n n n n 9 16 0.7 n n n n n n n n n n n n n n n 9 0.6 n n n n n n n n n n n n n n n 0 0.5 n n n n n n n n n n n n n n n n 0.4 n n n n n n n n n n n n n n n n CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 263 ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Table 91: Derating Values for tIS/t)(n!#$# "ASED ȟtIS with AC90 Threshold, ȟt)(WITH$#4HRESHOLD$ERATINGPS n!#$# "ASED CK, CK# Differential Slew Rate 10.0 V/ns 8.0 V/ns 6.0 V/ns 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.5 V/ns 1.0 V/ns CMD/ADD R Slew Rate V/ns ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH ȟtIH 7.0 68 47 69 47 70 48 72 50 73 52 77 56 85 63 100 78 6.0 66 45 67 46 68 47 69 49 71 50 75 54 83 62 98 77 5.0 63 43 64 44 65 45 66 46 68 48 72 52 80 60 95 75 4.0 59 40 59 40 60 41 62 43 64 45 68 49 75 56 90 71 3.0 51 34 52 35 53 36 54 38 56 40 60 43 68 51 83 66 2.0 36 24 37 24 38 25 39 27 41 29 45 33 53 40 68 55 1.5 21 13 22 13 23 14 24 16 26 18 30 22 38 29 53 44 1.0 n n n n n n n n n n 0 0 8 8 23 23 0.9 n n n n n n n n n n n n 1 4 16 19 0.8 n n n n n n n n n n n n n n 8 14 0.7 n n n n n n n n n n n n n n n 9 0.6 n n n n n n n n n n n n n n n 1 0.5 n n n n n n n n n n n n n n n n 0.4 n n n n n n n n n n n n n n n n ȟtIH ȟtIS ȟtIH ȟtIS ȟtIH Data Receiver Input Requirements The following parameters apply to the data receiver Rx MASK operation detailed in the Write Timing section, Data Strobe-to-Data Relationship. The rising edge slew rates are defined by srr1 and srr2. The slew rate measurement points for a rising edge are shown in the figure below. A LOW-to-HIGH transition time, tr1, is measured from 0.5 έ VdiVW,max below VCENTDQ,midpoint to the last transition through 0.5 έ VdiVW,max above VCENTDQ,midpoint; tr2 is measured from the last transition through 0.5 έ VdiVW,max above VCENTDQ,midpoint to the first transition through the 0.5 έ VIHL(AC)min above VCENTDQ,midpoint. The falling edge slew rates are defined by srf1 and srf2. The slew rate measurement points for a falling edge are shown in the figure below. A HIGH-to-LOW transition time, tf1, is measured from 0.5 έ VdiVW,max above VCENTDQ,midpoint to the last transition through 0.5 έ VdiVW,max below VCENTDQ,midpoint; tf2 is measured from the last transition through 0.5 έ VdiVW,max below VCENTDQ,midpoint to the first transition through the 0.5 έ VIHL(AC)min below VCENTDQ,midpoint. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 264 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Figure 213: DQ Slew Rate Definitions 0.5 × VIHL(AC)min VdiVW,max 0.5 × VIHL(AC)min 0.5 × VdiVW,max Rx Mask VCENTDQ,midpoint 0.5 × VdiVW,max tr1 0.5 × VdiVW,max Rx Mask VdiVW,max 0.5 × VIHL(AC)min tf1 VCENTDQ,midpoint 0.5 × VIHL(AC)min VIHL(AC)min VIHL(AC)min tr2 0.5 × VdiVW,max tf2 Notes: 1. Rising edge slew rate equation srr1 = VdiVW,max/(tr1). 2. Rising edge slew rate equation srr2 = (VIHL(AC)min - VdiVW,max )/(2 έ tr2). 3. Falling edge slew rate equation srf1 = VdiVW,max/(tf1). 4. Falling edge slew rate equation srf2 = (VIHL(AC)min - VdiVW,max )/(2 έ tf2). Table 92: DQ Input Receiver Specifications DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes VIN Rx mask input peak-to-peak VdiVW n 136 n 130 n 120 n 115 n 110 mV 2, 3 DQ Rx input timing window TdiVW n 0.2 n 0.2 n 0.22 n 0.23 n 0.23 UI 2, 3 DQ AC input swing peak-to-peak VIHL(AC) 186 n 160 n 150 n 145 n 140 n mV 4, 5 DQ input pulse width TdiPW 0.58 n 0.58 n 0.58 n 0.58 n 0.58 n UI 6 Parameter CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 265 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Table 92: DQ Input Receiver Specifications (Continued) DDR4-1600, 1866, 2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes DQS2DQ n 0.17 n 0.17 n 0.19 n 0.22 n 0.22 UI 7 DQ-to-DQ Rx mask offset tDQ2DQ n 0.1 n 0.1 n 0.105 n 0.115 n 0.125 UI 8 Input slew rate over VdiVW if srr1, srf1 1 9 1 9 1 9 1 9 1 9 V/ns 9 srr1, srf1 n n 1.25 9 1.25 9 1.25 9 1.25 9 V/ns 9 Rising input slew rate over 1/2 VIHL(AC) srr2 0.2 έ srr1 9 0.2 έ srr1 9 0.2 έ srr1 9 0.2 έ srr1 9 0.2 έ srr1 9 V/ns 10 Falling input slew rate over 1/2 VIHL(AC) srf2 0.2 έ srf1 9 0.2 έ srf1 9 0.2 έ srf1 9 0.2 έ srf1 9 0.2 έ srf1 9 V/ns 10 Parameter DQS-to-DQ Rx mask offset t t CK η 0.937ns Input slew rate over VdiVW if 0.937ns > tCK η 0.625ns Notes: 1. All Rx mask specifications must be satisfied for each UI. For example, if the minimum input pulse width is violated when satisfying TdiVW (MIN), VdiVW,max, and minimum slew rate limits, then either TdiVW (MIN) or minimum slew rates would have to be increased to the point where the minimum input pulse width would no longer be violated. 2. Data Rx mask voltage and timing total input valid window where VdiVW is centered around VCENTDQ,midpoint after VREFDQ training is completed. The data Rx mask is applied per bit and should include voltage and temperature drift terms. The input buffer design specification is to achieve at least a BER =1e- 16 when the Rx mask is not violated. 3. Defined over the DQ internal VREF range 1. 4. Overshoot and undershoot specifications apply. 5. DQ input pulse signal swing into the receiver must meet or exceed VIHL(AC)min. VIHL(AC)min is to be achieved on an UI basis when a rising and falling edge occur in the same UI (a valid TdiPW). 6. DQ minimum input pulse width defined at the VCENTDQ,midpoint. 7. DQS-to-DQ Rx mask offset is skew between DQS and DQ within a nibble (x4) or word (x8, x16 [for x16, the upper and lower bytes are treated as separate x8s]) at the SDRAM balls over process, voltage, and temperature. 8. DQ-to-DQ Rx mask offset is skew between DQs within a nibble (x4) or word (x8, x16) at the SDRAM balls for a given component over process, voltage, and temperature. 9. Input slew rate over VdiVW mask centered at VCENTDQ,midpoint. Slowest DQ slew rate to fastest DQ slew rate per transition edge must be within 1.7V/ns of each other. 10. Input slew rate between VdiVW mask edge and VIHL(AC)min points. 11. Note 1 applies to the entire table. The following figure shows the Rx mask relationship to the input timing specifications relative to system tDS and tDH. The classical definition for tDS/tDH required a DQ rising and falling edges to not violate tDS and tDH relative to the DQS strobe at any time; however, with the Rx mask tDS and tDH can shift relative to the DQS strobe provided the input pulse width specification is satisfied and the Rx mask is not violated. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 266 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Figure 214: Rx Mask Relative to tDS/tDH TdiPW VIH(DC) VdiVW 0.5 × VdiVW VCENTDQ,pin mean Rx Mask 0.5 × VdiVW VIL(DC) tf1 tDS tr1 TdiVW = Greater of 0.5 × TdiVW or 0.5 × (TdiPW + VdiVW/tf1) tDH = Greater of 0.5 × TdiVW or 0.5 × (TdiPW + VdiVW/tr1) DQS_c DQS_t The following figure and table show an example of the worst case Rx mask required if the DQS and DQ pins do not have DRAM controller to DRAM write DQ training. The figure and table show that without DRAM write DQ training, the Rx mask would increase from 0.2UI to essentially 0.54UI. This would also be the minimum tDS and tDH required as well. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 267 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Figure 215: Rx Mask Without Write Training TdiVW + 2 × tDQS2DQ VdiVW VIH(DC) 0.5 × VdiVW Rx Mask VCENTDQ,midpoint 0.5 × VdiVW VIL(DC) tDS tDH 0.5 × TdiVW + tDQS2DQ 0.5 × TdiVW + tDQS2DQ DQS_c DQS_t Table 93: Rx Mask and tDS/tDH without Write Training DQ2DQ (UI) Rx Mask with Write Train (ps) ά0.17 0.1 125 338 0.2 ά0.17 0.1 107.1 289 136 0.2 ά0.17 0.1 94 253 0.58 130 0.2 ά0.17 0.1 83.3 225 150 0.58 120 0.22 ά0.19 0.105 82.5 225 2933 145 0.58 115 0.23 ά0.22 0.115 78.4 228 3200 140 0.58 110 0.23 ά0.22 0.125 71.8 209 DDR4 VIHL(AC) (mV) TdiPW (UI) VdiVW (mV) TdiVW (UI) 1600 186 0.58 136 0.2 1866 186 0.58 136 2133 186 0.58 2400 160 2666 t DQS2DQ (UI) t t DS + tDH (ps) Notes: 1. VIHL(AC), VdiVW, and VILH(DC) referenced to VCENTDQ,midpoint. Connectivity Test (CT) Mode Input Levels Table 94: TEN Input Levels (CMOS) Parameter Symbol Min Max Unit Note TEN AC input high voltage VIH(AC)_TEN 0.8 έ VDD VDD V 1 TEN DC input high voltage VIH(DC)_TEN 0.7 έ VDD VDD V TEN DC input low voltage VIL(DC)_TEN VSS 0.3 έ VDD V TEN AC input low voltage VIL(AC)_TEN VSS 0.2 έ VDD V n 10 ns TEN falling time CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN t F_TEN 268 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Table 94: TEN Input Levels (CMOS) (Continued) Parameter Symbol Min Max Unit tR_TEN n 10 ns TEN rising time Note Notes: 1. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table. 2. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table. Figure 216: TEN Input Slew Rate Definition VIH(AC)_TENmin VIH(DC)_TENmin VIL(DC)_TENmin VIL(AC)_TENmin tF_TEN tR_TEN Table 95: CT Type-A Input Levels Symbol Min CTipA AC input high voltage Parameter VIH(AC) VREF + 200 Max Unit Note V VDD1 2, 3 CTipA DC input high voltage VIH(DC) VREF + 150 VDD V 2, 3 CTipA DC input low voltage VIL(DC) VSS VREF - 150 V 2, 3 CTipA AC input low voltage VIL(AC) VSS1 1 VREF - 200 V 2, 3 1 CTipA falling time t F_CTipA n 5 ns 2 CTipA rising time tR_CTipA n 5 ns 2 Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-A inputs: CS_n, BG[1:0], BA[1:0], A[9:0], A10/AP, A11, A12/BC_n, A13, WE_n/A14, CAS_n/A15, RAS_n/A16, A17, CKE, ACT_n, ODT, CLK_t, CLK_C, PAR. 3. VREFCA = 0.5 έ VDD. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 269 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Figure 217: CT Type-A Input Slew Rate Definition VIH(AC)_CTipAmin VIH(DC)_CTipAmin VREFCA VIL(DC)_CTipAmax VIL(AC)_CTipAmax tF_CTipA tR_CTipA Table 96: CT Type-B Input Levels Symbol Min CTipB AC input high voltage Parameter VIH(AC) VREF + 300 Max Unit Note V VDD1 2, 3 CTipB DC input high voltage VIH(DC) VREF + 200 VDD V 2, 3 CTipB DC input low voltage VIL(DC) VSS VREF - 200 V 2, 3 CTipB AC input low voltage VIL(AC) VSS11 VREF - 300 V 2, 3 1 CTipB falling time t F_CTipB n 5 ns 2 CTipB rising time t R_CTipB n 5 ns 2 Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-B inputs: DML_n/DBIL_n, DMU_n/DBIU_n and DM_n/DBI_n. 3. VREFDQ should be 0.5 έ VDD Figure 218: CT Type-B Input Slew Rate Definition VIH(AC)_CTipBmin VIH(DC)_CTipBmin VREFDQ VIL(DC)_CTipBmax VIL(AC)_CTipBmax tF_CTipB tR_CTipB Table 97: CT Type-C Input Levels (CMOS) Parameter Symbol Min Max Unit Note CTipC AC input high voltage VIH(AC)_CTipC 0.8 έ VDD VDD1 V 2 CTipC DC input high voltage VIH(DC)_CTipC 0.7 έ VDD VDD V 2 CTipC DC input low voltage VIL(DC)_CTipC VSS 0.3 έ VDD V 2 CTipC AC input low voltage VIL(AC)_CTipC VSS1 0.2 έ VDD V 2 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 270 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#3INGLE %NDED)NPUT Measurement Levels Table 97: CT Type-C Input Levels (CMOS) (Continued) Parameter Symbol Min Max Unit Note CTipC falling time tF_CTipC n 10 ns 2 CTipC rising time t n 10 ns 2 R_CTipC Notes: 1. Refer to Overshoot and Undershoot Specifications. 2. CT Type-C inputs: Alert_n. Figure 219: CT Type-C Input Slew Rate Definition VIH(AC)_TENmin VIH(DC)_TENmin VIL(DC)_TENmin VIL(AC)_TENmin tF_TEN tR_TEN Table 98: CT Type-D Input Levels Parameter Symbol Min Max Unit Note CTipD AC input high voltage VIH(AC)_CTipD 0.8 έ VDD VDD V 4 CTipD DC input high voltage VIH(DC)_CTipD 0.7 έ VDD VDD V 2 CTipD DC input low voltage VIL(DC)_CTipD VSS 0.3 έ VDD V 1 CTipD AC input low voltage VIL(AC)_CTipD VSS 0.2 έ VDD V 5 R_RESET n 1 ρs 3 PW_RESET_S Rising time t RESET pulse width - after power-up t 1 n ρs RESET pulse width - during power-up t 200 n ρs PW_RESET_L Notes: 1. After RESET_n is registered LOW, the RESET_n level must be maintained below VIL(DC)_RESET during tPW_RESET, otherwise, the DRAM may not be reset. 2. After RESET_n is registered HIGH, the RESET_n level must be maintained above VIH(DC)_RESET, otherwise, operation will be uncertain until it is reset by asserting RESET_n signal LOW. 3. Slope reversal (ring-back) during this level transition from LOW to HIGH should be mitigated as much as possible. 4. Overshoot should not exceed the VIN values in the Absolute Maximum Ratings table. 5. Undershoot should not exceed the VIN values in the Absolute Maximum Ratings table. 6. CT Type-D inputs: RESET_n; same requirements as in normal mode. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 271 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels Figure 220: CT Type-D Input Slew Rate Definition tPW_RESET VIH(AC)_RESETmin VIH(DC)_RESETmin VIL(DC)_RESETmax VIL(AC)_RESETmax tR_RESET %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT-EASUREMENT Levels Differential Inputs Figure 221: $IFFERENTIAL!#3WINGANDh4IME%XCEEDING!# ,EVELvtDVAC tDVAC VIH,diff(AC)min VIH,diff,min CK_t, CK_c 0.0 VIL,diff,max VIL,diff(AC)max tDVAC Half cycle Notes: 1. Differential signal rising edge from VIL,diff,max to VIH,diff(AC)min must be monotonic slope. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 272 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels 2. Differential signal falling edge from IH,diff,min to VIL,diff(AC)max must be monotonic slope. Table 99: Differential Input Swing Requirements for CK_t, CK_c DDR4-1600 / 1866 / 2133 DDR4-2400 / 2666 DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Min Max Unit Notes Differential input high VIHdiff 150 Note 3 135 Note 3 125 Note 3 110 Note 3 mV 1 Differential input low VILdiff Note 3 n Note 3 -135 Note 3 -125 Note 3 -110 mV 1 Differential input high (AC) VIH- V 2 diff(AC) Note 3 2έ Note 3 2έ Note 3 2έ Note 3 2έ (VIH(AC) (VIH(AC) (VIH(AC) (VIH(AC) - VREF) - VREF) - VREF) - VREF) Differential input low (AC) Note 3 2έ Note 3 2έ Note 3 2έ 2έ (VIL(AC) (VIL(AC) (VIL(AC) (VIL(AC) - VREF) - VREF) - VREF) - VREF) V 2 diff(AC) Parameter VIL- Note 3 Notes: 1. Used to define a differential signal slew-rate. 2. For CK_t, CK_c use VIH(AC) and VIL(AC) of ADD/CMD and VREFCA. 3. These values are not defined; however, the differential signals (CK_t, CK_c) need to be within the respective limits, VIH(DC)max and VIL(DC)min for single-ended signals as well as the limitations for overshoot and undershoot. Table 100: Minimum Time AC Time tDVAC for CK t DVAC (ps) at |VIH,diff(AC) to VIL,diff(AC)| Slew Rate (V/ns) 200mV TBDmV >4.0 120 TBD 4.0 115 TBD 3.0 110 TBD 2.0 105 TBD 1.9 100 TBD 1.6 95 TBD 1.4 90 TBD 1.2 85 TBD 1.0 80 TBD VDD/2 + 145mV N/A 120mV VDD/2 + 100mV ζ VSEH ζ VDD/2 + 145mV N/A (VSEH - VDD/2) - 25mV VDD/2 - 145mV ζ VSEL ζ VDD/2 - 100mV n6DD/2 - VSEL) + 25mV N/A VSEL < VDD/2 - 145mV nM6 N/A Table 104: Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 DDR4-2666, 2933, 3200 Parameter Differential input cross point voltage relative to VDD/2 for CK_t, CK_c Sym Input Level Min Max VIX(CK) VSEH > VDD/2 + 145mV N/A 110mV VDD/2 + 90mV ζ VSEH ζ VDD/2 + 145mV N/A (VSEH - VDD/2) - 30mV VDD/2 - 145mV ζ VSEL ζ VDD/2 - 90mV n6DD/2 - VSEL) + 30mV N/A VSEL < VDD/2 - 145mV nM6 N/A CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 276 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels DQS Differential Input Signal Definition and Swing Requirements DQS_t, DQS_c: Differential Input Voltage Figure 225: Differential Input Signal Definition for DQS_t, DQS_c VIH,diff,peak Half cycle 0.0V Half cycle VIL,diff,peak Table 105: DDR4-1600 through DDR4-2400 Differential Input Swing Requirements for DQS_t, DQS_c DDR4-1600, 1866, 2133 Parameter DDR4-2400 Symbol Min Max Min Max Unit Notes Peak differential input high voltage VIH,diff,peak 186 VDDQ 160 VDDQ mV 1, 2 Peak differential input low voltage VIL,diff,peak VSSQ n VSSQ n mV 1, 2 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Minimum value point is used to determine differential signal slew-rate. Table 106: DDR4-2633 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c DDR4-2666 DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Unit Notes Peak differential input high voltage VIH,diff,peak 150 VDDQ 145 VDDQ 140 VDDQ mV 1, 2 Peak differential input low voltage VIL,diff,peak VSSQ n VSSQ n VSSQ n mV 1, 2 Parameter Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Minimum value point is used to determine differential signal slew-rate. The peak voltage of the DQS signals are calculated using the following equations: VIH,dif,Peak voltage = MAX(ft) VIL,dif,Peak voltage = MIN(ft) (ft) = DQS_t, DQS_c. The MAX(f(t)) or MIN(f(t)) used to determine the midpoint from which to reference the ά35% window of the exempt non-monotonic signaling shall be the smallest peak voltage observed in all UIs. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 277 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels DQS_t, DQS_c: Single-Ended Input Voltages Figure 226: DQS_t, DQS_c Input Peak Voltage Calculation and Range of Exempt non-Monotonic Signaling CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN DQS_t +35% +50% MIN(ft) MAX(ft) –35% –50% DQS_c 278 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels DQS Differential Input Cross Point Voltage To achieve tight RxMask input requirements as well as output skew parameters with respect to strobe, the cross point voltage of differential input signals (DQS_t, DQS_c) must meet VIX_DQS,ratio in the table below. The differential input cross point voltage VIX_DQS (VIX_DQS_FR and VIX_DQS_RF) is measured from the actual cross point of DQS_t, DQS_c relative to the VDQS,mid of the DQS_t and DQS_c signals. VDQS,mid is the midpoint of the minimum levels achieved by the transitioning DQS_t and DQS_c signals, and noted by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQS,mid of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of THETRANSITIONING$13SIGNALS!NON MONOTONICTRANSITIONINGSIGNALSLEDGEISEXEMPTORNOTUSEDIN determination of a horizontal tangent provided the said ledge occurs within ά35% of the midpoint of either VIH.DIFF.Peak voltage (DQS_t rising) or VIL.DIFF.Peak voltage (DQS_c rising), as shown in the figure below. A secondary horizontal tangent resulting from a ring-back transition is also exempt in determination OFAHORIZONTALTANGENT4HATISAFALLINGTRANSITIONSHORIZONTALTANGENTISDERIVEDFROMITSNEGATIVE SLOPETOZEROSLOPETRANSITIONPOINT!INTHEFIGUREBELOW ANDARING BACKSHORIZONTALTANGENTIS derived from its positive slope to zero slope transition (point B in the figure below) and is not a valid HORIZONTALTANGENTARISINGTRANSITIONSHORIZONTALTANGENTISDERIVEDFROMITSPOSITIVESLOPETOZERO SLOPETRANSITIONPOINT#INTHEFIGUREBELOW ANDARING BACKSHORIZONTALTANGENTDERIVEDFROMITS negative slope to zero slope transition (point D in the figure below) and is not a valid horizontal tangent. Figure 227: VIXDQS Definition Lowest horizontal tanget above VDQS,mid of the transitioning signals VIX_DQS,RF VDQS,mid VIX_DQS,FR VIX_DQS,RF B VDQS_trans D VIX_DQS,FR VDQS_trans/2 DQS_t, DQS_c: Single-Ended Input Voltages C DQS_t DQS_c A Highest horizontal tanget below VDQS,mid of the transitioning signals VSSQ Table 107: Cross Point Voltage For Differential Input Signals DQS DDR4-1600, 1866, 2133, 2400, 2666, 2933, 3200 Parameter DQS_t and DQS_c crossing relative to the midpoint of the DQS_t and DQS_c signal swings VDQS,mid to Vcent(midpoint) offset Symbol Min Max Unit Notes VIX_DQS,ratio n 25 % 1, 2 VDQS,mid_to_V- n Note 3 mV 2 cent CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 279 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels Notes: 1. VIX_DQS,ratio is DQS VIX crossing (VIX_DQS,FR or VIX_DQS,RF) divided by VDQS_trans. VDQS_trans is the difference between the lowest horizontal tangent above VDQS,midd of the transitioning DQS signals and the highest horizontal tangent below VDQS,mid of the transitioning DQS signals. 2. VDQS,mid will be similar to the VREFDQ internal setting value (Vcent(midpoint) offset) obtained during VREF Training if the DQS and DQs drivers and paths are matched. 3. The maximum limit shall not exceed the smaller of V IH,diff,DQS minimum limit or 50mV. Slew Rate Definitions for DQS Differential Input Signals Table 108: DQS Differential Input Slew Rate Definition Measured Description From To Defined by Differential input slew rate for rising edge VIL,diff,DQS VIH,diff,DQS |VIH,diff,DQS - VIL,diff,DQS|/ȟTRdiff Differential input slew rate for falling edge VIH,diff,DQS VIL,diff,DQS |VIHdiffDQS - VIL,diff,DQS|/ȟTFdiff Notes: 1. The differential signal DQS_t, DQS_c must be monotonic between these thresholds. Figure 228: Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c Table 109: DDR4-1600 through DDR4-2400 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c DDR4-1600, 1866, 2133 Parameter DDR4-2400 Symbol Min Max Min Max Unit Notes Peak differential input high voltage VIH,diff,peak 186 VDDQ 160 VDDQ mV 1 Differential input high voltage VIH,diff,DQS 136 n 130 n mV 2, 3 Differential input low voltage VIL,diff,DQS n n n n mV 2, 3 Peak differential input low voltage VIL,diff,peak -VDDQ n -VDDQ n mV 1 SRIdiff 3.0 18 3.0 18 V/ns 4, 5 DQS differential input slew rate Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |VIL,diff,min VIH,diff,max|/ȟTRdiff. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 280 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#$IFFERENTIAL)NPUT Measurement Levels 5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |VIL,diff,min VIH,diff,max|/ȟTFdiff. Table 110: DDR4-2666 through DDR4-3200 Differential Input Slew Rate and Input Levels for DQS_t, DQS_c DDR4-2666 Parameter DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Unit Notes Peak differential input high voltage VIH,diff,peak 150 VDDQ 145 VDDQ 140 VDDQ mV 1 Differential input high voltage VIH,diff,DQS 130 n 115 n 110 n mV 2, 3 Differential input low voltage VIL,diff,DQS n n n n n n mV 2, 3 Peak differential input low voltage VIL,diff,peak VSSQ n VSSQ n VSSQ n mV 1 DQS differential input slew rate SRIdiff 2.5 18 2.5 18 2.5 18 V/ns 4, 5 Notes: 1. Minimum and maximum limits are relative to single-ended portion and can be exceeded within allowed overshoot and undershoot limits. 2. Differential signal rising edge from VIL,diff,DQS to VIH,diff,DQS must be monotonic slope. 3. Differential signal falling edge from VIH,diff,DQS to VIL,diff,DQS must be monotonic slope. 4. Differential input slew rate for rising edge from VIL,diff,DQS to VIH,diff,DQS is defined by |VIL,diff,min VIH,diff,max|/ȟTRdiff. 5. Differential input slew rate for falling edge from VIH,diff,DQS to VIL,diff,DQS is defined by |VIL,diff,min VIH,diff,max|/ȟTFdiff. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 281 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/VERSHOOTAND5NDERSHOOT Specifications %LECTRICAL#HARACTERISTICSn/VERSHOOTAND5NDERSHOOT3PECIFICATIONS Address, Command, and Control Overshoot and Undershoot Specifications Table 111: ADDR, CMD, CNTL Overshoot and Undershoot/Specifications DDR4- DDR41600 1866 Description DDR42133 DDR4- DDR4- DDR4- DDR42400 2666 2933 3200 Unit Address and control pins (A[17:0], BG[1:0], BA[1:0], CS_n, RAS_n, CAS_n, WE_n, CKE, ODT, C2-0) Area A: Maximum peak amplitude above VDD absolute MAX 0.06 0.06 0.06 0.06 0.06 0.06 0.06 V Area B: Amplitude allowed between VDD and VDD absolute MAX 0.24 0.24 0.24 0.24 0.24 0.24 0.24 V Area C: Maximum peak amplitude allowed for undershoot below VSS 0.30 0.30 0.30 0.30 0.30 0.30 0.30 V Area A maximum overshoot area per 1tCK 0.0083 0.0071 0.0062 0.0055 0.0055 0.0055 0.0055 V/ns Area B maximum overshoot area per 1tCK 0.2550 0.2185 0.1914 0.1699 0.1699 0.1699 0.1699 V/ns Area C maximum undershoot area per 1tCK 0.2644 0.2265 0.1984 0.1762 0.1762 0.1762 0.1762 V/ns Figure 229: ADDR, CMD, CNTL Overshoot and Undershoot Definition Absolute MAX overshoot Volts (V) VDD absolute MAX VDD VSS A Overshoot area above VDD absolute MAX B Overshoot area below VDD absolute MAX and above VDD MAX 1tCK C CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Undershoot area below VSS 282 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/VERSHOOTAND5NDERSHOOT Specifications Clock Overshoot and Undershoot Specifications Table 112: CK Overshoot and Undershoot/ Specifications DDR41600 DDR41866 DDR42133 DDR42400 DDR42666 DDR42933 DDR43200 Unit Area A: Maximum peak amplitude above VDD absolute MAX 0.06 0.06 0.06 0.06 0.06 0.06 0.06 V Area B: Amplitude allowed between VDD and VDD absolute MAX 0.24 0.24 0.24 0.24 0.24 0.24 0.24 V Area C: Maximum peak amplitude allowed for undershoot below VSS 0.30 0.30 0.30 0.30 0.30 0.30 0.30 V Area A maximum overshoot area per 1UI 0.0038 0.0032 0.0028 0.0025 0.0025 0.0025 0.0025 V/ns Area B maximum overshoot area per 1UI 0.1125 0.0964 0.0844 0.0750 0.0750 0.0750 0.0750 V/ns Area C maximum undershoot area per 1UI 0.1144 0.0980 0.0858 0.0762 0.0762 0.0762 0.0762 V/ns Description CLK_t, CLK_n Figure 230: CK Overshoot and Undershoot Definition Absolute MAX overshoot Volts (V) VDD absolute MAX A Overshoot area above VDD absolute MAX B Overshoot area below VDD absolute MAX and above VDD MAX VDD VSS 1UI C CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Undershoot area below VSS 283 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/VERSHOOTAND5NDERSHOOT Specifications Data, Strobe, and Mask Overshoot and Undershoot Specifications Table 113: Data, Strobe, and Mask Overshoot and Undershoot/ Specifications DDR41600 Description DDR41866 DDR42133 DDR42400 DDR42666 DDR42933 DDR43200 Unit DQS_t, DQS_n, LDQS_t, LDQS_n, UDQS_t, UDQS_n, DQ[0:15], DM/DBI, UDM/UDBI, LDM/LDBI, Area A: Maximum peak amplitude above VDDQ absolute MAX 0.16 0.16 0.16 0.16 0.16 0.16 0.16 V Area B: Amplitude allowed between VDDQ and VDDQ absolute MAX 0.24 0.24 0.24 0.24 0.24 0.24 0.24 V Area C: Maximum peak amplitude allowed for undershoot below VSSQ 0.30 0.30 0.30 0.30 0.30 0.30 0.30 V Area D: Maximum peak amplitude below VSSQ absolute MIN 0.10 0.10 0.10 0.10 0.10 0.10 0.10 V Area A maximum overshoot area per 1UI 0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100 V/ns Area B maximum overshoot area per 1UI 0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700 V/ns Area C maximum undershoot area per 1UI 0.1050 0.0900 0.0788 0.0700 0.0700 0.0700 0.0700 V/ns Area D maximum undershoot area per 1UI 0.0150 0.0129 0.0113 0.0100 0.0100 0.0100 0.0100 V/ns Figure 231: Data, Strobe, and Mask Overshoot and Undershoot Definition Absolute MAX overshoot Volts (V) VDDQ absolute MAX A Overshoot area above VDDQ absolute MAX B Overshoot area below VDDQ absolute MAX and above VDDQ MAX VDDQ 1UI VSSQ C VSSQ absolute MIN Undershoot area below VSSQ MIN and above VSSQ absolute MIN D Undershoot area below VSSQ absolute MIN Absolute MAX undershoot CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 284 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT Levels %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT,EVELS Single-Ended Outputs Table 114: Single-Ended Output Levels Parameter Symbol DDR4-1600 to DDR4-3200 Unit DC output high measurement level (for IV curve linearity) VOH(DC) 1.1 έ VDDQ V DC output mid measurement level (for IV curve linearity) VOM(DC) 0.8 έ VDDQ V DC output low measurement level (for IV curve linearity) VOL(DC) 0.5 έ VDDQ V AC output high measurement level (for output slew rate) VOH(AC) (0.7 + 0.15) έ VDDQ V AC output low measurement level (for output slew rate) VOL(AC) (0.7 - 0.15) έ VDDQ V Notes: 1. The swing of ά0.15 έ VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50ȳ to VTT = VDDQ. Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL(AC) and VOH(AC) for single-ended signals. Table 115: Single-Ended Output Slew Rate Definition Measured Description From To Defined by Single-ended output slew rate for rising edge VOL(AC) VOH(AC) [VOH(AC) - VOL(AC)]/ȟTRse Single-ended output slew rate for falling edge VOH(AC) VOL(AC) [VOH(AC) - VOL(AC)]/ȟTFse CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 285 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT Levels Figure 232: Single-ended Output Slew Rate Definition TRse Single-Ended Output Voltage (DQ) VOH(AC) VOL(AC) TFse Table 116: Single-Ended Output Slew Rate DDR4-1600/ 1866 / 2133 / 2400 Parameter DDR4-2666 DDR4-2933 / 3200 Symbol Min Max Min Max Min Max Unit SRQse 4 9 4 9 4 9 V/ns Single-ended output slew rate Notes: 1. SR = slew rate; Q = query output; se = single-ended signals. 2. In two cases a maximum slew rate of 12V/ns applies for a single DQ signal within a byte lane: s Case 1 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are static (they stay at either HIGH or LOW). s Case 2 is defined for a single DQ signal within a byte lane that is switching into a certain direction (either from HIGH-to-LOW or LOW-to-HIGH) while all remaining DQ signals in the same byte lane are switching into the opposite direction (from LOW-to-HIGH or HIGH-to-LOW, respectively). For the remaining DQ signal switching into the opposite direction, the standard maximum limit of 9 V/ns applies. 3. For RON = RZQ/7. Differential Outputs Table 117: Differential Output Levels Parameter Symbol DDR4-1600 to DDR4-3200 Unit AC differential output high measurement level (for output slew rate) VOH,diff(AC) 0.3 έ VDDQ V AC differential output low measurement level (for output slew rate) VOL,diff(AC) nέ VDDQ V CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 286 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT Levels Notes: 1. The swing of ά0.3 έ VDDQ is based on approximately 50% of the static single-ended output peak-to-peak swing with a driver impedance of RZQ/7 and an effective test load of 50ȳ to VTT = VDDQ at each differential output. Using the same reference load used for timing measurements, output slew rate for falling and rising edges is defined and measured between VOL,diff(AC) and VOH,diff(AC) for differential signals. Table 118: Differential Output Slew Rate Definition Measured Description From To Defined by Differential output slew rate for rising edge VOL,diff(AC) VOH,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ȟTRdiff Differential output slew rate for falling edge VOH,diff(AC) VOL,diff(AC) [VOH,diff(AC) - VOL,diff(AC)]/ȟTFdiff Figure 233: Differential Output Slew Rate Definition Differential Input Voltage (DQS_t, DQS_c) TRdiff VOH,diff(AC) VOL,diff(AC) TFdiff CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 287 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT Levels Table 119: Differential Output Slew Rate DDR4-1600 / 1866 / 2133 / 2400 Parameter Differential output slew rate DDR4-2666 DDR4-2933 / 3200 Symbol Min Max Min Max Min Max Unit SRQdiff 8 18 8 18 8 18 V/ns Notes: 1. SR = slew rate; Q = query output; diff = differential signals. 2. For RON = RZQ/7. Reference Load for AC Timing and Output Slew Rate The effective reference load of 50ȳ to VTT = VDDQ and driver impedance of RZQ/7 for each output was used in defining the relevant AC timing parameters of the device as well as output slew rate measurements. RON nominal of DQ, DQS_t and DQS_c drivers uses 34 ohms to specify the relevant AC timing parameter values of the device. The maximum DC high level of output signal = 1.0 έ VDDQ, the minimum DC low level of output signal = { 34 /( 34 + 50 ) } έ VDDQ = 0.4 έ VDDQ. The nominal reference level of an output signal can be approximated by the following: The center of maximum DC high and minimum DC low = { ( 1 + 0.4 ) / 2 } έ VDDQ = 0.7 έ VDDQ. The actual reference level of output signal might vary with driver RON and reference load tolerances. Thus, the actual referENCELEVELORMIDPOINTOFANOUTPUTSIGNALISATTHEWIDESTPARTOFTHEOUTPUTSIGNALSEYE Figure 234: Reference Load For AC Timing and Output Slew Rate VDDQ VTT = VDDQ DQ, DQS_t, DQS_c, DM, TDQS_t, TDQS_c CK_t, CK_c DUT RTT = 50ȍ VSSQ Timing reference point Connectivity Test Mode Output Levels Table 120: Connectivity Test Mode Output Levels Parameter Symbol DDR4-1600 to DDR4-3200 Unit DC output high measurement level (for IV curve linearity) VOH(DC) 1.1 έ VDDQ V DC output mid measurement level (for IV curve linearity) VOM(DC) 0.8 έ VDDQ V DC output low measurement level (for IV curve linearity) VOL(DC) 0.5 έ VDDQ V DC output below measurement level (for IV curve linearity) VOB(DC) 0.2 έ VDDQ V AC output high measurement level (for output slew rate) VOH(AC) VTT + (0.1 έ VDDQ) V CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 288 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT-EASUREMENT Levels Table 120: Connectivity Test Mode Output Levels (Continued) Parameter Symbol DDR4-1600 to DDR4-3200 Unit AC output low measurement level (for output slew rate) VOL(AC) VTT - (0.1 έ VDDQ) V Notes: 1. Driver impedance of RZQ/7 and an effective test load of 50ȳ to VTT = VDDQ. Figure 235: Connectivity Test Mode Reference Test Load VDDQ CT_Inputs DUT DQ, DQS_t, DQS_c, LDQS_t, LDQS_c, UDQS_t, UDQS_c, DM, LDM, HDM, TDQS_t, TDQS_c 0.5 × VDDQ RTT = 50 ȍ VSSQ Timing reference point Figure 236: Connectivity Test Mode Output Slew Rate Definition VOH(AC) VTT 0.5 x VDD VOL(AC) TFoutput_CT TRoutput_CT Table 121: Connectivity Test Mode Output Slew Rate DDR4-1600 / 1866 / 2133 / 2400 Parameter DDR4-2666 DDR4-2933 / 3200 Symbol Min Max Min Max Min Max Unit Output signal falling time TF_output_CT n 10 n 10 n 10 ns/V Output signal rising time TR_output_CT n 10 n 10 n 10 ns/V CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 289 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER#HARACTERISTICS Connectivity Test Mode Output Driver Electrical Characteristics The DDR4 driver supports special values during connectivity test mode. These RON values are referenced in this section. A functional representation of the output buffer is shown in the figure below. Figure 237: Output Driver During Connectivity Test Mode Chip in drive mode Output driver VDDQ IPU_CT To other circuitry like RCV, ... RONPU_CT DQ IOUT RONPD_CT VOUT IPD_CT VSSQ The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON = RZQ/7. This targets 34ȳ with nominal RZQ = 240ȳ; however, connectivity test mode uses uncalibrated drivers and only a maximum target is defined. Mismatch between pull up and pull down is undefined. The individual pull-up and pull-down resistors (RONPu_CT and RONPd_CT) are defined as follows: RONPu_CT when RONPd_CT is off: RONPU_CT = VDDQ - VOUT IOUT RONPD_CT when RONPU_CT is off: RONPD_CT = CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 290 VOUT IOUT Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics Table 122: Output Driver Electrical Characteristics During Connectivity Test Mode RON,nom_CT Resistor RONPD_CT 34ȳ RONPU_CT VOUT Min Nom Max Unit VOB(DC) = 0.2 έ VDDQ N/A N/A 1.9 RZQ/7 VOL(DC) = 0.5 έ VDDQ N/A N/A 2.0 RZQ/7 VOM(DC) = 0.8 έ VDDQ N/A N/A 2.2 RZQ/7 VOH(DC) = 1.1 έ VDDQ N/A N/A 2.5 RZQ/7 VOB(DC) = 0.2 έ VDDQ N/A N/A 1.9 RZQ/7 VOL(DC) = 0.5 έ VDDQ N/A N/A 2.0 RZQ/7 VOM(DC) = 0.8 έ VDDQ N/A N/A 2.2 RZQ/7 VOH(DC) = 1.1 έ VDDQ N/A N/A 2.5 RZQ/7 Notes: 1. Assumes RZQ = 240ȳ; ZQ calibration not required. Output Driver Electrical Characteristics The DDR4 driver supports two RON values. These RON values are referred to as strong mode (low RON: 34ȳ) and weak mode (high RON: 48ȳ). A functional representation of the output buffer is shown in the figure below. Figure 238: Output Driver: Definition of Voltages and Currents Chip in drive mode Output driver VDDQ IPU To other circuitry like RCV, ... RONPU DQ IOUT RONPD VOUT IPD VSSQ The output driver impedance, RON, is determined by the value of the external reference resistor RZQ as follows: RON(34) = RZQ/7, or RON(48) = RZQ/5. This provides either a nominal 34.3ȳ ά10% or 48ȳ ά10% with nominal RZQ = 240ȳ. The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: RONPu when RONPd is off: CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 291 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics RONPU = VDDQ - VOUT IOUT RONPD when RONPU is off: RONPD = VOUT IOUT Table 123: Strong Mode (34ȳ) Output Driver Electrical Characteristics RON,nom Resistor VOUT Min Nom Max Unit Notes VOL(DC) = 0.5 έ VDDQ 0.73 1.00 1.10 RZQ/7 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.83 1.00 1.10 RZQ/7 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.83 1.00 1.25 RZQ/7 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.90 1.00 1.25 RZQ/7 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.90 1.00 1.10 RZQ/7 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.80 1.00 1.10 RZQ/7 1, 2, 3 Mismatch between pull-up and pull-down, MMPUPD VOM(DC) = 0.8 έ VDDQ 10 n 23 % 1, 2, 3, 4, 6, 7 Mismatch between DQ to DQ within byte variation pull-up, MMPUdd VOM(DC) = 0.8 έ VDDQ n n 10 % 1, 2, 3, 4, 5 Mismatch between DQ to DQ within byte variation pull-down, MMPDdd VOM(DC) = 0.8 έ VDDQ - n 10 % 1, 2, 3, 4, 6, 7 RON34PD 34ȳ RON34PU Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 έ VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 έ VDDQ and 1.1 VDDQ. 4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized). 5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure both RONPU and RONPD at 0.8 έ VDDQ separately; RON,nom is the nominal RON value: MMPUPD = RONPU - RONPD × 100 RON,nom 6. RON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c: MMPUDD = MMPDDD = RONPU,max - RONPU,min RON,nom × 100 RONPD,max - RONPD,min × 100 RON,nom 7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. 4HEMINIMUMVALUESAREDERATEDBYWHENTHEDEVICEOPERATESBETWEENnιC and 0ιC (TC). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 292 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics 9. Assumes RZQ = 240ȳ; entire operating temperature range after proper ZQ calibration. Table 124: Weak Mode (48ȳ) Output Driver Electrical Characteristics RON,nom Resistor VOUT Min Nom Max Unit Notes 48ȳ RON48PD VOL(DC) = 0.5 έ VDDQ 0.73 1.00 1.10 RZQ/5 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.83 1.00 1.10 RZQ/5 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.83 1.00 1.25 RZQ/5 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.90 1.00 1.25 RZQ/5 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.90 1.00 1.10 RZQ/5 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.80 1.00 1.10 RZQ/5 1, 2, 3 Mismatch between pull-up and pull-down, MMPUPD VOM(DC) = 0.8 έ VDDQ 10 n 23 % 1, 2, 3, 4, 6, 7 Mismatch between DQ to DQ within byte variation pull-up, MMPUdd VOM(DC) = 0.8 έ VDDQ n n 10 % 1, 2, 3, 4, 5 Mismatch between DQ to DQ within byte variation pull-down, MMPDdd VOM(DC) = 0.8 έ VDDQ n n 10 % 1, 2, 3, 4, 6, 7 RON48PU Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Micron recommends calibrating pull-down and pull-up output driver impedances at 0.8 έ VDDQ. Other calibration schemes may be used to achieve the linearity specification shown above; for example, calibration at 0.5 έ VDDQ and 1.1 VDDQ. 4. DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c (characterized). 5. Measurement definition for mismatch between pull-up and pull-down, MMPUPD: Measure both RONPU and RONPD at 0.8 έ VDDQ separately; RON,nom is the nominal RON value: MMPUPD = RONPU - RONPD × 100 RON,nom 6. RON variance range ratio to RON nominal value in a given component, including DQS_t and DQS_c: MMPUDD = MMPDDD = RONPU,max - RONPU,min RON,nom RONPD,max - RONPD,min RON,nom × 100 × 100 7. The lower and upper bytes of a x16 are each treated on a per byte basis. 8. 4HEMINIMUMVALUESAREDERATEDBYWHENTHEDEVICEOPERATESBETWEENnιC and 0ιC (TC). 9. Assumes RZQ = 240ȳ; entire operating temperature range after proper ZQ calibration Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the equations and tables below. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 293 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics ȟT = T - T(@calibration); ȟV = VDDQ - VDDQ(@ calibration); VDD = VDDQ Table 125: Output Driver Sensitivity Definitions Symbol Min Max Unit RONPU@ VOH(DC) 0.6 - dRONdTH έ |ȟT| - dRONdVH έ |ȟV| 1.1 _ dRONdTH έ |ȟT| + dRONdVH έ |ȟV| RZQ/6 RON@ VOM(DC) 0.9 - dRONdTM έ |ȟT| - dRONdVM έ |ȟV| 1.1 + dRONdTM έ |ȟT| + dRONdVM έ |ȟV| RZQ/6 RONPD@ VOL(DC) 0.6 - dRONdTL έ |ȟT| - dRONdVL έ |ȟV| 1.1 + dRONdTL έ |ȟT| + dRONdVL έ |ȟV| RZQ/6 Table 126: Output Driver Voltage and Temperature Sensitivity Voltage and Temperature Range Symbol Min Max Unit dRONdTM 0 1.5 %/ιC dRONdVM 0 0.15 %/mV dRONdTL 0 1.5 %/ιC dRONdVL 0 0.15 %/mV dRONdTH 0 1.5 %/ιC dRONdVM 0 0.15 %/mV Alert Driver A functional representation of the alert output buffer is shown in the figure below. Output driver impedance, RON, is defined as follows. Figure 239: Alert Driver Alert driver DRAM Alert RONPD IOUT IPD VOUT VSSQ RONPD when RONPU is off: RONPD = CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 294 VOUT IOUT Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn!#AND$#/UTPUT$RIVER Characteristics Table 127: Alert Driver Voltage RON,nom Register VOUT Min Nom Max Unit N/A RONPD VOL(DC) = 0.1 έ VDDQ 0.3 N/A 1.2 RZQ/7 VOM(DC) = 0.8 έ VDDQ 0.4 N/A 1.2 RZQ/7 VOH(DC) = 1.1 έ VDDQ 0.4 N/A 1.4 RZQ/7 Notes: 1. VDDQ voltage is at VDDQ(DC). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 295 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS ODT Levels and I-V Characteristics On-die termination (ODT) effective resistance settings are defined and can be selected by any or all of the following options: s MR1[10:8] (RTT(NOM)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms. s MR2[11:9] (RTT(WR)): Disable, 240 ohms,120 ohms, and 80 ohms. s MR5[8:6] (RTT(Park)): Disable, 240 ohms, 120 ohms, 80 ohms, 60 ohms, 48 ohms, 40 ohms, and 34 ohms. ODT is applied to the following inputs: s x4: DQ, DM_n, DQS_t, and DQS_c inputs. s x8: DQ, DM_n, DQS_t, DQS_c, TDQS_t, and TDQS_c inputs. s x16: DQ, LDM_n, UDM_n, LDQS_t, LDQS_c, UDQS_t, and UDQS_c inputs. A functional representation of ODT is shown in the figure below. Figure 240: ODT Definition of Voltages and Currents Chip in termination mode ODT To other circuitry like RCV, ... VDDQ RTT DQ IOUT VOUT VSSQ Table 128: ODT DC Characteristics RTT VOUT Min Nom Max Unit Notes 240 ohm VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/2 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/2 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/2 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/3 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/3 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/3 1, 2, 3 120 ohm 80 ohm CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 296 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS Table 128: ODT DC Characteristics (Continued) RTT VOUT Min Nom Max Unit Notes 60 ohm VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/4 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/4 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/4 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/5 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/5 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/5 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/6 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/6 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/6 1, 2, 3 VOL(DC) = 0.5 έ VDDQ 0.9 1 1.25 RZQ/7 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0.9 1 1.1 RZQ/7 1, 2, 3 VOH(DC) = 1.1 έ VDDQ 0.8 1 1.1 RZQ/7 1, 2, 3 VOM(DC) = 0.8 έ VDDQ 0 n 10 % 1, 2, 4, 5, 6 48 ohm 40 ohm 34 ohm DQ-to-DQ mismatch within byte Notes: 1. The tolerance limits are specified after calibration to 240 ohm ά1% resistor with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see ODT Temperature and Voltage Sensitivity. 2. Micron recommends calibrating pull-up ODT resistors at 0.8 έ VDDQ. Other calibration schemes may be used to achieve the linearity specification shown here. 3. The tolerance limits are specified under the condition that VDDQ = VDD and VSSQ = VSS. 4. The DQ-to-DQ mismatch within byte variation for a given component including DQS_t and DQS_c. 5. RTT variance range ratio to RTT nominal value in a given component, including DQS_t and DQS_c. DQ-to-DQ mismatch = RTT(MAX) - RTT(MIN) RTT(NOM) × 100 6. DQ-to-DQ mismatch for a x16 device is treated as two separate bytes. 7. &OR)4!4AND54DEVICESTHEMINIMUMVALUESAREDERATEDBYWHENTHEDEVICEOPERATESBETWEENnιC and 0ιC (TC). ODT Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the following equations and tables. ȟT = T - T(@ calibration); ȟV = VDDQ - VDDQ(@ calibration); VDD = VDDQ Table 129: ODT Sensitivity Definitions Parameter RTT@ CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Min Max Unit 0.9 - dRTTdT έ |ȟT| - dRTTdV έ |ȟV| 1.6 + dRTTdTH έ |ȟT| + dRTTdVH έ |ȟV| RZQ/n 297 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS Table 130: ODT Voltage and Temperature Sensitivity Parameter Min Max Unit dRTTdT 0 1.5 %/ιC dRTTdV 0 0.15 %/mV ODT Timing Definitions The reference load for ODT timings is different than the reference load used for timing measurements. Figure 241: ODT Timing Reference Load VDDQ DQ, DQS_t, DQS_c, DM, TDQS_t, TDQS_c CK_t, CK_c DUT RTT = 50ȍ VTT = VSSQ VSSQ Timing reference point ODT Timing Definitions and Waveforms Definitions fortADC, tAONAS, and tAOFAS are provided in the 4 and shown in 3 and 5. Measurement reference settings are provided in the subsequent 5. The tADC for the dynamic ODT case and read disable ODT cases are represented by tADC of Direct ODT Control case. Table 131: ODT Timing Definitions Parameter Begin Point Definition End Point Definition Figure Rising edge of CK_t, CK_c defined by the end point of DOD- Extrapolated point at VRTT,nom TLoff 3 Rising edge of CK_t, CK_c defined by the end point of DOD- Extrapolated point at VSSQ TLon 3 Rising edge of CK_t, CK_c defined by the end point of ODTLcnw Extrapolated point at VRTT,nom 4 Rising edge of CK_t, CK_c defined by the end point of ODTLcwn4 or ODTLcwn8 Extrapolated point at VSSQ 4 t Rising edge of CK_t, CK_c with ODT being first registered HIGH Extrapolated point at VSSQ 5 t Rising edge of CK_t, CK_c with ODT being first registered LOW Extrapolated point at VRTT,nom 5 tADC AONAS AOFAS CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 298 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS Table 132: Reference Settings for ODT Timing Measurements Measure Parameter RTT(Park) RTT(NOM) RTT(WR) VSW1 VSW2 Note Disable RZQ/7 (34ȳ) n 0.20V 0.40V 1, 2, 4 n RZQ/7 (34ȳ) High-Z 0.20V 0.40V 1, 3, 5 tAONAS Disable RZQ/7 (34ȳ) n 0.20V 0.40V 1, 2, 6 tAOFAS Disable RZQ/7 (34ȳ) n 0.20V 0.40V 1, 2, 6 t ADC Notes: 1. MR settings are as follows: MR1 has A10 = 1, A9 = 1, A8 = 1 for RTT(NOM) setting; MR5 has A8 = 0, A7 = 0, A6 = 0 for RTT(Park) setting; and MR2 has A11 = 0, A10 = 1, A9 = 1 for RTT(WR) setting. 2. ODT state change is controlled by ODT pin. 3. ODT state change is controlled by a WRITE command. 4. Refer to Figure 3. 5. Refer to Figure 4. 6. Refer to Figure 5. Figure 242: tADC Definition with Direct ODT Control DODTLoff Begin point: Rising edge of CK_t, CK_c defined by the end point of DODTLoff DODTLon Begin point: Rising edge of CK_t, CK_c defined by the end point of DODTLon CK_c CK_t tADC VRTT,nom DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN tADC End point: Extrapolated point at VRTT,nom VRTT,nom Vsw2 Vsw1 VSSQ 299 VSSQ End point: Extrapolated point at VSSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM %LECTRICAL#HARACTERISTICSn/N $IE4ERMINATION#HARACTERISTICS Figure 243: tADC Definition with Dynamic ODT Control ODTLcnw Begin point: Rising edge of CK_t, CK_c defined by the end point of ODTLcnw ODTLcnw4/8 Begin point: Rising edge of CK_t, CK_c defined by the end point of ODTLcnw4 or ODTLcnw8 CK_c CK_t tADC VRTT,nom tADC End point: Extrapolated point at VRTT,nom VRTT,nom Vsw2 DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c Vsw1 VSSQ VSSQ End point: Extrapolated point at VSSQ Figure 244: tAOFAS and tAONAS Definitions Rising edge of CK_t, CK_c with ODT being first registered LOW Rising edge of CK_t, CK_c with ODT being first registered HIGH CK_c CK_t tAOFAS VRTT,nom DQ, DM DQS_t, DQS_c TDQS_t, TDQS_c CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN tAONAS End point: Extrapolated point at VRTT_NOM VRTT,nom Vsw2 Vsw1 VSSQ 300 VSSQ End point: Extrapolated point at VSSQ Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications DRAM Package Electrical Specifications Table 133: DRAM Package Electrical Specifications for x4 and x8 Devices 1600/1866/2133/ 2400/2666 Parameter 2933 3200 Symbol Min Max Min Max Min Max Unit Notes ZIO 45 85 48 85 48 85 ohm 1, 2, 4 TdIO 14 42 14 40 14 40 ps 1, 3, 4 Lpkg LIO n 3.3 n 3.3 n 3.3 nH 10 Cpkg CIO n 0.78 n 0.78 n 0.78 pF 11 Zpkg ZIO DQS 45 85 48 85 48 85 ohm 1, 2 Package delay TdIO DQS 14 42 14 40 14 40 ps 1, 3 Delta Zpkg DZIO DQS n 10 n 10 n 10 ohm 1, 2, 6 Delta delay DTdIO DQS n 5 n 5 n 5 ps 1, 3, 6 Lpkg LIO DQS n 3.3 n 3.3 n 3.3 nH 10 Cpkg CIO DQS n 0.78 n 0.78 n 0.78 pF 11 Zpkg ZI CTRL 50 90 50 90 50 90 ohm 1, 2, 8 TdI CTRL 14 42 14 40 14 40 ps 1, 3, 8 Lpkg LI CTRL n 3.4 n 3.4 n 3.4 nH 10 Cpkg CI CTRL n 0.7 n 0.7 n 0.7 pF 11 Zpkg ZI ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7 TdI ADD CMD 14 45 14 40 14 40 ps 1, 3, 7 Lpkg LI ADD CMD n 3.6 n 3.6 n 3.6 nH 10 Cpkg CI ADD CMD n 0.74 n 0.74 n 0.74 pF 11 Zpkg ZCK 50 90 50 90 50 90 ohm 1, 2 TdCK 14 42 14 42 14 42 ps 1, 3 Delta Zpkg DZDCK n 10 n 10 n 10 ohm 1, 2, 5 Delta delay DTdDCK n 5 n 5 n 5 ps 1, 3, 5 Lpkg LI CLK n 3.4 n 3.4 n 3.4 nH 10 Cpkg CI CLK n 0.7 n 0.7 n 0.7 pF 11 ZQ Zpkg ZO ZQ n 100 n 100 n 100 ohm 1, 2 ZQ delay TdO ZQ 20 90 20 90 20 90 ps 1, 3 ALERT Zpkg ZO ALERT 40 100 40 100 40 100 ohm 1, 2 ALERT delay TdO ALERT 20 55 20 55 20 55 ps 1, 3 Input/output DQS_t, DQS_c Input CTRL pins Input CMD ADD pins CK_t, CK_c Zpkg Package delay Package delay Package delay Package delay Notes: 1. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these values but use the Micron package model. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 301 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side. 2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg). 3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg έ Cpkg). 4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c. 5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td). 6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td). 7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n, ACT_n, and PAR. 8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown. 10. It is assumed that Lpkg can be approximated as Lpkg = ZO έ Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO. Table 134: DRAM Package Electrical Specifications for x16 Devices 1600/1866/2133/ 2400/2666 Parameter Input/output Symbol Zpkg ZIO Package delay TdIO 2933 3200 Min Max Min Max Min Max Unit Notes 45 85 45 85 45 85 ohm 1, 2, 4 14 45 14 45 14 45 ps 1, 3, 4 Lpkg LIO n 3.4 n 3.4 n 3.4 nH 11 Cpkg CIO n 0.82 n 0.82 n 0.82 pF 11 45 85 45 85 45 85 ohm 1, 2 14 45 14 45 14 45 ps 1, 3 n 3.4 n 3.4 n 3.4 nH 11 CIO DQS n 0.82 n 0.82 n 0.82 pF 11 LDQS_t/LDQ Delta Zpkg S_c, UDQS_t/UD Delta delay QS_c, DZIO DQS n 10.5 n 10.5 n 10.5 ohm 1, 2, 6 DTdIO DQS n 5 n 5 n 5 ps 1, 3, 6 Input CTRL pins ZI CTRL 50 90 50 90 50 90 ohm 1, 2, 8 14 42 14 42 14 42 ps 1, 3, 8 LDQS_t/LDQ Zpkg ZIO DQS S_c/UDQS_t/ Package delay TdIO DQS UDQS_c Lpkg LIO DQS Cpkg Input CMD ADD pins Zpkg Package delay TdI CTRL Lpkg LI CTRL n 3.4 n 3.4 n 3.4 nH 11 Cpkg CI CTRL n 0.7 n 0.7 n 0.7 pF 11 Zpkg ZI ADD CMD 50 90 50 90 50 90 ohm 1, 2, 7 14 52 14 52 14 52 ps 1, 3, 7 Package delay TdI ADD CMD Lpkg LI ADD CMD n 3.9 n 3.9 n 3.9 nH 11 Cpkg CI ADD CMD n 0.86 n 0.86 n 0.86 pF 11 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 302 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications Table 134: DRAM Package Electrical Specifications for x16 Devices (Continued) 1600/1866/2133/ 2400/2666 Parameter CK_t, CK_c Symbol Zpkg ZCK Package delay TdCK 2933 3200 Min Max Min Max Min Max Unit Notes 50 90 50 90 50 90 ohm 1, 2 14 42 14 42 14 42 ps 1, 3 Delta Zpkg DZDCK n 10.5 n 10.5 n 10.5 ohm 1, 2, 5 Delta delay DTdDCK n 5 n 5 n 5 ps 1, 3, 5 Lpkg LI CLK n 3.4 n 3.4 n 3.4 nH 11 Cpkg CI CLK n 0.7 n 0.7 n 0.7 pF 11 ZQ Zpkg ZO ZQ n 100 n 100 n 100 ohm 1, 2 ZQ delay TdO ZQ 20 90 20 90 20 90 ps 1, 3 ALERT Zpkg ZO ALERT 40 100 40 100 40 100 ohm 1, 2 ALERT delay TdO ALERT 20 55 20 55 20 55 ps 1, 3 Input CLK Notes: 1. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these values but use the Micron package model. The package parasitic (L and C) are validated using package only samples. The capacitance is measured with VDD, VDDQ, VSS, and VSSQ shorted with all other signal pins floating. The inductance is measured with VDD, VDDQ, VSS, and VSSQ shorted and all other signal pins shorted at the die, not pin, side. 2. Package-only impedance (Zpkg) is calculated based on the Lpkg and Cpkg total for a given pin where: Zpkg (total per pin) = SQRT (Lpkg/Cpkg). 3. Package-only delay (Tpkg) is calculated based on Lpkg and Cpkg total for a given pin where: Tdpkg (total per pin) = SQRT (Lpkg έ Cpkg). 4. ZIO and TdIO apply to DQ, DM, TDQS_t and TDQS_c. 5. Absolute value of ZCK_t, ZCK_c for impedance (Z) or absolute value of TdCK_t, TdCK_c for delay (Td). 6. Absolute value of ZIO (DQS_t), ZIO (DQS_c) for impedance (Z) or absolute value of TdIO (DQS_t), TdIO (DQS_c) for delay (Td). 7. ZI ADD CMD and TdI ADD CMD apply to A[17:0], BA[1:0], BG[1:0], RAS_n CAS_n, WE_n, ACT_n, and PAR. 8. ZI CTRL and TdI CTRL apply to ODT, CS_n, and CKE. 9. Package implementations will meet specification if the Zpkg and package delay fall within the ranges shown, and the maximum Lpkg and Cpkg do not exceed the maximum values shown. 10. It is assumed that Lpkg can be approximated as Lpkg = ZO έ Td. 11. It is assumed that Cpkg can be approximated as Cpkg = Td/ZO. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 303 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM DRAM Package Electrical Specifications Table 135: Pad Input/Output Capacitance DDR4-1600, 1866, 2133 DDR4-2400, 2666 DDR4-2933 DDR4-3200 Symbol Min Max Min Max Min Max Min Max Unit Notes Input/output capacitance: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c CIO 0.55 1.4 0.55 1.15 0.55 1.00 0.55 1.00 pF 1, 2, 3 Input capacitance: CK_t and CK_c CCK 0.2 0.8 0.2 0.7 0.2 0.7 0.15 0.7 pF 2, 3 Input capacitance delta: CK_t and CK_c CDCK - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 6 Input/output capacitance delta: DQS_t and DQS_c CDDQS - 0.05 - 0.05 - 0.05 - 0.05 pF 2, 3, 5 Input capacitance: CTRL, ADD, CMD input-only pins CI 0.2 0.8 0.2 0.7 0.2 0.6 0.15 0.55 pF 2, 3, 4 Input capacitance delta: All CTRL input-only pins CDI_CTRL n 0.1 n 0.1 n 0.1 n 0.1 pF 2, 3, 8, 9 Input capacitance delta: All ADD/CMD input-only pins CDI_AD- n 0.1 n 0.1 n 0.1 n 0.1 pF 1, 2, 10, 11 Parameter D_CMD Input/output capacitance delta: DQ, DM, DQS_t, DQS_c, TDQS_t, TDQS_c CDIO n 0.1 n 0.1 n 0.1 n 0.1 pF 1, 2, 3, 4 Input/output capacitance: ALERT pin CALERT 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 pF 2, 3 Input/output capacitance: ZQ pin CZQ n 2.3 n 2.3 n 2.3 n 2.3 pF 2, 3, 12 Input/output capacitance: TEN pin CTEN 0.2 2.3 0.2 2.3 0.2 2.3 0.15 2.3 pF 2, 3, 13 Notes: 1. Although the DM, TDQS_t, and TDQS_c pins have different functions, the loading matches DQ and DQS. 2. This parameter is not subject to a production test; it is verified by design and characterization and are provided for reference; system signal simulations should not use these values but use the Micron package model. The capacITANCEIFANDWHENISMEASUREDACCORDINGTOTHE*%0SPECIFICATIONh0ROCEDUREFOR-EASURING)NPUT#APACITANCE5SINGA6ECTOR.ETWORK!NALYZER6.! vWITH6DD, VDDQ, VSS, and VSSQ applied and all other pins floating (except the pin under test, CKE, RESET_n and ODT, as necessary). VDD = VDDQ = 1.2V, VBIAS = VDD/2 and on-die termination off. Measured data is rounded using industry standard half-rounded up methodology to the nearest hundredth of the MSB. 3. This parameter applies to monolithic die, obtained by de-embedding the package L and C parasitics. 4. CDIO = CIO(DQ, DM) - 0.5 έ (CIO(DQS_t) + CIO(DQS_c)). 5. Absolute value of CIO (DQS_t), CIO (DQS_c) 6. Absolute value of CCK_t, CCK_c 7. CI applies to ODT, CS_n, CKE, A[17:0], BA[1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n. 8. CDI_CTRL applies to ODT, CS_n, and CKE. 9. CDI_CTRL = CI(CTRL) - 0.5 έ (CI(CLK_t) + CI(CLK_c)). 10. CDI_ADD_CMD applies to A[17:0], BA1:0], BG[1:0], RAS_n, CAS_n, ACT_n, PAR and WE_n. 11. CDI_ADD_CMD = CI(ADD_CMD) - 0.5 έ (CI(CLK_t) + CI(CLK_c)). 12. Maximum external load capacitance on ZQ pin: 5pF. 13. Only applicable if TEN pin does not have an internal pull-up. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 304 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Thermal Characteristics Thermal Characteristics Table 136: Thermal Characteristics Parameter/Condition Value Units Symbol Notes Operating case temperature: Commercial 0 to +85 ιC TC 1, 2, 3 0 to +95 ιC TC 1, 2, 3, 4 Operating case temperature: Industrial nTO ιC TC 1, 2, 3 nTO ιC TC 1, 2, 3, 4 Operating case temperature: Automotive nTO ιC TC 1, 2, 3 nTO ιC TC 1, 2, 3, 4 Junction-to-case (TOP) 3.1 ιC/W ȣJC 5 Junction-to-board 10.6 ιC/W ȣJB Junction-to-case (TOP) 3.0 ιC/W ȣJC Junction-to-board 9.9 ιC/W ȣJB Junction-to-case (TOP) 3.5 ιC/W ȣJC Junction-to-board 21 ιC/W ȣJB Junction-to-case (TOP) 4.1 ιC/W ȣJC Junction-to-board 16.2 ιC/W ȣJB Junction-to-case (TOP) 3.2 ιC/W ȣJC Junction-to-board 20.2 ιC/W ȣJB Junction-to-case (TOP) TBD ιC/W ȣJC Junction-to-board TBD ιC/W ȣJB Junction-to-case (TOP) 4.9 ιC/W ȣJC Junction-to-board 14.2 ιC/W ȣJB Junction-to-case (TOP) 4.8 ιC/W ȣJC Junction-to-board 15.2 ιC/W ȣJB Junction-to-case (TOP) 2.8 ιC/W ȣJC Junction-to-board 13.1 ιC/W ȣJB Junction-to-case (TOP) N/A ιC/W ȣJC Junction-to-board N/A ιC/W ȣJB Junction-to-case (TOP) 4.4 ιC/W ȣJC Junction-to-board 13.2 ιC/W ȣJB Junction-to-case (TOP) 3.4 ιC/W ȣJC Junction-to-board 14.7 ιC/W ȣJB Junction-to-case (TOP) 6.0 ιC/W ȣJC Junction-to-board 17.9 ιC/W ȣJB Junction-to-case (TOP) 5.9 ιC/W ȣJC Junction-to-board 17.4 ιC/W ȣJB 78-ball h0-v REV A 96-ball h(!v 78-ball h7%v REV B  BALLh*9v 78-ball h7%v REV D  BALLh,9v  BALLh3!v REV E  BALLh,9v 78-ball h7%v REV G N/A  BALLh3!v REV H  BALLh,9v  BALLh3!v REV J  BALLh4"v CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 305 5 5 5 5 5 5 5 5 5 5 5 5 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS Table 136: Thermal Characteristics (Continued) Parameter/Condition 78-ball "SA" REV R 96-ball "TB" Value Units Symbol Notes Junction-to-case (TOP) 8.2 ιC/W ȣJC 5 Junction-to-board 19.8 ιC/W ȣJB Junction-to-case (TOP) 8.1 ιC/W ȣJC Junction-to-board 19.2 ιC/W ȣJB 5 Notes: 1. MAX operating case temperature. TCis measured in the center of the package. 2. A thermal solution must be designed to ensure the DRAM device does not exceed the maximum TC during operation. 3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation. 4. If TC exceeds 85ιC, the DRAM must be refreshed externally at 2x refresh, which is a 3.9ρs interval refresh rate. 5. The thermal resistance data is based off of a typical number. Figure 245: Thermal Measurement Point TC test point (L/2) L (W/2) W #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS IDD, IPP, and IDDQ Measurement Conditions IDD, IPP, and IDDQ measurement conditions, such as test load and patterns, are defined in this section. s IDD currents (IDD0, IDD1, IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5R, IDD6N, IDD6E, IDD6R, IDD6A, IDD7, DD8 and IDD9) are measured as time-averaged currents with all VDD balls of the device under test grouped together. s IPP currents are IPP3N for standby cases (IDD2N, IDD2NT, IDD2P, IDD2Q, IDD3N, IDD3P, IDD8), IPP0 for active cases (IDD0,IDD1, IDD4R, IDD4W), IPP5R for the distributed refresh case (IDD5R), IPP6x for self refresh cases (IDD6N, IDD6E, IDD6R, IDD6A), IPP7 for the operating bank interleave read case (IDD7) and IPP9 for the MBIST-PPR operation case. These have the same definitions as the IDD currents referenced but are measured on the VPP supply. s IDDQ currents are measured as time-averaged currents with VDDQ balls of the device under test grouped together. Micron does not specify IDDQ currents. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 306 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS s IPP and IDDQ currents are not included in IDD currents, IDD and IDDQ currents are not included in IPP currents, and IDD and IPP currents are not included in IDDQ currents. NOTE: IDDQ values cannot be directly used to calculate the I/O power of the device. They can be used to support correlation of simulated I/O power to actual I/O power. In DRAM module application, IDDQ cannot be measured separately because VDD and VDDQ are using a merged-power layer in the module PCB. The following definitions apply for IDD, IPP and IDDQ measurements. s hvANDh,/7vAREDEFINEDAS6IN ζVIL(AC)max s hvANDh()'(vAREDEFINEDAS6IN ηVIH(AC)min s h-IDLEVELvISDEFINEDASINPUTS6REF = VDD/2 s Timings used for IDD, IPP and IDDQ measurement-loop patterns are provided in the Current Test Definition and Patterns section. s Basic IDD, IPP, and IDDQ measurement conditions are described in the Current Test Definition and Patterns section. s Detailed IDD, IPP, and IDDQ measurement-loop patterns are described in the Current Test Definition and Patterns section. s Current measurements are done after properly initializing the device. This includes, but is not limited to, setting: RON = RZQ/7 (34 ohm in MR1); Qoff = 0B (output buffer enabled in MR1); RTT(NOM) = RZQ/6 (40 ohm in MR1); RTT(WR) = RZQ/2 (120 ohm in MR2); RTT(Park) = disabled; TDQS feature disabled in MR1; CRC disabled in MR2; CA parity feature disabled in MR3; Gear-down mode disabled in MR3; Read/Write DBI disabled in MR5; DM disabled in MR5 s Define D = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, LOW, LOW, LOW}; apply BG/BA changes when directed. s Define D_n = {CS_n, RAS_n, CAS_n, WE_n}: = {HIGH, HIGH, HIGH, HIGH}; apply invert of BG/BA changes when directed above. NOTE: The measurement-loop patterns must be executed at least once before actual current measurements can be taken, with the exception of IDD9 which may be measured any time after MBIST-PPR entry. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 307 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS Figure 246: Measurement Setup and Test Load for IDDx, IPPx, and IDDQx IDD VDD RESET_n CK_t/CK_c IPP IDDQ VPP DDR4 SDRAM CKE CS_n C ACT_n, RAS_n, CAS_n, WE_n VDDQ DQS_t, DQS_c DQ DM_n A, BG, BA ODT ZQ V VSSQ SS Figure 247: Correlation: Simulated Channel I/O Power to Actual Channel I/O Power Applic ation-s pe c ific memory c ha nne l env ironmen t C hanne l I/O pow er simulation I DD Q tes t loa d I DD Q simulation IDD Q meas ure ment C or relation C orre c tion C hanne l I/O pow er n umber Note: 1. Supported by IDDQ measurement. IDD Definitions Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions Symbol Description IDD0 Operating One Bank Active-Precharge Current (AL = 0) CKE: HIGH; External clock: On; tCK, nRC, nRAS, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between ACT and PRE; Command, address, bank group address, bank address inputs: partially toggling according to the next table; Data I/O: VDDQ; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the IDD0 Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD0 Measurement-Loop Pattern table CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 308 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions Symbol Description IPP0 Operating One Bank Active-Precharge IPP Current (AL = 0) Same conditions as IDD0 above IDD1 Operating One Bank Active-Read-Precharge Current (AL = 0) CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, CL: see the previous table; BL: 8;,, 5 AL: 0; CS_n: HIGH between ACT, RD, and PRE; Command, address, bank group address, bank address inputs, Data I/O: partially toggling according to the IDD1 Measurement-Loop Pattern table; DM_n: stable at 0; Bank activity: cycling with one bank active at a time: 0, 0, 1, 1, 2, 2, ... (see the following table); Output buffer and RTT: enabled in mode registers;2 ODT Signal: stable at 0; Pattern details: see the IDD1 Measurement-Loop Pattern table IDD2N Precharge Standby Current (AL = 0) CKE: HIGH; External clock: On; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address Inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-Loop Pattern table IDD2NT Precharge Standby ODT Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank gropup address, bank address inputs: partially toggling according to the IDD2NT Measurement-Loop Pattern table; Data I/O: VSSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: enabled in mode registers;2 ODT signal: toggling according to the IDD2NT Measurement-Loop Pattern table; Pattern details: see the IDD2NT Measurement-Loop Pattern table IDD2P Precharge Power-Down Current CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD2Q Precharge Quiet Standby Current CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD3N Active Standby Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: partially toggling according to the IDD2N and IDD3N Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD2N and IDD3N Measurement-Loop Pattern table IPP3N Active Standby IPP3N Current (AL = 0) Same conditions as IDD3N above IDD3P Active Power-Down Current (AL = 0) CKE: LOW; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 309 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions Symbol Description IDD4R Operating Burst Read Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;, 5 AL: 0; CS_n: HIGH between RD; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4R Measurement-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the next one according to the IDD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the IDD4R Measurement-Loop Pattern table); Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD4R Measurement-Loop Pattern table IDD4W Operating Burst Write Current (AL = 0) CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between WR; Command, address, bank group address, bank address inputs: partially toggling according to the IDD4W Measurement-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the next one according to the IDD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see IDD4W Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see the IDD4W Measurement-Loop Pattern table IDD5R Distributed Refresh Current (1X REF) CKE: HIGH; External clock: on; tCK, CL, nREFI: see the previous table; BL: 8;1 AL: 0; CS_n: HIGH between REF; Command, address, bank group address, bank address inputs: partially toggling according to the IDD5R Measurement-Loop Pattern table; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: REF command every nREFI (see the IDD5R Measurement-Loop Pattern table); Output buffer and RTT: enabled in mode registers2; ODT signal: stable at 0; Pattern details: see the IDD5R Measurement-Loop Pattern table IPP5R Distributed Refresh Current (1X REF) Same conditions as IDD5R above IDD6N Self Refresh Current: Normal Temperature Range TCnιC; Auto self refresh (ASR): disabled;3 Self refresh temperature range (SRT): normal;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the table above; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel IDD6E Self Refresh Current: Extended Temperature Range 4 TCnιC; Auto self refresh (ASR): disabled4; Self refresh temperature range (SRT): extended;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, group bank address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel IPP6x Self Refresh IPP Current Same conditions as IDD6E above IDD6R Self Refresh Current: Reduced Temperature Range TCnιC; Auto self refresh (ASR): disabled; Self refresh temperature range (SRT): reduced;4 CKE: LOW; External clock: off; CK_t and CK_c: LOW; CL: see the previous table; BL: 8;1 AL: 0; CS_n, command, address, bank group address, bank address, data I/O: VDDQ; DM_n: stable at 1; Bank activity: EXTENDED TEMPERATURE SELF REFRESH operation; Output buffer and RTT: enabled in mode registers;2 ODT signal: midlevel CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 310 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn-EASUREMENT#ONDITIONS Table 137: Basic IDD, IPP, and IDDQ Measurement Conditions Symbol Description IDD7 Operating Bank Interleave Read Current CKE: HIGH; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see the previous table; BL: 8;, 5 AL: CL 1; CS_n: HIGH between ACT and RDA; Command, address, group bank adress, bank address inputs: partially toggling according to the IDD7 Measurement-Loop Pattern table; Data I/O: read data bursts with different data between one burst and the next one according to the IDD7 Measurement-Loop Pattern table; DM: stable at 1; Bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see the IDD7 Measurement-Loop Pattern table; Output buffer and RTT: enabled in mode registers;2 ODT signal: stable at 0; Pattern details: see the IDD7 Measurement-Loop Pattern table IPP7 Operating Bank Interleave Read IPP Current Same conditions as IDD7 above IDD8 Maximum Power Down Current Place DRAM in MPSM then CKE: HIGH; External clock: on; tCK, CL: see the previous table; BL: 8;1 AL: 0; CS_n: stable at 1; Command, address, bank group address, bank address inputs: stable at 0; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IDD9 MBIST-PPR Current 7 Device in MBIST-PPR mode; External clock: on; CS_n: stable at 1 after MBIST-PPR entry; Command, address, bank group address, bank address inputs: stable at 1; Data I/O: VDDQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer and RTT: Enabled in mode registers;2 ODT signal: stable at 0 IPP9 MBIST-PPR IPP Current Same condition with IDD9 above Notes: 1. Burst length: BL8 fixed by MRS: set MR0[1:0] 00. 2. Output buffer enable: set MR1[12] 0 (output buffer enabled); set MR1[2:1] 00 (RON = RZQ/7); RTT(NOM) enable: set MR1[10:8] 011 (RZQ/6); RTT(WR) enable: set MR2[11:9] 001 (RZQ/2), and RTT(Park) enable: set MR5[8:6] 000 (disabled). 3. Auto self refresh (ASR): set MR2[6] 0 to disable or MR2[6] 1 to enable feature. 4. Self refresh temperature range (SRT): set MR2[7] 0 for normal or MR2[7] 1 for extended temperature range. 5. READ burst type: Nibble sequential, set MR0[3] 0. 6. In the dual-rank DDP case, note the following IDD measurement considerations: s For all IDD measurements except IDD6, the unselected rank should be in an IDD2P condition. s For all IPP measurements except IPP6, the unselected rank should be in an IDD3N condition. s For all IDD6/IPP6 measurements, both ranks should be in the same IDD6 condition. 7. When measuring IDD9/IPP9 after entering MBIST-PPR mode and ALERT_N driving LOW, there is a chance that the DRAM may perform an internal hPPR if fails are found after internal self-test is completed and before ALERT_N fires HIGH. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 311 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Current Test Definitions and Patterns Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_t, CK_c Table 138: IDD0 and IPP0 Measurement-Loop Pattern1 0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 3, 4 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n ... Static High Toggling nRAS Notes: 1. 2. 3. 4. Data3 Repeat pattern 1...4 until nRAS - 1; truncate if necessary PRE 0 1 0 1 0 0 0 0 0 0 0 0 0 0 ... Repeat pattern 1...4 until nRC - 1; truncate if necessary 1 1 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 2 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 5 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 6 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 7 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 8 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 9 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 10 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 11 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 12 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 13 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 14 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 15 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4 n DQS_t, DQS_c are VDDQ. BG1 is a "Don't Care" for x16 devices. DQ signals are VDDQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 312 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_c, CK_t, Table 139: IDD1-EASUREMENTn,OOP0ATTERN1 0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 n 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 3, 4 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n ... nRCD - AL Repeat pattern 1...4 until nRCD - AL - 1; truncate if necessary RD ... nRAS PRE Static High 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 Repeat pattern 1...4 until nRC - 1; truncate if necessary D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF 1 έ nRC + 0 ACT 0 0 0 1 1 0 1 1 0 0 0 0 0 0 n 1 έ nRC + 1, 2 D, D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 1 έ nRC + 3, 4 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n Repeat pattern nRC + 1...4 until 1 έ nRC + nRAS - 1; truncate if necessary ... Toggling 0 Repeat pattern 1...4 until nRAS - 1; truncate if necessary ... 1 Data3 1έ nRC+nRCD AL RD ... 1 έ nRC + nRAS ... 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 Repeat pattern 1...4 until nRAS - 1; truncate if necessary PRE 0 1 0 1 0 0 1 1 0 0 0 0 Repeat pattern nRC + 1...4 until 2 έ nRC - 1; truncate if necessary 2 2 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 5 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 6 έ nRC Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 7 έ nRC Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 9 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 10 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 11 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 12 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 13 έ nRC Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 313 D0 = FF, D1 = 00, D2 = 00, D3 = FF, D4 = 00, D5 = FF, D5 = FF, D7 = 00 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Notes: 1. 2. 3. 4. A[17,13,11]] WE_n/A14 CAS_n/A15 RAS_n/A16 15 16 έ nRC Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4 A[9:7] BA[1:0] ODT A[2:0] Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 A[6:3] 15 έ nRC A[10]/AP 14 A12/BC_n Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4 BG[1:0]2 14 έ nRC ACT_n 13 CS_n Cycle Number Command Sub-Loop Static High CKE Toggling CK_c, CK_t, Table 139: IDD1-EASUREMENTn,OOP0ATTERN1 Data3 DQS_t, DQS_c are VDDQ when not toggling. BG1 is a "Don't Care" for x16 devices. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command. For x4 and x8 only. Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE Static High Toggling CK_c, CK_t, Table 140: IDD2N, IDD3N, and IPP3P-EASUREMENTn,OOP0ATTERN1 0 0 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 2 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n 3 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n 1 n Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 n Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 n Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 n Repeat sub-loop 0, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 n Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 n Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 n Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 n Repeat sub-loop 0, use BG[1:0] = 3, use BA[1:0] = 0 instead4 Data3 Notes: 1. DQS_t, DQS_c are VDDQ. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 314 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS 2. BG1 is a "Don't Care" for x16 devices. 3. DQ signals are VDDQ. 4. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 315 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Notes: 1. 2. 3. 4. Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE Static High Toggling CK_c, CK_t, Table 141: IDD2NT-EASUREMENTn,OOP0ATTERN1 0 0 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 2 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n 3 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n Data3 1 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 1 instead 2 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 n Repeat sub-loop 0 with ODT = 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 n Repeat sub-loop 0 with ODT = 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4 DQS_t, DQS_c are VSSQ. BG1 is a "Don't Care" for x16 devices. DQ signals are VSSQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 316 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_c, CK_t, Table 142: IDD4R-EASUREMENTn,OOP0ATTERN1 0 0 RD 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2, 3 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 4 RD 0 1 1 0 1 0 1 1 0 0 0 7 F 0 5 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 6, 7 D_n, D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 Static High Toggling 1 Notes: 1. 2. 3. 4. 2 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4 Data3 D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF D0 = FF, D1 = 00 D2 = 00, D3 = FF D4 = 00, D5 = FF D5 = FF, D7 = 00 DQS_t, DQS_c are VDDQ when not toggling. BG1 is a "Don't Care" for x16 devices. Burst sequence driven on each DQ signal by a READ command. Outside burst operation, DQ signals are VDDQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 317 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_c, CK_t, Table 143: IDD4W-EASUREMENTn,OOP0ATTERN1 0 0 WR 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 2, 3 D_n, D_n 1 1 1 1 0 1 3 3 0 0 0 7 F 0 4 WR 0 1 1 0 0 1 1 1 0 0 0 7 F 0 5 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 6, 7 D_n, D_n 1 1 1 1 0 1 3 3 0 0 0 7 F 0 Static High Toggling 1 Notes: 1. 2. 3. 4. Data3 D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D5 = 00, D7 = FF 2 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4 D0 = FF, D1 = 00 D2 = 00, D3 = FF D4 = 00, D5 = FF D5 = FF, D7 = 00 DQS_t, DQS_c are VDDQ when not toggling. BG1 is a "Don't Care" for x16 devices. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation, DQ signals are VDDQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 318 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]3 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_c, CK_t, Table 144: IDD4Wc-EASUREMENTn,OOP0ATTERN1 0 0 WR 0 1 1 0 0 1 0 0 0 0 0 0 0 0 1, 2 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 3, 4 D_n, D_n 1 1 1 1 0 1 3 3 0 0 0 7 F 0 5 WR 0 1 1 0 0 1 1 1 0 0 0 7 F 0 6, 7 D, D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 8, 9 D_n, D_n 1 1 1 1 0 1 3 3 0 0 0 7 F 0 Static High Toggling 1 Notes: 1. 2. 3. 4. 5. Data4 D0 = 00, D1 = FF, D2 = FF, D3 = 00, D4 = FF, D5 = 00, D8 = CRC D0 = FF, D1 = 00, D2 = 00, D3 = FF, D4 = 00, D5 = FF, D5 = FF, D7 = 00 D8 = CRC 2 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 5 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 6 n Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 7 n Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 8 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead4 9 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead4 10 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead4 11 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead4 12 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead4 13 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead4 14 n Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead4 15 n Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead4 Pattern provided for reference only. DQS_t, DQS_c are VDDQ when not toggling. BG1 is a "Don't Care" for x16 devices. Burst sequence driven on each DQ signal by WRITE command. Outside burst operation, DQ signals are VDDQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 319 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE 0 0 REF 0 1 0 0 1 0 0 0 0 0 0 0 0 0 n 1 1 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 3 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n 4 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n Static High Toggling CK_c, CK_t, Table 145: IDD5R-EASUREMENTn,OOP0ATTERN1 2 Notes: 1. 2. 3. 4. n Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 1 instead n Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 2 instead n Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 3 instead n Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 1 instead n Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 2 instead n Repeat pattern 1...4, use BG[1:0] = 0, use BA[1:0] = 3 instead n Repeat pattern 1...4, use BG[1:0] = 1, use BA[1:0] = 0 instead n Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 0 instead4 n Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 1 instead4 n Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 2 instead4 n Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 3 instead4 n Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 1 instead4 n Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 2 instead4 n Repeat pattern 1...4, use BG[1:0] = 2, use BA[1:0] = 3 instead4 n Repeat pattern 1...4, use BG[1:0] = 3, use BA[1:0] = 0 instead4 65...nREFI - 1 Repeat sub-loop 1; truncate if necessary Data3 DQS_t, DQS_c are VDDQ. BG1 is a "Don't Care" for x16 devices. DQ signals are VDDQ. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 320 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS Sub-Loop Cycle Number Command CS_n ACT_n RAS_n/A16 CAS_n/A15 WE_n/A14 ODT BG[1:0]2 BA[1:0] A12/BC_n A[17,13,11]] A[10]/AP A[9:7] A[6:3] A[2:0] CKE CK_t, CK_c Table 146: IDD7-EASUREMENTn,OOP0ATTERN1 0 0 ACT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 RDA 0 1 1 0 1 0 0 0 0 0 1 0 0 0 2 D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 n 3 D_n 1 1 1 1 1 0 3 3 0 0 0 7 F 0 n ... Static High Toggling 1 Notes: 1. 2. 3. 4. Data3 n Repeat pattern 2...3 until nRRD - 1, if nRRD > 4. Truncate if necessary nRRD ACT 0 0 0 0 0 0 1 1 0 0 0 0 0 0 nRRD+1 RDA 0 1 1 0 1 0 1 1 0 0 1 0 0 0 n ... Repeat pattern 2...3 until 2 έ nRRD - 1, if nRRD > 4. Truncate if necessary 2 2 έ nRRD Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 2 instead 3 3 έ nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 3 instead 4 4 έ nRRD Repeat pattern 2...3 until nFAW - 1, if nFAW > 4 έ nRRD. Truncate if necessary 5 nFAW Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 1 instead 6 nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 2 instead 7 nFAW + 2 έ nRRD Repeat sub-loop 0, use BG[1:0] = 0, use BA[1:0] = 3 instead 8 nFAW + 3 έ nRRD Repeat sub-loop 1, use BG[1:0] = 1, use BA[1:0] = 0 instead 9 nFAW + 4 έ nRRD Repeat sub-loop 4 10 2 έ nFAW Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 0 instead 11 2 έ nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 1 instead 12 2 έ nFAW + 2 έ nRRD Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 2 instead 13 2 έ nFAW + 3 έ nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 3 instead 14 2 έ nFAW + 4 έ nRRD Repeat sub-loop 4 15 3 έ nFAW Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 1 instead 16 3 έ nFAW + nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 2 instead 17 3 έ nFAW + 2 έ nRRD Repeat sub-loop 0, use BG[1:0] = 2, use BA[1:0] = 3 instead 18 3 έ nFAW + 3 έ nRRD Repeat sub-loop 1, use BG[1:0] = 3, use BA[1:0] = 0 instead 19 3 έ nFAW + 4 έ nRRD Repeat sub-loop 4 20 4 έ nFAW Repeat pattern 2...3 until nRC - 1, if nRC > 4 έ nFAW. Truncate if necessary DQS_t, DQS_c are VDDQ. BG1 is a "Don't Care" for x16 devices. DQ signals are VDDQ except when burst sequence drives each DQ signal by a READ command. For x4 and x8 only. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 321 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn0ATTERNSAND4EST#ONDITIONS IDD Specifications 0.682 24-24-24 22-22-22 20-20-20 22-22-22 20-20-20 0.75 21-21-21 18-18-18 0.833 20-20-20 16-16-16 0.937 19-19-19 14-14-14 1.071 18-18-18 12-12-12 1.25 tCK 17-17-17 DDR4-3200 16-16-16 DDR4-2933 15-15-15 DDR4-2666 14-14-14 DDR4-2400 13-13-13 DDR4-2133 12-12-12 DDR4-1866 11-11-11 Symbol DDR4-1600 10-10-10 Table 147: Timings used for IDD, IPP, and IDDQ-EASUREMENTn,OOP0ATTERNS 0.625 Unit ns CL 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 20 21 22 20 22 24 CK CWL 9 11 11 10 12 12 11 14 14 16 16 16 18 18 18 14 18 18 16 20 20 CK nRCD 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 19 20 21 20 22 24 CK nRC 38 39 40 44 45 46 50 51 52 55 56 57 61 62 63 66 67 68 72 74 76 CK nRP 10 11 12 12 13 14 14 15 16 16 17 18 18 19 20 19 20 21 20 22 24 CK nRAS 28 32 36 39 43 47 52 CK nFAW x41 16 16 16 16 16 16 16 CK x8 20 22 23 26 28 31 34 CK x1 6 28 28 32 36 40 44 48 CK x4 4 4 4 4 4 4 4 CK x8 4 4 4 4 4 4 4 CK x1 6 5 6 6 7 8 8 9 CK x4 5 5 6 6 7 8 8 CK x8 5 5 6 6 7 8 8 CK x1 6 6 6 7 8 9 10 11 CK nCCD_S 4 4 4 4 4 4 4 CK nCCD_L 5 5 6 6 7 8 8 CK nWTR_S 2 3 3 3 4 4 4 CK nWTR_L 6 7 8 9 10 11 12 CK nREFI 6,240 7,283 8,325 9,364 10,400 11,437 12,480 CK nRFC 2Gb 128 150 171 193 214 235 256 CK nRFC 4Gb 208 243 278 313 347 382 416 CK nRFC 8Gb 280 327 374 421 467 514 560 CK nRFC 16Gb 280 327 374 421 467 514 560 CK nRRD_ S nRRD_ L Notes: 1. 1KB based x4 use same numbers of clocks for nFAW as the x8. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 322 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS #URRENT3PECIFICATIONSn,IMITS Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. A (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 Unit IDD0: One bank ACTIVATE-to-PRECHARGE current x4, x8 55 60 65 TBD mA x16 85 90 95 TBD mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 TBD mA x16 4 4 4 TBD mA IDD1: One bank ACTIVATE-to-READ-toPRECHARGE current x4, x8 70 75 80 TBD mA x16 105 110 115 TBD mA IDD2N: Precharge standby current x4, x8 45 50 55 TBD mA x16 65 70 75 TBD mA x4, x8 55 60 65 TBD mA x16 75 80 90 TBD mA x4, x8 25 30 35 TBD mA x16 45 50 55 TBD mA x4, x8 45 45 50 TBD mA x16 65 65 70 TBD mA x4, x8 55 55 60 TBD mA x16 75 75 85 TBD mA ALL 3 3 3 TBD mA x4, x8 35 40 40 TBD mA x16 55 60 65 TBD mA x4 135 145 160 TBD mA x8 150 150 175 TBD mA x16 210 230 250 TBD mA x4 135 145 160 TBD mA x8 150 160 175 TBD mA x16 210 230 250 TBD mA x4, x8 64 64 68 TBD mA x16 84 84 94 TBD mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 TBD mA IDD6N3ELFREFRESHCURRENTnιC 1 ALL 30 30 30 TBD mA x4, x8 35 35 35 TBD mA x16 50 50 50 IDD6R3ELFREFRESHCURRENTn#3, 4 ALL 25 25 25 TBD mA IDD6A: Auto self refresh current (25ιC)4 ALL 20 20 20 TBD mA IDD2NT: Precharge standby ODT current IDD2P: Precharge power-down current IDD2Q: Precharge quiet standby current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current IDD5R: Distributed refresh current (1X REF) IDD6E3ELFREFRESHCURRENTnιC 2, 4 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 323 mA Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 148: IDD, IPP, and IDDQ Current Limits; Die Rev. A (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 Unit IDD6A: Auto self refresh current (45ιC)4 ALL 25 25 25 TBD mA IDD6A: Auto self refresh current (75ιC)4 x4, x8 35 35 35 TBD mA x16 50 50 50 TBD mA ALL 5 5 5 x4 250 255 265 TBD mA x8 200 205 215 TBD mA x16 265 270 280 TBD mA x4 25 25 25 TBD mA x8 15 15 15 TBD x16 20 20 20 TBD mA ALL 20 20 20 TBD mA IPP6x: Auto self refresh IPP current; mA nιC25 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately 0%. 6. When additive latency is enabled for IDD1, current changes by approximately +5%(x4/x8), +4%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately +0%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%(x4/x8), +10%(x16). 18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16). 19. When 2X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 20. When 4X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0ιC ζ TC ζ 85ιC: When TC < 0ιC: IDD2P, and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by 4%; IDD6, IDD6ET, and IDD7 must be derated by 11%. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 324 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS When TC > 85ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by 3%; IDD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test. 25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 149: IDD, IPP, and IDDQ Current Limits; Die Rev. B (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 40 43 46 49 52 mA x8 45 48 51 54 57 mA x16 75 80 85 90 95 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 52 55 58 61 64 mA x8 57 60 63 66 69 mA x16 95 100 105 110 115 mA IDD2N: Precharge standby current ALL 33 34 35 36 37 mA IDD2NT: Precharge standby ODT current x4, x8 45 50 50 55 60 mA x16 67 75 75 78 81 mA IDD2P: Precharge power-down current ALL 25 25 25 25 25 mA IDD2Q: Precharge quiet standby current ALL 30 30 30 30 30 mA x4 35 38 41 44 47 mA x8 40 43 46 49 52 mA x16 44 47 50 53 56 mA ALL 3 3 3 3 3 mA x4 30 32 34 36 38 mA x8 35 37 39 41 43 mA x16 39 41 43 45 47 mA x4 100 110 121 132 143 mA x8 125 135 146 157 168 mA x16 225 243 263 283 302 mA x4 95 103 112 121 130 mA x8 115 123 132 141 150 mA x16 213 228 244 261 278 mA IDD5R: Distributed refresh current (1X REF) x4, x8 50 53 56 59 62 mA x16 56 59 61 64 67 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD0: One bank ACTIVATE-to-PRECHARGE current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 325 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 149: IDD, IPP, and IDDQ Current Limits; Die Rev. B (0ι ζ TC ζ 85ιC) Symbol IDD6N: Self refresh current; nιC DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit ALL 30 30 30 30 30 mA ALL 35 35 35 35 35 mA ALL 20 20 20 20 20 mA ALL 8.6 8.6 8.6 8.6 8.6 mA ALL 20 20 20 20 20 mA ALL 30 30 30 30 30 mA ALL 5 5 5 5 5 mA x4 175 185 200 215 230 mA x8 170 175 180 185 190 mA x16 239 249 259 269 279 mA x4 16 17 18 19 20 mA x8 15 15 15 15 15 mA x16 20 20 20 20 20 mA ALL 25 25 25 25 25 mA 1 IDD6E: Self refresh current; nιC Width 2, 4 IDD6R: Self refresh current; n#3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IPP6x: Auto self refresh IPP CURRENTnιC25 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately 0%. 6. When additive latency is enabled for IDD1, current changes by approximately +5%(x4/x8), +4%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately 0%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%(x4/x8), +10%(x16). CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 326 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16). 19. When 2X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 20. When 4X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0ιC ζ TC ζ 85ιC: When TC < 0ιC: IDD2P, and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by 4%; IDD6, IDD6ET, and IDD7 must be derated by 11%. When TC > 85ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by 3%; IDD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test. 25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 150: IDD, IPP, and IDDQ Current Limits; Die Rev. D (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 40 43 46 49 52 mA x8 45 48 51 54 57 mA x16 75 80 85 90 95 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 52 55 58 61 64 mA x8 57 60 63 66 69 mA x16 95 100 105 110 115 mA IDD2N: Precharge standby current ALL 33 34 35 36 37 mA IDD2NT: Precharge standby ODT current x4, x8 45 50 50 55 60 mA x16 67 75 75 78 81 mA IDD2P: Precharge power-down current ALL 25 25 25 25 25 mA IDD2Q: Precharge quiet standby current ALL 30 30 30 30 30 mA x4 40 43 46 49 52 mA x8 45 48 51 54 56 mA x16 49 52 55 58 61 mA ALL 3 3 3 3 3 mA x4 30 32 34 36 38 mA x8 35 37 39 41 43 mA x16 39 41 43 45 47 mA IDD0: One bank ACTIVATE-to-PRECHARGE current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 327 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 150: IDD, IPP, and IDDQ Current Limits; Die Rev. D (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 100 110 121 132 143 mA x8 125 135 146 157 168 mA x16 225 243 263 283 302 mA x4 105 113 122 130 140 mA x8 125 132 142 150 160 mA x16 225 240 255 270 290 mA IDD5R: Distributed refresh current (1X REF) x4, x8 56 58 61 64 66 mA x16 61 64 67 69 72 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 31 31 31 31 31 mA ALL 36 36 36 36 36 mA ALL 21 21 21 21 21 mA ALL 8.6 8.6 8.6 8.6 8.6 mA ALL 21 21 21 21 21 mA ALL 31 31 31 31 31 mA ALL 5 5 5 5 5 mA x4 175 185 200 215 230 mA x8 170 175 180 185 190 mA x16 239 249 259 269 279 mA x4 16 17 18 19 20 mA x8 15 15 15 15 15 mA x16 20 20 20 20 20 mA ALL 25 25 25 25 25 mA IDD4R: Burst read current IDD4W: Burst write current nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; n#3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IPP6x: Auto self refresh IPP CURRENTnιC25 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately 0%. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 328 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 6. When additive latency is enabled for IDD1, current changes by approximately +5%(x4/x8), +4%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately 0%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%(x4/x8), +10%(x16). 18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16). 19. When 2X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 20. When 4X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0ιC ζ TC ζ 85ιC: When TC < 0ιC: IDD2P, and IDD3P must be derated by +6%; IDD4R and IDD4W must be derated by +4%; IDD6, IDD6ET, and IDD7 must be derated by +11%. When TC > 85ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W must be derated by +3%; IDD2P must be derated by +40%; and IDD5R and IPP5R must be derated by +40%. These values are verified by design and characterization, and may not be subject to production test. 25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 151: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 37 39 41 43 45 mA x8 39 41 43 45 47 mA x16 46 48 50 52 54 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 50 52 54 56 58 mA x8 55 57 59 61 63 mA x16 72 74 76 78 80 mA IDD2N: Precharge standby current ALL 29 30 31 32 33 mA IDD2NT: Precharge standby ODT current x4, x8 36 38 40 42 44 mA x16 43 46 49 52 55 mA IDD2P: Precharge power-down current ALL 22 22 22 22 22 mA IDD2Q: Precharge quiet standby current ALL 26 26 26 26 26 mA IDD0: One bank ACTIVATE-to-PRECHARGE current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 329 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 151: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 34 36 38 40 42 mA x8 35 37 39 41 43 mA x16 36 38 40 42 44 mA ALL 3 3 3 3 3 mA x4 28 29 30 31 32 mA x8 29 30 31 32 33 mA x16 30 31 32 33 34 mA x4 110 120 131 142 153 mA x8 135 145 156 167 178 mA x16 235 253 273 293 312 mA x4 96 105 114 123 132 mA x8 114 123 132 141 150 mA x16 182 199 216 233 250 mA IDD5R: Distributed refresh current (1X REF) ALL 46 47 48 49 50 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 34 34 34 34 34 mA ALL 58 58 58 58 58 mA ALL 21 21 21 21 21 mA ALL 8.6 8.6 8.6 8.6 8.6 mA ALL 21 21 21 21 21 mA ALL 31 31 31 31 31 mA ALL 58 58 58 58 58 mA ALL 5 5 5 5 5 mA x4 175 185 200 215 230 mA x8 170 175 180 185 190 mA x16 234 243 252 261 270 mA IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; nιC 3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IDD6A: Auto self refresh current (95ιC)4 IPP6x: Auto self refresh IPP CURRENT nιC26 IDD7: Bank interleave read current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 330 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 151: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 85ιC) Symbol IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 14 14 14 14 14 mA x8 13 13 13 13 13 mA x16 18 18 18 18 18 mA ALL 18 18 18 18 18 mA Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation  nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation  nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation  nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1, current changes by approximately +8%(x4/x8), +7%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately +1%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +10%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4%. 14. When read DBI is enabled for IDD4R, current changes by approximately -14%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately +0%. 20. When 4X REF is enabled for IDD5R, current changes by approximately +0%. 21. When 2X REF is enabled for IPP5R, current changes by approximately +0%. 22. When 4X REF is enabled for IPP5R, current changes by approximately +0%. 23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 26. The IDD values must be derated (increased) when operating between 85ιC < TC ζ 95ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W must be derated by +3%; IDD2P must be derated by +10%; and IDD5R and IPP5R must be derated by +43%; All IPP currents except IPP6x and IPP5R must be derated by +0%. These values are verified by design and characterization, and may not be subject to production test. 27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 152: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 105ιC) Symbol IDD0: One bank ACTIVATE-to-PRECHARGE current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x8 43 45 47 49 51 mA x16 50 52 54 56 58 mA 331 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 152: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 105ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA x8 59 61 63 65 67 mA x16 77 79 81 83 85 mA IDD2N: Precharge standby current ALL 32 33 34 35 36 mA IDD2NT: Precharge standby ODT current x8 40 42 44 46 48 mA x16 47 49 53 56 59 mA IDD2P: Precharge power-down current ALL 26 26 26 26 26 mA IDD2Q: Precharge quiet standby current ALL 29 29 29 29 29 mA x8 39 41 43 45 47 mA x16 40 42 44 46 48 mA ALL 3 3 3 3 3 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current x8 33 34 35 36 37 mA x16 34 35 36 37 38 mA IDD4R: Burst read current x8 145 155 166 178 189 mA x16 247 265 292 306 326 mA x8 123 132 141 151 160 mA x16 193 210 228 245 263 mA IDD5R: Distributed refresh current (1X REF) ALL 96 97 98 99 100 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 34 34 34 34 34 mA ALL 95 95 95 95 95 mA ALL 21 21 21 21 21 mA ALL 8.6 8.6 8.6 8.6 8.6 mA ALL 21 21 21 21 21 mA ALL 31 31 31 31 31 mA IDD4W: Burst write current nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; nιC 3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 332 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 152: IDD, IPP, and IDDQ Current Limits; Die Rev. E (-40ι ζ TC ζ 105ιC) Symbol IDD6A: Auto self refresh current Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit ALL 95 95 95 95 95 mA ALL 6 6 6 6 6 mA x8 175 180 185 190 195 mA x16 239 248 257 266 275 mA x8 13 13 13 13 13 mA x16 18 18 18 18 18 mA ALL 20 20 20 20 20 mA (105ιC)4 IPP6x: Auto self refresh IPP CURRENT nιC26 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation  nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation  nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation  nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1, current changes by approximately +8%(x4/x8), +7%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately +1%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +10%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4%. 14. When read DBI is enabled for IDD4R, current changes by approximately -14%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately +0%. 20. When 4X REF is enabled for IDD5R, current changes by approximately +0%. 21. When 2X REF is enabled for IPP5R, current changes by approximately +0%. 22. When 4X REF is enabled for IPP5R, current changes by approximately +0%. 23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 333 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 26. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 153: IDD, IPP, and IDDQ Current Limits; Die Rev. G (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 40 43 46 49 52 mA x8 45 48 51 54 57 mA x16 75 80 85 90 95 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 52 55 58 61 64 mA x8 57 60 63 66 69 mA x16 95 100 105 110 115 mA IDD2N: Precharge standby current ALL 33 34 35 36 37 mA IDD2NT: Precharge standby ODT current x4, x8 45 50 50 55 60 mA x16 67 75 75 78 81 mA IDD2P: Precharge power-down current ALL 25 25 25 25 25 mA IDD2Q: Precharge quiet standby current ALL 30 30 30 30 30 mA x4 40 43 46 49 52 mA x8 45 48 51 54 56 mA x16 49 52 55 58 61 mA ALL 3 3 3 3 3 mA x4 30 32 34 36 38 mA x8 35 37 39 41 43 mA x16 39 41 43 45 47 mA x4 100 110 121 132 143 mA x8 125 135 146 157 168 mA x16 225 243 263 283 302 mA x4 100 108 117 126 135 mA x8 120 128 137 146 155 mA x16 218 233 249 266 283 mA IDD5R: Distributed refresh current (1X REF) x4, x8 56 58 61 64 66 mA x16 61 64 67 69 72 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 31 31 31 31 31 mA IDD0: One bank ACTIVATE-to-PRECHARGE current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current nιC 1 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 334 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 153: IDD, IPP, and IDDQ Current Limits; Die Rev. G (0ι ζ TC ζ 85ιC) Symbol IDD6E: Self refresh current; nιC Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit ALL 36 36 36 36 36 mA ALL 21 21 21 21 21 mA ALL 8.6 8.6 8.6 8.6 8.6 mA ALL 21 21 21 21 21 mA ALL 31 31 31 31 31 mA ALL 5 5 5 5 5 mA x4 175 185 200 215 230 mA x8 170 175 180 185 190 mA x16 239 249 259 269 279 mA x4 16 17 18 19 20 mA x8 15 15 15 15 15 mA x16 20 20 20 20 20 mA ALL 25 25 25 25 25 mA 2, 4 IDD6R: Self refresh current; n#3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IPP6x: Auto self refresh IPP CURRENTnιC25 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately 0%. 6. When additive latency is enabled for IDD1, current changes by approximately +5%(x4/x8), +4%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately 0%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%(x4/x8), +10%(x16). 18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16). 19. When 2X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 20. When 4X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 335 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0ιC ζ TC ζ 85ιC: When TC < 0ιC: IDD2P, and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by 4%; IDD6, IDD6ET, and IDD7 must be derated by 11%. When TC > 85ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by 3%; IDD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test. 25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 154: IDD, IPP, and IDDQ Current Limits; Die Rev. H (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 55 55 57 60 na mA x8 55 55 60 61 na mA x16 75 75 80 83 na mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 na mA x16 5 5 5 5 na mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 68 68 71 75 na mA x8 68 68 73 75 na mA x16 100 100 107 111 na mA IDD2N: Precharge standby current ALL 39 39 42 43 na mA IDD2NT: Precharge standby ODT current x4, x8 43 43 48 50 na mA x16 47 47 50 54 na mA IDD2P: Precharge power-down current ALL 27 27 27 27 na mA IDD2Q: Precharge quiet standby current ALL 34 34 36 36 na mA x4 46 47 49 52 na mA x8 46 47 49 52 na mA x16 46 47 50 53 na mA ALL 4.5 4.5 4.5 4.5 na mA x4 34 34 34 37 na mA x8 36 36 39 40 na mA x16 37 37 40 42 na mA x4 135 135 157 173 na mA x8 147 147 174 188 na mA x16 259 259 312 341 na mA IDD0: One bank ACTIVATE-to-PRECHARGE current IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 336 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 154: IDD, IPP, and IDDQ Current Limits; Die Rev. H (0ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 163 163 192 210 na mA x8 181 181 217 234 na mA x16 298 298 359 392 na mA x4 49 49 51 53 na mA x8 49 49 51 53 na mA x16 49 49 52 54 na mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5.5 5.5 5.5 5.5 na mA IDD6N: Self refresh current; ALL 36 36 36 36 na mA x4, x8 48 48 49 49 na mA x16 50 50 50 51 na mA ALL 26 26 26 26 na mA ALL 15 15 15 15 na mA ALL 26 26 26 26 na mA ALL 36 36 36 36 na mA ALL 5 5 5 5 na mA x4 278 278 388 369 na mA x8 228 228 240 244 na mA x16 311 311 321 331 na mA x4 21 21 26 28 na mA x8 16 16 16 16 na mA x16 22 22 22 22 na mA ALL 21 21 21 21 na mA IDD4W: Burst write current IDD5R: Distributed refresh current (1X REF) nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; n#3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IPP6x: Auto self refresh IPP CURRENTnιC25 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately 0%. 6. When additive latency is enabled for IDD1, current changes by approximately +5%(x4/x8), +4%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately 0%. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 337 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +7%. 12. When additive latency is enabled for IDD3N, current changes by approximately +1%. 13. When additive latency is enabled for IDD4R, current changes by approximately +5%. 14. When read DBI is enabled for IDD4R, current changes by approximately 0%. 15. When additive latency is enabled for IDD4W, current changes by approximately +3%(x4/x8), +4%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately +10%(x4/x8), +10%(x16). 18. When CA parity is enabled for IDD4W, current changes by approximately +12% (x8), +12% (x16). 19. When 2X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 20. When 4X REF is enabled for IDD5RCURRENTCHANGESBYAPPROXIMATELYn 21. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 22. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 23. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 24. The IDD values must be derated (increased) when operated outside of the range 0ιC ζ TC ζ 85ιC: When TC < 0ιC: IDD2P, and IDD3P must be derated by 6%; IDD4R and IDD4W must be derated by 4%; IDD6, IDD6ET, and IDD7 must be derated by 11%. When TC > 85ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5R must be derated by 3%; IDD2P must be derated by 40%. These values are verified by design and characterization, and may not be subject to production test. 25. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 155: IDD, IPP, and IDDQ Current Limits; Die Rev. J (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 35 37 39 41 43 mA x8 37 39 41 43 44 mA x16 44 46 48 50 52 mA IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 3 3 3 3 3 mA x16 4 4 4 4 4 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 48 50 51 53 55 mA x8 52 54 56 58 60 mA x16 68 70 72 74 76 mA IDD2N: Precharge standby current ALL 28 29 30 30 31 mA IDD2NT: Precharge standby ODT current x4, x8 34 36 38 40 42 mA x16 41 44 47 50 53 mA IDD2P: Precharge power-down current ALL 22 22 22 22 22 mA IDD2Q: Precharge quiet standby current ALL 26 26 26 26 26 mA IDD0: One bank ACTIVATE-to-PRECHARGE current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 338 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 155: IDD, IPP, and IDDQ Current Limits; Die Rev. J (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 34 36 38 40 42 mA x8 35 37 39 41 43 mA x16 36 38 40 42 44 mA ALL 3 3 3 3 3 mA x4 28 29 30 31 32 mA x8 29 30 31 32 33 mA x16 30 31 32 33 34 mA x4 105 114 125 135 145 mA x8 128 138 148 158 169 mA x16 223 240 260 278 296 mA x4 91 100 108 117 126 mA x8 108 116 125 134 142 mA x16 173 189 205 221 238 mA IDD5R: Distributed refresh current (1X REF) ALL 44 45 45 46 47 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 32 32 32 32 32 mA ALL 55 55 55 55 55 mA ALL 20 20 20 20 20 mA ALL 8.2 8.2 8.2 8.2 8.2 mA ALL 20 20 20 20 20 mA ALL 30 30 30 30 30 mA ALL 55 55 55 55 55 mA ALL 5 5 5 5 5 mA x4 166 176 190 205 219 mA x8 161 166 171 175 180 mA x16 222 231 240 248 257 mA IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; nιC 3, 4 IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IDD6A: Auto self refresh current (95ιC)4 IPP6x: Auto self refresh IPP CURRENT nιC27 IDD7: Bank interleave read current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 339 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 155: IDD, IPP, and IDDQ Current Limits; Die Rev. J (-40ι ζ TC ζ 85ιC) Symbol IPP7: Bank interleave read IPP current IDD8: Maximum power-down current Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 11 11 11 11 11 mA x8 10 10 10 10 13 mA x16 15 15 15 15 15 mA ALL 18 18 18 18 18 mA Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation  nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation  nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation  nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1, current changes by approximately +8%(x4/x8), +7%(x16). 7. When additive latency is enabled for IDD2N, current changes by approximately +1%. 8. When DLL is disabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 9. When CAL is enabled for IDD2NCURRENTCHANGESBYAPPROXIMATELYn 10. When gear-down is enabled for IDD2N, current changes by approximately 0%. 11. When CA parity is enabled for IDD2N, current changes by approximately +13%. 12. When additive latency is enabled for IDD3N, current changes by approximately +2%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4(x4/x8), +3%(x16). 14. When read DBI is enabled for IDD4R, current changes by approximately -14%(x4/x8), -20%(x16). 15. When additive latency is enabled for IDD4W, current changes by approximately +4%(x4/x8), +3%(x16). 16. When write DBI is enabled for IDD4W, current changes by approximately 0%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +12%. 19. When 2X REF is enabled for IDD5R, current changes by approximately +0%. 20. When 4X REF is enabled for IDD5R, current changes by approximately +0%. 21. When 2X REF is enabled for IPP5R, current changes by approximately +0%. 22. When 4X REF is enabled for IPP5R, current changes by approximately +0%. 23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 26. The IDD values must be derated (increased) when operating between 85ιC < TC ζ 95ιC: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W, must be derated by +3%; IDD2P must be derated by +13%; IDD5R and IPP5R must be derated by +43%; All IPP currents except IPP6x and IPP5R must be derated by +0%. These values are verified by design and characterization, and may not be subject to production test. 27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. Table 156: IDD, IPP, and IDDQ Current Limits; Die Rev. R (-40ι ζ TC ζ 85ιC) Symbol IDD0: One bank ACTIVATE-to-PRECHARGE current CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit x4 38 40 42 44 46 mA x8 40 42 44 46 48 mA x16 51 53 55 57 59 mA 340 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 156: IDD, IPP, and IDDQ Current Limits; Die Rev. R (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit IPP0: One bank ACTIVATE-to-PRECHARGE IPP current x4, x8 4 4 4 4 4 mA x16 5 5 5 5 5 mA IDD1: One bank ACTIVATE-to-READ-to- PRECHARGE current x4 43 45 47 49 51 mA x8 47 49 51 53 55 mA x16 61 63 65 67 69 mA IDD2N: Precharge standby current ALL 34 35 36 37 38 mA IDD2NT: Precharge standby ODT current x4, x8 33 35 37 39 41 mA x16 38 40 42 44 46 mA IDD2P: Precharge power-down current ALL 30 30 30 30 30 mA IDD2Q: Precharge quiet standby current ALL 34 34 34 34 34 mA x4 34 36 38 40 42 mA x8 35 37 39 41 43 mA x16 36 38 40 42 44 mA ALL 3 3 3 3 3 mA x4 28 29 30 31 32 mA x8 29 30 31 32 33 mA x16 30 31 32 33 34 mA x4 74 80 88 95 103 mA x8 92 98 105 113 123 mA x16 130 139 151 164 176 mA x4 62 66 70 76 82 mA x8 79 85 91 98 106 mA x16 102 109 119 127 138 mA IDD5R: Distributed refresh current (1X REF) ALL 44 45 45 46 47 mA IPP5R: Distributed refresh IPP current (1X REF) ALL 5 5 5 5 5 mA IDD6N: Self refresh current; ALL 32 32 32 32 32 mA ALL 52 52 52 52 52 mA ALL 19 19 19 19 19 mA IDD3N: Active standby current IPP3N: Active standby IPP current IDD3P: Active power-down current IDD4R: Burst read current IDD4W: Burst write current nιC 1 IDD6E: Self refresh current; nιC 2, 4 IDD6R: Self refresh current; nιC 3, 4 CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 341 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS Table 156: IDD, IPP, and IDDQ Current Limits; Die Rev. R (-40ι ζ TC ζ 85ιC) Symbol Width DDR4-2133 DDR4-2400 DDR4-2666 DDR4-2933 DDR4-3200 Unit ALL 8 8 8 8 8 mA ALL 19 19 19 19 19 mA ALL 29 29 29 29 29 mA ALL 52 52 52 52 52 mA ALL 5 5 5 5 5 mA x4 154 169 186 200 215 mA x8 135 140 145 150 155 mA x16 165 179 196 210 225 mA x4 13 13 13 13 13 mA x8 8 8 8 8 8 mA x16 13 13 13 13 13 mA IDD8: Maximum power-down current ALL 24 24 24 24 24 mA IDD9: MBIST-PPR current ALL 170 170 170 170 170 mA IPP9: MBIST-PPR IPP current ALL 13 13 13 13 13 mA IDD6A: Auto self refresh current (25ιC)4 IDD6A: Auto self refresh current (45ιC)4 IDD6A: Auto self refresh current (75ιC)4 IDD6A: Auto self refresh current (95ιC)4 IPP6x: Auto self refresh IPP CURRENT nιC27 IDD7: Bank interleave read current IPP7: Bank interleave read IPP current Notes: 1. Applicable for MR2 settings A7 = 0 and A6 = 0; manual mode with normal temperature range of operation  nιC). 2. Applicable for MR2 settings A7 = 1 and A6 = 0; manual mode with extended temperature range of operation  nιC). 3. Applicable for MR2 settings A7 = 0 and A6 = 1; manual mode with reduced temperature range of operation  nιC). 4. IDD6E, IDD6R, IDD6A values are verified by design and characterization, and may not be subject to production test. 5. When additive latency is enabled for IDD0, current changes by approximately +1%. 6. When additive latency is enabled for IDD1, current changes by approximately +5%. 7. When additive latency is enabled for IDD2N, current changes by approximately 2%. 8. When DLL is disabled for IDD2N, current changes by approximately +19%. 9. When CAL is enabled for IDD2N, current changes by approximately -20%. 10. When gear-down is enabled for IDD2N, current changes by approximately +2%. 11. When CA parity is enabled for IDD2N, current changes by approximately +10%. 12. When additive latency is enabled for IDD3N, current changes by approximately -2%. 13. When additive latency is enabled for IDD4R, current changes by approximately +4%. 14. When read DBI is enabled for IDD4R, current changes by approximately -14% 15. When additive latency is enabled for IDD4W, current changes by approximately +6%. 16. When write DBI is enabled for IDD4W, current changes by approximately +1%. 17. When write CRC is enabled for IDD4W, current changes by approximately -5%. 18. When CA parity is enabled for IDD4W, current changes by approximately +14%. 19. When 2X REF is enabled for IDD5R, current changes by approximately 0%. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 342 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM #URRENT3PECIFICATIONSn,IMITS 20. When 4X REF is enabled for IDD5R, current changes by approximately 0%. 21. When 2X REF is enabled for IPP5R, current changes by approximately 0%. 22. When 4X REF is enabled for IPP5R, current changes by approximately 0%. 23. IPP0 test and limit is applicable for IDD0 and IDD1 conditions. 24. IPP3N test and limit is applicable for all IDD2x, IDD3x, IDD4x and IDD8 conditions; that is, testing IPP3N should satisfy the IPPs for the noted IDD tests. 25. DDR4-1600 and DDR4-1866 use the same IDD limits as DDR4-2133. 26. The IDD values must be derated (increased) when operating between 85ιC < TC ζ 95ιC: IDD0, IDD1, IDD2N ,IDD2P ,IDD2NT ,IDD2Q, IDD3N, IDD3P, IDD4R, and IDD4W, must be derated by +10%. IDD5R and IPP5R must be derated by +43%; IPP0 must be derated by +13%. IPP3N must be derated by +22%. IPP7 must be derated by +3%. These values are verified by design and characterization, and may not be subject to production test. 27. IPP6x is applicable to IDD6N, IDD6E, IDD6R and IDD6A conditions. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 343 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. 8Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables Speed Bin Tables DDR4 DRAM timing is primarily covered by two types of tables: the Speed Bin tables in this section and the tables found in the Electrical Characteristics and AC Timing Parameters section. The timing parameter tables define the applicable timing specifications based on the speed rating. The Speed Bin tables on the following pages list the tAA, tRCD, tRP, tRAS, and tRC limits of a given speed mark and are applicable to the CL settings in the lower half of the table provided they are applied in the correct clock range, which is noted. Backward Compatibility Although the speed bin tables list the slower data rates, tAA, CL, and CWL, it is difficult to determine whether a faster speed bin supports all of the tAA, CL, and CWL combinations across all the data rates of a slower speed bin. To assist in this process, please refer to the Backward Compatibility table. CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN 344 Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. Note 1 applies to the entire table. Speed Bin Supported Component Speed Bin CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Table 157: Backward Compatibility -125 -125 yes -125E yes2 -107 yes -107E yes2 -093 yes -093E yes2 -083D yes yes yes yes -083 yes yes yes yes 345 -083E yes 2 -125E -107 -107E -093 -093E -083D -083 -083E -075D -075 -075E -068D -068 -068E -062 -062E -062Y yes yes yes yes2 yes yes yes yes yes2 yes 2 yes yes yes yes2 yes 2 yes yes yes 2 yes yes2 yes yes yes yes yes -075 yes yes yes yes yes yes yes -075E yes yes yes yes yes -068D yes yes yes yes -068 yes yes yes yes yes yes yes yes yes -068E yes yes yes yes yes yes yes yes yes -062 yes yes yes yes -062E yes yes yes yes yes -062Y yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes Notes: 1. The backward compatibility table is not meant to guarantee that any new device will be a drop in replacement for an existing part number. Customers should review the operating conditions for any device to determine its suitability for use in their design. 2. This condition exceeds the JEDEC requirement in order to allow additional flexibility for components. However, JEDEC SPD compliance may force modules to only support the JEDEC-defined value. Refer to the SPD documentation for further clarification. 8Gb: x4, x8, x16 DDR4 SDRAM Speed Bin Tables Micron Technology, Inc. reserves the right to change products or specifications without notice. ¥2015 Micron Technology, Inc. All rights reserved. -075D CCMTD-1725822587-9875 8gb_ddr4_dram.pdf - Rev. T 09/2021 EN Table 158: DDR4-1600 Speed Bins and Operating Conditions Notes 1n3 apply to the entire table DDR4-1600 Speed Bin -125E CL-nRCD-nRP 11-11-11 Parameter Symbol AA_DBI t AA (MIN) + 2nCK t AA (MAX) + 2nCK t AA (MIN) + 2nCK t AA (MAX) + 2nCK ns RCD 13.75 (13.50)4 n 15.00 n ns t RP 13.75 (13.50)4 n 15.00 n ns RAS 35 9 έ tREFI 35 9 έ tREFI ns RAS + t RP n RAS + t RP n ns t ACTIVATE-to-ACTIVATE or REFRESH command period t 346 1600 READ CL: DBI - 13.50 9 11 - 15.00 10 12 -125E 13.75 11 13 -125 15.00 12 14 WRITE CWL 9 Symbol Min Max 1.500 1.9006 t 1.5006 1.9006 t 1.250