MT41J256M16HA-107:E

4Gb: x16 DDR3 SDRAM Reduced tFAW Addendum Features DDR3 SDRAM Reduced tFAW Addendum MT41J256M16 – 32 Meg x 16 x 8 Banks Features • • • • • • • • • • • • • • • • • • Options Marking • Configuration – 256 Meg x 16 • FBGA package (Pb-free) – x16 – 96-ball (8mm x 14mm) • Timing – cycle time – 938ps @ CL = 14 (DDR3-2133) • Reduced tFAW – tFAW = 30ns1 • Operating temperature – Commercial (0°C ≤ T C ≤ +95°C) • Revision VDD = V DDQ = 1.5V ±0.075V 1.5V center-terminated push/pull I/O Differential bidirectional data strobe 8n-bit prefetch architecture Differential clock inputs (CK, CK#) 8 internal banks Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals Programmable CAS READ latency (CL) Posted CAS additive latency (AL) Programmable CAS WRITE latency (CWL) based on tCK Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) Selectable BC4 or BL8 on-the-fly (OTF) Self refresh mode TC of 0°C to 95°C – 64ms, 8192 cycle refresh at 0°C to 85°C – 32ms, 8192 cycle refresh at 85°C to 95°C Self refresh temperature (SRT) Write leveling Multipurpose register Output driver calibration Notes: 256M16 HA -093 J None :E 1. Standard DDR3-2133, 2KB page size, tFAW specification is 35ns. 2. For complete device functionality and specifications, refer to the standard 4Gb DDR3 SDRAM data sheet found at www.micron.com. The information in this data sheet supersedes the standard data sheet. Table 1: Key Timing Parameters Speed Grade Data Rate (MT/s) tFAW Target tRCD-tRP-CL -093 2133 30ns 14-14-14 tRCD (ns) tRP 13.09 (ns) 13.09 CL (ns) 13.09 Table 2: Addressing Parameter 256 Meg x 16 Configuration 32 Meg x 16 x 8 banks Refresh count 8K Row addressing 32K (A[14:0]) Bank addressing 8 (BA[2:0]) Column addressing 1K (A[9:0]) Page size 2KB PDF: 09005aef857c6ed1 4Gb_DDR3_SDRAM_tFAW.pdf - Rev. B 3/14 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 4Gb: x16 DDR3 SDRAM Reduced tFAW Addendum Features Figure 1: DDR3 Part Numbers Example Part Number: MT41J256M16HA-093 J:E - MT41J Configuration Package : Speed Revision :E Configuration 256 Meg x 16 Reduced tFAW 30ns tFAW 256M16 Package 96-ball 9mm x 14mm FBGA Note: Revision Rev. Mark E HA J Speed Grade -093 tCK = 0.938ns, CL = 14 1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings. FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site: http://www.micron.com. PDF: 09005aef857c6ed1 4Gb_DDR3_SDRAM_tFAW.pdf - Rev. B 3/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved. 4Gb: x16 DDR3 SDRAM Reduced tFAW Addendum AC Timing Adjustments AC Timing Adjustments Table 3: Electrical Characteristics and AC Operating Conditions for Speed Extensions Notes 1–8 apply to the entire table DDR3-2133 Parameter Symbol Min Max Unit Notes – ns 9 Command and Address Timing Four ACTIVATE windows Notes: 2KB page size 1. 2. 3. 4. 5. 6. 7. 8. 9. tFAW 30 AC timing parameters are valid from specified TC MIN to TC MAX values. All voltages are referenced to VSS. Output timings are only valid for RON34 output buffer selection. The unit tCK (AVG) represents the actual tCK (AVG) of the input clock. The unit CK represents one clock cycle of the input clock, counting the actual clock edges. AC timing and IDD tests may use a VIL-to-VIH swing of up to 900mV in the test environment, but input timing is still referenced to VREF (except tIS, tIH, tDS, and tDH use the AC/DC trip points and CK, CK# and DQS, DQS# use their crossing points). The minimum slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs (DQs are at 2V/ns for DDR3-1866 and DDR3-2133) and 2 V/ns for differential inputs in the range between VIL(AC) and VIH(AC). All timings that use time-based values (ns, µs, ms) should use tCK (AVG) to determine the correct number of clocks (Table 3 (page 3) uses CK or tCK [AVG] interchangeably). In the case of noninteger results, all minimum limits are to be rounded up to the nearest whole integer, and all maximum limits are to be rounded down to the nearest whole integer. Strobe or DQSdiff refers to the DQS and DQS# differential crossing point when DQS is the rising edge. Clock or CK refers to the CK and CK# differential crossing point when CK is the rising edge. This output load is used for all AC timing (except ODT reference timing) and slew rates. The actual test load may be different. The output signal voltage reference point is VDDQ/2 for single-ended signals and the crossing point for differential signals. For these parameters, the DDR3 SDRAM device supports tnPARAM (nCK) = RU(tPARAM [ns]/tCK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP (nCK) = RU(tRP/tCK[AVG]) if all input clock jitter specifications are met. This means that for DDR3-800 6-6-6, of which tRP = 5ns, the device will support tnRP = RU(tRP/tCK[AVG]) = 6 as long as the input clock jitter specifications are met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are valid even if six clocks are less than 15ns due to input clock jitter. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef857c6ed1 4Gb_DDR3_SDRAM_tFAW.pdf - Rev. B 3/14 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2013 Micron Technology, Inc. All rights reserved.