2Gb: x4, x8, x16 DDR3 SDRAM
Features
DDR3 SDRAM
MT41J512M4 – 64 Meg x 4 x 8 Banks
MT41J256M8 – 32 Meg x 8 x 8 Banks
MT41J128M16 – 16 Meg x 16 x 8 Banks
Options1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Marking
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. H,M,J,K
– 78-ball (9mm x 11.5mm) Rev. D
• FBGA package (Pb-free) – x16
– 96-ball (9mm x 14mm) Rev. D
– 96-ball (8mm x 14mm) Rev. K
• Timing – cycle time
– 938ps @ CL = 14 (DDR3-2133)
– 1.071ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
• Operating temperature
– Commercial (0°C ื T C ื +95°C)
– Industrial (–40°C ื T C ื +95°C)
• Revision
VDD = V DDQ = 1.5V ±0.075V
1.5V center-terminated push/pull I/O
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS READ latency (CL)
Posted CAS additive latency (AL)
Programmable CAS WRITE latency (CWL) based on
tCK
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
TC of 0°C to 95°C
– 64ms, 8192 cycle refresh at 0°C to 85°C
– 32ms, 8192 cycle refresh at 85°C to 95°C
Self refresh temperature (SRT)
Write leveling
Multipurpose register
Output driver calibration
Note:
512M4
256M8
128M16
DA
HX
HA
JT
-093
-107
-125
-15E
-187E
None
IT
:D/:H/:J/:K/
:M
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-0931, 2, 3, 4
2133
14-14-14
13.09
13.09
13.09
-1071, 2, 3
1866
13-13-13
13.91
13.91
13.91
-1251, 2,
1600
11-11-11
13.75
13.75
13.75
-15E1,
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
Notes:
1.
2.
3.
4.
tRCD
(ns)
tRP
(ns)
CL (ns)
Backward compatible to 1066, CL = 7 (-187E).
Backward compatible to 1333, CL = 9 (-15E).
Backward compatible to 1600, CL = 11 (-125).
Backward compatible to 1866, CL = 13 (-107).
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 2: Addressing
Parameter
Configuration
512 Meg x 4
256 Meg x 8
128 Meg x 16
64 Meg x 4 x 8 banks
32 Meg x 8 x 8 banks
16 Meg x 16 x 8 banks
Refresh count
8K
8K
8K
Row addressing
32K (A[14:0])
32K (A[14:0])
16K (A[13:0])
Bank addressing
8 (BA[2:0])
8 (BA[2:0])
8 (BA[2:0])
2K (A[11, 9:0])
1K (A[9:0])
1K (A[9:0])
1KB
1KB
2KB
Column addressing
Page size
Figure 1: DDR3 Part Numbers
Example Part Number:
MT41J256M8JE-125:M
-
Configuration
Package
Speed
Revision
^
MT41J
:
:D/:H/:K/:M Revision
Configuration
512 Meg x 4
512M4
Temperature
256 Meg x 8
256M8
Commercial
128 Meg x 16
128M16
Industrial temperature
Package
78-ball 9mm x 11.5mm FBGA
HX
-093
78-ball 8mm x 10.5mm FBGA
DA
-107
96-ball 9mm x 14mm FBGA
HA
-125
96-ball 8mm x 14mm FBGA
JT
-15E
-187E
Note:
None
IT
Speed Grade
tCK = 0.938ns, CL = 14
tCK = 1.071ns, CL = 13
tCK = 1.25ns, CL = 11
tCK = 1.5ns, CL = 9
tCK = 1.87ns, CL = 7
1. Not all options listed can be combined to define an offered product. Use the part catalog search on
http://www.micron.com for available offerings.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the
part number. For a quick conversion of an FBGA code, see the FBGA Part Marking Decoder on Micron’s Web site:
http://www.micron.com.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Contents
State Diagram ................................................................................................................................................ 11
Functional Description ................................................................................................................................... 12
Industrial Temperature ............................................................................................................................... 12
General Notes ............................................................................................................................................ 12
Functional Block Diagrams ............................................................................................................................. 14
Ball Assignments and Descriptions ................................................................................................................. 16
Package Dimensions ....................................................................................................................................... 22
Electrical Specifications .................................................................................................................................. 26
Absolute Ratings ......................................................................................................................................... 26
Input/Output Capacitance .......................................................................................................................... 27
Thermal Characteristics .................................................................................................................................. 28
Electrical Specifications – IDD Specifications and Conditions ............................................................................ 30
Electrical Characteristics – IDD Specifications .................................................................................................. 41
Electrical Specifications – DC and AC .............................................................................................................. 45
DC Operating Conditions ........................................................................................................................... 45
Input Operating Conditions ........................................................................................................................ 45
AC Overshoot/Undershoot Specification ..................................................................................................... 48
Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 52
Slew Rate Definitions for Differential Input Signals ...................................................................................... 54
ODT Characteristics ....................................................................................................................................... 55
ODT Resistors ............................................................................................................................................ 56
ODT Sensitivity .......................................................................................................................................... 57
ODT Timing Definitions ............................................................................................................................. 57
Output Driver Impedance ............................................................................................................................... 61
34 Ohm Output Driver Impedance .............................................................................................................. 62
34 Ohm Driver ............................................................................................................................................ 63
34 Ohm Output Driver Sensitivity ................................................................................................................ 64
Alternative 40 Ohm Driver .......................................................................................................................... 65
40 Ohm Output Driver Sensitivity ................................................................................................................ 65
Output Characteristics and Operating Conditions ............................................................................................ 67
Reference Output Load ............................................................................................................................... 69
Slew Rate Definitions for Single-Ended Output Signals ................................................................................. 70
Slew Rate Definitions for Differential Output Signals .................................................................................... 71
Speed Bin Tables ............................................................................................................................................ 72
Electrical Characteristics and AC Operating Conditions ................................................................................... 77
Command and Address Setup, Hold, and Derating ........................................................................................... 97
Data Setup, Hold, and Derating ...................................................................................................................... 105
Commands – Truth Tables ............................................................................................................................. 114
Commands ................................................................................................................................................... 117
DESELECT ................................................................................................................................................ 117
NO OPERATION ........................................................................................................................................ 117
ZQ CALIBRATION LONG ........................................................................................................................... 117
ZQ CALIBRATION SHORT .......................................................................................................................... 117
ACTIVATE ................................................................................................................................................. 117
READ ........................................................................................................................................................ 117
WRITE ...................................................................................................................................................... 118
PRECHARGE ............................................................................................................................................. 119
REFRESH .................................................................................................................................................. 119
SELF REFRESH .......................................................................................................................................... 120
DLL Disable Mode ..................................................................................................................................... 121
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Input Clock Frequency Change ...................................................................................................................... 125
Write Leveling ............................................................................................................................................... 127
Write Leveling Procedure ........................................................................................................................... 129
Write Leveling Mode Exit Procedure ........................................................................................................... 131
Initialization ................................................................................................................................................. 132
Mode Registers .............................................................................................................................................. 134
Mode Register 0 (MR0) ................................................................................................................................... 135
Burst Length ............................................................................................................................................. 135
Burst Type ................................................................................................................................................. 136
DLL RESET ................................................................................................................................................ 137
Write Recovery .......................................................................................................................................... 137
Precharge Power-Down (Precharge PD) ...................................................................................................... 138
CAS Latency (CL) ....................................................................................................................................... 138
Mode Register 1 (MR1) ................................................................................................................................... 139
DLL ENABLE/DISABLE .............................................................................................................................. 139
Output Drive Strength ............................................................................................................................... 140
OUTPUT ENABLE/DISABLE ...................................................................................................................... 140
TDQS ENABLE .......................................................................................................................................... 140
On-Die Termination (ODT) ........................................................................................................................ 141
WRITE LEVELING ..................................................................................................................................... 141
Posted CAS Additive Latency (AL) ............................................................................................................... 141
Mode Register 2 (MR2) ................................................................................................................................... 143
CAS WRITE Latency (CWL) ........................................................................................................................ 143
AUTO SELF REFRESH (ASR) ....................................................................................................................... 144
SELF REFRESH TEMPERATURE (SRT) ........................................................................................................ 144
SRT versus ASR .......................................................................................................................................... 145
Dynamic On-Die Termination (ODT) ......................................................................................................... 145
Mode Register 3 (MR3) ................................................................................................................................... 146
MULTIPURPOSE REGISTER (MPR) ............................................................................................................ 146
MPR Functional Description ...................................................................................................................... 147
MPR Address Definitions and Bursting Order .............................................................................................. 148
MPR Read Predefined Pattern .................................................................................................................... 153
MODE REGISTER SET (MRS) Command ........................................................................................................ 153
ZQ CALIBRATION Operation ......................................................................................................................... 154
ACTIVATE Operation ..................................................................................................................................... 155
READ Operation ............................................................................................................................................ 157
WRITE Operation .......................................................................................................................................... 168
DQ Input Timing ....................................................................................................................................... 176
PRECHARGE Operation ................................................................................................................................. 178
SELF REFRESH Operation .............................................................................................................................. 178
Extended Temperature Usage ........................................................................................................................ 180
Power-Down Mode ........................................................................................................................................ 181
RESET Operation ........................................................................................................................................... 189
On-Die Termination (ODT) ............................................................................................................................ 191
Functional Representation of ODT ............................................................................................................. 191
Nominal ODT ............................................................................................................................................ 191
Dynamic ODT ............................................................................................................................................... 193
Dynamic ODT Special Use Case ................................................................................................................. 193
Functional Description .............................................................................................................................. 193
Synchronous ODT Mode ................................................................................................................................ 199
ODT Latency and Posted ODT .................................................................................................................... 199
Timing Parameters .................................................................................................................................... 199
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
ODT Off During READs .............................................................................................................................. 202
Asynchronous ODT Mode .............................................................................................................................. 204
Synchronous to Asynchronous ODT Mode Transition (Power-Down Entry) .................................................. 206
Asynchronous to Synchronous ODT Mode Transition (Power-Down Exit) ........................................................ 208
Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse) ...................................................... 210
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
List of Figures
Figure 1: DDR3 Part Numbers .......................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................. 11
Figure 3: 512 Meg x 4 Functional Block Diagram ............................................................................................. 14
Figure 4: 256 Meg x 8 Functional Block Diagram ............................................................................................. 15
Figure 5: 128 Meg x 16 Functional Block Diagram ........................................................................................... 15
Figure 6: 78-Ball FBGA – x4, x8 (Top View) ...................................................................................................... 16
Figure 7: 96-Ball FBGA – x16 (Top View) ......................................................................................................... 17
Figure 8: 78-Ball FBGA – x4, x8 (DA) ............................................................................................................... 22
Figure 9: 78-Ball FBGA – x4, x8 (HX) ............................................................................................................... 23
Figure 10: 96-Ball FBGA – x16 (HA) ................................................................................................................. 24
Figure 11: 96-Ball FBGA – x16 (JT) .................................................................................................................. 25
Figure 12: Thermal Measurement Point ......................................................................................................... 29
Figure 13: Input Signal .................................................................................................................................. 47
Figure 14: Overshoot ..................................................................................................................................... 48
Figure 15: Undershoot ................................................................................................................................... 48
Figure 16: V IX for Differential Signals .............................................................................................................. 50
Figure 17: Single-Ended Requirements for Differential Signals ........................................................................ 50
Figure 18: Definition of Differential AC-Swing and tDVAC ............................................................................... 51
Figure 19: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 53
Figure 20: Nominal Differential Input Slew Rate Definition for DQS, DQS# and CK, CK# .................................. 54
Figure 21: ODT Levels and I-V Characteristics ................................................................................................ 55
Figure 22: ODT Timing Reference Load .......................................................................................................... 58
Figure 23: tAON and tAOF Definitions ............................................................................................................ 59
Figure 24: tAONPD and tAOFPD Definitions ................................................................................................... 59
Figure 25: tADC Definition ............................................................................................................................. 60
Figure 26: Output Driver ................................................................................................................................ 61
Figure 27: DQ Output Signal .......................................................................................................................... 68
Figure 28: Differential Output Signal .............................................................................................................. 69
Figure 29: Reference Output Load for AC Timing and Output Slew Rate ........................................................... 69
Figure 30: Nominal Slew Rate Definition for Single-Ended Output Signals ....................................................... 70
Figure 31: Nominal Differential Output Slew Rate Definition for DQS, DQS# .................................................... 71
Figure 32: Nominal Slew Rate and tVAC for tIS (Command and Address – Clock) ............................................. 101
Figure 33: Nominal Slew Rate for tIH (Command and Address – Clock) ........................................................... 102
Figure 34: Tangent Line for tIS (Command and Address – Clock) .................................................................... 103
Figure 35: Tangent Line for tIH (Command and Address – Clock) .................................................................... 104
Figure 36: Nominal Slew Rate and tVAC for tDS (DQ – Strobe) ......................................................................... 110
Figure 37: Nominal Slew Rate for tDH (DQ – Strobe) ...................................................................................... 111
Figure 38: Tangent Line for tDS (DQ – Strobe) ................................................................................................ 112
Figure 39: Tangent Line for tDH (DQ – Strobe) ............................................................................................... 113
Figure 40: Refresh Mode ............................................................................................................................... 120
Figure 41: DLL Enable Mode to DLL Disable Mode ........................................................................................ 122
Figure 42: DLL Disable Mode to DLL Enable Mode ........................................................................................ 123
Figure 43: DLL Disable tDQSCK .................................................................................................................... 124
Figure 44: Change Frequency During Precharge Power-Down ........................................................................ 126
Figure 45: Write Leveling Concept ................................................................................................................. 127
Figure 46: Write Leveling Sequence ............................................................................................................... 130
Figure 47: Write Leveling Exit Procedure ....................................................................................................... 131
Figure 48: Initialization Sequence ................................................................................................................. 133
Figure 49: MRS to MRS Command Timing ( tMRD) ......................................................................................... 134
Figure 50: MRS to nonMRS Command Timing ( tMOD) .................................................................................. 135
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 51: Mode Register 0 (MR0) Definitions ................................................................................................ 136
Figure 52: READ Latency .............................................................................................................................. 138
Figure 53: Mode Register 1 (MR1) Definition ................................................................................................. 139
Figure 54: READ Latency (AL = 5, CL = 6) ....................................................................................................... 142
Figure 55: Mode Register 2 (MR2) Definition ................................................................................................. 143
Figure 56: CAS WRITE Latency ...................................................................................................................... 144
Figure 57: Mode Register 3 (MR3) Definition ................................................................................................. 146
Figure 58: MPR Block Diagram ...................................................................................................................... 147
Figure 59: MPR System Read Calibration with BL8: Fixed Burst Order Single Readout ..................................... 149
Figure 60: MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout .......................... 150
Figure 61: MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble .................................... 151
Figure 62: MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble .................................... 152
Figure 63: ZQ CALIBRATION Timing (ZQCL and ZQCS) ................................................................................. 154
Figure 64: Example: Meeting tRRD (MIN) and tRCD (MIN) ............................................................................. 155
Figure 65: Example: tFAW ............................................................................................................................. 156
Figure 66: READ Latency .............................................................................................................................. 157
Figure 67: Consecutive READ Bursts (BL8) .................................................................................................... 159
Figure 68: Consecutive READ Bursts (BC4) .................................................................................................... 159
Figure 69: Nonconsecutive READ Bursts ....................................................................................................... 160
Figure 70: READ (BL8) to WRITE (BL8) .......................................................................................................... 160
Figure 71: READ (BC4) to WRITE (BC4) OTF .................................................................................................. 161
Figure 72: READ to PRECHARGE (BL8) .......................................................................................................... 161
Figure 73: READ to PRECHARGE (BC4) ......................................................................................................... 162
Figure 74: READ to PRECHARGE (AL = 5, CL = 6) ........................................................................................... 162
Figure 75: READ with Auto Precharge (AL = 4, CL = 6) ..................................................................................... 162
Figure 76: Data Output Timing – tDQSQ and Data Valid Window .................................................................... 164
Figure 77: Data Strobe Timing – READs ......................................................................................................... 165
Figure 78: Method for Calculating tLZ and tHZ ............................................................................................... 166
Figure 79: tRPRE Timing ............................................................................................................................... 166
Figure 80: tRPST Timing ............................................................................................................................... 167
Figure 81: tWPRE Timing .............................................................................................................................. 169
Figure 82: tWPST Timing .............................................................................................................................. 169
Figure 83: WRITE Burst ................................................................................................................................ 170
Figure 84: Consecutive WRITE (BL8) to WRITE (BL8) ..................................................................................... 171
Figure 85: Consecutive WRITE (BC4) to WRITE (BC4) via OTF ........................................................................ 171
Figure 86: Nonconsecutive WRITE to WRITE ................................................................................................. 172
Figure 87: WRITE (BL8) to READ (BL8) .......................................................................................................... 172
Figure 88: WRITE to READ (BC4 Mode Register Setting) ................................................................................. 173
Figure 89: WRITE (BC4 OTF) to READ (BC4 OTF) ........................................................................................... 174
Figure 90: WRITE (BL8) to PRECHARGE ........................................................................................................ 175
Figure 91: WRITE (BC4 Mode Register Setting) to PRECHARGE ...................................................................... 175
Figure 92: WRITE (BC4 OTF) to PRECHARGE ................................................................................................ 176
Figure 93: Data Input Timing ........................................................................................................................ 177
Figure 94: Self Refresh Entry/Exit Timing ...................................................................................................... 179
Figure 95: Active Power-Down Entry and Exit ................................................................................................ 183
Figure 96: Precharge Power-Down (Fast-Exit Mode) Entry and Exit ................................................................. 184
Figure 97: Precharge Power-Down (Slow-Exit Mode) Entry and Exit ................................................................ 184
Figure 98: Power-Down Entry After READ or READ with Auto Precharge (RDAP) ............................................. 185
Figure 99: Power-Down Entry After WRITE .................................................................................................... 185
Figure 100: Power-Down Entry After WRITE with Auto Precharge (WRAP) ...................................................... 186
Figure 101: REFRESH to Power-Down Entry .................................................................................................. 186
Figure 102: ACTIVATE to Power-Down Entry ................................................................................................. 187
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Figure 103:
Figure 104:
Figure 105:
Figure 106:
Figure 107:
Figure 108:
Figure 109:
Figure 110:
Figure 111:
Figure 112:
Figure 113:
Figure 114:
Figure 115:
Figure 116:
Figure 117:
Figure 118:
Figure 119:
Figure 120:
PRECHARGE to Power-Down Entry ............................................................................................. 187
MRS Command to Power-Down Entry ......................................................................................... 188
Power-Down Exit to Refresh to Power-Down Entry ....................................................................... 188
RESET Sequence ......................................................................................................................... 190
On-Die Termination ................................................................................................................... 191
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4 .................................................... 196
Dynamic ODT: Without WRITE Command .................................................................................. 196
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8 ............ 197
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4 .......................... 198
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4 .......................... 198
Synchronous ODT ...................................................................................................................... 200
Synchronous ODT (BC4) ............................................................................................................. 201
ODT During READs .................................................................................................................... 203
Asynchronous ODT Timing with Fast ODT Transition .................................................................. 205
Synchronous to Asynchronous Transition During Precharge Power-Down (DLL Off) Entry ............ 207
Asynchronous to Synchronous Transition During Precharge Power-Down (DLL Off) Exit ............... 209
Transition Period for Short CKE LOW Cycles with Entry and Exit Period Overlapping ..................... 211
Transition Period for Short CKE HIGH Cycles with Entry and Exit Period Overlapping ................... 211
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
List of Tables
Table 1: Key Timing Parameters ....................................................................................................................... 1
Table 2: Addressing ......................................................................................................................................... 2
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions .............................................................................................. 18
Table 4: 96-Ball FBGA – x16 Ball Descriptions ................................................................................................. 20
Table 5: Absolute Maximum Ratings .............................................................................................................. 26
Table 6: DDR3 Input/Output Capacitance ...................................................................................................... 27
Table 7: Thermal Characteristics .................................................................................................................... 28
Table 8: Timing Parameters Used for I DD Measurements – Clock Units ............................................................ 30
Table 9: IDD0 Measurement Loop ................................................................................................................... 31
Table 10: IDD1 Measurement Loop .................................................................................................................. 32
Table 11: IDD Measurement Conditions for Power-Down Currents ................................................................... 33
Table 12: IDD2N and IDD3N Measurement Loop ................................................................................................ 34
Table 13: IDD2NT Measurement Loop .............................................................................................................. 34
Table 14: IDD4R Measurement Loop ................................................................................................................ 35
Table 15: IDD4W Measurement Loop ............................................................................................................... 36
Table 16: IDD5B Measurement Loop ................................................................................................................ 37
Table 17: IDD Measurement Conditions for IDD6, IDD6ET, and IDD8 .................................................................... 38
Table 18: IDD7 Measurement Loop .................................................................................................................. 39
Table 19: IDD Maximum Limits – Die Rev D ..................................................................................................... 41
Table 20: IDD Maximum Limits – Die Rev H .................................................................................................... 42
Table 21: IDD Maximum Limits – Die Rev J, M ................................................................................................. 43
Table 22: IDD Maximum Limits – Die Rev K ..................................................................................................... 43
Table 23: DC Electrical Characteristics and Operating Conditions ................................................................... 45
Table 24: DC Electrical Characteristics and Input Conditions .......................................................................... 45
Table 25: Input Switching Conditions ............................................................................................................. 46
Table 26: Control and Address Pins ................................................................................................................ 48
Table 27: Clock, Data, Strobe, and Mask Pins .................................................................................................. 48
Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#) .................................................. 49
Table 29: Allowed Time Before Ringback ( tDVAC) for CK - CK# and DQS - DQS# ............................................... 51
Table 30: Single-Ended Input Slew Rate Definition .......................................................................................... 52
Table 31: Differential Input Slew Rate Definition ............................................................................................. 54
Table 32: On-Die Termination DC Electrical Characteristics ............................................................................ 55
Table 33: RTT Effective Impedances ................................................................................................................ 56
Table 34: ODT Sensitivity Definition .............................................................................................................. 57
Table 35: ODT Temperature and Voltage Sensitivity ........................................................................................ 57
Table 36: ODT Timing Definitions .................................................................................................................. 58
Table 37: Reference Settings for ODT Timing Measurements ........................................................................... 58
Table 38: 34 Ohm Driver Impedance Characteristics ....................................................................................... 62
Table 39: 34 Ohm Driver Pull-Up and Pull-Down Impedance Calculations ....................................................... 63
Table 40: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.5V ................................................................ 63
Table 41: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.575V ............................................................. 63
Table 42: 34 Ohm Driver IOH/IOL Characteristics: V DD = V DDQ = 1.425V ............................................................. 64
Table 43: 34 Ohm Output Driver Sensitivity Definition .................................................................................... 64
Table 44: 34 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 64
Table 45: 40 Ohm Driver Impedance Characteristics ....................................................................................... 65
Table 46: 40 Ohm Output Driver Sensitivity Definition .................................................................................... 65
Table 47: 40 Ohm Output Driver Voltage and Temperature Sensitivity .............................................................. 66
Table 48: Single-Ended Output Driver Characteristics ..................................................................................... 67
Table 49: Differential Output Driver Characteristics ........................................................................................ 68
Table 50: Single-Ended Output Slew Rate Definition ....................................................................................... 70
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Features
Table 51:
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
Table 62:
Table 63:
Table 64:
Table 65:
Table 66:
Table 67:
Table 68:
Table 69:
Table 70:
Table 71:
Table 72:
Table 73:
Table 74:
Table 75:
Table 76:
Table 77:
Table 78:
Table 79:
Table 80:
Table 81:
Table 82:
Table 83:
Table 84:
Table 85:
Table 86:
Table 87:
Table 88:
Table 89:
Table 90:
Table 91:
Table 92:
Table 93:
Differential Output Slew Rate Definition .......................................................................................... 71
DDR3-1066 Speed Bins ................................................................................................................... 72
DDR3-1333 Speed Bins ................................................................................................................... 73
DDR3-1600 Speed Bins ................................................................................................................... 74
DDR3-1866 Speed Bins ................................................................................................................... 75
DDR3-2133 Speed Bins ................................................................................................................... 76
Electrical Characteristics and AC Operating Conditions .................................................................... 77
Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 87
Command and Address Setup and Hold Values Referenced – AC/DC-Based ...................................... 97
Derating Values for tIS/tIH – AC175/DC100-Based ............................................................................ 98
Derating Values for tIS/tIH – AC150/DC100-Based ............................................................................ 98
Derating Values for tIS/tIH – AC135/DC100-Based ............................................................................ 99
Derating Values for tIS/tIH – AC125/DC100-Based ............................................................................ 99
Minimum Required Time tVAC Above V IH(AC) or Below V IL(AC)for Valid Transition .............................. 100
DDR3 Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based ......................... 105
Derating Values for tDS/tDH – AC175/DC100-Based ........................................................................ 106
Derating Values for tDS/tDH – AC150/DC100-Based ........................................................................ 106
Derating Values for tDS/tDH – AC135/DC100-Based at 1V/ns ........................................................... 107
Derating Values for tDS/tDH – AC135/DC100-Based at 2V/ns ........................................................... 108
Required Minimum Time tVAC Above V IH(AC) (Below V IL(AC)) for Valid DQ Transition ......................... 109
Truth Table – Command ................................................................................................................. 114
Truth Table – CKE .......................................................................................................................... 116
READ Command Summary ............................................................................................................ 118
WRITE Command Summary .......................................................................................................... 118
READ Electrical Characteristics, DLL Disable Mode ......................................................................... 124
Write Leveling Matrix ..................................................................................................................... 128
Burst Order .................................................................................................................................... 137
MPR Functional Description of MR3 Bits ........................................................................................ 147
MPR Readouts and Burst Order Bit Mapping ................................................................................... 148
Self Refresh Temperature and Auto Self Refresh Description ............................................................ 180
Self Refresh Mode Summary ........................................................................................................... 180
Command to Power-Down Entry Parameters .................................................................................. 181
Power-Down Modes ....................................................................................................................... 182
Truth Table – ODT (Nominal) ......................................................................................................... 192
ODT Parameters ............................................................................................................................ 192
Write Leveling with Dynamic ODT Special Case .............................................................................. 193
Dynamic ODT Specific Parameters ................................................................................................. 194
Mode Registers for RTT,nom ............................................................................................................. 194
Mode Registers for RTT(WR) ............................................................................................................. 195
Timing Diagrams for Dynamic ODT ................................................................................................ 195
Synchronous ODT Parameters ........................................................................................................ 200
Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 205
ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 207
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
10
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
State Diagram
State Diagram
Figure 2: Simplified State Diagram
CKE L
Power
applied
MRS, MPR,
write
leveling
Initialization
Reset
procedure
Power
on
Self
refresh
SRE
ZQCL
From any
state
RESET
ZQ
calibration
MRS
SRX
REF
ZQCL/ZQCS
Refreshing
Idle
PDE
ACT
PDX
Active
powerdown
Precharge
powerdown
Activating
PDX
CKE L
CKE L
PDE
Bank
active
WRITE
WRITE
READ
WRITE AP
Writing
READ
READ AP
READ
WRITE
WRITE AP
Reading
READ AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Reading
Precharging
Automatic
sequence
Command
sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
PREA = PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
11
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Description
Functional Description
DDR3 SDRAM uses a double data rate architecture to achieve high-speed operation.
The double data rate architecture is an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write
operation for the DDR3 SDRAM effectively consists of a single 8n-bit-wide, four-clockcycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, onehalf-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
The DDR3 SDRAM operates from a differential clock (CK and CK#). The crossing of CK
going HIGH and CK# going LOW is referred to as the positive edge of CK. Control, command, and address signals are registered at every positive edge of CK. Input data is registered on the first rising edge of DQS after the WRITE preamble, and output data is referenced on the first rising edge of DQS after the READ preamble.
Read and write accesses to the DDR3 SDRAM are burst-oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVATE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with
the ACTIVATE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE commands are used to select
the bank and the starting column location for the burst access.
The device uses a READ and WRITE BL8 and BC4. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAM, the pipelined, multibank architecture of DDR3 SDRAM
allows for concurrent operation, thereby providing high bandwidth by hiding row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
Industrial Temperature
The industrial temperature (IT) device requires that the case temperature not exceed
–40°C or 95°C. JEDEC specifications require the refresh rate to double when T C exceeds
85°C; this also requires use of the high-temperature self refresh option. Additionally,
ODT resistance and the input/output impedance must be derated when T C is < 0°C or
>95°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL enable mode of operation (normal operation).
• Throughout this data sheet, various figures and text refer to DQs as “DQ.” DQ is to be
interpreted as any and all DQ collectively, unless specifically stated otherwise.
• The terms “DQS” and “CK” found throughout this data sheet are to be interpreted as
DQS, DQS# and CK, CK# respectively, unless specifically stated otherwise.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
12
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Description
• Complete functionality may be described throughout the document; any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements.
• Any specific requirement takes precedence over a general statement.
• Any functionality not specifically stated is considered undefined, illegal, and not supported, and can result in unknown operation.
• Row addressing is denoted as A[n:0]. For example, 1Gb: n = 12 (x16); 1Gb: n = 13 (x4,
x8); 2Gb: n = 13 (x16) and 2Gb: n = 14 (x4, x8); 4Gb: n = 14 (x16); and 4Gb: n = 15 (x4,
x8).
• Dynamic ODT has a special use case: when DDR3 devices are architected for use in a
single rank memory array, the ODT ball can be wired HIGH rather than routed. Refer
to the Dynamic ODT Special Use Case section.
• A x16 device's DQ bus is comprised of two bytes. If only one of the bytes needs to be
used, use the lower byte for data transfers and terminate the upper byte as noted:
–
–
–
–
Connect UDQS to ground via 1k˖* resistor.
Connect UDQS# to V DD via 1k˖* resistor.
Connect UDM to V DD via 1k˖* resistor.
Connect DQ[15:8] individually to either V SS, V DD, or V REF via 1k˖ resistors,* or float
DQ[15:8].
*If ODT is used, 1k˖ resistor should be changed to 4x that of the selected ODT.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
13
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Functional Block Diagrams
DDR3 SDRAM is a high-speed, CMOS dynamic random access memory. It is internally
configured as an 8-bank DRAM.
Figure 3: 512 Meg x 4 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQ CAL
RESET#
ZQCL, ZQCS
CKE
VSSQ
To pullup/pulldown
networks
Control
logic
A12
CK, CK#
VDDQ/2
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
18
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
15
15
Bank 0
rowaddress
32,768
latch
and
decoder
DLL
(1 . . . 4)
Bank 0
memory
array
(32,768 x 256 x 32)
32
READ
FIFO
and
data
MUX
4
DQ[3:0]
READ
drivers
VDDQ/2
32
BC4
RTT,nom
8,192
BC4
OTF
I/O gating
DM mask logic
3
18
Address
register
3
DM
(1, 2)
Columnaddress
counter/
latch
DQS, DQS#
VDDQ/2
32
Data
interface
Column
decoder
4
Data
WRITE
drivers
and
input
logic
8
RTT,nom
SW1
RTT(WR)
SW2
DM
3
Columns 0, 1, and 2
CK,CK#
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
RTT(WR)
SW2
SW1
Bank
control
logic
256
(x32)
11
DQ[3:0]
DQS, DQS#
Sense amplifiers
A[14:0]
BA[2:0]
RTT(WR)
SW2
SW1
15
Rowaddress
MUX
RTT,nom
CK,CK#
14
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Functional Block Diagrams
Figure 4: 256 Meg x 8 Functional Block Diagram
ODT
control
ODT
ZQ
ZQ CAL
RESET#
RZQ
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
CK, CK#
SW1
(1 . . . 8)
18
Bank 0
Memory
array
(32,768 x 128 x 64)
Bank 0
rowaddress
32,768
latch
and
decoder
15
15
Sense amplifiers
SW2
DLL
15
Rowaddress
MUX
64
DQ8
READ
FIFO
and
data
MUX
8
18
Address
register
DQ[7:0]
DQS, DQS#
VDDQ/2
64
BC4
OTF
RTT,nom
SW1
RTT(WR)
SW2
I/O gating
DM mask logic
3
A[14:0]
BA[2:0]
TDQS#
DQ[7:0]
Read
drivers
BC4
8,192
RTT(WR)
RTT,nom
Columns 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
(1, 2)
Bank
control
logic
3
(128
x64)
64
8
Data
interface
Data
Column
decoder
Columnaddress
counter/
latch
10
DQS/DQS#
VDDQ/2
Write
drivers
and
input
logic
RTT,nom
SW1
RTT(WR)
SW2
7
DM/TDQS
(shared pin)
3
Columns 0, 1, and 2
CK, CK#
Column 2
(select upper or
lower nibble for BC4)
Figure 5: 128 Meg x 16 Functional Block Diagram
ODT
control
ODT
ZQ
RZQ
ZQ CAL
RESET#
Control
logic
CKE
VSSQ
To ODT/output drivers
ZQCL, ZQCS
A12
VDDQ/2
CK, CK#
BC4 (burst chop)
Command
decode
CS#
RAS#
CAS#
WE#
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
OTF
Mode registers
Refresh
counter
17
14
14
Bank 0
rowaddress
latch
and
decoder
16,384
RTT(WR)
CK, CK#
SW2
SW1
DLL
(1 . . . 16)
13
Rowaddress
MUX
RTT,nom
Column 0, 1, and 2
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
memory
array
(16,384 x 128 x 128)
128
READ
FIFO
and
data
MUX
16
DQ[15:0]
READ
drivers
LDQS, LDQS#, UDQS, UDQS#
DQ[15:0]
VDDQ/2
Sense amplifiers
BC4
128
16,384
17
3
LDQS, LDQS#
I/O gating
DM mask logic
3
Address
register
Bank
control
logic
(1 . . . 4)
128
Data
interface
Column
decoder
Columnaddress
counter/
latch
16
Data
WRITE
drivers
and
input
logic
RTT,nom
SW1
RTT(WR)
SW2
7
(1, 2)
LDM/UDM
3
Columns 0, 1, and 2
CK, CK#
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
UDQS, UDQS#
VDDQ/2
(128
x128)
10
RTT(WR)
SW2
SW1
BC4
OTF
A[13:0]
BA[2:0]
RTT,nom
15
Column 2
(select upper or
lower nibble for BC4)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 6: 78-Ball FBGA – x4, x8 (Top View)
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5
VDDQ NF, DQ4
VDDQ
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
G
H
J
K
L
M
N
Notes:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. Ball descriptions listed in Table 3 (page 18) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
16
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Figure 7: 96-Ball FBGA – x16 (Top View)
A
B
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. Ball descriptions listed in Table 4 (page 20).
17
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
Type
Description
A[14:13], A12/BC#,
A11, A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE command. Address inputs are referenced
to VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during
READ and WRITE commands to determine whether burst chop (on-the-fly) will be
performed (HIGH = BL8 or no burst chop, LOW = BC4). See Table 71 (page 114).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command.
BA[2:0] are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of
CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks
idle), or active power-down (row active in any bank). CKE is synchronous for powerdown entry and exit and for self refresh entry. CKE is asynchronous for self refresh
exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF
REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the
command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with the input data during a write access.
Although the DM ball is input-only, the DM loading is designed to match that of the
DQ and DQS balls. DM is referenced to VREFDQ. DM has an optional use as TDQS on
the x8.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#,
and DM for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is
ignored if disabled via the LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ุ 0.8 × VDD and
DC LOW ื 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
18
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
Type
DQ[3:0]
I/O
Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are
referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are
referenced to VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write
data. Center-aligned to write data.
TDQS, TDQS#
Output
Termination data strobe: Applies to the x8 configuration only. When TDQS is
enabled, DM is disabled, and the TDQS and TDQS# balls provide termination
resistance.
VDD
Supply
Power supply: 1.5V ±0.075V.
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference
External reference ball for output drive calibration: This ball is tied to external
240˖ resistor RZQ, which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
NF
–
No function: When configured as a x4 device, these balls are NF. When configured
as a x8 device, these balls are defined as TDQS#, DQ[7:4].
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
Description
19
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A13, A12/BC#, A11,
A10/AP, A[9:0]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. Address inputs are referenced to
VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ
and WRITE commands to determine whether burst chop (on-the-fly) will be performed
(HIGH = BL8 or no burst chop, LOW = BC4). See Table 71 (page 114).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0]
are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or
active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,
UDQS, UDQS#, LDM, and UDM. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ุ 0.8 × VDD and DC
LOW ื 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
Description
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte
input data is masked when UDM is sampled HIGH along with that input data during a
WRITE access. Although the UDM ball is input-only, the UDM loading is designed to
match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. Center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. DQS is center-aligned to write data.
VDD
Supply
Power supply: 1.5V ±0.075V.
VDDQ
Supply
DQ power supply: 1.5V ±0.075V. Isolated on the device for improved noise immunity.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
NC
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
Reference External reference ball for output drive calibration: This ball is tied to external
240˖ resistor RZQ, which is tied to VSSQ.
–
No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Package Dimensions
Figure 8: 78-Ball FBGA – x4, x8 (DA)
0.8 ±0.05
0.155
Seating
Plane
0.12 A
1.8 CTR
Nonconductive overmold
A
78X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
9 8 7
on Ø0.35 SMD ball
pads.
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
9.6 CTR
0.8 TYP
Ball A1 ID
10.5 ±0.1
0.8 TYP
1.2 MAX
6.4 CTR
0.25 MIN
8 ±0.1
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. All dimensions are in millimeters.
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 9: 78-Ball FBGA – x4, x8 (HX)
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
78X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
A
0.12
A
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
11.5 ±0.1
9.6 CTR
J
K
L
M
N
0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. All dimensions are in millimeters.
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 10: 96-Ball FBGA – x16 (HA)
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
9
8
7
3
A
2
0.12
A
Ball A1 Index
(covered by SR)
1
Ball A1 Index
A
B
C
D
E
F
G
H
12 CTR
J
14 ±0.1
K
L
M
N
P
R
0.8 TYP
T
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. All dimensions are in millimeters.
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Package Dimensions
Figure 11: 96-Ball FBGA – x16 (JT)
0.155
Seating plane
A
1.8 CTR
Nonconductive
overmold
96X Ø0.45
Dimensions apply
to solder balls postreflow on Ø0.35
SMD ball pads.
0.12 A
Ball A1 ID
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
E
F
14 ±0.1
G
H
12 CTR
J
K
L
M
N
P
R
0.8 TYP
T
1.1 ±0.1
0.8 TYP
6.4 CTR
0.25 MIN
8 ±0.1
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. All dimensions are in millimeters.
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications
Electrical Specifications
Absolute Ratings
Stresses greater than those listed in Table 5 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 5: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
Notes
1
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VDDQ
VDD supply voltage relative to VSSQ
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
0
95
°C
2, 3
Operating case temperature - Industrial
–40
95
°C
2, 3
Operating case temperature - Automotive
–40
105
°C
2, 3
Storage temperature
–55
150
°C
TC
TSTG
Operating case temperature - Commercial
Notes:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. VDD and VDDQ must be within 300mV of each other at all times, and VREF must not be
greater than 0.6 × VDDQ. When VDD and VDDQ are 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; and IDD2Px must be derated by 30%.
Table 20: IDD Maximum Limits – Die Rev H
Speed Bin
IDD
Width
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Unit
Notes
IDD0
All
70
75
80
88
mA
1, 2
IDD1
All
90
95
100
108
mA
1, 2
IDD2P0 (Slow)
All
12
12
12
14
mA
1, 2
IDD2P1 (Fast)
All
30
35
40
48
mA
1, 2
IDD2Q
All
35
40
45
53
mA
1, 2
IDD2N
All
37
42
47
55
mA
1, 2
IDD2NT
All
45
50
55
63
mA
1, 2
IDD3P
All
40
45
50
58
mA
1, 2
IDD3N
All
45
50
55
63
mA
1, 2
IDD4R
x4
115
130
145
165
mA
1, 2
x8
130
145
160
180
mA
IDD4W
x4
115
130
145
165
mA
x8
130
145
160
180
mA
IDD5B
All
185
190
195
205
mA
1, 2
IDD6
All
12
12
12
12
mA
1, 2, 3
IDD6ET
All
15
15
15
15
mA
2, 4
IDD7
All
230
245
260
280
mA
1, 2
IDD8
All
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
1, 2
Notes:
1.
2.
3.
4.
5.
1, 2
TC = +85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC MAX = +85°C.
TC = +85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option devices when operated outside
the range 0°C ื TC ื +85°C:
5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must
be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.
5b. When TC > +85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; and IDD2Px must be derated by 30%.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Characteristics – IDD Specifications
Table 21: IDD Maximum Limits – Die Rev J, M
Speed Bin
IDD
Width
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
Unit
Notes
IDD0
All
60
65
70
75
mA
1, 2
IDD1
All
70
75
80
85
mA
1, 2
IDD2P0 (Slow)
All
12
12
12
12
mA
1, 2
IDD2P1 (Fast)
All
27
32
37
42
mA
1, 2
IDD2Q
All
30
35
40
45
mA
1, 2
IDD2N
All
33
38
43
48
mA
1, 2
IDD2NT
All
35
40
45
50
mA
1, 2
IDD3P
All
40
45
50
55
mA
1, 2
IDD3N
All
45
50
55
60
mA
1, 2
IDD4R
x4
115
126
141
156
mA
1, 2
x8
130
141
156
171
mA
IDD4W
x4
100
115
130
145
mA
x8
115
130
145
160
mA
IDD5B
All
185
190
195
200
mA
1, 2
IDD6
All
12
12
12
12
mA
1, 2, 3
IDD6ET
All
15
15
15
15
mA
2, 4
IDD7
All
210
225
240
255
mA
1, 2
IDD8
All
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
1, 2
Notes:
1.
2.
3.
4.
5.
1, 2
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC MAX = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option devices when operated outside
the range 0°C ื TC ื +85°C:
5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must
be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.
5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; and IDD2Px must be derated by 30%.
Table 22: IDD Maximum Limits – Die Rev K
Speed Bin
IDD
Widt
h
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
Notes
IDD0
x4, x8
39
41
42
43
46
mA
1, 2
x16
46
48
49
51
55
mA
x4
46
50
52
55
57
mA
x8
50
54
56
58
60
mA
x16
62
67
69
72
75
mA
IDD1
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
43
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Characteristics – IDD Specifications
Table 22: IDD Maximum Limits – Die Rev K (Continued)
Speed Bin
Widt
h
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
Notes
IDD2P0
(Slow)
All
12
12
12
12
12
mA
1, 2
IDD2P1 (Fast)
All
15
15
15
15
15
mA
1, 2
IDD
IDD2Q
All
22
22
22
22
22
mA
1, 2
IDD2N
All
23
23
23
23
23
mA
1, 2
IDD2NT
x4,x8
29
32
34
36
40
mA
1, 2
x16
33
36
37
39
43
mA
IDD3P
All
22
22
22
22
22
mA
1, 2
IDD3N
x4,x8
31
33
35
37
40
mA
1, 2
x16
33
36
37
39
43
mA
x4
70
84
96
106
120
mA
IDD4R
IDD4W
x8
74
88
100
110
125
mA
x16
95
115
135
155
180
mA
x4
75
87
99
110
122
mA
x8
79
91
103
114
126
mA
1, 2
1, 2
x16
107
127
146
164
184
mA
IDD5B
All
109
111
112
114
120
mA
1, 2
IDD6
All
12
12
12
12
12
mA
1, 2, 3
IDD6ET
All
15
15
15
15
15
mA
2, 4
x4, x8
128
157
163
171
190
mA
1, 2
x16
159
179
202
226
248
mA
All
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
IDD7
IDD8
Notes:
1.
2.
3.
4.
5.
1, 2
TC = 85°C; SRT and ASR are disabled.
Enabling ASR could increase IDDx by up to an additional 2mA.
Restricted to TC MAX = 85°C.
TC = 85°C; ASR and ODT are disabled; SRT is enabled.
The IDD values must be derated (increased) on IT-option devices when operated outside
the range 0°C ื TC ื +85°C:
5a. When TC < 0°C: IDD2P0, IDD2P1 and IDD3P must be derated by 4%; IDD4R and IDD4W must
be derated by 2%; and IDD6, IDD6ET and IDD7 must be derated by 7%.
5b. When TC > 85°C: IDD0, IDD1, IDD2N, IDD2NT, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, and IDD5B
must be derated by 2%; and IDD2Px must be derated by 30%.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Electrical Specifications – DC and AC
DC Operating Conditions
Table 23: DC Electrical Characteristics and Operating Conditions
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Unit
Notes
Supply voltage
VDD
1.425
1.5
1.575
V
1, 2
I/O supply voltage
VDDQ
1.425
1.5
1.575
V
1, 2
II
–2
–
2
μA
IVREF
–1
–
1
μA
Input leakage current
Any input 0V ื VIN ื VDD, VREF pin 0V ื VIN ื 1.1V
(All other pins not under test = 0V)
VREF supply leakage current
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
Notes:
4
1. VDD and VDDQ must track one another. VDDQ must be ื VDD. VSS = VSSQ.
2. VDD and VDDQ may include AC noise of ±50mV (250 kHz to 20 MHz) in addition to the
DC (0 Hz to 250 kHz) specifications. VDD and VDDQ must be at same level for valid AC
timing parameters.
3. VREF (see Table 24).
4. The minimum limit requirement is for testing purposes. The leakage current on the VREF
pin should be minimal.
Input Operating Conditions
Table 24: DC Electrical Characteristics and Input Conditions
All voltages are referenced to VSS
Parameter/Condition
VIN low; DC/commands/address busses
VIN high; DC/commands/address busses
Symbol
Min
Nom
Max
Unit
VIL
VSS
n/a
See Table 25
V
Notes
VIH
See Table 25
n/a
VDD
V
Input reference voltage command/address bus
VREFCA(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
1, 2
I/O reference voltage DQ bus
VREFDQ(DC)
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
2, 3
I/O reference voltage DQ bus in SELF REFRESH
VREFDQ(SR)
VSS
0.5 × VDD
VDD
V
4
VTT
–
0.5 × VDDQ
–
V
5
Command/address termination voltage
(system level, not direct DRAM input)
Notes:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFCA may not exceed
±1% × VDD around the VREFCA(DC) value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC).
2. DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the DRAM induces additional AC noise greater than 20 MHz in frequency.
3. VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC
level. Externally generated peak noise (noncommon mode) on VREFDQ may not exceed
±1% × VDD around the VREFDQ(DC) value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC).
45
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2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
4. VREFDQ(DC) may transition to VREFDQ(SR) and back to VREFDQ(DC) when in SELF REFRESH,
within restrictions outlined in the SELF REFRESH section.
5. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. Minimum and maximum values are system-dependent.
Table 25: Input Switching Conditions
Parameter/Condition
DDR3-800
DDR3-1066
Symbol
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Unit
–
mV
Command and Address
Input high AC voltage: Logic 1 @ 175mV
VIH(AC175)min
175
175
Input high AC voltage: Logic 1 @ 150mV
VIH(AC150)min
150
150
–
mV
Input high AC voltage: Logic 1 @ 135 mV
VIH(AC135)min
–
–
135
mV
Input high AC voltage: Logic 1 @ 125 mV
VIH(AC125)min
–
–
125
mV
Input high DC voltage: Logic 1 @ 100 mV
VIH(DC100)min
100
100
100
mV
Input low DC voltage: Logic 0 @ –100mV
VIL(DC100)max
–100
–100
–100
mV
Input low AC voltage: Logic 0 @ –125mV
VIL(AC125)max
–
–
–125
mV
Input low AC voltage: Logic 0 @ –135mV
VIL(AC135)max
–
–
–135
mV
Input low AC voltage: Logic 0 @ –150mV
VIL(AC150)max
–150
–150
–
mV
Input low AC voltage: Logic 0 @ –175mV
VIL(AC175)max
–175
–175
–
mV
DQ and DM
Input high AC voltage: Logic 1
VIH(AC175)min
175
–
–
mV
Input high AC voltage: Logic 1
VIH(AC150)min
150
150
–
mV
Input high AC voltage: Logic 1
VIH(AC135)min
–
–
135
mV
Input high DC voltage: Logic 1
VIH(DC100)min
100
100
100
mV
Input low DC voltage: Logic 0
VIL(DC100)max
–100
–100
–100
mV
Input low AC voltage: Logic 0
VIL(AC135)max
–
–
–135
mV
Input low AC voltage: Logic 0
VIL(AC150)max
–150
–150
–
mV
Input low AC voltage: Logic 0
VIL(AC175)max
–175
–
–
mV
Notes:
1. All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All
slew rates and setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ
and DM inputs.
2. Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
3. Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
4. Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is
900mV (peak-to-peak).
5. When two VIH(AC) values (and two corresponding VIL(AC) values) are listed for a specific
speed bin, the user may choose either value for the input AC level. Whichever value is
used, the associated setup time for that AC level must also be used. Additionally, one
VIH(AC) value may be used for address/command inputs and the other VIH(AC) value may
be used for data inputs.
For example, for DDR3-800, two input AC levels are defined: VIH(AC175),min and
VIH(AC150),min (corresponding VIL(AC175),min and VIL(AC150),min). For DDR3-800, the address/
command inputs must use either VIH(AC175),min with tIS(AC175) of 200ps or VIH(AC150),min
with tIS(AC150) of 350ps; independently, the data inputs must use either VIH(AC175),min
with tDS(AC175) of 75ps or VIH(AC150),min with tDS(AC150) of 125ps.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
46
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Figure 13: Input Signal
VIL and VIH levels with ringback
1.90V
VDDQ + 0.4V narrow
pulse width
1.50V
VDDQ
Minimum VIL and VIH levels
0.925V
0.850V
VIH(AC)
VIH(DC)
0.575V
VIH(AC)
0.850V
VIH(DC)
0.780V
0.765V
0.750V
0.735V
0.720V
0.780V
0.765V
0.750V
0.735V
0.720V
0.650V
0.925V
VIL(DC)
VIL(AC)
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
0.650V
VIL(DC)
0.575V
VIL(AC)
0.0V
VSS
VSS - 0.4V narrow
pulse width
–0.40V
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
1. Numbers in diagrams reflect nominal values.
47
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
AC Overshoot/Undershoot Specification
Table 26: Control and Address Pins
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Maximum peak amplitude allowed for overshoot area
(see Figure 14)
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 15)
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above
VDD (see Figure 14)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
0.25 Vns
Maximum undershoot area below VSS (see Figure 15)
0.67 Vns
0.5 Vns
0.4 Vns
0.33 Vns
0.28 Vns
0.25 Vns
Table 27: Clock, Data, Strobe, and Mask Pins
Parameter
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
DDR3-1866
DDR3-2133
Maximum peak amplitude allowed for overshoot area
(see Figure 14)
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum peak amplitude allowed for undershoot area
(see Figure 15)
0.4V
0.4V
0.4V
0.4V
0.4V
0.4V
Maximum overshoot area above
VDD/VDDQ (see Figure 14)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
0.10 Vns
Maximum undershoot area below VSS/VSSQ (see Figure 15)
0.25 Vns
0.19 Vns
0.15 Vns
0.13 Vns
0.11 Vns
0.10 Vns
Figure 14: Overshoot
Maximum amplitude
Overshoot area
Volts (V)
VDD/VDDQ
Time (ns)
Figure 15: Undershoot
VSS/VSSQ
Volts (V)
Undershoot area
Maximum amplitude
Time (ns)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
48
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Table 28: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Differential input voltage logic high - slew
Symbol
Min
Max
Unit
Notes
VIH,diff
200
n/a
mV
4
VIL,diff
n/a
–200
mV
4
Differential input voltage logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
5
Differential input voltage logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VIL(AC)-VREF)
mV
6
Differential input crossing voltage relative
to VDD/2 for DQS, DQS#; CK, CK#
VIX
VREF(DC) - 150
VREF(DC) + 150
mV
4, 7
Differential input crossing voltage relative
to VDD/2 for CK, CK#
VIX (175)
VREF(DC) - 175
VREF(DC) + 175
mV
4, 7, 8
VSEH
VDDQ/2 + 175
VDDQ
mV
5
VDD/2 + 175
VDD
mV
5
VSSQ
VDDQ/2 - 175
mV
6
VSS
VDD/2 - 175
mV
6
Differential input voltage logic low - slew
Single-ended high level for strobes
Single-ended high level for CK, CK#
Single-ended low level for strobes
VSEL
Single-ended low level for CK, CK#
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ.
Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.
Differential input slew rate = 2 V/ns
Defines slew rate reference points, relative to input crossing voltages.
Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable.
Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable.
The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
The VIX extended range (±175mV) is allowed only for the clock; this VIX extended range
is only allowed when the following conditions are met: The single-ended input signals
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 ±250mV, and
the differential slew rate of CK, CK# is greater than 3 V/ns.
VIX must provide 25mV (single-ended) of the voltages separation.
49
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Figure 16: VIX for Differential Signals
VDD, VDDQ
VDD, VDDQ
CK#, DQS#
CK#, DQS#
X
VIX
VIX
VDD/2, VDDQ/2
X
X
VDD/2, VDDQ/2
VIX
X
VIX
CK, DQS
CK, DQS
VSS, VSSQ
VSS, VSSQ
Figure 17: Single-Ended Requirements for Differential Signals
VDD or VDDQ
VSEH,min
VDD/2 or VDDQ/2
VSEH
CK or DQS
VSEL,max
VSEL
VSS or VSSQ
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
50
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3 SDRAM
Electrical Specifications – DC and AC
Figure 18: Definition of Differential AC-Swing and tDVAC
tDVAC
VIH,diff(AC)min
VIH,diff,min
CK - CK#
DQS - DQS#
0.0
VIL,diff,max
VIL,diff(AC)max
tDVAC
Half cycle
Table 29: Allowed Time Before Ringback (tDVAC) for CK - CK# and DQS DQS#
tDVAC
Note:
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. P 2/12 EN
(ps) at |VIH,diff(AC) to VIL,diff(AC)|
Slew Rate (V/ns)
350mV
300mV
>4.0
75
175
4.0
57
170
3.0
50
167
2.0
38
163
1.9
34
162
1.6
29
161
1.4
22
159
1.2
13
155
1.0
0
150
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