2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Description
1.35V DDR3L SDRAM Addendum
MT41K512M4 – 64 Meg x 4 x 8 banks
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L
SDRAM meet the functional and timing specifications
listed in the equivalent density DDR3 SDRAM data
sheet located on www.micron.com.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
VDD = VDDQ = +1.35V (1.283V to 1.45V)
Backward-compatible to VDD = VDDQ = +1.5V ±0.075V
Differential bidirectional data strobe
8n-bit prefetch architecture
Differential clock inputs (CK, CK#)
8 internal banks
Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
Programmable CAS (READ) latency (CL)
Programmable posted CAS additive latency (AL)
Programmable CAS (WRITE) latency (CWL)
Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
Selectable BC4 or BL8 on-the-fly (OTF)
Self refresh mode
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. H, M
– 78-ball FBGA (9mm x 11.5mm) Rev. D
• FBGA package (Pb-free) – x16
– 96-ball FBGA (9mm x 14mm) Rev. D
• Timing – cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Revision
Marking
512M4
256M8
128M16
DA
HX
HA
-125
-15E
-187E
:D/ :H/ :M
Table 1: Key Timing Parameters
Speed Grade
Data Rate (MT/s)
Target tRCD-tRP-CL
-1251, 2
1600
11-11-11
13.75
13.75
13.75
-15E1
1333
9-9-9
13.5
13.5
13.5
-187E
1066
7-7-7
13.1
13.1
13.1
Notes:
tRCD
(ns)
tRP
(ns)
CL (ns)
1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Description
Table 2: Addressing
Parameter
Configuration
Refresh count
512 Meg x 4
256 Meg x 8
128 Meg x 16
64 Meg x 4 x 8 banks
32 Meg x 8 x 8 banks
16 Meg x 16 x 8 banks
8K
8K
8K
Row address
32K A[14:0]
32K A[14:0]
16K A[13:0]
Bank address
8 BA[2:0]
8 BA[2:0]
8 BA[2:0]
2K A[11, 9:0]
1K A[9:0]
1K A[9:0]
Column address
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2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Figure 1: 78-Ball FBGA – x4, x8 Ball Assignments (Top View)
1
2
3
VSS
VDD
VSS
VDDQ
4
5
6
7
8
9
NC
NF, NF/TDQS#
VSS
VDD
VSSQ
DQ0
DM, DM/TDQS
VSSQ
VDDQ
DQ2
DQS
DQ1
DQ3
VSSQ
NF, DQ6 DQS#
VDD
VSS
VSSQ
A
B
C
D
VSSQ
E
VREFDQ
NF, DQ7 NF, DQ5
VDDQ NF, DQ4
VDDQ
F
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
A14
A8
VSS
G
H
J
K
L
M
N
Notes:
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1. Ball descriptions listed in Table 3 (page 5) are listed as “x4, x8” if unique; otherwise,
x4 and x8 are the same.
2. A comma separates the configuration; a slash defines a selectable function.
Example: D7 = NF, NF/TDQS#. NF applies to the x4 configuration only. NF/TDQS# applies
to the x8 configuration only—selectable between NF or TDQS# via MRS (symbols are defined in Table 3).
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Figure 2: 96-Ball FBGA – x16 Ball Assignments (Top View)
A
B
1
2
3
VDDQ
DQ13
VSSQ
4
5
6
7
8
9
DQ15
DQ12
VDDQ
VSS
VDD
VSS
UDQS#
DQ14
VSSQ
VDDQ
DQ11
DQ9
UDQS
DQ10
VDDQ
VSSQ
VDDQ
UDM
DQ8
VSSQ
VDD
VSS
VSSQ
DQ0
LDM
VSSQ
VDDQ
VDDQ
DQ2
LDQS
DQ1
DQ3
VSSQ
VSSQ
DQ6
LDQS#
VDD
VSS
VSSQ
VREFDQ
VDDQ
DQ4
DQ7
DQ5
VDDQ
NC
VSS
RAS#
CK
VSS
NC
ODT
VDD
CAS#
CK#
VDD
CKE
NC
CS#
WE#
A10/AP
ZQ
NC
VSS
BA0
BA2
NC
VREFCA
VSS
VDD
A3
A0
A12/BC#
BA1
VDD
VSS
A5
A2
A1
A4
VSS
VDD
A7
A9
A11
A6
VDD
VSS
RESET#
A13
NC
A8
VSS
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Notes:
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1. Ball descriptions listed in Table 4 (page 7) are listed as “x16.”
2. A comma separates the configuration; a slash defines a selectable function.
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
Type
Description
A[9:0], A10/AP,
A11, A12/BC#,
A[14:13]
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to
VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
DM
Input
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with the input data during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC
LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
DQ[3:0]
I/O
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Data input/output: Bidirectional data bus for the x4 configuration. DQ[3:0] are referenced to VREFDQ.
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2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions (Continued)
Symbol
Type
DQ[7:0]
I/O
Description
Data input/output: Bidirectional data bus for the x8 configuration. DQ[7:0] are referenced to VREFDQ.
DQS, DQS#
I/O
Data strobe: Output with read data. Edge-aligned with read data. Input with write data. Center-aligned to write data.
TDQS, TDQS#
I/O
Termination data strobe: Applies to the x8 configuration only. When TDQS is enabled,
DM is disabled, and the TDQS and TDQS# balls provide termination resistance.
VDD
Supply
Power supply: 1.35V, 1.283V to 1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V, 1.283V to 1.45V operational; compatible with 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation.
VSS
Supply
Ground.
Supply
DQ ground: Isolated on the device for improved noise immunity.
VSSQ
ZQ
Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC
–
No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
NF
–
No function: When configured as a x4 device, these balls are NF. When configured as a
x8 device, these balls are defined as TDQS#, DQ[7:4].
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2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A[9:0], A10/AP,
A11, A12/BC#, A13
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to determine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Output data strobe (LDQS, LDQS#, UDQS, UDQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is dependent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers
(excluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to
VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for external rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte input data is masked when LDM is sampled HIGH along with the input data during a write
access. Although the LDM ball is input-only, the LDM loading is designed to match that
of the DQ and LDQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#, UDQS,
UDQS#, LDM, and UDM for the x16. The ODT input is ignored if disabled via the LOAD
MODE command. ODT is referenced to VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC
LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Ball Assignments and Descriptions
Table 4: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
Type
Description
UDM
Input
Input data mask: UDM is an upper-byte, input mask signal for write data. Upper-byte
input data is masked when UDM is sampled HIGH along with the input data during a
write access. Although the UDM ball is input-only, the UDM loading is designed to match
that of the DQ and UDQS balls. UDM is referenced to VREFDQ.
DQ[7:0]
I/O
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
DQ[15:8]
I/O
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
LDQS, LDQS#
I/O
Lower byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. LDQS is center-aligned to write data.
UDQS, UDQS#
I/O
Upper byte data strobe: Output with read data. Edge-aligned with read data. Input
with write data. UDQS is center-aligned to write data.
VDD
Supply
Power supply: 1.35V, 1.283V to 1.45V operational; compatible to 1.5V operation.
VDDQ
Supply
DQ power supply: 1.35V, 1.283V to 1.45V operational; compatible with 1.5V operation.
VREFCA
Supply
Reference voltage for control, command, and address: VREFCA must be maintained
at all times (including self refresh) for proper device operation.
VREFDQ
Supply
Reference voltage for data: VREFDQ must be maintained at all times (including self refresh) for proper device operation.
VSS
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
ZQ
Reference External reference ball for output drive calibration: This ball is tied to an external
240Ω resistor (RZQ), which is tied to VSSQ.
NC
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–
No connect: These balls should be left unconnected (the ball has no connection to the
DRAM or to other balls).
8
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
Package Dimensions
Figure 3: 78-Ball FBGA – x4, x8 (DA)
0.8 ±0.05
0.155
Seating
Plane
0.12 A
1.8 CTR
Nonconductive overmold
A
78X Ø0.45
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
9 8 7
on Ø0.35 SMD ball
pads.
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
J
K
L
M
N
9.6 CTR
0.8 TYP
Ball A1 ID
10.5 ±0.1
0.8 TYP
1.2 MAX
6.4 CTR
0.25 MIN
8 ±0.1
Note:
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1. All dimensions are in millimeters.
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
Figure 4: 78-Ball FBGA – x4, x8; Die Rev. D (HX)
0.155
Seating plane
1.8 CTR
Nonconductive
overmold
78X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
A
0.12
A
Ball A1 ID
9 8 7
Ball A1 ID
3 2 1
A
B
C
D
E
F
G
H
11.5 ±0.1
9.6 CTR
J
K
L
M
N
0.8 TYP
0.8 TYP
1.1 ±0.1
6.4 CTR
0.25 MIN
9 ±0.1
Notes:
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
1. All dimensions are in millimeters.
2. Solder ball material: SAC305 (96.5% SN, 3% Ag, 0.5% Cu).
10
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Package Dimensions
Figure 5: 96-Ball FBGA – x16; Die Rev. D (HA)
0.8 ±0.1
Seating
plane
0.12 A
A
96X Ø0.45
Solder ball
material: SAC305.
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
Ball A1 ID
9
8
7
3
2
Ball A1 ID
1
A
B
C
D
E
F
G
H
12 CTR
J
14 ±0.15
K
L
M
N
P
R
0.8 TYP
T
0.8 TYP
1.2 MAX
6.4 CTR
0.25 MIN
9 ±0.15
Note:
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1. All dimensions are in millimeters.
11
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
Electrical Characteristics – IDD Specifications
Table 5: IDD Maximum Limits – Rev. D
Speed Bin
IDD
Width
DDR3L-800
DDR3L-1066
DDR3L-1333
Units
IDD0
x4, 8
70
x16
85
75
85
mA
90
100
mA
x4, 8
92
95
100
mA
x16
122
125
130
mA
IDD2P0
All
12
12
12
mA
IDD2P1
x4, 8
22
25
30
mA
x16
27
30
35
mA
All
27
30
35
mA
IDD2N
All
28
32
37
mA
IDD2NT
x4, 8
37
40
45
mA
x16
52
55
60
mA
x4, 8
27
30
35
mA
IDD1
IDD2Q
IDD3P
x16
32
35
40
mA
IDD3N
All
32
35
40
mA
IDD4R
x4
110
125
145
mA
x8
125
140
160
mA
x16
160
200
245
mA
x4
120
135
155
mA
x8
130
145
165
mA
x16
170
210
255
mA
IDD5B
All
185
190
200
mA
IDD6
All
12
12
12
mA
IDD6ET
All
15
15
15
mA
IDD7
x4, 8
290
335
385
mA
IDD4W
IDD8
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x16
330
375
425
mA
All
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
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2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
Table 6: IDD Maximum Limits – Die Rev H
Speed Bin
IDD
Width
DDR3L-1066
DDR3L-1333
DDR3L-1600
Unit
IDD0
x4, 8
65
70
75
mA
IDD1
x4, 8
85
90
95
mA
IDD2P0 (Slow)
x4, 8
12
12
12
mA
IDD2P1 (Fast)
x4, 8
27
32
37
mA
IDD2Q
x4, 8
32
37
42
mA
IDD2N
x4, 8
34
38
43
mA
IDD2NT
x4, 8
42
47
52
mA
IDD3P
x4, 8
37
42
47
mA
IDD3N
x4, 8
42
47
52
mA
IDD4R
x4
110
125
140
mA
x8
125
140
155
mA
IDD4W
x4
110
125
140
mA
x8
125
140
155
mA
IDD5B
x4, 8
180
185
190
mA
IDD6
x4, 8
12
12
12
mA
IDD6ET
x4, 8
15
15
15
mA
IDD7
x4, 8
225
240
255
mA
IDD8
x4, 8
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
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© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Characteristics – IDD Specifications
Table 7: IDD Maximum Limits – Die Rev M
Speed Bin
IDD
Width
DDR3L-1066
DDR3L-1333
DDR3L-1600
Unit
IDD0
x4, 8
50
55
60
mA
IDD1
x4, 8
65
70
75
mA
IDD2P0 (Slow)
x4, 8
12
12
12
mA
IDD2P1 (Fast)
x4, 8
23
28
33
mA
IDD2Q
x4, 8
23
28
33
mA
IDD2N
x4, 8
25
30
35
mA
IDD2NT
x4, 8
30
35
40
mA
IDD3P
x4, 8
37
42
47
mA
IDD3N
x4, 8
42
47
52
mA
IDD4R
x4
95
110
125
mA
x8
110
125
140
mA
IDD4W
x4
85
100
115
mA
x8
95
110
125
mA
IDD5B
x4, 8
180
185
190
mA
IDD6
x4, 8
12
12
12
mA
IDD6ET
x4, 8
15
15
15
mA
IDD7
x4, 8
190
205
220
mA
IDD8
x4, 8
IDD2P0 + 2mA
IDD2P0 + 2mA
IDD2P0 + 2mA
mA
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
Electrical Specifications
Table 8: Input/Output Capacitance
Gray-shaded cells have the same values as those in the 1.5V DDR3 data sheet
DDR3L-800
DDR3L-1066
Capacitance Parame-
DDR3L-1333
DDR3L-1600
ters
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
s
Single-end I/O: DQ, DM
CIO
1.5
2.5
1.5
2.5
1.5
2.3
1.5
2.3
pF
Differential I/O: DQS,
DQS#, TDQS, TDQS#
CIO
1.5
2.5
1.5
2.5
1.5
2.3
1.5
2.3
pF
Inputs (CTRL,
CMD,ADDR)
CI
0.75
1.3
0.75
1.3
0.75
1.3
0.75
1.3
pF
Table 9: DC Electrical Characteristics and Operating Conditions – 1.35V Operation
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDD
1.283
1.35
1.45
V
1, 2, 3, 4
I/O supply voltage
VDDQ
1.283
1.35
1.45
V
1, 2, 3, 4
Notes:
1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average
of VDD/VDDQ(t) over a very long period of time (e.g., 1 sec).
2. If the maximum limit is exceeded, input levels shall be governed by DDR3 specifications.
3. Under these supply voltages, the device operates to this DDR3L specification.
4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3 operation (see Figure 6 (page 23)).
Table 10: DC Electrical Characteristics and Operating Conditions – 1.5V Operation
All voltages are referenced to VSS
Parameter/Condition
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDD
1.425
1.5
1.575
V
1, 2, 3
I/O supply voltage
VDDQ
1.425
1.5
1.575
V
1, 2, 3
Notes:
1. If the minimum limit is exceeded, input levels shall be governed by DDR3L specifications.
2. Under 1.5V operation, this DDR3L device operates in accordance with the DDR3 specifications under the same speed timings as defined for this device.
3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is
in reset while VDD and VDDQ are changed for DDR3L operation (see Figure 6 (page 23)).
Table 11: Input Switching Conditions – Command and Address
Parameter/Condition
Symbol
DDR3L-800/1066
DDR3L-1333/1600
Units
Input high AC voltage: Logic 1
VIH(AC160)min
160
160
mV
Input high AC voltage: Logic 1
VIH(AC135)min
135
135
mV
Input high DC voltage: Logic 1
VIH(DC90)min
90
90
mV
Input low AC voltage: Logic 0
VIL(AC160)min
–160
–160
mV
Input low AC voltage: Logic 0
VIL(AC135)min
–135
–135
mV
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2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
Table 11: Input Switching Conditions – Command and Address (Continued)
Parameter/Condition
Input low DC voltage: Logic 0
Symbol
DDR3L-800/1066
DDR3L-1333/1600
Units
VIL(DC90)min
–90
–90
mV
Table 12: Input Switching Conditions – DQ and DM
Parameter/Condition
Symbol
DDR3L-800/1066
DDR3L-1333/1600
Units
Input high AC voltage: Logic 1
VIH(AC160)min
160
–
mV
Input high AC voltage: Logic 1
VIH(AC135)min
135
135
mV
Input high DC voltage: Logic 1
VIH(DC90)min
90
90
mV
Input low AC voltage: Logic 0
VIL(AC160)min
–160
–
mV
Input low AC voltage: Logic 0
VIL(AC135)min
–135
–135
mV
Input low DC voltage: Logic 0
VIL(DC90)min
–90
–90
mV
Table 13: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)
Parameter/Condition
Symbol
Min
Max
Units
Differential input logic high – slew
VIH,diff(AC)slew
180
N/A
mV
Differential input logic low – slew
VIL,diff(AC)slew
N/A
–180
mV
Differential input logic high
VIH,diff(AC)
2 × (VIH(AC) - VREF)
VDD/VDDQ
mV
Differential input logic low
VIL,diff(AC)
VSS/VSSQ
2 × (VREF - VIL(AC))
mV
VSEH
VDDQ/2 + 160
VDDQ
mV
VDD/2 + 160
VDD
mV
VSSQ
VDDQ/2 - 160
mV
VSS
VDD/2 - 160
mV
Single-ended high level for strobes
Single-ended high level for CK, CK#
Single-ended low level for strobes
VSEL
Single-ended low level for CK, CK#
Table 14: Required Time tDVAC for CK/CK#, DQS/DQS# Differential for AC Ringback
Slew Rate (V/ns)
tDVAC
at 320mV (ps)
tDVAC
at 270mV (ps)
>4.0
70
209
4.0
53
198
3.0
47
194
2.0
35
186
1.8
31
184
1.6
26
181
1.4
20
177
1.2
12
171
1.0
0
164
2.0
70
209
2.0
53
198
1.5
47
194
1.0
35
186
0.9
31
184
0.8
26
181
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. E 1/11 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
2Gb: x4, x8, x16 DDR3L SDRAM Addendum
Electrical Specifications
Table 24: Required Time tVAC Above VIH(AC) (Below VIL[AC]) for Valid ADD/CMD Transition (Continued)
tVAC
Slew Rate (V/ns)
tVAC
at 160mV (ps)
at 135mV (ps)
0.7
20
177
0.6
12
171
0.5
0
164
2.0
70
109
2.0
53
98
1.5
47
94
1.0
35
86
0.9
31
84
0.8
26
81
0.7
20
77
0.6
12
71
0.5
0
64
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