1Gb: x4, x8, x16 DDR2 SDRAM
Features
DDR2 SDRAM
MT47H256M4 – 32 Meg x 4 x 8 banks
MT47H128M8 – 16 Meg x 8 x 8 banks
MT47H64M16 – 8 Meg x 16 x 8 banks
For the latest data sheet, refer to Micron’s Web site: http://www.micron.com/ddr2
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Options
RoHS compliant
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS#) option
4-bit prefetch architecture
Duplicate output strobe (RDQS) option for x8
DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL)
Posted CAS additive latency (AL)
WRITE latency = READ latency – 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength
64ms, 8,192-cycle refresh
On-die termination (ODT)
Industrial temperature (IT) option
Supports JEDEC clock jitter specification
Table 1:
Table 2:
Configuration Addressing
Architecture
256 Meg x 4 128 Meg x 8 64 Meg x 16
32 Meg x 4
16 Meg x 4
x 8 banks
x 8 banks
8K
8K
Refresh Count
16K (A0–A13) 16K (A0–A13)
Row Addr.
8 (BA0–BA2) 8 (BA0–BA2)
Bank Addr.
Column Addr. 2K (A0–A9, A11) 1K (A0–A9)
Configuration
Marking
• Configuration
256 Meg x 4 (32 Meg x 4 x 8 banks )
128 Meg x 8 (16 Meg x 8 x 8 banks)
64 Meg x 16 (8 Meg x 16 x 8 banks)
• FBGA package (lead-free)
92-ball FBGA (11mm x 19mm) (:A)
84-ball FBGA (10mm x 16.5mm) (:D)
68-ball FBGA (10mm x 16.5mm) (:D)
• Timing – cycle time
5.0ns @ CL = 3 (DDR2-400)
3.75ns @ CL = 4 (DDR2-533)
3.0ns @ CL = 5 (DDR2-667)
3.0ns @ CL = 4 (DDR2-667)
2.5ns @ CL = 6 (DDR2-800)
2.5ns @ CL = 5 (DDR2-800)
• Self refresh
Standard
Low-power
• Operating temperature
Commercial (0°C ≤ TC ≤ 85°C)
Industrial (–40°C ≤ TC ≤ 95°C; –40°C ≤ TA ≤ 85°C)
• Revision
256M4
128M8
64M16
BT
B7
B7
-5E
-37E
-3
-3E
-25
-25E
None
L
None
IT
:A/:D
Key Timing Parameters
Data Rate (MHz)
t
Speed
RCD tRP
Grade CL = 3 CL = 4 CL = 5 CL = 6 (ns) (ns)
8 Meg x 16
x 8 banks
8K
8K (A0–A12)
8 (BA0–BA2)
1K (A0–A9)
-5E
-37E
-3
-3E
-25
-25E
400
400
400
N/A
N/A
N/A
400
533
533
667
N/A
533
N/A
N/A
667
667
667
800
N/A
N/A
N/A
N/A
800
N/A
15
15
15
12
15
12.5
15
15
15
12
15
12.5
t
RC
(ns)
55
55
55
54
55
55
Note: CL = CAS latency.
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbbDDR2_1.fm - Rev. K 4/06 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Industrial Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
General Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Assignment and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
DLL RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Extended Mode Register (EMR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
DQS# Enable/Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
RDQS Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
On-Die Termination (ODT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Off-Chip Driver (OCD) Impedance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Extended Mode Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Extended Mode Register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DESELECT, NOP, and LM Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
WRITE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
PRECHARGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
SELF REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Precharge Power-Down Clock Frequency Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
RESET Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
(CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2TOC.fm - Rev. K 4/06 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Input Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Input Slew Rate Derating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
AC Overshoot/Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Output Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Full Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Full Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reduced Strength Pull-Down Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Reduced Strength Pull-Up Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
FBGA Package Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
IDD7 Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
AC Operating Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2TOC.fm - Rev. K 4/06 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
List of Figures
List of Figures
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1Gb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
84-Ball FBGA (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
68-Ball FBGA (x4, x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
92-Ball FBGA (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
92-Ball FBGA (x4/x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Functional Block Diagram – 64 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Functional Block Diagram – 128 Meg x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Functional Block Diagram – 256 Meg x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DDR2 Power-up and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WRITE Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Extended Mode Register 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Extended Mode Register 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
8-Bank Activate Restriction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
READ Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
READ Interrupted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
READ-to-PRECHARGE – BL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
READ-to-PRECHARGE – BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Bank Read – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Bank Read – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Data Output Timing – tAC and tDQSCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Nonconsecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
WRITE-to-PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Bank Write – without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Bank Write – with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WRITE – DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
READ to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
READ with Auto Precharge to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
WRITE to Power-Down or Self-Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
WRITE with Auto Precharge to Power-Down or Self Refresh Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
REFRESH Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
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4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
List of Figures
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LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Input Clock Frequency Change During Precharge Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . .76
RESET Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
ODT Timing for Entering and Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Timing for MRS Command to ODT Update Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
ODT Timing for Active or Fast-Exit Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
ODT Timing for Slow-Exit or Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
ODT Turn-off Timings When Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
ODT Turn-On Timing When Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
ODT Turn-Off Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
ODT Turn-on Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Single-Ended Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Differential Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
Nominal Slew Rate for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
Tangent Line for tIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
Nominal Slew Rate for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
Tangent Line for tIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Nominal Slew Rate for tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Tangent Line for tDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Nominal Slew Rate for tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Tangent Line for tDH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
AC Input Test Signal Waveform Command/Address Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) . . . . . . . . . . . . . . . . . . . . . 107
AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . 108
AC Input Test Signal Waveform (differential) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Overshoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Output Slew Rate Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Full Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Full Strength Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reduced Strength Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Reduced Strength Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
84-Ball FBGA Package – 10mm x 16.5mm (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
68-Ball FBGA Package – 10mm x 16.5mm (x4/x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
92-Ball FBGA Package – 11mm x 19mm (x4/x8/x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
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5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
List of Tables
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Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
84-/68-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Truth Table – DDR2 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Truth Table – Current State Bank n – Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Truth Table – Current State Bank n – Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Minimum Delay with Auto Precharge Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
READ Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
WRITE Using Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes . . . . . . . . . . . . . . . . . . . . .81
DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes . . . . . . . . . . . . . . . . .82
DDR2-400/533 ODT Turn-off Timings When Entering Power-Down Mode. . . . . . . . . . . . . . . . . . . . .83
DDR2-400/533 ODT Turn-on Timing When Entering Power-Down Mode. . . . . . . . . . . . . . . . . . . . . .84
DDR2-400/533 ODT Turn-off Timing When Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . .85
DDR2-400/533 ODT Turn-On Timing When Exiting Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . .86
Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
Recommended DC Operating Conditions (SSTL_18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
DDR2-667 Setup and Hold Time Derating Values (tIS and tIH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
DDR2-400/533 tDS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
DDR2-667 tDS, tDH Derating Values with Differential Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb . . . . . . . . . . . . . . . . . . . . . . . . . 101
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667 . . . . . . . . . . . . . . . . . 101
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533 . . . . . . . . . . . . . . . . . 102
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400 . . . . . . . . . . . . . . . . . 102
Input Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Address and Control Balls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Clock, Data, Strobe, and Mask Balls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Output Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Full Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Full Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Reduced Strength Pull-Down Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Reduced Strength Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
DDR2 IDD Specifications and Conditions (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
General IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
IDD7 Timing Patterns (8-bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
AC Operating Conditions for -25E and -25 Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
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1GbDDR2LOT.fm - Rev. K 4/06 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Part Numbers
Part Numbers
Figure 1:
1Gb DDR2 Part Numbers
Example Part Number: M T47H 128M 8B 7- 37E : D
Configuration
Package
:
Speed
Revision
{
MT47H
:A/:D Revision
Configuration
256 Meg x 4
256M4
128 Meg x 8
128M8
L
64M16
IT Industrial Temperature
64 Meg x 16
Package
92-Ball 11mm x 19mm FBGA
BT
-5E
Speed Grade
tCK = 5ns, CL = 3
84-Ball 10mm x 16.5mm FBGA
B7
-37E
tCK = 3.75ns, CL = 4
68-Ball 10mm x 16.5mm FBGA
B7
-3
-3E
-25
-25E
Note:
Low-Power
tCK = 3ns, CL = 5
tCK = 3ns, CL = 4
tCK = 2.5ns, CL = 6
tCK = 2.5ns, CL = 5
Not all speeds and configurations are available. Contact Micron sales for current revision.
FBGA Part Marking Decoder
Due to space limitations, FBGA-packaged components have an abbreviated part
marking that is different from the part number. Micron’s FBGA Part Marking Decoder is
available at www.micron.com/decoder.
General Description
The 1Gb DDR2 SDRAM is a high-speed CMOS, dynamic random access memory
containing 1,073,741,824 bits. It is internally configured as an 8-bank DRAM. The functional block diagrams of the all device configurations are shown in “Functional Description” on page 18. Ball assignments and signal descriptions are shown in “Ball
Assignment and Description” on page 9.
The 1Gb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an
interface designed to transfer two data words per clock cycle at the I/O balls. A single
read or write access for the 1Gb DDR2 SDRAM effectively consists of a single 4n-bitwide, one-clock-cycle data transfer at the internal DRAM core and four corresponding
n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.
A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM
during READs and by the memory controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs. The x16 offering has two data
strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS,
UDQS#).
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1GbDDR2_2.fm - Rev. K 4/06 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
General Description
The 1Gb DDR2 SDRAM operates from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands (address and control signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and output data is referenced to both
edges of DQS as well as to both edges of CK.
Read and write accesses to the DDR2 SDRAM are burst-oriented; accesses start at a
selected location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed. The address bits
registered coincident with the READ or WRITE command are used to select the bank and
the starting column location for the burst access.
The DDR2 SDRAM provides for programmable read or write burst lengths of four or
eight locations. DDR2 SDRAM supports interrupting a burst read of eight with another
read or a burst write of eight with another write. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
access.
As with standard DDR SDRAMs, the pipelined, multibank architecture of DDR2 SDRAMs
allows for concurrent operation, thereby providing high, effective bandwidth by hiding
row precharge and activation time.
A self refresh mode is provided, along with a power-saving, power-down mode.
All inputs are compatible with the JEDEC standard for SSTL_18. All full drive-strength
outputs are SSTL_18-compatible.
Industrial Temperature
The industrial temperature (IT) device has two simultaneous requirements: ambient
temperature surrounding the device cannot exceed –40°C or +85°C, and the case
temperature cannot exceed –40°C or 95°C. JEDEC specifications require the refresh rate
to double when TC exceeds 85°C; this also requires use of the high-temperature self
refresh option. Additionally, ODT resistance and the input/output impedance must be
derated when the TC is < 0°C or > 85°C.
General Notes
• The functionality and the timing specifications discussed in this data sheet are for the
DLL-enabled mode of operation.
• Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ
term is to be interpreted as any and all DQ collectively, unless specifically stated
otherwise. Additionally, the x16 is divided into 2 bytes, the lower byte and upper byte.
For the lower byte (DQ0–DQ7), DM refers to LDM and DQS refers to LDQS. For the
upper byte (DQ8–DQ15), DM refers to UDM and DQS refers to UDQS.
• Complete functionality is described throughout the document, and any page or
diagram may have been simplified to convey a topic and may not be inclusive of all
requirements.
• Any specific requirement takes precedence over a general statement.
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1GbDDR2_2.fm - Rev. K 4/06 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Ball Assignment and Description
Figure 2:
84-Ball FBGA (x16)
10mm x 16.5mm (top view)
A
B
C
D
E
F
G
H
J
1
2
3
4
5
6
7
8
9
VDD
NC
VSS
DQ14
VSSQ
UDM
UDQS
VSSQ
DQ15
VDDQ
DQ9
VDDQ
VDDQ
DQ8
VDDQ
DQ12
VSSQ
DQ11
DQ10
VSSQ
DQ13
VDD
NC
VSS
DQ6
VSSQ
LDM
LDQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
A12
RFU
RFU
RFU
VSSQ UDQS#/NU VDDQ
VSSQ LDQS#/NU VDDQ
K
L
RFU
M
VDD
N
VSS
P
VSS
R
VDD
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1GbDDR2_2.fm - Rev. K 4/06 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Figure 3:
68-Ball FBGA (x4, x8)
10mm x 16.5mm (top view)
1
2
NC
NC
3
4
5
6
7
8
9
NC
NC
A
B
C
D
E
VDD NU/RDQS#
VSSQ DQS#/NU VDDQ
VSS
F
NF, DQ6 VSSQ DM/RDQS
DQS
VDDQ DQ1 VDDQ
VDDQ
VSSQ NF,DQ7
G
DQ0
VDDQ
H
NF, DQ4 VSSQ
DQ3
DQ2
VSSQ NF, DQ5
VREF
VSS
VSSDL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
VDD
A12
RFU
RFU
A13
NC
NC
J
VDDL
K
L
BA2
M
VDD
N
VSS
P
VSS
R
T
U
V
W
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1GbDDR2_2.fm - Rev. K 4/06 EN
NC
10
NC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 3:
84-/68-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16
x16 Ball
Number
x4, x8 Ball
Number
Symbol
K9
K9
ODT
J8, K8
J8, K8
CK, CK#
K2
K2
CKE
L8
L8
CS#
K7, L7,
K3
F3, B3
K7, L7,
K3
F3
RAS#, CAS#,
WE#
LDM, UDM
(DM)
L2, L3, L1
L2, L3, L1
BA0–BA2
M8, M3, M7,
N2, N8, N3,
N7, P2,
P8, P3, M2,
P7, R2
M8, M3, M7,
N2, N8, N3,
N7, P2,
P8, P3, M2,
P7, R2
R8
A0–A2,
A3–A5,
A6–A7,
A8–A10,
A11–A12
A13 (x4, x8)
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1GbDDR2_2.fm - Rev. K 4/06 EN
Type Description
Input On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is only
applied to each of the following balls: DQ0–DQ15, LDM, UDM, LDQS,
LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7, DQS, DQS#, RDQS,
RDQS#, and DM for the x8; DQ0–DQ3, DQS, DQS#, and DM for the
x4. The ODT input will be ignored if disabled via the LOAD MODE
command.
Input Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive edge
of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is
referenced to the crossings of CK and CK#.
Input Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The specific
circuitry that is enabled/disabled is dependent on the DDR2 SDRAM
configuration and operating mode. CKE LOW provides precharge
power-down mode and SELF REFRESH operation (all banks idle), or
active power-down (row active in any bank). CKE is synchronous for
power-down entry, power-down exit, output disable, and for self
refresh entry. CKE is asynchronous for SELF REFRESH exit. Input
buffers (excluding CK, CK#, CKE, and ODT) are disabled during
power-down. Input buffers (excluding CKE) are disabled during self
refresh. CKE is an SSTL_18 input but will detect a LVCMOS LOW level
once VDD is applied during first power-up. After VREF has become
stable during the power on and initialization sequence, it must be
maintained for proper operation of the CKE receiver. For proper SELF
REFRESH operation, VREF must be maintained.
Input Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH. CS# provides for external bank selection on systems
with multiple ranks. CS# is considered part of the command code.
Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.
Input Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of DQ
and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM
for upper byte DQ8–DQ15.
Input Bank address inputs: BA0–BA2 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–BA2
define which mode register, including MR, EMR, EMR(2), and EMR(3),
is loaded during the LOAD MODE command.
Input Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective bank. A10 sampled during a PRECHARGE command
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA2–BA0) or all banks (A10 HIGH). The address
inputs also provide the op-code during a LOAD MODE command.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 3:
x16 Ball
Number
84-/68-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16 (Continued)
x4, x8 Ball
Number
Symbol
G8, G2, H7, H3,
–
DQ0–DQ3,
H1, H9, F1, F9,
DQ4–DQ7,
C8, C2, D7,
DQ8–DQ10,
D3, D1, D9,
DQ11–DQ13,
B1, B9
DQ14–DQ15
–
G8, G2, H7, H3, DQ0–DQ3
H1, H9, F1, F9
DQ4–DQ7
–
G8, G2, H7, H3 DQ0–DQ2
DQ3
B7
–
UDQS,
A8
UDQS#
F7
E8
–
–
Type Description
I/O
Data input/output: Bidirectional data bus for 64 Meg x 16.
I/O
Data input/output: Bidirectional data bus for 128 Meg x 8.
I/O
Data input/output: Bidirectional data bus for 256 Meg x 4.
I/O
Data strobe for upper byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. UDQS# is only used when differential
data strobe mode is enabled via the LOAD MODE command.
–
LDQS, LDQS#
I/O Data strobe for lower byte: Output with read data, input with write
data for source synchronous operation. Edge-aligned with read data,
center-aligned with write data. LDQS# is only used when differential
data strobe mode is enabled via the LOAD MODE command.
F7, E8
DQS, DQS#
I/O Data strobe: Output with read data, input with write data for source
synchronous operation. Edge-aligned with read data, center-aligned
with write data. DQS# is only used when differential data strobe
mode is enabled via the LOAD MODE command.
F3, E2
RDQS, RDQS# Output Redundant data strobe for 128 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the extended mode
register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is disabled,
ball F3 becomes data mask (see DM ball). RDQS# is only used when
RDQS is enabled and differential data strobe mode is enabled.
E1, J9, M9, R1
VDD
Supply Power supply: 1.8V ±0.1V.
A1, E1, J9, M9,
R1
J1
J1
A9, C1, C3, C7, E9, G1, G3, G7,
C9, E9, G1, G3,
G9
G7, G9
J2
J2
A3, E3, J3, N1, J3, E3, N1, P9
P9
J7
J7
A7, B2, B8, D2, E7, F2, F8, H2,
D8, E7, F2, F8,
H8
H2, H8
A2, E2
W1, W2, W8,
W9, A1, A2,
A8, A9
A8, E8
–
VDDL
VDDQ
VREF
VSS
VSSDL
VSSQ
Supply DLL power supply: 1.8V ±0.1V.
Supply DQ power supply: 1.8V ±0.1V. Isolated on the device for improved
noise immunity.
Supply SSTL_18 reference voltage.
Supply Ground.
Supply DLL ground. Isolated on the device from VSS and VSSQ.
Supply DQ ground. Isolated on the device for improved noise immunity.
NC
–
No connect: These balls should be left unconnected.
NU
–
–
E2, E8
NU
–
–
F1, F9, H1, H9,
E2
R3, R7
NF
–
Not used: Not used only on x16. If EMR[E10] = 0, A8 and E8 are
UDQS# and LDQS#. If EMR[E10] = 1, then A8 and E8 are not used.
Not used: Not used only on x8. If EMR[E10] = 0, E2 and E8 are RDQS#
and DQS#. If EMR[E10] = 1, then E2 and E8 are not used.
Not funtion: Not used only on x4. These are data lines on the x8.
RFU
–
Reserved for future use: Row address bits A14 (R3) and A13 (R8).
R8, R3, R7
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Figure 4:
92-Ball FBGA (x16)
11mm x 19mm top (view)
1
2
3
4
5
6
7
8
9
NC
NC
NC
NC
VDD
NC
VSS
DQ14
VSSQ
UDM
UDQS
VSSQ
DQ15
VDDQ
DQ9
VDDQ
VDDQ
DQ8
VDDQ
DQ12
VSSQ
DQ11
DQ10
VSSQ
DQ13
VDD
NC
VSS
DQ6
VSSQ
LDM
LDQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
VSSDL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
VDD
A12
RFU
RFU
RFU
NC
NC
A
B
C
D
VSSQ UDQS#/NU VDDQ
E
F
G
H
VSSQ LDQS#/NU VDDQ
J
K
L
M
N
P
BA2
R
VDD
T
VSS
U
VSS
V
W
Y
AA
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
NC
13
NC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Figure 5:
92-Ball FBGA (x4/x8)
11mm x 19mm top (view)
1
2
3
NC
NC
V DD
NC
V SS
NC
NC
NC
NC
4
5
6
7
8
9
NC
NC
V SS Q
NC
V DD Q
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
G
H
V DD
NF, RDQS#/NU
V SS Q DQS#/NU
V SS
V DD Q
J
NF, DQ6
V SS Q DM/RDQS
DQS
V SS Q
NF, DQ7
V DD Q
DQ1
VDDQ
V DD Q
DQ0
V DD Q
NF,DQ 4
V SS Q
DQ3
DQ2
V SS Q
NF, DQ5
VDD L
V REF
V SS
V SS DL
CK
VDD
CKE
WE#
RAS#
CK#
ODT
BA0
BA1
CAS#
CS#
A10
A1
A2
A0
A3
A5
A6
A4
A7
A9
A11
A8
V DD
A12
RFU
RFU
A13
NC
NC
K
L
M
N
P
BA2
R
V DD
T
V SS
U
V SS
V
W
Y
AA
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1GbDDR2_2.fm - Rev. K 4/06 EN
NC
14
NC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 4:
92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16
x16 Ball
Number
x4, x8 Ball
Number
Symbol
Type
Description
N9
N9
ODT
Input
M8, N8
M8, N8
CK, CK#
Input
N2
N2
CKE
Input
P8
P8
CS#
Input
N7, P7,
N3
J3, E3
N7, P7,
N3
Input
J3
RAS#, CAS#,
WE#
LDM, UDM,
(DM)
P2, P3, P1
P2, P3, P1
BA0–BA2
Input
R8, R3, R7,
T2, T8, T3, T7,
U2, U8, U3,
R2, U7, V2
–
A0–A2,
A3–A6,
A7–A9,
A10–A12
Input
On-die termination: ODT (registered HIGH) enables termination
resistance internal to the DDR2 SDRAM. When enabled, ODT is
only applied to each of the following balls: DQ0–DQ15, LDM,
UDM, LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0–DQ7,
DQS, DQS#, RDQS, RDQS#, and DM for the x8; DQ0–DQ3, DQS,
DQS#, and DM for the x4. The ODT input will be ignored if
disabled via the LOAD MODE command.
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and DQS/
DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered
LOW) deactivates clocking circuitry on the DDR2 SDRAM. The
specific circuitry that is enabled/disabled is dependent on the
DDR2 SDRAM configuration and operating mode. CKE LOW
provides precharge power-down mode and SELF REFRESH
operation (all banks idle), or active power-down (row active in any
bank). CKE is synchronous for power-down entry, power-down
exit, output disable, and self refresh entry. CKE is asynchronous for
SELF REFRESH exit. Input buffers (excluding CK, CK#, CKE, and
ODT) are disabled during power-down. Input buffers (excluding
CKE) are disabled during self refresh. CKE is an SSTL_18 input but
will detect a LVCMOS LOW level once VDD is applied during first
power-up. After VREF has become stable during the power on and
initialization sequence, it must be maintained for proper
operation of the CKE receiver. For proper SELF REFRESH operation,
VREF must be maintained.
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS#
is registered HIGH. CS# provides for external bank selection on
systems with multiple ranks. CS# is considered part of the
command code.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define
the command being entered.
Input data mask: DM is an input mask signal for write data. Input
data is masked when DM is concurrently sampled HIGH during a
WRITE access. DM is sampled on both edges of DQS. Although DM
balls are input-only, the DM loading is designed to match that of
DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is
DM for upper byte DQ8–DQ15.
Bank address inputs: BA0–BA2 define to which bank an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied. BA0–BA2
define which mode register including MR, EMR, EMR(2), and
EMR(3) is loaded during the LOAD MODE command.
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD
MODE command.
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1GbDDR2_2.fm - Rev. K 4/06 EN
Input
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 4:
92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16
x16 Ball
Number
x4, x8 Ball
Number
Symbol
Type
Description
–
R8, R3, R7, T2,
T8, T3, T7, U2,
U8, U3, R2,
U7, V2, V8
A0–A3,
A4–A7,
A8–A10,
A11–A13
Input
I/O
Address inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory array
in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
bank (A10 LOW, bank selected by BA2–BA0) or all banks (A10
HIGH). The address inputs also provide the op-code during a LOAD
MODE command.
Data input/output: Bidirectional data bus for 64 Meg x 16.
I/O
Data input/output: Bidirectional data bus for 128 Meg x 8.
K8, K2, L7, L3,
–
DQ0–DQ3,
L1, L9, J1, J9,
DQ4–DQ7,
F8, F2, G7,
DQ8–DQ10,
G3, G1, G9,
DQ11–DQ13,
E1, E9
DQ14–DQ15
–
K8, K2, L7, L3, DQ0–DQ3,
L1, L9, J1, J9
DQ4–DQ7
–
K8, K2, L7, L3
DQ0–DQ3
E7,
–
UDQS,
D8
UDQS#
J7,
H8
–
–
J7, H8
–
J3, H2
D1, H1, M9,
R9, V1
M1
D9, F1, F3, F7,
F9, H9, K1,
K3, K7, K9
M2
D3, H3, M3,
T1, U9
M7
D7, E2, E8,
G2, G8, H7,
J2, J8, L2, L8
D1, H1, M9,
R9, V1
M1
D9, H9, K1,
K3, K7, K9
M2
D3, H3, M3,
T1, U9
M7
D7, H7,J 2,
J8, L2, L8
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1GbDDR2_2.fm - Rev. K 4/06 EN
I/O
I/O
Data input/output: Bidirectional data bus for 256 Meg x 4.
Data strobe for upper byte: Output with read data, input with
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. UDQS# is only used
when differential data strobe mode is enabled via the LOAD
MODE command.
LDQS,
I/O
Data strobe for lower byte: Output with read data, input with
LDQS#
write data for source synchronous operation. Edge-aligned with
read data, center-aligned with write data. LDQS# is only used
when differential data strobe mode is enabled via the LOAD
MODE command.
DQS, DQS#
I/O
Data strobe: Output with read data, input with write data for
source synchronous operation. Edge-aligned with read data,
center-aligned with write data. DQS# is only used when
differential data strobe mode is enabled via the LOAD MODE
command.
RDQS, RDQS# Output Redundant data strobe for 128 Meg x 8 only. RDQS is enabled/
disabled via the LOAD MODE command to the extended mode
register (EMR). When RDQS is enabled, RDQS is output with read
data only and is ignored during write data. When RDQS is
disabled, ball J3 becomes data mask (see DM ball). RDQS# is only
used when RDQS is enabled and differential data strobe mode is
enabled.
Supply Power Supply: 1.8V ±0.1V.
VDD
VDDL
VDDQ
VREF
VSS
VSSDL
VSSQ
Supply DLL Power supply: 1.8V ±0.1V.
Supply DQ Power supply: 1.8V ±0.1V. Isolated on the device for improved
noise immunity.
Supply SSTL_18 reference voltage.
Supply Ground.
Supply DLL ground: Isolated on the device from VSS and VSSQ.
Supply DQ ground: Isolated on the device for improved noise immunity.
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Ball Assignment and Description
Table 4:
92-Ball Descriptions – 256 Meg x 4, 128 Meg x 8, 64 Meg x 16
x16 Ball
Number
x4, x8 Ball
Number
A1, A2, A8,
A9 D2, H2,
AA1, AA2,
AA8, AA9
D8, H8
A1, A2, A8,
A9, D2, D8,
E1–E3, E7–E9,
F1–F3, F7–F9,
G1–G3,
G7–G9, AA1,
AA2, AA8,
AA9
J1, J9, L1, L9,
H2,
–
–
V3, V7, V8
–
Symbol
Type
NC
–
No connect: These balls should be left unconnected.
NF
–
NU
–
H2, H8
NU
–
V3, V7
RFU
–
No function: These balls are used as DQ4–DQ7 on the 128 Meg x8 ,
but are NF (no function) on the 256 Meg x 4 configuration.
Not used: Not used only on x16. If EMR[E10] = 0, D8 and H8 are
UDQS# and LDQS#.
If EMR[E10] = 1, then D8 and H8 are not used.
Not used: Not used only on x8. If EMR[E10] = 0, H2 and H8 are
RDQS# and DQS#.
If EMR[E10] = 1, then H2 and H8 are not used.
Reserved for future use: Row address bits A13 (V8), A14(V3), and
A15(V7) are reserved.
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1GbDDR2_2.fm - Rev. K 4/06 EN
Description
17
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Functional Description
Functional Description
The 1Gb DDR2 SDRAM is a high-speed CMOS dynamic random access memory
containing 1,073,741,824 bits. The 1Gb DDR2 SDRAM is internally configured as an 8bank DRAM.
The 1Gb DDR2 SDRAM uses a double data rate architecture to achieve high-speed operation. The DDR2 architecture is essentially a 4n-prefetch architecture, with an interface
designed to transfer two data words per clock cycle at the I/O balls. A single read or write
access for the 1Gb DDR2 SDRAM consists of a single 4n-bit-wide, one-clock-cycle data
transfer at the internal DRAM core and four corresponding n-bit- wide, one-half-clockcycle data transfers at the I/O balls.
Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections
provide detailed information covering device initialization, register definition,
command descriptions, and device operation.
Figure 9 on page 20 shows a simplified state diagram to provide the basic command flow.
It is not comprehensive and does not identify all timing requirements or possible
command restrictions.
Figure 6:
Functional Block Diagram – 64 Meg x 16
ODT
CS#
RAS#
CAS#
WE#
CONTROL
LOGIC
COMMAND
DECODE
CKE
CK
CK#
13
MODE
REGISTERS
16
REFRESH 13
COUNTER
ROWADDRESS
MUX
BANK 7
BANK 7
BANK 6
BANK 6
BANK 5
BANK 5
BANK 4
BANK 4
BANK 3
BANK 3
BANK 2
BANK 2
BANK 1
BANK 1
BANK 0
BANK 0
ROWMEMORY
ADDRESS
ARRAY
LATCH 8,192
&
(8,192 x 256 x 64)
DECODER
13
64 READ
LATCH
3
10
BANK
CONTROL
LOGIC
COLUMNADDRESS
COUNTER/
LATCH
sw1
16
DRVRS
MUX DATA
64
UDQS, UDQS#
INPUT LDQS, LDQS#
REGISTERS
2
2
2
8
WRITE
2
FIFO MASK
2
&
64
DRIVERS
16
COLUMN
DECODER
CK,CK#
2
CK OUT
64 16
CK IN DATA 16
16
sw2 sw3
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
DQ0–DQ15
4
DQS
GENERATOR
256
(x64)
8
16
16
ODT CONTROL VDDQ
sw1 sw2 sw3
DLL
16
I/O GATING
DM MASK LOGIC
2
16 ADDRESS
REGISTER
16
SENSE AMPLIFIERS
16,384
A0–A12,
BA0–BA2
CK,CK#
COL0,COL1
2
2
2
2
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
UDQS, UDQS#
LDQS, LDQS#
RCVRS
16
16 16
16
R1
R2
R3
16
R1
R2
R3
UDM, LDM
4
COL0,COL1
VssQ
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1GbDDR2_2.fm - Rev. K 4/06 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Functional Description
Figure 7:
Functional Block Diagram – 128 Meg x 8
ODT
CKE
CK
CK#
COMMAND
DECODE
CONTROL
LOGIC
CS#
RAS#
CAS#
WE#
14
MODE
REGISTERS
17
REFRESH 14
COUNTER
14
ROWADDRESS
MUX
BANK 7
BANK 7
BANK 6
BANK 6
BANK 5
BANK 5
BANK 4
BANK 4
BANK 3
BANK 3
BANK 2
BANK 2
BANK 1
BANK 1
BANK 0
BANK 0
ROWMEMORY
ADDRESS
ARRAY
LATCH 16,384
&
(16,384 x 256 x 32)
DECODER
32 READ
LATCH
BANK
CONTROL
LOGIC
3
COLUMNADDRESS
COUNTER/
LATCH
10
8
sw1
8
8
8
MUX
2
2
4
WRITE
2
FIFO MASK
2
&
32
DRIVERS
8
CK,CK#
2
sw2 sw3
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
DQ0–DQ7
2
UDQS, UDQS#
INPUT LDQS, LDQS#
REGISTERS
2
2
32
COLUMN
DECODER
DRVRS
DATA
DQS
GENERATOR
256
(x32)
ODT CONTROL VDDQ
sw1 sw2 sw3
DLL
8
I/O GATING
DM MASK LOGIC
2
17 ADDRESS
REGISTER
8
SENSE AMPLIFIERS
8,192
A0-A13,
BA0-BA2
CK,CK#
COL0,COL1
2
2
R1
R2
R3
R1
R2
R3
DQS, DQS#
RDQS#
2
RCVRS
8
CK OUT
32 8
CK IN DATA 8
8
8
8
8
8
sw1
sw2 sw3
R1
R2
R3
R1
R2
R3
RDQS
DM
2
COL0,COL1
VssQ
Figure 8:
Functional Block Diagram – 256 Meg x 4
ODT
CS#
RAS#
CAS#
WE#
CONTROL
LOGIC
COMMAND
DECODE
CKE
CK
CK#
14
MODE
REGISTERS
17
REFRESH 14
COUNTER
14
ROWADDRESS
MUX
BANK 7
BANK 7
BANK 6
BANK 6
BANK 5
BANK 5
BANK 4
BANK 4
BANK 3
BANK 3
BANK 2
BANK 2
BANK 1
BANK 1
BANK 0
BANK 0
ROWMEMORY
ADDRESS
ARRAY
LATCH 16,384
&
(16,384 x 512 x 16)
DECODER
16 READ
LATCH
3
11
BANK
CONTROL
LOGIC
COLUMNADDRESS
COUNTER/
LATCH
9
sw1
4
4
4
MUX
DRVRS
DATA
DQS, DQS#
INPUT
REGISTERS
1
1
16
1
4
WRITE
1
FIFO MASK
1
&
16
DRIVERS
4
COLUMN
DECODER
CK,CK#
2
CK OUT
16 4
CK IN DATA 4
4
sw2 sw3
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
DQ0–DQ3
2
DQS
GENERATOR
512
(x16)
ODT CONTROL VDDQ
sw1 sw2 sw3
DLL
4
I/O GATING
DM MASK LOGIC
2
17 ADDRESS
REGISTER
4
SENSE AMPLIFIERS
8,192
A0-A13,
BA0-BA2
CK,CK#
COL0,COL1
1
1
1
1
R1
R2
R3
R1
R2
R3
sw1
sw2 sw3
DQS, DQS#
RCVRS
4
4
4
4
R1
R2
R3
4
R1
R2
R3
DM
2
COL0,COL1
VssQ
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1GbDDR2_2.fm - Rev. K 4/06 EN
19
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
State Diagram
State Diagram
Figure 9 shows a simplified state diagram to provide the basic command flow. It is not
comprehensive and does not identify all timing requirements or possible command
restrictions.
Figure 9:
Simplified State Diagram
CKE_L
Initialization
Sequence
OCD
calibration
Self
Refreshing
SR
PRE
E_H
CK
Setting
MRS
EMRS
Idle
All banks
Precharged
(E)MRS
REFRESH
CK
E_
H
Refreshing
L
CK
E_
L
E_
CK
Precharge
PowerDown
CKE_L
Automatic Sequence
Command Sequence
ACT = Activate
CKE_H = CKE HIGH, exit power-down or self refresh
CKE_L = CKE LOW, enter power-down
(E)MRS = (Extended) mode register set
PRE = PRECHARGE
PRE_A = PRECHARGE ALL
READ = READ
RD_A = READ with auto precharge
REFRESH = REFRESH
SR = SELF REFRESH
WRITE = WRITE
WR_A = WRITE with auto precharge
ACT
CKE_L
Activating
_L
CKE
Active
PowerDown
CK CKE_
E_L H
Bank
Active
E
R_
A
W
W
RE
AD
_A
RD
RIT
WRITE
Writing
READ
READ
Reading
WR_A
RD
_A
_A
RD_A
PR
E
,
PRE, PRE_A
PR
A
E_
PR
Writing
with
Auto
Precharge
E_
A
E,
PR
WR_A
WR
Reading
with
Auto
Precharge
Precharging
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1GbDDR2_2.fm - Rev. K 4/06 EN
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©2004 Micron Technology, Inc. All rights reserved.
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1GbDDR2_2.fm - Rev. K 4/06 EN
Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. Figure 10 illustrates the sequence required for power-up and
initialization.
Figure 10: DDR2 Power-up and Initialization
Notes appear on page 22
VDD
VDDL
VDDQ
tVTD1
VTT1
VREF
T0
tCK
Ta0
Tb0
Tc0
Td0
Te0
Tf0
Tg0
Th0
Ti0
Tj0
Tk0
Tl0
NOP5
PRE
LM7
LM8
LM9
LM10
PRE11
REF12
REF
LM13
LM14
LM15
A10 = 1
CODE
CODE
CODE
CODE
A10 = 1
Tm0
CK#
CK
tCL
tCL
SSTL_18
LVCMOS
CKE LOW LEVEL2 LOW LEVEL2
ODT
21
COMMAND3
VALID16
ADDRESS3
DQS4
High-Z
DQ4
High-Z
RTT
High-Z
T = 200µs (MIN)
Power-up:
VDD and stable
clock (CK, CK#)
T = 400ns
(MIN)6
tRPA
tMRD
tMRD
tMRD
tMRD
CODE
tRPA
tRFC
tRFC
CODE
CODE
tMRD
tMRD
VALID
tMRD
See note 12
EMR(2)
EMR(3)
EMR
MR without
DLL RESET
MR with
DLL RESET
EMR with
OCD Default
EMR with
OCD Exit
200 cycles of CK are required before a READ command can be issued.
Indicates a break in
time scale
Normal
Operation
DON’T CARE
1Gb: x4, x8, x16 DDR2 SDRAM
Initialization
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
DM4
1Gb: x4, x8, x16 DDR2 SDRAM
Initialization
Notes:
1. Applying power; if CKE is maintained below 0.2 x VDDQ, outputs remain disabled. To guarantee RTT (ODT resistance) is off, VREF must be valid and a low level must be applied to the
ODT ball (all other inputs may be undefined; I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DDR2 SDRAM device latch-up). VTT is not applied directly to
the device; however, tVTT should be ≥0 to avoid device latch-up. At least one of the following two sets of conditions (A or B) must be met to obtain a stable supply state (stable supply
defined as VDD, VDDL, VDDQ, VREF, and VTT are between their minimum and maximum values as stated in Table 20 on page 89):
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
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1GbDDR2_2.fm - Rev. K 4/06 EN
A. Single power source: The VDD voltage ramp from 300mV to VDD (MIN) must take no
longer than 200ms; during the VDD voltage ramp, |VDD - VDDQ| ≤ 0.3V. Once supply voltage
ramping is complete (when VDDQ crosses VDD [MIN]), Table 20 specifications apply.
• VDD, VDDL, and VDDQ are driven from a single power converter output
• VTT is limited to 0.95V MAX
• VREF tracks VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during supply ramp time
• VDDQ ≥ VREF at all times
B. Multiple power sources: VDD ≥ VDDL ≥ VDDQ must be maintained during supply voltage ramping, for both AC and DC levels, until supply voltage ramping completes (VDDQ
crosses VDD [MIN]). Once supply voltage ramping is complete, Table 20 specifications apply.
• Apply VDD and VDDL before or at the same time as VDDQ; VDD/VDDL voltage ramp
time must be ≤200ms from when VDD ramps from 300mV to VDD (MIN)
• Apply VDDQ before or at the same time as VTT; the VDDQ voltage ramp time from
when VDD (MIN) is achieved to when VDDQ (MIN) is achieved must be ≤500ms; while
VDD is ramping, current can be supplied from VDD through the device to VDDQ
• VREF must track VDDQ/2; VREF must be within ±0.3V with respect to VDDQ/2 during
supply ramp time; VDDQ ≥ VREF must be met at all times
• Apply VTT; the VTT voltage ramp time from when VDDQ (MIN) is achieved to when
VTT (MIN) is achieved must be no greater than 500ms
CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during device
power-up prior to VREF being stable. After state T0, CKE is required to have SSTL_18 input
levels. Once CKE transitions to a high level, it must stay HIGH for the duration of the initialization sequence.
PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode Register, EMR =
extended mode register, EMR2 = extended mode register 2, EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE command, A10 = PRECHARGE ALL, CODE =
desired values for mode registers (bank addresses are required to be decoded), VALID - any
valid command/address, RA = row address, bank address.
DM represents DM for x4, x8 configurations and UDM, LDM for x16 configuration; DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16); DQ represents DQ0–DQ3 for x4, DQ–DQ7 for x8, and DQ0–DQ15 for x16.
For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or DESELECT
commands, then take CKE HIGH.
Wait a minimum of 400ns, then issue a PRECHARGE ALL command.
Issue a LOAD MODE command to the EMR(2). (To issue an EMR(2) command, provide LOW
to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to “0” or “1;” all others must be
“0.”
Issue a LOAD MODE command to the EMR(3). (To issue an EMR(3) command, provide HIGH
to BA0 =1, BA1 = 1, and BA2 = 0.) Set all registers to “0.”
Issue a LOAD MODE command to the EMR to enable DLL. To issue a DLL ENABLE command,
provide LOW to BA1, BA2, and A0; provide HIGH to BA0. Bits E7, E8, and E9 can be set to
“0” or “1;” Micron recommends setting them to “0.”
Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is required to lock
the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide LOW to BA2 = BA1 = BA0 =
0.) CKE must be HIGH the entire time.
Issue PRECHARGE ALL command.
Issue two or more REFRESH commands.
22
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1Gb: x4, x8, x16 DDR2 SDRAM
Initialization
13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e., to program operating parameters without resetting the DLL). To access the mode registers, BA0 =
0, BA1 = 0, BA2 = 0.
14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, and
E9 to “1,” and then setting all other desired parameters. To access the extended mode register, BA2 = 0, BA1 = 0, BA0 = 1.
15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and E9
to “0,” and then setting all other desired parameters. To access the extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1.
16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles after
the DLL RESET at Tf0.
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1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Mode Register (MR)
The mode register is used to define the specific mode of operation of the DDR2 SDRAM.
This definition includes the selection of a burst length, burst type, CAS latency, operating mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 11
on page 25. Contents of the mode register can be altered by re-executing the LOAD
MODE (LM) command. If the user chooses to modify only a subset of the MR variables,
all variables (M0–M13 for x4 and x8 or M0–M12 for x16) must be programmed when the
command is issued.
The MR is programmed via the LM command (bits BA2–BA0 = 0, 0, 0) and other bits
(M13–M0 for x4 and x8, M12–M0 for x16) will retain the stored information until it is
programmed again or the device loses power (except for bit M8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory array,
provided it is performed correctly.
The LM command can only be issued (or reissued) when all banks are in the precharged
state (idle state) and no bursts are in progress. The controller must wait the specified
time tMRD before initiating any subsequent operations such as an ACTIVE command.
Violating either of these requirements will result in unspecified operation.
Burst Length
Burst length is defined by bits M0–M3, as shown in Figure 11 on page 25. Read and write
accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of
column locations that can be accessed for a given READ or WRITE command.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A2–Ai when BL = 4 and by A3–Ai when BL = 8 (where Ai is the most
significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The
programmed burst length applies to both READ and WRITE bursts.
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1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Figure 11:
Mode Register (MR) Definition
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
16 15 14 13 12 11 10
MR
01 PD
WR
9
8
Slow Exit
(Low Power)
6
5
4
3
2
Notes:
0
Mode Register (Mx)
M2 M1 M0 Burst Length
M7 Mode
0 Normal
0
0
0
Reserved
1
0
0
1
Reserved
0
1
0
4
0
1
1
8
Test
M8 DLL Reset
0
No
1
0
0
Reserved
1
Yes
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M11 M10 M9 WRITE RECOVERY
M16 M15 M14
0
0
0
1
DLL TM CAS# Latency BT Burst Length
M12 PD mode
0
Fast Exit
(Normal)
1
7
Address Bus
0
0
0
Reserved
0
0
1
2
M3
0
1
0
3
0
Sequential
0
1
1
4
1
Interleaved
1
0
0
5
1
0
1
6
1
1
0
Reserved
1
1
1
Reserved
M6 M5 M4
Mode Register Definition
Mode Register (MR)
0
0
1
Extended Mode Register (EMR)
0
1
0
Extended Mode Register (EMR2)
0
1
1
Extended Mode Register (EMR3)
Burst Type
CAS Latency (CL)
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
1. M13 (A13) is reserved for future use and must be programmed to “0.” A13 is not used in
x16 configuration.
2. Not all listed CL options are supported in any individual speed grade.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved.
The burst type is selected via bit M3, as shown in Figure 11. The ordering of accesses
within a burst is determined by the burst length, the burst type, and the starting column
address, as shown in Table 5 on page 26. DDR2 SDRAM supports 4-bit burst mode and 8bit burst mode only. For 8-bit burst mode, full, interleaved address ordering is
supported; however, sequential address ordering is nibble-based.
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1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Table 5:
Burst Definition
Starting Column
Address
Burst Length
(A2, A1, A0)
4
8
00
01
10
11
000
001
010
011
100
101
110
111
Order of Accesses Within a Burst
Burst Type = Sequential
Burst Type = Interleaved
0, 1, 2, 3
1, 2, 3, 0
2, 3, 0, 1
3, 0, 1, 2
0, 1, 2, 3, 4, 5, 6, 7
1, 2, 3, 0, 5, 6, 7, 4
2, 3, 0, 1, 6, 7, 4, 5
3, 0, 1, 2, 7, 4, 5, 6
4, 5, 6, 7, 0, 1, 2, 3
5, 6, 7, 4, 1, 2, 3, 0
6, 7, 4, 5, 2, 3, 0, 1
7, 4, 5, 6, 3, 0, 1, 2
0, 1, 2, 3
1, 0, 3, 2
2, 3, 0, 1
3, 2, 1, 0
0, 1, 2, 3, 4, 5, 6, 7
1, 0, 3, 2, 5, 4, 7, 6
2, 3, 0, 1, 6, 7, 4, 5
3, 2, 1, 0, 7, 6, 5, 4
4, 5, 6, 7, 0, 1, 2, 3
5, 4, 7, 6, 1, 0, 3, 2
6, 7, 4, 5, 2, 3, 0, 1
7, 6, 5, 4, 3, 2, 1, 0
Operating Mode
The normal operating mode is selected by issuing a command with bit M7 set to “0,” and
all other bits set to the desired values, as shown in Figure 11 on page 25. When bit M7 is
“1,” no other bits of the mode register are programmed. Programming bit M7 to “1”
places the DDR2 SDRAM into a test mode that is only used by the manufacturer and
should not be used. No operation or functionality is guaranteed if M7 bit is “1.”
DLL RESET
DLL RESET is defined by bit M8, as shown in Figure 11 on page 25. Programming bit M8
to “1” will activate the DLL RESET function. Bit M8 is self-clearing, meaning it returns
back to a value of “0” after the DLL RESET function has been issued.
Anytime the DLL RESET function is used, 200 clock cycles must occur before a READ
command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of
the tAC or tDQSCK parameters.
Write Recovery
Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 11 on page 25.
The WR register is used by the DDR2 SDRAM during WRITE with auto precharge operation. During WRITE with auto precharge operation, the DDR2 SDRAM delays the
internal auto precharge operation by WR clocks (programmed in bits M9–M11) from the
last data burst. An example of WRITE with auto precharge is shown in Figure 43 on
page 62.
WR values of 2, 3, 4, 5, or 6 clocks may be used for programming bits M9–M11. The user
is required to program the value of WR, which is calculated by dividing tWR (in nanoseconds) by tCK (in nanoseconds) and rounding up a noninteger value to the next integer;
WR [cycles] = tWR [ns] / tCK [ns]. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
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1Gb: x4, x8, x16 DDR2 SDRAM
Mode Register (MR)
Power-Down Mode
Active power-down (PD) mode is defined by bit M12, as shown in Figure 11 on page 25.
PD mode allows the user to determine the active power-down mode, which determines
performance versus power savings. PD mode bit M12 does not apply to precharge PD
mode.
When bit M12 = 0, standard active PD mode, or “fast-exit” active PD mode, is enabled.
The tXARD parameter is used for fast-exit active PD exit timing. The DLL is expected to
be enabled and running during this mode.
When bit M12 = 1, a lower-power active PD mode, or “slow-exit” active PD mode, is
enabled. The tXARDS parameter is used for slow-exit active PD exit timing. The DLL can
be enabled but “frozen” during active PD mode since the exit-to-READ command timing
is relaxed. The power difference expected between IDD3P normal and IDD3P low-power
mode is defined in Table 45 on page 118.
CAS Latency (CL)
The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 11 on page 25. CL is
the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, or 6 clocks, depending
on the speed grade option being used.
DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be
used as unknown operation or incompatibility with future versions may result.
DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This
feature allows the READ command to be issued prior to tRCD (MIN) by delaying the
internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in
more detail in “Posted CAS Additive Latency (AL)” on page 31.
Examples of CL = 3 and CL = 4 are shown in Figure 12 on page 28; both assume AL = 0. If
a READ command is registered at clock edge n, and the CL is m clocks, the data will be
available nominally coincident with clock edge n + m (this assumes AL = 0).
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1Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register (EMR)
Figure 12:
CK#
CAS Latency (CL)
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
DQS, DQS#
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 3 (AL = 0)
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
DQS, DQS#
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CL = 4 (AL = 0)
TRANSITIONING DATA
Notes:
DON’T CARE
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal tAC, tDQSCK, and tDQSQ.
Extended Mode Register (EMR)
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable, output drive strength, ondie termination (ODT) (RTT), posted AL, off-chip driver impedance calibration (OCD),
DQS# enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These
functions are controlled via the bits shown in Figure 13 on page 29. The EMR is
programmed via the LM command and will retain the stored information until it is
programmed again or the device loses power. Reprogramming the EMR will not alter the
contents of the memory array, provided it is performed correctly.
The EMR must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
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1Gb: x4, x8, x16 DDR2 SDRAM
DLL Enable/Disable
Figure 13:
Extended Mode Register Definition
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16 15 14
13
MRS
12
11
10
9
8
7
0
E12
Outputs
0
Enabled
4
3
2
1
1
Disabled
E6 E2 Rtt (nominal)
E11 RDQS Enable
0
0
No
1
Yes
0
Enable
1
Disable
RTT disabled
Address Bus
Extended Mode
Register (Ex)
E0
DLL Enable
0
Enable (Normal)
1
Disable (Test/Debug)
0
0
0
1
75Ω
1
0
150Ω
E1
1
1
50Ω
0
Full strength (18Ω target)
1
Reduced strength (40Ω target)
E10 DQS# Enable
Output Drive Strength
E5 E4 E3 Posted CAS# Additive Latency (AL)
E9 E8 E7 OCD Operation
Notes:
5
out RDQS DQS# OCD Program RTT Posted CAS# RTT ODS DLL
2
E16 E15 E14
6
A1 A0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
0
0
0
OCD not supported1
1
0
0
4
0
0
1
Reserved
1
0
1
Reserved
0
1
0
Reserved
1
1
0
Reserved
1
0
0
Reserved
1
1
1
Reserved
1
1
1
OCD default state1
Mode Register Set
Mode register set (MRS)
0
0
0
0
0
1
Extended mode register (EMRS)
0
1
0
Extended mode register (EMRS2)
0
1
1
Extended mode register (EMRS3)
1. During initialization, all three bits must be set to “1” for OCD default state, then must be
set to “0” before initialization is finished, as detailed in the notes on pages 22–23.
2. E13 (A13) is not used on the x16 configuration.
DLL Enable/Disable
The DLL may be enabled or disabled by programming bit E0 during the LM command,
as shown in Figure 13. The DLL must be enabled for normal operation. DLL enable is
required during power-up initialization and upon returning to normal operation after
having disabled the DLL for the purpose of debugging or evaluation. Enabling the DLL
should always be followed by resetting the DLL using the LM command.
The DLL is automatically disabled when entering SELF REFRESH operation and is automatically re-enabled and reset upon exit of SELF REFRESH operation.
Anytime the DLL is enabled (and subsequently reset), 200 clock cycles must occur before
a READ command can be issued, to allow time for the internal clock to synchronize with
the external clock. Failing to wait for synchronization to occur may result in a violation
of the tAC or tDQSCK parameters.
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1Gb: x4, x8, x16 DDR2 SDRAM
Output Drive Strength
Output Drive Strength
The output drive strength is defined by bit E1, as shown in Figure 13 on page 29. The
normal drive strength for all outputs are specified to be SSTL_18. Programming bit E1 = 0
selects normal (full strength) drive strength for all outputs. Selecting a reduced drive
strength option (E1 = 1) will reduce all outputs to approximately 60 percent of the
SSTL_18 drive strength. This option is intended for the support of lighter load and/or
point-to-point environments.
DQS# Enable/Disable
The DQS# ball is enabled by bit E10. When E10 = 0, DQS# is the complement of the
differential data strobe pair DQS/DQS#. When disabled (E10 = 1), DQS is used in a
single-ended mode and the DQS# ball is disabled. When disabled, DQS# should be left
floating. This function is also used to enable/disable RDQS#. If RDQS is enabled (E11 =
1) and DQS# is enabled (E10 = 0), then both DQS# and RDQS# will be enabled.
RDQS Enable/Disable
The RDQS ball is enabled by bit E11, as shown in Figure 13 on page 29. This feature is
only applicable to the x8 configuration. When enabled (E11 = 1), RDQS is identical in
function and timing to data strobe DQS during a READ. During a WRITE operation,
RDQS is ignored by the DDR2 SDRAM.
Output Enable/Disable
The OUTPUT ENABLE function is defined by bit E12, as shown in Figure 13 on page 29.
When enabled (E12 = 0), all outputs (DQs, DQS, DQS#, RDQS, RDQS#) function
normally. When disabled (E12 = 1), all DDR2 SDRAM outputs (DQs, DQS, DQS#, RDQS,
RDQS#) are disabled, thus removing output buffer current. The output disable feature is
intended to be used during IDD characterization of read current.
On-Die Termination (ODT)
ODT effective resistance, RTT (EFF), is defined by bits E2 and E6 of the EMR, as shown in
Figure 13 on page 29. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DDR2 SDRAM controller to independently turn on/off
ODT for any or all devices. RTT effective resistance values of 50Ω, 75Ω, and 150Ω are
selectable and apply to each DQ, DQS/DQS#, RDQS/RDQS#, UDQS/UDQS#, LDQS/
LDQS#, DM, and UDM/LDM signals. Bits (E6, E2) determine what ODT resistance is
enabled by turning on/off “sw1,” “sw2,” or “sw3.” The ODT effective resistance value is
selected by enabling switch “sw1,” which enables all R1 values that are 150Ω each,
enabling an effective resistance of 75Ω (RTT2 (EFF) = R2/2). Similarly, if “sw2” is enabled,
all R2 values that are 300Ω each, enable an effective ODT resistance of 150Ω (RTT2 (EFF)
= R2/2). Switch “sw3” enables R1 values of 100Ω, enabling effective resistance of 50Ω.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
The ODT control ball is used to determine when RTT (EFF) is turned on and off,
assuming ODT has been enabled via bits E2 and E6 of the EMR. The ODT feature and
ODT input ball are only used during active, active power-down (both fast-exit and slowexit modes), and precharge power-down modes of operation. ODT must be turned off
prior to entering self refresh. During power-up and initialization of the DDR2 SDRAM,
ODT should be disabled until issuing the EMR command to enable the ODT feature, at
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1Gb: x4, x8, x16 DDR2 SDRAM
Off-Chip Driver (OCD) Impedance Calibration
which point the ODT ball will determine the RTT (EFF) value. Any time the EMR enables
the ODT function, ODT may not be driven HIGH until eight clocks after the EMR has
been enabled. See “ODT Timing” on page 79 for ODT timing diagrams.
Off-Chip Driver (OCD) Impedance Calibration
The OFF-CHIP DRIVER function is no longer supported and must be set to the default
state. See “Initialization” on page 21 for proper setting of OCD defaults.
Posted CAS Additive Latency (AL)
Posted CAS additive latency (AL) is supported to make the command and data bus efficient for sustainable bandwidths in DDR2 SDRAM. Bits E3–E5 define the value of AL, as
shown in Figure 13 on page 29. Bits E3–E5 allow the user to program the DDR2 SDRAM
with an inverse AL of 0, 1, 2, 3, or 4 clocks. Reserved states should not be used as
unknown operation or incompatibility with future versions may result.
In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued
prior to tRCD (MIN) with the requirement that AL ≤ tRCD (MIN). A typical application
using this feature would set AL = tRCD (MIN) - 1 x tCK. The READ or WRITE command is
held for the time of the AL before it is issued internally to the DDR2 SDRAM device. RL is
controlled by the sum of AL and CL; RL = AL + CL. Write latency (WL) is equal to RL
minus one clock; WL = AL + CL - 1 x tCK. An example of RL is shown in Figure 14. An
example of a WL is shown in Figure 15 on page 32.
Figure 14:
CK#
READ Latency
T0
T1
T2
T3
T4
T5
T6
T7
T8
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
DQS, DQS#
tRCD (MIN)
DQ
AL = 2
CL = 3
DOUT
n
DOUT
n+1
DOUT
n+2
DOUT
n+3
RL = 5
TRANSITIONING DATA
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
1.
2.
3.
4.
5.
DON’T CARE
BL = 4.
Shown with nominal tAC, tDQSCK, and tDQSQ.
CL = 3.
AL = 2.
RL = AL +CL = 5.
31
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1Gb: x4, x8, x16 DDR2 SDRAM
Extended Mode Register 2
Figure 15:
WRITE Latency
T0
T1
ACTIVE n
WRITE n
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
COMMAND
t
RCD (MIN)
DQS, DQS#
AL = 2
CL - 1 = 2
DIN
n
DQ
DIN
n+1
DIN
n+2
DIN
n+3
WL = AL + CL - 1 = 4
TRANSITIONING DATA
Notes:
1.
2.
3.
4.
DON’T CARE
BL = 4.
CL = 3.
AL = 2.
WL = AL + CL - 1 = 4.
Extended Mode Register 2
The extended mode register 2 (EMR2) controls functions beyond those controlled by the
mode register. Currently all bits in EMR2 are reserved, except for E7, which is for
commercial or high-temperature operations, as shown in Figure 16. The EMR2 is
programmed via the LM command and will retain the stored information until it is
programmed again or the device loses power. Reprogramming the EMR will not alter the
contents of the memory array, provided it is performed correctly.
Bit E7 (A7) must be programmed as “1” to provide a faster refresh rate on IT devices if the
TCASE exceeds 85°C.
EMR2 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 16:
Extended Mode Register 2 (EMR2) Definition
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2
EMR2
01 01 01 01 01 01 01 01 01 01 01 01
M16 M15 M14
Notes:
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Mode Register Definition
A1 A0
1
1
0
0
01
Address Bus
Extended Mode
Register (Ex)
E7 High Temperature Self Refresh rate enable
0
0
0
Mode register (MR)
0
0
1
Extended mode register (EMR)
0
1
0
Extended mode register (EMR2)
0
1
1
Extended mode register (EMR3)
0
1
Commercial temperature default
Industrial temperature option;
use if TC exceeds 85°C
1. E13 (A13)–E8 (A8) and E6 (A6)–E0 (A0) are reserved for future use and must all be programmed to “0.” A13 is not used in x16 configuration.
32
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Extended Mode Register 3
Extended Mode Register 3
The extended mode register 3 (EMR3) controls functions beyond those controlled by the
mode register. Currently all bits in EMR3 are reserved, as shown in Figure 17 on page 33.
The EMR3 is programmed via the LM command and will retain the stored information
until it is programmed again or the device loses power. Reprogramming the EMR will not
alter the contents of the memory array, provided it is performed correctly.
EMR3 must be loaded when all banks are idle and no bursts are in progress, and the
controller must wait the specified time tMRD before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation.
Figure 17:
Extended Mode Register 3 (EMR3) Definition
BA2 BA1 BA0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16 15 14 13 12 11 10 9 8 7 6 5 4 3
EMR3
01 01 01 01 01 01 01 01 01 01 01
M16 M15 M14
Notes:
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2
01
A1 A0
1
01
0
01
Address Bus
Extended Mode
Register (Ex)
Mode Register Definition
0
0
0
Mode register (MR)
0
0
1
Extended mode register (EMR)
0
1
0
Extended mode register (EMR2)
0
1
1
Extended mode register (EMR3)
1. E13 (A13)–E0 (A0) are reserved for future use and must all be programmed to “0.” A13 is
not used in x16 configuration.
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Command Truth Tables
Command Truth Tables
The following tables provide a quick reference of DDR2 SDRAM available commands,
including CKE power-down modes and bank-to-bank commands.
Table 6:
Truth Table – DDR2 Commands
Notes: 1, 5, and 6 apply to all
CKE
Function
BA2
BA1
BA0
A13,
A12,
A11
L
H
H
X
H
BA
X
X
H
L
L
H
H
Previous
Cycle
Current
Cycle
CS#
A10
A9–A0
LOAD MODE
REFRESH
SELF REFRESH entry
H
H
H
H
H
L
SELF REFRESH exit
L
H
L
L
L
H
L
L
L
L
X
H
L
L
L
X
H
X
X
OP Code
X
X
X
X
X
X
X
X
7
H
H
L
L
L
BA
X
L
X
2
H
H
L
H
L
X
X
H
X
H
H
L
H
H
BA
WRITE
H
L
H
L
L
BA
WRITE with auto
precharge
H
L
H
L
L
BA
READ
H
H
L
H
L
H
BA
H
H
L
H
L
H
BA
H
H
X
X
H
L
Power-down exit
L
H
H
X
X
H
X
H
H
X
X
H
X
H
H
X
X
H
X
H
X
X
Power-down entry
L
H
H
L
H
L
Single bank
PRECHARGE
All banks
PRECHARGE
Bank activate
READ with auto
precharge
NO OPERATION
Device DESELECT
Notes:
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RAS# CAS# WE#
Notes
2
Row Address
Column
Column
L
Address
Address
Column
Column
H
Address
Address
Column
Column
L
Address
Address
Column
Column
H
Address
Address
X
X
X
X
X
X
2, 3
2, 3
2, 3
2, 3
X
X
X
X
4
X
X
X
X
4
1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the
rising edge of the clock.
2. Bank addresses (BA) BA0–BA2 determine which bank is to be operated upon. BA during a
LM command selects which mode register is programmed.
3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See Figure 25 on
page 45 and Figure 39 on page 58 for other restrictions and details.
4. The power-down mode does not perform any REFRESH operations. The duration of powerdown is limited by the refresh requirements outlined in the AC parametric section.
5. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh. See “ODT Timing” on page 79 for details.
6. “X” means “H or L” (but a defined logic level).
7. SELF REFRESH exit is asynchronous.
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Command Truth Tables
Table 7:
Truth Table – Current State Bank n – Command to Bank n
Notes: 1–6; notes appear below and on next page
Current
State
CS#
RAS#
CAS#
WE#
Command/Action
Notes
Any
H
L
X
H
X
H
X
H
Idle
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
L
H
H
L
H
L
L
L
L
H
L
L
H
L
L
H
H
H
L
H
L
L
H
L
L
H
L
L
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous
operation)
ACTIVE (select and activate row)
REFRESH
LOAD MODE
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (deactivate row in bank or banks)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE (start PRECHARGE)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE (start PRECHARGE)
7
7
9
9
8
9
9, 10
8
9
9
8
Row active
Read (autoprecharge
Disabled
Write (autoprecharge
disabled)
Notes:
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table is bank-specific, except where noted (the current state is for a specific bank and
the commands shown are those allowed to be issued to that bank when in that state).
Exceptions are covered in the notes below.
3. Current state definitions:
The bank has been precharged, tRP has been met, and any READ burst is
complete.
Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not
yet terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated.
4. The following states must not be interrupted by a command issued to the same bank. Issue
DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge
occurring during these states. Allowable commands to the other bank are determined by its
current state and this table, and according to Table 8 on page 37.
Idle:
Starts with registration of a PRECHARGE command and ends when tRP
is met. Once tRP is met, the bank will be in the idle state.
Read with auto
Starts with registration of a READ command with auto precharge
precharge enabled: enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Row activating:
Starts with registration of an ACTIVE command and ends when tRCD is
met. Once tRCD is met, the bank will be in the “row active” state.
Write with auto
Starts with registration of a WRITE command with auto precharge
precharge enabled: enabled and ends when tRP has been met. Once tRP is met, the bank
will be in the idle state.
Precharging:
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Command Truth Tables
5. The following states must not be interrupted by any executable command (DESELECT or
NOP commands must be applied on each positive clock edge during these states):
Starts with registration of a REFRESH command and ends when tRFC is
met. Once tRFC is met, the DDR2 SDRAM will be in the all banks idle state.
Accessing mode Starts with registration of the LM command and ends when tMRD has
register:
been met. Once tMRD is met, the DDR2 SDRAM will be in the all banks idle
state.
Precharging all: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met. Once tRP is met, all banks will be in the idle state.
Refreshing:
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a
valid state for precharging.
9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
10. A WRITE command may be applied after the completion of the READ burst.
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Command Truth Tables
Table 8:
Truth Table – Current State Bank n – Command to Bank m
Notes: 1–6; notes appear below and on next page
Current State
Any
Idle
Row Activating,
Active, or
Precharging
Read (auto
precharge
disabled
Write (auto
precharge
disabled.)
Read (with autoprecharge)
Write (with autoprecharge)
CS#
RAS#
CAS#
WE#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
Notes:
Command/Action
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any command otherwise allowed to bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
Notes
7
7
7
7, 9
7, 8
7
7, 3
7, 9, 3
7, 3
7, 3
1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH and after tXSNR has been met
(if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted (i.e., the current state is
for bank n and the commands shown are those allowed to be issued to bank m, assuming
that bank m is in such a state that the given command is allowable). Exceptions are covered
in the notes below.
3. Current state definitions:
The bank has been precharged, tRP has been met, and any READ burst is
complete.
Row active: A row in the bank has been activated and tRCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated with auto precharge disabled, and has not
yet terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not
yet terminated.
Idle:
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Command Truth Tables
READ with
auto
precharge
enabled/
WRITE with
auto
precharge
enabled:
The READ with auto precharge enabled or WRITE with auto precharge
enabled states can each be broken into two parts: the access period and the
precharge period. For READ with auto precharge, the precharge period is
defined as if the same burst was executed with auto precharge disabled and
then followed with the earliest possible PRECHARGE command that still
accesses all of the data in the burst. For WRITE with auto precharge, the
precharge period begins when tWR ends, with tWR measured as if auto
precharge was disabled. The access period starts with registration of the
command and ends where the precharge period (or tRP) begins. This device
supports concurrent auto precharge such that when a READ with auto
precharge is enabled or a WRITE with auto precharge is enabled, any
command to other banks is allowed, as long as that command does not
interrupt the read or write data transfer already in process. In either case, all
other related limitations apply (contention between read data and write data
must be avoided).
The minimum delay from a READ or WRITE command with auto precharge
enabled to a command to a different bank is summarized in Table 9:
Table 9:
Minimum Delay with Auto Precharge Enabled
From Command
(Bank n)
To Command (Bank m)
WRITE with auto
precharge
READ or READ with auto
precharge
WRITE or WRITE with auto
precharge
PRECHARGE or ACTIVE
READ or READ with auto
precharge
WRITE or WRITE with auto
precharge
PRECHARGE or ACTIVE
READ with auto
precharge
Minimum Delay
(with concurrent
auto precharge)
Units
(CL - 1) + (BL / 2) + tWTR
tCK
(BL / 2)
tCK
1
(BL / 2)
tCK
(BL / 2) + 2
tCK
1
tCK
tCK
4.
5.
6.
7.
REFRESH and LM commands may only be issued when all banks are idle.
Not used.
All states and sequences not shown are illegal or reserved.
READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto
precharge enabled and READs or WRITEs with auto precharge disabled.
8. Requires appropriate DM.
9. A WRITE command may be applied after the completion of the READ burst.
10. The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
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DESELECT, NOP, and LM Commands
DESELECT, NOP, and LM Commands
DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by
the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in
progress are not affected. DESELECT is also referred to as COMMAND INHIBIT.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR2 SDRAM to
perform a NOP (CS# is LOW; RAS#, CAS#, and WE are HIGH). This prevents unwanted
commands from being registered during idle or wait states. Operations already in
progress are not affected.
LOAD MODE (LM)
The mode registers are loaded via inputs BA2–BA0 and A13–A0 for x4 and x8, and A12–A0
for x16 configurations. BA2–BA0 determine which mode register will be programmed.
See “Mode Register (MR)” on page 24. The LM command can only be issued when all
banks are idle, and a subsequent executable command cannot be issued until tMRD is
met.
Bank/Row Activation
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for a
subsequent access. The value on the BA2–BA0 inputs selects the bank, and the address
provided on inputs (A13–A0 for x4 and x8, and A12–A0 for x16) selects the row. This row
remains active (or open) for accesses until a PRECHARGE command is issued to that
bank. A PRECHARGE command must be issued before opening a different row in the
same bank.
ACTIVE Operation
Before any READ or WRITE commands can be issued to a bank within the DDR2
SDRAM, a row in that bank must be opened (activated), even when additive latency is
used. This is accomplished via the ACTIVE command, which selects both the bank and
the row to be activated, as shown in Figure 18 on page 40.
After a row is opened with an ACTIVE command, a READ or WRITE command may be
issued to that row subject to the tRCD specification. tRCD (MIN) should be divided by
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. The same procedure is used to convert other specification limits from time
units to clock cycles. For example, a tRCD (MIN) specification of 20ns with a 266 MHz
clock (tCK = 3.75ns) results in 5.3 clocks, rounded up to 6. This is reflected in Figure 21 on
page 42, which covers any case where 5 < tRCD (MIN) / tCK ≤ 6. Figure 21 also shows the
case for tRRD where 2 < tRRD (MIN) / tCK ≤ 3.
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been closed (precharged). The minimum time interval
between successive ACTIVE commands to the same bank is defined by tRC.
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Bank/Row Activation
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
RRD.
Figure 18:
ACTIVE Command
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
ADDRESS
Row
BANK ADDRESS
Bank
DON’T CARE
DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to
be issued prior to tRCD (MIN) by delaying the actual registration of the READ/WRITE
command to the internal device by AL clock cycles.
No more than 4-bank ACTIVE commands may be issued in a given tFAW (MIN) period.
RRD (MIN) restriction still applies. The tFAW (MIN) parameters apply to all 8-bank
DDR2 devices, regardless of the number of banks already open or closed, as shown in
Figure 19 .
t
Figure 19:
8-Bank Activate Restriction
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
COMMAND
ACT
READ
ACT
READ
ACT
READ
ACT
READ
NOP
NOP
ACT
ADDRESS
Row
Col
Row
Col
Row
Col
Row
Col
Row
Bank a
Bank b
Bank b
Bank c
Bank c
Bank d
Bank d
Bank e
CK#
CK
BA0, BA1, BA2
Bank a
t
RRD (MIN)
t
FAW (MIN)
DON’T CARE
Note:
8-bank DDR2-533 (-37E, x4 or x8), tCK = 3.75ns, BL = 4, AL = 3, CL = 4, tRRD (MIN) = 7.5ns,
FAW (MIN) = 37.5ns.
t
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
READ Command
The READ command is used to initiate a burst read access to an active row. The value on
the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where i =
A9 for x16, A9 for x8, or A9, A11 for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the READ burst; if auto
precharge is not selected, the row will remain open for subsequent accesses.
READ Operation
READ bursts are initiated with a READ command, as shown in Figure 20 on page 42. The
starting column and bank addresses are provided with the READ command and auto
precharge is either enabled or disabled for that burst access. If auto precharge is
enabled, the row being accessed is automatically precharged at the completion of the
burst. If auto precharge is disabled, the row will be left open after the completion of the
burst.
During READ bursts, the valid data-out element from the starting column address will
be available READ latency (RL) clocks later. RL is defined as the sum of AL and CL;
RL = AL + CL. The value for AL and CL are programmable via the MR and EMR
commands, respectively. Each subsequent data-out element will be valid nominally at
the next positive or negative clock edge (i.e., at the next crossing of CK and CK#).
Figure 22 on page 43 shows examples of RL based on different AL and CL settings.
DQS/DQS# is driven by the DDR2 SDRAM along with output data. The initial LOW state
on DQS and HIGH state on DQS# is known as the read preamble (tRPRE). The LOW state
on DQS and HIGH state on DQS# coincident with the last data-out element is known as
the read postamble (tRPST).
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window are depicted in Figure 31 on page 51 and
Figure 32 on page 52. A detailed explanation of tDQSCK (DQS transition skew to CK) and
t
AC (data-out transition skew to CK) is shown in Figure 33 on page 53.
Data from any READ burst may be concatenated with data from a subsequent READ
command to provide a continuous flow of data. The first data element from the new
burst follows the last element of a completed burst. The new READ command should be
issued x cycles after the first READ command, where x equals BL / 2 cycles. This is shown
in Figure 23 on page 44.
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READ Command
Figure 20:
READ Command
CK#
CK
CKE
CS#
RAS#
CAS#
WE#
ADDRESS
Col
ENABLE
AUTO PRECHARGE
A10
DISABLE
BANK ADDRESS
Bank
DON’T CARE
Figure 21:
CK#
Example: Meeting tRRD (MIN) and tRCD (MIN)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
CK
COMMAND
ADDRESS
BA0, BA1, BA2
Row
Row
Bank x
Col
Bank y
Bank y
tRRD
tRCD
DON’T CARE
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READ Command
Figure 22:
READ Latency
T0
T1
T2
T3
T3n
READ
NOP
NOP
NOP
T4
T4n
T5
CK#
CK
COMMAND
ADDRESS
NOP
NOP
Bank a,
Col n
RL = 3 (AL = 0, CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
CK#
CK
COMMAND
ADDRESS
NOP
Bank a,
Col n
CL = 3
AL = 1
RL = 4 (AL = 1 + CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK#
CK
COMMAND
ADDRESS
NOP
NOP
Bank a,
Col n
RL = 4 (AL = 0, CL = 4)
DQS, DQS#
DQ
DO
n
DON’T CARE
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
1.
2.
3.
4.
TRANSITIONING DATA
DO n = data-out from column n.
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Shown with nominal tAC, tDQSCK, and tDQSQ.
43
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 23:
Consecutive READ Bursts
T0
T1
T2
T3
COMMAND
READ
NOP
READ
NOP
ADDRESS
Bank,
Col n
T3n
T4
T4n
T5n
T5
T6n
T6
CK#
CK
NOP
NOP
NOP
Bank,
Col b
t
CCD
RL = 3
DQS, DQS#
DO
n
DQ
T0
T1
T2
COMMAND
READ
NOP
READ
ADDRESS
Bank,
Col n
T2n
T3
CK#
DO
b
T3n
T4
T4n
T5
T5n
T6n
T6
CK
NOP
NOP
NOP
NOP
Bank,
Col b
t
CCD
RL = 4
DQS, DQS#
DO
n
DQ
DON’T CARE
Notes:
1.
2.
3.
4.
5.
6.
DO
b
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b).
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Three subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies only when READ commands are issued to same device.
Nonconsecutive read data is illustrated in Figure 24 on page 45. Full-speed random read
accesses within a page (or pages) can be performed. DDR2 SDRAM supports the use of
concurrent auto precharge timing, shown in Table 10 on page 46.
DDR2 SDRAM does not allow interrupting or truncating of any READ burst using BL = 4
operations. Once the BL = 4 READ command is registered, it must be allowed to
complete the entire READ burst. However, a READ (with auto precharge disabled) using
BL = 8 operation may be interrupted and truncated only by another READ burst as long
as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of
DDR2 SDRAM. READ burst BL = 8 operations may not be interrupted or truncated with
any command except another READ command, as shown in Figure 25 on page 45.
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
44
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 24:
Nonconsecutive READ Bursts
T0
T1
T2
T3
COMMAND
READ
NOP
NOP
READ
ADDRESS
Bank,
Col n
CK#
T3n
T4
T4n
T5
T6
T6n
NOP
NOP
T7
T7n
T8
CK
NOP
NOP
NOP
Bank,
Col b
CL = 3
DQS, DQS#
DO
n
DQ
DO
b
T4n
T0
T1
T2
T3
T4
COMMAND
READ
NOP
NOP
READ
NOP
ADDRESS
Bank,
Col n
CK#
T5
T5n
T6
T7
T7n
NOP
NOP
T8
CK
NOP
NOP
Bank,
Col b
CL = 4
DQS, DQS#
DO
n
DQ
DON’T CARE
Notes:
Figure 25:
CK#
T0
1.
2.
3.
4.
5.
6.
DO
b
TRANSITIONING DATA
DO n (or b) = data-out from column n (or column b).
BL = 4.
Three subsequent elements of data-out appear in the programmed order following DO n.
Three subsequent elements of data-out appear in the programmed order following DO b.
Shown with nominal tAC, tDQSCK, and tDQSQ.
Example applies when READ commands are issued to different devices or nonconsecutive
READs.
READ Interrupted by READ
T1
T2
T3
T4
T5
T6
T7
T8
T9
READ3
NOP5
VALID
VALID
VALID
VALID
VALID
VALID
CK
COMMAND
READ1
ADDRESS
VALID2
NOP5
VALID2
VALID4
A10
DQS, DQS#
DQ
CL = 3 (AL = 0)
tCCD
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
CL = 3 (AL = 0)
TRANSITIONING DATA
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
DOUT
DON’T CARE
1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. READ command can be issued to any valid bank and row address (READ command at T0 and
T2 can be either same bank or different bank).
3. Interrupting READ command must be issued exactly 2 x tCK from previous READ.
4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interrupting READ command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
banks used for READs at T0 and T2.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.
45
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Table 10:
READ Using Concurrent Auto Precharge
From
Command
(Bank n)
To Command
(Bank m)
Minimum Delay (with
Concurrent Auto Precharge)
READ with
auto
precharge
READ or READ with auto precharge
WRITE or WRITE with auto precharge
PRECHARGE or ACTIVE
BL/2
(BL/2) + 2
1
Units
t
CK
CK
t
CK
t
Data from any READ burst must be completed before a subsequent WRITE burst is
allowed. An example of a READ burst followed by a WRITE burst is shown in Figure 28 on
page 48. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle
time. (tDQSS [MIN] and tDQSS [MAX] are defined in Figure 35 on page 56.)
A READ burst may be followed by a PRECHARGE command to the same bank, provided
that auto precharge was not activated. The minimum READ-to-PRECHARGE command
spacing to the same bank is AL + BL/2 clocks and must also satisfy a minimum analog
time from the rising clock edge that initiates the last 4-bit prefetch of a READ-toPRECHARGE command. This READ-to-PRECHARGE time is called tRTP. For BL = 4 this
is the time from the actual READ (AL after the READ command) to PRECHARGE
command. For BL = 8 this is the time from AL + 2CK after the READ-to-PRECHARGE
command. Following the PRECHARGE command, a subsequent command to the same
bank cannot be issued until tRP is met.
Note:
Part of the row precharge time is hidden during the access of the last data elements.
Examples of READ-to-PRECHARGE are shown in Figure 26 on page 47 for BL = 4 and
Figure 27 on page 47 for BL = 8. The delay from READ-to-PRECHARGE command to the
same bank is AL + BL/2 + MAX (tRTP/tCK or 2CK) - 2CK.
If A10 is HIGH when a READ command is issued, the READ with auto precharge function
is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising edge,
which is AL + (BL/2) cycles later than the READ with auto precharge command if tRAS
(MIN) and tRTP are satisfied. If tRAS (MIN) is not satisfied at the edge, the start point of
auto precharge operation will be delayed until tRAS (MIN) is satisfied. If tRTP (MIN) is
not satisfied at the edge, the start point of the auto precharge operation will be delayed
until tRTP (MIN) is satisfied. In case the internal precharge is pushed out by tRTP, tRP
starts at the point where the internal precharge happens (not at the next rising clock
edge after this event). For BL = 4, the minimum time from READ with auto precharge to
the next ACTIVATE command becomes AL + (tRTP + tRP)*, shown in Figure 26 on
page 47; for BL = 8, the time from READ with auto precharge to the next ACTIVATE
command is AL + 2 clocks + (tRTP + tRP)*, shown in Figure 27 on page 47. The * indicates
each parameter term is divided by tCK and rounded up to the next integer. In any event,
internal precharge does not start earlier than two clocks after the last 4-bit prefetch.
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
46
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 26:
READ-to-PRECHARGE – BL = 4
CK#
4-bit
prefetch
T1
T0
T2
T3
T4
T5
T6
T7
NOP
PRECHG
NOP
NOP
ACTIVE
NOP
CK
COMMAND
NOP
READ
AL + BL/2 + MAX(tRTP/tCK or 2CK) - 2CK
ADDRESS
Bank a
A10
Bank a
Bank a
Valid
Valid
CL = 3
AL = 1
DQS, DQS#
≥tRTP (MIN)
DQ
DOUT
≥tRAS (MIN)
DOUT
DOUT
DOUT
≥tRP (MIN)
≥tRC (MIN)
TRANSITIONING DATA
Notes:
Figure 27:
1.
2.
3.
DON’T CARE
RL = 4 (AL = 1, CL = 3); BL = 4.
≥ 2 clocks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
tRTP
READ-to-PRECHARGE – BL = 8
CK#
CK
COMMAND
first 4-bit
prefetch
T1
T0
READ
NOP
second 4-bit
prefetch
T3
T2
NOP
NOP
T4
T5
T6
T7
T8
NOP
PRECHG
NOP
NOP
ACTIVE
AL + BL/2 + MAX(tRTP/tCK or 2CK) -2CK
ADDRESS
Bank a
A10
AL = 1
Bank a
Bank a
Valid
Valid
CL = 3
DQS, DQS#
DQ
DOUT
≥tRTP (MIN)
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
≥tRP (MIN)
≥tRAS (MIN)
≥tRC (MIN)
TRANSITIONING DATA
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
1.
2.
3.
DON’T CARE
RL = 4 (AL = 1, CL = 3); BL = 8.
≥ 2 clocks.
Shown with nominal tAC, tDQSCK, and tDQSQ.
tRTP
47
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 28:
CK#
CK
COMMAND
READ-to-WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
WRITE
WRITEn
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
tRCD = 3
WL = RL - 1 = 4
DOUT
n
DQ
AL = 2
CL = 3
DOUT
n+1
DOUT
n+2
DOUT
n+3
DIN
n
DIN
n+1
DIN
n+2
DIN
n+3
RL = 5
TRANSITIONING DATA
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
DON’T CARE
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal tAC, tDQSCK, and tDQSQ.
48
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 29:
CK#
Bank Read – without Auto Precharge
T1
T0
T2
CK
tCK
tCH
T3
T4
NOP6
READ2
T5
T6
T7
T7n
T8
T8n
tCL
CKE
COMMAND5
NOP6
ACT
NOP6
PRE7
NOP6
NOP6
NOP6
ACT
tRTP 8
ADDRESS5
RA
Col n
A105
RA
3
RA
ALL BANKS
RA
ONE BANK
BA0, BA1, BA2
Bank x
Bank x4
Bank x
tRCD
Bank x
CL = 3
tRP
tRAS7
tRC
DM
tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
9
DQS, DQS#
tRPST
9
tRPRE
tLZ (MIN)
DO
n
DQ1
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
9
tRPRE
tHZ (MIN)
tAC (MIN)
tDQSCK (MAX)
tRPST
9
DQS, DQS#
tLZ (MAX)
DQ1
DO
n
tLZ (MIN)
tAC (MAX)
DON’T CARE
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
tHZ (MAX)
TRANSITIONING DATA
1. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. The PRECHARGE command can only be applied at T6 if tRAS (MIN) is met.
8. READ-to-PRECHARGE = AL + BL/2 + (tRTP - 2 clocks).
9. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
49
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 30:
CK#
Bank Read – with Auto Precharge
T1
T0
T2
T3
T4
T5
T6
T7
NOP5
NOP5
T7n
T8
T8n
CK
tCK
tCH
tCL
CKE
COMMAND5
NOP5
ACT
NOP5
NOP5
NOP5
NOP5
ACT
Col n
RA
ADDRESS
READ2,6
RA
3
A10
BA0, BA1, BA2
RA
RA
Bank x
Bank x
Bank x
tRCD
AL = 1
CL = 3
tRTP
tRAS
tRP
tRC
DM
tDQSCK (MIN)
Case 1: tAC (MIN) and tDQSCK (MIN)
7
tRPRE
tRPST
7
DQS, DQS#
tLZ (MIN)
DO
n
DQ1
tLZ (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
7
tRPRE
tHZ (MIN)
tAC (MIN)
tDQSCK (MAX)
tRPST
7
DQS, DQS#
tLZ (MAX)
DQ1
DO
n
4-bit
prefetch
t
Internal LZ (MAX)
precharge
tAC (MAX)
DON’T CARE
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
tHZ (MAX)
TRANSITIONING DATA
1. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. Enable auto precharge.
4. ACT = ACTIVE, RA = row address, BA = bank address.
5. NOP commands are shown for ease of illustration; other commands may be valid at these
times.
6. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN)
have been satisfied.
7. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
50
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 31:
x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
T2
T2n
T3
T3n
T4
CK#
CK
tHP5
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
tHP5
tHP5
tDQSQ3
tDQSQ3
DQS#
DQS1
DQ (Last data valid)
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)
tQH4
tQH4
DQ (Last data valid)
T2
T2n
T3
T3n
DQ (First data no longer valid)
T2
T2n
T3
T3n
All DQs and DQS, collectively6
T2
T2n
T3
T3n
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
Data
Valid
Window
Earliest signal transition
Latest signal transition
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at
T2n are “early DQS,” at T3 are “nominal DQS,” and at T3n are “late DQS.”
2. DQ0, DQ1, DQ2, DQ3 for x4 or DQ0–DQ7 for x8.
3. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is defined as tQH - tDQSQ.
51
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 32:
x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window
CK#
T1
T2
T2n
T3
T3n
T4
CK
tHP5
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tQH4
tQH4
tHP5
tHP5
tDQSQ3
tDQSQ3
LDSQ#
LDQS1
Lower Byte
DQ (Last data valid)2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)2
tQH4
tQH4
DQ (Last data valid)2
T2
T2n
T3
T3n
DQ (First data no longer valid)2
T2
T2n
T3
T3n
DQ0–DQ7 and LDQS, collectively6
T2
T2n
T3
T3n
Data Valid
Window
Data Valid
Window
Data Valid
Window
tDQSQ3
Data Valid
Window
tDQSQ3
tDQSQ3
tDQSQ3
UDQS#
UDQS1
Upper Byte
DQ (Last data valid)7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (First data no longer valid)7
tQH4
tQH4
tQH4
DQ (Last data valid)7
T2
T2n
DQ (First data no longer valid)7
T2
T2n
DQ8–DQ15 and UDQS, collectively6
T2
T2n
Data Valid
Window
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Data Valid
Window
tQH4
T3
T3
T3n
T3n
T3
T3n
Data Valid
Window
Data Valid
Window
1. DQ transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower
byte, and UDQS defines the upper byte.
2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
3. tDQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.
6. The data valid window is derived for each DQS transition and is tQH - tDQSQ.
7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
52
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1Gb: x4, x8, x16 DDR2 SDRAM
READ Command
Figure 33:
Data Output Timing – tAC and tDQSCK
T07
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
T7
CK#
CK
tDQSCK1 (MIN)
tLZ (MIN)
DQS#/DQS, or
LDQS#/LDQS / UDQ#/UDQS2
tHZ (MAX)
tDQSCK1 (MAX)
tRPST
tRPRE
DQ (Last data valid)
T3
T3n
T4
T4n
T5
T5n
T6
T6n
DQ (First data valid)
T3
T3n
T4
T4n
T5
T5n
T6
T6n
All DQs, collectively3
T3
T3n
T4
T4n
T5
T5n
T6
T6n
tLZ (MIN)
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
tAC4 (MIN)
tAC4 (MAX)
tHZ (MAX)
1. tDQSCK is the DQS output window relative to CK and is the “long-term” component of DQS
skew.
2. DQ transitioning after DQS transitions define tDQSQ window.
3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC.
4. tAC is the DQ output window relative to CK and is the “long term” component of DQ skew.
5. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.
6. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.
7. READ command with CL = 3, AL = 0 issued at T0.
8. I/O balls, when entering or exiting HIGH-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
53
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
WRITE Command
The WRITE command is used to initiate a burst write access to an active row. The value
on the BA2–BA0 inputs selects the bank, and the address provided on inputs A0–i (where
i = A9 for x8 and x16; or A9, A11 for x4) selects the starting column location. The value on
input A10 determines whether or not auto precharge is used. If auto precharge is
selected, the row being accessed will be precharged at the end of the WRITE burst; if
auto precharge is not selected, the row will remain open for subsequent accesses.
Figure 34:
WRITE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ADDRESS
CA
EN AP
A10
DIS AP
BANK ADDRESS
BA
DON’T CARE
Note:
CA = column address; BA = bank address; EN AP = enable auto precharge; and DIS AP = disable auto precharge.
Input data appearing on the DQ is written to the memory array subject to the DM input
logic level appearing coincident with the data. If a given DM signal is registered LOW, the
corresponding data will be written to memory; if the DM signal is registered HIGH, the
corresponding data inputs will be ignored, and a WRITE will not be executed to that
byte/column location (Figure 44 on page 63).
WRITE Operation
WRITE bursts are initiated with a WRITE command, as shown in Figure 34. DDR2
SDRAM uses WL equal to RL minus one clock cycle [WL = RL - 1CK = AL + (CL - 1CK)].
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst.
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
For the generic WRITE commands used in the following illustrations, auto precharge
is disabled.
54
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
During WRITE bursts, the first valid data-in element will be registered on the first rising
edge of DQS following the WRITE command, and subsequent data elements will be
registered on successive edges of DQS. The LOW state on DQS between the WRITE
command and the first rising edge is known as the write preamble; the LOW state on
DQS following the last data-in element is known as the write postamble.
The time between the WRITE command and the first rising DQS edge is WL ±tDQSS.
Subsequent DQS positive rising edges are timed, relative to the associated clock edge, as
±tDQSS. tDQSS is specified with a relatively wide range (25 percent of one clock cycle).
All of the WRITE diagrams show the nominal case, and where the two extreme cases
(tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included.
Figure 35 on page 56 shows the nominal case and the extremes of tDQSS for BL = 4. Upon
completion of a burst, assuming no other commands have been initiated, the DQ will
remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with a subsequent WRITE command to
provide continuous flow of input data. The first data element from the new burst is
applied after the last element of a completed burst. The new WRITE command should
be issued x cycles after the first WRITE command, where x equals BL/2.
Figure 36 on page 57 shows concatenated bursts of BL = 4. An example of nonconsecutive WRITEs is shown in Figure 37 on page 57. Full-speed random write accesses within a
page or pages can be performed as shown in Figure 38 on page 58. DDR2 SDRAM
supports concurrent auto precharge options, as shown in Table 11.
DDR2 SDRAM does not allow interrupting or truncating any WRITE burst using BL = 4
operation. Once the BL = 4 WRITE command is registered, it must be allowed to
complete the entire WRITE burst cycle. However, a WRITE BL = 8 operation (with auto
precharge disabled) might be interrupted and truncated ONLY by another WRITE burst
as long as the interruption occurs on a 4-bit boundary, due to the 4n prefetch architecture of DDR2 SDRAM. WRITE burst BL = 8 operations may not be interrupted or truncated with any command except another WRITE command, as shown in Figure 39 on
page 58.
Data for any WRITE burst may be followed by a subsequent READ command. To follow a
WRITE, tWTR should be met, as shown in Figure 40 on page 59. The number of clock
cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is greater. Data for any
WRITE burst may be followed by a subsequent PRECHARGE command. tWR must be
met, as shown in Figure 41 on page 60. tWR starts at the end of the data burst, regardless
of the data mask condition.
Table 11:
WRITE Using Concurrent Auto Precharge
From Command
(Bank n)
WRITE with auto
precharge
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1GbDDR2_2.fm - Rev. K 4/06 EN
Minimum Delay
(with concurrent
auto precharge)
To Command
(Bank m)
READ or READ with auto
precharge
WRITE or WRITE with
auto precharge
PRECHARGE or ACTIVE
55
(CL - 1) + (BL/2) +
tWTR
Units
tCK
(BL/2)
tCK
1
tCK
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 35:
WRITE Burst
T0
T1
T2
COMMAND
WRITE
NOP
NOP
ADDRESS
Bank a,
Col b
T2n
T3
T3n
T4
CK#
CK
tDQSS (NOM)
NOP
WL ± tDQSS
NOP
5
DQS, DQS#
DI
b
DQ
DM
tDQSS (MIN)
WL - tDQSS
tDQSS 5
DQS, DQS#
DI
b
DQ
DM
tDQSS (MAX)
tDQSS
WL + tDQSS
5
DQS, DQS#
DI
b
DQ
DM
DON’T CARE
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
TRANSITIONING DATA
1. DI b = data-in for column b.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
4. A10 is LOW with the WRITE command (auto precharge is disabled).
5. Subsequent rising DQS signals must align to the clock within tDQSS.
56
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 36:
Consecutive WRITE-to-WRITE
CK#
T0
T1
WRITE
NOP
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
COMMAND
WRITE
NOP
NOP
NOP
6
6
NOP
t
CCD
WL = 2
WL = 2
ADDRESS
Bank,
Col n
Bank,
Col b
t
WL ± tDQSS
DQSS (NOM)
6
DQS, DQS#
DI
b
DQ
DI
n
DM
DON’T CARE
Notes:
Figure 37:
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
Nonconsecutive WRITE-to-WRITE
CK#
T0
T1
T2
WRITE
NOP
NOP
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CK
COMMAND
WRITE
t
DQSS (NOM)
NOP
NOP
6
6
WL = 2
WL = 2
ADDRESS
NOP
Bank,
Col b
Bank,
Col n
WL ± tDQSS
6
DQS, DQS#
DI
n
DI
b
DQ
DM
DON’T CARE
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
57
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 38:
Random WRITE Cycles
CK#
T0
T1
T1n
WRITE
NOP
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
COMMAND
WRITE
NOP
NOP
NOP
6
6
NOP
t
CCD
WL = 2
WL = 2
ADDRESS
Bank,
Col n
Bank,
Col b
t
WL ± tDQSS
DQSS (NOM)
6
DQS, DQS#
DI
b
DQ
DI
n
DM
DON’T CARE
Notes:
Figure 39:
CK#
CK
COMMAND
ADDRESS
TRANSITIONING DATA
1. DI b, etc. = data-in for column b, etc.
2. Three subsequent elements of data-in are applied in the programmed order following
DI b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI n.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. Each WRITE command may be to any bank.
6. Subsequent rising DQS signals must align to the clock within tDQSS.
WRITE Interrupted by WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE1
a
NOP5
WRITE3
b
NOP5
NOP5
NOP5
NOP5
VALID6
VALID6
VALID6
VALID2
VALID2
VALID4
A10
8
8
8
8
8
DQS, DQS#
DQ
WL = 3
2 clock requirement
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
DIN
a
DIN
a+1
DIN
a+2
DIN
a+3
DIN
b
DIN
b+1
DIN
b+2
DIN
b+3
DIN
b+4
DIN
b+5
DIN
b+6
TRANSITIONING DATA
WL = 3
DIN
b+7
DON’T CARE
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. WRITE command can be issued to any valid bank and row address (WRITE command at T0
and T2 can be either same bank or different bank).
3. Interrupting WRITE command must be issued exactly 2 x tCK from previous WRITE.
4. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interrupting WRITE command.
5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to
banks used for WRITEs at T0 and T2.
6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR starts
with T7 and not T5 (since BL = 8 from MR and not the truncated length).
7. Example shown uses AL = 0; CL = 4, BL = 8.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 40:
WRITE-to-READ
T0
T1
T2
COMMAND
WRITE
NOP
NOP
ADDRESS
Bank a,
Col b
CK#
T2n
T3
T3n
T4
T5
T6
T7
T8
READ
NOP
NOP
T9
T9n
CK
tDQSS (NOM)
NOP
NOP
NOP
tWTR7
NOP
Bank a,
Col n
WL ± tDQSS
CL = 3
8
DQS, DQS#
DI
b
DQ
DIN
DM
tDQSS (MIN)
WL - tDQSS
CL = 3
8
DQS, DQS#
DI
b
DQ
DIN
DM
tDQSS (MAX)
WL + tDQSS
CL = 3
8
DQS, DQS#
DI
b
DQ
DIN
DM
DON’T CARE
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
TRANSITIONING DATA
1.
2.
3.
4.
5.
6.
DI b = data-in for column b; DOUT n = data-out from column n.
BL = 4, AL = 0, CL = 3; thus, WL = 2.
One subsequent element of data-in is applied in the programmed order following DI b.
tWTR is referenced from the first positive CK edge after the last data-in pair.
A10 is LOW with the WRITE command (auto precharge is disabled).
The number of clock cycles required to meet tWTR is either 2 or tWTR/tCK, whichever is
greater.
7. tWTR is required for any READ following a WRITE to the same device, but it is not required
between module ranks.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
59
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 41:
WRITE-to-PRECHARGE
T0
T1
T2
WRITE
NOP
NOP
CK#
T2n
T3
T3n
T4
T5
T6
T7
NOP
NOP
NOP
PRE7
CK
COMMAND
NOP
tWR
ADDRESS
Bank,
(a or all)
Bank a,
Col b
tDQSS (NOM)
tRP
WL + tDQSS
8
DQS#
DQS
DI
b
DQ
DM
tDQSS (MIN)
WL - tDQSS
8
DQS#
DQS
DI
b
DQ
DM
tDQSS (MAX)
WL + tDQSS
8
DQS#
DQS
DI
b
DQ
DM
DON’T CARE
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
TRANSITIONING DATA
1.
2.
3.
4.
5.
DI b = data-in for column b.
Three subsequent elements of data-in are applied in the programmed order following DI b.
BL = 4, CL = 3, AL = 0; thus, WL = 2.
tWR is referenced from the first positive CK edge after the last data-in pair.
The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case tWR is not required and the
PRECHARGE command could be applied earlier.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. PRE = PRECHARGE command.
8. Subsequent rising DQS signals must align to the clock within tDQSS.
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 42:
CK#
Bank Write – without Auto Precharge
T1
T0
T3
T4
T5
WRITE2
NOP6
NOP6
T2
CK
tCK
tCH
T5n
T6
T6n
T7
T8
T9
NOP6
NOP6
PRE
tCL
CKE
COMMAND5
NOP6
ACT
NOP6
ADDRESS
RA
Col n
A10
RA
3
NOP6
ALL BANKS
ONE BANK
BA0, BA1, BA2
Bank x
Bank x4
Bank x
tRCD
tWR
WL = 2
tRP
tRAS
WL ± tDQSS (NOM)
9
DQS, DQS#
tWPRE
tDQSL tDQSH tWPST
DI
n
DQ1
DM
DON’T CARE
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
TRANSITIONING DATA
1.
2.
3.
4.
5.
6.
DI n = data-in from column n; subsequent elements are applied in the programmed order.
BL = 4, AL = 0, and WL = 2 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T9.
PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
9. Subsequent rising DQS signals must align to the clock within tDQSS.
61
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 43:
CK#
Bank Write – with Auto Precharge
T1
T0
CK
T2
tCK
tCH
T3
T4
T5
WRITE2
NOP5
NOP5
T5n
T6
T6n
T7
T8
T9
NOP5
NOP5
NOP5
tCL
CKE
COMMAND4
NOP5
ACT
NOP5
RA
ADDRESS
NOP5
Col n
3
A10
BA0, BA1, BA2
RA
Bank x
Bank x
tRCD
WR8
WL = 2
tRP
tRAS
WL ± tDQSS (NOM)
9
DQS,DQS#
tWPRE
tDQSL tDQSH tWPST
DI
n
DQ1
DM
TRANSITIONING DATA
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
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1GbDDR2_2.fm - Rev. K 4/06 EN
DON’T CARE
DI n = data-in from column n; subsequent elements are applied in the programmed order.
BL = 4, AL = 0, and WL = 2 in the case shown.
Enable auto precharge.
ACT = ACTIVE, RA = row address, BA = bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.
tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.
WR is programmed via MR[11, 10, 9] and is calculated by dividing tWR (in nanoseconds) by
tCK and rounding up to the next integer value.
Subsequent rising DQS signals must align to the clock within tDQSS.
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 44:
CK#
CK
WRITE – DM Operation
T0
T1
T2
T3
T4
T5
T6
T6n
T7
T7n
T8
T9
NOP6
NOP6
T10
T11
tCH tCL
tCK
CKE
COMMAND5
NOP6
ACT
NOP6
WRITE2
ADDRESS
RA
Col n
A10
RA
3
NOP6
AL = 1
NOP6
WL = 2
NOP6
NOP6
NOP6
PRE
ALL BANKS
ONE BANK
BA0, BA1, BA2
Bank x
Bank x4
Bank x
tWR9
tRCD
tRPA
tRAS
WL ± tDQSS (NOM)
10
DQS, DQS#
tWPRE
DQ
tDQSL tDQSH tWPST
DI
n
1
DM
TRANSITIONING DATA
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
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1GbDDR2_2.fm - Rev. K 4/06 EN
DON’T CARE
DI n = data-in from column n; subsequent elements are applied in the programmed order.
Burst length = 4, AL = 1, and WL = 2 in the case shown.
Disable auto precharge.
“Don’t Care” if A10 is HIGH at T11.
PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.
NOP commands are shown for ease of illustration; other commands may be valid at these
times.
tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.
t
DSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.
t
WR starts at the end of the data burst regardless of the data mask condition.
Subsequent rising DQS signals must align to the clock within tDQSS.
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1Gb: x4, x8, x16 DDR2 SDRAM
WRITE Command
Figure 45:
Data Input Timing
T0
T1
T1n
T2
T2n
T3
T3n
T4
CK#
CK
tDSH1 tDSS2
WL - tDQSS (NOM)
6
DQS
DQS#
tWPRE
DQ
tDSH1 tDSS2
tDQSL tDQSH tWPST
DI
DM
TRANSITIONING DATA
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
1.
2.
3.
4.
5.
6.
DON’T CARE
tDSH
(MIN) generally occurs during tDQSS (MIN).
(MIN) generally occurs during tDQSS (MAX).
WRITE command issued at T0.
For x16, LDQS controls the lower byte and UDQS controls the upper byte.
WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
Subsequent rising DQS signals must align to the clock within tDQSS.
tDSS
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1Gb: x4, x8, x16 DDR2 SDRAM
PRECHARGE Command
PRECHARGE Command
The PRECHARGE command, illustrated in Figure 46, is used to deactivate the open row
in a particular bank or the open row in all banks. The bank(s) will be available for a
subsequent row activation a specified time (tRP) after the PRECHARGE command is
issued, except in the case of concurrent auto precharge, where a READ or WRITE
command to a different bank is allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing parameters. Once a bank has
been precharged, it is in the idle state and must be activated prior to any READ or WRITE
commands being issued to that bank. A PRECHARGE command is allowed if there is no
open row in that bank (idle state) or if the previously open row is already in the process
of precharging. However, the precharge period will be determined by the last
PRECHARGE command issued to the bank.
PRECHARGE Operation
Input A10 determines whether one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA2–BA0 select the bank. Otherwise
BA2–BA0 are treated as “Don’t Care.”
When all banks are to be precharged, inputs BA2–BA0 are treated as “Don’t Care.” Once a
bank has been precharged, it is in the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank. tRPA timing applies when the
PRECHARGE (ALL) command is issued, regardless of the number of banks already open
or closed. If a single-bank PRECHARGE command is issued, tRP timing applies. tRPA
(MIN) applies to all 8-bank DDR2 devices.
Figure 46:
PRECHARGE Command
CK#
CK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ADDRESS
ALL BANKS
A10
ONE BANK
BA2, BA0, BA1
BA
DON’T CARE
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
BA = bank address (if A10 is LOW; otherwise “Don’t Care”).
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1Gb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH Command
SELF REFRESH Command
The SELF REFRESH command can be used to retain data in the DDR2 SDRAM, even if
the rest of the system is powered down. When in the self refresh mode, the DDR2
SDRAM retains data without external clocking. All power supply inputs (including VREF )
must be maintained at valid levels upon entry/exit and during SELF REFRESH operation.
The SELF REFRESH command is initiated like a REFRESH command except CKE is LOW.
The DLL is automatically disabled upon entering self refresh and is automatically
enabled upon exiting self refresh (200 clock cycles must then occur before a READ
command can be issued). The differential clock should remain stable and meet tCKE
specifications at least 1 x tCK after entering self refresh mode. All command and address
input signals except CKE are “Don’t Care” during self refresh.
The procedure for exiting self refresh requires a sequence of commands. First, the differential clock must be stable and meet tCK specifications at least 1 x tCK prior to CKE
going back HIGH. Once CKE is HIGH (tCKE [MIN] has been satisfied with four clock
registrations), the DDR2 SDRAM must have NOP or DESELECT commands issued for
tXSNR because time is required for the completion of any internal refresh in progress. A
simple algorithm for meeting both refresh and DLL requirements is to apply NOP or
DESELECT commands for 200 clock cycles before applying any other command.
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1GbDDR2_2.fm - Rev. K 4/06 EN
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1Gb: x4, x8, x16 DDR2 SDRAM
SELF REFRESH Command
Figure 47:
Self Refresh
T0
CK#
CK1
T1
tCH
tCL
T2
Ta0
tCK1
Ta1
tCK1
Tb0
Ta2
tISXR6
Tc0
tCKE10
Td0
tIH
CKE1
COMMAND5
NOP
NOP7
REF
NOP7
VALID3
VALID3
tIH
ODT8
tAOFD / tAOFPD8
ADDRESS
VALID
VALID4
DQS#,
DQS
DQ
DM
tRP2
tXSNR3, 6, 11
tCKE (MIN)9
tXSRD4,6
Enter self refresh
mode (synchronous)
Notes:
Exit self refresh
mode (asynchronous)
DON’T CARE
Indicates a break in
time scale
1. Clock must be stable and meeting tCK specifications at least 1 x tCK after entering self
refresh mode and at least 1 x tCK prior to exiting self refresh mode.
2. Device must be in the all banks idle state prior to entering self refresh mode.
3. tXSNR is required before any non-READ command can be applied.
4. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
5. REF = REFRESH command.
6. Self refresh exit is asynchronous; however, tXSNR and tXSRD timing starts at the first rising
clock edge where CKE HIGH satisfies tISXR.
7. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0, which
allows any non-READ command.
8. ODT must be disabled and RTT off (tAOFD and tAOFPD have been satisfied) prior to entering
SELF REFRESH at state T1.
9. Once self refresh has been entered, tCKE (MIN) must be satisfied prior to exiting self refresh.
10. CKE must stay HIGH until tXSRD is met; however, if self refresh is being re-entered, CKE may
go back LOW after tXSNR is satisfied.
11. Once exiting SELF REFRESH, ODT must remain LOW until tXSRD is satisfied.
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1Gb: x4, x8, x16 DDR2 SDRAM
REFRESH Command
REFRESH Command
REFRESH is used during normal operation of the DDR2 SDRAM and is analogous to
CAS#-Before-RAS# (CBR) REFRESH. This command is nonpersistent, so it must be
issued each time a refresh is required. The addressing is generated by the internal refresh
controller. This makes the address bits a “Don’t Care” during an REFRESH command.
The 1Gb DDR2 SDRAM requires REFRESH cycles at an average interval of 7.8125µs
(MAX). To allow for improved efficiency in scheduling and switching between tasks,
some flexibility in the absolute refresh interval is provided. A maximum of eight
REFRESH commands can be posted (to defer issuing REFRESH commands) to any given
DDR2 SDRAM, meaning that the maximum absolute interval between any REFRESH
command and the next REFRESH command is 9 × 7.8125µs (70.3µs; 3.9µs for hightemperature operation). The refresh period begins when the REFRESH command is
registered and ends tRFC (MIN) later.
Figure 48:
Refresh Mode
T0
T2
T1
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
NOP2
REF
NOP2
REF5
NOP2
NOP2
ACT
CK#
CK
tCK
tCH
tCL
CKE
COMMAND1
NOP 2
NOP2
PRE
ADDRESS
RA
ALL BANKS
A101
RA
ONE BANK
BANK1
Bank(s)3
BA
DQS, DQS#4
DQ4
DM4
tRP
tRFC(MIN)
tRFC5
Indicates a break in
time scale
Notes:
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DON’T CARE
1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address.
2. NOP commands are shown for ease of illustration; other valid commands may be possible at
these times. CKE must be active during clock positive transitions.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active
(i.e., must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
5. The second REFRESH is not required and is only shown as an example of two back-to-back
REFRESH commands.
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Power-Down Mode
DDR2 SDRAMs support multiple power-down modes that allow significant power
savings over normal operating modes. CKE is used to enter and exit different powerdown modes. Power-down entry and exit timings are shown in Figure 49 on page 70.
Detailed power-down entry conditions are shown in Figures 50 through 57. The CKE
Truth Table, Table 12, is shown on page 71.
DDR2 SDRAMs require CKE to be registered HIGH (active) at all times that an access is
in progress—from the issuing of a READ or WRITE command until completion of the
burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined
when the read postamble is satisfied; for WRITEs, a burst completion is defined when
the write postamble and tWR or tWTR are satisfied, as shown in Figures 52 and 53 on
page 73. The number of clock cycles required to meet tWTR is either two or tWTR/tCK,
whichever is greater.
Power-down mode (see Figure 49 on page 70) is entered when CKE is registered LOW
coincident with a NOP or DESELECT command. CKE is not allowed to go LOW during a
mode register or extended mode register command time, or while a READ or WRITE
operation is in progress. If power-down occurs when all banks are idle, this mode is
referred to as precharge power-down. If power-down occurs when there is a row active in
any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CK, CK#, ODT, and CKE. For maximum
power savings, the DLL is frozen during precharge power-down. Exiting active powerdown requires the device to be at the same voltage and frequency as when it entered
power-down. Exiting precharge power-down requires the device to be at the same
voltage as when it entered power-down; however, the clock frequency is allowed to
change. See “Precharge Power-Down Clock Frequency Change” on page 76.
The maximum duration for either active or precharge power-down is limited by the
refresh requirements of the device tRFC (MAX). The minimum duration for power-down
entry and exit is limited by the tCKE (MIN) parameter. While in power-down mode, CKE
LOW, a stable clock signal, and stable power supply signals must be maintained at the
inputs of the DDR2 SDRAM, while all other input signals are “Don’t Care” except ODT.
Detailed ODT timing diagrams for different power-down modes are shown in Figures 60
through 67.
The power-down state is synchronously exited when CKE is registered HIGH (in
conjunction with an NOP or DESELECT command), as shown in Figure 49 on page 70.
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 49:
Power-Down
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
VALID
VALID
CK#
CK
COMMAND
tCK
VALID1
tCH
tCL
NOP
tCKE (MIN)3
tIH
CKE
tIH
tCKE (MIN)3
tIS
ADDRESS
VALID
VALID
VALID
tXP4, tXARD5
tXARDS6
DQS, DQS#
DQ
DM
Enter
power-down
mode2
Notes:
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Exit
power-down
mode
DON’T CARE
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at
least one row is already active), then the power-down mode shown is active power-down.
2. No column accesses are allowed to be in progress at the time power-down is entered. If the
DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting
power-down mode for proper READ operation.
3. tCKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock
edges. CKE must remain at the valid input level the entire time it takes to achieve the three
clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid
level during the time period of tIS + 2 x tCK + tIH. CKE must not transition during its tIS and
tIH window.
4. tXP timing is used for exit precharge power-down and active power-down to any non-READ
command.
5. tXARD timing is used for exit active power-down to READ command if fast exit is selected
via MR (bit 12 = 0).
tXARDS timing is used for exit active power-down to READ command if slow exit is selected
6.
via MR (bit 12 = 1).
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Table 12:
CKE Truth Table
Notes 1–3, 12
CKE
Current
State
Power-down
Bank(s) active
L
L
L
L
H
L
H
L
H
L
All banks idle
H
L
H
H
L
H
Self refresh
Notes:
Previous
Current
Cycle
Cycle (n)
(n-1)
Command (n)
CS#, RAS#,
CAS#, WE#
Action (n)
Notes
X
Maintain power-down
13, 14
DESELECT or NOP
Power-down exit
4, 8
X
Maintain self refresh
14
DESELECT or NOP
Self refresh exit
4, 5, 9
DESELECT or NOP
Active power-down
4, 8, 10, 11
entry
DESELECT or NOP Precharge power-down
4, 8, 10
entry
REFRESH
Self refresh entry
6, 9, 11
Shown in Table 6 on page 34
7
1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.
3. Command (n) is the command registered at clock edge n, and action (n) is a result of command (n).
4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR period. READ commands may be issued only after tXSRD (200 clocks)
is satisfied.
6. Self refresh mode can only be entered from the all banks idle state.
7. Must be a legal command, as defined in Table 6 on page 34.
8. Valid commands for power-down entry and exit are NOP and DESELECT only.
9. Valid commands for self refresh exit are NOP and DESELECT only.
10. Power-down and self refresh can not be entered while READ or WRITE operations, LOAD
MODE operations, or PRECHARGE operations are in progress. See “Power-Down Mode” on
page 69 and See “SELF REFRESH Command” on page 66 for a list of detailed restrictions.
11. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This
requires a minimum of 3 clock cycles of registration.
12. The state of ODT does not affect the states described in this table. The ODT function is not
available during self refresh. See “ODT Timing” on page 79 for more details and specific
restrictions.
13. Power-down modes do not perform any REFRESH operations. The duration of power-down
mode is therefore limited by the refresh requirements.
14. “X” means “Don’t Care” (including floating around VREF) in self refresh and power-down.
However, ODT must be driven HIGH or LOW in power-down if the ODT function is enabled
via EMR(1).
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 50:
CK#
READ to Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
VALID
VALID
T7
CK
COMMAND
NOP2
tCKE (MIN)
CKE
ADDRESS
VALID
A10
DQS, DQS#
DQ
DOUT
RL = 3
DOUT
DOUT
DOUT
Power-down1
or self refresh
entry
Notes:
Figure 51:
CK#
DON’T CARE
TRANSITIONING DATA
1. Power-down or self refresh entry may occur after the READ burst completes.
2. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
READ with Auto Precharge to Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
VALID
VALID
NOP2
T7
CK
COMMAND
tCKE (MIN)
CKE
ADDRESS
VALID
A10
DQS, DQS#
DQ
RL = 3
DOUT
DOUT
DOUT
DOUT
Power-down
TRANSITIONING DATA or self refresh1
entry
Notes:
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DON’T CARE
1. Power-down or self refresh entry may occur after the READ burst completes.
2. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 52:
T0
T1
T2
T3
T4
T5
T6
T7
WRITE
NOP
NOP
NOP
VALID
VALID
VALID
NOP1
CK#
CK
COMMAND
WRITE to Power-Down or Self-Refresh Entry
T8
tCKE (MIN)
CKE
ADDRESS
VALID
A10
DQS, DQS#
DQ
DOUT
WL = 3
DOUT
DOUT
DOUT
tWTR
TRANSITIONING DATA
Notes:
Figure 53:
CK#
CK
COMMAND
Power-down
or self refresh
entry1
DON’T CARE
1. Power-down or self refresh entry may occur after the WRITE burst completes.
WRITE with Auto Precharge to Power-Down or Self Refresh Entry
T0
T1
T2
T3
T4
T5
Ta0
Ta1
WRITE
NOP
NOP
NOP
VALID
VALID
VALID2
NOP
Ta2
tCKE (MIN)
CKE
ADDRESS
VALID
A10
DQS, DQS#
DQ
DOUT
WL = 3
DOUT
DOUT
DOUT
WR1
TRANSITIONING DATA
Notes:
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DON’T CARE
Indicates a break in
time scale
Power-down
or self refresh
entry
1. WR is programmed through MR[9, 10, 11] and represents (tWR [MIN] ns / tCK) rounded up
to next integer tCK.
2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur
1 x tCK later at Ta1, prior to tRP being satisfied.
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 54:
REFRESH Command to Power-Down Entry
CK#
T0
T1
T2
VALID
REFRESH
NOP
T3
CK
COMMAND
t
CKE (MIN)
CKE
1 x tCK
DON’T CARE
Power-down1
entry
Notes:
Figure 55:
1. The earliest precharge power-down entry may occur is at T2 which is 1 x tCK after the
REFRESH command. Precharge power down entry occurs prior to tRFC (MIN) being satisfied.
ACTIVE Command to Power-Down Entry
CK#
T0
T1
T2
VALID
ACTIVE
NOP
T3
CK
COMMAND
ADDRESS
VALID
tCKE (MIN)
CKE
1 tCK
DON’T CARE
Power-down1
entry
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
1. The earliest active power-down entry may occur is at T2, which is 1 x tCK after the ACTIVE
command. Active power-down entry occurs prior to tRCD (MIN) being satisfied.
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1Gb: x4, x8, x16 DDR2 SDRAM
Power-Down Mode
Figure 56:
PRECHARGE Command to Power-Down Entry
CK#
T0
T1
T2
VALID
PRECHARGE
NOP
T3
CK
COMMAND
ADDRESS
VALID
ALL BANKS
vs
SINGLE BANK
A10
tCKE
(MIN)
CKE
1 x tCK
Power-down1
entry
Notes:
Figure 57:
DON’T CARE
1. The earliest precharge power-down entry may occur is at T2, which is 1 x tCK after the PRECHARGE command. Precharge power-down entry occurs prior to tRP (MIN) being satisfied.
LOAD MODE Command to Power-Down Entry
T0
T1
T2
T3
LM
NOP
NOP
T4
CK#
CK
COMMAND
VALID
VALID3
ADDRESS
tCKE (MIN)
CKE
tRP2
tMRD
Power-down1
entry
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
DON’T CARE
1. The earliest precharge power-down entry is at T3, which is after tMRD is satisfied.
2. All banks must be in the precharged state and tRP met prior to issuing LM command.
3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
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1Gb: x4, x8, x16 DDR2 SDRAM
Precharge Power-Down Clock Frequency Change
Precharge Power-Down Clock Frequency Change
When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off
and CKE must be at a logic LOW level. A minimum of two differential clock cycles must
pass after CKE goes LOW before clock frequency may change. The device input clock
frequency is allowed to change only within minimum and maximum operating frequencies specified for the particular speed grade. During input clock frequency change, ODT
and CKE must be held at stable LOW levels. Once the input clock frequency is changed,
new stable clocks must be provided to the device before precharge power-down may be
exited, and DLL must be reset via EMR after precharge power-down exit. Depending on
the new clock frequency, an additional LM command might be required to appropriately
set the WR MR[11, 10, 9]. During the DLL relock period of 200 cycles, ODT must remain
off. After the DLL lock time, the DRAM is ready to operate with a new clock frequency.
Figure 58:
Input Clock Frequency Change During Precharge Power-Down Mode
PREVIOUS CLOCK FREQUENCY
T0
T1
T2
NEW CLOCK FREQUENCY
T3
Ta1
Ta0
Ta2
Ta3
Ta4
Tb0
NOP
VALID
CK#
CK
tCH
tCH
tCL
tCL
tCK
tCK
2 x tCK (MIN)2
1 x tCK (MIN)3
tCKE (MIN)4
CKE
COMMAND
ADDR
tCKE (MIN)4
VALID1
NOP
NOP
NOP
VALID
LM
DLL RESET
VALID
tXP
ODT
DQS, DQS#
High-Z
DQ
High-Z
DM
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
200 x tCK
Indicates a break in
time scale
Notes:
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DON’T CARE
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down, which is required prior to the clock
frequency change.
2. A minimum of 2 x tCK is required after entering precharge power-down prior to changing
clock frequencies.
3. Once the new clock frequency has changed and is stable, a minimum of 1 x tCK is required
prior to exiting precharge power-down.
4. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE LOW time is tCKE = 3 x tCK. This
requires a minimum of three clock cycles of registration.
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1Gb: x4, x8, x16 DDR2 SDRAM
RESET Function
RESET Function
(CKE LOW Anytime)
DDR2 SDRAM applications may go into a reset state anytime during normal operation.
If an application enters a reset condition, CKE is used to ensure the DDR2 SDRAM
device resumes normal operation after re-initializing. All data will be lost during a reset
condition; however, the DDR2 SDRAM device will continue to operate properly if the
following conditions outlined in this section are satisfied.
The reset condition defined here assumes all supply voltages (VDD, VDDQ, VDDL, and
VREF ) are stable and meet all DC specifications prior to, during, and after the RESET
operation. All other input pins of the DDR2 SDRAM device are a “Don’t Care” during
RESET with the exception of CKE.
If CKE asynchronously drops LOW during any valid operation (including a READ or
WRITE burst), the memory controller must satisfy the timing parameter tDELAY before
turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM before
CKE is raised HIGH, at which time the normal initialization sequence must occur. See
“Initialization” on page 21. The DDR2 SDRAM device is now ready for normal operation
after the initialization sequence. Figure 59 on page 78 shows the proper sequence for a
RESET operation.
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1Gb: x4, x8, x16 DDR2 SDRAM
RESET Function
Figure 59:
RESET Function
T0
T1
T2
T3
T4
T5
Tb0
Ta0
tCK
CK#
CK
tCL
tDELAY
tCL
tCKE (MIN)
6
CKE
ODT
COMMAND2
READ
NOP1
READ
NOP1
NOP1
NOP1
PRE
DM3
ADDRESS
Col n
Col n
ALL BANKS
A10
BA0, BA1, BA2
Bank a
DQS3
High-Z
DQ3
High-Z
Bank b
5
High-Z
DOUT
High-Z
DOUT DOUT
High-Z
RTT
System
RESET
T = 400ns (MIN)
tRP
A
Start of normal4
initialization
sequence
Indicates a break in
time scale
Notes:
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Unknown
RTT ON
DON’T CARE
TRANSITIONING DATA
1. Either NOP or DESELECT command may be applied.
2. PRE = PRECHARGE command.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4, x8, x16).
4. Initialization timing is shown in Figure 10 on page 21.
5. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the completion of the burst.
6. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
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1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
ODT Timing
Once a 12ns delay (tMOD) has been satisfied, and after the ODT function has been
enabled via the EMR LOAD MODE command, ODT can be accessed under two timing
categories. ODT will operate in either synchronous mode or asynchronous mode,
depending on the state of CKE. ODT can switch anytime except during self refresh mode
and a few clocks after being enabled via EMR, as shown in Figure 60 on page 80.
There are two timing categories for ODT—turn-on and turn-off. During active mode
(CKE HIGH) and fast-exit power-down mode (any row of any bank open, CKE LOW,
MR[12 = 0]), tAOND, tAON, tAOFD, and tAOF timing parameters are applied, as shown in
Figure 62 on page 81 and Table 13 on page 81.
During slow-exit power-down mode (any row of any bank open, CKE LOW, MR[12] = 1)
and precharge power-down mode (all banks/rows precharged and idle, CKE LOW),
tAONPD and tAOFPD timing parameters are applied, as shown in Figure 63 on page 82
and Table 14 on page 82.
ODT turn-off timing, prior to entering any power-down mode, is determined by the
parameter tANPD (MIN), as shown in Figure 64 on page 83. At state T2, the ODT HIGH
signal satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD
(MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 64 on page 83 also
shows the example where tANPD (MIN) is not satisfied since ODT HIGH does not occur
until state T3. When tANPD (MIN) is not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing prior to entering any power-down mode is determined by the
parameter tANPD, as shown in Figure 65 on page 84. At state T2, the ODT HIGH signal
satisfies tANPD (MIN) prior to entering power-down mode at T5. When tANPD (MIN) is
satisfied, tAOND and tAON timing parameters apply. Figure 65 also shows the example
where tANPD (MIN) is not satisfied since ODT HIGH does not occur until state T3. When
tANPD (MIN) is not satisfied, tAONPD timing parameters apply.
ODT turn-off timing after exiting any power-down mode is determined by the parameter
tAXPD (MIN), as shown in Figure 66 on page 85. At state Ta1, the ODT LOW signal satis-
fies tAXPD (MIN) after exiting power-down mode at state T1. When tAXPD (MIN) is satisfied, tAOFD and tAOF timing parameters apply. Figure 66 also shows the example where
t
AXPD (MIN) is not satisfied since ODT LOW occurs at state Ta0. When tAXPD (MIN) is
not satisfied, tAOFPD timing parameters apply.
ODT turn-on timing after exiting either slow-exit power-down mode or precharge
power-down mode is determined by the parameter tAXPD (MIN), as shown in Figure 67
on page 86. At state Ta1, the ODT HIGH signal satisfies tAXPD (MIN) after exiting powerdown mode at state T1. When tAXPD (MIN) is satisfied, tAOND and tAON timing parameters apply. Figure 67 also shows the example where tAXPD (MIN) is not satisfied since
ODT HIGH occurs at state Ta0. When tAXPD (MIN) is not satisfied, tAONPD timing
parameters apply.
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1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 60:
ODT Timing for Entering and Exiting Power-Down Mode
Synchronous
Synchronous or
Synchronous
Asynchronous
tANPD (3 tCKs)
1st CKE latched LOW
tAXPD (8 tCKs)
1st CKE latched HIGH
CKE
Any mode except
self refresh mode
Any mode except
self refresh mode
Active power-down fast (synchronous)
Active power-down slow (asynchronous)
Precharge power-down (asynchronous)
Applicable modes
tAOND/tAOFD
tAOND/tAOFD
tAOND/tAOFD
(synchronous)
tAONPD/tAOFPD
(asynchronous)
Applicable timing parameters
MRS Command to ODT Update Delay
During normal operation, the value of the effective termination resistance can be
changed with an EMRS set command. tMOD (MAX) updates the RTT setting.
Figure 61:
Timing for MRS Command to ODT Update Delay
CMD
EMRS1
NOP
NOP
NOP
NOP
NOP
CK#
CK
2
ODT2
tAOFD
tMOD
tIS
0ns
Internal
RTT Setting
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
Old Setting
Undefined
New Setting
1. LM command directed to mode register, which updates the information in EMR(1)[A6, A2],
i.e., RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
tAOFD must be met before issuing the LM command; ODT must remain LOW for the entire
duration of the tMOD window, until tMOD is met.
80
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ODT Timing
Figure 62:
ODT Timing for Active or Fast-Exit Power-Down Mode
T0
CK#
CK
T1
tCK
tCH
T2
T3
T4
T5
T6
tCL
CMD
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ADDR
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
tAOND
ODT
tAOFD
RTT
tAON (MIN)
tAOF (MAX)
tAOF (MIN)
tAON (MAX)
RTT Unknown
Table 13:
RTT On
DON’T CARE
DDR2-400/533 ODT Timing for Active and Fast-Exit Power-Down Modes
Parameter
ODT turn-on delay
ODT turn-on
ODT turn-off delay
ODT turn-off
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
Symbol
Min
Max
Units
tAOND
2
tAC (MIN)
2.5
tAC (MIN)
2
tAC (MAX) + 1,000
2.5
tAC (MAX) + 600
tCK
tAON
tAOFD
tAOF
ps
tCK
ps
The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, for tAOF (MAX).
81
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1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 63:
ODT Timing for Slow-Exit or Precharge Power-Down Modes
CK#
T0
CK
T1
tCK
tCH
T2
T3
T4
T5
T6
T7
tCL
CMD
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
ADDR
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CKE
ODT
tAONPD (MAX)
tAONPD (MIN)
RTT
tAOFPD (MIN)
tAOFPD (MAX)
Transitioning RTT
Table 14:
RTT Unknown
RTT On
DON’T CARE
DDR2-400/533 ODT Timing for Slow-Exit and Precharge Power-Down Modes
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Parameter
Symbol
ODT turn-on
(power-down mode)
ODT turn-off
(power-down mode)
tAONPD
tAC
(MIN) + 2,000
tAOFPD
tAC
(MIN) + 2,000
82
Min
Max
2x
tCK
+tAC
(MAX) +
1,000
2.5 x tCK + tAC (MAX) +
1,000
Units
ps
ps
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1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 64:
ODT Turn-off Timings When Entering Power-Down Mode
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
tANPD (MIN)
CKE
tAOFD
ODT
tAOF (MAX)
RTT
tAOF (MIN)
tAOFPD (MAX)
ODT
RTT
tAOFPD (MIN)
Transitioning RTT
Table 15:
RTT Unknown
RTT On
DON’T CARE
DDR2-400/533 ODT Turn-off Timings When Entering Power-Down Mode
Parameter
ODT turn-off delay
ODT turn-off
ODT turn-off
(power-down mode)
ODT to power-down entry latency
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
Symbol
Min
tAOFD
2.5
(MIN)
tAC (MIN) +
2,000
3
tAOF
tAOFPD
t
ANPD
tAC
Max
Units
2.5
(MAX) + 600
2.5 x tCK + tAC
(MAX) + 1,000
tCK
tAC
ps
ps
t
CK
The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, for tAOF (MAX).
83
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ODT Timing
Figure 65:
ODT Turn-On Timing When Entering Power-Down Mode
CK#
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
t
ANPD (MIN)
CKE
tAOND
ODT
tAON
(MAX)
RTT
t
AON (MIN)
ODT
tAONPD
(MAX)
tAONPD
(MIN)
RTT
RTT Unknown
Transitioning RTT
Table 16:
RTT On
DON’T CARE
DDR2-400/533 ODT Turn-on Timing When Entering Power-Down Mode
Parameter
Symbol
ODT turn-on delay
ODT turn-on
ODT turn-on
(power-down mode)
ODT to power-down entry latency
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1GbDDR2_2.fm - Rev. K 4/06 EN
84
t
AOND
tAON
tAONPD
tANPD
Min
Max
2
tAC (MIN)
tAC (MIN) +
2,000
3
2
tAC (MAX) + 1,000
2 x tCK + tAC
(MAX) + 1,000
Units
t
CK
ps
ps
tCK
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1Gb: x4, x8, x16 DDR2 SDRAM
ODT Timing
Figure 66:
CK#
ODT Turn-Off Timing When Exiting Power-Down Mode
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
tAXPD (MIN)
CKE
tCKE (MIN)
tAOFD
ODT
tAOF (MAX)
RTT
tAOF (MIN)
tAOFPD (MAX)
ODT
RTT
tAOFPD (MIN)
Transitioning RTT
Table 17:
RTT Unknown
RTT On
DON’T CARE
Indicates a break in
time scale
DDR2-400/533 ODT Turn-off Timing When Exiting Power-Down Mode
Parameter
ODT turn-off delay
ODT turn-off
ODT turn-off
(power-down mode)
ODT to power-down exit latency
Note:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Symbol
Min
Max
Units
tAOFD
2.5
tAC (MIN)
t
AC (MIN) +
2,000
8
2.5
tAC (MAX) + 600
2.5 x tCK + tAC
(MAX) + 1,000
tCK
tAOF
t
AOFPD
tAXPD
ps
ps
tCK
The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock value
must be derated by the amount of half-clock duty cycle error. For example, if the clock
duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN) and 2.5 +
0.03, or 2.53, fortAOF (MAX).
85
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ODT Timing
Figure 67:
ODT Turn-on Timing When Exiting Power-Down Mode
CK#
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
COMMAND
tAXPD (MIN)
CKE
tCKE (MIN)
tAOND
ODT
tAON (MAX)
RTT
tAON (MIN)
tAONPD (MAX)
ODT
RTT
tAONPD (MIN)
Transitioning RTT
Table 18:
RTT Unknown
RTT On
Indicates a break in
time scale
DON’T CARE
DDR2-400/533 ODT Turn-On Timing When Exiting Power-Down Mode
Parameter
ODT turn-on delay
ODT turn-on
ODT turn-on
(power-down mode)
ODT to power-down exit latency
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1GbDDR2_2.fm - Rev. K 4/06 EN
86
Symbol
Min
tAOND
2
(MIN)
tAC (MIN) +
2,000
8
tAON
tAONPD
t
AXPD
tAC
Max
2
(MAX) + 1,000
2 x tCK + tAC
(MAX) + 1,000
tAC
Units
tCK
ps
ps
t
CK
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1Gb: x4, x8, x16 DDR2 SDRAM
Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 17:
Absolute Maximum DC Ratings
Parameter
Symbol
Min
Max
Units
Notes
VDD
VDD supply voltage relative to VSS
VDDQ
VDDQ supply voltage relative to VSSQ
VDDL
VDDL supply voltage relative to VSSL
VIN, VOUT
Voltage on any ball relative to VSS
II
Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls
not under test = 0V)
IOZ
Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled
IVREF
VREF leakage current; VREF = Valid VREF level
–1.0
–0.5
–0.5
–0.5
–5
2.3
2.3
2.3
2.3
5
V
V
V
V
µA
1
1, 2
1
3
–5
–2
5
2
µA
µA
Notes:
1. VDD, VDDQ, and VDDL must be within 300mV of each other at all times.
2. VREF ≤ 0.6 x VDDQ; however, VREF may be ≥ VDDQ provided that VREF ≤ 300mV.
3. Voltage on any I/O may not exceed voltage on VDDQ.
Temperature and Thermal Impedance
It is imperative that the DDR2 SDRAM device’s temperature specifications, shown in
Table 18 on page 88, be maintained in order to ensure the junction temperature is in the
proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances
correctly. The thermal impedances are listed in Table 19 on page 88 for the applicable
and available die revision and packages.
Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedances
listed below. For designs that are expected to last several years and require the flexibility
to use several designs, consider using final target theta values, rather than existing
values, to account for larger thermal impedances.
The DDR2 SDRAM device’s safe junction temperature range can be maintained when
the TCASE (TC) specification is not exceeded. In applications where the device’s ambient
temperature is too high, use of forced air and/or heat sinks may be required in order to
satisfy the case temperature specifications.
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Temperature and Thermal Impedance
Table 18:
Temperature Limits
Parameter
Storage temperature
Operating temperature – commercial
Operating temperature – industrial
Notes:
Table 19:
Package
Substrate
A
92-ball
D1
68-ball
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
2-layer
4-layer
38.3
24.7
46.6
32.8
46.6
32.8
60.0
39.0
55.0
38.0
84-ball
68-ball
84-ball
Notes:
Figure 68:
Max
Units
Notes
TSTG
TC
TC
TAMB
–55
0
–40
–40
100
85
95
85
°C
°C
°C
°C
1
2, 3
2, 3, 4
4, 5
Thermal Impedance
1
Last shrink
target2
Min
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in
Figure 68. This case temperature limit is allowed to be exceeded briefly during package
reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Parameters.”
2. MAX operating case temperature; TC is measured in the center of the package, as shown in
Figure 68.
3. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
4. Both temperature specifications must be satisfied.
5. Operating ambient temperature surrounding the package.
θ JA (°C/W)
Airflow =
0m/s
Die Rev
Symbol
θ JA (°C/W)
Airflow =
1m/s
θ JA (°C/W)
Airflow =
2m/s
θ JB (°C/W)
θ JC (°C/W)
25.3
18.1
33.5
26.1
33.5
26.1
48.0
34.0
42.0
32.0
21.3
16.0
28.7
23.3
28.7
23.3
45.0
32.0
37.0
30.0
11.8
10.8
18.3
18.0
18.3
18.0
22.0
22.0
22.0
21.0
1.7
2.5
2.5
6.0
6.0
1. Thermal resistance data is based on a number of samples from multiple lots and should be
viewed as a typical number.
2. This is an estimate; simulated number and actual results could vary.
Example Temperature Test Point Location
Test Point
Test Point
16.50
19.0
6.75
9.5
5.00
5.5
10.00
11.00
11mm x 19mm “BT” FGBA
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1GbDDR2_2.fm - Rev. K 4/06 EN
10mm x 16.5 mm “B7” FBGA
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1Gb: x4, x8, x16 DDR2 SDRAM
AC and DC Operating Conditions
AC and DC Operating Conditions
Table 20:
Recommended DC Operating Conditions (SSTL_18)
All voltages referenced to VSS
Parameter
Symbol
Min
Nom
Max
Units
Notes
Supply voltage
VDDL supply voltage
I/O supply voltage
I/O reference voltage
I/O termination voltage (system)
VDD
VDDL
VDDQ
VREF(DC)
VTT
1.7
1.7
1.7
0.49 x VDDQ
VREF(DC) - 40
1.8
1.8
1.8
0.50 x VDDQ
VREF(DC)
1.9
1.9
1.9
0.51 X VDDQ
VREF(DC) + 40
V
V
V
V
mV
1, 5
4, 5
4, 5
2
3
Notes:
Table 21:
1. VDD and VDDQ must track each other. VDDQ must be ≤ VDD.
2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±1
percent of the DC value. Peak-to-peak AC noise on VREF may not exceed ±2 percent of
VREF(DC). This measurement is to be taken at the nearest VREF bypass capacitor.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF.
4. VDDQ tracks with VDD; VDDL tracks with VDD.
5. VSSQ = VSSL = VSS.
ODT DC Electrical Characteristics
All voltages referenced to VSS
Parameter
Symbol
Min
Nom
Max
Units
Notes
RTT effective impedance value for 75Ω setting
EMR (A6, A2) = 0, 1
RTT effective impedance value for 150Ω setting
EMR (A6, A2) = 1, 0
RTT effective impedance value for 50Ω setting
EMR (A6, A2) = 1, 1
Deviation of VM with respect to VDDQ/2
RTT1(EFF)
60
75
90
Ω
1, 3
RTT2(EFF)
120
150
180
Ω
1, 3
RTT3(EFF)
40
50
60
Ω
1, 3
ΔVM
–6
6
%
2
Notes:
1. RTT1(EFF) and RTT2(EFF) are determined by separately applying VIH(AC) and VIL(AC) to the ball
being tested, and then measuring current, I(VIH(AC)), and I(VIL(AC)), respectively.
V IH ( AC ) – V IL ( AC )
R TT ( EFF ) = ------------------------------------------------------------I ( V IH ( AC ) ) – I ( V IL ( AC ) )
2. Measure voltage (VM) at tested ball with no load.
2 × VM
ΔVM = ⎛⎝ ------------------ – 1⎞⎠ × 100
V DD Q
3. IT device minimum values are derated by six percent when device operates between –40°C
and 0°C (TC).
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1GbDDR2_2.fm - Rev. K 4/06 EN
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Input Electrical Characteristics and Operating Conditions
Input Electrical Characteristics and Operating Conditions
Table 22:
Input DC Logic Levels
All voltages referenced to VSS
Parameter
Input HIGH (logic 1) voltage
Input LOW (logic 0) voltage
Table 23:
Symbol
Min
Max
Units
VIH(DC)
VIL(DC)
VREF(DC) + 125
–300
VDDQ + 300
VREF(DC) - 125
mV
mV
Input AC Logic Levels
All voltages referenced to VSS
Parameter
Input HIGH (logic 1) voltage (-5E/-37E)
Input HIGH (logic 1) voltage (-3/-3E/-25/-25E)
Input LOW (logic 0) voltage (-5E/-37E)
Input LOW (logic 0) voltage (-3/-3E/-25/-25E)
Figure 69:
Symbol
Min
Max
Units
VIH(AC)
VIH(AC)
VIL(AC)
VIL(AC)
VREF(DC) + 250
VREF(DC) + 200
–
–
–
–
VREF(DC) - 250
VREF(DC) - 200
mV
mV
mV
mV
Single-Ended Input Signal Levels
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
1,150mV
VIH(AC)
1,025mV
VIH(DC)
936mV
918mV
900mV
882mV
864mV
VREF + AC Noise
VREF + DC Error
VREF - DC Error
VREF - AC Noise
775mV
VIL(DC)
650mV
VIL(AC)
Numbers in diagram reflect nominal values.
90
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1Gb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Table 24:
Differential Input Logic Levels
All voltages referenced to VSS
Parameter
Symbol
Min
Max
Units
Notes
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross-point voltage
Input midpoint voltage
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
VMP(DC)
–300
250
500
0.50 x VDDQ - 175
850
VDDQ + 300
VDDQ + 600
VDDQ + 600
0.50 x VDDQ + 175
950
mV
mV
mV
mV
mV
1
2
3
4
5
Notes:
Figure 70:
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK,
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
2. VID(DC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS) level and VCP is the complementary input
(such as CK#, DQS#, LDQS#, UDQS#). The minimum value is equal to VIH(DC) - VIL(DC). Differential input signal levels are shown in Figure 70.
3. VID(AC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR
is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and VCP is the complementary
input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#). The minimum value is equal to VIH(AC) VIL(AC), as shown in Table 23 on page 90.
4. The typical value of VIX(AC) is expected to be about 0.5 x VDDQ of the transmitting device
and VIX(AC) is expected to track variations in VDDQ. VIX(AC) indicates the voltage at which
differential input signals must cross, as shown in Figure 70.
5. VMP(DC) specifies the input differential common mode voltage (VTR + VCP)/2 where VTR is
the true input (CK, DQS) level and VCP is the complementary input (CK#, DQS#). VMP(DC) is
expected to be approximately 0.5 x VDDQ.
Differential Input Signal Levels
VIN(DC) MAX5
2.1V
@ VDDQ = 1.8V
CP8
X
1.075V
VMP(DC)1
0.9V
0.725 V
VIX(AC) 2
VID(DC)3
VID(AC)4
X
TR8
5
VIN(DC) MIN
- 0.30V
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
1.
2.
3.
4.
5.
6.
7.
8.
This provides a minimum of 850mV to a maximum of 950mV and is expected to be VDDQ/2.
TR and CP must cross in this region.
TR and CP must meet at least VID(DC) MIN when static and is centered around VMP(DC).
TR and CP must have a minimum 500mV peak-to-peak swing.
TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.
For AC operation, all DC clock requirements must also be satisfied.
Numbers in diagram reflect nominal values (VDDQ = 1.8V).
TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
RDQS#, LDQS#, and UDQS# signals.
91
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1Gb: x4, x8, x16 DDR2 SDRAM
Input Electrical Characteristics and Operating Conditions
Table 25:
AC Input Test Conditions
Parameter
Symbol
Input setup timing measurement reference level
BA2–BA0, A0–A12 A0–A13 (A12 x16) A0–A13 A0–A14,
CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE
Input hold timing measurement reference level
BA2–BA0, A0–A12 A0–A13 (A12 x16) A0–A13 A0–A14,
CS#, RAS#, CAS#, WE#, ODT, DM, UDM, LDM, and CKE
Input timing measurement reference level (single-ended)
DQS for x4, x8; UDQS, LDQS for x16
Input timing measurement reference level (differential)
CK, CK# for x4, x8, x16
DQS, DQS# for x4, x8; RDQS, RDQS# for x8
UDQS, UDQS#, LDQS, LDQS# for x16
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
Min
Max
Units
Notes
VRS
See Note 2
1, 2, 7,
8
VRH
See Note 3
1, 3, 7,
8
VREF(DC)
VRD
VDDQ x 0.49
VDDQ x 0.51
VIX(AC)
V
V
1, 4, 7,
8
1, 5, 6,
7, 9
1. All voltages referenced to VSS.
2. Input waveform setup timing (tISb) is referenced from the input signal crossing at the
VIH(AC) level for a rising signal and VIL(AC) for a falling signal applied to the device under
test, as shown in Figure 79 on page 107.
3. Input waveform hold (tIHb) timing is referenced from the input signal crossing at the VIL(DC)
level for a rising signal and VIH(DC) for a falling signal applied to the device under test, as
shown in Figure 79 on page 107.
4. Input waveform setup timing (tDS) and hold timing (tDH) for single-ended data strobe is
referenced from the crossing of DQS, UDQS, or LDQS through the VREF level applied to the
device under test, as shown in Figure 81 on page 108.
5. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is
enabled is referenced from the cross-point of DQS/DQS#, UDQS/UDQS#, or LDQS/LDQS#, as
shown in Figure 80 on page 107.
6. Input waveform timing is referenced to the crossing point level (VIX) of two input signals
(VTR and VCP) applied to the device under test, where VTR is the “true” input signal and VCP
is the complementary input signal, as shown in Figure 82 on page 108.
7. See “Input Slew Rate Derating” on page 93.
8. The slew rate for single-ended inputs is measured from DC-level to AC-level, (VIL(DC) to
VIH(AC) on the rising edge and VIL(AC) to VIH(DC) on the falling edge. For signals referenced
to VREF, the valid intersection is where the “tangent” line intersects VREF, as shown in
Figures 72, 74, 76, and 78.
9. The slew rate for differentially ended inputs is measured from twice the DC-level to twice
the AC-level: 2 x VIL(DC) to 2 x VIH(AC) on the rising edge and 2 x VIL(AC) to 2 x VIH(DC) on the
falling edge). For example, the CK/CK# would be –250mV to +500mV for CK rising edge and
would be +250mV to –500mV for CK falling edge.
92
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Input Slew Rate Derating
For all input signals, the total tIS (setup time) and tIH (hold time) required is calculated
by adding the data sheet tIS (base) and tIH (base) value to the ΔtIS and ΔtIH derating
value, respectively. Example: tIS (total setup time) = tIS (base) + ΔtIS.
t
IS, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VREF(DC) and the first crossing of VIH(AC) MIN. Setup nominal slew rate (tIS)
for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and
the first crossing of VIL(AC) MAX.
If the actual signal is always earlier than the nominal slew rate line between shaded
“VREF(DC) to AC region,” use nominal slew rate for derating value (Figure 71 on page 95).
If the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 72 on page 96).
t
IH, the nominal slew rate for a rising signal, is defined as the slew rate between the last
crossing of VIL(DC) MAX and the first crossing of VREF(DC). tIH, nominal slew rate for a
falling signal, is defined as the slew rate between the last crossing of VIH(DC) MIN and
the first crossing of VREF(DC).
If the actual signal is always later than the nominal slew rate line between shaded “DC to
VREF(DC) region,” use nominal slew rate for derating value (Figure 73 on page 97).
If the actual signal is earlier than the nominal slew rate line anywhere between shaded
“DC to VREF(DC)) region,” the slew rate of a tangent line to the actual signal from the DC
level to VREF(DC) level is used for the derating value (Figure 74 on page 98).
Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid
input signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
For slew rates in between the values listed in Tables 26 and 27, the derating values may
obtained by linear interpolation.
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1GbDDR2_2.fm - Rev. K 4/06 EN
93
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 26:
DDR2-400/533 Setup and Hold Time Derating Values (tIS and tIH)
CK, CK# Differential Slew Rate
Command/
Address Slew
Rate (V/ns)
t
Δ IS
t
Δ IH
t
Δ IS
t
Δ IH
t
Δ IS
ΔtIH
Units
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+187
+179
+167
+150
+125
+83
0
–11
–25
–43
–67
–110
–175
–285
–350
–525
–800
–1,450
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1,125
+217
+209
+197
+180
+155
+113
+30
+19
+5
–13
–37
–80
–145
–255
–320
–495
–770
–1,420
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1,095
+247
+239
+227
+210
+185
+143
+60
+49
+35
+17
–7
–50
–115
–225
–290
–465
–740
–1,390
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1,065
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
Table 27:
2.0 V/ns
1.5 V/ns
1.0 V/ns
DDR2-667 Setup and Hold Time Derating Values (tIS and tIH)
CK, CK# Differential Slew Rate
Command/
Address Slew
Rate (V/ns)
ΔtIS
ΔtIH
ΔtIS
ΔtIH
ΔtIS
ΔtIH
Units
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.25
0.2
0.15
0.1
+150
+143
+133
+120
+100
+67
0
–5
–13
–22
–34
–60
–100
–168
–200
–325
–517
–1,000
+94
+89
+83
+75
+45
+21
0
–14
–31
–54
–83
–125
–188
–292
–375
–500
–708
–1,125
+180
+173
+163
+150
+160
+97
+30
+25
+17
+8
–4
–30
–70
–138
–170
–295
–487
–970
+124
+119
+113
+105
+75
+51
+30
+16
–1
–24
–53
–95
–158
–262
–345
–470
–678
–1,095
+210
+203
+193
+180
+160
+127
+60
+55
+47
+38
+36
0
–40
–108
–140
–265
–457
–940
+154
+149
+143
+135
+105
+81
+60
+46
+29
+6
–23
–65
–128
–232
–315
–440
–648
–1,065
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
2.0 V/ns
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1GbDDR2_2.fm - Rev. K 4/06 EN
1.5 V/ns
94
1.0 V/ns
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 71:
Nominal Slew Rate for tIS
CK
CK#
tIH
tIS
VDDQ
tIH
tIS
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
VSS
ΔTF
Setup slew rate
falling signal
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1GbDDR2_2.fm - Rev. K 4/06 EN
=
ΔTR
VREF(DC) - VIL(AC) MAX
ΔTF
95
Setup slew rate
rising signal
=
VIH(AC) MIN - VREF(DC)
ΔTR
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 72:
Tangent Line for tIS
CK
CK#
tIS
tIH
tIH
tIS
VDDQ
VIH(AC) MIN
VREF to AC
region
Nominal
line
VIH(DC) MIN
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
Nominal
line
VREF to AC
region
VIL(AC) MAX
ΔTF
ΔTR
VSS
Setup slew rate
=
rising signal
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1GbDDR2_2.fm - Rev. K 4/06 EN
96
tangent line [VIH(AC) MIN - VREF(DC)]
ΔTR
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1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 73:
Nominal Slew Rate for tIH
CK
CK#
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
VIH(DC) MIN
DC to VREF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTR
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1GbDDR2_2.fm - Rev. K 4/06 EN
97
ΔTF
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Figure 74:
Tangent Line for tIH
CK
CK#
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal line
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
Hold slew rate
=
rising signal
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1GbDDR2_2.fm - Rev. K 4/06 EN
tangent line [VREF(DC) - VIL(DC) MAX]
ΔTR
98
Hold slew rate
=
falling signal
tangent line [VIH(DC) MIN - VREF(DC)]
ΔTF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 28:
DDR2-400/533 tDS, tDH Derating Values with Differential Strobe
Notes: 1–7; all units in ps
DQS, DQS# Differential Slew Rate
DQ
Slew
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
Rate
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(V/ns) Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS ΔtDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
125
83
0
–
–
–
–
–
–
45
21
0
–
–
–
–
–
–
125
83
0
–11
–
–
–
–
–
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
45
21
0
–14
–
–
–
–
–
125
83
0
–11
–25
–
–
–
–
45
21
0
–14
–31
–
–
–
–
–
95
12
1
–13
–31
–
–
–
–
33
12
–2
–19
–42
–
–
–
–
–
24
13
–1
–19
–43
–
–
–
–
24
10
–7
–30
–59
–
–
–
–
–
25
11
–7
–31
–74
–
–
–
–
22
5
–18
–47
–89
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
23
17
–
–
–
–
5
–6
17
6
–
–
–19 –35
–7
–23
5
–11
–62 –77 –50 –65 –38 –53
–127 –140 –115 –128 –103 –116
1. For all input signals, the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 28.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
shaded “VREF(DC) to AC region,” use nominal slew rate for derating value (see Figure 75). If
the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 76).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first crossing
of VREF (DC). If the actual signal is always later than the nominal slew rate line between
shaded “DC level to VREF(DC) region,” use nominal slew rate for derating value (see
Figure 77). If the actual signal is earlier than the nominal slew rate line anywhere between
shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal from the
DC level to VREF(DC) level is used for derating value (see Figure 78).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 30 are the DQS singleended slew rate derating with DQS referenced at VREF and DQ referenced at the logic levels
t
DSb and tDHb. Table 31 provides the VREF-based fully derated values for the DQ (tDSa and
tDH ) for DDR2-667. Table 32 provides the VREF-based fully derated values for the DQ (tDS
a
a
and tDHa) for DDR2-533. Table 33 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-400.
99
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 29:
DDR2-667 tDS, tDH Derating Values with Differential Strobe
Notes: 1–7; all units in ps
DQS, DQS# Differential Slew Rate
DQ
Slew
2.8 V/ns
2.4 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
Rate
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(V/ns) Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS Δ DH Δ DS ΔtDH
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
100
63
100
63
100
63
67
42
67
42
67
42
0
0
0
0
0
0
–5
–14
–5
–14
–5
–14
–13 –31 –13 –31 –13 –31
–22 –54 –22 –54 –22 –54
–34 –83 –34 –83 –34 –83
–60 –125 –60 –125 –60 –125
–100 –188 –100 –188 –100 –188
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
112
79
12
7
–1
–10
–22
–48
–88
75
54
12
–2
–19
–42
–71
–113
–176
124
91
24
19
11
2
–10
–36
–76
87
66
24
10
–7
–30
–59
–101
–164
136
103
36
31
23
14
2
–24
–64
99
78
36
22
5
–18
–47
–89
–152
148
115
48
43
35
26
14
–12
–52
111
90
48
34
17
–6
–35
–77
–140
160
127
60
55
47
38
26
0
–40
123
102
60
46
29
6
–23
–65
–128
172
139
72
67
59
50
38
12
–28
135
114
72
58
41
18
–11
–53
–116
1. For all input signals the total tDS and tDH required is calculated by adding the data sheet
value to the derating value listed in Table 29.
2. tDS nominal slew rate for a rising signal is defined as the slew rate between the last crossing
of VREF(DC) and the first crossing of VIH(AC) MIN. tDS nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of
VIL(AC) MAX. If the actual signal is always earlier than the nominal slew rate line between
shaded “VREF(DC) to AC region,” use nominal slew rate for derating value (see Figure 75). If
the actual signal is later than the nominal slew rate line anywhere between shaded
“VREF(DC) to AC region,” the slew rate of a tangent line to the actual signal from the AC
level to DC level is used for derating value (see Figure 76).
3. tDH nominal slew rate for a rising signal is defined as the slew rate between the last
crossing of VIL(DC) MAX and the first crossing of VREF(DC). tDH nominal slew rate for a falling
signal is defined as the slew rate between the last crossing of VIH(DC) MIN and the first
crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line
between shaded “DC level to VREF(DC) region,” use nominal slew rate for derating value
(see Figure 77). If the actual signal is earlier than the nominal slew rate line anywhere
between shaded “DC to VREF(DC) region,” the slew rate of a tangent line to the actual signal
from the DC level to VREF(DC) level is used for derating value (see Figure 78).
4. Although the total setup time might be negative for slow slew rates (a valid input signal
will not have reached VIH(AC)/VIL(AC) at the time of the rising clock transition), a valid input
signal is still required to complete the transition and reach VIH(AC)/VIL(AC).
5. For slew rates between the values listed in this table, the derating values may be obtained
by linear interpolation.
6. These values are typically not subject to production test. They are verified by design and
characterization.
7. Single-ended DQS requires special derating. The values in Table 30 are the DQS singleended slew rate derating with DQS referenced at VREF and DQ referenced at the logic levels
t
DSb and tDHb. Table 31 provides the VREF-based fully derated values for the DQ (tDSa and
tDH ) for DDR2-667. Table 32 provides the VREF-based fully derated values for the DQ (tDS
a
a
and tDHa) for DDR2-533. Table 33 provides the VREF-based fully derated values for the DQ
(tDSa and tDHa) for DDR2-400.
100
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Input Slew Rate Derating
Table 30:
Single-Ended DQS Slew Rate Derating Values Using tDSb and tDHb
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
t
(V/ns) DS tDH
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
1.8 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
t
t
t
t
t
t
t
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
130
97
30
25
17
5
–7
–28
–78
53
32
–10
–24
–41
–64
–93
–135
–198
DS
DH
DS
DH
DS
DH
DS
DH
0.8 V/ns
0.6 V/ns
0.4V/ns
t
t
t
t
t
t
t
t
145
112
45
40
32
20
8
–13
–63
48
27
–15
–29
–46
–69
–98
–140
–203
155
122
55
50
42
30
18
–3
–53
45
24
–18
–32
–49
–72
–102
–143
–206
165
132
65
60
52
40
28
7
–43
41
20
–22
–36
–53
–75
–105
–147
–210
175
142
75
70
61
50
38
17
–33
38
17
–25
–39
–56
–79
–108
–150
–213
DS
DH
DS
DH
DS
DH
DS
DH
1. Derating values, to be used with base tDSb- and tDHb-specified values.
Notes:
Table 31:
1.6 V/ns
t
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-667
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
t
(V/ns) DS tDH
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
0.6 V/ns
0.4V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
330
330
330
347
367
391
426
472
522
291
290
290
290
290
290
290
290
289
345
345
345
362
382
406
441
487
537
286
285
285
285
285
285
285
285
284
355
355
355
372
392
416
451
497
547
282
282
282
282
282
281
282
282
281
365
365
365
382
402
426
461
507
557
29
279
278
278
278
278
278
278
278
375
375
375
392
412
436
471
517
567
276
275
275
275
275
275
275
275
274
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Input Slew Rate Derating
Table 32:
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-533
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
(V/ns) tDS tDH
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
355
364
380
402
429
463
510
572
647
Table 33:
341
340
340
340
340
340
340
340
339
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
t
t
t
t
t
t
t
t
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
355
364
380
402
429
463
510
572
647
341
340
340
340
340
340
340
340
339
DS
DH
DS
DH
DS
DH
DS
DH
1.0 V/ns
0.8 V/ns
0.6 V/ns
0.4V/ns
t
t
t
t
t
t
t
t
370
379
395
417
444
478
525
587
662
336
335
335
335
335
335
335
335
334
380
389
405
427
454
488
535
597
672
332
332
332
332
332
331
332
332
331
390
399
415
437
464
498
545
607
682
329
329
328
328
328
328
328
328
328
400
409
425
447
474
508
555
617
692
326
325
325
325
325
325
325
325
324
DS
DH
DS
DH
DS
DH
DS
DH
Single-Ended DQS Slew Rate Fully Derated (DQS, DQ at VREF) at DDR2-400
Reference points indicated in bold
DQS Single-Ended Slew Rate Derated (at VREF)
2.0 V/ns
DQ
t
(V/ns) DS tDH
2
1.5
1
0.9
0.8
0.7
0.6
0.5
0.4
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
0.6 V/ns
0.4V/ns
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
tDS
tDH
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
405
414
430
452
479
513
560
622
697
391
390
390
390
390
390
390
390
389
420
429
445
467
494
528
575
637
712
386
385
385
385
385
385
385
385
384
430
439
455
477
504
538
585
647
722
382
382
382
382
382
381
382
382
381
440
449
465
487
514
548
595
657
732
379
379
378
378
378
378
378
378
378
450
459
475
497
524
558
605
667
742
376
375
375
375
375
375
375
375
374
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Input Slew Rate Derating
Figure 75:
Nominal Slew Rate for tDS
DQS1
DQS#1
t
DS
t
t
DH
t
DS
DH
VDDQ
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
VSS
ΔTF
Setup slew rate
=
falling signal
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
ΔTR
VREF(DC) - VIL(AC) MAX
ΔTF
Setup slew rate
=
rising signal
VIH(AC) MIN - VREF(DC)
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
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Input Slew Rate Derating
Figure 76:
Tangent Line for tDS
DQS1
DQS#1
t
t
t
DS
DS
DH
VDDQ
VIH(AC) MIN
t
DH
Nominal
line
VREF to AC
region
VIH(DC) MIN
Tangent line
VREF(DC)
Tangent line
VIL(DC) MAX
Nominal line
VREF to AC
region
VIL(AC) MAX
ΔTR
ΔTF
VSS
Setup Slew Rate tangent line [VREF(DC) - VIL(AC) MAX]
Falling Signal =
ΔTF
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
Setup Slew Rate tangent line [VIH(AC) MIN - VREF(DC)]
Rising Signal =
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
104
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Input Slew Rate Derating
Figure 77:
Nominal Slew Rate for tDH
DQS1
DQS#1
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
VIH(DC) MIN
DC to VREF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTR
Hold slew rate VREF(DC) - VIL(DC) MAX
rising signal =
ΔTR
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
ΔTF
Hold slew rate
VIH(DC) MIN - VREF(DC)
falling signal =
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
105
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Input Slew Rate Derating
Figure 78:
Tangent Line for tDH
DQS1
DQS#1
tIS
tIS
tIH
tIH
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal line
DC to VREF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
ΔTF
ΔTR
Hold Slew Rate
=
Rising Signal
Notes:
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1GbDDR2_2.fm - Rev. K 4/06 EN
tangent line [VREF(DC) - VIL(DC) MAX]
ΔTR
Hold Slew Rate
Falling Signal =
tangent line [VIH(DC) MIN - VREF(DC)]
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC) MAX and VIH(DC) MIN.
106
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Input Slew Rate Derating
Figure 79:
AC Input Test Signal Waveform Command/Address Balls
CK#
CK
tIS
b
tIS
b
tIH
b
tIH
b
Logic Levels
VDDQ
VSWING (MAX)
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VREF Levels
Figure 80:
tIS
a
tIS
a
tIH
a
tIH
a
AC Input Test Signal Waveform for Data with DQS, DQS# (Differential)
DQS#
DQS
tDS
b
tDH
b
tDS
b
tDH
b
Logic Levels
VDDQ
VSWING (MAX)
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VREF Levels
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tDS
a
107
tDH
a
tDS
a
tDH
a
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Input Slew Rate Derating
Figure 81:
AC Input Test Signal Waveform for Data with DQS (single-ended)
VREF
DQS
tDS
b
Logic Levels
tDH
b
tDS
b
tDH
b
VDDQ
VSWING (MAX)
VIH(AC) MIN
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
VREF Levels
tDS
a
Figure 82:
tDH
a
tDS
a
tDH
a
AC Input Test Signal Waveform (differential)
VDDQ
VTR
Crossing Point
VSWING
VIX
VCP
VSSQ
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Power and Ground Clamp Characteristics
Power and Ground Clamp Characteristics
Power and ground clamps are provided on the following input-only balls: BA2–BA0, A0–
A13 ( x4, x8), A0–A12 (x16), CS#, RAS#, CAS#, WE#, ODT, and CKE.
Table 34:
Figure 83:
Input Clamp Characteristics
Voltage Across Clamp
(V)
Minimum Power Clamp
Current (mA)
Minimum Ground Clamp
Current (mA)
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.1
1.0
2.5
4.7
6.8
9.1
11.0
13.5
16.0
18.2
21.0
Input Clamp Characteristics
Minimum Clamp Current (mA)
25.0
20.0
15.0
10.0
5.0
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Voltage Across Clamp (V)
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AC Overshoot/Undershoot Specification
AC Overshoot/Undershoot Specification
Some revisions will support the 0.9V maximum average amplitude instead of the 0.5V
maximum average amplitude that is shown in Table 35 and Table 36.
Table 35:
Address and Control Balls
Applies to BA2–BA0, A0–A13 ( x4, x8), A0–A12 (x16), CS#, RAS#, CAS#, WE#, CKE, ODT
Specification
Parameter
Maximum peak amplitude allowed for overshoot area (see Figure 84)
Maximum peak amplitude allowed for undershoot area (see Figure 85)
Maximum overshoot area above VDD (see Figure 84)
Maximum undershoot area below VSS (see Figure 85)
Table 36:
-5E
-37E
-3/-3E
-25/-25E
0.50V
0.50V
1.33 Vns
1.33 Vns
0.50V
0.50V
1.00 Vns
1.00 Vns
0.50V
0.50V
0.80 Vns
0.80 Vns
0.50V
0.50V
0.66 Vns
0.66 Vns
Clock, Data, Strobe, and Mask Balls
Applies to DQ, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM
Specification
Parameter
Maximum peak amplitude allowed for overshoot area (see Figure 84)
Maximum peak amplitude allowed for undershoot area (see Figure 85)
Maximum overshoot area above VDDQ (see Figure 84)
Maximum undershoot area below VSSQ (see Figure 85)
-37E
-3/-3E
-25/-25E
0.50V
0.50V
0.28 Vns
0.28 Vns
0.50V
0.50V
0.23 Vns
0.23 Vns
0.50V
0.50V
0.19 Vns
0.19 Vns
Overshoot
Volts (V)
Figure 84:
-5E
0.50V
0.50V
0.38 Vns
0.38 Vns
Maximum Amplitude
Overshoot Area
VDD/VDDQ
VSS/VSSQ
Time (ns)
Figure 85:
Undershoot
Volts (V)
VSS/VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
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Output Electrical Characteristics and Operating Conditions
Output Electrical Characteristics and Operating Conditions
Table 37:
Differential AC Output Parameters
Parameter
Symbol
Min
Max
Units
Notes
AC differential cross-point voltage
AC differential voltage swing
VOX(AC)
VSWING
0.50 x VDDQ - 125
1.0
0.50 x VDDQ + 125
mV
mV
1
Notes:
Figure 86:
1. The typical value of VOX(AC) is expected to be about 0.5 x VDDQ of the transmitting device
and VOX(AC) is expected to track variations in VDDQ. VOX(AC) indicates the voltage at which
differential output signals must cross.
Differential Output Signal Levels
VDDQ
VTR
Crossing Point
VSWING
VOX
VCP
VSSQ
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Output Electrical Characteristics and Operating Conditions
Table 38:
Output DC Current Drive
Parameter
Output minimum source DC current
Output minimum sink DC current
Notes:
Table 39:
Value
Units
Notes
IOH
IOL
–13.4
13.4
mA
mA
1, 2, 4
2, 3, 4
1. For IOH(DC); VDDQ = 1.7V, VOUT = 1,420mV. (VOUT - VDDQ)/IOH must be less than 21Ω for values of VOUT between VDDQ and VDDQ - 280mV.
2. For IOL(DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21Ω for values of VOUT
between 0V and 280mV.
3. The DC value of VREF applied to the receiving device is set to VTT.
4. The values of IOH(DC) and IOL(DC) are based on the conditions given in Notes 1 and 2. They
are used to test device drive current capability to ensure VIH (MIN) plus a noise margin and
VIL (MAX) minus a noise margin are delivered to an SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (see output IV curves) along a
21Ω load line to define a convenient driver current for measurement.
Output Characteristics
Parameter
Output impedance
Pull-up and pull-down
mismatch
Output slew rate
Notes:
Figure 87:
Symbol
Min
Nom
Max
See “Full Strength Pull-Down Driver
Characteristics” on page 113
0
4
1.5
5
Units
Notes
Ω
1, 2
Ω
1, 2, 3
V/ns
1, 4, 5, 6
1. Absolute specifications: 0°C ≤ TC ≤ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V.
2. Impedance measurement conditions for output source DC current: VDDQ = 1.7V; VOUT =
1,420mV; (VOUT - VDDQ)/IOH must be less than 23.4Ω for values of VOUT between VDDQ and
VDDQ - 280mV. Impedance measurement condition for output sink DC current: VDDQ = 1.7V;
VOUT = 280mV; VOUT/IOL must be less than 23.4Ω for values of VOUT between 0V and 280mV.
3. Mismatch is absolute value between pull-up and pull-down; both are measured at same
temperature and voltage.
4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT +
250mV for single-ended signals. For differential signals (DQS - DQS#), output slew rate is
measured between DQS - DQS# = –500mV and DQS# - DQS = +500mV. Output slew rate is
guaranteed by design, but is not necessarily tested on each device.
5. The absolute value of the slew rate as measured from VIL(DC) MAX to VIH(DC) MIN is equal to
or greater than the slew rate as measured from VIL(AC) MAX to VIH(AC) MIN. This is guaranteed by design and characterization.
6. IT devices require an additional 0.4 V/ns in the MAX limit when TC is between –40°C and
0°C.
Output Slew Rate Load
VTT = VDDQ/2
Output
(VOUT)
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25Ω
Reference
Point
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Full Strength Pull-Down Driver Characteristics
Full Strength Pull-Down Driver Characteristics
Figure 88:
Full Strength Pull-Down Characteristics
Pull-down Characteristics
120.00
I OUT (mA)
100.00
80.00
60.00
40.00
20.00
0.00
0.0
0.5
1.0
1.5
V OUT(V)
Table 40:
Full Strength Pull-Down Current (mA)
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1GbDDR2_2.fm - Rev. K 4/06 EN
Voltage (V)
Minimum
Nominal
Maximum
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
4.3
8.6
12.9
16.9
20.4
23.28
25.44
26.79
27.67
28.38
28.96
29.46
29.90
30.29
30.65
30.98
31.31
31.64
31.96
0.00
5.63
11.3
16.52
22.19
27.59
32.39
36.45
40.38
44.01
47.01
49.63
51.71
53.32
54.9
56.03
57.07
58.16
59.27
60.35
0.00
7.95
15.90
23.85
31.80
39.75
47.70
55.55
62.95
69.55
75.35
80.35
84.55
87.95
90.70
93.00
95.05
97.05
99.05
101.05
113
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1Gb: x4, x8, x16 DDR2 SDRAM
Full Strength Pull-Up Driver Characteristics
Full Strength Pull-Up Driver Characteristics
Figure 89:
Full Strength Pull-Up Characteristics
Pull-up Characteristics
0.0
0.0
0.5
1.0
1.5
-20.0
I OUT (mA)
-40.0
-60.0
-80.0
-100.0
-120.0
V DDQ - VOUT (V)
Table 41:
Full Strength Pull-Up Current (mA)
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Voltage (V)
Minimum
Nominal
Maximum
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
–4.3
–8.6
–12.9
–16.9
–20.4
–23.28
–25.44
–26.79
–27.67
–28.38
–28.96
–29.46
–29.90
–30.29
–30.65
–30.98
–31.31
–31.64
–31.96
0.00
–5.63
–11.3
–16.52
–22.19
–27.59
–32.39
–36.45
–40.38
–44.01
–47.01
–49.63
–51.71
–53.32
–54.90
–56.03
–57.07
–58.16
–59.27
–60.35
0.00
–7.95
–15.90
–23.85
–31.80
–39.75
–47.70
–55.55
–62.95
–69.55
–75.35
–80.35
–84.55
–87.95
–90.70
–93.00
–95.05
–97.05
–99.05
–101.05
114
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1Gb: x4, x8, x16 DDR2 SDRAM
Reduced Strength Pull-Down Driver Characteristics
Reduced Strength Pull-Down Driver Characteristics
Figure 90:
Reduced Strength Pull-Down Characteristics
Pull-down Characteristics
70.00
60.00
I OUT (mA)
50.00
40.00
30.00
20.00
10.00
0.00
0.0
0.5
1.0
1.5
VOUT (V)
Table 42:
Reduced Strength Pull-Down Current (mA)
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Voltage (V)
Minimum
Nominal
Maximum
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
1.72
3.44
5.16
6.76
8.16
9.31
10.18
10.72
11.07
11.35
11.58
11.78
11.96
12.12
12.26
12.39
12.52
12.66
12.78
0.00
2.98
5.99
8.75
11.76
14.62
17.17
19.32
21.40
23.32
24.92
26.30
27.41
28.26
29.10
29.70
30.25
30.82
31.41
31.98
0.00
4.77
9.54
14.31
19.08
23.85
28.62
33.33
37.77
41.73
45.21
48.21
50.73
52.77
54.42
55.80
57.03
58.23
59.43
60.63
115
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1Gb: x4, x8, x16 DDR2 SDRAM
Reduced Strength Pull-Up Driver Characteristics
Reduced Strength Pull-Up Driver Characteristics
Figure 91:
Reduced Strength Pull-Up Characteristics
Pull-up Characteristics
0.0
0.0
0.5
1.0
1.5
-10.0
I OUT (mA)
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
VDDQ - VOUT (V)
Table 43:
Reduced Strength Pull-Up Current (mA)
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Voltage (V)
Minimum
Nominal
Maximum
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
0.00
–1.72
–3.44
–5.16
–6.76
–8.16
–9.31
–10.18
–10.72
–11.07
–11.35
–11.58
–11.78
–11.96
–12.12
–12.26
–12.39
–12.52
–12.66
–12.78
0.00
–2.98
–5.99
–8.75
–11.76
–14.62
–17.17
–19.32
–21.40
–23.32
–24.92
–26.30
–27.41
–28.26
–29.10
–29.69
–30.25
–30.82
–31.42
–31.98
0.00
–4.77
–9.54
–14.31
–19.08
–23.85
–28.62
–33.33
–37.77
–41.73
–45.21
–48.21
–50.73
–52.77
–54.42
–55.8
–57.03
–58.23
–59.43
–60.63
116
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1Gb: x4, x8, x16 DDR2 SDRAM
FBGA Package Capacitance
FBGA Package Capacitance
Table 44:
Input Capacitance
Parameter
Input capacitance: CK, CK#
Delta input capacitance: CK, CK#
Input capacitance: BA2–BA0, A0–A13 (A0–A12 on
x16), CS#, RAS#, CAS#, WE#, CKE, ODT
Delta input capacitance: BA2–BA0, A0–A13 (A0–A12
on x16), CS#, RAS#, CAS#, WE#, CKE, ODT
Input/Output capacitance: DQs, DQS, DM, NF
Delta input/output capacitance: DQs, DQS, DM, NF
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
Symbol
Min
Max
Units
Notes
CCK
CDCK
CI
1.0
–
1.0
2.0
0.25
2.0
pF
pF
pF
1
2
1
CDI
–
0.25
pF
2
CIO
CDIO
2.5
–
4.0
0.5
pF
pF
1, 4
3
1. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz,
TC = 25°C, VOUT(DC) = VDDQ/2, VOUT (peak-to-peak) = 0.1V. DM input is grouped with I/O
balls, reflecting the fact that they are matched in loading.
2. The input capacitance per ball group will not differ by more than this maximum amount for
any given device.
3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum
amount for any given device.
4. Reduce MAX limit by 0.5pF for -3/-3E/-25/-25E speed devices.
5. Reduce MAX limit by 0.25pF for -3/-3E/-25/-25E speed devices.
117
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1Gb: x4, x8, x16 DDR2 SDRAM
IDD Specifications and Conditions
IDD Specifications and Conditions
Table 45:
DDR2 IDD Specifications and Conditions (continued)
Notes: 1–7; notes appear on page 119
Parameter/Condition
Sym
Config
-25E
-25
100
100
90
80
70
150
150
135
110
110
110
110
100
95
80
x16
175
175
130
120
115
x4, x8, x16
7
7
7
7
7
65
65
55
41
35
75
75
65
45
40
70
70
60
45
40
80
80
70
50
40
45
45
40
30
25
10
10
10
10
10
75
75
70
55
45
x16
85
85
75
60
55
x4, x8
185
185
160
130
110
tCK
Operating one bank active-precharge current:
=
t
CK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is
IDD0
HIGH, CS# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current:
IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD),
t
RC = tRC (Idd), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD);
IDD1
CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data pattern is same as
IDD4W
Precharge power-down current: All banks idle; tCK =
tCK (IDD); CKE is LOW; Other control and address bus
IDD2P
inputs are stable; Data bus inputs are floating
Precharge quiet standby current: All banks idle; tCK =
tCK (IDD); CKE is HIGH, CS# is HIGH; Other control and
IDD2Q
address bus inputs are stable; Data bus inputs are
floating
Precharge standby current: All banks idle; tCK = tCK
(IDD); CKE is HIGH, CS# is HIGH; Other control and address IDD2N
bus inputs are switching; Data bus inputs are switching
Active power-down current: All banks open; tCK = tCK
(IDD); CKE is LOW; Other control and address bus inputs
are stable; Data bus inputs are floating
IDD3P
Active standby current: All banks open; tCK = tCK
(IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH,
CS# is HIGH between valid commands; Other control and IDD3N
address bus inputs are switching; Data bus inputs are
switching
Operating burst write current: All banks open,
continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK
= tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is IDD4W
HIGH, CS# is HIGH between valid commands; Address bus
inputs are switching; Data bus inputs are switching
Operating burst read current: All banks open,
continuous burst reads, IOUT = 0mA; BL = 4, CL = CL (IDD),
AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP
IDD4R
(IDD); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching
Burst refresh current: tCK = tCK (IDD); refresh
command at every tRFC (IDD) interval; CKE is HIGH, CS# is
IDD5
HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are
switching
IDD6
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V;
Other control and address bus inputs are floating; Data
IDD6L
bus inputs are floating
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1GbDDR2_2.fm - Rev. K 4/06 EN
118
x4, x8
x16
x4, x8
-3E/-3 -37E
-5E
Units
mA
mA
x4, x8
x16
x4, x8
x16
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
x4, x8
mA
mA
mA
mA
mA
mA
x16
315
315
200
180
160
x4, x8
190
190
160
145
110
mA
x16
x4, x8
320
320
220
180
160
280
280
260
250
220
280
280
270
250
240
7
7
7
7
7
3
3
3
3
3
mA
x16
x4, x8, x16
mA
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
IDD Specifications and Conditions
Table 45:
DDR2 IDD Specifications and Conditions (continued)
Notes: 1–7; notes appear on page 119
Parameter/Condition
Sym
Operating bank interleave read current: All bank
interleaving reads, IOUT = 0mA; BL = 4, CL = CL (IDD), AL =
t
RCD (IDD) - 1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC (IDD),
tRRD = tRRD (IDD), tRCD = tRCD (IDD); CKE is HIGH, CS# is
HIGH between valid commands; Address bus inputs are
stable during deselects; Data bus inputs are switching
(see Table 47 on page 120 for details)
Notes:
Config
-25E
-25
x4, x8
335
335
-3E/-3 -37E
300
290
-5E
Units
260
IDD7
mA
x16
440
430
350
330
300
1. IDD specifications are tested after the device is properly initialized. 0°C ≤ TC ≤ +85°C.
VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL = +1.8V ±0.1V, VREF = VDDQ/2.
–37V VDDQ = +1.9V ±0.1V, VDDL = +1.9V ±0.1.
2. Input slew rate is specified by AC parametric test conditions (Table 46 on page 120).
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#.
IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
LOW
HIGH
Stable
Floating
Switching
Switching
VIN ≤ VIL(AC) MAX
VIN ≥ VIH(AC) MIN
Inputs stable at a HIGH or LOW level
Inputs at VREF = VDDQ/2
Inputs changing between HIGH and LOW every other clock cycle (once per two
clocks) for address and control signals
Inputs changing between HIGH and LOW every other data transfer (once per
clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR1 to be enabled during testing.
7. The following IDDs must be derated (IDD limits increase) on IT-option devices when operated
outside of the range 0°C ≤ TC ≤ 85°C:
When
TC ≤ 0°C
When
TC ≥ 85°C
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
IDD2P and IDD3P (slow) must be derated by 4 percent; IDD4R and IDD5W must be
derated by 2 percent; and IDD6 and IDD7 must be derated by 7 percent
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P (fast), IDD4R, IDD4W, and IDD5W must be
derated by 2 percent; IDD2P must be derated by 20 percent; IDD3Pslow must be
derated by 30 percent; and IDD6 must be derated by 80 percent (IDD6 will
increase by this amount if TC < 85°C and the 2x refresh option is still enabled)
119
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1Gb: x4, x8, x16 DDR2 SDRAM
IDD7 Conditions
Table 46:
General IDD Parameters
IDD Parameter
CL (IDD)
t
RCD (IDD)
t
RC (IDD)
tRRD (IDD) - x4/x8 (1KB)
t
RRD (IDD) - x16 (2KB)
t
CK (IDD)
t
RAS MIN (IDD)
t
RAS MAX (IDD)
tRP (IDD)
t
RFC (IDD)
tFAW (1KB) (IDD)
tFAW (2KB) (IDD)
-25E
-25
-3E
-3
-37E
-5E
5
12.5
57.5
7.5
10
2.5
45
70,000
12.5
127.5
35
45
6
15
60
7.5
10
2.5
45
70,000
15
127.5
35
45
4
12
57
7.5
10
3
45
70,000
12
127.5
37.5
50
5
15
60
7.5
10
3
45
70,000
15
127.5
37.5
50
4
15
60
7.5
10
3.75
45
70,000
15
127.5
37.5
50
3
15
55
7.5
10
5
40
70,000
15
127.5
37.5
50
Units
t
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IDD7 Conditions
The detailed timings are shown below for IDD7. Changes will be required if timing
parameter changes are made to the specification. Where general IDD parameters in
Table 46 on page 120 conflict with pattern requirements of Table 47, then Table 47
requirements take precedence.
Table 47:
IDD7 Timing Patterns (8-bank)
All bank interleave READ operation
Speed Grade
IDD7 Timing Patterns for x4/x8/x16
Timing Patterns for 8-bank devices x4/x8
-5E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-37E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-3
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-3E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-25
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-25E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
Timing Patterns for 8-bank devices x16
-5E
A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-37E
A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-3
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
-3E
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D
-25
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
-25E
A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D A4 RA4 D D A5 RA5 D D A6 RA6 D D A7 RA7 D D D D
Notes:
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
1. A = active; RA = read auto precharge; D = deselect.
2. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a
BL = 4.
3. Control and address bus inputs are STABLE during DESELECTs.
4. IOUT = 0mA.
120
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1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 1 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
-3E
Symbol
CL = 5 tCKAVG(5)
CL = 4 tCKAVG(4)
CL = 3 tCKAVG(3)
CK high-level width tCHAVG
tCL
CK low-level width
AVG
tHP
Half clock period
Clock Jitter
Clock (absolute)
Clock
Clock cycle
time
Absolute tCK
tCK
abs
Absolute CK highlevel width
tCH
Absolute CK lowlevel width
tCL
abs
Clock jitter – period
Clock jitter – half
period
Clock jitter – cycle to
cycle
Cumulative jitter
error, 2 cycles
Cumulative jitter
error, 3 cycles
Cumulative jitter
error, 4 cycles
Cumulative jitter
error, 5 cycles
Cumulative jitter
error, 6–10 cycles
Cumulative jitter
error, 11–50 cycles
abs
tJIT
PER
tJIT
DUTY
Min
Max
-37E
Min
Max
Min
-5E
Max
Min
Max
3,000
8,000
3,000
8,000
–
–
–
–
3,000
8,000
3,750
8,000
3,750
8,000
5,000
8,000
–
–
5,000
8,000
5,000
8,000
5,000
8,000
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
0.48
0.52
MIN
MIN
MIN
MIN
(tCH,
(tCH,
(tCH,
(tCH,
t
t
t
t
CL)
CL)
CL)
CL)
t
t
t
t
t
t
t
tCK
CK
CK
CK
CK
CK
CK
AVG
AVG
AVG
AVG
AVG(
AVG(
AVG( CKAVG
(MIN) + (MAX) +
MIN) +
(MAX) +
MIN) +
MAX) +
MIN) +
(MAX) +
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
PER
PER
PER
PER
PER
PER
PER
PER
(MIN)
tCK
AVG
t
(MAX)
(MIN)
(MAX)
(MIN)
(MAX)
(MIN)
(MIN)
tCK
AVG
(MAX)
tCK
AVG
(MIN)
tCK
AVG
(MAX)
tCK
AVG
(MIN)
tCK
AVG
(MAX)
tCK
AVG
(MIN)
tCK
AVG
(MAX)
tCK
AVG
(MIN) *
tCL
AVG
(MAX) *
tCL
AVG
(MIN) *
tCL
AVG
(MAX) *
tCL
AVG
(MIN) *
tCL
AVG
(MAX) *
tCL
AVG
(MIN) *
tCL
AVG
(MAX) *
tCL
AVG
(MIN) +
tJIT
DTY
(MAX) +
tJIT
DTY
(MIN) +
tJIT
DTY
(MAX) +
tJIT
DTY
(MIN) +
tJIT
DTY
(MAX) +
tJIT
DTY
(MIN) +
tJIT
DTY
(MAX) +
tJIT
DTY
(MIN)
(MAX)
(MIN)
(MAX)
(MIN)
(MAX)
(MIN)
(MAX)
–125
–125
125
125
–125
–125
125
125
–125
–125
125
125
–125
–150
125
150
JITCC
250
250
250
Units Notes
ps
ps
ps
t
CK
tCK
ps
16, 22,
36, 38
45
46
ps
(MAX)
CKAVG tCKAVG tCKAVG tCKAVG tCKAVG tCKAVG tCKAVG
*
(MIN)
(MAX) *
(MIN)*
(MAX) *
(MIN) *
(MAX) *
(MIN)*
(MAX) *
tCH
tCH
tCH
tCH
tCH
tCH
tCH
tCH
AVG
AVG
AVG
AVG
AVG
AVG
AVG
AVG
(MIN) + (MAX) +
(MIN)+
(MAX) + (MIN) + (MAX) +
(MIN)+
(MAX) +
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
tJIT
DTY
DTY
DTY
DTY
DTY
DTY
DTY
DTY
t
tERR
-3
250
ps
ps
ps
ps
39
40
ps
41
2per
–175
175
–175
175
–175
175
–175
175
ps
42
ERR3per
–225
225
–225
225
–225
225
–225
225
ps
42
4per
–250
250
–250
250
–250
250
–250
250
ps
42
ERR5per
–250
250
–250
250
–250
250
–250
250
ps
42, 48
tERR
6-
–350
350
–350
350
–350
350
–350
350
ps
42, 48
–450
450
–450
450
–450
450
–450
450
ps
42
t
tERR
t
10per
tERR
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
11-
50per
121
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 2 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
-3E
Symbol
Data
DQ output access
time from CK/CK#
Data-out High-Z
window from CK/
CK#
DQS Low-Z window
from CK/CK#
DQ Low-Z window
from CK/CK#
DQ and DM input
setup time relative to
DQS
DQ and DM input
hold time relative to
DQS
DQ and DM input
setup time relative to
DQS
DQ and DM input
hold time relative to
DQS
DQ and DM input
pulse width (for each
input)
Data hold skew
factor
DQ–DQS hold, DQS
to first DQ to go
nonvalid, per access
Data valid output
window (DVW)
AC
LZ1
tLZ
2
Units Notes
Min
Max
Min
Max
Min
Max
–
340
–
340
–
400
–
450
ps
47
–450
+450
–450
+450
–500
+500
–600
+600
ps
34, 43
ps
8, 9,
43
t
t
AC
(MAX)
tHZ
t
-5E
Max
QHS
t
-37E
Min
t
DQ hold skew factor
-3
tAC
(MIN)
2 * tAC
(MIN)
t
AC
(MAX)
tAC
(MAX)
t
AC
(MAX)
t
AC
(MIN)
2 * tAC
(MIN)
t
AC
(MAX)
tAC
(MAX)
t
AC
(MAX)
t
AC
(MIN)
2 * tAC
(MIN)
t
AC
(MAX)
tAC
(MAX)
AC
(MAX)
t
AC
(MIN)
2 * tAC
(MIN)
t
AC
(MAX)
tAC
(MAX)
ps
ps
8, 10,
43
8, 10,
43
tDS
a
300
300
350
400
ps
7, 15,
19
tDH
a
300
300
350
400
ps
7, 15,
19
tDS
b
100
100
100
150
ps
7, 15,
19
tDH
b
175
175
225
275
ps
7, 15,
19
tDIPW
0.35
0.35
0.35
0.35
tCK
37
ps
47
ps
15,
17, 47
ns
15, 17
tQHS
tQH
tDVW
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
340
tHP
-
tQHS
t
QH -
tDQSQ
340
tHP
-
tQHS
t
QH -
tDQSQ
122
400
tHP
-
tQHS
t
QH -
tDQSQ
450
tHP
-
tQHS
t
QH -
tDQSQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 3 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Data Strobe
Parameter
-3E
Symbol
DQS input-high pulse t
DQSH
width
DQS input-low pulse t
DQSL
width
DQS output access
t
DQSCK
time from CK/CK#
DQS falling edge to
tDSS
CK rising – setup
time
DQS falling edge
from CK rising – hold tDSH
time
DQS–DQ skew, DQS
to last DQ valid, per tDQSQ
group, per access
DQS read preamble
tRPRE
Min
-3
Max
Min
-37E
Max
Min
-5E
Max
Min
Max
Units Notes
0.35
0.35
0.35
0.35
t
CK
37
0.35
0.35
0.35
0.35
tCK
37
ps
34, 43
–400
+400
–400
+400
–450
+450
–500
+500
0.2
0.2
0.2
0.2
tCK
37
0.2
0.2
0.2
0.2
tCK
37
350
ps
15, 17
33, 34,
37, 43
33, 34,
37, 43
240
240
300
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
DQS read postamble
tRPST
0.4
Write preamble
setup time
DQS write preamble
DQS write postamble
Positive DQS latching
edge to associated
clock edge
WRITE command to
first DQS latching
transition
tWPRES
0
0
0
0
ps
12, 13
tWPRE
0.35
0.4
0.6
0.35
0.4
0.6
0.25
0.4
0.6
0.25
0.4
tCK
tWPST
0.6
tCK
37
11, 37
tDQSS
–0.25
0.25
–0.25
0.25
–0.25
0.25
–0.25
0.25
tCK
37
tCK
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
WL -
WL +
WL -
WL +
WL -
WL +
WL -
WL +
tDQSS
tDQSS
tDQSS
tDQSS
tDQSS
tDQSS
tDQSS
tDQSS
123
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 4 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Command and Address
Parameter
Symbol
Address and control
t
IPW
input pulse width for
each input
Address and control
tIS
a
input setup time
Address and control
t
IHa
input hold time
Address and control
tIS
b
input setup time
Address and control
t
IHb
input hold time
CAS# to CAS#
tCCD
command delay
ACTIVE-to-ACTIVE
tRC
(same bank)
command
tRRD
ACTIVE bank a to
(x4, x8)
ACTIVE bank b
tRRD
command
(x16)
ACTIVE-to-READ or
tRCD
WRITE delay
tFAW
4-Bank activate
(x4, x8)
period
tFAW
4-Bank activate
(x16)
period
ACTIVE-totRAS
PRECHARGE
command
Internal READ-tot
RTP
PRECHARGE
command delay
tWR
Write recovery time
Auto precharge
t
DAL
write recovery +
precharge time
Internal WRITE-tot
WTR
READ command
delay
PRECHARGE
tRP
command period
PRECHARGE ALL
tRPA
command period
LOAD MODE
tMRD
command cycle time
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
-3E
Min
-3
Max
Min
-37E
Max
Min
Max
-5E
Min
0.6
0.6
0.6
0.6
400
400
500
400
400
200
Max
Units Notes
t
CK
37
600
ps
6, 19
500
600
ps
6, 19
200
250
350
ps
6, 19
275
275
375
475
ps
6, 19
2
2
2
2
tCK
37
54
55
55
55
ns
31, 37
7.5
7.5
7.5
7.5
ns
25, 37
10
10
10
10
ns
25, 37
12
15
15
15
ns
37
37.5
37.5
37.5
37.5
ns
28, 37
50
50
50
50
ns
28, 37
ns
18, 31,
37
7.5
ns
21, 25,
37
ns
25, 37
ns
20
40
70,000
7.5
40
70,000
7.5
40
70,000
7.5
40
15
15
15
15
tWR
tWR
tWR
tWR
t
+
RP
t
+
RP
+
t
t
RP
70,000
+
RP
7.5
7.5
7.5
10
ns
25, 37
12
15
15
15
ns
29, 37
tRP
+
tRP
+
tRP
+
tRP
+
tCK
tCK
tCK
tCK
ns
29
2
2
2
2
tCK
37
124
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 5 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
ODT
Self Refresh
Refresh
Parameter
Symbol
-3E
Min
-3
Max
Min
-37E
Max
Min
Max
-5E
Min
Max
CKE LOW to CK, CK# t
t
t
t
t
DELAY
IS + tCK +tIH
IS + tCK +tIH
IS + tCK +tIH
IS + tCK +tIH
uncertainty
REFRESH-to-ACTIVE
or REFRESH-totRFC
127.5 70,000 127.5 70,000 127.5 70,000 127.5 70,000
REFRESH command
interval
Average periodic
t
REFI
7.8
7.8
7.8
7.8
refresh interval
(commercial)
Average periodic
tREFI
3.9
3.9
3.9
3.9
refresh interval
IT
(industrial)
tRFC
tRFC
tRFC
tRFC
Exit SELF REFRESH to
tXSNR
(MIN) +
(MIN) +
(MIN) +
(MIN) +
non-READ command
10
10
10
10
Exit SELF REFRESH to t
XSRD
200
200
200
200
READ command
Exit SELF REFRESH
tISXR
tIS
tIS
tIS
tIS
timing reference
tAOND
2
2
2
2
2
2
2
2
ODT turn-on delay
tAC
tAC
tAC
tAC
ODT turn-on
tAC
tAC
tAC
tAC
tAON
(MAX) +
(MAX) +
(MAX) +
(MAX) +
(MIN)
(MIN)
(MIN)
(MIN)
700
700
1,000
1000
tAOFD
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
ODT turn-off delay
tAC
tAC
tAC
tAC
ODT turn-off
tAC
tAC
tAC
tAC
tAOF
(MAX) +
(MAX) +
(MAX) +
(MAX) +
(MIN)
(MIN)
(MIN)
(MIN)
600
600
600
600
tCK
tCK
tCK +
x
2
x
2
x
2
2
x tCK
ODT turn-on (powertAC
tAC
tAC
tAC
t
t
t
+ AC
+ AC
AC
+ tAC
down mode)
tAONPD (MIN) +
(MIN) +
(MIN) +
(MIN) +
(MAX) +
(MAX) +
(MAX) +
(MAX) +
2,000
2,000
2000
2,000
1,000
1,000
1,000
1000
2.5 x
2.5 x
2.5 x
2.5 x
ODT turn-off (powertAC
tCK +
tAC
tCK +
tAC
tCK +
tAC
tCK +
down mode)
tAOFPD (MIN) +
tAC
tAC
tAC
tAC
(MIN) +
(MIN) +
(MIN) +
2,000 (MAX) + 2,000 (MAX) + 2,000 (MAX) + 2,000 (MAX) +
1,000
1,000
1,000
1,000
ODT to power-down t
ANPD
3
3
3
3
entry latency
ODT power-down
tAXPD
8
8
8
8
exit latency
ODT enable from
tMOD
12
12
12
12
MRS command
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
125
Units Notes
ns
26
ns
14, 37
µs
14, 37
µs
14, 37
ns
tCK
37
ps
6, 27
tCK
37
ps
23, 43
tCK
35, 37
ps
24, 44
ps
ps
t
CK
37
tCK
37
ns
37, 49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 48:
AC Operating Conditions for -3E, -3, -37E, and -5E Speeds (Sheet 6 of 6)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Power-Down
Parameter
Symbol
Exit active powerdown to READ
t
XARD
command,
MR[12] = 0
Exit active powerdown to READ
tXARDS
command,
MR[12] = 1
Exit precharge
tXP
power-down to any
non-READ command
CKE MIN HIGH/LOW
tCKE
time
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
-3E
Min
-3
Max
Min
-37E
Max
Min
Max
-5E
Min
2
2
2
2
7 - AL
7 - AL
6 - AL
2
2
3
3
126
Max
Units Notes
t
CK
37
6 - AL
tCK
37
2
2
tCK
37
3
3
tCK
32, 37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 49:
AC Operating Conditions for -25E and -25 Speeds (Sheet 1 of 4)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
Clock cycle time
Symbol
CL = 6
CL = 5
CL = 4
CK high-level width
CK low-level width
Half-clock period
Clock
-25E
t
CKAVG(6)
AVG(5)
t
CKAVG(4)
t
CHAVG
t
CLAVG
tCK
t
HP
Absolute tCK
t
Min
Max
Min
Max
–
2,500
3,750
0.48
0.48
MIN
(tCH, tCL)
–
8,000
8,000
0.52
0.52
2,500
3,000
N/A
0.48
0.48
MIN
(tCH, tCL)
8,000
8,000
N/A
0.52
0.52
CKAVG(MIN) + tCKAVG(MAX) tCKAVG(MIN) + tCKAVG(MAX)
t
JITPER(MIN) + JITPER(MAX)
Units
ps
ps
ps
t
CK
t
CK
ps
t
t
t
Notes
16, 22,
36, 38
45
45
46
ps
t
JITPER(MIN) + JITPER(MAX)
Absolute CK high-level width
tCH
ABS
t
t
t
tCK
AVG(MIN) * CKAVG(MAX) * CKAVG(MIN) * CKAVG(MAX) *
tCH
t
t
t
AVG(MIN) + CHAVG(MAX) + CHAVG(MIN)+ CHAVG(MAX) +
tJIT
tJIT
tJIT
tJIT
DTY(MIN)
DTY(MAX)
DTY(MIN)
DTY(MAX)
ps
Absolute CK low-level width
tCL
ABS
tCK
AVG(MIN) *
tCL
AVG(MIN) +
tJIT
DTY(MIN)
tCK
AVG(MAX)
t
* CLAVG(MAX)
+ tJITDTY(MAX)
ps
Clock jitter – period
tJIT
PER
–100
100
–100
100
ps
39
–100
100
–100
100
ps
40
ps
41
tJIT
Clock jitter – half period
DUTY
Cumulative jitter error, 2 cycles
tERR
2per
Cumulative jitter error, 3 cycles
tERR
3per
Cumulative jitter error, 4 cycles
tERR
4per
Cumulative jitter error, 5 cycles
tERR
5per
tERR
Cumulative jitter error, 6–10 cycles
Cumulative jitter error, 11–50 cycles
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
610per
t
ERR11-50per
tCK
t
AVG(MAX) CKAVG(MIN) *
* tCLAVG(MAX) tCLAVG(MIN) +
+ tJITDTY(MAX) tJITDTY(MIN)
200
tJIT
CC
Clock jitter – cycle to cycle
Clock Jitter
CKabs
-25
200
–150
150
–150
150
ps
42
–175
175
–175
175
ps
42
–200
200
–200
200
ps
42
–200
200
–200
200
ps
42, 48
–300
300
–300
300
ps
42, 48
–450
450
–450
450
ps
42
127
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 49:
AC Operating Conditions for -25E and -25 Speeds (Sheet 2 of 4)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Data
Parameter
-25E
Symbol
t
AC
DQ output access time from CK/CK#
Data-out High-Z window from CK/CK#
DQS Low-Z window from CK/CK#
t
LZ1
DQ Low-Z window from CK/CK#
t
DQ and DM input setup time relative to
DQS
DQ and DM input hold time relative to
DQS
DQ and DM input setup time relative to
DQS
DQ and DM input hold time relative to
DQS
DQ and DM input pulse width
(for each input)
Data hold skew factor
DQ–DQS hold from DQS
Data Strobe
Max
Min
+400
(MAX)
–400
tAC
t
Units
Notes
+400
(MAX)
ps
ps
AC (MAX)
34, 43
8, 9, 43
8, 10,
43
8, 10,
43
Max
tAC
AC (MIN)
t
LZ2
2 * tAC
(MIN)
t
t
DSa
250
250
ps
15, 19
tDH
a
250
250
ps
15, 19
50
50
ps
15, 19
125
125
ps
15, 19
0.35
0.35
tCK
37
ps
47
15, 17,
47
tDS
b
tDH
b
tDIPW
tQHS
tQH
tDVW
tDQSH
DQS input-high pulse width
tDQSL
DQS input-low pulse width
tDQSCK
DQS output access time from CK/CK#
tDSS
DQS falling edge to CK rising – setup time
DQS falling edge from CK rising – hold
tDSH
time
DQS–DQ skew, DQS to last DQ valid, per
t
DQSQ
group, per access
DQS read preamble
tRPRE
AC (MAX)
AC (MAX)
t
AC (MIN)
t
ps
2 * tAC
(MIN)
t
ps
300
tHP -tQHS
tQH
300
tHP -tQHS
tQH
-
tDQSQ
0.35
0.35
–350
0.2
AC (MAX)
+350
0.2
ps
-
tDQSQ
ns
15, 17
0.35
0.35
–350
0.2
tCK
tCK
37
37
34, 43
37
tCK
37
200
ps
15, 17
tCK
+350
0.2
200
ps
0.9
1.1
0.9
1.1
tCK
tRPST
0.4
0.6
0.4
0.6
tCK
WPRES
tWPST
0
0.35
0.4
0.6
0
0.35
0.4
0.6
tCK
33, 34,
37, 43
33, 34,
37, 43
12, 13
37
11, 37
tDQSS
–0.25
+0.25
–0.25
+0.25
tCK
37
DQS read postamble
PDF: 09005aef821ae8bf/Source: 09005aef821aed36
1GbDDR2_2.fm - Rev. K 4/06 EN
–400
tHZ
Data valid output window (DVW)
Write preamble setup time
DQS write preamble
DQS write postamble
Positive DQS latching edge to associated
clock edge
WRITE command to first DQS latching
transition
Min
-25
t
tWPRE
ps
tCK
WL - tDQSS WL + tDQSS WL - tDQSS WL + tDQSS
128
t
CK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 49:
AC Operating Conditions for -25E and -25 Speeds (Sheet 3 of 4)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Self Refresh
Refresh
Command and Address
Parameter
Address and control input pulse width for
each input
Address and control input setup time
Address and control input hold time
Address and control input setup time
Address and control input hold time
CAS# to CAS# command delay
ACTIVE-to-ACTIVE (same bank) command
ACTIVE bank a to ACTIVE bank b
command
ACTIVE-to-READ or WRITE delay
4-bank activate period
4-bank activate period
-25E
Symbol
t
Min
-25
Max
Min
Max
Units
Notes
IPW
0.6
0.6
t
CK
37
tIS
375
375
175
250
2
55
375
375
175
250
2
55
ps
ps
ps
ps
t
CK
ns
19
19
19
19
37
31, 37
7.5
7.5
ns
25, 37
10
10
ns
25, 37
12.5
15
ns
37
37.5
37.5
ns
28, 37
50
50
ns
28, 37
a
t
IHa
tIS
b
t
IHb
t
CCD
tRC
tRRD
(x4, x8)
tRRD
(x16)
tRCD
tFAW
(1K page)
tFAW
(2K page)
ACTIVE-to-PRECHARGE command
tRAS
45
Internal READ-to-PRECHARGE command
delay
Write recovery time
Auto precharge write recovery +
precharge time
Internal WRITE-to-READ command delay
PRECHARGE command period
PRECHARGE ALL command period
LOAD MODE command cycle time
CKE low to CK, CK# uncertainty
REFRESH-to-ACTIVE or REFRESH-toREFRESH command interval
Average periodic refresh interval
Average periodic refresh interval
(industrial)
Exit self refresh to non-READ command
tRTP
7.5
7.5
ns
tWR
15
15
ns
18, 31,
37
21, 25,
37
25, 37
ns
20
ns
ns
ns
tCK
ns
25, 37
29, 37
29
37
26
70,000
ns
14, 37
7.8
7.8
µs
14, 37
3.9
3.9
µs
14, 37
Exit self refresh to READ command
Exit self refresh timing reference
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tDAL
tWR
tWTR
7.5
12.5
tRP + tCK
2
t
IS + tCK +tIH
tRP
tRPA
tMRD
t
70,000
DELAY
tRFC
+ tRP
127.5
tREFI
tREFI
IT
45
tWR
70,000
70,000
+ tRP
10
15
tRP + tCK
2
t
IS + tCK +tIH
127.5
ns
tXSRD
t
RFC
(MIN) + 10
200
t
RFC
(MIN) + 10
200
tCK
37
tISXR
tIS
tIS
ps
6, 27
tXSNR
129
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
AC Operating Specifications
Table 49:
AC Operating Conditions for -25E and -25 Speeds (Sheet 4 of 4)
Notes: 1–5; notes appear on page 131; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V
AC Characteristics
Parameter
ODT turn-on delay
ODT turn-on
ODT turn-off delay
ODT
ODT turn-off
ODT turn-on (power-down mode)
Power-Down
ODT turn-off (power-down mode)
ODT to power-down entry latency
ODT power-down exit latency
ODT enable from MRS command
Exit active power-down to READ
command, MR[12] = 0
Exit active power-down to READ
command, MR[12] = 1
Exit precharge power-down to any nonREAD command
CKE MIN HIGH/LOW time
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-25E
Symbol
t
AOND
Min
-25
Max
Min
2
Max
2
2
2
tAC (MAX)
(MAX)
t
t
t
AON
AC (MIN)
AC (MIN)
+ 700
+ 700
tAOFD
2.5
2.5
2.5
2.5
t
t
AC (MAX) t
AC (MAX)
t
t
AOF
AC (MIN)
AC (MIN)
+ 600
+ 600
t
2 x CK +
2 x tCK +
tAC
tAC
t
t
AC
AC
t
AONPD
(MIN) +
(MIN) +
(MAX) +
(MAX) +
2,000
2,000
1,000
1,000
2.5 x tCK +
2.5 x tCK +
t
tAC
tAC (MIN) +
tAC
tAOFPD AC (MIN) +
2,000
(MAX) +
2,000
(MAX) +
1,000
1,000
tANPD
3
3
tAXPD
10
10
tMOD
12
12
tAC
Units
t
Notes
CK
37
ps
23, 43
tCK
35, 37
ps
24, 44
ps
ps
tCK
ns
37
37
37, 49
tCK
tXARD
2
2
tCK
37
tXARDS
8 - AL
8 - AL
tCK
37
tXP
2
2
tCK
37
tCKE
3
3
tCK
32, 37
130
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Notes
Notes
1. All voltages are referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operation are guaranteed for the full voltage range specified. ODT is disabled for all
measurements that are not ODT-specific.
3. Outputs measured with equivalent load:
VTT = VDDQ/2
Output
(VOUT)
25Ω
Reference
Point
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.0V in the test environment and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The slew rate for the input signals used to test the
device is 1.0 V/ns for signals in the range between VIL(AC) and VIH(AC). Slew rates
other than 1.0 V/ns may require the timing parameters to be derated as specified.
5. The AC and DC input level specifications are as defined in the SSTL_18 standard (i.e.,
the receiver will effectively switch as a result of the signal crossing the AC input level
and will remain in that state as long as the signal does not ring back above [below] the
DC input LOW [HIGH] level).
6. There are two sets of values listed for Command/Address: tISa, tIHa and tISb, tIHb. The
t
ISa, tIHa values (for reference only) are equivalent to the baseline values of tISb, tIHb
at VREF when the slew rate is 1 V/ns. The baseline values, tISb, tIHb, are the JEDECdefined values, referenced from the logic trip points. tISb is referenced from VIH(AC)
for a rising signal and VIL(AC) for a falling signal, while tIHb is referenced from VIL(DC)
for a rising signal and VIH(DC) for a falling signal. If the Command/Address slew rate is
not equal to 1 V/ns, then the baseline values must be derated by adding the values
from Tables 26 and 27 on page 94.
7. The values listed are for the differential DQS strobe (DQS and DQS#) with a differential slew rate of 2 V/ns (1 V/ns for each signal). There are two sets of values listed: tDSa,
t
DHa and tDSb, tDHb. The tDSa, tDHa values (for reference only) are equivalent to the
baseline values of tDSb, tDHb at VREF when the slew rate is 2 V/ns, differentially. The
baseline values, tDSb, tDHb, are the JEDEC-defined values, referenced from the logic
trip points. tDSb is referenced from VIH(AC) for a rising signal and VIL(AC) for a falling
signal, while tDHb is referenced from VIL(DC) for a rising signal and VIH(DC) for a falling signal. If the differential DQS slew rate is not equal to 2 V/ns, then the baseline values must be derated by adding the values from Tables 28 and 29 on pages 99–100. If
the DQS differential strobe feature is not enabled, then the DQS strobe is singleended, the baseline values not applicable, and timing is not referenced to the logic
trip points. Single-ended DQS data timing is referenced to DQS crossing VREF. The
correct timing values for a single-ended DQS strobe are listed in Tables 30–33 on
pages 101–102; listed values are already derated for slew rate variations and can be
used directly from the table.
8. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (tHZ) or begins driving (tLZ).
9. This maximum value is derived from the referenced test load. tHZ (MAX) will prevail
over tDQSCK (MAX) + tRPST (MAX) condition.
10. tLZ (MIN) will prevail over a tDQSCK (MIN) + tRPRE (MAX) condition.
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1Gb: x4, x8, x16 DDR2 SDRAM
Notes
11. The intent of the “Don’t Care” state after completion of the postamble is that the DQSdriven signal should either be HIGH, LOW, or High-Z, and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions HIGH (above VIH[DC] MIN), then it must not transition LOW (below
VIH[DC]) prior to tDQSH (MIN).
12. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
13. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
14. The refresh period is 64ms (commercial) or 32ms (industrial). This equates to an average refresh rate of 7.8125µs (commercial) or 3.9607µs (industrial). However, a
REFRESH command must be asserted at least once every 70.3µs or tRFC (MAX). To
ensure all rows of all banks are properly refreshed, 8,192 REFRESH commands must
be issued every 64ms (commercial) or 32ms (industrial).
15. Referenced to each output group: x4 = DQS with DQ0–DQ3; x8 = DQS with DQ0–DQ7;
x16 = LDQS with DQ0–DQ7; and UDQS with DQ8–DQ15.
16. CK and CK# input slew rate is referenced at 1 V/ns (2 V/ns if measured differentially).
17. The data valid window is derived by achieving other specifications: tHP (tCK/2),
t
DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived.
18. READs and WRITEs with auto precharge are allowed to be issued before tRAS (MIN) is
satisfied since tRAS lockout feature is supported in DDR2 SDRAM.
19. VIL/VIH DDR2 overshoot/undershoot. See “AC Overshoot/Undershoot Specification”
on page 110.
t
20. DAL = (nWR) + (tRP/tCK). Each of these terms, if not already an integer, should be
rounded up to the next integer. tCK refers to the application clock period; nWR refers
to the tWR parameter stored in the MR[11, 10, 9]. For example, -37E at tCK = 3.75ns
with tWR programmed to four clocks would have tDAL = 4 + (15ns/3.75ns) clocks = 4 +
(4) clocks = 8 clocks.
21. The minimum internal READ to PRECHARGE time. This is the time from the last 4-bit
prefetch begins to when the PRECHARGE command can be issued. A 4-bit prefetch is
when the READ command internally latches the READ so that data will output CL
later. This parameter is only applicable when tRTP / (2 x tCK) > 1, such as frequencies
faster than 533 MHz when tRTP = 7.5ns. If tRTP / (2 x tCK) ≤ 1, then equation AL + BL/
2 applies. tRAS (MIN) also has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal PRECHARGE command until tRAS (MIN) has been satisfied.
22. Operating frequency is only allowed to change during self refresh mode (see Figure 58
on page 76), precharge power-down mode, or system reset condition (See “Reset
Function” on page 77). SSC allows for small deviations in operating frequency, provided the SSC guidelines are satisfied.
23. ODT turn-on time tAON (MIN) is when the device leaves High-Z and ODT resistance
begins to turn on. ODT turn-on time tAON (MAX) is when the ODT resistance is fully
on. Both are measured from tAOND.
24. ODT turn-off time tAOF (MIN) is when the device starts to turn off ODT resistance.
ODT turn off time tAOF (MAX) is when the bus is in High-Z. Both are measured from
tAOFD.
25. This parameter has a two clock minimum requirement at any tCK.
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1Gb: x4, x8, x16 DDR2 SDRAM
Notes
26. tDELAY is calculated from tIS + tCK + tIH so that CKE registration LOW is guaranteed
prior to CK, CK# being removed in a system RESET condition. See “Reset Function” on
page 77.
t
27. ISXR is equal to tIS and is used for CKE setup time during self refresh exit, as shown in
Figure 47 on page 67.
28. No more than four bank-ACTIVE commands may be issued in a given tFAW (MIN)
period. tRRD (MIN) restriction still applies. The tFAW (MIN) parameter applies to all
8-bank DDR2 devices, regardless of the number of banks already open or closed.
29. tRPA timing applies when the PRECHARGE (ALL) command is issued, regardless of
the number of banks already open or closed. If a single-bank PRECHARGE command
is issued, tRP timing applies. tRPA (MIN) applies to all 8-bank DDR2 devices.
30. N/A.
31. This is applicable to READ cycles only. WRITE cycles generally require additional time
due to tWR during auto precharge.
t
32. CKE (MIN) of three clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to
achieve the three clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2 x tCK + tIH.
33. This parameter is not referenced to a specific voltage level, but specified when the
device output is no longer driving (tRPST) or beginning to drive (tRPRE).
34. When DQS is used single-ended, the minimum limit is reduced by 100ps.
35. The half-clock of tAOFD’s 2.5 tCK assumes a 50/50 clock duty cycle. This half-clock
value must be derated by the amount of half-clock duty cycle error. For example, if the
clock duty cycle was 47/53, tAOFD would actually be 2.5 - 0.03, or 2.47, for tAOF (MIN)
and 2.5 + 0.03, or 2.53, for tAOF (MAX).
36. The clock’s tCKAVG is the average clock over any 200 consecutive clocks and tCKAVG
(MIN) is the smallest clock rate allowed, except a deviation due to allowed clock jitter.
Input clock jitter is allowed provided it does not exceed values specified. Also, the jitter must be of a random Gaussian distribution in nature.
37. The inputs to the DRAM must be aligned to the associated clock; that is, the actual
clock that latches it in. However, the input timing (in ns) references to the tCKAVG
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the tCKAVG rather than tCK: tIPW,
tDIPW, tDQSS, tDQSH, tDQSL, tDSS, tDSH, tWPST, and tWPRE.
38. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz with
additional one percent of tCKAVG as a long-term jitter component; however, the
spread spectrum may not use a clock rate below tCKAVG(MIN) or above tCKAVG(MAX).
39. The period jitter (tJITPER) is the maximum deviation in the clock period from the average or nominal clock allowed in either the positive or negative direction. JEDEC specifies tighter jitter numbers during DLL locking time. During DLL lock time, the jitter
values should be 20 percent less than noted in the table (DLL locked).
40. The half-period jitter (tJITDTY) applies to either the high pulse of clock or the low pulse
of clock; however, the two cumulatively can not exceed tJITPER.
41. The cycle-to-cycle jitter (tJITCC) is the amount the clock period can deviate from one
cycle to the following cycle. JEDEC specifies tighter jitter numbers during DLL locking
time. During DLL lock time, the jitter values should be 20 percent less than noted in
the table (DLL locked).
42. The cumulative jitter error (tERRnPER), where n is 2, 3, 4, 5, 6–10, or 11–50, is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
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©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Notes
43. The DRAM output timing is aligned to the nominal or average clock. Most output
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting tERR5PER (MAX): tAC (MIN), tDQSCK (MIN),
t
LZDQS (MIN), tLZDQ (MIN), tAON (MIN); while these following parameters are
required to be derated by subtracting tERR5PER (MIN): tAC (MAX), tDQSCK (MAX), tHZ
(MAX), tLZDQS (MAX), tLZDQ (MAX), tAON (MAX). The parameter tRPRE (MIN) is derated by subtracting tJITPER (MAX), while tRPRE (MAX), is derated by subtracting tJITPER
(MIN). The parameter tRPST (MIN) is derated by subtracting tJITDTY (MAX), while
t
RPST (MAX), is derated by subtracting tJITDTY (MIN).
44. Half-clock output parameters must be derated by the actual tERR5PER and tJITDTY
when input clock jitter is present; this will result in each parameter becoming larger.
The parameter tAOF (MIN) is required to be derated by subtracting both tERR5PER
(MAX) and tJITDTY (MAX). The parameter tAOF (MAX) is required to be derated by
subtracting both tERR5PER (MIN) and tJITDTY (MIN).
45. MIN(tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock
HIGH time driven to the device. The clock’s half period must also be of a Gaussian distribution; tCHAVG and tCLAVG must be met with or without clock jitter and with or
without duty cycle jitter. tCHAVG and tCLAVG are the average of any 200 consecutive CK
falling edges.
46. tHP (MIN) is the lesser of tCL and tCH actually applied to the device CK and CK#
inputs; thus, tHP (MIN) ≥ the lesser of tCLABS (MIN) and tCHABS (MIN).
47. tQH = tHP - tQHS; the worst case tQH would be the smaller of tCLABS (MAX) or tCHABS
(MAX) times tCKABS (MIN) - tQHS. Minimizing the amount of tCHAVG offset and value
of tJITDTY will provide a larger tQH, which in turn will provide a larger valid data out
window.
48. JEDEC specifies using tERR6–10PER when derating clock-related output timing (notes
43–44). Micron requires less derating by allowing tERR5PER to be used.
49. Requires 8 tCK for backward compatibility.
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134
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1Gb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Package Dimensions
Figure 92:
84-Ball FBGA Package – 10mm x 16.5mm (x16)
0.65 ±0.05
0.155 ±0.013
SEATING
PLANE
C
0.10 C
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø 0.33
NON SOLDER MASK DEFINED
SUBSTRATE:
PLASTIC LAMINATE
MOLD COMPOUND:
EPOXY NOVOLAC
1.80 ±0.05
CTR
6.40
84X Ø 0.45
SOLDER BALL
DIAMETER REFERS TO
POST REFLOW CONDITION.
THE PRE-REFLOW
DIAMETER IS Ø 0.42
0.80 TYP
BALL A1 ID
BALL A1 ID
BALL A1
8.25 ±0.05
BALL A9
CL
11.20
5.60
16.50 ±0.10
0.80 TYP
CL
3.20
5.00 ±0.05
1.00 MAX
10.00 ±0.10
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
All dimensions are in millimeters.
135
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 93:
68-Ball FBGA Package – 10mm x 16.5mm (x4/x8)
0.65 ±0.05
0.155 ±0.013
SEATING PLANE
C
0.10 C
SOLDER BALL MATERIAL:
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD:
Ø 0.33 NON SOLDER MASK DEFINED
1.80 ±0.05
CTR
68X Ø0.45
SOLDER BALL
DIAMETER REFERS TO
POST REFLOW CONDITION.
THE PRE-REFLOW
DIAMETER IS Ø0.42.
SUBSTRATE: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
6.40
BALL A1
BALL A1 ID
0.80
TYP
BALL A9
BALL #1 ID
3.20
8.25 ±0.05
CL
14.40
16.50 ±0.10
7.20
0.80 TYP
CL
3.20
5.00 ±0.05
1.00 MAX
10.00 ±0.10
Note:
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1GbDDR2_2.fm - Rev. K 4/06 EN
All dimensions are in millimeters.
136
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
1Gb: x4, x8, x16 DDR2 SDRAM
Package Dimensions
Figure 94:
92-Ball FBGA Package – 11mm x 19mm (x4/x8/x16)
0.80 ±0.05
0.17 MAX
SEATING
PLANE
C
0.10 C
92X Ø 0.45
SOLDER BALL
DIAMETER REFERS
TO POST REFLOW
CONDITION. THE
PRE-REFLOW
DIAMETER IS Ø 0.42.
SOLDER BALL MATERIAL:
62% Sn, 36% Pb, 2% Ag OR
96.5% Sn, 3% Ag, 0.5% Cu
SOLDER BALL PAD: Ø 0.33
NON SOLDER MASK DEFINED
1.80 ±0.05
CTR
SUBSTRATE:
PLASTIC LAMINATE
6.40
MOLD COMPOUND:
EPOXY NOVOLAC
BALL A1 ID
BALL A1
BALL A1 ID
0.80
TYP
2.40
9.50 ±0.05
BALL A9
CL
16.00
19.00 ±0.10
8.00
0.80
TYP
CL
3.20
1.20 MAX
5.50 ±0.05
11.00 ±0.10
Note:
All dimensions are in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of
their respective owners.
This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range
for production devices. Although considered final, these specifications are subject to change, as further product
development and data characterization sometimes occur.
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