64Mb: x16
MOBILE SDRAM
SYNCHRONOUS
DRAM
MT48H4M16LF - 1 MEG x 16 x 4 BANKS
Features
Figure 1: 54-Ball FBGA Pin Assignment
(Top View)
• Temperature compensated self refresh (TCSR)
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes concurrent auto
precharge, and auto refresh modes
• Self refresh mode; standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Low voltage power supply
• Partial array self refresh power-saving mode
• Deep power-down mode
• Programmable output drive strength
• Operating temperature ranges:
Extended (-25°C to +85°C)
Industrial (-40°C to +85°C)
OPTIONS
1
2
3
A
VSS
DQ15
B
DQ14
C
7
8
9
VSSQ
VDDQ
DQ0
VDD
DQ13
VDDQ
VSSQ
DQ2
DQ1
DQ12
DQ11
VSSQ
VDDQ
DQ4
DQ3
D
DQ10
DQ9
VDDQ
VSSQ
DQ6
DQ5
E
DQ8
NC
VSS
VDD
LDQM
DQ7
F
UDQM
CLK
CKE
CAS#
RAS#
WE#
G
NC/A12
A11
A9
BA0
BA1
CS#
H
A8
A7
A6
A0
A1
A10
J
VSS
A5
A4
A3
A2
VDD
MARKING
• VDD/VDDQ
1.8V/1.8V
• Configurations
4 Meg x 16 (1 Meg x 16 x 4 banks)
• Package/Ball out
54-ball FBGA, 8mm x 8mm (standard)
54-ball FBGA, 8mm x 8mm (lead-free)
• Timing (Cycle Time)
8ns @ CL = 3 (125 MHz)
9.6ns @ CL = 3 (104 MHz)
• Operating Temperature
Extended (-25°C to +85°C)
Industrial (-40°C to +85°C)
5
6
Top View
(Ball Down)
H
Table 1:
4M16
Address Table
4 MEG x 16
F4
B4
1 Meg x 16 x 4 banks
4K
4K (A0–A11)
4 (BA0, BA1)
256 (A0–A7)
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
-8
-10
none
IT
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
FBGA Part Number System
Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. For a quick conversion of an
FBGA code, see the FBGA Part Marking Decoder on the
Micron web site, www.micron.com/decoder.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_1.fm - Rev. E 11/04 EN
4
SPEED
CLOCK
GRADE FREQUENCY
-8
-10
-8
-10
1
125 MHz
104 MHz
104 MHz
83 MHz
ACCESS TIME
CL = 2
CL = 3
–
8ns
8ns
6ns
7ns
–
-
SETUP HOLD
TIME TIME
2.5ns
2.5ns
2.5ns
2.5ns
1ns
1ns
1ns
1ns
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
64Mb: x16
MOBILE SDRAM
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
FBGA Part Number System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Partial Array Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Command Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Deep Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Bank/row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
DEEP POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
WRITE with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64MTOC.fm - Rev. E 11/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
Figure 46:
Figure 47:
Figure 48:
Figure 49:
Figure 50:
54-Ball FBGA Pin Assignment (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Part Numbering Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Functional Block Diagram 4 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Extended Mode Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Activating a Specific Row in a Specific Bank Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK< 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ to WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WRITE to READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Initialize and Load Mode Register1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Power-Down Mode1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Clock Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
READ – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Single READ – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Single READ – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
READ – Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
READ – DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
WRITE – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
WRITE – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Single WRITE – Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Single WRITE – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
WRITE – Full-page Burst1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
WRITE – DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
54-Ball FBGA (8mm x 8mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Address Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Truth Table 1 – Commands and DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Truth Table 2 – CKE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Truth Table 3 – Current State Bank n, Command to Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Truth Table 4 – Current State Bank n, Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .31
AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
IDD7 - Self Refresh Current Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 2: Part Numbering Diagram
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0–A11 select the row). The
address bits registered coincident with the READ or
WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or
write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.
The 64Mb SDRAM is designed to operate in 1.8V,
low-power memory systems. An auto refresh mode is
provided, along with a power-saving, Deep PowerDown Mode. All inputs and outputs are LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.
Example Part Number: MT48H4M16LF-8 IT
–
MT48
VDD/
VDDQ
Configuration
Package
Temp
Speed
Operating Temp
VDD/VDDQ
1.8/1.8V
H
None
Extended
IT
Industrial
Configuration
4 Meg x16
4M16LF
Package
Speed Grade
54-ball VFBGA (8mm x 8mm)
F4
-8
8ns
54-ball VFBGA (8mm x 8mm) Lead-Free
B4
-10
9.6ns
General Description
The Micron® 64Mb SDRAM is a high-speed CMOS,
dynamic
random-access
memory
containing
67,108,864-bits. It is internally configured as a quadbank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 3: Functional Block Diagram 4 Meg x 16 SDRAM
BA1
0
0
1
1
CKE
BA0
0
1
0
1
Bank
0
1
2
3
CLK
COMMAND
DECODE
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
REFRESH 12
COUNTER
12
ROWADDRESS
MUX
12
12
BANK0
ROWADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 256 x 16)
2
DQML,
DQMH
SENSE AMPLIFIERS
16
4096
14
ADDRESS
REGISTER
2
DATA
OUTPUT
REGISTER
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
2
A0-A11,
BA0, BA1
2
BANK
CONTROL
LOGIC
16
16
256
(x16)
DQ0DQ15
DATA
INPUT
REGISTER
COLUMN
DECODER
8
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COLUMNADDRESS
COUNTER/
LATCH
8
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Table 3:
Ball Descriptions
54-BALL FBGA
SYMBOL
TYPE
DESCRIPTION
F2
CLK
Input
F3
CKE
Input
G9
CS#
Input
F7, F8, F9
CAS#, RAS#,
WE#
LDQM,
UDQM
Input
G7, G8
BA0, BA1
Input
H7, H8, J8, J7, J3, J2, H3,
H2, H1, G3, H9, G2
A0–A11
Input
A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,
C1, B2, B1, A2
E2, G1
DQ0–DQ15
I/O
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank), DEEP POWER DOWN (all banks idle), or CLOCK SUSPEND
operation (burst/access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE becomes
asynchronous until after exiting the same mode. The input buffers,
including CLK, are disabled during power-down and self refresh modes,
providing low standby power. CKE may be tied HIGH.
Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.
Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.
Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. LDQM corresponds to
DQ0–DQ7, UDQM corresponds to DQ8–DQ15. LDQM and UDQM are
considered same state when referenced as DQM.
Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied. These pins also
select between the mode register and the extended mode register.
Address Inputs: A0–A11 are sampled during the ACTIVE command (rowaddress A0–A11) and READ/WRITE command (column-address A0–A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1. The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
Data Input/Output: Data bus.
NC
–
A7, B3, C7, D3
A3, B7, C3, D7
A9, E7, J9
A1, E3, J1
VDDQ
VSSQ
VDD
VSS
Supply
Supply
Supply
Supply
E8, F1
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Input
These could be left unconnected, but it is recommended they be
connected to VSS. G1 is a no connect for this part but may be used as A12
in future designs.
DQ Power: Provide isolated power to DQs for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
Core Power Supply.
Ground.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Functional Description
Mode Register Definition
In general, the 64Mb SDRAMs (1 Meg x 16 x 4 banks)
are quad-bank DRAMs that operate at 1.8V and
include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK).
Each of the x16’s 16,777,216-bit banks is organized as
4,096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a
programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0-A11 select the row).
The address bits (A0–A7) registered coincident with
the READ or WRITE command are used to select the
starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register
definition, command descriptions and device operation.
In order to achieve low power consumption, there
are two mode registers in the mobile component,
mode register and extended mode register. The mode
register is illustrated in Figure 4, Mode Register Definition, on page 9 (the extended mode register is illustrated in Figure 6, Extended Mode Register Table, on
page 11).
The mode register defines the specific mode of
operation of the SDRAM, including burst length, burst
type, CAS latency, operating mode and write burst
mode. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10, and M11 should be set to zero.
M12 and M13 should be set to zero to prevent
extended mode register.
The mode register must be loaded when all banks
are idle, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined operation. Power should be applied to VDD and VDDQ simultaneously. Once the power is applied to VDD and VDDQ
and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the
clock pin), the SDRAM requires a 100µs delay prior to
issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100µs period and continuing at least through the end
of this period, command inhibit or NOP commands
should be applied.
Once the 100µs delay has been satisfied with at least
one command inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All banks must then be precharged, thereby placing
the device in the all banks idle state.
Once in the idle state, two AUTO refresh cycles must
be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.
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Burst Length
Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition, on
page 9. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2,
4, or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A0–A7 when the burst length is set to two;
by A2–A7 when the burst length is set to four; and by
A3–A7 when the burst length is set to eight.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Table 4:
Burst Definition
7. For a burst length of one, A0–A7 select the unique column to be accessed, and mode register bit M3 is
ignored.
ORDER OF ACCESSES WITHIN
A BURST
BURST
LENGTH
STARTING
COLUMN
ADDRESS
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
0
0-1
0-1
1
1-0
1-0
Figure 4: Mode Register Definition
BA1 BA0
A0
2
4
1
1
A8
M13 M12 M11 M10 M9 M8
13
0
1
0-1-2-3
1-2-3-0
0
1
2-3-0-1
3-0-1-2
12
11
10
9
Reserved** Reserved* WB
8
A7
A6
M7 M6
6
7
Op Mode
A5
A4
A3
M5
M4
5
4
CAS Latency
0-1-2-3
1-0-3-2
M3
M2
BT
A1
Address Bus
A0
M1
1
2
M0
0
Mode Register (Mx)
Burst Length
Burst Length
M2 M1 M0
** BA1, BA0 = “0, 0”
to prevent Extended
Mode Register.
2-3-0-1
3-2-1-0
A2
3
*Should program
M10 = “0, 0”
to ensure compatibility
with future devices.
A1 A0
0
0
A9
A11 A10
M3 = 0
M3 = 1
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Full Page
Reserved
A2 A1 A0
8
Full
Page (y)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
n = A0–A7
(location
0-y)
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
Cn, Cn+1,
Not Supported
Cn+2, Cn+3,
Cn+4..., …Cn-1,
Cn…
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
CAS Latency
0
0
0
Reserved
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
All other states reserved
NOTE:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1–A7 select the block-oftwo burst; A0 selects the starting column within the
block.
3. For a burst length of four, A2–A7 select the block-offour burst; A0–A1 select the starting column within the
block.
4. For a burst length of eight, A3–A7 select the block-ofeight burst; A0–A2 select the starting column within
the block.
5. For a full-page burst, the full row is selected and A0–A7
select the starting column.
6. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
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M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4.
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
CAS Latency
Table 5:
The CAS latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to one, two, or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 5, CAS Latency.
Table 5, indicates the operating frequencies at which
each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
ALLOWABLE OPERATING
FREQUENCY (MHZ)
T1
T2
READ
NOP
NOP
tLZ
T3
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
CLK
tOH
DOUT
tAC
CASLatency = 3
DON’T CARE
UNDEFINED
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≤ 125
≤ 104
The extended mode register controls the functions
beyond those controlled by the mode register. These
additional functions are special features of the mobile
device. They include temperature compensated self
refresh (TCSR) control, partial array self refresh (PASR),
and output drive strength. Not programming the
extended mode register upon initialization, will result
in default settings for the low power features. The
extended mode will default to the +85°C setting for
TCSR, full drive strength, and full array refresh.
The extended mode register is programmed via the
MODE REGISTER SET command (BA1 = 1, BA0 = 0)
and retains the stored information until it is programmed again or the device loses power.
The extended mode register must be programmed
with E6 through E11 set to “0.” It must be loaded when
all banks are idle and no bursts are in progress, and the
controller must wait the specified time before initiating any subsequent operation. Violating either of these
requirements results in unspecified operation.
Once the values are entered the extended mode register settings will be retained even after exiting deep
power-down.
CASLatency = 2
DQ
≤ 104
≤ 83.3
Extended Mode Register
DOUT
tLZ
-8
-10
When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9
= 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst) accesses.
tAC
COMMAND
CAS LATENCY = 3
Write Burst Mode
tOH
DQ
CAS LATENCY = 2
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
CLK
COMMAND
SPEED
Operating Mode
Figure 5: CAS Latency
T0
CAS Latency
10
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64Mb: x16
MOBILE SDRAM
Temperature Compensated Self Refresh
Driver Strength
Temperature compensated self refresh (TCSR)
allows the controller to program the refresh interval
during self refresh mode, according to the case temperature of the mobile device. This allows great power
savings during SELF REFRESH during most operating
temperature ranges. Only during extreme temperatures would the controller have to select the maximum
TCSR level. This would guarantee data during SELF
REFRESH.
Every cell in the SDRAM requires refreshing due to
the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher temperatures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during self refresh, the refresh rate
has been set to accommodate the worst case, or highest temperature range expected.
Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. Adjusting the refresh rate by setting E4
and E3 allows the SDRAM to accommodate more specific temperature regions during SELF REFRESH.
There are four temperature settings, which will vary
the SELF REFRESH current according to the selected
temperature. This selectable refresh rate will save
power when the SDRAM is operating at normal temperatures.
Bits E5 and E6 of the extended mode register can be
used to select the driver strength of the DQ outputs.
This value should be set according to the application’s
requirements. Full drive strength was carried over
from standard SDRAM and is suitable to drive higher
load systems. Full drive strength is not recommended
for loads under 30pF. Half drive strength is intended
for multi-drop systems with various loads. This drive
option is not recommended for loads under 15pF.
Quarter drive strength is intended for lighter loads or
point-to-point systems.
Figure 6: Extended Mode Register
Table
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
13 12 11 10
1
9
8
7
6
0 All must be set to "0"
DS
5
4
3
TCSR
2
1
0
PASR
E6 E5 Driver Strength
E4
0 0 Full Strength3
1
1
85˚C3
0 1 Half Strength
0
0
70˚C
1 0 Quarter Strength
0
1
45˚C
1 1 Reserved
1
0
15˚C
Extended Mode
Register (Ex)
E3 Maximum Case Temp
E2
E1
E0
Partial Array Self Refresh
0
0
0
Four Banks3
For further power savings during SELF REFRESH,
the partial array self refresh (PASR) feature allows the
controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options
are all banks (banks 0, 1, 2, and 3); two banks (banks 0
and 1); and one bank (bank 0). Also included in the
refresh options are the 1/2 bank and 1/4 bank partial
array self refresh (bank 0). WRITE and READ commands occur to any bank selected during standard
operation, but only the selected banks in PASR will be
refreshed during SELF REFRESH. It’s important to note
that data in unused banks, or portions of banks, will be
lost when PASR is used. Data will be lost in banks 1, 2,
and 3 when the one bank option is used.
0
0
1
Two Banks (Bank 0,1)
0
1
0
One Bank (Bank 0)
0
1
1
RFU
1
0
0
RFU
1
0
1
1/2 Bank (Bank 0)4
1
1
0
1/4 Bank (Bank 0)5
1
1
1
RFU
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Self Refresh Coverage
NOTE:
1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the
extended mode register (vs. the base mode register).
2. RFU: Reserved for future use
3. Default EMR values are full array for PASR, full drive
strength, and 85° for TCSR.
4. E11 = 0
5. E10, E11 = 0
11
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64Mb: x16
MOBILE SDRAM
Commands
Figure 6, Truth Table 1 – Commands and DQM
Operation1 provides a quick reference of available
commands. This is followed by a written description of
Table 6:
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.
Truth Table 1 – Commands and DQM Operation1
NAME (FUNCTION)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE or DEEP POWER DOWN
(Enter deep power down mode)
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)
LOAD MODE REGISTER/LOAD EXTENDED MODE
REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
CS# RAS# CAS# WE#
DQM
ADDR
DQS
NOTES
H
L
L
L
L
L
X
H
L
H
H
H
X
H
H
L
L
H
X
H
H
H
L
L
X
X
X
L/H
L/H
X
X
X
Bank/Row
Bank/Col
Bank/Col
X
X
X
X
X
Valid
X
3
4
4
9, 10
L
L
L
L
H
L
L
H
X
X
Bank, A10
X
X
X
5
6, 7
L
L
L
L
X
Op-Code
X
2
X
X
X
X
X
X
X
X
L
H
X
X
Active
High-Z
8
8
NOTE:
1.
2.
3.
4.
CKE is HIGH for all commands shown except SELF REFRESH and DEEP POWER DOWN
A0-A11 define op-code written to mode register.
A0–A11 provide row address, and BA0, BA1 determine which bank is made active.
A0–A7 provide column address; A10 HIGH enables the auto precharge feature (non persistent), while A10 LOW disables
the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t
Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQML controls DQ0-7,
DQMH controls DQ8-15.
9. This command is BURST TERMINATE when CKE is high and DEEP POWER DOWN when CKE is low.
10. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on
the bus. However the DQs column reads a don’t care state to illustrate that the BURST TERMINATE command can occur
when there is no data present.
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MOBILE SDRAM
Command Inhibit
WRITE
The COMMAND INHIBIT function prevents new
commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
The WRITE command is used to initiate a burst
write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0–A7 selects the starting column location.
The value on input A10 determines whether or not
auto precharge is used. If auto precharge is selected,
the row being accessed will be precharged at the end of
the write burst; if auto precharge is not selected, the
row will remain open for subsequent accesses. Input
data appearing on the DQ is written to the memory
array subject to the DQM input logic level appearing
coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to
memory; if the DQM signal is registered HIGH, the
corresponding data inputs will be ignored, and a write
will not be executed to that byte/column location.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to
perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.
LOAD MODE REGISTER
The mode register is loaded via inputs A0–A11, BA0,
BA1. See mode register heading in the Register Definition section. The LOAD MODE REGISTER and LOAD
EXTENDED MODE REGISTER commands can only be
issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.
The values of the mode register and extended mode
register will be retained even when exiting deep
power-down.
PRECHARGE
The PRECHARGE command is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (tRP) after the precharge
command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
“Don’t Care.” Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.
ACTIVE
The ACTIVE command is used to open (or activate)
a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0–A11 selects the row.
This row remains active (or open) for accesses until a
precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank.
Auto Precharge
Auto precharge is a feature which performs the
same individual-bank precharge function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable auto precharge
in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE
burst, except in the full-page burst mode, where auto
precharge does not apply. Auto precharge is non persistent in that it is either enabled or disabled for each
individual Read or Write command.
Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (tRP) is completed. This is
determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this
data sheet.
READ
The READ command is used to initiate a burst read
access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0–A7 selects the starting column location. The
value on input A10 determines whether or not auto
precharge is used. If auto precharge is selected, the row
being accessed will be precharged at the end of the
read burst; if auto precharge is not selected, the row
will remain open for subsequent accesses. Read data
appears on the DQ subject to the logic level on the
DQM inputs two clocks earlier. If a given DQM signal
was registered HIGH, the corresponding DQ will be
High-Z two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data.
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MOBILE SDRAM
AUTO REFRESH
AUTO REFRESH is used during normal operation of
the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) refresh in conventional DRAMs. This command
is non persistent, so it must be issued each time a
refresh is required. All active banks must be PRECHARGED prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be
issued until the minimum tRP has been met after the
PRECHARGE command as shown in the operation section.
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
during an AUTO REFRESH command. The 64Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (tREF). Providing a distributed AUTO REFRESH
command every 15.625µs will meet the refresh
requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be
issued in a burst at the minimum cycle rate (tRFC),
once every 64ms.
tered, all the inputs to the SDRAM become “Don’t
Care” with the exception of CKE, which must remain
LOW.
Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform
its own auto refresh cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to
tRAS and may remain in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a
sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for tXSR because time is required for the completion of any internal refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands should be issued at once and then every
15.625µs or less, as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
SELF REFRESH
Deep Power-Down
The SELF REFRESH command can be used to retain
data in the SDRAM, even if the rest of the system is
powered down, as long as power is not completely
removed from the SDRAM. When in the self refresh
mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an
AUTO REFRESH command except CKE is disabled
(LOW). Once the SELF REFRESH command is regis-
The operating mode deep power-down achieves
maximum power reduction by eliminating the power
of the whole memory array of the device. Array data
will not be retained once the device enters deep
power-down mode.
This mode is entered by having all banks idle then
CS# and WE# held low with RAS# and CAS# held high
at the rising edge of the clock, while CKE is low. This
mode is exited by asserting CKE high.
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MOBILE SDRAM
Operation
Bank/row Activation
head. The minimum time interval between successive
ACTIVE commands to different banks is defined by
t
RRD.
Before any READ or WRITE commands can be
issued to a bank within the SDRAM, a row in that bank
must be “opened.” This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated (see Figure 7, Activating a Specific Row in a Specific Bank Register).
After opening a row (issuing an ACTIVE command),
a READ or WRITE command may be issued to that row,
subject to the tRCD specification. tRCD (MIN) should
be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a tRCD
specification of 20ns with a 125 MHz clock (8ns
period) results in 2.5 clocks, rounded to 3. This is
reflected in Figure 8, which covers any case where 2 <
t
RCD (MIN)/tCK ≤ 3. (The same procedure is used to
convert other specification limits from time units to
clock cycles.)
A subsequent ACTIVE command to a different row
in the same bank can only be issued after the previous
active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.
A subsequent ACTIVE command to another bank
can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-
Figure 7: Activating a Specific Row in a
Specific Bank Register
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
ROW
ADDRESS
A0–A10, A11
BANK
ADDRESS
BA0, BA1
DON’T CARE
Figure 8: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK< 3
T0
T1
T2
T3
NOP
NOP
T4
CLK
COMMAND
ACTIVE
READ or
WRITE
tRCD
DON’T CARE
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MOBILE SDRAM
READs
Data from any READ burst may be truncated with a
subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by
data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQ go High-Z. In this case, at least a singlecycle delay should occur between the last read data
and the WRITE command.
READ bursts are initiated with a READ command, as
shown in Figure 8.
The starting column and bank addresses are provided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic
READ commands used in the following illustrations,
auto precharge is disabled.
During READ bursts, the valid data-out element
from the starting column address will be available following the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 5, CAS Latency, on
page 10, shows general timing for each possible CAS
latency setting.
Upon completion of a burst, assuming no other
commands have been initiated, the DQ will go High-Z.
A full-page burst will continue until terminated. (At the
end of the page, it will wrap to column 0 and continue.)
Data from any READ burst may be truncated with a
subsequent READ command, and data from a fixedlength READ burst may be immediately followed by
data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last
element of a completed burst or the last desired data
element of a longer burst that is being truncated. The
new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one.
This is shown in Figure 10, Consecutive READ
Bursts, on page 17 for CAS latencies of two and three;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. The 64Mb SDRAM
uses a pipelined architecture and therefore does not
require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock
cycle following a previous READ command. Full-speed
random read accesses can be performed to the same
bank, as shown in Figure 11, Random READ Accesses,
on page 17, or each subsequent READ may be performed to a different bank.
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Figure 9: READ Command
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A7
COLUMN
ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0,1
BANK
ADDRESS
DON’T CARE
16
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MOBILE SDRAM
Figure 10: Consecutive READ Bursts
T0
T1
T2
T3
T4
T5
The DQM input is used to avoid I/O contention, as
shown in Figure 12, READ to WRITE, and Figure 13,
READ to WRITE with Extra Clock Cycle, on page 18.
The DQM signal must be asserted (HIGH) at least two
clocks prior to the WRITE command (DQM latency is
two clocks for output buffers) to suppress data-out
from the READ. Once the WRITE command is registered, the DQ will go High-Z (or remain High-Z),
regardless of the state of the DQM signal, provided the
DQM was active on the clock just prior to the WRITE
command that truncated the READ command. If not,
the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14, READ to
PRECHARGE, on page 18, then the WRITEs at T5 and
T7 would be valid, while the WRITE at T6 would be
invalid.
The DQM signal must be de-asserted prior to the
WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 13, READ to WRITE with Extra Clock
Cycle, shows the case where the clock frequency allows
for bus contention to be avoided without adding a
NOP cycle, and Figure 13 shows the case where the
additional NOP is needed. A fixed-length READ burst
may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-page burst may
be truncated with a PRECHARGE command to the
same bank. The PRECHARGE command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 14 for each
possible CAS latency; data element n + 3 is either the
last of a burst of four or the last desired of a longer
burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met. Note that part of the row precharge
time is hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
T6
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
X = 1 cycle
BANK,
COL b
DOUT
n
DQ
DOUT
n+2
DOUT
n+1
DOUT
n+3
DOUT
b
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
NOP
READ
NOP
NOP
X = 2 cycles
BANK,
COL b
DOUT
n+1
DOUT
n
DQ
DOUT
n+2
DOUT
n+3
DOUT
b
CAS Latency = 3
TRANSITIONING DATA
NOTE:
DON’T CARE
Each READ command may be to any bank.
DQM is LOW.
Figure 11: Random READ Accesses
T0
T1
T2
T3
T4
T5
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
NOP
DOUT
x
DOUT
a
DOUT
m
CAS Latency = 2
T0
T1
T2
T3
T4
T5
T6
CLK
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
DOUT
n
DQ
NOP
DOUT
a
NOP
DOUT
x
NOP
DOUT
m
CAS Latency = 3
TRANSITIONING DATA
NOTE:
DON’T CARE
Each READ command may be to any bank.
DQM is LOW.
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MOBILE SDRAM
Figure 12: READ to WRITE
T0
T1
T2
T3
Figure 14: READ to PRECHARGE
T0
T4
T1
T2
T3
T4
T5
T6
T7
CLK
CLK
t RP
DQM
COMMAND
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 1 cycle
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
WRITE
ADDRESS
BANK,
COL b
DQ
BANK
(a or all)
BANK a,
COL n
DOUT
n+2
DOUT
n+1
DOUT
n
BANK a,
ROW
DOUT
n+3
tCK
CAS Latency = 2
tHZ
DOUT n
DQ
DIN b
T0
tDS
T1
T2
T3
T4
T5
T6
t RP
DON’T CARE
COMMAND
NOTE:
A CAS latency of three is used for illustration.
The READ command may be to any bank,
and the WRITE command may be to any
bank. If a burst of one is used, then DQM is
not required.
T1
T2
T3
T4
READ
NOP
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
X = 2 cycles
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
DOUT
n+2
DOUT
n+1
DOUT
n
DQ
DOUT
n+3
CAS Latency = 3
TRANSITIONING DATA
Figure 13: READ to WRITE with Extra
Clock Cycle
T0
T7
CLK
NOTE:
DON’T CARE
DQM is LOW.
Figure 15: Terminating a READ Burst
T5
T0
CLK
T1
T2
T3
T4
T5
T6
CLK
DQM
COMMAND
COMMAND
READ
NOP
NOP
NOP
NOP
READ
NOP
NOP
NOP
WRITE
BURST
TERMINATE
NOP
NOP
X = 1 cycle
ADDRESS
BANK,
COL b
BANK,
COL n
ADDRESS
BANK,
COL n
tHZ
DQ
DOUT n
DOUT
n
DQ
DIN b
tDS
DOUT
n+2
DOUT
n+1
DOUT
n+3
CAS Latency = 2
T0
DON’T CARE
T1
T2
T3
T4
T5
T6
T7
CLK
NOTE:
A CAS latency of three is used for illustration.
The READ command may be to any bank,
and the WRITE command may be to any
bank.
COMMAND
READ
ADDRESS
BANK,
COL n
NOP
NOP
NOP
BURST
TERMINATE
NOP
NOP
NOP
X = 2 cycles
DOUT
n
DQ
DOUT
n+1
DOUT
n+2
DOUT
n+3
CAS Latency = 3
TRANSITIONING DATA
NOTE:
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DON’T CARE
DQM is LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 16: WRITE Command
Full-page READ bursts can be truncated with the
BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 15, Terminating a READ Burst, for each possible
CAS latency; data element n + 3 is the last desired data
element of a longer burst.
CLK
CKE HIGH
CS#
RAS#
CAS#
WE#
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 16, WRITE Command.
The starting column and bank addresses are provided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations,
auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain High-Z and
any additional input data will be ignored (see Figure
18, WRITE to WRITE). A full-page burst will continue
until terminated. (At the end of the page, it will wrap to
column 0 and continue.)
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A0-A8
COLUMN
ADDRESS
A9, A11
ENABLE AUTO PRECHARGE
A10
DISABLE AUTO PRECHARGE
BA0, 1
BANK
ADDRESS
VALID ADDRESS
DON’T CARE
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 19, Random
WRITE Cycles. Data n + 1 is either the last of a burst of
two or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on
any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 19, or
each subsequent WRITE may be performed to a different bank.
19
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MOBILE SDRAM
Figure 17: WRITE Burst
T0
T1
T2
T3
COMMAND
WRITE
NOP
NOP
NOP
ADDRESS
BANK,
COL n
Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued
tWR after the clock edge at which the last desired input
data element is registered. The auto precharge mode
requires a tWR of at least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the
DQM signal must be used to mask input data for the
clock edge prior to, and the clock edge coincident with,
the PRECHARGE command. An example is shown in
Figure 21, WRITE to PRECHARGE. Data n + 1 is either
the last of a burst of two or the last desired of a longer
burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued
until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.
Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 23, Terminating a WRITE Burst,
where data n is the last desired data element of a
longer burst.
CLK
DIN
n
DQ
DIN
n+1
DON’T CARE
NOTE:
Burst length = 2. DQM is LOW.
Figure 18: WRITE to WRITE
T0
T1
T2
COMMAND
WRITE
NOP
WRITE
ADDRESS
BANK,
COL n
CLK
DQ
DIN
n
BANK,
COL b
DIN
n+1
DIN
b
DON’T CARE
NOTE:
DQM is LOW. Each WRITE command may be
to any bank.
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a
READ command. Once the READ command is registered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 20,
WRITE to READ. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst.
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MOBILE SDRAM
Figure 19: Random WRITE Cycles
T0
T1
T2
Figure 21: WRITE to PRECHARGE
T3
T0
T1
T2
T3
WRITE
NOP
PRECHARGE
NOP
T4
T5
T6
NOP
ACTIVE
NOP
CLK
CLK
tWR @ tCK 15ns
COMMAND
WRITE
WRITE
WRITE
WRITE
DQM
ADDRESS
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
COMMAND
DIN
n
DIN
a
DIN
x
DIN
m
t RP
ADDRESS
DQ
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
DIN
n
DIN
n+1
DON’T CARE
NOTE:
tWR @ tCK < 15ns
Each WRITE command may be to any bank.
DQM is LOW.
DQM
t RP
Figure 20: WRITE to READ
T0
T1
T2
T3
T4
COMMAND
WRITE
NOP
NOP
PRECHARGE
NOP
NOP
ACTIVE
T5
ADDRESS
CLK
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t WR
DQ
COMMAND
WRITE
ADDRESS
BANK,
COL n
NOP
READ
NOP
NOP
DQ
DON’T CARE
DIN
n+1
DOUT
b
DOUT
b+1
The PRECHARGE command (see Figure 24, PRECHARGE Command, on page 22) is used to deactivate
the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access some specified time (tRP) after the precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in
the case where only one bank is to be precharged,
inputs BA0, BA1 select the bank. When all banks are to
be precharged, inputs BA0, BA1 are treated as “Don’t
Care.” Once a bank has been precharged, it is in the
idle state and must be activated prior to any READ or
WRITE commands being issued to that bank.
The WRITE command may be to any bank,
and the READ command may be to any bank.
DQM is LOW. CAS latency = 2 for illustration.
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DQM could remain LOW in this example if
the WRITE burst is a fixed length of two.
PRECHARGE
DON’T CARE
NOTE:
DIN
n+1
BANK,
COL b
NOTE:
DIN
n
DIN
n
NOP
21
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MOBILE SDRAM
POWER-DOWN
Figure 24: PRECHARGE Command
Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP
or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting tCKS). See Figure 22, PowerDown.
CLK
CKE
HIGH
CS#
RAS#
CAS#
WE#
A0-A9, A11
All Banks
Figure 22: Power-Down
A10
Bank Selected
((
))
((
))
CLK
tCKS
CKE
> tCKS
BANK
ADDRESS
BA0,1
((
))
COMMAND
VALID ADDRESS
((
))
((
))
NOP
NOP
tRCD
tRAS
All banks idle
Input buffers gated off
Enter power-down mode.
Exit power-down mode.
DEEP POWER-DOWN
tRC
Deep power down mode is a maximum power savings feature achieved by shutting off the power to the
entire memory array of the device. Data on the memory array will not be retained once deep power down
mode is executed. Deep power down mode is entered
by having all banks idle then CS# and WE# held low
with RAS# and CAS# high at the rising edge of the
clock, while CKE is low. CKE must be held low during
deep power-down.
In order to exit deep power down mode, CKE must
be asserted high. After exiting, the following sequence
is needed in order to enter a new command. Maintain
NOP input conditions for a minimum of 100us. Issue
PRECHARGE commands for all banks. Issue eight or
more AUTOREFRESH commands. The values of the
mode register and extended mode register will be
retained upon exiting deep power-down.
Figure 23: Terminating a WRITE Burst
T0
T1
COMMAND
WRITE
BURST
TERMINATE
ADDRESS
BANK,
COL n
(ADDRESS)
T2
DIN
n
(DATA)
CLK
DQ
TRANSITIONING DATA
NOTE:
DON’T CARE
ACTIVE
NEXT
COMMAND
DON’T CARE
DQMs are LOW.
CLOCK SUSPEND
The clock suspend mode occurs when a column
access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input
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64Mb: x16
MOBILE SDRAM
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Figure
25, Clock Suspend During WRITE Burst, and Figure 26,
Clock Suspend During READ Burst.)
Clock suspend mode is exited by registering CKE
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
Figure 25: Clock Suspend During WRITE
Burst
T0
T1
NOP
WRITE
T2
T3
T4
T5
NOP
NOP
DIN
n+1
DIN
n+2
CLK
CKE
BURST READ/SINGLE WRITE
INTERNAL
CLOCK
The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE commands result in the access of a single column location
(burst of one), regardless of the programmed burst
COMMAND
BANK,
COL n
ADDRESS
DIN
n
DIN
DON’T CARE
NOTE:
For this example, burst length = 4 or greater,
and DM is LOW.
Figure 26: Clock Suspend During READ
Burst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
COMMAND
READ
ADDRESS
BANK,
COL n
DQ
NOP
NOP
DOUT
n
NOP
DOUT
n+1
NOP
NOP
DOUT
n+2
DOUT
n+3
DON’T CARE
NOTE:
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For this example, CAS latency = 2, burst
length = 4 or greater, and DQM is LOW.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Concurrent Auto Precharge
CAS latency. The precharge to bank n will begin
when the READ to bank m is registered (Figure 27,
READ With Auto Precharge Interrupted by a READ).
2. Interrupted by a WRITE (with or without auto
precharge): When a WRITE to bank m registers, a
READ on bank n will be interrupted. DQM should
be used two clocks prior to the WRITE command to
prevent bus contention. The precharge to bank n
will begin when the WRITE to bank m is registered
(Figure 28, READ With Auto Precharge Interrupted
by a WRITE).
Micron SDRAM devices support Concurrent Auto
precharge, which allows an access command (READ or
WRITE) to another bank while an access command
with auto precharge enabled is executing. Four cases
where concurrent auto precharge occurs are defined
below.
READ with Auto Precharge
1. Interrupted by a READ (with or without auto
precharge): A READ to bank m will interrupt a READ
on bank n, two or three clocks later, depending on
Figure 27: READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
NOP
Page Active
READ - AP
BANK m
NOP
READ with Burst of 4
NOP
NOP
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK m
t RP - BANK n
Page Active
BANK m
BANK n,
COL a
ADDRESS
Precharge
READ with Burst of 4
BANK m,
COL d
DOUT
a+1
DOUT
a
DQ
DOUT
d
DOUT
d+1
CAS Latency = 3 (BANK n)
CAS Latency = 3 (BANK m)
DON’T CARE
NOTE:
DQM is LOW.
Figure 28: READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
READ - AP
BANK n
Page
Active
NOP
NOP
NOP
READ with Burst of 4
WRITE - AP
BANK m
NOP
NOP
Interrupt Burst, Precharge
Idle
tRP - BANK n
Page Active
BANK m
ADDRESS
NOP
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
BANK m,
COL d
1
DQM
DOUT
a
DQ
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
CAS Latency = 3 (BANK n)
DON’T CARE
NOTE:
DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4.
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©2003 Micron Technology, Inc. All rights reserved.
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MOBILE SDRAM
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto
precharge): When a READ to bank m registers, it will
interrupt a WRITE on bank n, with the data-out
appearing 2 or 3 clocks later, (depending on CAS
latency). The precharge to bank n will begin after
tWR is met, where tWR begins when the READ to
bank m is registered. The last valid WRITE to bank n
will be data-in registered one clock prior to the
READ to bank m (Figure 29, WRITE With Auto Precharge Interrupted by a READ).
4. Interrupted by a WRITE (with or without auto
precharge): When a WRITE to bank m registers, it
will interrupt a WRITE on bank n. The precharge to
bank n will begin after tWR is met, where tWR begins
when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered
one clock prior to a WRITE to bank m (Figure 30,
WRITE With Auto Precharge Interrupted by a
WRITE).
Figure 29: WRITE With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
Internal
States
NOP
WRITE - AP
BANK n
Page Active
READ - AP
BANK m
NOP
WRITE with Burst of 4
Page Active
BANK m
DIN
a
DQ
NOP
NOP
Interrupt Burst, Write-Back
Precharge
tWR - BANK n
tRP - BANK n
NOP
tRP - BANK m
READ with Burst of 4
BANK n,
COL a
ADDRESS
NOP
BANK m,
COL d
DOUT
d+1
DOUT
d
DIN
a+1
CAS Latency = 3 (BANK m)
DON’T CARE
NOTE:
DQM is LOW.
Figure 30: WRITE With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
COMMAND
BANK n
NOP
WRITE - AP
BANK n
Page Active
NOP
NOP
WRITE with Burst of 4
WRITE - AP
BANK m
NOP
Interrupt Burst, Write-Back
Internal
States
tWR - BANK n
BANK m
ADDRESS
DQ
Page Active
NOP
Precharge
tRP - BANK n
t WR - BANK m
Write-Back
WRITE with Burst of 4
BANK n,
COL a
DIN
a
NOP
BANK m,
COL d
DIN
a+1
DIN
a+2
DIN
d
DIN
d+1
DIN
d+2
DIN
d+3
DON’T CARE
NOTE:
DQM is LOW.
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MOBILE SDRAM
Table 7:
Truth Table 2 – CKE
Notes: 1-4: Notes appear below table
CKEn-1
L
CKEn
L
L
H
H
L
H
H
CURRENT STATE
COMMANDn
ACTIONn
Power-Down
Self Refresh
Clock Suspend
Deep Power-Down
Power-Down
Deep Power-Down
Self Refresh
Clock Suspend
All Banks Idle
All Banks Idle
All Banks Idle
Reading or Writing
X
X
X
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
X
COMMAND INHIBIT or NOP
BURST TERMINATE
AUTO REFRESH
VALID
See Truth Table 3
Maintain Power-Down
Maintain Self Refresh
Maintain Clock Suspend
Maintain Deep Power-Down
Exit Power-Down
Exit Deep Power-Down
Exit Self Refresh
Exit Clock Suspend
Power-Down Entry
Deep Power-Down Entry
Self Refresh Entry
Clock Suspend Entry
NOTES
8
5
8
6
7
8
NOTE:
1.
2.
3.
4.
5.
CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.
Current state is the state of the SDRAM immediately prior to clock edge n.
COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn.
All states and sequences not shown are illegal or reserved.
Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or
NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
edge n + 1.
8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is BURST TERMINATE when
CKE is high and DEEP POWER DOWN when CKE is low.
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MOBILE SDRAM
Table 8:
Truth Table 3 – Current State Bank n, Command to Bank n
Notes: 1-6; notes appear below table
CURRENT
STATE
Any
Idle
Row Active
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
CS#
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS# CAS#
X
H
L
L
L
L
H
H
L
H
H
L
H
H
H
L
H
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
WE#
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
NOTES
7
7
11
10
10
8
10
10
8
9
10
10
8
9
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was
self refresh).
2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other
bank are determined by its current state and Truth Table 3, and according to Truth Table 4.
Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in
the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be
in the row active state.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP
has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when
t
RP has been met. Once tRP is met, the bank will be in the idle state.
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on
each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will
be in the all banks idle state.
Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met.
Once tMRD is met, the SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks
will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Deep Power-Down is power savings feature of this Mobile SDRAM device. This command is BURST TERMINATE when CKE is high and
DEEP POWER DOWN when CKE is low.
10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs
with auto precharge disabled.
11. Does not affect the state of the bank and acts as a NOP to that bank.
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Table 9:
Truth Table 4 – Current State Bank n, Command to Bank m
Notes: 1-6; notes appear below and on next page
CURRENT
STATE
Any
Idle
Row
Activating,
Active, or
Precharging
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
Read
(With Auto
Precharge)
Write
(With Auto
Precharge)
CS#
H
L
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS CAS
#
#
WE# COMMAND (ACTION)
X
H
X
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
X
H
X
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
X
H
X
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
NOTES
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE
ACTIVE (Select and activate row)
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE
7
7
7, 10
7, 11
9
7, 12
7, 13
9
7, 8, 14
7, 8, 15
9
7, 8, 16
7, 8, 17
9
NOTE:
1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been
terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been
terminated.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and
ends when tRP has been met. Once tRP is met, the bank will be in the idle state.
4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current
state only.
6. All states and sequences not shown are illegal or reserved.
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7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge
enabled and READs or WRITEs with auto precharge disabled.
8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted
by bank m’s burst.
9. Burst in bank n continues as initiated.
10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 10, Consecutive READ Bursts, on page 17).
11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figure 12, READ to WRITE, on page 18, and Figure 13, READ to WRITE
with Extra Clock Cycle, on page 18). DQM should be used one clock prior to the WRITE command to prevent bus contention.
12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered (Figure 20, WRITE to READ, on page 21), with the data-out appearing
CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.
13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m
will interrupt the WRITE on bank n when registered (Figure 18, WRITE to WRITE, on page 20). The last valid WRITE to
bank n will be data-in registered one clock prior to the READ to bank m.
14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the READ on bank n, CAS latency later (Figure 27, READ With Auto Precharge Interrupted by a READ, on
page 24). The PRECHARGE to bank n will begin when the READ to bank m is registered.
15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the READ on bank n when registered (Figure 28, READ With Auto Precharge Interrupted by a WRITE, on
page 24). DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to
bank n will begin when the WRITE to bank m is registered.
16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will
interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later (Figure 29, WRITE With
Auto Precharge Interrupted by a READ, on page 25). The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to
the READ to bank m.
17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will
interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR
begins when the WRITE to bank m is registered (Figure 30, WRITE With Auto Precharge Interrupted by a WRITE, on
page 25). The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m.
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Absolute Maximum Ratings
Voltage on VDD/VDDQ Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . -0.35V to +2.8V
Voltage on Inputs, NC or I/O Pins
Relative to VSS . . . . . . . . . . . . . . . . . . . -0.35V to +2.8V
Operating Temperature
TA (Extended) . . . . . . . . . . . . . . . . . . . .-25°C to +85°C
TA (Industrial) . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Storage Temperature (plastic) . . . . .-55°C to +150°C
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 34; VDD = VDDQ = +1.8V ±0.1V
PARAMETER/CONDITION
SYMBOL
Supply Voltage
I/O Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Output High Voltage: All inputs
Output Low Voltage: All inputs
Input Leakage Current:
Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V)
Output Leakage Current: DQ disabled; 0V ≤ VOUT ≤ VDDQ
VDD
VDDQ
VIH
VIL
VOH
VOL
II
IOZ
MIN
MAX
1.7
1.9
1.7
1.9
0.8 x VDDQ VDD +0.3
-0.3
+0.3
0.9 x VDDQ
–
–
0.2
-1.0
1.0
-1.5
1.5
UNITS
V
V
V
V
V
V
µA
NOTES
22
22
µA
Table 11: AC Electrical Characteristics and Operating Conditions
VDD = 1.7V - 1.9V; VDDQ = 1.7V - 1.9V
PARAMETER/CONDITION
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
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SYMBOL
MIN
MAX
UNITS
VIH
VIL
1.4
-
+0.4
V
V
NOTES
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Table 12: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11; notes appear on page 34
AC CHARACTERISTICS
-8
PARAMETER
Access time from CLK (pos. edge)
SYMBOL
CL = 3
t
CL = 2
tAC
MIN
AC (3)
(2)
-10
MAX
MIN
MAX
UNITS
NOTES
6
7
ns
27
8
8
ns
Address hold time
tAH
1
1
ns
Address setup time
tAS
2.5
2.5
ns
CLK high-level width
t
CH
3
3
ns
CLK low-level width
t
3
3
ns
Clock cycle time
CL
CL = 3
tCK
CL = 2
tCK
(3)
8
100
9.6
100
ns
23
(2)
9.6
100
12
100
ns
23
CKE hold time
tCKH
1
1
ns
CKE setup time
tCKS
1.5
2.5
ns
CS#, RAS#, CAS#, WE#, DQM hold time
tCMH
1
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
tCMS
1.5
2.5
ns
Data-in hold time
tDH
1
1
ns
Data-in setup time
tDS
2.5
Data-out high-impedance time
CL = 3
tHZ
CL = 2
tHZ
2.5
ns
(3)
7
7
ns
10
(2)
8
8
ns
10
tLZ
1
1
ns
tOH
Data-out low-impedance time
2.5
2.5
ns
Data-out hold time (no load)
tOH
N
1.8
1.8
ns
ACTIVE to PRECHARGE command
tRAS
48
tRC
80
100
ns
ACTIVE to READ or WRITE delay
tRCD
19
20
ns
Refresh period (4,096 rows)
t
AUTO REFRESH period
tRFC
80
100
ns
tRP
19
20
ns
RRD
16
20
ns
Data-out hold time (load)
ACTIVE to ACTIVE command period
ACTIVE bank a to ACTIVE bank b command
t
0.5
WR (a)
WR (m)
1 CLK
+7ns
15
1 CLK
+5ns
15
tXSR
80
100
t
t
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1.2
120,000
64
T
t
Transition time
Exit SELF REFRESH to ACTIVE command
50
64
REF
PRECHARGE command period
WRITE recovery time
120,000
0.3
1.2
28
ns
ms
ns
7
–
24
ns
25
ns
20
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Table 13: AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11; notes appear on page 34
PARAMETER
SYMBOL
-8
-10
CCD
1
1
t
17
CKED
1
1
t
14
CKE to clock enable or power-down exit setup mode
t
PED
1
1
t
14
DQM to input data delay
t
DQD
0
0
t
17
DQM to data mask during WRITEs
t
DQM
0
0
t
17
DQM to data high-impedance during READs
t
DQZ
2
2
t
CK
17
WRITE command to input data delay
tDWD
0
0
tCK
17
Data-in to ACTIVE command
tDAL
5
5
tCK
15, 21
Data-in to PRECHARGE command
tDPL
2
2
tCK
16, 21
Last data-in to burst STOP command
tBDL
1
1
tCK
17
Last data-in to new READ/WRITE command
tCDL
1
1
tCK
17
Last data-in to PRECHARGE command
tRDL
2
2
tCK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH
command
Data-out to high-impedance from PRECHARGE command
tMRD
2
2
tCK
26
CL = 3
tROH(3)
3
3
tCK
17
CL = 2
tROH(2)
2
2
tCK
17
t
READ/WRITE command to READ/WRITE command
CKE to clock disable or power-down entry mode
t
UNITS
CK
CK
CK
CK
CK
NOTES
Table 14: IDD Specifications and Conditions
Notes: 1, 5, 6, 11, 13, 32; notes appear on page 34; VDD = VDDQ = +1.8V ±0.1V
MAX
PARAMETER/CONDITION
Operating Current: Active Mode;
Burst = 2; READ or WRITE; tRC = tRC (MIN)
Standby Current: Power-Down Mode; All banks idle; CKE = LOW
Standby Current: Active Mode;
CKE = HIGH; CS# = HIGH; All banks active after tRCD met;
No accesses in progress
Operating Current: Burst Mode; Continuous burst;
READ or WRITE; All banks active
tRC = tRFC (MIN)
Auto Refresh Current
CKE = HIGH; CS# = HIGH
t
RFC = 15.625µs
DEEP POWER DOWN
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SYMBOL
IDD1
-8
50
-10
50
UNITS
mA
NOTES
3, 18,
19
IDD2
IDD3
150
35
150
30
µA
mA
32
3, 12,
19
IDD4
50
50
mA
IDD5
60
50
mA
IDD6
2
2
mA
IZZ
10
10
µA
3, 18,
19
3, 12,
18, 19,
33
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Table 15: IDD7 - Self Refresh Current Options
Notes: 4; notes appear on page 34; VDD = VDDQ = +1.8V ±0.1V
TEMPERATURE COMPENSATED SELF REFRESH
PARAMETER/CONDITION
MAX
TEMPERATURE
-8 & -10
UNITS
NOTES
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
85ºC
70ºC
45ºC
15ºC
160
130
110
100
130
100
90
80
110
80
70
65
105
75
65
65
100
75
65
65
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Self Refresh Current:
CKE < 0.2V – 4 Banks Open
Self Refresh Current:
CKE < 0.2V – 2 Banks Open
Self Refresh Current:
CKE < 0.2V – 1 Bank Open
Self Refresh Current:
CKE < 0.2V – 1/2 Bank Open
Self Refresh Current:
CKE < 0.2V – 1/4 Bank Open
Table 16: Capacitance
Note: 2; notes appear following on page 34
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
CI1
CI2
CIO
1.5
1.5
3.0
4.0
4.0
6.0
pF
pF
pF
29
30
31
Input Capacitance: CLK
Input Capacitance: All other input-only pins
Input/Output Capacitance: DQ
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Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. VDD, VDDQ = +1.8V; TA
= 25°C; pin under test biased at 1.4V. f = 1 MHz.
3. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range (-25°C ≤ TA ≤
+85°C for standard parts; -40°C ≤ TA ≤ +85°C for IT
parts) is ensured.
6. An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (VDD
and VDDQ must be powered up simultaneously.
VSS and VSSQ must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
7. AC characteristics assume tT = 1ns.
8. In addition to meeting the transition rate specification, the clock and CKE must transit between
VIH and VIL (or between VIL and VIH) in a monotonic manner.
9. Outputs measured for 1.8V at 0.9V with equivalent
load:
14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate.
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.
18. The IDD current will increase or decrease proportionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on tCK = 8ns for -8 and tCK = 9.6ns for -10.
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins at 7ns for -8 after the first
clock delay, after the last WRITE is executed. May
not exceed limit set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -8 at CL = 3 with no load is 7ns and is guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -8, CL = 2, tCK = 9.6ns. For -10, CL = 3 and tCK
= 9.6ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a
fail value.
34. Deep power down current is a nominal value at
25°C. The parameter is not tested.
Q
30pF
10. tHZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data element will meet
tOH before going High-Z.
11. AC timing and IDD tests have VIL and VIH, with
timing referenced to VIH/2 = crossover point. If
the input transition time is longer than tT (MAX),
then the timing is referenced at VIL (MAX) and VIH
(MIN) and no longer at the VIH/2 crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are otherwise at valid VIH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
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Figure 31: Initialize and Load Mode Register1
T0
T1
T3
T5
T7
T9
CLK
((
))
((
))
CKE
((
))
((
))
COMMAND3
((
))
((
))
DQML, DQMU
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
A10
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tRP
tMRD
tMRD
tRP
T19
T29
((
))
((
tCK ) )
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tCKS tCKH
tCMS tCMH
NOP
((
))
((
))
PRE
AR
((
))
((
))
((
))
((
))
AR
LMR
((
))
((
))
LMR
((
))
((
))
((
))
((
))
PRE2
((
))
((
))
ACT
((
))
((
))
((
))
((
))
CODE
((
))
((
))
((
))
((
))
RA
CODE
((
))
((
))
((
))
((
))
RA
((
))
((
))
((
))
((
))
RA
((
))
((
))
tAS tAH
BA0, BA1
((
))
((
))
DQ
((
))
ALL BANKS
t AS tAH
t AS tAH
tAS tAH
High-Z
BA0 = L,
BA1 = H
ALL BANKS
((
))
((
))
BA0
BA0 == L,
L,
BA1
BA1==HL
T = 100µs
Power-up:
VDD and
CLK stable
Load Extended
Mode Register
tRFC
tRFC
Load Mode
Register
DON’T CARE
NOTE:
1. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE
command, RA = Row Address, BA = Bank Address
2. Optional refresh command.
3. Device timing is -10 with 104 MHz clock.
-8
SYMBOL1
MIN
tAH
1
tAS
-10
MAX
MIN
-8
MAX
-10
UNITS
SYMBOL
MIN
1
ns
tCKH
MAX
MIN
MAX
UNITS
1
1
ns
tCKS
2.5
2.5
ns
ns
2.5
2.5
ns
t
CH
3
3
ns
t
1
1
t
3
CMS
2.5
2.5
MRD
2
2
RFC
80
100
CK
ns
t
19
20
ns
CMH
CL
3
ns
t
t
CK (3)
8
100
9.6
100
ns
t
t
9.6
100
12
100
ns
CK (2)
t
RP
ns
t
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
35
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©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 32: Power-Down Mode1
T0
T1
T2
tCK
CLK
tCH
tCKS
CKE
tCKS
Tn + 2
tCKS
((
))
tCKH
tCMS tCMH
COMMAND
Tn + 1
((
))
((
))
tCL
PRECHARGE
NOP
((
))
((
))
NOP
NOP
ACTIVE
DQML, DQMU
((
))
((
))
A0-A9, A11
((
))
((
))
ROW
((
))
((
))
ROW
((
))
((
))
BANK
ALL BANKS
A10
SINGLE BANK
tAS
BA0, BA1
tAH
BANK(S)
High-Z
((
))
DQ
Two clock cycles
Input buffers gated off while in
power-down mode
Precharge all
active banks
All banks idle
All banks idle, enter
power-down mode
Exit power-down mode
DON’T CARE
NOTE:
1. Violating refresh requirements during power-down may result in a loss of data.
-8
SYMBOL1
MIN
tAH
1
tAS
2.5
t
CH
t
-10
MAX
MIN
-8
MAX
UNITS
SYMBOL
1
ns
tCKH
1
1
ns
2.5
ns
tCKS
2.5
2.5
ns
3
3
ns
t
1
1
ns
3
CMS
2.5
2.5
MRD
2
2
RFC
80
100
CK
ns
t
19
20
ns
CMH
CL
3
ns
t
t
CK (3)
8
100
9.6
100
ns
t
t
9.6
100
12
100
ns
CK (2)
t
RP
MIN
-10
MAX
MIN
MAX
UNITS
ns
t
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 33: Clock Suspend Mode
T0
T1
T2
tCK
CLK
T3
T4
T5
T6
T7
T8
T9
tCL
tCH
tCKS tCKH
CKE
tCKS
tCKH
tCMS tCMH
COMMAND
READ
NOP
NOP
NOP
NOP
NOP
WRITE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2
tAS
COLUMN e 2
tAH
A10
tAH
tAS
BA0, BA1
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tLZ
tHZ
tDS
DOUT m + 1
tDH
DOUT e
DOUT e + 1
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
MIN
-10
MAX
MIN
-8
-10
MAX
UNITS
SYMBOL
MIN
MAX
MIN
MAX UNITS
tCKS
2.5
2.5
ns
(3)
7
7
ns
AC (2)
8
8
ns
t
CMH
1
1
ns
1
ns
tCMS
2.5
2.5
ns
tDH
1
1
ns
tDS
2.5
2.5
ns
tAC
t
tAH
1
tAS
2.5
2.5
ns
tCH
3
3
ns
tCL
3
3
tCK
tCK
ns
tHZ
(3)
tHZ
(2)
7
7
(3)
8
100
9.6
100
ns
(2)
9.6
100
12
100
ns
tLZ
1
1
ns
ns
tOH
2.5
2.5
ns
tCKH
1
1
7
8
ns
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 34: Auto Refresh Mode
T0
CLK
T1
T2
tCK
((
))
((
))
tCH
tCKS
tCKH
tCMS
tCMH
PRECHARGE
AUTO
REFRESH
NOP
NOP
A0-A9, A11
ALL BANKS
A10
SINGLE BANK
tAS
DQ
((
))
AUTO
REFRESH
NOP
((
))
((
))
DQMU, DQML
BA0, BA1
((
))
( ( NOP
))
To + 1
((
))
((
))
((
))
CKE
COMMAND
Tn + 1
tCL
((
))
( ( NOP
))
ACTIVE
((
))
((
))
((
))
((
))
((
))
((
))
ROW
((
))
((
))
((
))
((
))
ROW
tAH
((
))
((
))
BANK(S)
High-Z
((
))
((
))
((
))
tRP
BANK
((
))
tRFC1
tRFC1
Precharge all
active banks
DON’T CARE
NOTE:
1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
-8
SYMBOL1
MIN
tAH
1
tAS
tCH
tCL
tCK
tCK
-10
MAX
MIN
-8
MAX
-10
UNITS
SYMBOL
MIN
1
ns
tCKH
MAX
MIN
MAX
UNITS
1
1
ns
2.5
2.5
ns
tCKS
2.5
2.5
ns
3
3
ns
tCMH
1
1
ns
3
3
ns
tCMS
2.5
2.5
ns
(3)
8
100
9.6
100
ns
tMRD
2
2
tCK
(2)
9.6
100
12
100
ns
tRFC
80
100
ns
tRP
19
20
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 35: Self Refresh Mode
T0
CLK
T1
tCK
tCL
tCH
T2
tCKS
CKE
tCKS
tCKH
tCMS
tCMH
COMMAND
PRECHARGE
Tn + 1
((
))
((
))
((
))
((
))
> tRAS
AUTO
REFRESH
((
))
((
))
((
))
))
((
))
((
))
((
))
((
))
A0-A9, A11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
ALL BANKS
SINGLE BANK
tAS
BA0, BA1
DQ
AUTO
REFRESH
NOP ( (
DQMU, DQML
A10
To + 2
((
))
((
))
((
))
NOP
To + 1
tAH
BANK(S)
High-Z
((
))
((
))
tRP
Precharge all
active banks
tXSR
Enter self refresh mode
Exit self refresh mode
(Restart refresh time base)
CLK stable prior to exiting
self refresh mode
DON’T CARE
NOTE:
1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.
-8
SYMBOL1
MIN
tAH
1
tAS
-10
MAX
MIN
-8
MAX UNITS
SYMBOL
MIN
-10
MAX
MIN
MAX
UNITS
1
ns
tCKH
1
1
ns
2.5
2.5
ns
tCKS
2.5
2.5
ns
tCH
3
3
ns
tCMH
1
1
ns
t
3
3
ns
t
CMS
2.5
2.5
ns
tCK
(3)
8
100
9.6
100
ns
tRAS
48
(2)
9.6
100
12
100
ns
tRP
19
20
ns
80
100
ns
CL
tCK
t
XSR
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 36: READ – Without Auto Precharge1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
NOP
PRECHARGE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m2
ROW
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
ROW
SINGLE BANKS
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
BANK(S)
tAC
tAC
DQ
tLZ
tRCD
BANK
tAC
tAC
tOH
tOH
tOH
tOH
DOUT m
DOUT m+1
DOUT m+2
DOUT m+3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
tAC
tAC
MIN
-10
MAX
MIN
-8
MAX UNITS
-10
SYMBOL
MIN
(3)
7
7
ns
tCMH
1
MAX
MIN
1
MAX
UNITS
ns
(2)
8
8
ns
tCMS
2.5
2.5
ns
tAH
1
1
ns
tHZ
(3)
7
7
ns
tAS
2.5
2.5
ns
tHZ
(2)
8
8
ns
t
CH
3
3
ns
t
t
3
ns
t
t
CL
3
t
CK (3)
8
100
9.6
100
ns
t
9.6
100
12
100
ns
CK (2)
t
CKH
t
CKS
1
1
ns
2.5
2.5
ns
LZ
1
1
ns
OH
2.5
2.5
ns
RAS
48
t
RC
80
100
ns
RCD
19
20
ns
t
19
20
ns
t
RP
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 37: READ – With Auto Precharge1
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
ACTIVE
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
tAH
BANK
BANK
BANK
tAC
tOH
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
DOUT m + 1
tAC
tOH
tOH
DOUT m + 2
DOUT m + 3
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
tAC
tAC
t
MAX
MIN
-8
-10
MAX
UNITS
SYMBOL
MIN
(3)
7
7
ns
tCMH
1
1
ns
(2)
8
8
ns
tCMS
2.5
2.5
ns
MAX
MIN
MAX
UNITS
1
1
ns
tHZ
t
AS
2.5
2.5
ns
t
t
CH
3
3
ns
t
LZ
1
1
ns
t
CL
3
3
ns
t
OH
3
3
ns
CK (3)
8
100
9.6
100
ns
t
RAS
48
CK (2)
9.6
100
12
100
ns
t
RC
80
100
ns
RCD
19
20
ns
tRP
19
20
ns
tAH
t
MIN
-10
CKH
1
1
ns
tCKS
1.5
2.5
ns
t
(3)
7
7
ns
HZ (2)
8
8
ns
t
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
41
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 38: Single READ – Without Auto Precharge1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP 3
NOP 3
T6
T7
T8
tCL
tCH
tCKS
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP
READ
PRECHARGE
ACTIVE
NOP
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
COLUMN m2
ROW
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANKS
BANK
tAC
DQ
tLZ
tRCD
BANK
BANK(S)
tOH
DOUT m
tHZ
tRP
CAS Latency
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
-8
SYMBOL1
tAC
tAC
-10
-8
MIN MAX MIN MAX
UNITS
SYMBOL
MIN
1
2.5
(3)
7
7
ns
tCMH
(2)
8
8
ns
tCMS
-10
MAX
MIN
MAX
1
UNITS
ns
2.5
ns
tAH
1
1
ns
tHZ
tAS
2.5
2.5
ns
tHZ
tCH
3
3
ns
tLZ
1
1
ns
tCL
3
3
ns
tOH
3
3
ns
t
CK (3)
8
100
9.6
100
ns
t
t
9.6
100
12
100
ns
CK (2)
t
1
1
ns
t
2.5
2.5
ns
CKH
CKS
(3)
7
7
ns
(2)
8
8
ns
RAS
48
t
RC
80
66
ns
RCD
19
20
ns
t
19
20
ns
t
RP
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
42
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 39: Single READ – With Auto Precharge1
T0
T1
T2
tCK
CLK
tCKS
T3
T4
T5
T6
T7
T8
tCL
tCH
tCKH
CKE
tCMS tCMH
COMMAND
ACTIVE
NOP3
NOP
NOP3
READ
tCMS
NOP
NOP
ACTIVE
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m2
ROW
tAS
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
ROW
tAH
BANK
BANK
BANK
tAC
t OH
DOUT m
DQ
tRCD
CAS Latency
tHZ
tRP
tRAS
tRC
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.
2. A9 and A11 = “Don’t Care.”
3. PRECHARGE command not allowed or tRAS would be violated.
-8
SYMBOL1
tAC
tAC
MIN
-10
MAX
MIN
-8
-10
MAX
UNITS
SYMBOL
MIN
(3)
7
7
ns
tCMH
1
MAX
MIN
1
MAX
UNITS
ns
(2)
8
8
ns
tCMS
2.5
2.5
ns
tAH
1
1
ns
tHZ
(3)
7
7
ns
tAS
2.5
2.5
ns
tHZ
(2)
8
8
ns
tCH
3
3
ns
tLZ
1
1
ns
tCL
3
3
ns
tOH
3
3
ns
t
CK (3)
8
100
9.6
100
ns
t
t
9.6
100
12
100
ns
CK (2)
t
CKH
t
CKS
1
1
ns
2.5
2.5
ns
t
RAS
48
t
RC
80
66
ns
RCD
19
20
ns
t
19
20
ns
RP
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 40: Alternating Bank Read Accesses1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
ACTIVE
T6
T7
T8
READ
NOP
ACTIVE
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ENABLE AUTO PRECHARGE
tAS
BA0, BA1
ROW
ENABLE AUTO PRECHARGE
ROW
A10
COLUMN b 2
ROW
ROW
ROW
tAH
BANK 0
BANK 0
BANK 3
tAC
DQ
tLZ
tRCD - BANK 0
BANK 3
tAC
tOH
DOUT m
tAC
tOH
BANK 0
tAC
tOH
DOUT m + 1
DOUT m + 2
tAC
tOH
DOUT m + 3
tRP - BANK 0
CAS Latency - BANK 0
tAC
tOH
DOUT b
tRCD - BANK 0
tRAS - BANK 0
tRC - BANK 0
tRCD - BANK 3
tRRD
CAS Latency - BANK 3
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the burst length = 4, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
MAX
MIN
-8
MAX
UNITS
SYMBOL
(3)
7
7
ns
tCMH
AC (2)
8
8
ns
t
tAC
t
MIN
-10
CMS
MIN
-10
MAX
MIN
MAX
UNITS
1
1
ns
2.5
2.5
ns
tAH
1
1
ns
tHZ
(3)
7
7
ns
tAS
2.5
2.5
ns
tHZ
(2)
8
8
ns
tCH
3
3
ns
tLZ
1
1
ns
tCL
3
3
ns
tOH
3
3
ns
48
tCK
tCK
(3)
8
100
9.6
100
ns
tRAS
(2)
9.6
100
12
100
ns
tRC
80
120,000
50
66
120,000
ns
ns
tCKH
1
1
ns
tRCD
19
20
ns
tCKS
2.5
2.5
ns
tRP
19
20
ns
tRRD
16
20
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
44
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 41: READ – Full-page Burst1
T0
T1
T2
tCL
CLK
T3
T4
T5
T6
((
))
((
))
tCK
tCH
tCKS
Tn + 1
Tn + 2
Tn + 3
Tn + 4
tCKH
((
))
((
))
CKE
tCMS
COMMAND
tCMH
ACTIVE
NOP
READ
tCMS
NOP
NOP
NOP
NOP
tCMH
tAS
tAH
tAS
tAH
tAS
BA0, BA1
NOP
NOP
((
))
((
))
ROW
A10
BURST TERM
((
))
((
))
COLUMN m 2
ROW
NOP
((
))
((
))
DQMU, DQML
A0-A9, A11
((
))
((
))
tAH
BANK
((
))
((
))
BANK
tAC
tAC
tOH
DOUT m
DQ
tAC
tAC ( (
tOH ) )
tOH
DOUT m+1
DOUT
tLZ
tRCD
CAS Latency
tAC
((
))
m+2
((
))
tAC
tOH
tOH
tOH
DOUT m-1
DOUT m
DOUT m+1
tHZ
256 (x16) locations within same row
Full page completed
DON’T CARE
Full-page burst does not self-terminate.
3
Can use BURST TERMINATE command.
UNDEFINED
NOTE:
1. For this example, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
3. Page left open; no tRP.
-8
SYMBOL1
tAC
tAC
t
MAX
MIN
-8
MAX UNITS
-10
SYMBOL
MIN
(3)
7
7
ns
tCMH
1
MAX
MIN
1
MAX
UNITS
ns
(2)
8
8
ns
tCMS
2.5
2.5
ns
AH
1
1
ns
t
tAS
2.5
2.5
ns
tHZ
tCH
3
3
ns
tLZ
1
1
ns
t
CL
3
3
ns
t
3
3
ns
CK (3)
8
100
9.6
100
ns
t
CK (2)
9.6
100
12
100
ns
tCKH
1
1
ns
tCKS
2.5
2.5
ns
t
t
MIN
-10
HZ (3)
(2)
OH
7
7
ns
8
8
ns
RAS
48
t
RC
80
66
ns
tRCD
19
20
ns
tRP
19
20
ns
RRD
16
20
ns
t
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
45
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 42: READ – DQM Operation1
T0
T1
T2
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T3
T4
T5
NOP
NOP
T6
T7
T8
NOP
NOP
NOP
tCL
tCH
CKE
COMMAND
ACTIVE
NOP
READ
tCMS
NOP
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
tAS
A10
tAH
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
BANK
tAC
DQ
DOUT m
tLZ
tRCD
tAC
tOH
tAC
tOH
tOH
DOUT m + 2
tLZ
tHZ
DOUT m + 3
tHZ
CAS Latency
DON’T CARE
UNDEFINED
NOTE:
1. For this example, the CAS latency = 2.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
MIN
-10
MAX
MIN
-8
MAX
UNITS
SYMBOL
MIN
-10
MAX
MIN
MAX
UNITS
tAC
(3)
7
7
ns
tCMH
1
1
ns
tAC
(2)
8
8
ns
tCMS
2.5
2.5
ns
tAH
1
1
ns
tHZ
(3)
7
7
ns
tAS
2.5
2.5
ns
tHZ
(2)
8
8
ns
tCH
3
3
ns
tLZ
1
1
ns
t
3
3
ns
t
OH
2.5
2.5
ns
tCK
(3)
8
100
9.6
100
ns
tRAS
48
tCK
(2)
9.6
100
12
100
ns
tRC
80
66
ns
RCD
19
20
ns
t
RP
19
20
ns
RRD
16
20
ns
CL
t
1
1
ns
t
2.5
2.5
ns
CKH
CKS
t
t
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 43: WRITE – Without Auto Precharge1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 3
ROW
tAS
ROW
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
ROW
DISABLE AUTO PRECHARGE
tAH
BANK
SINGLE BANK
BANK
tDS
tDH
DIN m
DQ
BANK
BANK
tDS
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
t WR 2
tRCD
tRAS
tRP
tRC
DON’T CARE
NOTE:
1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.
2. 15ns is required between and the PRECHARGE command, regardless of frequency.
3. A9 and A11 = “Don’t Care.”
-8
-10
SYMBOL1 MIN MAX
MAX UNITS
MIN
1
1
ns
2.5
2.5
ns
1
1
ns
7
7
ns
tCMH
AC (2)
8
8
ns
t
t
AH
CMS
1
1
ns
t
t
DH
MAX
MIN
MAX
AS
2.5
2.5
ns
DS
2.5
3
3
ns
tRAS
48
tCL
3
3
ns
tRC
80
100
ns
CK (3)
8
100
9.6
100
ns
RCD
19
20
ns
9.6
100
12
100
ns
tRP
19
20
ns
1 CLK
+7ns
15
1 CLK
+5ns
15
–
tCK
(2)
tCKH
1
1
tCKS
2.5
2.5
t
ns
tWR
(a)
ns
tWR
(m)
2.5
UNITS
tCH
t
t
-10
SYMBOL
(3)
tAC
t
MIN
-8
120,000
50
ns
120,000
ns
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
47
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 44: WRITE – With Auto Precharge1
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
NOP
NOP
ACTIVE
tCH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
ROW
tAH
BANK
BANK
tDS
tDH
BANK
tDS
DIN m
DQ
tDH
DIN m + 1
tDS
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
tRAS
tRP
tWR
tRC
DON’T CARE
NOTE:
1. For this example, the burst length = 4.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
tAC
tAC
-10
MIN MAX MIN
-8
MAX UNITS
SYMBOL
MIN
-10
MAX
MIN
MAX
UNITS
(3)
7
7
ns
tCMH
1
1
ns
(2)
8
8
ns
tCMS
2.5
2.5
ns
1
1
ns
t
AS
2.5
2.5
ns
t
tCH
3
3
ns
tRAS
48
tCL
3
3
ns
tRC
80
100
ns
tRCD
19
20
ns
tRP
19
20
ns
1 CLK
+7ns
15
1 CLK
+5ns
15
–
t
AH
t
tCK
(3)
8
100
9.6
100
ns
tCK
(2)
9.6
100
12
100
ns
tCKH
1
1
tCKS
2.5
2.5
1
1
ns
DS
2.5
2.5
ns
DH
ns
tWR
(a)
ns
tWR
(m)
120,000
50
120,000
ns
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
48
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 45: Single WRITE – Without Auto Precharge1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
NOP 4
NOP 4
T6
T7
T8
ACTIVE
NOP
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
PRECHARGE
NOP
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 3
ROW
tAS
tAH
ALL BANKS
ROW
A10
tAS
BA0, BA1
ROW
tAH
DISABLE AUTO PRECHARGE
SINGLE BANK
BANK
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
t WR 2
tRC
DON’T CARE
NOTE:
1.
2.
3.
4.
For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
15ns is required between and the PRECHARGE command, regardless of frequency.
A9 and A11 = “Don’t Care.”
PRECHARGE command not allowed else tRAS would be violated.
-8
SYMBOL1
MIN
-10
MAX
MIN
-8
MAX
UNITS
SYMBOL
MIN
1
1
ns
2.5
2.5
ns
1
ns
(3)
7
7
ns
tCMH
AC (2)
8
8
ns
t
tAC
t
-10
CMS
MAX
MIN
MAX
UNITS
AH
1
1
ns
t
DH
1
tAS
2.5
2.5
ns
tDS
2.5
tCH
3
3
ns
tRAS
48
tCL
3
3
ns
tRC
80
100
ns
tRCD
19
20
ns
tRP
19
20
ns
1 CLK
+7ns
15
1 CLK
+5ns
15
–
t
tCK
(3)
8
100
9.6
100
ns
tCK
(2)
9.6
100
12
100
ns
tCKH
1
1
tCKS
2.5
2.5
ns
tWR
(a)
ns
tWR
(m)
2.5
120,000
50
ns
120,000
ns
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
49
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 46: Single WRITE – With Auto Precharge1
T0
tCK
CLK
tCKS
tCKH
tCMS
tCMH
T1
T2
tCL
T3
T4
T5
T6
T7
NOP3
WRITE
NOP
NOP
NOP
T8
T9
tCH
CKE
COMMAND
NOP3
ACTIVE
NOP3
tCMS
NOP
ACTIVE
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
tAS
A10
tAH
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
COLUMN m 2
ROW
ROW
tAH
BANK
BANK
tDS
BANK
tDH
DIN m
DQ
tRCD
tRAS
tRP
tWR
tRC
DON’T CARE
NOTE:
1.
2.
3.
4.
For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.
15ns is required between and the PRECHARGE command, regardless of frequency.
A9 and A11 = “Don’t Care.”
WRITE command not allowed else tRAS would be violated.
-8
SYMBOL1
t
MIN
AC (3)
tAC
MAX
MIN
-8
MAX UNITS
SYMBOL
MIN
-10
MAX
MIN
MAX
UNITS
7
7
ns
t
CMH
1
1
ns
8
8
ns
tCMS
2.5
2.5
ns
tAH
1
1
ns
tDH
1
1
ns
tAS
2.5
2.5
ns
tDS
2.5
2.5
ns
tCH
3
3
ns
tRAS
48
tCL
3
3
ns
tRC
80
100
ns
tRCD
19
20
ns
19
20
ns
1 CLK
+7ns
15
1 CLK
+5ns
15
–
8
100
9.6
100
ns
CK (2)
9.6
100
12
100
ns
t
tCKH
1
1
ns
tWR
(a)
tCKS
2.5
2.5
ns
tWR
(m)
tCK
t
(2)
-10
(3)
RP
120,000
50
120,000
ns
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
50
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 47: Alternating Bank Write Accesses1
T0
tCK
CLK
T1
T2
tCL
T3
T4
T5
T6
T7
T8
T9
NOP
NOP
ACTIVE
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS
NOP
ACTIVE
NOP
WRITE
tCMH
DQMU, DQML
tAS
A0-A9, A11
tAS
A10
COLUMN m 2
tAH
COLUMN b 2
ROW
ENABLE AUTO PRECHARGE
ROW
ENABLE AUTO PRECHARGE
ROW
tAS
BA0, BA1
tAH
ROW
ROW
ROW
tAH
BANK 0
BANK 0
tDS
BANK 1
tDH
DIN m
DQ
tDS
tDH
DIN m + 1
tDS
BANK 1
tDH
tDS
DIN m + 2
tDH
tDS
DIN m + 3
DIN b
tWR - BANK 0
tRCD - BANK 0
BANK 0
tDH
tDS
tDH
tDS
DIN b + 1
tDH
DIN b + 2
tDS
tDH
DIN b + 3
tRCD - BANK 0
tRP - BANK 0
tRAS - BANK 0
tRC - BANK 0
tWR - BANK 1
tRCD - BANK 1
tRRD
DON’T CARE
NOTE:
1. For this example, the burst length = 4.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
MIN
-10
MAX
MIN
-8
MAX
UNITS
SYMBOL
(3)
7
7
ns
tCMH
AC (2)
8
8
ns
t
tAC
t
CMS
MIN
-10
MAX
MIN
MAX
UNITS
1
1
ns
2.5
2.5
ns
AH
1
1
ns
t
DH
1
1
ns
tAS
2.5
2.5
ns
tDS
2.5
2.5
ns
tCH
3
3
ns
tRAS
48
tCL
3
3
ns
tRC
80
100
ns
19
20
ns
19
20
ns
1 CLK
+7ns
15
1 CLK +5ns
–
15
ns
t
tCK
tCK
(3)
8
100
9.6
100
ns
tRCD
(2)
9.6
100
12
100
ns
tRP
tCKH
1
1
ns
tWR
(a)
tCKS
2.5
2.5
ns
tWR
(m)
120,000
50
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
51
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 48: WRITE – Full-page Burst1
T0
T1
T2
tCL
CLK
T3
T4
T5
((
))
((
))
tCK
tCH
tCKS
tCKH
tCMS
tCMH
ACTIVE
NOP
WRITE
NOP
NOP
tCMS tCMH
tAS
tAS
tAS
BA0, BA1
NOP
BURST TERM
NOP
((
))
((
))
COLUMN m 1
tAH
((
))
((
))
ROW
A10
Tn + 3
((
))
((
))
tAH
ROW
((
))
((
))
NOP
DQMU, DQML
A0-A9, A11
Tn + 2
((
))
((
))
CKE
COMMAND
Tn + 1
tAH
BANK
((
))
((
))
BANK
tDS
tDH
DIN m
DQ
tDS
tDH
tDS
DIN m + 1
tDH
tDS
DIN m + 2
tDH
((
))
DIN m + 3 ( (
tDS
tDH
DIN m - 1
))
tRCD
Full-page burst does not
self-terminate. Can use
BURST TERMINATE
command to stop.2, 3
256 (x16) locations within same row
Full page completed
DON’T CARE
NOTE:
1.
2.
3.
A9 and A11 = “Don’t Care.”
tWR must be satisfied prior to PRECHARGE command.
Page left open; no tRP.
-8
SYMBOL1
MIN
-10
MAX
MIN
-8E
MAX
UNITS
SYMBOL
MIN
MAX
-10
MIN
MAX
UNITS
tAC
(3)
7
7
ns
tCMH
1
1
ns
tAC
(2)
8
8
ns
tCMS
2.5
2.5
ns
1
1
ns
t
1
1
ns
t
t
AS
2.5
2.5
ns
t
t
CH
3
3
ns
t
CL
3
3
ns
CK (3)
8
100
9.6
100
ns
9.6
100
12
100
ns
AH
t
t
CK (2)
t
CKH
t
CKS
DH
DS
2.5
RAS
48
t
RC
80
100
ns
RCD
19
20
ns
t
RP
19
20
ns
WR (a)
1 CLK
+7ns
15
1 CLK +5ns
–
15
ns
t
t
1
1
ns
t
2.5
2.5
ns
t
WR (m)
2.5
120,000
50
ns
120,000
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
52
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 49: WRITE – DQM Operation1
T0
T1
T2
tCK
CLK
T3
T4
T5
NOP
NOP
NOP
T6
T7
NOP
NOP
tCL
tCH
tCKS
tCKH
tCMS
tCMH
CKE
COMMAND
ACTIVE
NOP
WRITE
tCMS tCMH
DQMU, DQML
tAS
A0-A9, A11
tAH
COLUMN m 2
ROW
tAS
tAH
ENABLE AUTO PRECHARGE
ROW
A10
tAS
BA0, BA1
tAH
DISABLE AUTO PRECHARGE
BANK
BANK
tDS
tDH
tDS
DIN m
DQ
tDH
DIN m + 2
tDS
tDH
DIN m + 3
tRCD
DON’T CARE
NOTE:
1. For this example, the burst length = 4.
2. A9 and A11 = “Don’t Care.”
-8
SYMBOL1
tAC
MIN
-10
MAX
MIN
-8
MAX
UNITS
SYMBOL
MIN
-10
MAX
MIN
MAX
UNITS
(3)
7
7
ns
tCMH
1
1
ns
(2)
8
8
2.5
2.5
ns
1
1
ns
DS
2.5
2.5
ns
RAS
48
ns
tCMS
1
1
ns
tDH
t
AS
2.5
2.5
ns
t
t
CH
3
3
ns
tCL
3
3
ns
tRC
80
100
ns
tAC
tAH
tCK
tCK
120,000
50
120,000
ns
(3)
8
100
9.6
100
ns
tRCD
19
20
ns
(2)
9.6
100
12
100
ns
tRP
19
20
ns
WR (a)
1 CLK
+7ns
15
1 CLK
+5ns
15
–
t
CKH
t
t
CKS
1
1
ns
t
2.5
2.5
ns
t
WR (m)
ns
NOTE:
1. CAS latency indicated in parentheses.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
53
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16
MOBILE SDRAM
Figure 50: 54-Ball FBGA (8mm x 8mm)
0.65 ±0.05
SEATING PLANE
C
0.10 C
SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2% Ag
SOLDER MASK DEFINED BALL PADS: Ø0.40
SUBSTRATE MATERIAL: PLASTIC LAMINATE
MOLD COMPOUND: EPOXY NOVOLAC
6.40
54X Ø0.45 ±0.05
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-REFLOW
DIAMETER IS 0.42.
0.80
TYP
BALL A1 ID
BALL A1 ID
BALL A1
4.00 ±0.05
BALL A9
6.40
CL
8.00 ±0.10
3.20 ±0.05
0.80 TYP
CL
3.20 ±0.05
4.00 ±0.05
1.00 MAX
8.00 ±0.10
NOTE:
1. All dimensions are in millimeters.
Data Sheet Designation
Production: This data sheet contains minimum and
maximum limits specified over the complete power
supply and temperature range for production devices.
Although considered final, these specifications are
subject to change, as further product development and
data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
54
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
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