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MT48LC128M4A2TG-7E:C

MT48LC128M4A2TG-7E:C

  • 厂商:

    MICRON(镁光)

  • 封装:

    TSOP54

  • 描述:

    IC DRAM 512MBIT PAR 54TSOP II

  • 详情介绍
  • 数据手册
  • 价格&库存
MT48LC128M4A2TG-7E:C 数据手册
512Mb: x4, x8, x16 SDRAM Features SDR SDRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks Features Options Marking • Configurations – 128 Meg x 4 (32 Meg x 4 x 4 banks) – 64 Meg x 8 (16 Meg x 8 x 4 banks) – 32 Meg x 16 (8 Meg x 16 x 4 banks) • Write recovery (tWR) – tWR = 2 CLK1 • Plastic package – OCPL2 – 54-pin TSOP II (400 mil) (standard) – 54-pin TSOP II (400 mil) Pb-free • Timing – cycle time – 7.5ns @ CL = 3 (PC133) – 7.5ns @ CL = 2 (PC133) • Self refresh – Standard – Low power • Operating temperature range – Commercial (0˚C to +70˚C) – Industrial (–40˚C to +85˚C) • Revision • PC100- and PC133-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal, pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode • Auto refresh – 64ms, 8192-cycle refresh (commercial and industrial) • LVTTL-compatible inputs and outputs • Single 3.3V ±0.3V power supply Notes: 128M4 64M8 32M16 A2 TG P -75 -7E3 None L4 None IT :C 1. See technical note TN-48-05 on Micron's Web site. 2. Off-center parting line. 3. Available on x4 and x8 only. 4. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Access Time Speed Grade Clock Frequency CL = 2 CL = 3 Setup Time Hold Time -7E 143 MHz – 5.4ns 1.5ns 0.8ns -75 133 MHz – 5.4ns 1.5ns 0.8ns -7E 133 MHz 5.4ns – 1.5ns 0.8ns -75 100 MHz 6ns – 1.5ns 0.8ns PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512Mb: x4, x8, x16 SDRAM Features Table 2: Address Table 32 Meg x 4 32 Meg x 8 32 Meg x 16 32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks Parameter Configuration Refresh count 8K 8K 8K Row addressing 8K A[12:0] 8K A[12:0] 8K A[12:0] Bank addressing 4 BA[1:0] 4 BA[1:0] 4 BA[1:0] 4K A[9:0], A11, A12 2K A[9:0], A11 1K A[9:0] Column addressing Table 3: 512Mb SDR Part Numbering Part Numbers Architecture Package MT48LC128M4A2P 128 Meg x 4 54-pin TSOP II MT48LC128M4A2TG 128 Meg x 4 54-pin TSOP II MT48LC64M8A2P 64 Meg x 8 54-pin TSOP II MT48LC64M8A2TG 64 Meg x 8 54-pin TSOP II MT48LC32M16A2P 32 Meg x 16 54-pin TSOP II MT48LC32M16A2TG 32 Meg x 16 54-pin TSOP II PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Features Contents General Description ......................................................................................................................................... 6 Functional Block Diagrams ............................................................................................................................... 7 Pin and Ball Assignments and Descriptions ..................................................................................................... 10 Package Dimensions ....................................................................................................................................... 12 Temperature and Thermal Impedance ............................................................................................................ 13 Electrical Specifications .................................................................................................................................. 15 Electrical Specifications – IDD Parameters ........................................................................................................ 17 Electrical Specifications – AC Operating Conditions ......................................................................................... 18 Functional Description ................................................................................................................................... 21 Commands .................................................................................................................................................... 22 COMMAND INHIBIT .................................................................................................................................. 22 NO OPERATION (NOP) ............................................................................................................................... 23 LOAD MODE REGISTER (LMR) ................................................................................................................... 23 ACTIVE ...................................................................................................................................................... 23 READ ......................................................................................................................................................... 24 WRITE ....................................................................................................................................................... 25 PRECHARGE .............................................................................................................................................. 26 BURST TERMINATE ................................................................................................................................... 26 REFRESH ................................................................................................................................................... 27 AUTO REFRESH ..................................................................................................................................... 27 SELF REFRESH ....................................................................................................................................... 27 Truth Tables ................................................................................................................................................... 28 Initialization .................................................................................................................................................. 33 Mode Register ................................................................................................................................................ 35 Burst Length .............................................................................................................................................. 37 Burst Type .................................................................................................................................................. 37 CAS Latency ............................................................................................................................................... 39 Operating Mode ......................................................................................................................................... 39 Write Burst Mode ....................................................................................................................................... 39 Bank/Row Activation ...................................................................................................................................... 40 READ Operation ............................................................................................................................................. 41 WRITE Operation ........................................................................................................................................... 50 Burst Read/Single Write .............................................................................................................................. 57 PRECHARGE Operation .................................................................................................................................. 58 Auto Precharge ........................................................................................................................................... 58 AUTO REFRESH Operation ............................................................................................................................. 70 SELF REFRESH Operation ............................................................................................................................... 72 Power-Down .................................................................................................................................................. 74 Clock Suspend ............................................................................................................................................... 75 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Features List of Figures Figure 1: 128 Meg x 4 Functional Block Diagram ............................................................................................... 7 Figure 2: 64 Meg x 8 Functional Block Diagram ................................................................................................. 8 Figure 3: 32 Meg x 16 Functional Block Diagram ............................................................................................... 9 Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 10 Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P ......................................................................... 12 Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ................................................. 14 Figure 7: ACTIVE Command .......................................................................................................................... 23 Figure 8: READ Command ............................................................................................................................. 24 Figure 9: WRITE Command ........................................................................................................................... 25 Figure 10: PRECHARGE Command ................................................................................................................ 26 Figure 11: Initialize and Load Mode Register .................................................................................................. 34 Figure 12: Mode Register Definition ............................................................................................................... 36 Figure 13: CAS Latency .................................................................................................................................. 39 Figure 14: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 40 Figure 15: Consecutive READ Bursts .............................................................................................................. 42 Figure 16: Random READ Accesses ................................................................................................................ 43 Figure 17: READ-to-WRITE ............................................................................................................................ 44 Figure 18: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 45 Figure 19: READ-to-PRECHARGE .................................................................................................................. 45 Figure 20: Terminating a READ Burst ............................................................................................................. 46 Figure 21: Alternating Bank Read Accesses ..................................................................................................... 47 Figure 22: READ Continuous Page Burst ......................................................................................................... 48 Figure 23: READ – DQM Operation ................................................................................................................ 49 Figure 24: WRITE Burst ................................................................................................................................. 50 Figure 25: WRITE-to-WRITE .......................................................................................................................... 51 Figure 26: Random WRITE Cycles .................................................................................................................. 52 Figure 27: WRITE-to-READ ............................................................................................................................ 52 Figure 28: WRITE-to-PRECHARGE ................................................................................................................. 53 Figure 29: Terminating a WRITE Burst ............................................................................................................ 54 Figure 30: Alternating Bank Write Accesses ..................................................................................................... 55 Figure 31: WRITE – Continuous Page Burst ..................................................................................................... 56 Figure 32: WRITE – DQM Operation ............................................................................................................... 57 Figure 33: READ With Auto Precharge Interrupted by a READ ......................................................................... 59 Figure 34: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 60 Figure 35: READ With Auto Precharge ............................................................................................................ 61 Figure 36: READ Without Auto Precharge ....................................................................................................... 62 Figure 37: Single READ With Auto Precharge .................................................................................................. 63 Figure 38: Single READ Without Auto Precharge ............................................................................................. 64 Figure 39: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 65 Figure 40: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 65 Figure 41: WRITE With Auto Precharge ........................................................................................................... 66 Figure 42: WRITE Without Auto Precharge ..................................................................................................... 67 Figure 43: Single WRITE With Auto Precharge ................................................................................................. 68 Figure 44: Single WRITE Without Auto Precharge ............................................................................................ 69 Figure 45: Auto Refresh Mode ........................................................................................................................ 71 Figure 46: Self Refresh Mode .......................................................................................................................... 73 Figure 47: Power-Down Mode ........................................................................................................................ 74 Figure 48: Clock Suspend During WRITE Burst ............................................................................................... 75 Figure 49: Clock Suspend During READ Burst ................................................................................................. 76 Figure 50: Clock Suspend Mode ..................................................................................................................... 77 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Features List of Tables Table 1: Key Timing Parameters ....................................................................................................................... 1 Table 2: Address Table ..................................................................................................................................... 2 Table 3: 512Mb SDR Part Numbering ............................................................................................................... 2 Table 4: Pin and Ball Descriptions .................................................................................................................. 11 Table 5: Temperature Limits .......................................................................................................................... 13 Table 6: Thermal Impedance Simulated Values ............................................................................................... 14 Table 7: Absolute Maximum Ratings .............................................................................................................. 15 Table 8: DC Electrical Characteristics and Operating Conditions ..................................................................... 15 Table 9: Capacitance ..................................................................................................................................... 16 Table 10: IDD Specifications and Conditions (-7E, -75) ..................................................................................... 17 Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) ............................. 18 Table 12: AC Functional Characteristics (-7E, -75) ........................................................................................... 19 Table 13: Truth Table – Commands and DQM Operation ................................................................................. 22 Table 14: Truth Table – Current State Bank n, Command to Bank n .................................................................. 28 Table 15: Truth Table – Current State Bank n, Command to Bank m ................................................................. 30 Table 16: Truth Table – CKE ........................................................................................................................... 32 Table 17: Burst Definition Table ..................................................................................................................... 38 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM General Description General Description The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[12:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Functional Block Diagrams Functional Block Diagrams Figure 1: 128 Meg x 4 Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8192 x 4096 x 4) 1 DQM SENSE AMPLIFIERS 4 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A[12:0] BA[1:0] 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 4 4 4096 (x4) 1 DQ[3:0] DATA INPUT REGISTER COLUMN DECODER 12 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN COLUMNADDRESS COUNTER/ LATCH 12 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Functional Block Diagrams Figure 2: 64 Meg x 8 Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER ROWADDRESS MUX 12 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8192 x 2048 x 8) 1 DQM SENSE AMPLIFIERS 8 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A[12:0] BA[1:0] 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 8 8 2048 (x8) 1 DQ[7:0] DATA INPUT REGISTER COLUMN DECODER 11 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN COLUMNADDRESS COUNTER/ LATCH 11 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Functional Block Diagrams Figure 3: 32 Meg x 16 Functional Block Diagram CKE CLK COMMAND DECODE CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8192 x 1024 x 16) 2 DQML, DQMH SENSE AMPLIFIERS 16 16384 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A[12:0] BA[1:0] 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 1024 (x16) 2 DQ[15:0] DATA INPUT REGISTER COLUMN DECODER 10 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN COLUMNADDRESS COUNTER/ LATCH 10 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Pin and Ball Assignments and Descriptions Pin and Ball Assignments and Descriptions Figure 4: 54-Pin TSOP (Top View) x4 x8 NC NC DQ0 NC NC NC DQ1 NC NC - VDD DQ0 DQ0 VDDQ NC DQ1 DQ1 DQ2 VSSQ NC DQ3 DQ2 DQ4 VDDQ NC DQ5 DQ3 DQ6 VSSQ NC DQ7 VDD NC DQML WE# CAS# RAS# CS# BA0 BA1 A10 A0 A1 A2 A3 VDD - Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN x16 x16 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC DQMH CLK CKE A12 A11 A9 A8 A7 A6 A5 A4 VSS x8 x4 DQ7 NC DQ6 NC DQ5 NC DQ4 NC DQM - NC NC DQ3 NC NC NC DQ2 NC DQM - 1. The # symbol indicates that the signal is active LOW. A dash (-) indicates that the x8 and x4 pin function is the same as the x16 pin function. 2. Package may or may not be assembled with a location notch. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Pin and Ball Assignments and Descriptions Table 4: Pin and Ball Descriptions Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. CS# Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue, and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. CAS#, RAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. x4, x8: DQM Input Input/output mask: DQM is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. On the x4 and x8, DQML (pin 15) is a NC and DQMH is DQM. On the x16, DQML corresponds to DQ[7:0], and DQMH corresponds to DQ[15:8]. DQML and DQMH are considered same state when referenced as DQM. BA[1:0] Input Bank address input(s): BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. A[12:0] Input Address inputs: A[12:0] are sampled during the ACTIVE command (row address A[12:0]) and READ or WRITE command (column address A[9:0], A11, and A12 for x4; A[9:0] and A11 for x8; A[9:0] for x16; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by A10 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. x16: DQ[15:0] I/O Data input/output: Data bus for x16 (pins 4, 7, 10, 13, 15, 42, 45, 48, and 51 are NC for x8; and pins 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NC for x4). x8: DQ[7:0] I/O Data input/output: Data bus for x8 (pins 2, 8, 47, 53 are NC for x4). x4: DQ[3:0] I/O Data input/output: Data bus for x4. VDDQ Supply DQ power: DQ power to the die for improved noise immunity. VSSQ Supply DQ ground: DQ ground to the die for improved noise immunity. VDD Supply Power supply: +3.3V ±0.3V. VSS Supply NC – x16: DQML, DQMH LDQM, UDQM (54-ball) PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Ground. These should be left unconnected. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Package Dimensions Package Dimensions Figure 5: 54-Pin Plastic TSOP (400 mil) – Package Codes TG/P 0.10 1.2 MAX 0.375 ±0.075 TYP Pin #1 ID 0.80 TYP (for reference only) 22.22 ±0.08 2X R 0.75 2X R 1.00 2X 0.71 Plated lead finish: 90% Sn, 10% Pb, or 100% Sn Plastic package material: Epoxy novolac Package width and length do not include mold protrusion. Allowable protrusion is 0.25 per side. 2X 0.10 2.80 Gage plane 10.16 ±0.08 0.25 +0.10 0.10 -0.05 11.76 ±0.20 See Detail A 0.15 +0.03 -0.02 0.50 ±0.10 0.80 Detail A Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. 2X means the notch is present in two locations (both ends of the device). 4. Package may or may not be assembled with a location notch. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Temperature and Thermal Impedance Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 6 (page 14), be maintained to ensure the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed in Table 6 (page 14) for the applicable die revision and packages being made available. These thermal impedance values vary according to the density, package, and particular design used for each device. Incorrectly using thermal impedances can produce significant errors. Read Micron technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances listed in Table 6 (page 14). To ensure the compatibility of current and future designs, contact Micron Applications Engineering to confirm thermal impedance values. The SDRAM device’s safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device’s ambient temperature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. Table 5: Temperature Limits Parameter Operating case temperature Symbol Min Max Unit Notes TC 0 80 °C 1, 2, 3, 4 –40 90 0 85 °C 3 –40 95 0 70 °C 3, 5 –40 85 – 260 Commercial Industrial Junction temperature Commercial TJ Industrial Ambient temperature Commercial TA Industrial Peak reflow temperature Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN TPEAK °C 1. MAX operating case temperature, TC, is measured in the center of the package on the top side of the device, as shown in Figure 6 (page 14). 2. Device functionality is not guaranteed if the device exceeds maximum TC during operation. 3. All temperature specifications must be satisfied. 4. The case temperature should be measured by gluing a thermocouple to the top-center of the component. This should be done with a 1mm bead of conductive epoxy, as defined by the JEDEC EIA/JESD51 standards. Take care to ensure that the thermocouple bead is touching the case. 5. Operating ambient temperature surrounding the package. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Temperature and Thermal Impedance Table 6: Thermal Impedance Simulated Values Die Revision Package D 54-pin TSOP Notes: Substrate Θ JA (°C/W) Airflow = 0m/s Θ JA (°C/W) Airflow = 1m/s Θ JA (°C/W) Airflow = 2m/s 2-layer 62.6 48.4 44.2 19.2 4-layer 39.2 32.3 30.6 19.3 Θ JB (°C/W) Θ JC (°C/W) 6.7 1. For designs expected to last beyond the die revision listed, contact Micron Applications Engineering to confirm thermal impedance values. 2. Thermal resistance data is sampled from multiple lots, and the values should be viewed as typical. 3. These are estimates; actual results may vary. Figure 6: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) 22.22mm 11.11mm Test point 10.16mm 5.08mm Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. Package may or may not be assembled with a location notch. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 7: Absolute Maximum Ratings Voltage/Temperature Symbol Min Max Unit Notes Voltage on VDD/VDDQ supply relative to VSS VDD/VDDQ –1 +4.6 V 1 Voltage on inputs, NC, or I/O balls relative to VSS VIN –1 +4.6 Storage temperature (plastic) TSTG –55 +155 °C – – 1 W Power dissipation Note: 1. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD. Table 8: DC Electrical Characteristics and Operating Conditions Notes 1–3 apply to all parameters and conditions; VDD/VDDQ = +3.3V ±0.3V Parameter/Condition Symbol VDD, VDDQ Supply voltage Min Max Unit 3 3.6 V Notes Input high voltage: Logic 1; All inputs VIH 2 VDD + 0.3 V 4 Input low voltage: Logic 0; All inputs VIL –0.3 +0.8 V 4 Output high voltage: IOUT = –4mA VOH 2.4 – V Output low voltage: IOUT = 4mA VOL – 0.4 V IL –5 5 μA IOZ –5 5 μA Input leakage current: Any input 0V ≤ VIN ≤ VDD (All other balls not under test = 0V) Output leakage current: DQ are disabled; 0V ≤ VOUT ≤ VDDQ Operating temperature: Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Commercial TA 0 +70 ˚C Industrial TA –40 +85 ˚C 1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)). 3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse width ≤3ns. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications Table 9: Capacitance Note 1 applies to all parameters and conditions Package Parameter TSOP "TG" package Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Symbol Min Max Unit Notes Input capacitance: CLK CL1 2.5 3.5 pF 2 Input capacitance: All other input-only balls CL2 2.5 3.8 pF 3 Input/output capacitance: DQ CL0 4 6 pF 4 1. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 2. PC100 specifies a maximum of 4pF. 3. PC100 specifies a maximum of 5pF. 4. PC100 specifies a maximum of 6.5pF. 5. PC133 specifies a minimum of 2.5pF. 6. PC133 specifies a minimum of 2.5pF. 7. PC133 specifies a minimum of 3.0pF. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications – IDD Parameters Electrical Specifications – IDD Parameters Table 10: IDD Specifications and Conditions (-7E, -75) Notes 1–5 apply to all parameters and conditions; VDD/VDDQ = +3.3V ±0.3V Max Parameter/Condition Symbol -7E -75 Unit Notes Operating current: Active mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1 120 110 mA 6, 9, 10, 13 Standby current: Power-down mode; All banks idle; CKE = LOW IDD2 3.5 3.5 mA 13 Standby current: Active mode; CKE = HIGH; CS# = HIGH; All banks active after tRCD met; No accesses in progress IDD3 45 45 mA 6, 8, 10, 13 Operating current: Burst mode; Page burst; READ or WRITE; All banks active IDD4 125 115 mA 6, 9, 10, 13 6, 8, 9, 10, 13, 14 Auto refresh current: CKE = HIGH; CS# = HIGH Self refresh current: CKE ≤ 0.2V Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN tRFC = tRFC (MIN) IDD5 255 255 mA tRFC = 7.813μs IDD6 6 6 mA Standard IDD7 6 6 mA Low power (L) IDD7 3 3 mA 7 1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured; (0°C ≤ TA ≤ +70°C (commercial), –40°C ≤ TA ≤ +85°C (industrial), and –40°C ≤ TA ≤ +105°C (automotive)). 3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is measured from VIL, max and VIH,min and no longer from the 1.5V midpoint. CLK should always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09. 5. IDD specifications are tested after the device is properly initialized. 6. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 7. Enables on-chip refresh and address counters. 8. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 9. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 10. Address transitions average one transition every two clocks. 11. PC100 specifies a maximum of 4pF. 12. PC100 specifies a maximum of 5pF. 13. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns. 14. CKE is HIGH during REFRESH command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications – AC Operating Conditions Electrical Specifications – AC Operating Conditions Table 11: Electrical Characteristics and Recommended AC Operating Conditions (-7E, -75) Notes 1, 2, 4, 5, 7, and 20 apply to all parameters and conditions -7E Parameter -75 Symbol Min Max Min Max Unit Notes CL = 3 tAC(3) – 5.4 – 5.4 ns 18 CL = 2 tAC(2) – 5.4 – 6 Address hold time tAH 0.8 – 0.8 – Address setup time tAS 1.5 – 1.5 – ns CLK high-level width tCH 2.5 – 2.5 – ns CLK low-level width tCL 2.5 – 2.5 – ns CL = 3 tCK(3) 7 – 7.5 – ns CL = 2 tCK(2) 7.5 – 10 – CKE hold time tCKH 0.8 – 0.8 – ns CKE setup time tCKS 1.5 – 1.5 – ns CS#, RAS#, CAS#, WE#, DQM hold time tCMH 0.8 – 0.8 – ns CS#, RAS#, CAS#, WE#, DQM setup time tCMS 1.5 – 1.5 – ns Data-in hold time tDH 0.8 – 0.8 – ns Data-in setup time tDS 1.5 – 1.5 – ns CL = 3 tHZ(3) – 5.4 – 5.4 ns CL = 2 tHZ(2) – 5.4 – 6 ns Data-out Low-Z time tLZ 1 – 1 – ns Data-out hold time (load) tOH 2.7 – 2.7 – ns Data-out hold time (no load) tOHn 1.8 – 1.8 – ns ACTIVE-to-PRECHARGE command tRAS 37 120,000 44 120,000 ns tRC 60 – 66 – ns ACTIVE-to-READ or WRITE delay tRCD 15 – 20 – ns Refresh period (8192 rows) tREF – 64 – 64 ms AUTO REFRESH period tRFC 66 – 66 – ns tRP 15 – 20 – ns Access time from CLK (positive edge) Clock cycle time Data-out High-Z time ACTIVE-to-ACTIVE command period PRECHARGE command period ns 14 21 6 19 23 tRRD 14 – 15 – tCK tT 0.3 1.2 0.3 1.2 ns 3 WRITE recovery time tWR 1 CLK + 7ns – 1 CLK + 7.5ns – ns 15 14 – 15 – Exit SELF REFRESH-to-ACTIVE command tXSR 67 – 75 – ACTIVE bank a to ACTIVE bank b command Transition time PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 18 16 ns 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications – AC Operating Conditions Table 12: AC Functional Characteristics (-7E, -75) Notes 1–5 and note 7 apply to all parameters and conditions Parameter Symbol -7E -75 Unit 1 1 tCK 11 1 1 tCK 11 1 tCK 11 1 tCK 8 9, 13 Last data-in to burst STOP command tBDL READ/WRITE command to READ/WRITE command tCCD Last data-in to new READ/WRITE command tCDL 1 tCKED CKE to clock disable or power-down entry mode 1 Notes Data-in to ACTIVE command tDAL 4 5 tCK Data-in to PRECHARGE command tDPL 2 2 tCK 10, 13 DQM to input data delay tDQD 0 0 tCK 11 DQM to data mask during WRITEs tDQM 0 tCK 11 DQM to data High-Z during READs tDQZ 2 2 tCK 11 WRITE command to input data delay tDWD 0 0 tCK 11 LOAD MODE REGISTER command to ACTIVE or REFRESH command tMRD 2 2 tCK 17 CKE to clock enable or power-down exit setup mode tPED 1 tCK 8 Last data-in to PRECHARGE command tRDL 2 2 tCK 10, 13 CL = 3 tROH(3) 3 3 tCK 11 CL = 2 tROH(2) 2 tCK 11 Data-out High-Z from PRECHARGE command Notes: 0 1 2 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0˚C ≤ TA ≤ +70˚C commercial temperature, -40˚C ≤ TA ≤ +85˚C industrial temperature, and -40˚C ≤ TA ≤ +105˚C automotive temperature) is ensured. 2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 6. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 7. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is measured from VIL,max and VIH,min and no longer from the 1.5V midpoint. CLK should always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09. 8. Timing is specified by tCKS. Clock(s) specified as a reference only at minimum cycle rate. 9. Timing is specified by tWR plus tRP. Clock(s) specified as a reference only at minimum cycle rate. 10. Timing is specified by tWR. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Electrical Specifications – AC Operating Conditions 11. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 12. CLK must be toggled a minimum of two times during this period. 13. Based on tCK = 7.5ns for -75 and -7E, 6ns for -6A. 14. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 15. Auto precharge mode only. The precharge timing budget (tRP) begins at 7ns for -7E and 7.5ns for -75 after the first clock delay and after the last WRITE is executed. 16. Precharge mode only. 17. JEDEC and PC100 specify three clocks. 18. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is guaranteed by design. 19. Parameter guaranteed by design. 20. PC100 specifies a maximum of 6.5pF. 21. For operating frequencies ≤ 45 MHz, tCKS = 3.0ns. 22. Auto precharge mode only. The precharge timing budget (tRP) begins 6ns for -6A after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 23. DRAM devices should be evenly addressed when being accessed. Disproportionate accesses to a particular row address may result in reduction of the product lifetime. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Functional Description Functional Description In general, 512Mb SDRAM devices (32 Meg x 4 x 4 banks, 16 Meg x 8 x 4 banks, and 16 Meg x 16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 4096 columns by 4 bits. Each of the x8’s 134,217,728-bit banks is organized as 8192 rows by 2048 columns by 8 bits. Each of the x16’s 134,217,728-bit banks is organized as 8192 rows by 1024 columns by 16 bits. Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A[12:0] select the row). The address bits (x4: A[9:0], A11, A12; x8: A[9:0], A11; x16: A[9:0]) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands Commands The following table provides a quick reference of available commands, followed by a written description of each command. Additional Truth Tables (Table 14 (page 28), Table 15 (page 30), and Table 16 (page 32)) provide current state/next state information. Table 13: Truth Table – Commands and DQM Operation Note 1 applies to all parameters and conditions Name (Function) CS# RAS# CAS# WE# DQM ADDR DQ Notes COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (select bank and activate row) L L H H X Bank/row X 2 READ (select bank and column, and start READ burst) L H L H L/H Bank/col X 3 WRITE (select bank and column, and start WRITE burst) L H L L L/H Bank/col Valid 3 BURST TERMINATE L H H L X X Active 4 PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or SELF REFRESH (enter self refresh mode) L L L H X X X 6, 7 LOAD MODE REGISTER L L L L X Op-code X 8 Write enable/output enable X X X X L X Active 9 Write inhibit/output High-Z X X X X H X High-Z 9 Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1 determine which bank is made active. 3. A[0:i] provide column address (where i = the most significant column address for a given device configuration). A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which bank is being read from or written to. 4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the command could coincide with data on the bus. However, the DQ column reads a “Don’t Care” state to illustrate that the BURST TERMINATE command can occur when there is no data present. 5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks precharged and BA0, BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. A[11:0] define the op-code written to the mode register. 9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay). COMMAND INHIBIT The COMMAND INHIBIT function prevents new commands from being executed by the device, regardless of whether the CLK signal is enabled. The device is effectively deselected. Operations already in progress are not affected. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to the selected device (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER (LMR) The mode registers are loaded via inputs A[n:0] (where An is the most significant address term), BA0, and BA1(see Mode Register (page 35)). The LOAD MODE REGISTER command can only be issued when all banks are idle and a subsequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to activate a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided selects the row. This row remains active for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. Figure 7: ACTIVE Command CLK CKE HIGH CS# RAS# CAS# WE# Address Row address BA0, BA1 Bank address Don’t Care PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands READ The READ command is used to initiate a burst read access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed is precharged at the end of the READ burst; if auto precharge is not selected, the row remains open for subsequent accesses. Read data appears on the DQ subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQ will be HighZ two clocks later; if the DQM signal was registered LOW, the DQ will provide valid data. Figure 8: READ Command CLK CKE HIGH CS# RAS# CAS# WE# Address Column address EN AP A101 DIS AP BA0, BA1 Bank address Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. EN AP = enable auto precharge, DIS AP = disable auto precharge. 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands WRITE The WRITE command is used to initiate a burst write access to an active row. The values on the BA0 and BA1 inputs select the bank; the address provided selects the starting column location. The value on input A10 determines whether auto precharge is used. If auto precharge is selected, the row being accessed is precharged at the end of the write burst; if auto precharge is not selected, the row remains open for subsequent accesses. Input data appearing on the DQ is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data is written to memory; if the DQM signal is registered HIGH, the corresponding data inputs are ignored and a WRITE is not executed to that byte/column location. Figure 9: WRITE Command CLK CKE HIGH CS# RAS# CAS# WE# Address Column address EN AP A101 DIS AP BA0, BA1 Bank address Valid address Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. EN AP = enable auto precharge, DIS AP = disable auto precharge. 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands are issued to that bank. Figure 10: PRECHARGE Command CLK CKE HIGH CS# RAS# CAS# WE# Address All banks A10 Bank selected BA0, BA1 Bank address Valid address Don’t Care BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or continuous page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command is truncated. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Commands REFRESH AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command, as shown in Bank/Row Activation (page 40). The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. Regardless of device width, the 512Mb SDRAM requires 8192 AUTO REFRESH cycles every 64ms (commercial and industrial). Providing a distributed AUTO REFRESH command every 7.813μs (commercial and industrial) will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRFC), once every 64ms (commercial and industrial). SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered-down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the SDRAM become a “Don’t Care” with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. After CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued at the specified intervals, as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Truth Tables Truth Tables Table 14: Truth Table – Current State Bank n, Command to Bank n Notes 1–6 apply to all parameters and conditions Current State CS# RAS# CAS# Any Idle Row active Read (auto precharge disabled) Write (auto precharge disabled) Notes: WE# Command/Action Notes H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) L L H H ACTIVE (select and activate row) L L L H AUTO REFRESH L L L L LOAD MODE REGISTER 7 L L H L PRECHARGE 8 L H L H READ (select column and start READ burst) 9 L H L L WRITE (select column and start WRITE burst) 9 L L H L PRECHARGE (deactivate row in bank or banks) 10 L H L H READ (select column and start new READ burst) 9 L H L L WRITE (select column and start WRITE burst) 9 L L H L PRECHARGE (truncate READ burst, start PRECHARGE) 10 L H H L BURST TERMINATE 11 L H L H READ (select column and start READ burst) 9 L H L L WRITE (select column and start new WRITE burst) 9 L L H L PRECHARGE (truncate WRITE burst, start PRECHARGE) 10 L H H L BURST TERMINATE 11 7 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 16 (page 32)) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (for example, the current state is for a specific bank and the commands shown can be issued to that bank when in that state). Exceptions are covered below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or supported commands to the other bank should be issued on any clock edge occurring during these states. Supported commands to any other bank are determined by the bank’s current state and the conditions described in this and the following table. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. After tRP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when tRCD is met. After tRCD is met, the bank will be in the row active state. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Truth Tables Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. Write with auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. After tRFC is met, the device will be in the all banks idle state. Accessing mode register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. After tMRD is met, the device will be in the all banks idle state. 6. 7. 8. 9. 10. 11. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Precharging all: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. After tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank specific; requires that all banks are idle. Does not affect the state of the bank and acts as a NOP to that bank. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. May or may not be bank specific; if all banks need to be precharged, each must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank. 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Truth Tables Table 15: Truth Table – Current State Bank n, Command to Bank m Notes 1–6 apply to all parameters and conditions Current State CS# RAS# CAS# Any WE# Command/Action Notes H X X X COMMAND INHIBIT (NOP/continue previous operation) L H H H NO OPERATION (NOP/continue previous operation) Idle X X X X Any command otherwise supported for bank m Row activating, active, or precharging L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) 7 L H L L WRITE (select column and start WRITE burst) 7 L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) 7, 10 L H L L WRITE (select column and start WRITE burst) 7, 11 L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) 7, 12 L H L L WRITE (select column and start new WRITE burst) 7, 13 L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start new READ burst) 7, 8, 14 L H L L WRITE (select column and start WRITE burst) 7, 8, 15 L L H L PRECHARGE L L H H ACTIVE (select and activate row) L H L H READ (select column and start READ burst) 7, 8, 16 L H L L WRITE (select column and start new WRITE burst) 7, 8, 17 L L H L PRECHARGE Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge) Notes: 9 9 9 9 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (Table 16 (page 32)), and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; for example, the current state is for bank n and the commands shown can be issued to bank m, assuming that bank m is in such a state that the given command is supported. Exceptions are covered below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Truth Tables Read with auto precharge enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Write with auto precharge enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. After tRP is met, the bank will be in the idle state. AUTO REFRESH, SELF REFRESH, and LOAD MODE REGISTER commands can only be issued when all banks are idle. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. All states and sequences not shown are illegal or reserved. READs or WRITEs to bank m listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Concurrent auto precharge: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m burst. The burst in bank n continues as initiated. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency (CL) later. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used one clock prior to the WRITE command to prevent bus contention. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CL later. The PRECHARGE to bank n will begin when the READ to bank m is registered. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CL later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE bank n will be data-in registered one clock prior to the READ to bank m. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Truth Tables Table 16: Truth Table – CKE Notes 1–4 apply to all parameters and conditions Current State CKEn-1 CKEn Power-down L Commandn Actionn X Maintain power-down X Maintain self refresh L Self refresh Clock suspend Power-down L H Self refresh X Maintain clock suspend COMMAND INHIBIT or NOP Exit power-down 5 COMMAND INHIBIT or NOP Exit self refresh 6 X Exit clock suspend 7 COMMAND INHIBIT or NOP Power-down entry AUTO REFRESH Self refresh entry VALID Clock suspend entry Clock suspend All banks idle H L All banks idle Reading or writing H Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN H Notes See Table 15 (page 30). 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during the tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Initialization Initialization SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. After power is applied to V DD and V DDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100μs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100μs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, at least two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it must be loaded prior to applying any operational command. If desired, the two AUTO REFRESH commands can be issued after the LMR command. The recommended power-up sequence for SDRAM: 1. Simultaneously apply power to V DD and V DDQ. 2. Assert and hold CKE at a LVTTL logic LOW since all inputs and outputs are LVTTLcompatible. 3. Provide stable CLOCK signal. Stable clock is defined as a signal cycling within timing constraints specified for the clock pin. 4. Wait at least 100μs prior to issuing any command other than a COMMAND INHIBIT or NOP. 5. Starting at some point during this 100μs period, bring CKE HIGH. Continuing at least through the end of this period, 1 or more COMMAND INHIBIT or NOP commands must be applied. 6. Perform a PRECHARGE ALL command. 7. Wait at least tRP time; during this time NOPs or DESELECT commands must be given. All banks will complete their precharge, thereby placing the device in the all banks idle state. 8. Issue an AUTO REFRESH command. 9. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 10. Issue an AUTO REFRESH command. 11. Wait at least tRFC time, during which only NOPs or COMMAND INHIBIT commands are allowed. 12. The SDRAM is now ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded with desired bit values prior to applying any operational command. Using the LMR command, program the mode register. The mode register is programmed via the MODE REGISTER SET command with BA1 = 0, BA0 = 0 and retains the stored information until it is programmed again or the device loses power. Not programming the mode register upon initialization will result in default settings which may not be desired. Outputs are guaranteed High-Z after the LMR command is issued. Outputs should be High-Z already before the LMR command is issued. 13. Wait at least tMRD time, during which only NOP or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Initialization Note: More than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + tRFC loops is achieved. Figure 11: Initialize and Load Mode Register T0 CK T1 (( )) (( )) tCK (( )) tCKS tCKH Tn + 1 tCH (( )) (( )) To + 1 tCL (( )) (( )) (( )) (( )) (( )) Tp + 1 Tp + 2 Tp + 3 (( )) CKE (( )) (( )) COMMAND (( )) (( )) DQM/DQML, DQMU (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A[9:0], A[12:11] (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tRFC tRFC tCMS tCMH BA[1:0] DQ NOP2 PRECHARGE ALL BANKS SINGLE BANK (( )) (( )) (( )) T = 100μs MIN ALL BANKS High-Z (( )) (( )) AUTO REFRESH (( )) NOP2 (( )) AUTO REFRESH (( )) NOP2 (( )) LOAD MODE REGISTER tAS NOP2 ACTIVE tAH5 ROW CODE tAS tAH ROW CODE Bank Address (( )) tRP Power-up: VDD and CLK stable Precharge all banks AUTO REFRESH AUTO REFRESH tMRD Program Mode Register1,3,4 DON’T CARE UNDEFINED Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. 2. 3. 4. 5. The mode register may be loaded prior to the AUTO REFRESH cycles if desired. If CS is HIGH at clock HIGH time, all commands applied are NOP. JEDEC and PC100 specify three clocks. Outputs are guaranteed High-Z after command is issued. A12 should be a LOW at tP + 1. 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Mode Register Mode Register The mode register defines the specific mode of operation, including burst length (BL), burst type, CAS latency (CL), operating mode, and write burst mode. The mode register is programmed via the LOAD MODE REGISTER command and retains the stored information until it is programmed again or the device loses power. Mode register bits M[2:0] specify the BL; M3 specifies the type of burst; M[6:4] specify the CL; M7 and M8 specify the operating mode; M9 specifies the write burst mode; and M10–Mn should be set to zero to ensure compatibility with future revisions. Mn + 1 and Mn + 2 should be set to zero to select the mode register. The mode registers must be loaded when all banks are idle, and the controller must wait tMRD before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Mode Register Figure 12: Mode Register Definition A12 A11 A10 12 11 10 A9 8 9 WB Reserved A8 A7 7 Op Mode A5 A6 A4 5 6 A3 3 4 CAS Latency Program BA1, BA0 = “0, 0” to ensure compatibility with future devices. A0 0 Address Bus Mode Register (Mx) Burst Length Burst Length M2 M1 M0 Write Burst Mode M9 1 2 BT A1 A2 0 Programmed Burst Length 1 Single Location Access M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved M8 M7 M6-M0 Operating Mode 1 0 1 Reserved Reserved 0 0 Defined Standard Operation 1 1 0 Reserved Reserved – – – All other states reserved 1 1 1 Full Page Reserved M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Burst Type 0 0 0 Reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Mode Register Burst Length Read and write accesses to the device are burst oriented, and the burst length (BL) is programmable. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, 8, or continuous locations are available for both the sequential and the interleaved burst types, and a continuous page burst is available for the sequential type. The continuous page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block when a boundary is reached. The block is uniquely selected by A[8:1] when BL = 2, A[8:2] when BL = 4, and A[8:3] when BL = 8. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Continuous page bursts wrap within the page when the boundary is reached. Burst Type Accesses within a given burst can be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Mode Register Table 17: Burst Definition Table Order of Accesses Within a Burst Burst Length Starting Column Address 2 Type = Interleaved 0 0-1 0-1 1 1-0 1-0 A0 4 8 Type = Sequential A1 A0 0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 A2 A1 A0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn... Not supported Continuous n = A0–An/9/8 (location 0–y) Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For full-page accesses: y = 2048 (x4); y = 1024 (x8); y = 512 (x16). 2. For BL = 2, A1–A9, A11 (x4); A1–A9 (x8); or A1–A8 (x16) select the block-of-two burst; A0 selects the starting column within the block. 3. For BL = 4, A2–A9, A11 (x4); A2–A9 (x8); or A2–A8 (x16) select the block-of-four burst; A0–A1 select the starting column within the block. 4. For BL = 8, A3–A9, A11 (x4); A3–A9 (x8); or A3–A8 (x16) select the block-of-eight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For BL = 1, A0–A9, A11 (x4); A0–A9 (x8); or A0–A8 (x16) select the unique column to be accessed, and mode register bit M3 is ignored. 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Mode Register CAS Latency The CAS latency (CL) is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 13: CAS Latency T0 T1 T2 T3 NOP NOP CLK Command READ tOH tLZ DOUT DQ tAC CL = 2 T0 T1 T2 T3 NOP NOP NOP T4 CLK Command READ tOH tLZ DOUT DQ tAC CL = 3 Don’t Care Undefined Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use. Reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M[2:0] applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Bank/Row Activation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with the ACTIVE command, a READ or WRITE command can be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 14 (page 40), which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been precharged. The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD. Figure 14: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 T0 T1 T2 T3 CLK tCK Command ACTIVE tCK NOP tCK NOP READ or WRITE tRCD(MIN) Don’t Care PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation READ Operation READ bursts are initiated with a READ command, as shown in Figure 8 (page 24). The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. In the following figures, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address is available following the CAS latency after the READ command. Each subsequent dataout element will be valid by the next positive clock edge. Figure 16 (page 43) shows general timing for each possible CAS latency setting. Upon completion of a burst, assuming no other commands have been initiated, the DQ signals will go to High-Z. A continuous page burst continues until terminated. At the end of the page, it wraps to column 0 and continues. Data from any READ burst can be truncated with a subsequent READ command, and data from a fixed-length READ burst can be followed immediately by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst either follows the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 16 (page 43) for CL2 and CL3. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a READ command. Full-speed random read accesses can be performed to the same bank, or each subsequent READ can be performed to a different bank. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 15: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK Command READ NOP NOP NOP NOP READ NOP X = 1 cycle Address Bank, Col n Bank, Col b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command READ NOP NOP NOP READ NOP NOP NOP X = 2 cycles Address Bank, Col n Bank, Col b DOUT DQ CL = 3 Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN DOUT DOUT Transitioning data DOUT DOUT Don’t Care 1. Each READ command can be issued to any bank. DQM is LOW. 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 16: Random READ Accesses T0 T1 T2 T3 T4 Command READ READ READ READ Address Bank, Col n Bank, Col a Bank, Col x Bank, Col m T5 CLK DOUT DQ NOP DOUT NOP DOUT DOUT CL = 2 T0 T1 T2 T3 T4 Command READ READ READ READ Address Bank, Col n Bank, Col a Bank, Col x Bank, Col m T5 T6 CLK NOP DOUT DQ DOUT NOP DOUT NOP DOUT CL = 3 Transitioning data Note: Don’t Care 1. Each READ command can be issued to any bank. DQM is LOW. Data from any READ burst can be truncated with a subsequent WRITE command, and data from a fixed-length READ burst can be followed immediately by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst can be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there is a possibility that the device driving the input data will go Low-Z before the DQ go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 17 (page 44) and Figure 18 (page 45). The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. After the WRITE command is registered, the DQ will go to High-Z (or remain High-Z), regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4, then the WRITEs at T5 and T7 would be valid, and the WRITE at T6 would be invalid. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 17 (page 44) shows where, due to the clock cycle frequency, bus contention is avoided without having to add a NOP cycle, while Figure 18 (page 45) shows the case where an additional NOP cycle is required. A fixed-length READ burst may be followed by or truncated with a PRECHARGE command to the same bank, provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 19 (page 45) for each possible CL; data element n + 3 is either the last of a burst of four or the last desired data element of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate fixed-length or continuous page bursts. Figure 17: READ-to-WRITE T0 T1 T2 T3 T4 CLK DQM Command READ Address Bank, Col n NOP NOP NOP WRITE Bank, Col b tCK tHZ DOUT DQ DIN t DS Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be to any bank. If a burst of one is used, DQM is not required. 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 18: READ-to-WRITE With Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM Command Address READ NOP NOP NOP NOP WRITE Bank, Col n Bank, Col b tHZ DOUT DQ DIN tDS Transitioning data Note: Don’t Care 1. CL = 3. The READ command can be issued to any bank, and the WRITE command can be to any bank. Figure 19: READ-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 CLK tRP Command READ Address Bank a, Col n NOP NOP NOP NOP PRECHARGE NOP ACTIVE X = 1 cycle Bank (a or all) DOUT DQ Bank a, Row DOUT DOUT DOUT CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK t RP Command READ NOP NOP NOP PRECHARGE NOP NOP ACTIVE X = 2 cycles Address Bank (a or all) Bank a, Col DOUT DQ DOUT Bank a, Row DOUT DOUT CL = 3 Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. DQM is LOW. 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Continuous-page READ bursts can be truncated with a BURST TERMINATE command and fixed-length READ bursts can be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x = CL - 1. This is shown in Figure 20 (page 46) for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. Figure 20: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK Command READ Address Bank, Col n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT DQ DOUT DOUT DOUT CL = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK Command READ Address Bank, Col n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT DQ DOUT DOUT DOUT CL = 3 Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. DQM is LOW. 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 21: Alternating Bank Read Accesses T0 T1 tCK CLK T2 T3 T4 T5 T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP READ ACTIVE NOP NOP tCMS tCMH DQM tAS Address Row tAS A10 Row Column m tAH Column b Enable auto precharge 1 Row Enable auto precharge Row tAS BA0, BA1 tAH Row Row tAH Bank 0 Bank 0 Bank 3 Bank 3 tAC tOH tAC DQ tLZ tRCD - bank 0 tAC tOH DOUT DOUT Bank 0 tAC tOH DOUT tAC tOH DOUT tRP - bank 0 CL - bank 0 tAC tOH DOUT tRCD - bank 0 tRAS - bank 0 tRC - bank 0 tRRD tRCD - bank 3 CL - bank 3 Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Undefined 1. For this example, BL = 4 and CL = 2. 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 22: READ Continuous Page Burst T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH Tn + 1 Tn + 2 Tn + 3 Tn + 4 tCKS tCKH (( )) (( )) CKE tCMS Command tCMH ACTIVE NOP READ tCMS NOP NOP NOP NOP tCMH tAS tAS A10 BURST TERM NOP NOP (( )) (( )) Column m tAH (( )) (( )) Row tAS BA0, BA1 tAH Row NOP (( )) (( )) DQM Address (( )) (( )) tAH Bank (( )) (( )) Bank tAC tAC tOH DOUT DQ DOUT tLZ tRCD CAS latency tAC tOH tAC tOH (( )) (( DOUT ) ) (( )) tAC tOH DOUT Full-page burst does not self-terminate. Can use BURST TERMINATE command. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN DOUT tOH DOUT tHZ All locations within same row Full page completed Note: tAC tOH Don’t Care Undefined 1. For this example, CL = 2. 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM READ Operation Figure 23: READ – DQM Operation T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP READ tCMS NOP NOP tCMH DQM tAS Row Address tAS Column m tAH Enable auto precharge Row A10 tAS BA0, BA1 tAH Disable auto precharge tAH Bank Bank tAC tOH tAC DQ DOUT tLZ tRCD tHZ CL = 2 tAC tLZ tOH tOH DOUT DOUT tHZ Don’t Care Undefined Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 4 and CL = 2. 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation WRITE Operation WRITE bursts are initiated with a WRITE command, as shown in Figure 9 (page 25). The starting column and bank addresses are provided with the WRITE command and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following figures, auto precharge is disabled. During WRITE bursts, the first valid data-in element is registered coincident with the WRITE command. Subsequent data elements are registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQ will remain at High-Z and any additional input data will be ignored (see Figure 24 (page 50)). A continuous page burst continues until terminated; at the end of the page, it wraps to column 0 and continues. Data for any WRITE burst can be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst can be followed immediately by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command (see Figure 25 (page 51)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 26 (page 52), or each subsequent WRITE can be performed to a different bank. Figure 24: WRITE Burst T0 T1 T2 T3 Command WRITE NOP NOP NOP Address Bank, Col n CLK DQ DIN DIN Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. BL = 2. DQM is LOW. 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 25: WRITE-to-WRITE T0 T1 T2 Command WRITE NOP WRITE Address Bank, Col n CLK DQ DIN Bank, Col b DIN Transitioning data Note: DIN Don’t Care 1. DQM is LOW. Each WRITE command may be issued to any bank. Data for any WRITE burst can be truncated with a subsequent READ command, and data for a fixed-length WRITE burst can be followed immediately by a READ command. After the READ command is registered, data input is ignored and WRITEs will not be executed (see Figure 27 (page 52)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. Data for a fixed-length WRITE burst can be followed by or truncated with a PRECHARGE command to the same bank, provided that auto precharge was not activated. A continuous-page WRITE burst can be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued tWR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock with time to complete, regardless of frequency. In addition, when truncating a WRITE burst at high clock frequencies ( tCK < 15ns), the DQM signal must be used to mask input data for the clock edge prior to and the clock edge coincident with the PRECHARGE command (see Figure 28 (page 53)). Data n + 1 is either the last of a burst of two or the last desired data element of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command. The advantage of the PRECHARGE command is that it can be used to truncate fixed-length bursts or continuous page bursts. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 26: Random WRITE Cycles T0 T1 T2 T3 Command WRITE WRITE WRITE WRITE Address Bank, Col n Bank, Col a Bank, Col x Bank, Col m DIN DIN DIN DIN CLK DQ Transitioning data Note: Don’t Care 1. Each WRITE command can be issued to any bank. DQM is LOW. Figure 27: WRITE-to-READ T0 T1 T2 Command WRITE NOP READ Address Bank, Col n T3 T4 T5 NOP NOP NOP DOUT DOUT CLK DQ DIN Bank, Col b DIN Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Don’t Care 1. The WRITE command can be issued to any bank, and the READ command can be to any bank. DQM is LOW. CL = 2 for illustration. 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 28: WRITE-to-PRECHARGE T0 T1 T2 T3 T4 T5 T6 NOP ACTIVE NOP CLK tWR @ tCK ≥ 15ns DQM tRP Command Address WRITE NOP NOP PRECHARGE Bank (a or all) Bank a, Col n Bank a, Row tWR DQ DIN DIN tWR @ tCK < 15ns DQM tRP Command Address WRITE NOP NOP PRECHARGE NOP NOP Bank (a or all) Bank a, Col n ACTIVE Bank a, Row t WR DQ DIN DIN Transitioning data Note: Don’t Care 1. In this example DQM could remain LOW if the WRITE burst is a fixed length of two. Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command is ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 29 (page 54), where data n is the last desired data element of a longer burst. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 29: Terminating a WRITE Burst T0 T1 Command WRITE BURST TERMINATE Address Bank, Col n T2 CLK DQ DIN Transitioning data Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN NEXT COMMAND Address Data Don’t Care 1. DQM is LOW. 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 30: Alternating Bank Write Accesses T0 T1 tCK CLK T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE tCMS NOP NOP ACTIVE tCMH DQM tAS Address tAS A10 Row Column m tAH Row Column b Enable auto precharge Enable auto precharge Row tAS BA0, BA1 tAH Row Row Row tAH Bank 0 Bank 0 tDS tDH DIN DQ Bank 1 tDS tDH DIN tDS Bank 1 tDS tDH DIN tDH DIN tDS tDH DIN tWR - bank 0 tRCD - bank 0 Bank 0 tDS tDH DIN tDS tDH DIN tRP - bank 0 tDS tDH DIN tRCD - bank 0 tRAS - bank 0 tWR - bank 1 tRC - bank 0 tRCD - bank 1 tRRD Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 4. 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 31: WRITE – Continuous Page Burst T0 T1 T2 tCL CLK T3 T4 T5 (( )) (( )) tCK tCH tCKS tCKH Command tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH Address A10 (( )) (( )) NOP tAH NOP (( )) (( )) tAH Bank (( )) (( )) Bank tDS DIN DQ tDH tDS tDH tDS DIN tDH DIN tRCD tDS tDH DIN (( )) (( )) tDS All locations within same row tDH DIN Full-page burst does not self-terminate. Use BURST TERMINATE command to stop.1, 2 Full page completed Notes: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN BURST TERM (( )) (( )) Column m Row tAS BA0, BA1 tAH Row tAS Tn + 3 (( )) (( )) DQM tAS Tn + 2 (( )) (( )) CKE tCMS Tn + 1 Don’t Care 1. tWR must be satisfied prior to issuing a PRECHARGE command. 2. Page left open; no tRP. 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM WRITE Operation Figure 32: WRITE – DQM Operation T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP NOP T6 T7 NOP NOP tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE tCMS tCMH DQM tAS Address Row tAS A10 Column m tAH Enable auto precharge Row tAS BA0, BA1 tAH Disable auto precharge tAH Bank Bank tDS tDH tDS DIN DQ DIN tRCD Note: tDH tDS tDH DIN Don’t Care 1. For this example, BL = 4. Burst Read/Single Write The burst read/single write mode is entered by programming the write burst mode bit (M9) in the mode register to a 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation PRECHARGE Operation The PRECHARGE command (see Figure 10 (page 26)) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged (A10 = LOW), inputs BA0 and BA1 select the bank. When all banks are to be precharged (A10 = HIGH), inputs BA0 and BA1 are treated as “Don’t Care.” After a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Auto Precharge Auto precharge is a feature that performs the same individual-bank PRECHARGE function described previously, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the continuous page burst mode where auto precharge does not apply. In the specific case of write burst mode set to single location access with burst length set to continuous, the burst length setting is the overriding setting and auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. Another command cannot be issued to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Burst Type (page 37) section. Micron SDRAM supports concurrent auto precharge; cases of concurrent auto precharge for READs and WRITEs are defined below. READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS latency. The precharge to bank n begins when the READ to bank m is registered (see Figure 33 (page 59)). READ with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The precharge to bank n begins when the WRITE to bank m is registered (see Figure 34 (page 60)). WRITE with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CL later. The precharge to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (see Figure 39 (page 65)). WRITE with auto precharge interrupted by a WRITE (with or without auto precharge) A WRITE to bank m will interrupt a WRITE on bank n when registered. The precharge to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is reg- PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation istered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (see Figure 40 (page 65)). Figure 33: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Bank n Internal states NOP Page active READ - AP Bank n READ - AP Bank m NOP READ with burst of 4 NOP NOP NOP Interrupt burst, precharge Idle tRP - bank n Bank m Page active Address Bank n, Col a NOP tRP - bank m Precharge READ with burst of 4 Bank m, Col d DOUT DQ DOUT DOUT DOUT CL = 3 (bank n) CL = 3 (bank m) Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. DQM is LOW. 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 34: READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Internal States Bank n READ - AP Bank n Page active NOP NOP NOP READ with burst of 4 WRITE - AP Bank m NOP NOP Interrupt burst, precharge Idle tWR - bankm tRP - bank n Page active Bank m Address NOP Write-back WRITE with burst of 4 Bank n, Col a Bank m, Col d DQM1 DOUT DQ CL = 3 (bank n) Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN DIN DIN DIN Transitioning data DIN Don’t Care 1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4. 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 35: READ With Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP READ tCMS NOP tCMH DQM tAS Address Row tAS A10 Row Column m tAH Enable auto precharge Row tAS BA0, BA1 tAH Row tAH Bank Bank Bank tAC tOH tAC DQ tLZ tRCD DOUT m tAC tOH DOUT m+1 tAC tOH DOUT m+2 tRP CL = 2 tOH DOUT m+3 tHZ tRAS tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Undefined 1. For this example, BL = 4 and CL = 2. 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 36: READ Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKS tCKH CKE tCMS tCMH Command ACTIVE NOP READ NOP PRECHARGE tCMS tCMH DQM tAS Row Address tAS Row Column m tAH All banks Row A10 tAS BA0, BA1 tAH Row tAH Bank Disable auto precharge Single bank Bank Bank(s) tAC tOH tAC DQ tLZ tRCD DOUT tOH DOUT Bank tAC tAC tOH DOUT tRP CL = 2 tOH DOUT tHZ tRAS tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Undefined 1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRECHARGE. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 37: Single READ With Auto Precharge T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP T6 T7 tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP READ NOP NOP ACTIVE tCMS tCMH DQM tAS tAH tAS tAH Enable auto precharge Row Row A10 tAS BA0, BA1 Row Column m Row Address tAH Bank Bank Bank tAC DQ DOUT tLZ tRCD tRAS tOH tRP CL = 2 tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Undefined 1. For this example, BL = 1 and CL = 2. 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 38: Single READ Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 T5 NOP NOP T6 T7 T8 tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM tAS Address A10 Row Column m Row tAS tAH All banks Row Row tAS BA0, BA1 tAH Single bank Disable auto precharge tAH Bank Bank(s) Bank DQ tLZ tRCD DOUT tHZ CL = 2 tRP Don’t Care tRAS tRC Undefined Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Bank tOH tAC 1. For this example, BL = 1, CL = 2, and the READ burst is followed by a manual PRECHARGE. 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 39: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Bank n NOP Page active WRITE - AP Bank n READ - AP Bank m NOP NOP NOP Interrupt burst, write-back WRITE with burst of 4 Internal States Page active Address Bank n, Col a DIN DQ NOP Precharge tRP - bank n t WR - bank n Bank m NOP tRP - bank m READ with burst of 4 Bank m, Col d DIN DOUT DOUT CL = 3 (bank m) Don’t Care Note: 1. DQM is LOW. Figure 40: WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK Command Bank n Internal States NOP Page active WRITE - AP Bank n NOP NOP WRITE with burst of 4 WRITE - AP Bank m NOP Interrupt burst, write-back Address DQ Page active DIN Precharge tWR - bank m Write-back WRITE with burst of 4 Bank n, Col a NOP tRP - bank n tWR - bank n Bank m NOP Bank m, Col d DIN DIN DIN DIN DIN DIN Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. DQM is LOW. 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 41: WRITE With Auto Precharge T0 tCK CLK T1 tCL T2 T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE tCMS tCMH DQM tAS Address Row tAS A10 Row Column m tAH Enable auto precharge Row Row tAS BA0, BA1 tAH tAH Bank Bank Bank tDS tDH DIN DQ tDS tDH DIN tDS tDH DIN tDS tDH DIN tRCD tRAS tWR tRP tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 4. 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 42: WRITE Without Auto Precharge T0 tCK CLK T1 tCL T2 T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 PRECHARGE NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE tCMS tCMH DQM tAS Address Row tAS A10 Column m Row tAH All banks Row Row tAS BA0, BA1 tAH tAH Bank Disable auto precharge Single bank Bank Bank tDS tDH DIN DQ tDS tDH DIN tDS tDH DIN tDS Bank tDH DIN tRCD tRAS tWR tRP tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 4 and the WRITE burst is followed by a manual PRECHARGE. 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 43: Single WRITE With Auto Precharge T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 ACTIVE NOP tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE tCMS tCMH DQM tAS Address Row tAS A10 Row Column m tAH Enable auto precharge Row Row tAS BA0, BA1 tAH tAH Bank Bank Bank tDS tDH DIN DQ tRCD tRAS tRP tWR tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 1. 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM PRECHARGE Operation Figure 44: Single WRITE Without Auto Precharge T0 T1 tCK CLK T2 T3 T4 NOP NOP T5 T6 T7 T8 tCL tCH tCKS tCKH tCMS tCMH CKE Command ACTIVE NOP WRITE PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM tAS Row Address tAS Column m tAH All banks Row Row A10 tAS BA0, BA1 tAH tAH Bank Disable auto precharge Single bank Bank Bank tDS DIN DQ tRCD tRP tWR tRAS tRC Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN Bank tDH 1. For this example, BL = 1 and the WRITE burst is followed by a manual PRECHARGE. 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM AUTO REFRESH Operation AUTO REFRESH Operation The AUTO REFRESH command is used during normal operation of the device to refresh the contents of the array. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be precharged prior to issuing an AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP is met following the PRECHARGE command. Addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. After the AUTO REFRESH command is initiated, it must not be interrupted by any executable command until tRFC has been met. During tRFC time, COMMAND INHIBIT or NOP commands must be issued on each positive edge of the clock. The SDRAM requires that every row be refreshed each tREF period. Providing a distributed AUTO REFRESH command—calculated by dividing the refresh period (tREF) by the number of rows to be refreshed—meets the timing requirement and ensures that each row is refreshed. Alternatively, to satisfy the refresh requirement a burst refresh can be employed after every tREF period by issuing consecutive AUTO REFRESH commands for the number of rows to be refreshed at the minimum cycle rate (tRFC). PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 70 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM AUTO REFRESH Operation Figure 45: Auto Refresh Mode T0 CLK T1 tCK T2 (( )) (( )) tCH (( )) (( )) (( )) CKE Command Tn + 1 tCL tCKS tCKH tCMS tCMH PRECHARGE NOP AUTO REFRESH NOP (( )) ( ( NOP )) (( )) AUTO REFRESH NOP (( )) (( )) DQM Address All banks A10 Single bank tAS BA0, BA1 (( )) ( ( NOP )) ACTIVE (( )) (( )) (( )) (( )) (( )) (( )) Row (( )) (( )) (( )) (( )) Row (( )) (( )) (( )) (( )) Bank (( )) (( )) tAH Bank(s) DQ High-Z tRP tRFC tRFC Precharge all active banks Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN To + 1 Don’t Care 1. Back-to-back AUTO REFRESH commands are not required. 71 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM SELF REFRESH Operation SELF REFRESH Operation The self refresh mode can be used to retain data in the device, even when the rest of the system is powered down. When in self refresh mode, the device retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command, except CKE is disabled (LOW). After the SELF REFRESH command is registered, all the inputs to the device become “Don’t Care” with the exception of CKE, which must remain LOW. After self refresh mode is engaged, the device provides its own internal clocking, enabling it to perform its own AUTO REFRESH cycles. The device must remain in self refresh mode for a minimum period equal to tRAS and remains in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable prior to CKE going back HIGH. (Stable clock is defined as a signal cycling within timing constraints specified for the clock ball.) After CKE is HIGH, the device must have NOP commands issued for a minimum of two clocks for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued according to the distributed refresh rate (tREF/refresh row count) as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 72 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM SELF REFRESH Operation Figure 46: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS CKE Command tCKS tCKH tCMS tCMH PRECHARGE (( )) (( )) (( )) NOP AUTO REFRESH (( )) (( )) Tn + 1 (( )) (( )) (( )) )) (( )) (( )) Address (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) Single bank tAS BA0, BA1 DQ tAH Bank(s) High-Z tRP Precharge all active banks tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) CLK stable prior to exiting self refresh mode Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN AUTO REFRESH NOP ( ( (( )) (( )) All banks To + 2 (( )) (( )) DQM A10 To + 1 Don’t Care 1. Each AUTO REFRESH command performs a REFRESH cycle. Back-to-back commands are not required. 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Power-Down Power-Down Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device cannot remain in the power-down state longer than the refresh period (64ms) because no REFRESH operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT with CKE HIGH at the desired clock edge (meeting tCKS). Figure 47: Power-Down Mode T0 T1 tCK CLK T2 (( )) (( )) tCL tCH tCKS CKE tCKS Tn + 2 tCKS (( )) tCKH tCMS tCMH Command Tn + 1 NOP PRECHARGE (( )) (( )) NOP NOP ACTIVE DQM (( )) (( )) Address (( )) (( )) Row (( )) (( )) Row (( )) (( )) Bank All banks A10 Single bank tAS BA0, BA1 DQ tAH Bank(s) High-Z (( )) Two clock cycles Input buffers gated off All banks idle while in power-down mode Precharge all active banks All banks idle, enter power-down mode Exit power-down mode Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. Violating refresh requirements during power-down may result in a loss of data. 74 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Clock Suspend Clock Suspend The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, freezing the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input balls when an internal clock edge is suspended will be ignored; any data present on the DQ balls remains driven; and burst counters are not incremented, as long as the clock is suspended. Exit clock suspend mode by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. Figure 48: Clock Suspend During WRITE Burst T0 T1 NOP WRITE T2 T3 T4 T5 NOP NOP DIN DIN CLK CKE Internal clock Command Address DIN Bank, Col n DIN Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, BL = 4 or greater, and DQM is LOW. 75 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Clock Suspend Figure 49: Clock Suspend During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE Internal clock Command READ Address Bank, Col n DQ NOP NOP NOP DOUT DOUT NOP DOUT NOP DOUT Don’t Care Note: PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW. 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved. 512Mb: x4, x8, x16 SDRAM Clock Suspend Figure 50: Clock Suspend Mode T0 T1 tCK CLK T2 T3 T4 T5 T6 T7 T8 T9 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS Command tCMH READ NOP NOP NOP NOP NOP WRITE NOP tCMS tCMH DQM tAS Address tAH Column e Column m tAS tAH tAS tAH A10 BA0, BA1 Bank Bank tAC tOH tAC DQ tLZ tHZ DOUT DOUT tDS tDH DIN DIN Don’t Care Note: Undefined 1. For this example, BL = 2, CL = 3, and auto precharge is disabled. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef809bf8f3 512Mb_sdr.pdf - Rev. R 05/15 EN 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2000 Micron Technology, Inc. All rights reserved.
MT48LC128M4A2TG-7E:C
物料型号: - MT48LC128M4A2:32 Meg x 4 x 4 banks - MT48LC64M8A2:16 Meg x 8 x 4 banks - MT48LC32M16A2:8 Meg x 16 x 4 banks

器件简介: Micron的512Mb SDRAM是一种高速CMOS动态随机存取存储器,包含536,870,912位。它内部配置为具有同步接口的四银行DRAM(所有信号都在时钟信号CLK的正边上注册)。

引脚分配: - CLK:系统时钟输入 - CKE:时钟使能输入 - CS#:芯片选择输入 - RAS#, CAS#, WE#:命令输入 - BA[1:0]:银行地址输入 - A[12:0]:地址输入 - DQ[15:0](或DQ[7:0]或DQ[3:0]):数据输入/输出

参数特性: - PC100和PC133兼容 - 完全同步;所有信号在正面时钟信号上注册 - 内部流水线操作;列地址可以每个时钟周期改变一次 - 可编程突发长度:1, 2, 4, 8, 或全页 - 自动预充电,包括同时自动预充电 - 自刷新模式

功能详解: - 512Mb SDRAM使用内部流水线架构实现高速操作,与2n规则的预取架构兼容,但也允许在每个时钟周期改变列地址以实现高速、完全随机访问。 - 通过在一个银行预充电的同时访问其他三个银行之一,可以隐藏预充电周期,并提供无缝的高速随机访问操作。

应用信息: - 设计用于3.3V内存系统 - 提供自动刷新模式和节能的电源下降模式 - 所有输入和输出都与LVTTL兼容

封装信息: - 54-pin TSOP II封装
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