288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Features
CIO RLDRAM® 2
MT49H32M9 – 32 Meg x 9 x 8 Banks
MT49H16M18 – 16 Meg x 18 x 8 Banks
MT49H8M36 – 8 Meg x 36 x 8 Banks
Features
Options1
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
– 32 Meg x 9, 16 Meg x 18, and 8 Meg x 36
• 8 internal banks for concurrent operation and
maximum bandwidth
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to
optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
• 144-ball µBGA package
• HSTL I/O (1.5V or 1.8V nominal)
• 25–60 matched impedance outputs
• 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
• On-die termination (ODT) RTT
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D1.fm - Rev. O 10/12 EN
Marking
• Clock cycle timing
– 1.875ns @ tRC = 15ns
-18
t
– 2.5ns @ RC = 15ns
-25E
t
– 2.5ns @ RC = 20ns
-25
t
– 3.3ns @ RC = 20ns
-33
– 5.0ns @ tRC = 20ns
-5
• Configuration
– 32 Meg x 9
32M9
– 16 Meg x 18
16M18
– 8 Meg x 36
8M36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
None
IT
• Package
– 144-ball µBGA
FM
– 144-ball µBGA (Pb-free)
BM
• Revision
:B
Notes: 1. Not all options listed can be combined to
define an offered product. Use the part catalog search on www.micron.com for available
offerings.
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Features
Figure 1:
288Mb RLDRAM 2 CIO Part Numbers
Example Part Number: MT 4 9 H1 6 M1 8 FM-2 5 :B
Configuration I/O Package
MT49H
:
Speed Temp
Revision
I/O
Common None
Configuration
Separate
Rev.
C
Rev. A
None
Rev. B
:B
32 Meg x 9
32M9
16 Meg x 18
16M18
Temperature
8 Meg x 36
8M36
Commercial
Industrial
Package
144-ball µBGA
FM
Speed Grade
144-ball µBGA (Pb-free)
BM
-18
None
IT
tCK = 1.875ns
-25E tCK = 2.5ns
-25
tCK = 2.5ns
-33
tCK = 3.3ns
-5
tCK = 5ns
BGA Part Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking
that is different from the part number. Micron’s BGA Part Marking Decoder is available
on Micron’s Web site at micron.com.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D1.fm - Rev. O 10/12 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
BGA Part Marking Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Ball Assignments and Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Electrical Specifications – IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Electrical Specifications – AC and DC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
AC and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input Slew Rate Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Temperature and Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
MODE REGISTER SET (MRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AUTO REFRESH (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Disabling the JTAG Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Test Access Port (TAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
TAP Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_CIOTOC.fm - Rev. O 10/12 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Figure 27:
Figure 28:
Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
Figure 41:
Figure 42:
Figure 43:
Figure 44:
Figure 45:
288Mb RLDRAM 2 CIO Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
32 Meg x 9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
16 Meg x 18 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
8 Meg x 36 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Example Temperature Test Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Mode Register Definition in Nonmultiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Read Burst Lengths. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
WRITE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
READ Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Power-Up/Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Power-Up/Initialization Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Consecutive WRITE-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
WRITE-to-READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
WRITE-to-READ (Separated by Two NOPs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
WRITE – DM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Consecutive READ Bursts (BL = 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Consecutive READ Bursts (BL = 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
READ-to-WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Read Data Valid Window for x9 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Read Data Valid Window for x18 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Read Data Valid Window for x36 Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
READ Burst with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
READ-NOP-READ with ODT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Command Description in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Power-Up/Initialization Sequence in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Mode Register Definition in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
BURST REFRESH Operation with Multiplexed Addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Consecutive WRITE Bursts with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
WRITE-to-READ with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Consecutive READ Bursts with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
READ-to-WRITE with Multiplexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
TAP Controller Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
JTAG Operation – Loading Instruction Code and Shifting Out Data. . . . . . . . . . . . . . . . . . . . . . . . . . . .73
TAP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
RLDRAM_CIOLOF.fm - 10/12 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
© Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
32 Meg x 9 Ball Assignments (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
8 Meg x 36 Ball Assignments (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IDD Operating Conditions and Maximum Limits – Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
IDD Operating Conditions and Maximum Limits – Rev. B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Differential Input Clock Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Address and Command Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Data Setup and Hold Derating Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Capacitance – µBGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
AC Electrical Characteristics: -18, -25E, -25, -33, -5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Temperature Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Thermal Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Cycle Time and READ/WRITE Latency Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Address Widths at Different Burst Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
On-Die Termination DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
288Mb Address Mapping in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode . . . . . . . . . . . . . .63
TAP Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_CIOLOT.fm - Rev. O 10/12 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
General Description
General Description
The Micron® reduced latency DRAM (RLDRAM®) 2 is a high-speed memory device
designed for high bandwidth data storage—telecommunications, networking, and
cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high
speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative edges
of the input data clock(s).
Read and write accesses to the RLDRAM are burst-oriented. The burst length (BL) is
programmable from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The µBGA 144-ball package is used to enable ultra high-speed data transfer rates and a
simple upgrade path from early generation devices.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
State Diagram
State Diagram
Figure 2:
Simplified State Diagram
Initialization
sequence
DSEL/NOP
WRITE
READ
MRS
AREF
Automatic sequence
Command sequence
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
Functional Block Diagrams
Figure 3: 32 Meg x 9 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Control
logic
WE#
VTT
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
13
Rowaddress
MUX
18
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 16 x 9)2
DLL
ZQ CAL
144
8
SENSEamplifiers
AMPLIFIERS
Sense
READ n
logic
n
9
9
(0 ....8)
9
Drivers
DQ
latch
QVLD
QK0/QK0#
2
QK/QK#
generator
8,192
144
DQ0–DQ8
BA0–BA2
24
Address
register
Bank
control
logic
3
31
I/O gating
DQM mask logic
8
8
32
144
5
8
81
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO n
and
drivers n
DK/DK#
2
9
Input
logic
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
A0–A201
9
RCVRS
9
CLK
in
VTT
81
RTT
31
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “16” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
State Diagram
Command
decode
CS#
REF#
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
CS#
Command
decode
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
Figure 4: 16 Meg x 18 Functional Block Diagram
REF#
WE#
Control
logic
VTT
13
Rowaddress
MUX
18
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 8 x 18)2
(0 ....17)
DLL
ZQ CAL
18
144
Sense
SENSEamplifiers
AMPLIFIERS
READ n
logic
n
18
18
Drivers
DQ
latch
4
QVLD
QK0–QK1/
QK0#–QK1#
QK/QK#
generator
8,192
144
9
DQ0–DQ17
23
Bank
control
logic
Address
register
3
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
144
5
8
71
Columnaddress
counter/
latch
DK/DK#
2
32
Column
decoder
WRITE
FIFO
and
drivers
n
n
18
Input
logic
A0–A191
BA0–BA2
21
I/O gating
DQM mask logic
18
18
RCVRS
VTT
CLK
in
71
RTT
21
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “8” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
State Diagram
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
CS#
Control
logic
Command
decode
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
Figure 5: 8 Meg x 36 Functional Block Diagram
REF#
WE#
VTT
18
13
Rowaddress
MUX
13
13
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
8,192
Bank 0
memory
array
(8,192 x 32 x 4 x 36)2
DLL
ZQ CAL
144
READ n
logic
n
36
36
DQ
latch
(0 ....35)
36
Drivers
SENSE
AMPLIFIERS
Sense amplifiers
4
QVLD
QK0–QK1/
QK0#–QK1#
QK/QK#
generator
8,192
10
144
DQ0–DQ35
22
Address
register
Bank
control
logic
3
8
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
32
144
5
8
61
Columnaddress
counter/
latch
WRITE
FIFO
and
drivers
CLK
in
Column
decoder
DK0–DK1/
DK0#–DK1#
4
n
n
36
36
Input
logic
A0–A181
BA0–BA2
11
I/O gating
DQM mask logic
36
RCVRS
VTT
61
RTT
11
ODT control
DM
Notes:
1. Examples for BL = 2; column address will be reduced with an increase in burst length.
2. The “4” = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
State Diagram
Mode register
Refresh
counter
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
32 Meg x 9 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A221
A212
A5
A8
B2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
DNU4
DNU4
DNU4
ZQ
VEXT
DNU4
DNU4
DNU4
DNU4
DNU4
A7
VSS
VDD
VDD
VSS
A17
DNU4
DNU4
DNU4
DNU4
DNU4
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ4
DQ5
DQ6
DQ7
DQ8
VEXT
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
B0
B1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
TCK
VDD
VTT
VSS
A20
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This signal is not connected.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This
may optionally be connected to GND. Note that if ODT is enabled on Rev. A die, these pins
will be connected to VTT. The DNU pins are High-Z on Rev. B die when ODT is enabled.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Ball Assignments and Descriptions
Table 2:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
16 Meg x 18 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A221
A212
A5
A8
B2
NF3
DK
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DNU4
DNU4
DNU4
DNU4
DNU4
A6
A9
NF3
DK#
CS#
A16
DNU4
DNU4
QK1
DNU4
DNU4
ZQ
VEXT
DQ4
DQ5
DQ6
DQ7
DQ8
A7
VSS
VDD
VDD
VSS
A17
DQ14
DQ15
QK1#
DQ16
DQ17
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ0
DQ1
QK0#
DQ2
DQ3
A2
VSS
VDD
VDD
VSS
A12
DQ9
DQ10
DQ11
DQ12
DQ13
VEXT
TMS
DNU4
DNU4
QK0
DNU4
DNU4
A1
A4
B0
B1
A14
A11
DNU4
DNU4
DNU4
DNU4
DNU4
TDO
TCK
VDD
VTT
VSS
A202
QVLD
A0
A3
CK
CK#
A13
A10
A19
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal. This may optionally be connected to GND.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This
may optionally be connected to GND. Note that if ODT is enabled on Rev. A die, these pins
will be connected to VTT. The DNU pins are High-Z on Rev. B die when ODT is enabled.
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Ball Assignments and Descriptions
Table 3:
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
8 Meg x 36 Ball Assignments (Top View) 144-Ball µBGA
1
2
3
4
VREF
VDD
VTT
A22
A212
A5
A8
B2
DK0
DK1
REF#
WE#
A18
A15
VSS
VTT
VDD
VREF
VSS
DQ8
DQ10
DQ12
DQ14
DQ16
A6
A9
DK0#
DK1#
CS#
A16
DQ24
DQ22
QK1
DQ20
DQ18
ZQ
VEXT
DQ9
DQ11
DQ13
DQ15
DQ17
A7
VSS
VDD
VDD
VSS
A17
DQ25
DQ23
QK1#
DQ21
DQ19
VEXT
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
5
6
7
8
9
10
11
12
VSS
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
VSS
VDD
VDD
VSS
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VSS
VEXT
DQ1
DQ3
QK0#
DQ5
DQ7
A2
VSS
VDD
VDD
VSS
A12
DQ35
DQ33
DQ31
DQ29
DQ27
VEXT
TMS
DQ0
DQ2
QK0
DQ4
DQ6
A1
A4
B0
B1
A14
A11
DQ34
DQ32
DQ30
DQ28
DQ26
TDO
TCK
VDD
VTT
VSS
A202
QVLD
A0
A3
CK
CK#
A13
A10
A192
DM
VSS
VTT
VDD
TDI
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics
of an address input signal. This may optionally be connected to GND.
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Ball Assignments and Descriptions
Table 4:
Ball Descriptions
Symbol
Type
A0–A20
Input
BA0–BA2
CK, CK#
CS#
DK, DK#
DM
TCK
TMS, TDI
WE#, REF#
DQ0–DQ35
ZQ
QKx, QKx#
QVLD
TDO
VDD
VDDQ
VEXT
VREF
VSS
VSSQ
VTT
A21
A22
Description
Address inputs: A0–A20 define the row and column addresses for READ and WRITE operations.
During a MODE REGISTER SET, the address inputs define the register settings. They are sampled
at the rising edge of CK.
Input
Bank address inputs: Select to which internal bank a command is being applied.
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on
the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Input
Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When
the command decoder is disabled, new commands are ignored, but internal operations continue.
Input
Input data clock: DK and DK# are the differential input data clocks. All input data is referenced
to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0–
DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the
x9 and x18 devices, all DQs are referenced to DK and DK#. All DKx and DKx# pins must always be
supplied to the device.
Input
Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked
when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for the x36 configuration).
Tie signal to ground if not used.
Input
IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used.
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used.
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with
CS#) the command to be executed.
I/O
Data input: The DQ signals form the 36-bit data bus. During READ commands, the data is
referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of
DK.
Reference External impedance (25–60): This signal is used to tune the device outputs to the system
data bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this
signal to ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ
to VDD invokes the maximum impedance mode. Refer to the Mode Register Definition in
Nonmultiplexed Address Mode figure to activate this function.
Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are freerunning, and during READs, are edge-aligned with data output from the RLDRAM. QKx# is
ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with
DQ0–DQ17, and QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0#
are aligned with DQ0–DQ8, while QK1 and QK1# are aligned with Q9–Q17. For the x9 device, all
DQs are aligned with QK0 and QK0#.
Output Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx and QKx#.
Output IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG function
is not used.
Supply
Power supply: Nominally, 1.8V. See Table 8 on page 20 for range.
Supply
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity.
See Table 8 on page 20 for range.
Supply
Power supply: Nominally, 2.5V. See Table 8 on page 20 for range.
Supply
Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers.
Supply
Ground.
Supply
DQ ground: Isolated on the device for improved noise immunity.
Supply
Power supply: Isolated termination supply. Nominally, VDDQ/2. See Table 8 on page 20 for
range.
–
Reserved for future use: This signal is internally connected and can be treated as an address
input.
–
Reserved for future use: This signal is not connected and can be connected to ground.
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288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
14
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Ball Assignments and Descriptions
Table 4:
Ball Descriptions (continued)
Symbol
Type
Description
DNU
–
NF
–
Do not use: These balls may be connected to ground. Note that if ODT is enabled on Rev. A die,
these pins will be connected to VTT. The DNU pins are High-Z on Rev. B die when ODT is enabled.
No function: These balls can be connected to ground.
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15
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Package Dimensions
Package Dimensions
Figure 6:
144-Ball µBGA
10.6 CTR
10º TYP
Seating
plane
0.12 A
A
144X Ø0.51
Solder ball material:
Eutectic (62% Sn,
36% Pb, 2% Ag) or
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Dimensions apply to
solder balls post-reflow
on Ø0.39 SMD
ball pads.
0.73 ±0.1
0.49 ±0.05
12 11 10 9
Ball A1 ID
4 3 2 1
Ball A1 ID
A
B
C
D
E
F
G
H
J
17 CTR
K
18.5 ±0.1
18.1 CTR
L
M
N
P
R
T
U
1 TYP
V
0.8 TYP
1.2 MAX
0.34 MIN
8.8 CTR
11 ±0.1
Notes:
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288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
1. All dimensions are in millimeters.
16
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288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Electrical Specifications – IDD
Electrical Specifications – IDD
Table 5:
IDD Operating Conditions and Maximum Limits – Rev. A
Notes appear on page 19
Description
Condition
Standby current
t
Active standby
current
CS# = 1; No commands; Bank address
incremented and half address/data change
once every 4 clock cycles
Operational
current
BL = 2; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
continuous data during WRITE commands
BL = 4; Sequential bank access; Bank transitions
once every tRC; Half address transitions once
every tRC; Read followed by write sequence;
Continuous data during WRITE commands
BL = 8; Sequential bank access; Bank transitions
once every tRC; half address transitions once
every tRC; Read followed by write sequence;
continuous data during WRITE commands
Eight-bank cyclic refresh; Continuous address/
data; Command bus remains in refresh for all
eight banks
Operational
current
Operational
current
Burst refresh
current
CK = idle; All banks idle; No inputs toggling
Distributed
refresh current
Single-bank refresh; Sequential bank access;
Half address transitions once every tRC,
continuous data
Operating burst
write current
example
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Continuous data;
measurement is taken during continuous
WRITE
Operating burst
write current
example
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Continuous data;
Measurement is taken during continuous
WRITE
Operating burst
write current
example
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; continuous data;
Measurement is taken during continuous
WRITE
Operating burst
read current
example
BL = 2; Cyclic bank access; Half of address bits
change every clock cycle; Measurement is taken
during continuous READ
Operating burst
read current
example
BL = 4; Cyclic bank access; Half of address bits
change every 2 clock cycles; Measurement is
taken during continuous READ
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288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
17
Symbol
-25
-33
-5
Units
ISB1 (VDD) x9/x18
ISB1 (VDD) x36
ISB1 (VEXT)
ISB2 (VDD) x9/x18
ISB2 (VDD) x36
ISB2 (VEXT)
IDD1 (VDD) x9/x18
IDD1 (VDD) x36
IDD1 (VEXT)
48
48
26
288
288
26
348
374
41
48
48
26
233
233
26
305
343
36
48
48
26
189
189
26
255
292
36
mA
IDD2 (VDD) x9/x18
IDD2 (VDD) x36
IDD2 (VEXT)
362
418
48
319
389
42
269
339
42
mA
IDD3 (VDD) x9/x18
IDD3 (VDD) x36
IDD3 (VEXT)
408
n/a
55
368
n/a
48
286
n/a
48
mA
IREF1 (VDD) x9/x18
IREF1 (VDD) x36
IREF1 (VEXT)
IREF2 (VDD) x9/x18
IREF2 (VDD) x36
IREF2 (VEXT)
IDD2W (VDD)
x9/x18
IDD2W (VDD) x36
IDD2W (VEXT)
IDD4W (VDD)
x9/x18
IDD4W (VDD) X36
IDD4W (VEXT)
IDD8W (VDD)
x9/x18
IDD8W (VDD) x36
IDD8W (VEXT)
IDD2R (VDD) x9/x18
IDD2R (VDD) x36
IDD2R (VEXT)
IDD4R (VDD) x9/x18
IDD4R (VDD) x36
IDD4R (VEXT)
785
785
133
325
326
48
970
615
615
111
267
281
42
819
430
430
105
221
227
42
597
mA
990
100
779
914
90
609
676
69
439
mA
882
88
668
790
77
525
567
63
364
mA
n/a
60
860
880
100
680
730
88
n/a
51
735
795
90
525
660
77
n/a
40
525
565
69
380
455
63
mA
mA
mA
mA
mA
mA
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Electrical Specifications – IDD
Table 5:
IDD Operating Conditions and Maximum Limits – Rev. A
Notes appear on page 19
Description
Operating burst
read current
example
Table 6:
Condition
BL = 8; Cyclic bank access; Half of address bits
change every 4 clock cycles; Measurement is
taken during continuous READ
Symbol
-25
-33
-5
Units
IDD8R (VDD) x9/x18
IDD8R (VDD) x36
IDD8R (VEXT)
570
n/a
60
450
n/a
51
310
n/a
40
mA
IDD Operating Conditions and Maximum Limits – Rev. B
Notes appear on page 19
Description
Condition
Standby current tCK = idle; All banks idle; No inputs
toggling
Active standby
current
CS# = 1; No commands; Bank address
incremented and half address/data
change once every 4 clock cycles
Operational
current
BL = 2; Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by write sequence; continuous data
during WRITE commands
BL = 4; Sequential bank access; Bank
transitions once every tRC; Half address
transitions once every tRC; Read followed
by write sequence; Continuous data
during WRITE commands
BL = 8; Sequential bank access; Bank
transitions once every tRC; half address
transitions once every tRC; Read followed
by write sequence; continuous data
during WRITE commands
Eight-bank cyclic refresh; Continuous
address/data; Command bus remains in
refresh for all eight banks
Operational
current
Operational
current
Burst refresh
current
Distributed
refresh current
Single-bank refresh; Sequential bank
access; Half address transitions once
every tRC, continuous data
Operating burst BL = 2; Cyclic bank access; Half of address
write current
bits change every clock cycle; Continuous
example
data; measurement is taken during
continuous WRITE
Operating burst BL = 4; Cyclic bank access; Half of address
write current
bits change every 2 clock cycles;
example
Continuous data; Measurement is taken
during continuous WRITE
Operating burst BL = 8; Cyclic bank access; Half of address
write current
bits change every 4 clock cycles;
example
continuous data; Measurement is taken
during continuous WRITE
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288Mb_RLDRAM_2_CIO_D2.fm - Rev. O 10/12 EN
Symbol
-18
-25E
-25
-33
Units
ISB1 (VDD) x9/x18
ISB1 (VDD) x36
ISB1 (VEXT)
ISB2 (VDD) x9/x18
ISB2 (VDD) x36
ISB2 (VEXT)
IDD1 (VDD) x9/x18
IDD1 (VDD) x36
IDD1 (VEXT)
55
55
5
250
250
5
310
320
10
55
55
5
215
215
5
285
295
10
55
55
5
215
215
5
260
270
10
55
55
5
190
190
5
225
230
10
mA
IDD2 (VDD) x9/x18
IDD2 (VDD) x36
IDD2 (VEXT)
315
330
10
290
305
10
260
275
10
220
230
10
mA
IDD3 (VDD) x9/x18
IDD3 (VDD) x36
IDD3 (VEXT)
330
390
15
305
365
15
275
320
15
230
265
15
mA
IREF1 (VDD) x9/x18
IREF1 (VDD) x36
IREF1 (VEXT)
IREF2 (VDD) x9/x18
IREF2 (VDD) x36
IREF2 (VEXT)
IDD2W (VDD)
x9/x18
IDD2W (VDD) x36
IDD2W (VEXT)
IDD4W (VDD)
x9/x18
IDD4W (VDD) X36
IDD4W (VEXT)
IDD8W (VDD)
x9/x18
IDD8W (VDD) x36
IDD8W (VEXT)
660
670
45
295
295
10
830
540
545
30
265
265
10
655
530
535
30
250
250
10
655
430
435
25
215
215
10
530
mA
885
40
580
700
35
465
700
35
465
565
30
385
mA
635
25
445
510
20
370
510
20
370
420
20
305
mA
560
25
455
20
455
20
375
20
18
mA
mA
mA
mA
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Electrical Specifications – IDD
Table 6:
IDD Operating Conditions and Maximum Limits – Rev. B (continued)
Notes appear on page 19
Description
Condition
Operating burst BL = 2; Cyclic bank access; Half of address
read current
bits change every clock cycle;
example
Measurement is taken during continuous
READ
Operating burst BL = 4; Cyclic bank access; Half of address
read current
bits change every 2 clock cycles;
example
Measurement is taken during continuous
READ
Operating burst BL = 8; Cyclic bank access; Half of address
read current
bits change every 4 clock cycles;
example
Measurement is taken during continuous
READ
Notes:
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Symbol
-18
-25E
-25
-33
Units
IDD2R (VDD) x9/x18
IDD2R (VDD) x36
IDD2R (VEXT)
805
850
40
640
675
35
640
675
35
515
540
30
mA
IDD4R (VDD) x9/x18
IDD4R (VDD) x36
IDD4R (VEXT)
545
590
25
440
475
20
440
475
20
365
390
20
mA
IDD8R (VDD) x9/x18
IDD8R (VDD) x36
IDD8R (VEXT)
410
525
25
335
425
20
335
425
20
280
350
20
mA
1. IDD specifications are tested after the device is properly initialized. +0°C TC +95°C; +1.7V
VDD +1.9V, +2.38V VEXT +2.63V, +1.4V VDDQ VDD, VREF = VDDQ/2.
2. tCK = tDK = MIN, tRC = MIN.
3. Input slew rate is specified in Table 9 on page 21.
4. Definitions for IDD conditions:
4a. LOW is defined as VIN VIL(AC) MAX.
4b. HIGH is defined as VIN VIH(AC) MIN.
4c. Stable is defined as inputs remaining at a HIGH or LOW level.
4d. Floating is defined as inputs at VREF = VDDQ/2.
4e. Continuous data is defined as half the DQ signals changing between HIGH and LOW
every half clock cycle (twice per clock).
4f. Continuous address is defined as half the address signals changing between HIGH and
LOW every clock cycle (once per clock).
4g. Sequential bank access is defined as the bank address incrementing by one every tRC.
4h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 2 this is every clock, for BL = 4 this is every other clock, and for
BL = 8 this is every fourth clock.
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
6. IDD parameters are specified with ODT disabled.
7. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are
tested for the full voltage range specified.
8. IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing
is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications
are tested for the specified AC input levels under normal use conditions. The minimum slew
rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and
VIH(AC).
19
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Electrical Specifications – AC and DC
Electrical Specifications – AC and DC
Absolute Maximum Ratings
Stresses greater than those listed in Table 7 may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Table 7:
Absolute Maximum Ratings
Parameter
Min
Max
Units
I/O voltage
Voltage on VEXT supply relative to VSS
Voltage on VDD supply relative to VSS
Voltage on VDDQ supply relative to VSS
–0.3
–0.3
–0.3
–0.3
VDDQ + 0.3
+2.8
+2.1
+2.1
V
V
V
V
AC and DC Operating Conditions
Table 8:
DC Electrical Characteristics and Operating Conditions
Note 1 applies to the entire table; Unless otherwise noted: +0°C TC +95°C; +1.7V VDD +1.9V
Description
Conditions
Symbol
Supply voltage
Supply voltage
Isolated output buffer supply
Reference voltage
Termination voltage
Input high (logic 1) voltage
Input low (logic 0) voltage
Output high current
–
–
–
–
–
–
–
VOH = VDDQ/2
VEXT
VDD
VDDQ
VREF
VTT
VIH
VIL
IOH
Output low current
VOL = VDDQ/2
IOL
0V VIN VDD
0V VIN VDD
0V VIN VDDQ
–
ILC
ILI
ILO
IREF
Clock input leakage current
Input leakage current
Output leakage current
Reference voltage current
Notes:
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Min
Max
2.38
2.63
1.7
1.9
1.4
VDD
0.49 × VDDQ 0.51 × VDDQ
0.95 × VREF
1.05 × VREF
VREF + 0.1
VDDQ + 0.3
VSSQ - 0.3
VREF - 0.1
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
(VDDQ/2)/
(VDDQ/2)/
(1.15 × RQ/5) (0.85 × RQ/5)
–5
5
–5
5
–5
5
–5
5
Units
Notes
V
V
V
V
V
V
V
A
2
2, 3
4, 5, 6
7, 8
2
2
9, 10, 11
A
9, 10, 11
µA
µA
µA
µA
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) VDD + 0.7V for t tCK/2. Undershoot: VIL(AC) –0.5V for t tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse
widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
5. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC
level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2% of
the DC value. Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error and an additional
±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor.
20
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Electrical Specifications – AC and DC
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using mode register bit 9 (see the Mode Register Definition in Nonmultiplexed Address Mode figure). A resistance RTT from each data input signal to the nearest VTT can be enabled.
RTT = 125–185 at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the
device, IOL flows into the device.
10. If MRS bit A8 is 0, use RQ = 250 in the equation in lieu of presence of an external impedance matched resistor.
11. For VOL and VOH, refer to the RLDRAM 2 HSPICE or IBIS driver models.
Table 9:
Input AC Logic Levels
Notes 1–3 apply to entire table; Unless otherwise noted: +0°C TC +95°C; +1.7V VDD +1.9V
Description
Input high (logic 1) voltage
Input low (logic 0) voltage
Notes:
Symbol
Min
Max
Units
VIH
VIL
VREF + 0.2
–
–
VREF - 0.2
V
V
1. All voltages referenced to VSS (GND).
2. The AC and DC input level specifications are as defined in the HSTL standard (that is, the
receiver will effectively switch as a result of the signal crossing the AC input level, and will
remain in that state as long as the signal does not ring back above [below] the DC input
LOW [HIGH] level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range
between VIL(AC) and VIH(AC). See illustration below:
VDDQ
VIH(AC) MIN
VSWING
VIL(AC) MAX
GND
Rise time:
2 V/ns
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Fall time:
2 V/ns
21
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Electrical Specifications – AC and DC
Table 10:
Differential Input Clock Operating Conditions
Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C TC +95°C; +1.7V VDD +1.9V
Parameter/Condition
Clock input voltage level: CK and CK#
Clock input differential voltage: CK and CK#
Clock input differential voltage: CK and CK#
Clock input crossing point voltage: CK and CK#
Notes:
Figure 7:
Symbol
Min
Max
Units
Notes
VIN(DC)
VID(DC)
VID(AC)
VIX(AC)
–0.3
0.2
0.4
VDDQ/2 - 0.15
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
VDDQ/2 + 0.15
V
V
V
V
5
5
6
1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS (GND).
3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK
and CK# cross. The input reference level for signals other than CK/CK# is VREF.
4. CK and CK# input slew rate must be 2 V/ns (4 V/ns if measured differentially).
5. VID is the magnitude of the difference between the input level on CK and the input level on
CK#.
6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same.
Clock Input
VIN(DC) MAX
Maximum clock level
CK#
X
VDDQ/2 + 0.15
VIX(AC) MAX
VDDQ/2
VDDQ/2A - 0.15
1
X
VID(DC)2
VID(AC)3
VIX(AC) MIN
CK
Minimum clock level
VIN(DC) MIN
Notes:
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1.
2.
3.
4.
CK and CK# must cross within this region.
CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2.
Minimum peak-to-peak swing.
It is a violation to tristate CK and CK# after the part is initialized.
22
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Electrical Specifications – AC and DC
Input Slew Rate Derating
Table 11 on page 24 and Table 12 on page 25 define the address, command, and data
setup and hold derating values. These values are added to the default tAS/tCS/tDS and
tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than
the 2 V/ns the nominal setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS
default specification to the “tAS/tCS VREF to CK/CK# Crossing” and the tAH/tCH default
specification to the “tAH/tCH CK/CK# Crossing to VREF ” derated values on Table 11. The
derated data setup and hold values can be determined in a like manner using the “tDS
VREF to CK/CK# Crossing” and “tDH to CK/CK# Crossing to VREF ” values on Table 12.
The derating values on Table 11 and Table 12 apply to all speed grades.
The setup times on Table 11 and Table 12 represent a rising signal. In this case, the time
from which the rising signal crosses VIH(AC) MIN to the CK/CK# cross point is static and
must be maintained across all slew rates. The derated setup timing represents the point
at which the rising signal crosses VREF(DC) to the CK/CK# cross point. This derated value
is calculated by determining the time needed to maintain the given slew rate and the
delta between VIH(AC) MIN and the CK/CK# cross point. The setup values in Table 11 and
Table 12 are also valid for falling signals (with respect to VIL[AC] MAX and the CK/CK#
cross point).
The hold times in Table 11 and Table 12 represent falling signals. In this case, the time
from the CK/CK# cross point to when the signal crosses VIH(DC) MIN is static and must
be maintained across all slew rates. The derated hold timing represents the delta
between the CK/CK# cross point to when the falling signal crosses VREF(DC). This derated
value is calculated by determining the time needed to maintain the given slew rate and
the delta between the CK/CK# cross point and VIH(DC). The hold values in Table 11 and
Table 12 are also valid for rising signals (with respect to VIL[DC] MAX and the CK and
CK# cross point).
Note:
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The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
23
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Electrical Specifications – AC and DC
Table 11:
Address and Command Setup and Hold Derating Values
t
Command/
Address Slew
Rate (V/ns)
AS/ CS VREF to
CK/CK# Crossing
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
11
18
25
33
43
54
67
82
100
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
41
48
55
63
73
84
97
112
130
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
71
78
85
93
103
114
127
142
160
t
t
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AS/tCS VIH(AC)
MIN to CK/CK#
Crossing
t
t
t
AH/ CH CK/CK#
Crossing to VREF
CK, CK# Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
CK, CK# Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
CK, CK# Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
24
AH/tCH CK/CK#
Crossing to
VIH(DC) MIN
Units
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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Electrical Specifications – AC and DC
Table 12:
Data Setup and Hold Derating Values
t
t
Data Slew Rate
(V/ns)
DS VREF to
CK/CK# Crossing
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0
5
11
18
25
33
43
54
67
82
100
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
30
35
41
48
55
63
73
84
97
112
130
2.0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
60
65
71
78
85
93
103
114
127
142
160
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t
DS VIH(AC) MIN to
CK/CK# Crossing
t
DH CK/CK#
Crossing to VREF
DK, DK# Differential Slew Rate: 2.0 V/ns
–100
0
–100
3
–100
6
–100
9
–100
13
–100
17
–100
22
–100
27
–100
34
–100
41
–100
50
DK, DK# Differential Slew Rate: 1.5 V/ns
–70
30
–70
33
–70
36
–70
39
–70
43
–70
47
–70
52
–70
57
–70
64
–70
71
–70
80
DK, DK# Differential Slew Rate: 1.0 V/ns
–40
60
–40
63
–40
66
–40
69
–40
73
–40
77
–40
82
–40
87
–40
94
–40
101
–40
110
25
DH CK/CK#
Crossing to
VIH(DC) MIN
Units
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
–50
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
–20
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
10
10
10
10
10
10
10
10
10
10
10
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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Electrical Specifications – AC and DC
Figure 8:
Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate
VIH(AC) MIN
VREF to DC VREF to DC
region
region
VSWING (MAX)
VREF to AC
region
VREF to AC
region
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
Table 13:
Capacitance – µBGA
Notes 1–2 apply to entire table
Description
Address/control input capacitance
Input/output capacitance (DQ, DM, and QK/QK#)
Clock capacitance (CK/CK#, and DK/DK#)
JTAG pins
Notes:
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Symbol
Conditions
Min
Max
Units
CI
CO
CCK
CJTAG
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
1.0
3.0
1.5
1.5
2.0
4.5
2.5
4.5
pF
pF
pF
pF
1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
26
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Electrical Specifications – AC and DC
Table 14:
AC Electrical Characteristics: -18, -25E, -25, -33, -5
Notes 1–4 (page 29) apply to the entire table
-18
Description
Symbol
-25E
-25
-33
-5
Min
Max
Min
Max
Min
Max
Min
Max
Min
t
CK
1.875
5.7
2.5
5.7
2.5
5.7
3.3
5.7
5.0
t
DK
t
Max Units Notes
Clock
Input clock cycle
time
Input data clock
cycle time
Clock jitter:
period
Clock jitter: cycleto-cycle
Clock HIGH time
t
JITPER
t
t
–100
JITCC
100
t
CK
–150
200
150
t
CK
–150
300
150
t
CK
–200
300
200
ns
CK
–250
400
ns
250
ps
500
ps
5, 6
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
t
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCKDK
–0.3
0.3
–0.45
0.5
–0.3
0.5
–0.3
1.0
–0.3
1.5
ns
tMRSC
6
–
6
–
6
–
6
–
6
–
tCK
tAS/tCS
0.3
–
0.4
–
0.4
–
0.5
–
0.8
–
ns
tDS
0.17
–
0.25
–
0.25
–
0.3
–
0.4
–
ns
tAH/tCH
0.3
–
0.4
–
0.4
–
0.5
–
0.8
–
ns
tDH
0.17
–
0.25
–
0.25
–
0.3
–
0.4
–
ns
QKH
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
t
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
MIN
(tQKH,
tQKL)
–0.2
–
–
0.3
MIN
(tQKH,
tQKL)
–0.5
–
0.25
MIN
(tQKH,
tQKL)
–0.3
–
0.25
MIN
(tQKH,
tQKL)
–0.25
–
0.2
MIN
(tQKH,
tQKL)
–0.25
0.5
ns
–0.12
0.12
–0.2
0.2
–0.2
0.2
–0.25
0.25
–0.3
0.3
ns
7
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
–0.4
0.4
ns
8
CKH,
CK
tDKH
tCKL,
Clock LOW time
Clock to input
data clock
Mode register set
cycle time to any
command
t
CK
5.7
tDKL
Setup Times
Address/
command and
input setup time
Data-in and data
mask to DK setup
time
Hold Times
Address/
command and
input hold time
Data-in and data
mask to DK hold
time
Data and Data Strobe
t
Output data
clock HIGH time
Output data
clock LOW time
Half-clock period
QK edge to clock
edge skew
QK edge to
output data edge
QK edge to any
output data edge
t
QHP
tCKQK
t
QKQ0,
CKH
tQKQ1
tQKQ
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Electrical Specifications – AC and DC
Table 14:
AC Electrical Characteristics: -18, -25E, -25, -33, -5 (continued)
Notes 1–4 (page 29) apply to the entire table
-18
Description
QK edge to QVLD
Data valid
window
Symbol
-25E
-25
Min
Max
Min
Max
QKVLD
tDVW
–0.22
(tQKQx
[MAX]
+
|tQKQx
[MIN]|)
0.22
–
–0.3
tQHP
0.3
–
tREFI
–
0.49
t
tQHP
(tQKQx
[MAX]
+
|tQKQx
[MIN]|)
-33
-5
Min
Max
Min
Max
Min
–0.3
0.3
–
–0.35
(tQKQx
[MAX]
+
|tQKQx
[MIN]|)
0.35
–
tQHP
0.49
–
0.49
tQHP
(tQKQx
[MAX]
+
|tQKQx
[MIN]|)
tQHP
–0.4
(tQKQx
[MAX]
+
|tQKQx
[MIN]|)
Max Units Notes
0.4
–
ns
0.49
µs
Refresh
Average periodic
refresh interval
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–
0.49
–
28
–
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Electrical Specifications – AC and DC
Notes
1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK#
and to the crossing point with VREF of the command, address, and data signals.
2. Outputs measured with equivalent load:
VTT
50
DQ
Test point
10pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted
at nominal reference/supply voltage levels, but the related specifications and device
operations are tested for the full voltage range specified.
4. AC timing may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input
timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter
specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in
the range between VIL(AC) and VIH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 for the x18
configuration. tQKQ1 is referenced to DQ18–DQ35 for the x36 configuration and
DQ9–DQ17 for the x18 configuration.
8. tQKQ takes into account the skew between any QKx and any Q.
9. To improve efficiency, eight AREF commands (one for each bank) can be posted to the
RLDRAM on consecutive cycles at periodic intervals of 3.90µs.
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Temperature and Thermal Impedance
Temperature and Thermal Impedance
It is imperative that the RLDRAM device’s temperature specifications, shown in Table 15,
are maintained in order to ensure that the junction temperature is in the proper operating range to meet data sheet specifications. An important step in maintaining the
proper junction temperature is using the device’s thermal impedances correctly. The
thermal impedances are listed for the available packages.
Using thermal impedances incorrectly can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications” prior to using the thermal impedances
listed in Table 15. For designs that are expected to last several years and require the flexibility to use several DRAM die shrinks, consider using final target theta values (rather
than existing values) to account for increased thermal impedances from the die size
reduction.
The RLDRAM device’s safe junction temperature range can be maintained when the TC
specification is not exceeded. In applications where the device’s ambient temperature is
too high, use of forced air and/or heat sinks may be required in order to satisfy the case
temperature specifications.
Table 15:
Temperature Limits
Parameter
Storage temperature
Reliability junction temperature
Operating junction temperature
Operating case temperature
Notes:
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Commercial
Industrial
Commercial
Industrial
Commercial
Industrial
Symbol
Min
Max
Units
Notes
TSTG
TJ
–55
–
–
0
–40
0
–40
+150
+110
+110
+100
+100
+95
+95
C
C
C
C
C
C
C
1
2
2
3
3
4, 5
4, 5, 6
TJ
TC
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown in
Figure 9 on page 31. This case temperature limit can be exceeded briefly during package
reflow, as noted in Micron technical note TN-00-15.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the reliability of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package, as shown in
Figure 9 on page 31.
5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
6. Both temperature specifications must be satisfied.
30
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Temperature and Thermal Impedance
Table 16:
Thermal Impedance
Package
Substrate
JA (°C/W)
Airflow = 0m/s
JA (°C/W)
Airflow = 1m/s
JA (°C/W)
Airflow = 2m/s
JB (°C/W)
JC (°C/W)
Rev. A die
2-layer
4-layer
2-layer
4-layer
41.2
28.2
53.7
34.1
29.1
21.9
42.0
28.9
25.3
19.9
37.7
27.1
14.3
13.6
28.9
21.9
2.27
Rev. B die
3.9
Notes: Thermal impedance data is based on a number of samples from multiple lots and should be
viewed as a typical number.
Figure 9:
Example Temperature Test Point Location
Test point
18.50
9.25
5.50
11.00
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Commands
Commands
The following table provides descriptions of the valid commands of the RLDRAM. All
input states or sequences not shown are illegal or reserved. All command and address
inputs must meet setup and hold times around the rising edge of CK.
Table 17:
Description of Commands
Command
DSEL/NOP
MRS
READ
WRITE
AREF
Description
Notes
The NOP command is used to perform a no operation to the RLDRAM, which essentially
deselects the chip. Use the NOP command to prevent unwanted commands from being
registered during idle or wait states. Operations already in progress are not affected.
Output values depend on command history.
The mode register is set via the address inputs A0–A17. See Figure 10 on page 34 for further
information. The MRS command can only be issued when all banks are idle and no other
operation is in progress.
The READ command is used to initiate a burst read access to a bank. The value on the BA0–
BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data
location within the bank.
The WRITE command is used to initiate a burst write access to a bank. The value on the
BA0–BA2 inputs selects the bank, and the address provided on inputs A0–An selects the
data location within the bank. Input data appearing on the DQ is written to the memory
array subject to the DM input logic level appearing coincident with the data. If the DM
signal is registered LOW, the corresponding data will be written to memory. If the DM signal
is registered HIGH, the corresponding data inputs will be ignored (that is, this part of the
data word will not be written).
The AREF command is used during normal operation of the RLDRAM to refresh the memory
content of a bank. The command is nonpersistent, so it must be issued each time a refresh is
required. The value on the BA0–BA2 inputs selects the bank. The refresh address is
generated by an internal refresh controller, effectively making each address bit a “Don’t
Care” during the AREF command. See “AUTO REFRESH (AREF)” on page 41 for more details.
1
Notes:
Table 18:
2
2
1. When the chip is deselected, internal NOP commands are generated and no commands are
accepted.
2. n = 20.
Command Table
Notes 1–2 apply to the entire table
Operation
Device DESELECT/no operation
MRS
READ
WRITE
AUTO REFRESH
Notes:
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1.
2.
3.
4.
Code
CS#
WE#
REF#
A0–An2
BA0–BA2
Notes
DSEL/NOP
MRS
READ
WRITE
AREF
H
L
L
L
L
X
L
H
L
H
X
L
H
H
L
X
OPCODE
A
A
X
X
X
BA
BA
BA
3
4
4
X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.
n = 20.
Only A0–A17 are used for the MRS command.
Address width varies with burst length; see the Address Widths at Different Burst Lengths
table for details.
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Commands
MODE REGISTER SET (MRS)
The mode register set stores the data for controlling the operating modes of the memory.
It programs the RLDRAM configuration, burst length, test mode, and I/O options.
During an MRS command, the address inputs A0–A17 are sampled and stored in the
mode register. After issuing a valid MRS command, tMRSC must be met before any
command can be issued to the RLDRAM. This statement does not apply to the consecutive MRS commands needed for internal logic reset during the initialization routine. The
MRS command can only be issued when all banks are idle and no other operation is in
progress.
Note:
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
CK#
CK
CS#
WE#
REF#
ADDRESS
OPCODE
BANK
ADDRESS
DON’T CARE
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Commands
Figure 10:
Mode Register Definition in Nonmultiplexed Address Mode
A17
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
17–10
9 8 7 6 5
Reserved1 ODT IM DLL NA2 AM
4 3
BL
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
On
M7
0
Drive Impedance
Internal 505 (default)
0
DLL Reset
DLL reset4 (default)
1
External (ZQ)
1
DLL enabled
M8
Notes:
Off (default)
1
1.
2.
3.
4.
5.
2 1 0
Config
Mode Register (Mx)
M2 M1 M0 Configuration
0 0 0 13 (default)
M9 On-Die Termination
0
Address Bus
0
0
1
13
0
1
0
2
0
1
1
3
1
0
0
43
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
M5
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
1
Multiplexed
0
1
4
1
0
8
1
1
Reserved
A10–A17 must be set to zero; A18–An = “Don’t Care.”
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
±30% temperature variation.
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Commands
Configuration Tables
Table 19 shows the different configurations that can be programmed into the mode
register. The WRITE latency is equal to the READ latency plus one in each configuration
in order to maximize data bus utilization. Bits M0, M1, and M2 are used to select the
configuration during the MRS command.
Table 19:
Cycle Time and READ/WRITE Latency Configuration Table
Notes 1 apply to the entire table
Configuration
2
Parameter
t
RC
RL
tWL
Valid frequency range
t
Notes:
1.
2.
3.
1
2
3
42, 3
5
4
4
5
266–175
6
6
7
400–175
8
8
9
533–175
3
3
4
200–175
5
5
6
333–175
Units
t
CK
CK
tCK
MHz
t
tRC
< 20ns in any configuration only available with -25E and -18 speed grades.
BL = 8 is not available.
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to
the same bank. In this instance the minimum tRC is 4 cycles.
Burst Length (BL)
Burst length is defined by M3 and M4 of the mode register. Read and write accesses to
the RLDRAM are burst-oriented, with the burst length being programmable to 2, 4, or 8.
Figure 11 on page 36 illustrates the different burst lengths with respect to a READ
command. Changes in the burst length affect the width of the address bus (see the
Address Widths at Different Burst Lengths table for details).
Note:
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
The data written by the prior burst length is not guaranteed to be accurate when the
burst length of the device is changed.
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Commands
Figure 11:
CK#
Read Burst Lengths
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
QK#
BL = 4
QK
QVLD
DO
an
DQ
QK#
BL = 8
QK
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
Table 20:
DON’T CARE
1. DO an = data-out from bank a and address an.
2. Subsequent elements of data-out appear after DO n.
3. Shown with nominal tCKQK.
Address Widths at Different Burst Lengths
Notes:
Burst Length
x9
x18
x36
2
4
8
A0–A20
A0–A19
A0–A18
A0–A19
A0–A18
A0–A17
A0–A18
A0–A17
A0–A161
1. Only available on Rev B die.
Address Multiplexing
Although the RLDRAM has the ability to operate with an SRAM interface by accepting
the entire address in one clock, an option in the mode register can be set so that it functions with multiplexed addresses, similar to a traditional DRAM. In multiplexed address
mode, the address can be provided to the RLDRAM in two parts that are latched into the
memory with two consecutive rising clock edges. This provides the advantage of only
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Commands
needing a maximum of 11 address balls to control the RLDRAM, reducing the number of
signals on the controller side. The data bus efficiency in continuous burst mode is only
affected when using the BL = 2 setting since the device requires two clocks to read and
write the data. The bank addresses are delivered to the RLDRAM at the same time as the
WRITE and READ command and the first address part, Ax. The Address Mapping in
Multiplexed Address Mode table shows the addresses needed for both the first and
second rising clock edges (Ax and Ay, respectively). The AREF command does not
require an address on the second rising clock edge, as only the bank address is needed
during this command. Because of this, AREF commands may be issued on consecutive
clocks.
The multiplexed address option is available by setting bit M5 to “1” in the mode register.
Once this bit is set, the READ, WRITE, and MRS commands follow the format described
in the Command Description in Multiplexed Address Mode table. Further information
on operation with multiplexed addresses can be seen in the Multiplexed Address Mode
section.
DLL RESET
DLL RESET is selected with bit M7 of the mode register as is shown in the Mode Register
Definition in Nonmultiplexed Address Mode figure. The default setting for this option is
LOW, whereby the DLL is disabled. Once M7 is set HIGH, 1,024 cycles (5µs at 200 MHz)
are needed before a READ command can be issued. This time allows the internal clock to
be synchronized with the external clock. Failing to wait for synchronization to occur
may result in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or
VDD is changed after the DLL has already been enabled. To reset the DLL, an MRS
command must be issued where M7 is set LOW. After waiting tMRSC, a subsequent MRS
command should be issued whereby M7 goes HIGH. 1,024 clock cycles are then needed
before a READ command is issued.
Drive Impedance Matching
The RLDRAM 2 is equipped with programmable impedance output buffers. This option
is selected by setting bit M8 HIGH during the MRS command. The purpose of the
programmable impedance output buffers is to allow the user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is
connected between the ZQ ball and Vss. The value of the resistor must be five times the
desired impedance. For example, a 300 resistor is required for an output impedance of
60. The range of RQ is 125–300, which guarantees output impedance in the range of
25–60 (within 15%).
Output impedance updates may be required because over time variations may occur in
supply voltage and temperature. When the external drive impedance is enabled in the
MRS, the device will periodically sample the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and
current specifications are met during an update.
When bit M8 is set LOW during the MRS command, the RLDRAM provides an internal
impedance at the output buffer of 50 (±30% with temperature variation). This impedance is also periodically sampled and adjusted to compensate for variation in supply
voltage and temperature.
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Commands
On-Die Termination (ODT)
ODT is enabled by setting M9 to “1” during an MRS command. With ODT on, the DQs
and DM are terminated to VTT with a resistance RTT. The command, address, QVLD, and
clock signals are not terminated. Figure 12 on page 38 shows the equivalent circuit of a
DQ receiver with ODT. The ODT function is dynamically switched off when a DQ begins
to drive after a READ command is issued. Similarly, ODT is designed to switch on at the
DQs after the RLDRAM has issued the last piece of data. The DM pin will always be
terminated. See section entitled "Operations" on page 42 for relevant timing diagrams.
Table 21:
On-Die Termination DC Parameters
Description
Termination voltage
On-die termination
Notes:
Figure 12:
Symbol
Min
Max
Units
Notes
VTT
RTT
0.95 × VREF
125
1.05 × VREF
185
V
1, 2
3
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
On-Die Termination-Equivalent Circuit
VTT
SW
RTT
Receiver
DQ
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Commands
WRITE
Write accesses are initiated with a WRITE command, as shown in Figure 13. The address
needs to be provided during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The RLDRAM operates with a WRITE latency (WL) that
is one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming tRC is
met). To avoid external data bus contention, at least one NOP command is needed
between the WRITE and READ commands. Figure 20 on page 47 and Figure 21 on
page 48 illustrate the timing requirements for a WRITE followed by a READ where one
and two intermediary NOPs are required, respectively.
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and
hold times for the DM signal are also tDS and tDH.
Figure 13:
WRITE Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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Commands
READ
Read accesses are initiated with a READ command, as shown in Figure 14. Addresses are
provided with the READ command.
During READ bursts, the memory device drives the read data so it is edge-aligned with
the QKx signals. After a programmable READ latency, data is available at the outputs.
One half clock cycle prior to valid data on the read bus, the data valid signal, QVLD, transitions from LOW to HIGH. QVLD is also edge-aligned with the QKx signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the
skew between QK0 and the last valid data edge generated at the DQ signals associated
with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8
for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge
generated at the DQ signals associated with QK1 (tQKQ1 is referenced to DQ18–DQ35 for
the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is derived at each QKx clock
edge and is not cumulative over time. tQKQ is defined as the skew between either QK
differential pair and any output data edge.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) will go High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. Note that if CK/CK# violates the VID(DC) specification while a READ burst is occurring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks
are free-running and will continue to cycle after the read burst is complete. Back-toback READ commands are possible, producing a continuous flow of output data.
The data valid window is derived from each QK transition and is defined as:
tQHP - (tQKQ [MAX] + |tQKQ [MIN]|). See Figures 27–29 for illustration.
Any READ burst may be followed by a subsequent WRITE command. Figure 26 on
page 52 illustrate the timing requirements for a READ followed by a WRITE. Some
systems having long line lengths or severe skews may need additional idle cycles
inserted between READ and WRITE commands to prevent data bus contention.
Figure 14:
READ Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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Commands
AUTO REFRESH (AREF)
AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the row
addresses are generated by an internal refresh counter for each bank, the external
address balls are “Don’t Care.” The bank addresses must be provided during the AREF
command. The bank address is needed during the AREF command so refreshing of the
part can effectively be hidden behind commands to other banks. The delay between the
AREF command and a subsequent command to the same bank must be at least tRC.
Within a period of 32ms (tREF), the entire device must be refreshed.For the 288Mb
device, the RLDRAM requires 64K cycles at an average periodic interval of 0.49µs MAX
(actual periodic refresh interval is 32ms/8K rows/8 banks = 0.488µs). To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 3.9µs (32ms/8K rows = 3.90µs). Figure 30 on page 56 illustrates an
example of a refresh sequence.
Figure 15:
AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
BA
DON’T CARE
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Operations
Operations
INITIALIZATION
The RLDRAM must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent
damage to the device.
The following sequence is used for power-up:
1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ.1 Apply VDDQ
before or at the same time as VREF and VTT. Although there is no timing relation
between VEXT and VDD, the chip starts the power-up sequence only after both voltages approach their nominal levels. CK/CK# must meet VID(DC) prior to being
applied.2 Apply NOP conditions to command pins. Ensuring CK/CK# meet VID(DC)
while applying NOP conditions to the command pins guarantees that the RLDRAM
will not receive unwanted commands during initialization.
2. Maintain stable conditions for 200µs (MIN).
3. Issue at least three consecutive MRS commands: two or more dummies plus one valid
MRS. The purpose of these consecutive MRS commands is to internally reset the logic
of the RLDRAM. Note that tMRSC does not need to be met between these consecutive
commands. It is recommended that all address pins are held LOW during the dummy
MRS commands.
4. tMRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along with
1,024 NOP commands) must be issued prior to normal operation. The sequence of
the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands)
does not matter. As is required for any operation, tRC must be met between an AUTO
REFRESH command and a subsequent VALID command to the same bank. Note that
older versions of the data sheet required each of these AUTO REFRESH commands be
separated by 2,048 NOP commands. This properly initializes the RLDRAM but is no
longer required.
Notes:
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1. It is possible to apply VDDQ before VDD. However, when doing this, the DQs, DM, and
all other pins with an output driver, will go HIGH instead of tri-stating. These pins will
remain HIGH until VDD is at the same level as VDDQ. Care should be taken to avoid
bus conflicts during this period.
2. If VID(DC) on CK/CK# can not be met prior to being applied to the RLDRAM, placing a
large external resistor from CS# to VDD is a viable option for ensuring the command
bus does not receive unwanted commands during this unspecified state.
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Operations
Figure 16:
Power-Up/Initialization Sequence
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK#
CK
tCKH
T3
T2
tCKL
T4
T5
T6
T8
T7
T9
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
tDKL
NOP
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
REF
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQ
RTT
High-Z
1,2
CODE
T = 200µs (MIN)
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
5.
2
CODE
tMRSC
Power-up:
VDD and stable
clock (CK, CK#)
Notes:
1,2
CODE
VALID
Bank 0
((
))
((
))
Refresh
all banks5
Bank 7
1,024 NOP
commands
Indicates a break in
time scale
DON’T CARE
Recommend all address pins held LOW during dummy MRS commands.
A10–A17 must be LOW.
DLL must be reset if tCK or VDD are changed.
CK and CK# must be separated at all times to prevent bogus commands from being issued.
The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
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Operations
Figure 17:
Power-Up/Initialization Flow Chart
Step
Notes:
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1
VDD, and VEXT ramp
2
VDDQ ramp
3
Apply VREF and VTT
4
Apply stable CK/CK# and DK/DK#
5
Wait at least 200µs
6
Issue MRS command—A10–A17 must be LOW
7
Issue MRS command—A10–A17 must be LOW
8
Desired load mode register with A10–A17 LOW
9
Assert NOP for tMRSC
10
Issue AUTO REFRESH to bank 0
11
Issue AUTO REFRESH to bank 1
12
Issue AUTO REFRESH to bank 2
13
Issue AUTO REFRESH to bank 3
14
Issue AUTO REFRESH to bank 4
15
Issue AUTO REFRESH to bank 5
16
Issue AUTO REFRESH to bank 6
17
Issue AUTO REFRESH to bank 7
18
Wait 1,024 NOP commands1
19
Valid command
Voltage rails
can be applied
simultaneously
MRS commands
must be on
consecutive clock
cycles
1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
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Operations
WRITE
Figure 18:
WRITE Burst
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T6n
T7
CK#
CK
tCKDK (NOM)
NOP
NOP
WL = 5
DK#
DK
DI
an
DQ
DM
tCKDK (MIN)
WL - tCKDK
DK#
DK
DI
an
DQ
DM
tCKDK (MAX)
WL + tCKDK
DK#
DK
DI
an
DQ
DM
TRANSITIONING DATA
Notes:
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
DON’T CARE
1. DI an = data-in for bank a and address n; subsequent elements of burst are applied following DI an.
2. BL = 4.
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Operations
Figure 19:
Consecutive WRITE-to-WRITE
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
T4
T5
T5n
T6
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
Bank a,
Add n
Bank b,
Add n
WRITE
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DK#
DK
t
RC = 4
WL = 5
WL = 5
DI
an
DQ
DI
bn
DI
an
DM
TRANSITIONING DATA
Notes:
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RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
DON’T CARE
1.
2.
3.
4.
DI an (or bn) = data-in for bank a (or b) and address n.
Three subsequent elements of the burst are applied following DI for each bank.
BL = 4.
Each WRITE command may be to any bank; if the second WRITE is to the same bank,
tRC must be met.
5. Nominal conditions are assumed for specifications not defined.
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Operations
Figure 20:
WRITE-to-READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T5n
T6
T6n
T7
CK#
CK
NOP
NOP
Bank b,
Add n
WL = 5
RL = 4
QK#
QK
DK#
DK
QVLD
DI
an
DQ
DO
bn
DM
DON’T CARE
Notes:
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1.
2.
3.
4.
5.
TRANSITIONING DATA
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
Two subsequent elements of each burst follow DI an and DO bn.
BL = 2.
Nominal conditions are assumed for specifications not defined.
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Operations
Figure 21:
WRITE-to-READ (Separated by Two NOPs)
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T7
NOP
NOP
T7n
T8
CK#
CK
NOP
Bank b,
Add n
WL = 5
tCKQK (MIN)
RL = 4
QK#
QK
DK#
DK
tCKDK (MAX)
QVLD
DI
an
DQ
DO
bn
DM
tDH
tQKQ (MIN)
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
DON’T CARE
1.
2.
3.
4.
5.
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
One subsequent element of each burst follow both DI an and DO bn.
BL = 2.
Only one NOP separating the WRITE and READ would have led to contention on the data
bus because of the input and output data timing conditions being used.
6. Nominal conditions are assumed for specifications not defined.
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Operations
Figure 22:
WRITE – DM Operation
T1
T0
T2
T3
T4
NOP
NOP
T5
T6
T6n
T7
T7n
T8
CK#
CK
tCK
COMMAND
NOP
WRITE
tCH
NOP
tCL
NOP
NOP
NOP
NOP
Bank a,
Add n
ADDRESS
DK#
DK
tDKL
WL = 5
tDKH
DI
an
DQ
DM
tDS
tDH
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
DON’T CARE
DI an = data-in for bank a and address n.
Subsequent elements of burst are provided on following clock edges.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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Operations
READ
Figure 23:
Basic READ Burst Timing
T1
T0
T2
T3
T4
T5
NOP
NOP
T5n
T6
T6n
T7
CK#
CK
tCK
COMMAND
NOP
READ
tCH
tCL
NOP
READ
Bank a
Add n
ADDRESS
NOP
NOP
Bank a
Add n
RL = 4
tRC = 4
DM
tCKQK (MIN)
tCKQK (MIN)
QK#
QK
tQK
tQKH
tQKVLD
tQKL
tQKVLD
QVLD
DO
an
DQ
tCKQK (MAX)
tCKQK (MAX)
QK#
QK
tQK
tQKH
tQKL
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
DON’T CARE
DO an = data-out from bank a and address an.
Three subsequent elements of the burst are applied following DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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Operations
Figure 24:
Consecutive READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
READ
READ
READ
ADDRESS
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
DQ
DO
bn
DO
cn
TRANSITIONING DATA
Notes:
Figure 25:
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn or cn) = data-out from bank a (or bank b or bank c) and address n.
One subsequent element of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
6. Data from the READ commands to bank d through bank g will appear on subsequent clock
cycles that are not shown.
Consecutive READ Bursts (BL = 4)
T0
T1
T2
T3
T4
COMMAND
READ
NOP
READ
NOP
READ
ADDRESS
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
DO
bn
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn) = data-out from bank a (or bank b) and address n.
Three subsequent elements of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same bank if
tRC has been met.
6. Data from the READ commands to banks c and d will appear on subsequent clock cycles
that are not shown.
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Operations
Figure 26:
READ-to-WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
CK#
CK
Bank b,
Add n
DM
QK#
QK
DK#
DK
RL = 4
WL = RL + 1 = 5
QVLD
DO
an
DQ
DI
bn
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
5.
DON’T CARE
DO an = data-out from bank a and address n.
DI bn = data-in for bank b and address n.
Three subsequent elements of each burst follow DI bn and each DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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Operations
Figure 27:
Read Data Valid Window for x9 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
tDVW3
tDVW3
tDVW3
tDVW3
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
tQHP
is defined as the lesser of tQKH or tQKL.
is referenced to DQ0–DQ8.
Minimum data valid window (tDVW) can be expressed as
tQHP - (tQKQx [MAX] + |tQKQx [MIN]|).
tQKQ0
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Operations
Figure 28:
Read Data Valid Window for x18 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MIN)4
DQ9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
tDVW3
t
t
tDVW3
tDVW3
t
1. QHP is defined as the lesser of QKH or QKL.
2. tQKQ0 is referenced to DQ0–DQ8.
3. Minimum data valid window (tDVW) can be expressed as
t
QHP - (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ9–DQ17.
5. tQKQ takes into account the skew between any QKx and any DQ.
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Operations
Figure 29:
Read Data Valid Window for x36 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
Lower word
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
tQHP1
tQKQ1(MAX)4
tQKQ1(MIN)4
tQKQ1 (MIN)4
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
Upper word
DQ18
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ35
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
tDVW3
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ17.
3. Minimum data valid window, tDVW, can be expressed as
tQHP - (tQKQx [MAX] + |tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ18–DQ35.
5. tQKQ takes into account the skew between any QKx and any DQ.
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Operations
AUTO REFRESH
Figure 30:
AUTO REFRESH Cycle
T0
T1
CK
tCK
COMMAND
AREFx
AREFy
ADDRESS
BANK
BAx
T2
((
))
CK#
BAy
((
))
T3
tCH
ACx
DQ
DM
tRC
((
))
((
))
((
))
Indicates a break in
time scale
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
ACy
((
))
((
))
DK, DK#
Notes:
tCL
DON’T CARE
1. AREFx = AUTO REFRESH command to bank x.
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
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Operations
On-Die Termination
Figure 31:
CK#
READ Burst with ODT
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT on
DQ ODT off
QK#
BL = 4
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT off
DQ ODT on
QK#
BL = 8
QK
QVLD
DO
an
DQ
DQ ODT off
DQ ODT on
DQ ODT
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
on
DON’T CARE
1. DO an = data out from bank a and address n.
2. DO an is followed by the remaining bits of the burst.
3. Nominal conditions are assumed for specifications not defined.
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Operations
Figure 32:
READ-NOP-READ with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
READ
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
CK
COMMAND
Bank a,
Col n
ADDRESS
NOP
NOP
Bank b,
Col n
RL = 4
QK#
QK
QVLD
DO
an
DQ
DQ ODT on
DQ ODT
DO
bn
DQ ODT on
DQ ODT off
DQ ODT on
DQ ODT off
TRANSITIONING DATA
Notes:
Figure 33:
1.
2.
3.
4.
DON’T CARE
DO an (or bn) = data-out from bank a (or bank b) and address n.
BL = 2.
One subsequent element of the burst appear after DO an and DO bn.
Nominal conditions are assumed for specifications not defined.
READ-to-WRITE with ODT
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
NOP
NOP
NOP
ADDRESS
Bank a
Add n
Bank b
Add n
T4n
T5
T6
NOP
NOP
T6n
T7
T8
NOP
NOP
T9
CK#
CK
RL = 4
WL = 5
DKx#
DKx
DO
an
DQ
DI
bn
QKx
QKx#
ODT
ODT on
ODT on
ODT off
TRANSITIONING DATA
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
UNDEFINED
DON’T CARE
DO an = data-out from bank a and address n; DI bn = data-in for bank b and address n.
BL = 2.
One subsequent element of each burst appears after each DO an and DI bn.
Nominal conditions are assumed for specifications not defined.
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Operations
Multiplexed Address Mode
Figure 34:
Command Description in Multiplexed Address Mode
READ
WRITE
MRS
REF
CK#
CK
CS#
WE#
REF#
ADDRESS
Ax
BANK
ADDRESS
BA
Ay
Ax
Ay
Ax
BA
BA
Ay
BA
DON’T CARE
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1. The minimum setup and hold times of the two address parts are defined tAS and tAH.
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Operations
Figure 35:
Power-Up/Initialization Sequence in Multiplexed Address Mode
VEXT
VDD
VDDQ
VREF
VTT
T0
T1
tCK
CK#
CK
tCKL
tCKH
T3
T2
T4
T5
T6
T7
T8
T9
T10
T11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
NOP
tDKL
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
MRS
NOP
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
5
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK
ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tMRSC
tMRSC
Refresh
all banks9
1,024 NOP
commands
DQ
RTT
High-Z
1,2
CODE
1,2
CODE
T = 200µs (MIN)
2,3
CODE
((
))
((
))
Ax
2,4
Ay
2
5
VALID
Bank 0
((
))
((
))
Bank 7
5
Power-up:
VDD and stable
clock (CK, CK#)
Indicates a break in
time scale
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
DON’T CARE
1. Recommended that all address pins held LOW during dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enables the part to enter multiplexed address mode when in nonmultiplexed mode operation. Multiplexed address mode can also be entered at some later
time by issuing an MRS command with A5 HIGH. Once address bit A5 is set HIGH, tMRSC
must be satisfied before the two-cycle multiplexed mode MRS command is issued.
4. Address A5 must be set HIGH. This and the following step set the desired mode register
once the RLDRAM is in multiplexed address mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the RLDRAM in the multiplexed
address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK# must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP commands) does not matter. As is required for any operation, tRC must be met between an
AUTO REFRESH command and a subsequent VALID command to the same bank.
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Operations
Figure 36:
Mode Register Definition in Multiplexed Address Mode
A5 A4 A3
A0
Ax A18 . . . A10 A9 A8
Ay A18 . . . A10
A9 A8
A4 A3
18–10
9 8 7 6 5
Reserved1 ODT IM DLL NA5 AM
4
3
2
BL
1
0
Mode Register (Mx)
Config
M2
M1
M0
0
Off (default)
0
0
0
Configuration
12 (default)
1
On
0
0
1
12
0
1
0
2
0
1
1
3
0
0
42
M9 On-Die Termination
M8
Drive Impedance
M7
DLL Reset
1
0
Internal 503 (default)
0
DLL reset4 (default)
1
0
1
5
External (ZQ)
1
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
1
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1.
2.
3.
4.
5.
6.
7.
Burst Length
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
Multiplexed
0
1
4
1
0
8
1
1
Reserved
1
Notes:
M4 M3
M5
Bits A10–A18 must be set to zero.
BL = 8 is not available.
±30% temperature variation.
DLL RESET turns the DLL off.
Ay8 not used in MRS.
BA0–BA2 are “Don’t Care.”
Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the mode
register in the multiplexed address mode.
61
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Operations
Address Mapping in Multiplexed Address Mode
Table 22:
288Mb Address Mapping in Multiplexed Address Mode
Data
Width
Burst
Length
x36
2
4
8
x18
2
4
8
x9
2
4
8
Address
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
Ax
Ay
A0
X
A0
X
A0
X
A0
X
A0
X
A0
X
A0
A20
A0
X
A0
X
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A3
A1
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A4
A2
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A5
X
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A8
A6
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A9
A7
A10
X
A10
X
A10
X
A10
A19
A10
X
A10
X
A10
A19
A10
A19
A10
X
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A13
A11
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A14
A12
A17
A16
A17
A16
X
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A17
A16
A18
A15
X
A15
X
A15
A18
A15
A18
A15
X
A15
A18
A15
A18
A15
A18
A15
Notes:
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_2_CIO_Core.fm - Rev. D 10/12 EN
1. X = “Don’t Care.”
62
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
288Mb: x9, x18, x36 2.5V VEXT, 1.8V VDD, HSTL, CIO, RLDRAM 2
Operations
Configuration Tables in Multiplexed Address Mode
In multiplexed address mode, the read and write latencies are increased by one clock
cycle. However, the RLDRAM cycle time remains the same as when in non-multiplexed
address mode.
Table 23:
Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Notes 1 apply to the entire table
Configuration
Parameter
1
t
RC
RL
tWL
Valid frequency range
t
Notes:
2
4
5
6
266–175
1.
2.
3.
2
3
42, 3
5
6
7
8
400–175
8
9
10
533–175
3
4
5
200–175
5
6
7
333–175
Units
t
CK
CK
tCK
MHz
t
tRC
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