576Mb: x9 x18 x36 CIO RLDRAM 2
Features
CIO RLDRAM 2
MT49H64M9 – 64 Meg x 9 x 8 Banks
MT49H32M18 – 32 Meg x 18 x 8 Banks
MT49H16M36 – 16 Meg x 36 x 8 Banks
Options1
Features
• Clock cycle timing
– 1.875ns @ tRC = 15ns
– 2.5ns @ tRC = 15ns
– 2.5ns @ tRC = 20ns
– 3.3ns @ tRC = 20ns
• Configuration
– 64 Meg x 9
– 32 Meg x 18
– 16 Meg x 36
• Operating temperature
– Commercial (0° to +95°C)
– Industrial (TC = –40°C to +95°C;
TA = –40°C to +85°C)
• Package
– 144-ball μBGA
– 144-ball μBGA (Pb-free)
– 144-ball FBGA
– 144-ball FBGA (Pb-free)
• Revision
• 533 MHz DDR operation (1.067 Gb/s/pin data rate)
• 38.4 Gb/s peak bandwidth (x36 at 533 MHz clock
frequency)
• Organization
– 64 Meg x 9, 32 Meg x 18, and 16 Meg x 36 I/O
– 8 banks
• Reduced cycle time (15ns at 533 MHz)
• Nonmultiplexed addresses (address multiplexing
option available)
• SRAM-type interface
• Programmable READ latency (RL), row cycle time,
and burst sequence length
• Balanced READ and WRITE latencies in order to optimize data bus utilization
• Data mask for WRITE commands
• Differential input clocks (CK, CK#)
• Differential input data clocks (DKx, DKx#)
• On-die DLL generates CK edge-aligned data and
output data clock signals
• Data valid signal (QVLD)
• 32ms refresh (16K refresh for each bank; 128K refresh command must be issued in total each 32ms)
• HSTL I/O (1.5V or 1.8V nominal)
• –Ω matched impedance outputs
• 2.5V V EXT, 1.8V V DD, 1.5V or 1.8V V DDQ I/O
• On-die termination (ODT) RTT
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
Note:
1
Marking
-18
-25E
-25
-33
64M9
32M18
16M36
None
IT
FM
BM
TR
SJ
:A/:B
1. Not all options listed can be combined to
define an offered product. Use the part catalog search on www.micron.com for available offerings.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
BGA Marking Decoder
Due to space limitations, BGA-packaged components have an abbreviated part marking that is different from the
part number. Micron’s BGA Part Marking Decoder is available on Micron’s web site at micron.com.
Figure 1: Part Numbers
Example Part Number:
MT49H16M36SJ-25 :B
-
MT49H
Configuration I/O Package
Configuration
:
Speed Temp.
I/O
Rev.
Revision
64 Meg x 9
64M9
Common None
Rev. A
:A
32 Meg x 18
32M18
Separate
Rev. B
:B
16 Meg x 36
16M36
C
Temperature
Package
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576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
Commercial
144-ball μBGA
FM
144-ball μBGA (Pb-free)
BM
144-ball FBGA
TR
144-ball FBGA (Pb-free)
SJ
2
Industrial
None
IT
Speed Grade
-18
tCK
-25E
tCK
= 2.5ns
-25
tCK
= 2.5ns
-33
tCK
= 3.3ns
= 1.875ns
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Features
Contents
General Description ......................................................................................................................................... 7
Functional Block Diagrams ............................................................................................................................... 8
Ball Assignments and Descriptions ................................................................................................................. 11
Package Dimensions ....................................................................................................................................... 16
Electrical Specifications – IDD .......................................................................................................................... 18
Absolute Maximum Ratings ............................................................................................................................ 22
AC and DC Operating Conditions .................................................................................................................... 23
Input Slew Rate Derating ................................................................................................................................ 26
Notes ............................................................................................................................................................. 31
Temperature and Thermal Impedance ............................................................................................................ 32
Commands .................................................................................................................................................... 34
MODE REGISTER SET (MRS) ...................................................................................................................... 35
Configuration Tables .............................................................................................................................. 37
Burst Length (BL) ................................................................................................................................... 37
Address Multiplexing .............................................................................................................................. 39
DLL RESET ............................................................................................................................................. 39
Drive Impedance Matching .................................................................................................................... 39
On-Die Termination (ODT) ..................................................................................................................... 40
WRITE ....................................................................................................................................................... 41
READ ......................................................................................................................................................... 42
AUTO REFRESH (AREF) .............................................................................................................................. 43
INITIALIZATION ............................................................................................................................................ 43
WRITE ........................................................................................................................................................... 47
READ ............................................................................................................................................................. 52
AUTO REFRESH ............................................................................................................................................. 60
On-Die Termination ....................................................................................................................................... 61
Multiplexed Address Mode .............................................................................................................................. 64
Address Mapping in Multiplexed Address Mode ........................................................................................... 67
Configuration Tables in Multiplexed Address Mode ...................................................................................... 67
REFRESH Command in Multiplexed Address Mode ..................................................................................... 68
IEEE 1149.1 Serial Boundary Scan (JTAG) ........................................................................................................ 72
Disabling the JTAG Feature ......................................................................................................................... 72
Test Access Port (TAP) ..................................................................................................................................... 72
Test Clock (TCK) ......................................................................................................................................... 72
Test Mode Select (TMS) .............................................................................................................................. 72
Test Data-In (TDI) ...................................................................................................................................... 73
Test Data-Out (TDO) .................................................................................................................................. 73
TAP Controller ................................................................................................................................................ 73
Test-Logic-Reset ......................................................................................................................................... 73
Run-Test/Idle ............................................................................................................................................. 73
Select-DR-Scan .......................................................................................................................................... 73
Capture-DR ................................................................................................................................................ 73
Shift-DR ..................................................................................................................................................... 73
Exit1-DR, Pause-DR, and Exit2-DR .............................................................................................................. 74
Update-DR ................................................................................................................................................. 74
Instruction Register States .......................................................................................................................... 74
Performing a TAP RESET ................................................................................................................................. 75
TAP Registers ................................................................................................................................................. 75
Instruction Register .................................................................................................................................... 75
Bypass Register .......................................................................................................................................... 75
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576Mb: x9 x18 x36 CIO RLDRAM 2
Features
Boundary Scan Register ..............................................................................................................................
Identification (ID) Register ..........................................................................................................................
TAP Instruction Set .........................................................................................................................................
EXTEST ......................................................................................................................................................
IDCODE .....................................................................................................................................................
High-Z .......................................................................................................................................................
CLAMP ......................................................................................................................................................
SAMPLE/PRELOAD ....................................................................................................................................
BYPASS ......................................................................................................................................................
Reserved for Future Use ..............................................................................................................................
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76
76
76
77
77
77
77
77
78
78
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576Mb: x9 x18 x36 CIO RLDRAM 2
Features
List of Figures
Figure 1: Part Numbers .................................................................................................................................... 2
Figure 2: Simplified State Diagram ................................................................................................................... 7
Figure 3: 64 Meg x 9 Functional Block Diagram ................................................................................................. 8
Figure 4: 32 Meg x 18 Functional Block Diagram ............................................................................................... 9
Figure 5: 16 Meg x 36 Functional Block Diagram ............................................................................................. 10
Figure 6: 144-Ball μBGA ................................................................................................................................. 16
Figure 7: 144-Ball FBGA ................................................................................................................................. 17
Figure 8: Clock Input ..................................................................................................................................... 25
Figure 9: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate ........................................................................... 29
Figure 10: Example Temperature Test Point Location ...................................................................................... 33
Figure 11: MODE REGISTER Command ......................................................................................................... 35
Figure 12: Mode Register Definition in Nonmultiplexed Address Mode ............................................................ 36
Figure 13: Read Burst Lengths ........................................................................................................................ 38
Figure 14: On-Die Termination-Equivalent Circuit .......................................................................................... 40
Figure 15: WRITE Command ......................................................................................................................... 41
Figure 16: READ Command ........................................................................................................................... 42
Figure 17: AUTO REFRESH Command ........................................................................................................... 43
Figure 18: Power-Up/Initialization Sequence ................................................................................................. 45
Figure 19: Power-Up/Initialization Flow Chart ................................................................................................ 46
Figure 20: WRITE Burst ................................................................................................................................. 47
Figure 21: Consecutive WRITE-to-WRITE ....................................................................................................... 48
Figure 22: WRITE-to-READ ............................................................................................................................ 49
Figure 23: WRITE-to-READ (Separated by Two NOPs) ..................................................................................... 50
Figure 24: WRITE – DM Operation ................................................................................................................. 51
Figure 25: Basic READ Burst Timing ............................................................................................................... 52
Figure 26: Consecutive READ Bursts (BL = 2) .................................................................................................. 53
Figure 27: Consecutive READ Bursts (BL = 4) .................................................................................................. 53
Figure 28: READ-to-WRITE ............................................................................................................................ 54
Figure 29: Read Data Valid Window for x9 Device ........................................................................................... 55
Figure 30: Read Data Valid Window for x18 Device .......................................................................................... 56
Figure 31: Read Data Valid Window for x36 Device .......................................................................................... 58
Figure 32: AUTO REFRESH Cycle ................................................................................................................... 60
Figure 33: READ Burst with ODT .................................................................................................................... 61
Figure 34: READ-NOP-READ with ODT .......................................................................................................... 62
Figure 35: READ-to-WRITE with ODT ............................................................................................................ 63
Figure 36: Command Description in Multiplexed Address Mode ..................................................................... 64
Figure 37: Power-Up/Initialization Sequence in Multiplexed Address Mode ..................................................... 65
Figure 38: Mode Register Definition in Multiplexed Address Mode .................................................................. 66
Figure 39: Burst REFRESH Operation with Multiplexed Addressing ................................................................. 68
Figure 40: Consecutive WRITE Bursts with Multiplexed Addressing ................................................................. 68
Figure 41: WRITE-to-READ with Multiplexed Addressing ................................................................................ 69
Figure 42: Consecutive READ Bursts with Multiplexed Addressing ................................................................... 70
Figure 43: READ-to-WRITE with Multiplexed Addressing ................................................................................ 70
Figure 44: TAP Controller State Diagram ......................................................................................................... 74
Figure 45: TAP Controller Block Diagram ........................................................................................................ 75
Figure 46: JTAG Operation – Loading Instruction Code and Shifting Out Data .................................................. 78
Figure 47: TAP Timing ................................................................................................................................... 79
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
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576Mb: x9 x18 x36 CIO RLDRAM 2
Features
List of Tables
Table 1: 64 Meg x 9 Ball Assignments (Top View) 144-Ball μBGA ......................................................................
Table 2: 32 Meg x 18 Ball Assignments (Top View) 144-Ball μBGA .....................................................................
Table 3: 16 Meg x 36 Ball Assignments (Top View) 144-Ball μBGA .....................................................................
Table 4: Ball Descriptions ..............................................................................................................................
Table 5: IDD Operating Conditions and Maximum Limits – Rev. A ....................................................................
Table 6: IDD Operating Conditions and Maximum Limits – Rev. B ....................................................................
Table 7: Absolute Maximum Ratings ..............................................................................................................
Table 8: DC Electrical Characteristics and Operating Conditions .....................................................................
Table 9: Input AC Logic Levels ........................................................................................................................
Table 10: Differential Input Clock Operating Conditions .................................................................................
Table 11: Address and Command Setup and Hold Derating Values ..................................................................
Table 12: Data Setup and Hold Derating Values ..............................................................................................
Table 13: Capacitance – μBGA ........................................................................................................................
Table 14: Capacitance – FBGA ........................................................................................................................
Table 15: AC Electrical Characteristics: -18, -25E, -25, -33 ................................................................................
Table 16: Temperature Limits .........................................................................................................................
Table 17: Thermal Impedance ........................................................................................................................
Table 18: Thermal Impedance ........................................................................................................................
Table 19: Description of Commands ..............................................................................................................
Table 20: Command Table .............................................................................................................................
Table 21: Cycle Time and READ/WRITE Latency Configuration Table ..............................................................
Table 22: Address Widths at Different Burst Lengths .......................................................................................
Table 23: On-Die Termination DC Parameters ................................................................................................
Table 24: 576Mb Address Mapping in Multiplexed Address Mode ....................................................................
Table 25: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode ..............................
Table 26: Instruction Codes ...........................................................................................................................
Table 27: TAP Input AC Logic Levels ...............................................................................................................
Table 28: TAP AC Electrical Characteristics .....................................................................................................
Table 29: TAP DC Electrical Characteristics and Operating Conditions .............................................................
Table 30: Identification Register Definitions ...................................................................................................
Table 31: Scan Register Sizes ..........................................................................................................................
Table 32: Boundary Scan (Exit) Order .............................................................................................................
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11
12
13
13
18
20
22
23
24
24
26
28
29
29
29
32
33
33
34
34
37
38
40
67
67
76
79
79
80
80
80
81
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576Mb: x9 x18 x36 CIO RLDRAM 2
General Description
General Description
RLDRAM® 2 is a high-speed memory device designed for high bandwidth data storage,
telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for sustainable high-speed operation.
The DDR I/O interface transfers two data words per clock cycle at the I/O balls. Output
data is referenced to the free-running output data clock.
Commands, addresses, and control signals are registered at every positive edge of the
differential input clock, while input data is registered at both positive and negative
edges of the input data clock(s).
Read and write accesses are burst-oriented. The burst length (BL) is programmable
from 2, 4, or 8 by setting the mode register.
The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output
drivers.
Bank-scheduled refresh is supported with the row address generated internally.
The μBGA 144-ball package enables ultra high-speed data transfer rates and a simple
upgrade path from early generation devices.
Figure 2: Simplified State Diagram
Initialization
sequence
DSEL/NOP
WRITE
READ
MRS
AREF
Automatic sequence
Command sequence
PDF: 09005aef80fe62fb
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576Mb: x9 x18 x36 CIO RLDRAM 2
Functional Block Diagrams
Functional Block Diagrams
Figure 3: 64 Meg x 9 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Command
decode
CS#
REF#
WE#
Control
logic
VTT
Refresh
counter
Mode register
18
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
14
Rowaddress
MUX
14
14
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
16,384
Bank 0
memory
array
(16,384 x 16 x 16 x 18)2
DLL
ZQ CAL
18
18
288
SENSE
AMPLIFIERS
Sense amplifiers
READ n
logic
n
18
Drivers
DQ
latch
DQ0–DQ17
288
24
Address
register
Bank
control
logic
3
1
I/O gating
DQM mask logic
8
3
8
7
1
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO
and
drivers
CLK
in
1
18
18
18
Input
logic
288
8
DK/DK#
2
16
4
QVLD
QK0–QK1/QK0#–QK1#
4
QK/QK#
generator
16,384
1
A0–A20
BA0–BA2
(0 ....17)
RCVRS
VTT
RTT
7
1
3
ODT control
DM
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 32 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
8
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© 2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Functional Block Diagrams
Figure 4: 32 Meg x 18 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Command
decode
CS#
REF#
WE#
Control
logic
VTT
Refresh
counter
Mode register
18
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
14
Rowaddress
MUX
14
14
Bank 0
rowaddress
latch
and
decoder
RTT
ODT control
CK/CK#
16,384
Bank 0
memory
array
(16,384 x 16 x 8 x 36)2
ZQ CAL
36
36
288
SENSEamplifiers
AMPLIFIERS
Sense
READ n
logic
n
36
Drivers
DQ
latch
288
24
Bank
control
logic
Address
register
3
DQ0–DQ35
1
I/O gating
DQM mask logic
8
2
8
6
1
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO
and
drivers
CLK
in
1
36
36
36
Input
logic
288
8
DK0–DK1/DK0#–DK1#
4
16
4
QVLD
QK0–QK1/QK0#–QK1#
4
QK/QK#
generator
16,384
1
A0–A19
BA0–BA2
(0 ....35)
DLL
RCVRS
VTT
RTT
6
1
2
ODT control
DM
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 16 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
9
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© 2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Functional Block Diagrams
Figure 5: 16 Meg x 36 Functional Block Diagram
ZQ
ZQ CAL
Output drivers
ODT control
CK
CK#
Command
decode
CS#
REF#
WE#
Control
logic
VTT
Refresh
counter
Mode register
18
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Bank 0
14
Rowaddress
MUX
14
14
RTT
ODT control
CK/CK#
Bank 0
rowaddress
latch
and
decoder
16,384
Bank 0
memory
array
2
(16,384 x 16 x 32 x 9)
DLL
ZQ CAL
288
SENSEamplifiers
AMPLIFIERS
Sense
READ n
logic
n
9
9
9
Drivers
DQ
latch
288
Address
register
3
DQ0–DQ8
1
I/O gating
DQM mask logic
8
4
8
DK/DK#
16
288
4
8
1
8
Columnaddress
counter/
latch
Column
decoder
WRITE
FIFO
and
drivers
CLK
in
n
n
9
9
Input
logic
25
Bank
control
logic
QVLD
QK0/QK0#
2
QK/QK#
generator
16,384
1
A0–A21
BA0–BA2
(0 ....8)
9
RCVRS
VTT
1
RTT
8
1
4
ODT control
DM
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. Example for BL = 2; column address will be reduced with an increase in burst length.
2. 8 = (length of burst) x 2^(number of column addresses to WRITE FIFO and READ logic).
10
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576Mb: x9 x18 x36 CIO RLDRAM 2
Ball Assignments and Descriptions
Ball Assignments and Descriptions
Table 1: 64 Meg x 9 Ball Assignments (Top View) 144-Ball μBGA
A
1
2
3
4
VREF
VSS
VEXT
VSS
DNU3
5
6
7
8
9
10
11
12
VSS
VEXT
TMS
TCK
VDD
B
VDD
DNU3
VSSQ
VSSQ
DQ0
DNU3
C
VTT
DNU3
DNU3
VDDQ
VDDQ
DQ1
DNU3
VTT
D
A221
DNU3
DNU3
VSSQ
VSSQ
QK0#
QK0
VSS
A21
DNU3
DNU3
DQ2
DNU3
A20
DNU3
QVLD
E
VDDQ
VDDQ
F
A5
DNU3
VSSQ
VSSQ
DQ3
DNU3
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
B2
A9
VSS
VSS
VSS
VSS
A4
A3
J
NF2
NF2
VDD
VDD
VDD
VDD
B0
CK
K
DK
DK#
VDD
VDD
VDD
VDD
B1
CK#
L
REF#
CS#
VSS
VSS
VSS
VSS
A14
A13
M
WE#
A16
A17
VDD
VDD
A12
A11
A10
A18
DNU3
DNU3
DQ4
DNU3
A19
P
A15
DNU3
DNU3
VDDQ
VDDQ
DQ5
DNU3
DM
R
VSS
DNU3
DNU3
VSSQ
VSSQ
DQ6
DNU3
VSS
VTT
DNU3
DNU4
DQ7
DNU3
VTT
U
VDD
DNU3
DNU3
VSSQ
VSSQ
DQ8
DNU3
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This signal is not connected.
2. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O.
This may optionally be connected to GND. Note that if ODT is enabled on Rev. A die,
these pins will be connected to VTT. The DNU pins are High-Z on Rev. B die when ODT is
enabled.
N
T
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
VSSQ
VSSQ
VDDQ
VDDQ
11
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576Mb: x9 x18 x36 CIO RLDRAM 2
Ball Assignments and Descriptions
Table 2: 32 Meg x 18 Ball Assignments (Top View) 144-Ball μBGA
A
1
2
3
4
VREF
VSS
VEXT
VSS
5
6
7
8
9
10
11
12
VSS
VEXT
TMS
TCK
VDD
B
VDD
DNU4
DQ4
VSSQ
VSSQ
DQ0
DNU4
C
VTT
DNU4
DQ5
VDDQ
VDDQ
DQ1
DNU4
VTT
D
A221
DNU4
DQ6
VSSQ
VSSQ
QK0#
QK0
VSS
E
A212
DNU4
DQ2
DNU4
A20
QVLD
DQ7
VDDQ
VDDQ
F
A5
DNU4
DQ8
VSSQ
VSSQ
DQ3
DNU4
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
B2
A9
VSS
VSS
VSS
VSS
A4
A3
J
NF3
NF3
VDD
VDD
VDD
VDD
B0
CK
K
DK
DK#
VDD
VDD
VDD
VDD
B1
CK#
L
REF#
CS#
VSS
VSS
VSS
VSS
A14
A13
M
WE#
A16
A17
VDD
VDD
A12
A11
A10
A18
DNU4
DQ9
DNU4
A19
P
A15
DNU4
DQ15
VDDQ
VDDQ
DQ10
DNU4
DM
R
VSS
QK1
QK1#
VSSQ
VSSQ
DQ11
DNU4
VSS
VTT
DNU4
DQ12
DNU4
VTT
U
VDD
DNU4
DQ17
VSSQ
VSSQ
DQ13
DNU4
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND.
3. No function. This signal is internally connected and has parasitic characteristics of a clock
input signal. This may optionally be connected to GND.
4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O.
This may optionally be connected to GND. Note that if ODT is enabled on Rev. A die,
these pins will be connected to VTT. The DNU pins are High-Z on Rev. B die when ODT is
enabled.
N
T
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DQ14
DQ16
VSSQ
VSSQ
VDDQ
VDDQ
12
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Ball Assignments and Descriptions
Table 3: 16 Meg x 36 Ball Assignments (Top View) 144-Ball μBGA
1
2
3
4
A
VREF
VSS
VEXT
VSS
5
6
7
8
9
10
11
12
VSS
VEXT
TMS
TCK
B
VDD
DQ8
DQ9
VSSQ
VSSQ
DQ1
DQ0
VDD
C
VTT
DQ10
DQ11
VDDQ
VDDQ
DQ3
DQ2
VTT
D
A221
DQ12
DQ13
VSSQ
VSSQ
QK0#
QK0
VSS
E
A212
DQ14
DQ15
VDDQ
VDDQ
DQ5
DQ4
A202
F
A5
DQ16
DQ17
VSSQ
VSSQ
DQ7
DQ6
QVLD
G
A8
A6
A7
VDD
VDD
A2
A1
A0
H
B2
A9
VSS
VSS
VSS
VSS
A4
A3
J
DK0
DK0#
VDD
VDD
VDD
VDD
B0
CK
K
DK1
DK1#
VDD
VDD
VDD
VDD
B1
CK#
L
REF#
CS#
VSS
VSS
VSS
VSS
A14
A13
M
WE#
A16
A17
VDD
VDD
A12
A11
A10
N
A18
DQ24
DQ25
VSSQ
VSSQ
DQ35
DQ34
A19
P
A15
DQ22
DQ23
VDDQ
VDDQ
DQ33
DQ32
DM
R
VSS
QK1
QK1#
VSSQ
VSSQ
DQ31
DQ30
VSS
T
VTT
DQ20
DQ21
VDDQ
VDDQ
DQ29
DQ28
VTT
U
VDD
DQ18
DQ19
VSSQ
VSSQ
DQ27
DQ26
VDD
V
VREF
ZQ
VEXT
VSS
VSS
VEXT
TDO
TDI
Notes:
1. Reserved for future use. This may optionally be connected to GND.
2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND.
Table 4: Ball Descriptions
Symbol
Type
Description
A0–A21
Input
Address inputs: A0–A21 define the row and column addresses for READ and WRITE
operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK.
BA0–BA2
Input
Bank address inputs: Select to which internal bank a command is being applied.
CK, CK#
Input
Input clock: CK and CK# are differential input clocks. Addresses and commands are
latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
CS#
Input
Chip select: CS# enables the command decoder when LOW and disables it when
HIGH. When the command decoder is disabled, new commands are ignored, but internal operations continue.
DK, DK#
Input
Input data clock: DK and DK# are the differential input data clocks. All input data is
referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For
the x36 device, DQ0–DQ17 are referenced to DK0 and DK0# and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18 devices, all DQs are referenced to DK
and DK#. All DKx and DKx# pins must always be supplied to the device.
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Ball Assignments and Descriptions
Table 4: Ball Descriptions (Continued)
Symbol
Type
Description
DM
Input
Input data mask: The DM signal is the input mask signal for WRITE data. Input data
is masked when DM is sampled HIGH. DM is sampled on both edges of DK (DK1 for
the x36 configuration). Tie signal to ground if not used.
TCK
Input
IEEE 1149.1 clock input: This ball must be tied to Vss if the JTAG function is not used.
TMS, TDI
Input
IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function
is not used.
WE#, REF#
Input
Command inputs: Sampled at the positive edge of CK, WE# and REF# define (together with CS#) the command to be executed.
DQ0–DQ35
I/O
Data input: The DQ signals form the 36-bit data bus. During READ commands, the
data is referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of DK.
QKx, QKx#
Output
Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They
are free-running, and during READs, are edge-aligned with data output from the
RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0
and QK0# are aligned with DQ0–DQ17, and QK1 and QK1# are aligned with DQ18–
DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0–DQ8, while QK1 and
QK1# are aligned with Q9–Q17. For the x9 device, all DQs are aligned with QK0 and
QK0#.
QVLD
Output
Data valid: The QVLD pin indicates valid output data. QVLD is edge-aligned with QKx
and QKx#.
TDO
Output
IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if the JTAG
function is not used.
ZQ
Reference
External impedance (25–60Ω
ΩThis signal is used to tune the device outputs to the
system data bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a
resistor from this signal to ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to VDD invokes the maximum impedance mode. Refer to
Mode Register Definition in Nonmultiplexed Address Mode to activate this function.
VDD
Supply
Power supply: Nominally, 1.8V. See DC Electrical Characteristics and Operating Conditions for range.
Vddq
Supply
DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise
immunity. See DC Electrical Characteristics and Operating Conditions for range.
VEXT
Supply
Power supply: Nominally, 2.5V. See DC Electrical Characteristics and Operating Conditions for range.
Vref
Supply
Input reference voltage: Nominally Vddq/2. Provides a reference voltage for the input buffers.
Vss
Supply
Ground.
VSSQ
Supply
DQ ground: Isolated on the device for improved noise immunity.
Vtt
Supply
Power supply: Isolated termination supply. Nominally, Vddq/2. See DC Electrical Characteristics and Operating Conditions for range.
A22
–
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Reserved for future use: This signal is not connected and may be connected to
ground.
14
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Ball Assignments and Descriptions
Table 4: Ball Descriptions (Continued)
Symbol
Type
DNU
–
Do not use: These balls may be connected to ground. Note that if ODT is enabled on
Rev. A die, these pins will be connected to Vtt. The DNU pins are High-Z on Rev. B die
when ODT is enabled.
NF
–
No function: These balls can be connected to ground.
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Description
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Package Dimensions
Package Dimensions
Figure 6: 144-Ball μBGA
10.6 CTR
10º TYP
Seating
plane
A
0.12 A
0.73 ±0.1
144X Ø0.51
Dimensions apply to
solder balls post-reflow
on Ø0.39 SMD
ball pads.
0.49 ±0.05
12 11 10 9
Ball A1 ID
4 3 2 1
Ball A1 ID
A
B
C
D
E
F
G
H
J
17 CTR
K
18.1 CTR
18.5 ±0.1
L
M
N
P
R
T
U
1 TYP
V
0.8 TYP
1.2 MAX
0.34 MIN
8.8 CTR
11 ±0.1
Notes:
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576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. All dimensions are in millimeters.
2. Solder Ball Material :
SAC305 (96.5% Sn, 3% Ag, 0.5% Cu) or
Eutectic (62% Sn, 36% Pb, 2% Ag)
16
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Package Dimensions
Figure 7: 144-Ball FBGA
Seating plane
A
144X Ø0.55
Dimensions apply
to solder balls postreflow on Ø0.40
NSMD ball pads.
0.12 A
Ball A1 ID
12 11 10
9
4
3
2
Ball A1 ID
1
A
B
C
D
E
F
G
H
18.5 ±0.1
J
K
17.0
CTR
L
M
N
P
R
T
U
1.0 TYP
V
1.1 ±0.1
0.8 TYP
8.8 CTR
0.3 MIN
11 ±0.1
Notes:
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576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. All dimensions are in millimeters.
2. Solder Ball Material :
SAC302 (96.8% Sn, 3% Ag, 0.2% Cu) or
Eutectic (62% Sn, 36% Pb, 2% Ag)
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Electrical Specifications – IDD
Electrical Specifications – IDD
Table 5: IDD Operating Conditions and Maximum Limits – Rev. A
Description
Condition
Standby current
tCK
Symbol
-18
-25E
-25
-33
Units
ISB1 (VDD) x9/x18
55
53
48
48
mA
ISB1 (VDD) x36
55
53
48
48
ISB1 (VEXT)
5
5
5
5
CS# = 1; No commands; Bank address incremented and half address/data change once every
four clock cycles
ISB2 (VDD) x9/x18
365
293
288
233
ISB2 (VDD) x36
365
293
288
233
ISB2 (VEXT)
5
5
5
5
BL = 2; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD1 (VDD) x9/x18
465
380
348
305
IDD1 (VDD) x36
485
400
374
343
IDD1 (VEXT)
15
15
15
13
BL = 4; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD2 (VDD) x9/x18
475
400
362
319
IDD2 (VDD) x36
510
425
418
389
IDD2 (VEXT)
15
15
15
13
BL = 8; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD3 (VDD) x9/x18
505
430
408
368
IDD3 (VDD) x36
625
540
460
425
IDD3 (VEXT)
20
20
20
18
Burst refresh cur- Eight bank cyclic refresh; Continrent
uous address/data; Command bus
remains in refresh for all eight
banks
IREF1 (VDD) x9/x18
995
790
785
615
IREF1 (VDD) x36
995
915
785
615
IREF1 (VEXT)
80
80
80
70
Distributed refresh current
Single bank refresh; Sequential
bank access; Half address transitions once every tRC; Continuous
data
IREF2 (VDD) x9/x18
425
330
325
267
IREF2 (VDD) x36
425
390
326
281
IREF2 (VEXT)
20
20
20
18
Operating burst
write current example
BL = 2; Cyclic bank access; Half of
address bits change every clock
cycle; Continuous data; Measurement is taken during continuous
WRITE
IDD2W (VDD) x9/x18
1335
980
970
819
IDD2W (VDD) x36
1545
1,105
1,100
914
IDD2W (VEXT)
50
50
50
40
Operating burst
write current example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during
continuous WRITE
IDD4W (VDD) x9/x18
985
785
779
609
IDD4W (VDD) x36
1185
887
882
790
IDD4W (VEXT)
30
30
30
25
Active standby
current
Operational current
Operational current
Operational current
= idle; All banks idle; No inputs toggling
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Electrical Specifications – IDD
Table 5: IDD Operating Conditions and Maximum Limits – Rev. A (Continued)
Description
Condition
Symbol
-18
-25E
-25
-33
Units
Operating burst
write current example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during
continuous WRITE
IDD8W (VDD) x9/x18
770
675
668
525
mA
IDD8W (VDD) x36
1095
755
750
580
IDD8W (VEXT)
30
30
30
25
Operating burst
read current example
BL = 2; Cyclic bank access; Half of
address bits change every clock
cycle; Continuous data; Measurement is taken during continuous
READ
IDD2R (VDD) x9/x18
1225
940
935
735
IDD2R (VDD) x36
1270
995
990
795
IDD2R (VEXT)
50
50
50
40
Operating burst
read current example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during
continuous READ
IDD4R (VDD) x9/x18
860
685
680
525
IDD4R (VDD) x36
920
735
730
660
IDD4R (VEXT)
30
30
30
25
Operating burst
read current example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during
continuous READ
IDD8R (VDD) x9/x18
655
575
570
450
IDD8R (VDD) x36
855
665
660
505
IDD8R (VEXT)
30
30
30
25
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mA
mA
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Electrical Specifications – IDD
Table 6: IDD Operating Conditions and Maximum Limits – Rev. B
Description
Condition
Standby current
tCK
Symbol
-18
-25E
-25
-33
Units
ISB1 (VDD) x9/x18
55
55
55
55
mA
ISB1 (VDD) x36
55
55
55
55
ISB1 (VEXT)
5
5
5
5
CS# = 1; No commands; Bank address incremented and half address/data change once every
four clock cycles
ISB2 (VDD) x9/x18
250
215
215
190
ISB2 (VDD) x36
250
215
215
190
ISB2 (VEXT)
5
5
5
5
BL = 2; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD1 (VDD) x9/x18
310
285
260
225
IDD1 (VDD) x36
320
295
270
230
IDD1 (VEXT)
10
10
10
10
BL = 4; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD2 (VDD) x9/x18
315
290
260
220
IDD2 (VDD) x36
330
305
275
230
IDD2 (VEXT)
10
10
10
10
BL = 8; Sequential bank access;
Bank transitions once every tRC;
Half address transitions once every tRC; Read followed by write
sequence; Continuous data during WRITE commands
IDD3 (VDD) x9/x18
330
305
275
230
IDD3 (VDD) x36
390
365
320
265
IDD3 (VEXT)
15
15
15
15
Burst refresh cur- Eight bank cyclic refresh; Continrent
uous address/data; Command bus
remains in refresh for all eight
banks
IREF1 (VDD) x9/x18
660
540
530
430
IREF1 (VDD) x36
670
545
535
435
IREF1 (VEXT)
45
30
30
25
Distributed refresh current
Single bank refresh; Sequential
bank access; Half address transitions once every tRC; Continuous
data
IREF2 (VDD) x9/x18
295
265
250
215
IREF2 (VDD) x36
295
265
250
215
IREF2 (VEXT)
10
10
10
10
Operating burst
write current example
BL = 2; Cyclic bank access; Half of
address bits change every clock
cycle; Continuous data; Measurement is taken during continuous
WRITE
IDD2W (VDD) x9/x18
830
655
655
530
IDD2W (VDD) x36
885
700
700
565
IDD2W (VEXT)
40
35
35
30
Operating burst
write current example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during
continuous WRITE
IDD4W (VDD) x9/x18
580
465
465
385
IDD4W (VDD) x36
635
510
510
420
IDD4W (VEXT)
25
20
20
20
Active standby
current
Operational current
Operational current
Operational current
= idle; All banks idle; No inputs toggling
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mA
mA
mA
mA
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Electrical Specifications – IDD
Table 6: IDD Operating Conditions and Maximum Limits – Rev. B (Continued)
Description
Condition
Symbol
-18
-25E
-25
-33
Units
Operating burst
write current example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during
continuous WRITE
IDD8W (VDD) x9/x18
445
370
370
305
mA
IDD8W (VDD) x36
560
455
455
375
IDD8W (VEXT)
25
20
20
20
Operating burst
read current example
BL = 2; Cyclic bank access; Half of
address bits change every clock
cycle; Continuous data; Measurement is taken during continuous
READ
IDD2R (VDD) x9/x18
805
640
640
515
IDD2R (VDD) x36
850
675
675
540
IDD2R (VEXT)
40
35
35
30
Operating burst
read current example
BL = 4; Cyclic bank access; Half of
address bits change every two
clock cycles; Continuous data;
Measurement is taken during
continuous READ
IDD4R (VDD) x9/x18
545
440
440
365
IDD4R (VDD) x36
590
475
475
390
IDD4R (VEXT)
25
20
20
20
Operating burst
read current example
BL = 8; Cyclic bank access; Half of
address bits change every four
clock cycles; Continuous data;
Measurement is taken during
continuous READ
IDD8R (VDD) x9/x18
410
335
335
280
IDD8R (VDD) x36
525
425
425
350
IDD8R (VEXT)
25
20
20
20
Notes:
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mA
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1. IDD specifications are tested after the device is properly initialized. +0°C ≤ TC ≤ +95°C;
+1.7V ≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ VDD, VREF = VDDQ/2.
2. tCK = tDK = MIN, tRC = MIN.
3. Input slew rate is specified in the Input AC Logic Levels table.
4. Definitions for IDD conditions:
– LOW = VIN ≤ VIL(AC) MAX.
– HIGH = VIN ≥ VIH(AC) MIN.
– Stable = Inputs remain at a HIGH or LOW level.
– Floating = Inputs at VREF = VDDQ/2.
– Continuous data = Half the DQ signals changing between HIGH and LOW every
half clock cycle (twice per clock).
– Continuous address = Half the address signals changing between HIGH and LOW
every clock cycle (once per clock).
– Sequential bank access = Bank address increments by one every tRC.
– Cyclic bank access = Bank address increments by one for each command access. For
BL = 2 this is every clock, for BL = 4 this is every other clock, and for BL = 8 this is
every fourth clock.
5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than once per clock cycle.
6. IDD parameters are specified with ODT disabled.
7. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at
nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified.
8. IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are tested for the specified AC input levels under normal use conditions. The
minimum slew rate for the input signals used to test the device is 2 V/ns in the range
between VIL(AC) and VIH(AC).
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Absolute Maximum Ratings
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Table 7: Absolute Maximum Ratings
Parameter
Min
Max
Units
I/O voltage
–0.3
VDDQ + 0.3
V
Voltage on VEXT supply relative to VSS
–0.3
+2.8
V
Voltage on VDD supply relative to VSS
–0.3
+2.1
V
Voltage on VDDQ supply relative to VSS
–0.3
+2.1
V
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AC and DC Operating Conditions
AC and DC Operating Conditions
Table 8: DC Electrical Characteristics and Operating Conditions
Note 1 applies to the entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Conditions
Symbol
Min
Max
Units
Notes
Supply voltage
–
VEXT
2.38
2.63
V
Supply voltage
–
VDD
1.7
1.9
V
2
Isolated output buffer
supply
–
VDDQ
1.4
VDD
V
2, 3
Reference voltage
–
VREF
0.49 × VDDQ
0.51 × VDDQ
V
4, 5, 6
Termination voltage
–
VTT
0.95 × VREF
1.05 × VREF
V
7, 8
Input high (logic 1) voltage
–
VIH
VREF + 0.1
VDDQ + 0.3
V
2
Input low (logic 0) voltage
–
VIL
VSSQ - 0.3
VREF - 0.1
V
2
Output high current
VOH = VDDQ/2
IOH
(VDDQ/2)/(1.15 (VDDQ/2)/(0.85
× RQ/5)
× RQ/5)
A
9, 10, 11
Output low current
VOL = VDDQ/2
IOL
(VDDQ/2)/(1.15 (VDDQ/2)/(0.85
× RQ/5)
× RQ/5)
A
9, 10, 11
Clock input leakage current
0V ≤ VIN ≤ VDD
ILC
–5
5
μA
Input leakage current
0V ≤ VIN ≤ VDD
ILI
–5
5
μA
Output leakage current
0V ≤ VIN ≤ VDDQ
ILO
–5
5
μA
Reference voltage current
–
IREF
–5
5
μA
Notes:
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1. All voltages referenced to VSS (GND).
2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ –0.5V for t ≤ tCK/2.
During normal operation, VDDQ must not exceed VDD. Control input signals may not
have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX).
3. VDDQ can be set to a nominal 1.5V ± 0.1V or 1.8V ± 0.1V supply.
4. Typically the value of VREF is expected to be 0.5 x VDDQ of the transmitting device. VREF is
expected to track variations in VDDQ.
5. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(DC).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the
DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed
±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±2% VDDQ/2 for DC error and
an additional ±2% VDDQ/2 for AC noise. This measurement is to be taken at the nearest
VREF bypass capacitor.
7. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
8. On-die termination may be selected using mode register bit 9 (see the Mode Register
Definition in Nonmultiplexed Address Mode figure). A resistance RTT from each data input signal to the nearest VTT can be enabled. RTT –Ω at 95°C TC.
9. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from
the device, IOL flows into the device.
10. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor.
11. For VO0L and VOH, refer to the RLDRAM 2 HSPICE or IBIS driver models.
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AC and DC Operating Conditions
Table 9: Input AC Logic Levels
Notes 1–3 apply to entire table; Unless otherwise noted: +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Description
Symbol
Min
Max
Units
Input high (logic 1) voltage
VIH
VREF + 0.2
–
V
Input low (logic 0) voltage
VIL
–
VREF - 0.2
V
Notes:
1. All voltages referenced to VSS (GND).
2. The AC and DC input level specifications are as defined in the HSTL standard (that is, the
receiver will effectively switch as a result of the signal crossing the AC input level, and
will remain in that state as long as the signal does not ring back above [below] the DC
input LOW [HIGH] level).
3. The minimum slew rate for the input signals used to test the device is 2 V/ns in the
range between VIL(AC) and VIH(AC). See illustration below:
VDDQ
VIH(AC) MIN
VSWING
VIL(AC) MAX
GND
Rise time:
2 V/ns
Fall time:
2 V/ns
Table 10: Differential Input Clock Operating Conditions
Notes 1–4 apply to the entire table; Unless otherwise noted: +0°C ≤ TC≤ +95°C; +1.7V ≤ VDD ≤ +1.9V
Parameter/Condition
Symbol
Min
Max
Units
Notes
Clock input voltage level: CK and CK#
VIN(DC)
–0.3
VDDQ + 0.3
V
Clock input differential voltage: CK and CK#
VID(DC)
0.2
VDDQ + 0.6
V
5
Clock input differential voltage: CK and CK#
VID(AC)
0.4
VDDQ + 0.6
V
5
Clock input crossing point voltage: CK and CK#
VIX(AC)
VDDQ/2 - 0.15
VDDQ/2 + 0.15
V
6
Notes:
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1. DKx and DKx# have the same requirements as CK and CK#.
2. All voltages referenced to VSS (GND).
3. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which
CK and CK# cross. The input reference level for signals other than CK/CK# is VREF.
4. CK and CK# input slew rate must be ≥2 V/ns (≥4 V/ns if measured differentially).
5. Vid is the magnitude of the difference between the input level on CK and the input level
on CK#.
6. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track
variations in the DC level of the same.
24
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AC and DC Operating Conditions
Figure 8: Clock Input
VIN(DC) MAX
Maximum clock level
CK#
X
VDDQ/2 + 0.15
VIX(AC) MAX
VDDQ/2
VDDQ/2A - 0.15
1
X
VID(DC)2
VID(AC)3
VIX(AC) MIN
CK
Minimum clock level
VIN(DC) MIN
Notes:
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1.
2.
3.
4.
CK and CK# must cross within this region.
CK and CK# must meet at least VID(DC) MIN when static and centered around Vddq/2.
Minimum peak-to-peak swing.
It is a violation to tristate CK and CK# after the part is initialized.
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Input Slew Rate Derating
Input Slew Rate Derating
The following tables define the address, command, and data setup and hold derating
values. These values are added to the default tAS/tCS/tDS and tAH/tCH/tDH specifications when the slew rate of any of these input signals is less than the 2 V/ns the nominal
setup and hold specifications are based upon.
To determine the setup and hold time needed for a given slew rate, add the tAS/tCS default specification to the “tAS/tCS V REF to CK/CK# Crossing” and the tAH/tCH default
specification to the “tAH/tCH CK/CK# Crossing to V REF” derated values on the Address
and Command Setup and Hold Derating Values table. The derated data setup and hold
values can be determined in a like manner using the “tDS V REF to CK/CK# Crossing”
and “tDH to CK/CK# Crossing to V REF” values on the Data Setup and Hold Derating Values table. The derating values on the Address and Command Setup and Hold Derating
Values table and the Data Setup and Hold Derating Values table apply to all speed
grades.
The setup times on the Address and Command Setup and Hold Derating Values table
and the Data Setup and Hold Derating Values table represent a rising signal. In this case,
the time from which the rising signal crosses V IH(AC) MIN to the CK/CK# cross point is
static and must be maintained across all slew rates. The derated setup timing represents
the point at which the rising signal crosses V REF(DC) to the CK/CK# cross point. This derated value is calculated by determining the time needed to maintain the given slew
rate and the delta between V IH(AC) MIN and the CK/CK# cross point. The setup values in
the Address and Command Setup and Hold Derating Values table and the Data Setup
and Hold Derating Values table are also valid for falling signals (with respect to V IL(AC)
MAX and the CK/CK# cross point).
The hold times in the Address and Command Setup and Hold Derating Values table and
the Data Setup and Hold Derating Values table represent falling signals. In this case, the
time from the CK/CK# cross point to when the signal crosses V IH(DC) MIN is static and
must be maintained across all slew rates. The derated hold timing represents the delta
between the CK/CK# cross point to when the falling signal crosses V REF(DC). This derated value is calculated by determining the time needed to maintain the given slew rate
and the delta between the CK/CK# cross point and V IH(DC). The hold values in The Address and Command Setup and Hold Derating Values table and the Data Setup and
Hold Derating Values table are also valid for rising signals (with respect to V IL(DC) MAX
and the CK and CK# cross point).
Note:
The above descriptions also pertain to data setup and hold derating when CK/CK# are
replaced with DK/DK#.
Table 11: Address and Command Setup and Hold Derating Values
Command/
Address Slew
Rate (V/ns)
tAS/tCS
tAS/tCS
VREF to
CK/CK# Crossing
VIH(AC)
MIN to CK/CK#
Crossing
tAH/tCH
CK/CK#
Crossing to VREF
CK/CK#
Crossing to VIH(DC)
MIN
Units
tAH/tCH
CK, CK# Differential Slew Rate: 2\.0 V/ns
2.0
0
–100
0
–50
ps
1.9
5
–100
3
–50
ps
1.8
11
–100
6
–50
ps
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Input Slew Rate Derating
Table 11: Address and Command Setup and Hold Derating Values (Continued)
Command/
Address Slew
Rate (V/ns)
tAS/tCS
tAH/tCH
VREF to
CK/CK# Crossing
VIH(AC)
MIN to CK/CK#
Crossing
CK/CK#
Crossing to VREF
CK/CK#
Crossing to VIH(DC)
MIN
Units
1.7
18
–100
9
–50
ps
1.6
25
–100
13
–50
ps
1.5
33
–100
17
–50
ps
1.4
43
–100
22
–50
ps
1.3
54
–100
27
–50
ps
1.2
67
–100
34
–50
ps
1.1
82
–100
41
–50
ps
1.0
100
–100
50
–50
ps
tAS/tCS
tAH/tCH
CK, CK# Differential Slew Rate: 1.5 V/ns
2.0
30
–70
30
–20
ps
1.9
35
–70
33
–20
ps
1.8
41
–70
36
–20
ps
1.7
48
–70
39
–20
ps
1.6
55
–70
43
–20
ps
1.5
63
–70
47
–20
ps
1.4
73
–70
52
–20
ps
1.3
84
–70
57
–20
ps
1.2
97
–70
64
–20
ps
1.1
112
–70
71
–20
ps
1.0
130
–70
80
–20
ps
CK, CK# Differential Slew Rate: 1.0 V/ns
2.0
60
–40
60
10
ps
1.9
65
–40
63
10
ps
1.8
71
–40
66
10
ps
1.7
78
–40
69
10
ps
1.6
85
–40
73
10
ps
1.5
93
–40
77
10
ps
1.4
103
–40
82
10
ps
1.3
114
–40
87
10
ps
1.2
127
–40
94
10
ps
1.1
142
–40
101
10
ps
1.0
160
–40
110
10
ps
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Input Slew Rate Derating
Table 12: Data Setup and Hold Derating Values
Data Slew Rate
(V/ns)
tDS
VREF to
CK/CK# Crossing
tDS
VIH(AC) MIN to
CK/CK# Crossing
tDH
CK/CK# Cross- tDH CK/CK# Crossing to VREF
ing to VIH(DC) MIN
Units
DK, DK# Differential Slew Rate: 2.0 V/ns
2.0
0
–100
0
–50
ps
1.9
5
–100
3
–50
ps
1.8
11
–100
6
–50
ps
1.7
18
–100
9
–50
ps
1.6
25
–100
13
–50
ps
1.5
33
–100
17
–50
ps
1.4
43
–100
22
–50
ps
1.3
54
–100
27
–50
ps
1.2
67
–100
34
–50
ps
1.1
82
–100
41
–50
ps
1.0
100
–100
50
–50
ps
DK, DK# Differential Slew Rate: 1.5 V/ns
2.0
30
–70
30
–20
ps
1.9
35
–70
33
–20
ps
1.8
41
–70
36
–20
ps
1.7
48
–70
39
–20
ps
1.6
55
–70
43
–20
ps
1.5
63
–70
47
–20
ps
1.4
73
–70
52
–20
ps
1.3
84
–70
57
–20
ps
1.2
97
–70
64
–20
ps
1.1
112
–70
71
–20
ps
1.0
130
–70
80
–20
ps
DK, DK# Differential Slew Rate: 1.0 V/ns
2.0
60
–40
60
10
ps
1.9
65
–40
63
10
ps
1.8
71
–40
66
10
ps
1.7
78
–40
69
10
ps
1.6
85
–40
73
10
ps
1.5
93
–40
77
10
ps
1.4
103
–40
82
10
ps
1.3
114
–40
87
10
ps
1.2
127
–40
94
10
ps
1.1
142
–40
101
10
ps
1.0
160
–40
110
10
ps
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Input Slew Rate Derating
Figure 9: Nominal tAS/tCS/tDS and tAH/tCH/tDH Slew Rate
VIH(AC) MIN
VREF to DC VREF to DC
region
region
VSWING (MAX)
VREF to AC
region
VREF to AC
region
VDDQ
VIH(DC) MIN
VREF(DC)
VIL(DC) MAX
VIL(AC) MAX
VSSQ
Table 13: Capacitance – μBGA
Notes 1–2 apply to entire table
Description
Symbol
Conditions
Min
Max
Units
Address/control input capacitance
CI
1.0
2.0
pF
Input/output capacitance (DQ, DM, and QK/QK#)
CO
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
3.0
4.5
pF
Clock capacitance (CK/CK#, and DK/DK#)
CCK
1.5
2.5
pF
CJTAG
1.5
4.5
pF
Jtag pins
Notes:
1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
Table 14: Capacitance – FBGA
Notes 1–2 apply to entire table
Description
Symbol
Conditions
Min
Max
Units
Address/control input capacitance
CI
1.5
2.5
pF
Input/output capacitance (DQ, DM, and QK/QK#)
CO
TA = 25°C; f = 100 MHz
VDD = VDDQ = 1.8V
3.5
5.0
pF
Clock capacitance (CK/CK#, and DK/DK#)
CCK
2.0
3.0
pF
CJTAG
2.0
5.0
pF
JTAG pins
Notes:
1. Capacitance is not tested on ZQ pin.
2. JTAG pins are tested at 50 MHz.
Table 15: AC Electrical Characteristics: -18, -25E, -25, -33
Notes 1–4 apply to the entire table
-18
Description
-25E
-25
-33
Symbol
Min
Max
Min
Max
Min
Max
Min
Input clock cycle time
tCK
1.875
5.7
2.5
5.7
2.5
5.7
3.3
Input data clock cycle
time
tDK
Max
Units Notes
Clock
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tCK
tCK
29
tCK
5.7
tCK
ns
10
ns
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Input Slew Rate Derating
Table 15: AC Electrical Characteristics: -18, -25E, -25, -33 (Continued)
Notes 1–4 apply to the entire table
-18
Description
-25E
-25
-33
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
tJITper
–100
100
–150
150
–150
150
–200
200
ps
400
ps
Clock jitter: period
tJITcc
Clock jitter: cycle-tocycle
tCKH,
200
300
300
Units Notes
5, 6
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
tCKL, tDKL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
Clock to input data
clock
tCKDK
–0.3
0.3
–0.45
0.5
–0.45
0.5
–0.45
1.2
ns
Mode register set cycle time to any command
tMRSC
6
–
6
–
6
–
6
–
tCK
tAS/tCS
0.3
–
0.4
–
0.4
–
0.5
–
ns
tDS
0.17
–
0.25
–
0.25
–
0.3
–
ns
tAH/tCH
0.3
–
0.4
–
0.4
–
0.5
–
ns
tDH
0.17
–
0.25
–
0.25
–
0.3
–
ns
Output data clock
HIGH time
tQKH
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKH
Output data clock
LOW time
tQKL
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCKL
Half-clock period
tQHP
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
MIN
(tQKH,
tQKL)
–
QK edge to clock
edge skew
tCKQK
–0.2
0.2
–0.25
0.25
–0.25
0.25
–0.3
0.3
ns
tQKQ0,
–0.12
0.12
–0.2
0.2
–0.2
0.2
–0.25
0.25
ns
7
tQKQ
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
8
tQKVLD
–0.22
0.22
–0.3
0.3
–0.3
0.3
–0.35
0.35
ns
Clock HIGH time
tDKH
Clock LOW time
Setup Times
Address/command
and input setup time
Data-in and data
mask to DK setup
time
Hold Times
Address/command
and input hold time
Data-in and data
mask to DK hold time
Data and Data Strobe
QK edge to output
data edge
QK edge to any output data edge
QK edge to QVLD
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tQKQ1
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Notes
Table 15: AC Electrical Characteristics: -18, -25E, -25, -33 (Continued)
Notes 1–4 apply to the entire table
-18
Description
Symbol
Data valid window
Min
-25E
Max
tQHP
Min
-25
Max
tQHP
Min
tQHP
-33
Max
Min
tQHP
Max
tDVW
(tQKQx
[MAX] + |
tQKQx
[MIN]|)
–
(tQKQx
[MAX] +
|tQKQx
[MIN]|)
–
(tQKQx
[MAX] +
|tQKQx
[MIN]|)
–
(tQKQx
[MAX] + |
tQKQx
[MIN]|)
–
tREFI
–
0.24
–
0.24
–
0.24
–
0.24
Units Notes
Refresh
Average periodic refresh interval
μs
9
Notes
1. All timing parameters are measured relative to the crossing point of CK/CK#,
DK/DK# and to the crossing point with V REF of the command, address, and data
signals.
2. Outputs measured with equivalent load:
VTT
50Ω
DQ
Test point
10pF
3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and
device operations are tested for the full voltage range specified.
4. AC timing may use a V IL-to-VIH swing of up to 1.5V in the test environment, but
input timing is still referenced to V REF (or to the crossing point for CK/CK#), and
parameter specifications are tested for the specified AC input levels under normal
use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between V IL(AC) and V IH(AC).
5. Clock phase jitter is the variance from clock rising edge to the next expected clock
rising edge.
6. Frequency drift is not allowed.
7. tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8 for the
x18 configuration. tQKQ1 is referenced to DQ18–DQ35 for the x36 configuration
and DQ9–DQ17 for the x18 configuration.
8. tQKQ takes into account the skew between any QKx and any Q.
9. To improve efficiency, eight AREF commands (one for each bank) can be posted
on consecutive cycles at periodic intervals of 1.95μs.
10. For Rev. A material, tCK MAX is 2.7ns at the -18 speed grade.
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Temperature and Thermal Impedance
Temperature and Thermal Impedance
It is imperative that the device’s temperature specifications are maintained in order to
ensure that the junction temperature is in the proper operating range to meet data
sheet specifications. An important step in maintaining the proper junction temperature
is using the device’s thermal impedances correctly. The thermal impedances are listed
for the available packages.
Using thermal impedances incorrectly can produce significant errors. Read Micron
technical note TN-00-08, “Thermal Applications,” prior to using the thermal impedances listed in the Temperature Limits table. For designs that are expected to last several
years and require the flexibility to use several DRAM die shrinks, consider using final
target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction.
The device’s safe junction temperature range can be maintained when the T C specification is not exceeded. In applications where the device’s ambient temperature is too
high, use of forced air and/or heat sinks may be required in order to satisfy the case
temperature specifications.
Table 16: Temperature Limits
Parameter
Storage temperature
Reliability junction temperature
Commercial
Symbol
Min
Max
Units
Notes
TSTG
–55
+150
°C
1
TJ
–
+110
°C
2
–
+110
°C
2
Industrial
Operating junction temperature
Commercial
TJ
Industrial
Operating case temperature
Commercial
TC
Industrial
Notes:
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0
+100
°C
3
–40
+100
°C
3
0
+95
°C
4, 5
–40
+95
°C
4, 5, 6
1. MAX storage case temperature; TSTG is measured in the center of the package, as shown
in the Example Temperature Test Point Location figure. This case temperature limit can
be exceeded briefly during package reflow, as noted in Micron technical note TN-00-15.
2. Temperatures greater than 110°C may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at or above this is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect the
reliability of the part.
3. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
4. MAX operating case temperature; TC is measured in the center of the package, as shown
in the Example Temperature Test Point Location figure.
5. Device functionality is not guaranteed if the device exceeds maximum TC during operation.
6. Both temperature specifications must be satisfied.
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Temperature and Thermal Impedance
Table 17: Thermal Impedance
Package
Substrate
θ JA (°C/W) Airflow = 0m/s
θ JA (°C/W) Airflow = 1m/s
θ JA (°C/W) Airflow = 2m/s
θ JB (°C/W)
θ JC (°C/W)
Rev. A
2-layer
45.4
31.5
26.3
15.1
1.5
4-layer
30.2
23.2
21.1
14.3
Note:
1. Thermal impedance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
Table 18: Thermal Impedance
Die Rev.
Package
μFBGA
Rev. B
FBGA
Θ JA (°C/W)
Airflow =
0m/s
Θ JA (°C/W)
Airflow =
1m/s
Θ JA (°C/W)
Airflow =
2m/s
Θ JB (°C/W)
Θ JC (°C/W)
Low
conductivity
53.7
42.0
37.7
N/A
3.9
High
conductivity
34.1
28.9
27.1
21.9
N/A
Low
conductivity
45.3
34.1
30.2
N/A
3.1
High
conductivity
28.2
23.2
21.5
17.3
N/A
Substrate
Note:
1. Thermal resistance data is based on a number of samples from multiple lots and should
be viewed as a typical number.
Figure 10: Example Temperature Test Point Location
Test point
18.50
9.25
5.50
11.00
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Commands
Commands
All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK.
Table 19: Description of Commands
Command
Description
Notes
1
DSEL/NOP The NOP command is used to perform a no operation, which essentially deselects the chip. Use the
NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history.
MRS
The mode register is set via the address inputs A0–A17. See Mode Register Definition in Nonmultiplexed Address Mode for further information. The MRS command can only be issued when all banks
are idle and no other operation is in progress.
READ
The READ command is used to initiate a burst read access to a bank. The value on the BA0–BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data location within the
bank.
2
WRITE
The WRITE command is used to initiate a burst write access to a bank. The value on the BA0–BA2 inputs selects the bank, and the address provided on inputs A0–An selects the data location within the
bank. Input data appearing on the DQ is written to the memory array subject to the DM input logic
level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data
will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be
ignored (that is, this part of the data word will not be written).
2
AREF
The AREF command is used during normal operation to refresh the memory content of a bank. The
command is nonpersistent, so it must be issued each time a refresh is required. The value on the BA0–
BA2 inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a “Don’t Care” during the AREF command. See AUTO REFRESH (AREF)
for more details.
Notes:
1. When the chip is deselected, internal NOP commands are generated and no commands
are accepted.
2. n = 21.
Table 20: Command Table
Notes 1–2 apply to the entire table
Operation
Device DESELECT/no operation
Code
CS#
WE#
REF#
A0–An2
BA0–BA2
Notes
DSEL/NOP
H
X
X
X
X
MRS
MRS
L
L
L
OPCODE
X
3
READ
READ
L
H
H
A
BA
4
WRITE
WRITE
L
L
H
A
BA
4
AREF
L
H
L
X
BA
AUTO REFRESH
Notes:
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1. X = “Don’t Care;” H = logic HIGH; L = logic LOW; A = valid address; BA = valid bank address.
2. n = 21.
3. Only A0–A17 are used for the MRS command.
4. Address width varies with burst length; see Burst Length for details.
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Commands
MODE REGISTER SET (MRS)
The mode register set stores the data for controlling the operating modes of the memory. It programs the device configuration, burst length, test mode, and I/O options. During an MRS command, the address inputs A0–A17 are sampled and stored in the mode
register. After issuing a valid MRS command, tMRSC must be met before any command
can be issued to the device. This statement does not apply to the consecutive MRS commands needed for internal logic reset during the initialization routine. The MRS command can only be issued when all banks are idle and no other operation is in progress.
Note: The data written by the prior burst length is not guaranteed to be accurate when
the burst length of the device is changed.
Figure 11: MODE REGISTER Command
CK#
CK
CS#
WE#
REF#
ADDRESS
OPCODE
BANK
ADDRESS
DON’T CARE
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Commands
Figure 12: Mode Register Definition in Nonmultiplexed Address Mode
A17
...
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
17–10
9 8 7 6 5
Reserved1 ODT IM DLL NA2 AM
4 3
BL
1
On
M7
0
Drive Impedance
Internal 50Ω5 (default)
0
DLL Reset
DLL reset4 (default)
1
External (ZQ)
1
DLL enabled
M8
Notes:
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Off (default)
1.
2.
3.
4.
5.
2 1 0
Config
Mode Register (Mx)
M2 M1 M0 Configuration
0 0 0 13 (default)
M9 On-Die Termination
0
Address Bus
0
0
1
13
0
1
0
2
0
1
1
3
1
0
0
43
1
0
1
5
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
M5
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
1
Multiplexed
0
1
4
1
0
8
1
1
Reserved
A10–A17 must be set to zero; A18–An = “Don’t Care.”
A6 not used in MRS.
BL = 8 is not available.
DLL RESET turns the DLL off.
±30% temperature variation.
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Commands
Configuration Tables
The following table shows the different configurations that can be programmed into the
mode register. The WRITE latency is equal to the READ latency plus one in each configuration in order to maximize data bus utilization. Bits M0, M1, and M2 are used to select the configuration during the MRS command.
Table 21: Cycle Time and READ/WRITE Latency Configuration Table
Notes 1–2 apply to the entire table
Configuration
13
2
3
43, 4
5
Units
tRC
4
6
8
3
5
tCK
tRL
4
6
8
3
5
tCK
tWL
5
7
9
4
6
tCK
266–175
400–175
533–175
200–175
333–175
MHz
Parameter
Valid frequency range
Notes:
1.
2.
3.
4.
tRC
< 20ns in any configuration only available with -25E and -18 speed grades.
Minimum operating frequency for the Die Rev. A -18 is 370 MHz.
BL = 8 is not available.
The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ
to the same bank. In this instance the minimum tRC is 4 cycles.
Burst Length (BL)
Burst length is defined by M3 and M4 of the mode register. Read and write accesses to
the device are burst-oriented, with the burst length being programmable to 2, 4, or 8.
The figure here illustrates the different burst lengths with respect to a READ command.
Changes in the burst length affect the width of the address bus.
Note: The data written by the prior burst length is not guaranteed to be accurate when
the burst length of the device is changed.
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Commands
Figure 13: Read Burst Lengths
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
NOP
NOP
NOP
NOP
Bank a,
Col n
ADDRESS
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
QK#
BL = 4
QK
QVLD
DO
an
DQ
QK#
BL = 8
QK
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
DON’T CARE
1. DO an = data-out from bank a and address an.
2. Subsequent elements of data-out appear after DO n.
3. Shown with nominal tCKQK.
Table 22: Address Widths at Different Burst Lengths
Burst Length
x9
x18
x36
2
A0–A21
A0–A20
A0–A19
4
A0–A20
A0–A19
A0–A18
8
A0–A19
A0–A18
A0–A17
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Commands
Address Multiplexing
Although the device has the ability to operate with an SRAM interface by accepting the
entire address in one clock, an option in the mode register can be set so that it functions
with multiplexed addresses, similar to a traditional DRAM. In multiplexed address
mode, the address can be provided to the device in two parts that are latched into the
memory with two consecutive rising clock edges. This provides the advantage of only
needing a maximum of 11 address balls to control the device, reducing the number of
signals on the controller side.
The data bus efficiency in continuous burst mode is only affected when using the BL = 2
setting because the device requires two clocks to read and write the data. The bank addresses are delivered to the device at the same time as the WRITE and READ commands
and the first address part, Ax. The 576Mb Address Mapping in Multiplexed Address
Mode table shows the addresses needed for both the first and second rising clock edges
(Ax and Ay, respectively).
The AREF command does not require an address on the second rising clock edge because only the bank address is needed during this command. Because of this, AREF
commands may be issued on consecutive clocks. The multiplexed address option is
available by setting bit M5 to 1 in the mode register. When this bit is set, the READ,
WRITE, and MRS commands follow the format described in Command Description in
Multiplexed Address Mode, which includes further information on operation with multiplexed addresses.
DLL RESET
DLL reset is selected with bit M7 of the mode register as shown in Mode Register Definition in Nonmultiplexed Address Mode table. The default setting for this option is LOW,
whereby the DLL is disabled. Once M7 is set HIGH, 1,024 cycles (5μs at 200 MHz) are
needed before a read command can be issued. This time allows the internal clock to be
synchronized with the external clock. Failing to wait for synchronization to occur may
result in a violation of the tCKQK parameter. A reset of the DLL is necessary if tCK or V dd
is changed after the DLL has already been enabled. To reset the DLL, an MRS command
must be issued where M7 is set LOW. After waiting tMRSC, a subsequent MRS command
should be issued whereby M7 goes high. 1,024 clock cycles are then needed before a
READ command is issued.
Drive Impedance Matching
The device is equipped with programmable impedance output buffers. This option is
selected by setting bit M8 HIGH during the MRS command. The purpose of the programmable impedance output buffers is to allow the user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is
connected between the ZQ ball and V SS. The value of the resistor must be five times the
desired impedance. For example, a 300Ω resistor is required for an output impedance of
60Ω. The range of RQ is 125–300Ω, which guarantees output impedance in the range of
25–60Ω (within 15%).
Output impedance updates may be required because over time variations may occur in
supply voltage and temperature. When the external drive impedance is enabled in the
MRS, the device will periodically sample the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and
current specifications are met during an update.
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Commands
When bit M8 is set LOW during the MRS command, the device provides an internal impedance at the output buffer of 50Ω (±30% with temperature variation). This impedance is also periodically sampled and adjusted to compensate for variation in supply
voltage and temperature.
On-Die Termination (ODT)
ODT is enabled by setting M9 to 1 during an MRS command. With ODT on, DQ and DM
pins are terminated to V TT with a resistance RTT. The command, address, QVLD, and
clock signals are not terminated. The figure here shows the equivalent circuit of a DQ
receiver with ODT. The ODT function is dynamically switched off when a DQ begins to
drive after a READ command is issued. Similarly, ODT is designed to switch on at DQ
after the device has issued the last piece of data. The DM pin will always be terminated.
See the Operations section for relevant timing diagrams.
Table 23: On-Die Termination DC Parameters
Description
Symbol
Min
Max
Termination voltage
VTT
0.95 × VREF
On-die termination
RTT
125
Notes:
Units
Notes
1.05 × VREF
V
1, 2
185
Ω
3
1. All voltages referenced to VSS (GND).
2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF.
3. The RTT value is measured at 95°C TC.
Figure 14: On-Die Termination-Equivalent Circuit
VTT
SW
RTT
Receiver
DQ
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Commands
WRITE
Write accesses are initiated with a WRITE command, as shown in the following figure.
The address needs to be provided during the WRITE command.
During WRITE commands, data will be registered at both edges of DK according to the
programmed burst length (BL). The device operates with a WRITE latency (WL) that is
one cycle longer than the programmed READ latency (RL + 1), with the first valid data
registered at the first rising DK edge WL cycles after the WRITE command.
Any WRITE burst may be followed by a subsequent READ command (assuming tRC is
met). To avoid external data bus contention, at least one NOP command is needed between the WRITE and READ commands. The WRITE-to-READ figure and the WRITE-toREAD (Separated by Two NOPs) figure illustrate the timing requirements for a WRITE
followed by a READ where one and two intermediary NOPs are required, respectively.
Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and
input data is masked if the corresponding DM signal is HIGH. The setup and
hold times for the DM signal are also tDS and tDH.
tDH. The
Figure 15: WRITE Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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Commands
READ
A READ command with an address initiates read access. During READ bursts, the memory device drives the read data so it is edge-aligned with the QKx signals. After a programmable READ latency, data is available at the outputs. One half clock cycle prior to
valid data on the read bus, the data valid signal, QVLD, transitions from LOW to HIGH.
QVLD is also edge-aligned with the QKx signals.
The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the
skew between QK0 and the last valid data edge generated at the DQ signals associated
with QK0 (tQKQ0 is referenced to DQ0–DQ17 for the x36 configuration and DQ0–DQ8
for the x18 configuration). tQKQ1 is the skew between QK1 and the last valid data edge
generated at the DQ signals associated with QK1 (tQKQ1 is referenced to DQ18–DQ35
for the x36 and DQ9–DQ17 for the x18 configuration). tQKQx is derived at each QKx
clock edge and is not cumulative over time. tQKQ is defined as the skew between either
QK differential pair and any output data edge.
After completion of a burst, assuming no other commands have been initiated, output
data (DQ) goes High-Z. The QVLD signal transitions LOW on the last bit of the READ
burst. Note that if CK/CK# violates the V id(DC) specification while a read burst is occurring, QVLD will remain HIGH until a dummy READ command is issued. The QK clocks
are free-running and will continue to cycle after the read burst is complete. Back-toback READ commands are possible, producing a continuous flow of output data. The
data valid window is derived from each QK transition and is defined as:
tQHP
- (tQKQ [MAX] + |tQKQ [MIN]|). See the Read Data Valid Window for x9 Device,
Read Data Valid Window for x18 Device, and Read Data Valid Window for x36 Device
figures for illustration.
Any READ burst may be followed by a subsequent WRITE command. The READ-toWRITE figure illustrates the timing requirements for a READ followed by a WRITE. Some
systems having long line lengths or severe skews may need additional idle cycles inserted between READ and WRITE commands to prevent data bus contention.
Figure 16: READ Command
CK#
CK
CS#
WE#
REF#
ADDRESS
A
BANK
ADDRESS
BA
DON’T CARE
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INITIALIZATION
AUTO REFRESH (AREF)
AREF is used to perform a REFRESH cycle on one row in a specific bank. Because the
row addresses are generated by an internal refresh counter for each bank, the external
address balls are “Don’t Care.” The bank addresses must be provided during the AREF
command, and is needed during the command so refreshing of the part can effectively
be hidden behind commands to other banks. The delay between the AREF command
and a subsequent command to the same bank must be at least tRC.
Within a period of 32ms (tREF), the entire device must be refreshed. The 576Mb device
requires 128K cycles at an average periodic interval of 0.24μs MAX (actual periodic refresh interval is 32ms/16K rows/8 = 0.244μs). To improve efficiency, eight AREF commands (one for each bank) can be posted to the device at periodic intervals of 1.95μs
(32ms/16K rows = 1.95μs). The figure here illustrates an example of a refresh sequence.
Figure 17: AUTO REFRESH Command
CK#
CK
CS#
WE#
REF#
ADDRESS
BANK
ADDRESS
BA
DON’T CARE
INITIALIZATION
The device must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for power-up:
1. Apply power (VEXT, V DD, V DDQ, V REF, V TT) and start clock as soon as the supply voltages are stable. Apply V DD and V EXT before or at the same time as V DDQ.1 Apply
VDDQ before or at the same time as V REF and V TT. Although there is no timing relation between V EXT and V DD, the chip starts the power-up sequence only after both
voltages approach their nominal levels. CK/CK# must meet VID(DC) prior to being
applied.2 Apply NOP conditions to command pins. Ensuring CK/CK# meet
VID(DC) while applying NOP conditions to the command pins guarantees that the
device will not receive unwanted commands during initialization.
2. Maintain stable conditions for 200μs (MIN).
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INITIALIZATION
3. Issue at least three consecutive MRS commands: two or more dummies plus one
valid MRS. The purpose of these consecutive MRS commands is to internally reset
the logic of the device. Note that tMRSC does not need to be met between these
consecutive commands. It is recommended that all address pins are held LOW
during the dummy MRS commands.
4. tMRSC after the valid MRS, an AUTO REFRESH command to all 8 banks (along
with 1,024 NOP commands) must be issued prior to normal operation. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP
commands) does not matter. As is required for any operation, tRC must be met between an AUTO REFRESH command and a subsequent VALID command to the
same bank. Note that older versions of the data sheet required each of these AUTO
REFRESH commands beseparated by 2,048 NOP commands. This properly initializes the device but is no longer required.
It is possible to apply V DDQ before V DD. However, when doing this, the DQ, DM, and all
other pins with an output driver, will go HIGH instead of tri-stating. These pins will remain HIGH until V DD is at the same level as V DDQ. Care should be taken to avoid bus
conflicts during this period.
If V ID(DC) on CK/CK# cannot be met prior to being applied to the device, placing a large
external resistor from CS# to V DD is a viable option for ensuring the command bus does
not receive unwanted commands during this unspecified state.
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INITIALIZATION
Figure 18: Power-Up/Initialization Sequence
Vext
Vdd
Vdd Q
Vref
Vtt
T0
T1
tCK
CK
tCKL
tCKH
T3
T2
CK#
T4
T6
T5
T8
T7
T9
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
tDKL
NOP
NOP
NOP
((
))
((
))
NOP
MRS
MRS
((
))
((
))
MRS
REF
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
VALID
((
))
((
))
VALID
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DQ
Rtt
High-Z
1,2
CODE
T = 200μs (MIN)
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2
CODE
tMRSC
Power-up:
Vdd and stable
clock (CK, CK#)
Notes:
1,2
CODE
VALID
Bank 0
((
))
((
))
Refresh
all banks5
Bank 7
1,024 NOP
commands
Indicates a break in
time scale
DON’T CARE
1.
2.
3.
4.
Recommend all address pins held LOW during dummy MRS commands.
A10–A17 must be LOW.
DLL must be reset if tCK or VDD are changed.
CK and CK# must be separated at all times to prevent bogus commands from being issued.
5. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent VALID command to the same bank.
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INITIALIZATION
Figure 19: Power-Up/Initialization Flow Chart
Step
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1
VDD, and VEXT ramp
2
VDDQ ramp
3
Apply VREF and VTT
4
Apply stable CK/CK# and DK/DK#
5
Wait at least 200μs
6
Issue MRS command—A10–A17 must be low
7
Issue MRS command—A10–A17 must be low
8
Desired load mode register with A10–A17 low
9
Assert NOP for tMRSC
10
Issue AUTO REFRESH to bank 0
11
Issue AUTO REFRESH to bank 1
12
Issue AUTO REFRESH to bank 2
13
Issue AUTO REFRESH to bank 3
14
Issue AUTO REFRESH to bank 4
15
Issue AUTO REFRESH to bank 5
16
Issue AUTO REFRESH to bank 6
17
Issue AUTO REFRESH to bank 7
18
Wait 1,024 NOP commands1
19
Valid command
Voltage rails
can be applied
simultaneously
46
MRS commands
must be on
consecutive clock
cycles
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576Mb: x9 x18 x36 CIO RLDRAM 2
WRITE
Note:
1. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent VALID command to the same bank.
WRITE
Figure 20: WRITE Burst
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T6n
T7
CK#
CK
t CKDK (NOM)
NOP
NOP
WL = 5
DK#
DK
DI
an
DQ
DM
t CKDK (MIN)
WL - tCKDK
DK#
DK
DI
an
DQ
DM
t CKDK (MAX)
WL + tCKDK
DK#
DK
DI
an
DQ
DM
TRANSITIONING DATA
Notes:
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576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
DON’T CARE
1. DI an = data-in for bank a and address n; subsequent elements of burst are applied following DI an.
2. BL = 4.
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WRITE
Figure 21: Consecutive WRITE-to-WRITE
T0
T1
T2
T3
WRITE
NOP
WRITE
NOP
T4
T5
T5n
T6
T6n
T7
T7n
T8
T8n
T9
CK#
CK
COMMAND
ADDRESS
Bank a,
Add n
Bank b,
Add n
WRITE
NOP
NOP
NOP
NOP
NOP
Bank a,
Add n
DK#
DK
t
RC = 4
WL = 5
WL = 5
DI
an
DQ
DI
bn
DI
an
DM
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
DON’T CARE
1.
2.
3.
4.
DI an (or bn) = data-in for bank a (or b) and address n.
Three subsequent elements of the burst are applied following DI for each bank.
BL = 4.
Each WRITE command may be to any bank; if the second WRITE is to the same bank,
tRC must be met.
5. Nominal conditions are assumed for specifications not defined.
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WRITE
Figure 22: WRITE-to-READ
T0
T1
T2
T3
T4
T5
COMMAND
WRITE
NOP
READ
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
T5n
T6
T6n
T7
CK#
CK
NOP
NOP
Bank b,
Add n
WL = 5
RL = 4
QK#
QK
DK#
DK
QVLD
DI
an
DQ
DO
bn
DM
DON’T CARE
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
5.
TRANSITIONING DATA
DI an = data-in for bank a and address n.
DO bn = data-out from bank b and address n.
Two subsequent elements of each burst follow DI an and DO bn.
BL = 2.
Nominal conditions are assumed for specifications not defined.
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WRITE
Figure 23: WRITE-to-READ (Separated by Two NOPs)
T0
T1
T2
T3
T4
T5
T5n
COMMAND
WRITE
NOP
NOP
READ
NOP
NOP
ADDRESS
Bank a,
Add n
T6
T7
NOP
NOP
T7n
T8
CK#
CK
NOP
Bank b,
Add n
WL = 5
tCKQK (MIN)
RL = 4
QK#
QK
DK#
DK
tCKDK (MAX)
QVLD
DI
an
DQ
DO
bn
DM
tDH
tQKQ (MIN)
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
DON’T CARE
1.
2.
3.
4.
5.
DI an = data-in for bank a and addressn.
DO bn = data-out from bank b and address n.
One subsequent element of each burst follow both DI an and DO bn.
BL = 2.
Only one NOP separating the WRITE and READ would have led to contention on the data bus because of the input and output data timing conditions being used.
6. Nominal conditions are assumed for specifications not defined.
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WRITE
Figure 24: WRITE – DM Operation
T1
T0
T2
T3
T4
NOP
NOP
T5
T6
T6n
T7
T7n
T8
CK#
CK
tCK
COMMAND
NOP
WRITE
tCH
NOP
tCL
NOP
NOP
NOP
NOP
Bank a,
Add n
ADDRESS
DK#
DK
tDKL
WL = 5
tDKH
DI
an
DQ
DM
tDS
tDH
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
DON’T CARE
DI an = data-in for bank a and address n.
Subsequent elements of burst are provided on following clock edges.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ
READ
Figure 25: Basic READ Burst Timing
T1
T0
T2
T3
T4
T5
NOP
NOP
T5n
T6
T6n
T7
CK#
CK
tCK
COMMAND
READ
NOP
tCH
tCL
NOP
READ
Bank a
Add n
ADDRESS
NOP
NOP
Bank a
Add n
RL = 4
tRC = 4
DM
t CKQK (MIN)
tCKQK (MIN)
QK#
QK
tQK
tQKH
tQKVLD
tQKL
tQKVLD
QVLD
DO
an
DQ
t CKQK (MAX)
tCKQK (MAX)
QK#
QK
tQK
tQKH
tQKL
QVLD
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
DON’T CARE
DO an = data-out from bank a and address an.
Three subsequent elements of the burst are applied following DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ
Figure 26: Consecutive READ Bursts (BL = 2)
T5n
T6n
T0
T1
T2
T3
T4
COMMAND
READ
READ
READ
READ
READ
READ
READ
ADDRESS
Bank a
Add n
Bank b
Add n
Bank c
Add n
Bank d
Add n
Bank e
Add n
Bank f
Add n
Bank g
Add n
CK#
T4n
T5
T6
CK
RL = 4
QVLD
QK#
QK
DO
an
DQ
DO
bn
DO
cn
TRANSITIONING DATA
Notes:
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn or cn) = data-out from bank a (or bank b or bank c) and address n.
One subsequent element of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
6. Data from the READ commands to bank d through bank g will appear on subsequent
clock cycles that are not shown.
Figure 27: Consecutive READ Bursts (BL = 4)
T0
T1
T2
T3
T4
COMMAND
READ
NOP
READ
NOP
READ
ADDRESS
Bank a
Add n
CK#
T4n
T5
T5n
T6n
T6
CK
Bank b
Add n
NOP
Bank c
Add n
READ
Bank d
Add n
RL = 4
QVLD
QK#
QK
DO
an
DQ
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
DO
bn
DON’T CARE
1.
2.
3.
4.
5.
DO an (or bn) = data-out from bank a (or bank b) and address n.
Three subsequent elements of the burst from each bank appears after each DO x.
Nominal conditions are assumed for specifications not defined.
Example applies only when READ commands are issued to same device.
Bank address can be to any bank, but the subsequent READ can only be to the same
bank if tRC has been met.
6. Data from the READ commands to banks c and d will appear on subsequent clock cycles
that are not shown.
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READ
Figure 28: READ-to-WRITE
T0
T1
T2
T3
T4
T5
T6
T7
T8
COMMAND
READ
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ADDRESS
Bank a,
Add n
CK#
CK
Bank b,
Add n
DM
QK#
QK
DK#
DK
RL = 4
WL = RL + 1 = 5
QVLD
DO
an
DQ
DI
bn
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
5.
DON’T CARE
DO an = data-out from bank a and address n.
DI bn = data-in for bank b and address n.
Three subsequent elements of each burst follow DI bn and each DO an.
BL = 4.
Nominal conditions are assumed for specifications not defined.
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READ
Figure 29: Read Data Valid Window for x9 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQKQ0 (MIN)2
tQHP1
tDVW3
tDVW3
tDVW3
tDVW3
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ8.
3. Minimum data valid window (tDVW) can be expressed as tQHP - (tQKQx [MAX] + |tQKQx
[MIN]|).
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READ
Figure 30: Read Data Valid Window for x18 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ8
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MIN)4
DQ9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
tDVW3
tDVW3
tDVW3
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ8.
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READ
3. Minimum data valid window (tDVW) can be expressed as tQHP - (tQKQx [MAX] + |
tQKQx [MIN]|).
4. tQKQ1 is referenced to DQ9–DQ17.
5. tQKQ takes into account the skew between any QKx and any DQ.
PDF: 09005aef80fe62fb
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READ
Figure 31: Read Data Valid Window for x36 Device
QK0#
QK0
tQKQ0 (MAX)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MAX)2
tQKQ0 (MIN)2
tQHP1
tQKQ0 (MIN)2
Lower word
DQ0
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ17
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
tDVW3
tDVW3
tDVW3
tQHP1
tQKQ1(MAX)4
tQKQ1(MIN)4
tQKQ1 (MIN)4
tDVW3
tDVW3
QK1#
QK1
tQKQ1 (MAX)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
tQKQ1 (MAX)4
tQKQ1 (MIN)4
tQHP1
Upper word
DQ18
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
DQ35
DQ (last valid data)
DQ (first valid data)
All DQs and QKs collectively
tDVW3
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
tDVW3
1. tQHP is defined as the lesser of tQKH or tQKL.
2. tQKQ0 is referenced to DQ0–DQ17.
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READ
3. Minimum data valid window, tDVW, can be expressed as tQHP - (tQKQx [MAX] + |tQKQx
[MIN]|).
4. tQKQ1 is referenced to DQ18–DQ35.
5. tQKQ takes into account the skew between any QKx and any DQ.
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AUTO REFRESH
AUTO REFRESH
Figure 32: AUTO REFRESH Cycle
T0
T1
CK
tCK
COMMAND
AREFx
AREFy
ADDRESS
BANK
BAx
T2
((
))
CK#
BAy
((
))
T3
tCH
ACx
DQ
DM
tRC
((
))
((
))
((
))
Indicates a break in
time scale
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ACy
((
))
((
))
DK, DK#
Notes:
tCL
DON’T CARE
1. AREFx = auto refresh command to bank x.
2. ACx = any command to bank x; ACy = any command to bank y.
3. BAx = bank address to bank x; BAy = bank address to bank y.
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On-Die Termination
On-Die Termination
Figure 33: READ Burst with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
NOP
NOP
NOP
T5
T5n
T6
T6n
T7
T7n
CK
COMMAND
ADDRESS
NOP
NOP
NOP
NOP
Bank a,
Col n
RL = 4
QK#
BL = 2
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT off
DQ ODT on
QK#
BL = 4
QK
QVLD
DO
an
DQ
DQ ODT
DQ ODT on
DQ ODT off
DQ ODT on
QK#
BL = 8
QK
QVLD
DO
an
DQ
DQ ODT off
DQ ODT on
DQ ODT
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
on
DON’T CARE
1. DO an = data out from bank a and address n.
2. DO an is followed by the remaining bits of the burst.
3. Nominal conditions are assumed for specifications not defined.
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On-Die Termination
Figure 34: READ-NOP-READ with ODT
T0
T1
T2
T3
T4
COMMAND
READ
WRITE
NOP
NOP
NOP
ADDRESS
Bank a
Add n
Bank b
Add n
T4n
T5
T6
NOP
NOP
T6n
T7
T8
NOP
NOP
T9
CK#
CK
RL = 4
WL = 5
DKx#
DKx
DO
an
DQ
DI
bn
QKx
QKx#
ODT
ODT on
ODT on
ODT off
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
UNDEFINED
DON’T CARE
DO an (or bn) = data-out from bank a (or bank b) and address n.
BL = 2.
One subsequent element of the burst appear after DO an and DO bn.
Nominal conditions are assumed for specifications not defined.
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On-Die Termination
Figure 35: READ-to-WRITE with ODT
CK#
T0
T1
T2
T3
T4
T4n
READ
NOP
READ
NOP
NOP
T5
T6
T6n
NOP
NOP
T7
CK
COMMAND
ADDRESS
Bank a,
Col n
NOP
NOP
Bank b,
Col n
RL = 4
QK#
QK
QVLD
DO
an
DQ
DQ ODT on
DQ ODT
DQ ODT off
DO
bn
DQ ODT on
DQ ODT off
TRANSITIONING DATA
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1.
2.
3.
4.
DQ ODT on
DON’T CARE
DO an = data-out from bank a and address n; DI bn = data-in for bank b and address n.
BL = 2.
One subsequent element of each burst appears after each DO an and DI bn.
Nominal conditions are assumed for specifications not defined.
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Multiplexed Address Mode
Multiplexed Address Mode
Figure 36: Command Description in Multiplexed Address Mode
READ
WRITE
MRS
REF
CK#
CK
CS#
WE#
REF#
ADDRESS
Ax
BANK
ADDRESS
BA
Ay
Ax
Ay
Ax
BA
BA
Ay
BA
DON’T CARE
Note:
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1. The minimum setup and hold times of the two address parts are defined tAS and tAH.
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Multiplexed Address Mode
Figure 37: Power-Up/Initialization Sequence in Multiplexed Address Mode
Vext
Vdd
Vdd Q
Vref
Vtt
T0
T1
tCK
CK
tCKH
T3
T2
CK#
tCKL
T4
T5
T6
T7
T8
T9
T10
T11
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tDK
DK#
DK
tDKH
COMMAND
NOP
tDKL
NOP
NOP
((
))
((
))
NOP
MRS
MRS
MRS
((
))
((
))
MRS
NOP
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
REF
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
DM
((
))
((
))
ADDRESS
((
))
((
))
BANK
ADDRESS
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
((
))
tMRSC
tMRSC
Refresh
all banks9
1,024 NOP
commands
DQ
Rtt
High-Z
CODE
1,2
1,2
CODE
T = 200μs (MIN)
CODE
2,3
((
))
((
))
Ax
2,4
Ay
2
Bank 0
((
))
((
))
((
))
((
))
Bank 7
VALID
VALID
VALID
5
5
5
Power-up:
Vdd and stable
clock (CK, CK#)
Indicates a break in
time scale
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
DON’T CARE
1. Recommended that all address pins held low during dummy MRS commands.
2. A10–A18 must be LOW.
3. Set address A5 HIGH. This enables the part to enter multiplexed address mode when in
non-multiplexed mode operation. Multiplexed address mode can also be entered at
some later time by issuing an MRS command with A5 HIGH. Once address bit A5 is set
HIGH, tMRSC must be satisfied before the two-cycle multiplexed mode MRS command is
issued.
4. Address A5 must be set HIGH. This and the following step set the desired mode register
once the device is in multiplexed address mode.
5. Any command or address.
6. The above sequence must be followed in order to power up the device in the multiplexed address mode.
7. DLL must be reset if tCK or VDD are changed.
8. CK and CK# must separated at all times to prevent bogus commands from being issued.
9. The sequence of the eight AUTO REFRESH commands (with respect to the 1,024 NOP
commands) does not matter. As is required for any operation, tRC must be met between
an AUTO REFRESH command and a subsequent VALID command to the same bank.
65
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Multiplexed Address Mode
Figure 38: Mode Register Definition in Multiplexed Address Mode
A5 A4 A3
A0
Ax A18 . . . A10 A9 A8
Ay A18 . . . A10
A9 A8
A4 A3
18–10
9 8 7 6 5
Reserved1 ODT IM DLL NA5 AM
4
0
1
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1
0
Mode Register (Mx)
Config
M2
M1
M0
Off (default)
0
0
0
Configuration
12 (default)
1
On
0
0
1
12
0
1
0
2
0
1
1
3
DLL Reset
DLL reset4 (default)
1
0
0
42
1
0
1
5
DLL enabled
1
1
0
Reserved
1
1
1
Reserved
M4 M3
Burst Length
Drive Impedance
Internal 50Ω3 (default)
External (ZQ)
1.
2.
3.
4.
5.
6.
7.
2
0
M9 On-Die Termination
M8
3
BL
M7
0
1
M5
Address MUX
0
Nonmultiplexed (default)
0
0
2 (default)
1
Multiplexed
0
1
4
1
0
8
1
1
Reserved
Bits A10–A18 must be set to zero.
BL = 8 is not available.
±30% temperature variation.
DLL RESET turns the DLL off.
Ay8 not used in MRS.
BA0–BA2 are “Don’t Care.”
Addresses A0, A3, A4, A5, A8, and A9 must be set as shown in order to activate the
mode register in the multiplexed address mode.
66
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2015 Micron Technology, Inc. All rights reserved.
576Mb: x9 x18 x36 CIO RLDRAM 2
Multiplexed Address Mode
Address Mapping in Multiplexed Address Mode
Table 24: 576Mb Address Mapping in Multiplexed Address Mode
Data
Burst
Width Length
x36
2
4
8
x18
2
4
8
x9
2
4
8
Address
Ball
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
X
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
X
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
A21
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
A20
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Ax
A0
A3
A4
A5
A8
A9
A10
A13
A14
A17
A18
Ay
X
A1
A2
X
A6
A7
A19
A11
A12
A16
A15
Note:
1. X = “Don’t Care.”
Configuration Tables in Multiplexed Address Mode
In multiplexed address mode, read and write latencies increase by one clock cycle, but
device cycle time remains the same as when in non-multiplexed address mode.
Table 25: Cycle Time and READ/WRITE Latency Configuration Table in Multiplexed Mode
Notes 1–2 apply to the entire table
Configuration
Parameter
13
2
3
43, 4
5
tRC
4
6
8
3
5
tCK
Units
tRL
5
7
9
4
6
tCK
tWL
6
8
10
5
7
tCK
Valid frequency range
266–175
400–175
533–175
200–175
333–175
MHz
Notes:
PDF: 09005aef80fe62fb
576Mb_RLDRAM_2_CIO_D1.pdf - Rev. M 09/15
1. tRC
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