288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Features
288Mb CIO Reduced Latency (RLDRAM® II)
MT49H8M36 MT49H16M18 MT49H32M9
For the latest data sheet, refer to Micron’s Web site: www.micron.com/rldram
Features
• 400 MHz DDR operation (800 Mb/s/pin data rate) • Organization 8 Meg x 36, 16 Meg x 18, and 32 Meg x 9 8 banks • Cyclic bank switching for maximum bandwidth • Reduced cycle time (20ns at 400 MHz) • Nonmultiplexed addresses (address multiplexing option available) • SRAM-type interface • Programmable READ latency (RL), row cycle time, and burst sequence length • Balanced READ and WRITE latencies in order to optimize data bus utilization • Data mask for WRITE commands • Differential input clocks (CK, CK#) • Differential input data clocks (DKx, DKx#) • On-chip DLL generates CK edge-aligned data and output data clock signals • Data valid signal (QVLD) • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) • 144-ball µBGA package • HSTL I/O (1.5V or 1.8V nominal) • 25Ω–60Ω matched impedance outputs • 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O • On-die termination (ODT) RTT Table 1: Valid Part Numbers
Description 8 Meg x 36 RLDRAM II 16 Meg x 18 RLDRAM II 32 Meg x 9 RLDRAM II
Figure 1:
144-Ball µBGA
Options
• Clock cycle timing 2.5ns (400 MHz) 3.3ns (300 MHz) 5ns (200 MHz) • Configuration 8 Meg x 36 16 Meg x 18 32 Meg x 9 • Operating temperature range Commercial 0° to +95°C Industrial TC = -40°C to +95°C TA = -40°C to 85°C) • Package 144-ball µBGA (11mm x 18.5mm, lead-free)
Marking
-25 -33 -5 MT49H8M36 MT49H16M18 MT49H32M9 None IT
Part Number MT49H8M36FM-xx MT49H16M18FM-xx MT49H32M9FM-xx
FM BM1
Notes: 1. Contact Micron for availability of lead-free products.
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36_1.fm - Rev. H 8/05 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Table of Contents Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Assignment and Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Programmable Impedance Output Buffer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Clock Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Mode Register Set Command (MRS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Write Basic Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Read Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AUTO REFRESH Command (AREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 On-Die Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Operation with Multiplexed Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 REFRESH Command in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Disabling the JTAG Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Performing a TAP RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 TAP Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Identification (ID) Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 TAP Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 EXTEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 High-Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 CLAMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 SAMPLE/PRELOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 BYPASS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Reserved for Future Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36TOC.fm - Rev. H 8/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II List of Figures List of Figures
Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8 Meg x 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Clock/Input Data Clock Command/Address Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Clock Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Mode Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Mode Register Bit Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Basic WRITE Burst/DM Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITE Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . .20 WRITE Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . .21 WRITE Followed By READ: BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 WRITE Followed By READ: BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Basic READ Burst Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 READ Burst: BL = 2, RL = 4, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 READ Burst: BL = 4, RL = 4, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 READ followed by WRITE, BL = 2, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ followed by WRITE, BL = 4, RL = 4, WL = 5, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AUTO REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 AUTO REFRESH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 On-Die Termination-Equivalent Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ Burst with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 READ NOP READ with ODT: BL = 2, Configuration 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 READ NOP NOP READ with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 READ followed by WRITE with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE followed by READ with ODT: BL = 2, Configuration 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Command Description in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Mode Register Set Command in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Power-Up Sequence in Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Burst REFRESH Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, WL = 6 . . . . . .35 READ Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, RL = 5. . . . . . . .35 TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 TAP Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 TAP Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Output Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Input Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36LOF.fm - Rev. H 8/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II List of Tables List of Tables
Table 1: Table 2: Table 3: Table 4: Table 5: Table 7: Table 8: Table 9: Table 10: Table 11: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Table 25: Valid Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 8 Meg x 36 Ball Assignment (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 16 Meg x 18 Ball Assignment (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 32 Meg x 9 Ball Assignment (Top View) 144-Ball µBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 RLDRAM Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Address Mapping in Multiplexed Address Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Configuration Table In Multiplexed Address Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 TAP AC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 TAP AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 TAP DC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Identification Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Scan Register Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Instruction Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Boundary Scan (Exit) Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 DC Electrical Characteristics and Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 AC Electrical Characteristics and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 IDD Operating Conditions and Maximum Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II General Description
General Description
The Micron® 288Mb reduced latency DRAM (RLDRAM®) II is a high-speed memory device designed for high bandwidth communication data storage—telecommunications, networking, and cache applications, etc. The chip’s 8-bank architecture is optimized for high speed and achieves a peak bandwidth of 28.8 Gb/s, using a 36-bit interface and a maximum system clock of 400 MHz. The double data rate (DDR) interface transfers two 36-, 18-, or 9-bit wide data word per clock cycle at the I/O pins. Output data is referenced to the free-running output data clock. Commands, addresses, and control signals are registered at every positive edge of the differential input clock, while input data is registered at both positive and negative edges of the input data clock(s). Read and write accesses to the RLDRAM are burst-oriented. The burst length is programmable from 2, 4, or 81 by setting the mode register. The device is supplied with 2.5V and 1.8V for the core and 1.5V or 1.8V for the output drivers. Bank-scheduled refresh is supported with row address generated internally. A standard µBGA 144-ball package is used to enable ultra high-speed data transfer rates and a simple upgrade path from former products. Notes: 1. Burst of 8 on x18 and x9 devices only.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Functional Block Diagram
Functional Block Diagram
Figure 2: 8 Meg x 36
A0–A18 , B0, B1, B2
1
Column Address Counter
Column Address Buffer
Row Address Buffer
Refresh Counter
Row Decoder Sense Amp and Data Bus Sense Amp and Data Bus Memory Array Column Decoder Bank 0
Row Decoder Sense Amp and Data Bus Memory Array Column Decoder Bank 1
Row Decoder Memory Array Bank 2 Column Decoder Sense Amp and Data Bus
Row Decoder Memory Array Bank 3
Column Decoder
Row Decoder Sense Amp and Data Bus Sense Amp and Data Bus Memory Array Column Decoder Bank 4
Row Decoder Sense Amp and Data Bus Memory Array Column Decoder Bank 5
Row Decoder Memory Array Bank 6 Column Decoder Sense Amp and Data Bus
Row Decoder Memory Array Bank 7
Column Decoder
Output Data Valid
Output Data Clock
Input Buffers
Output Buffers
Control Logic and Timing Generator
DK[1:0]
DK#[1:0]
REF#
QVLD
QK[1:0], QK#[1:0]
DQ0–DQ35
Notes: 1. When the BL = 4 setting is used, A18 is a “Don’t Care.“
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VREF
CK
CK#
WE#
CS#
DM
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Ball Assignment and Description
Ball Assignment and Description
Table 2: 8 Meg x 36 Ball Assignment (Top View) 144-Ball µBGA
1 A B C D E F G H J K L M N P R T U V VREF VDD VTT (A22)1 (A21)2 A5 A8 B2 DK0 DK1 REF# WE# A18 A15 VSS VTT VDD VREF 2 VSS DQ8 DQ10 DQ12 DQ14 DQ16 A6 A9 DK0# DK1# CS# A16 DQ24 DQ22 QK1 DQ20 DQ18 ZQ 3 VEXT DQ9 DQ11 DQ13 DQ15 DQ17 A7 VSS VDD VDD VSS A17 DQ25 DQ23 QK1# DQ21 DQ19 VEXT 4 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 5 6 7 8 9 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 10 VEXT DQ1 DQ3 QK0# DQ5 DQ7 A2 VSS VDD VDD VSS A12 DQ35 DQ33 DQ31 DQ29 DQ27 VEXT 11 TMS DQ0 DQ2 QK0 DQ4 DQ6 A1 A4 B0 B1 A14 A11 DQ34 DQ32 DQ30 DQ28 DQ26 TDO 12 TCK VDD VTT VSS (A20)2 QVLD A0 A3 CK CK# A13 A10 (A19)2 DM VSS VTT VDD TDI
Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Ball Assignment and Description
Table 3: 16 Meg x 18 Ball Assignment (Top View) 144-Ball µBGA
1 A B C D E F G H J K L M N P R T U V VREF VDD VTT (A22)1 (A21)2 A5 A8 B2 NF3 DK REF# WE# A18 A15 VSS VTT VDD VREF 2 VSS DNU4 DNU4 DNU4 DNU4 DNU4 A6 A9 NF3 DK# CS# A16 DNU4 DNU4 QK1 DNU4 DNU4 ZQ 3 VEXT DQ4 DQ5 DQ6 DQ7 DQ8 A7 VSS VDD VDD VSS A17 DQ14 DQ15 QK1# DQ16 DQ17 VEXT 4 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 5 6 7 8 9 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 10 VEXT DQ0 DQ1 QK0# DQ2 DQ3 A2 VSS VDD VDD VSS A12 DQ9 DQ10 DQ11 DQ12 DQ13 VEXT 11 TMS DNU4 DNU4 QK0 DNU4 DNU4 A1 A4 B0 B1 A14 A11 DNU4 DNU4 DNU4 DNU4 DNU4 TDO 12 TCK VDD VTT VSS (A20)2 QVLD A0 A3 CK CK# A13 A10 A19 DM VSS VTT VDD TDI
Notes: 1. Reserved for future use. This may optionally be connected to GND. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to GND 3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. 4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Ball Assignment and Description
Table 4: 32 Meg x 9 Ball Assignment (Top View) 144-Ball µBGA
1 A B C D E F G H J K L M N P R T U V VREF VDD VTT (A22)1 (A21)2 A5 A8 B2 NF3 DK REF# WE# A18 A15 VSS VTT VDD VREF 2 VSS DNU4 DNU4 DNU4 DNU4 DNU4 A6 A9 NF3 DK# CS# A16 DNU4 DNU4 DNU4 DNU4 DNU4 ZQ 3 VEXT DNU4 DNU4 DNU4 DNU4 DNU4 A7 VSS VDD VDD VSS A17 DNU4 DNU4 DNU4 DNU4 DNU4 VEXT 4 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 5 6 7 8 9 VSS VSSQ VDDQ VSSQ VDDQ VSSQ VDD VSS VDD VDD VSS VDD VSSQ VDDQ VSSQ VDDQ VSSQ VSS 10 VEXT DQ0 DQ1 QK0# DQ2 DQ3 A2 VSS VDD VDD VSS A12 DQ4 DQ5 DQ6 DQ7 DQ8 VEXT 11 TMS DNU4 DNU4 QK0 DNU4 DNU4 A1 A4 B0 B1 A14 A11 DNU4 DNU4 DNU4 DNU4 DNU4 TDO 12 TCK VDD VTT VSS A20 QVLD A0 A3 CK CK# A13 A10 A19 DM VSS VTT VDD TDI
Notes: 1. Reserved for future use. This signal is not connected. 2. Reserved for future use. This signal is internally connected and has parasitic characteristics of a clock input signal. 3. No Function. This signal is internally connected and has parasitic characteristics of a clock input signal. 4. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to GND.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Ball Assignment and Description
Table 5:
Symbol CK, CK# CS#
Ball Descriptions
Type Input Description
WE#, REF# A[0:20]
A21 A22 BA[0:2] DQ0–DQ35
QKx, QKx#
DKx, DKx#
DM
QVLD TMS TDI TCK TDO ZQ
VREF VEXT VDD
Input clock: CK and CK# are differential clock inputs. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. Input Chip select: CS# enables the command decoder when LOW and disables it when HIGH. When the command decoder is disabled, new commands are ignored, but internal operations continue. Input Command inputs: Sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the command to be executed. Input Address inputs: A[0:20] define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. In the x36 configuration, A[20:19] are reserved for address expansion; in the x18 configuration, A[20] is reserved for address epansion. These expansion addresses can be treated as address inputs, but they do not affect the operation of the device. – Reserved for future use. This signal is internally connected and can be treated as an address input. – Reserved for future use. This signal is not connected and may be connected to ground. Input Bank address inputs: Select to which internal bank a command is being applied. Input/Output Data input/output: The DQ signals form the 36-bit data bus. During READ commands, the data is referenced to both edges of QK. During WRITE commands, the data is sampled at both edges of DKx. Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. During READs, they are free running and edge-aligned with data output from the RLDRAM. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0–DQ17. QK1 and QK1# are aligned with DQ18–DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0–DQ8. QK1 and QK1# are aligned with DQ9–DQ17. Consult the RLDRAM II design guide for more details. Input Input data clock: DKx and DKx# are the differential input data clocks. All input data is referenced to both edges of DKx. DKx# is ideally 180 degrees out of phase with DKx. For the x36 device, DQ0–DQ17 are referenced to DK0 and DK0#, and DQ18–DQ35 are referenced to DK1 and DK1#. For the x9 and x18 devices, all DQs are referenced to DK and DK#. Input Input data mask: The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH, along with the WRITE input data. DM is sampled on both edges of DK (DK1 for the x36 configuration). Output Data valid: The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#. Input IEEE 1149.1 test inputs: These balls may be left no connects if the JTAG function is not used in the circuit Input IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used in the circuit. Output IEEE 1149.1 test output: JTAG Output Input/Output External impedance [25–60Ω]: This signal is used to tune the device outputs to the system data bus impedance. DQ output impedance is set to 0.2 × RQ, where RQ is a resistor from this signal to ground. Connecting ZQ to GND invokes the minimum impedance mode. Connecting ZQ to VDD invokes the maximum impedance mode. Refer to Figure 8 on page 18 to activate this function. Input Input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. Supply Power supply: 2.5V nominal. See Table 22 on page 44 for range. Supply Power supply: 1.8V nominal. See Table 22 on page 44 for range.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Commands
Table 5:
Symbol VDDQ VSS VSSQ VTT NF DNU
Ball Descriptions (continued)
Type Supply Supply Supply Supply – – Description DQ power supply: Nominally, 1.5V or 1.8V. Isolated on the device for improved noise immunity. See Table 22 on page 44 for range. Ground. DQ ground: Isolated on the device for improved noise immunity. Power supply: Isolated termination supply. Nominally, VDDQ/2. See Table 22 on page 44 for range. No function: These balls may be connected to ground. Do not use: These balls may be connected to ground.
Commands
According to the functional signal description, the following command sequences are possible. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK.
Table 6:
Address Widths at Different Burst Lengths
Configuration Burst Length BL = 2 BL = 4 BL = 8 x36 18:0 17:0 NA x18 19:0 18:0 17:0 x9 20:0 19:0 18:0
Table 7:
Operation
Command Table
Note 1 Code DESEL/NOP MRS READ WRITE AREF CS# H L L L L WE# X L H L H REF# X L H H L A[20:0] X OPCODE A A X B[2:0] X X BA BA BA Notes 2 3 3
Device DESELECT/No Operation MRS: Mode Register Set READ WRITE AUTO REFRESH
Notes: 1. X = “Don’t Care” H = logic HIGH L = logic LOW A = valid address BA = valid bank address. 2. Only A(17:0) are used for the MRS command. 3. See Table 6.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Commands
Table 8:
Command DESEL/NOP
1
Description of Commands
Description The NOP command is used to perform a no operation to the RLDRAM, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. The mode register is set via the address inputs A(17:0). See Figure 8 on page 18 for further information. The MRS command can only be issued when all banks are idle and no bursts are in progress. The READ command is used to initiate a burst read access to a bank. The value on the BA(2:0) inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within the bank. The WRITE command is used to initiate a burst write access to a bank. The value on the BA(2:0) inputs selects the bank, and the address provided on inputs A(20:0) selects the data location within the bank. Input data appearing on the DQs is written to the memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored (i.e., this part of the data word will not be written). The AREF is used during normal operation of the RLDRAM to refresh the memory content of a bank. The command is nonpersistent, so it must be issued each time a refresh is required. The value on the BA(2:0) inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a “Don’t Care” during the AREF command. The RLDRAM requires 64K cycles at an average periodic interval of 0.49µs2 (MAX). To improve efficiency, eight AREF commands (one for each bank) can be posted to the RLDRAM at periodic intervals of 3.9µs3. Notes: 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted. 2. Actual refresh is 32ms/8K/8 = 0.488µs. 3. Actual refresh is 32ms/8K = 3.90µs.
MRS
READ
WRITE
AREF
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Commands
Table 9: AC Electrical Characteristics
Note 1 -25 Description Clock Clock cycle time System frequency Clock phase jitter Clock HIGH time Clock LOW time Clock to input data clock Mode register set cycle time to any command Setup Times Address/command and input setup time Data-in and data mask to DK setup time Hold Times Address/command and input hold time Data-in and data mask to DK hold time Data and Data Strobe Output data clock HIGH time Output data clock LOW time QK edge to clock edge skew QK edge to output data edge QK edge to any output data edge QK edge to QVLD Symbol
tCK, tDK
-33 Max 5.7 400 0.15 0.55 0.55 0.5 Min 3.3 175 0.45 0.45 -0.3 6 Max 5.7 300 0.20 0.55 0.55 1.0 Min 5.0 175 0.45 0.45 -0.3 6
-5 Max 5.7 200 0.25 0.55 0.55 1.5 Units ns MHz ns tCK t CK ns t CK Notes
Min 2.5 175 0.45 0.45 -0.3 6
CK, DK t CKVAR tCKH, tDKH t CKL, tDKL tCKDK t MRSC
f
f
2
tAS/tCS tDS
0.4 0.25
0.5 0.3
0.8 0.4
ns ns
tAH/tCH tDH
0.4 0.25
0.5 0.3
0.8 0.4
ns ns
tQKH tQKL tCKQK tQKQ0, tQKQ1 tQKQ tQKVLD
0.9 0.9 -0.25 -0.2 -0.3 -0.3
1.1 1.1 0.25 0.2 0.3 0.3
0.9 0.9 -0.3 -0.25 -0.35 -0.35
1.1 1.1 0.3 0.25 0.35 0.35
0.9 0.9 -0.5 -0.3 -0.4 -0.4
1.1 1.1 0.5 0.3 0.4 0.4
tCKH tCKL
ns ns ns ns
3 4
Notes: 1. All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address, and data signals. 2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 3. tQKQ0 is referenced to Q0–Q17 in x36 and Q0–Q8 in x18. tQKQ1 is referenced to Q18–Q35 in x36 and Q9–Q17 in x18. 4. tQKQ takes into account the skew between any QKx and any Q.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Initialization
Figure 3: Clock/Input Data Clock Command/Address Timings
tCK tCKH tCKL
CK# CK CMD, ADDR VALID VALID VALID
tCKDK
tCKDK
tAS
tAH
DKx# DKx
tDK tDKH tDKL
DON’T CARE
Initialization
The RLDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF and VTT. Although there is no timing relation between VEXT and VDD, the chip starts the power-up sequence only after both voltages are at their nominal levels. The pad supply must not be applied before the core supplies. CK/CK# must meet VID(DC) prior to being applied. Maintain all remaining balls in NOP conditions. 2. Maintain stable conditions for 200µs (MIN). 3. Issue three MRS commands: two dummies plus one valid MRS. It is recommended that the dummy MRS commands are the same value as the desired MRS. 4. tMRSC after the valid MRS, issue eight AUTO REFRESH commands, one on each bank and separated by 2,048 cycles. Initial bank refresh order does not matter. 5. After tRC, the chip is ready for normal operation.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Programmable Impedance Output Buffer
Figure 4:
VEXT VDD VDDQ VREF VTT CK# CK CMD NOP NOP MRS MRS MRS NOP RF0 RF1 RF7 AC
Power-Up Sequence
ADD
200µs MIN
tMRSC
2,048 cycles MIN
6 × 2,048 cycles MIN
tRC
DON’T CARE
Notes: 1. MRS: MRS command RFx: REFRESH Bank x AC: Any command.
Programmable Impedance Output Buffer
The RLDRAM II is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 300Ω resistor is required for an output impedance of 60Ω. To ensure that output impedance is one fifth the value of RQ (within 15 percent), the range of RQ is 125Ω to 300Ω. Output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. The device samples the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and current specifications are met during an update.
Clock Considerations
The RLDRAM II utilizes internal delay-locked loops for maximum output, data valid windows. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 cycles. Table 10: Clock Input Operating Conditions
Notes 1–8 Parameter/Condition Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# Symbol VIN(DC) VID(DC) VID(AC) VIX(AC) Min -0.3 0.2 0.4 VDDQ/2 - 0.15 Max VDDQ + 0.3 VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 + 0.15 Units V V V V Notes 9 9 10
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Clock Considerations
Figure 5: Clock Input
Maximum Clock Level
VIN(DC) MAX
CK#
VDDQ/2 + 0.15 VDDQ/2 VDDQ/2 - 0.15
X X
VIX(AC) MAX VID(DC)12
11
VID(AC)
13
VIX(AC) MIN
CK
VIN(DC) MIN
Minimum Clock Level
Notes: 1. DKx and DKx# have the same requirements as CK and CK#. 2. All voltages referenced to VSS. 3. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operations are tested for the full voltage range specified. 4. Outputs (except for IDD measurements) measured with equivalent load. 5. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2 V/ns in the range between VIL(AC) and VIH(AC). 6. The AC and DC input level specifications are as defined in the HSTL Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 7. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signals other than CK/CK# is VREF. 8. CK and CK# input slew rate must be ≥ 2 V/ns (≥4 V/ns if measured differentially). 9. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 10. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 11. CK and CK# must cross within this region. 12. CK and CK# must meet at least VID(DC) MIN when static and centered around VDDQ/2. 13. Minimum peak-to-peak swing.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Mode Register Set Command (MRS)
Mode Register Set Command (MRS)
The mode register stores the data for controlling the operating modes of the memory. It programs the RLDRAM configuration, burst length, test mode, and I/O options. During a MRS command, the address inputs A(17:0) are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the RLDRAM. The mode register may be set at any time during device operation. However, any pending operations are not guaranteed to successfully complete. See the RLDRAM II design guide for more details. Figure 6: Mode Register Set Timing
CK# CK CMD MRS NOP NOP AC
tMRSC
DON’T CARE
Note:
MRS: MRS command; AC: any command.
Figure 7:
Mode Register Set
CK# CK CS#
WE#
REF#
A(17:0)
COD
A(20:18)
BA(2:0)
Note:
COD: code to be loaded into the register.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Configuration Table
Figure 8: Mode Register Bit Map
A(17:10) A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Reserved1
Impedance On-Die Termination Matching
DLL Reset
Unused
Address Mux
Burst Length
Configuration
On-Die Termination A9 0 1 Termination Disabled (default) Enabled Impedance Matching A8 0 1
DLL Reset A7 0 1 DLL Reset DLL reset (default) DLL enabled
Burst Length A4 0 0 1 1 Address Mux A5 0 1 Address Mux Nonmultiplexed (default) Address multiplexed A3 0 1 0 1 BL 2 (default) 4 82 Not valid
Configuration A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 RLDRAM Configuration 12 (default) 12 2 3 Reserved Reserved Reserved Reserved
Resistor Internal 50Ω3 (default) External
Notes: 1. Bits A(17:10) must be set to zero. 2. BL = 8 is not available for configuration 1. 3. ±15% temperature variation.
Configuration Table
Table 11 shows, for different operating frequencies, the different RLDRAM configurations that can be programmed into the mode register. The READ and WRITE latency (tRL and tWL) values along with the row cycle times (tRC) are shown in clock cycles as well as in nanoseconds. The shaded areas correspond to configurations that are not allowed. Table 11: RLDRAM Configuration Table
Configuration Frequency Symbol
tRC tRL t
11 4 4 5
2 6 6 7
3 8 8 9 20.0 20.0 22.5 26.7 26.7 30.0 40.0 40.0 45.0
Units cycles cycles cycles ns ns ns ns ns ns ns ns ns
WL
400 MHz
tRC tRL t
WL 20.0 20.0 23.3 30.0 30.0 35.0
300 MHz
tRC tRL t
WL 20.0 20.0 25.0
200 MHz
tRC tRL tWL
Notes: 1. BL = 8 is not available for configuration 1.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Write Basic Information
Write Basic Information
Write accesses are initiated with a WRITE command, as shown in Figure 9. Row and bank addresses are provided together with the WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). A WRITE latency (WL) one cycle longer than the programmed READ latency (RL + 1) is present, with the first valid data registered at the first rising DK edge WL cycles after the WRITE command. Any WRITE burst may be followed by a subsequent READ command. Figures 13 and 14 illustrate the timing requirements for a WRITE followed by a READ for bursts of two and four, respectively. Setup and hold times for incoming DQ relative to the DK edges are specified as tDS and tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and hold times for data mask are also tDS and tDH. Figure 9: WRITE Command
CK# CK CS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
DON’T CARE
Note:
A: Address; BA: Bank address.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Write Basic Information
Figure 10: Basic WRITE Burst/DM Timing
CK# CK
tCKDK
DKx# DKx Write Latency
tDS tDH tDS tDH
DQ
D0
D1
D2
D3
DM Data masked
tDS tDH
Data masked
DON’T CARE
Figure 11:
WRITE Burst Basic Sequence: BL = 2, RL = 4, WL = 5, Configuration 1
0 1 2 3 4 5 6 7 8
CK# CK CMD WR WR WR WR WR WR WR WR WR
ADDR
A BA0
A BA1
A BA2 RC = 4 WL = 5
A BA3
A BA0
A BA4
A BA5
A BA6
A BA7
DK# DK D D0a D0b D1a D1b D2a D2b D3a D3
DON’T CARE
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Write Basic Information
Figure 12: WRITE Burst Basic Sequence: BL = 4, RL = 4, WL = 5, Configuration 1
0 CK# CK CMD WR NOP WR NOP WR NOP WR NOP WR 1 2 3 4 5 6 7 8
ADDR
A BA0
A BA1
A BA0
A BA3
A BA0
RC = 4 WL = 5 DK# DK D D0a D0b D0c D0d D1a D1b D1c D1
DON’T CARE
Notes: 1. A/BAx: Address A of bank x WR: WRITE command Dxy: Data y to bank x RC: Row cycle time WL: WRITE latency. 2. Any free bank may be used in any given CMD. The sequence shown is only one example of a bank sequence.
Figure 13:
WRITE Followed By READ: BL = 2, RL = 4, WL = 5, Configuration 1
0 CK# CK CMD WR NOP RD RD NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0
A BA1
A BA2 RL = 4
WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b
QVLD QKx QKx#
DON’T CARE
UNDEFINED
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Read Basic Information
Figure 14: WRITE Followed By READ: BL = 4, RL = 4, WL = 5, Configuration 1
0 CK# CK CMD WR NOP NOP RD NOP RD NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0
A BA1
A BA2 RL = 4
WL = 5 DKx# DKx
DQ
D0a
D0b
D0c
D0d
Q1a Q1b Q1c
Q1d Q2a
QVLD
QKx QKx# DON’T CARE UNDEFINED
Note:
A/BAx: Address A of bank x WR: WRITE Dxy: Data y to bank x WL: WRITE latency RD: READ Qxy: Data y from bank x RL: READ latency.
Read Basic Information
Read accesses are initiated with a READ command, as shown in Figure 15. Row and bank addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next half clock cycle. The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data edge considered over all the data generated at the DQ signals. tQKQ1 is the skew between QK1 and the last valid data edge considered over all the data generated at the DQ signals. tQKQx is derived at each QKx clock edge and is not cumulative over time. tQKQ is the maximum of tQKQ0 and tQKQ1. After completion of a burst, assuming no other commands have been initiated, output data (DQ) will go High-Z. Back-to-back READ commands are possible, producing a continuous flow of output data. The data valid window is derived from each QK transisition and is defined as: MIN (tQKH, tQKL) - 2(tQKQ [MAX]).
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Read Basic Information
Any READ burst may be followed by a subsequent WRITE command. Figures 19 and 20 illustrate the timing requirements for a READ followed by a WRITE. Depending on the programmed READ latency, a READ-to-WRITE delay occurs in order to prevent bus contention. Some systems having long line lengths or severe skews may need additional idle cycles inserted. Refer to the RLDRAM II design guide for more details. Figure 15: READ Command
CK# CK CS#
WE#
REF#
A(20:0)
A
BA(2:0)
BA
DON’T CARE
Note:
A: Address; BA: Bank address.
Figure 16:
Basic READ Burst Timing
tCKH tCKL tCK
CK# CK
tCKQK tQKL tQKH
QKx QKx#
tQKVLD tQKVLD
QVLD
DQ
tQKQ
Q0
Q1
Q2
Q3
tQKQ
tQKQ Note 1
UNDEFINED
Notes: 1. Minimum data valid window can be expressed as MIN (tQKH, tQKL) - 2 x tQKQx (MAX). 2. tQKQ0 is referenced to DQ0–DQ17 in x36 and DQ0–DQ8 in x18. t QKQ1 is referenced to DQ18–DQ35 in x36 and DQ9–DQ17 in x18. 3. tQKQ takes into account the skew between any QKx and any DQ.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Read Basic Information
Figure 17: READ Burst: BL = 2, RL = 4, Configuration 1
0 CK# CK CMD RD RD RD RD RD RD RD RD RD 1 2 3 4 5 6 7 8
ADDR
A BA0
A BA1
A BA2 RC = RL = 4
A BA3
A BA0
A BA7
A BA6
A BA5
A BA4
QKx QKx#
QVLD DQ Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a
DON’T CARE
UNDEFINED
Figure 18:
READ Burst: BL = 4, RL = 4, Configuration 1
0 1 2 3 4 5 6 7 8
CK# CK CMD RD NOP RD NOP RD NOP RD NOP RD
ADDR
A BA0
A BA1 RC = RL = 4
A BA0
A BA1
A BA3
QKx QKx#
QVLD DQ Q0a Q0b Q0c Q0d Q1a Q1b Q1c Q1d Q0a
DON’T CARE
UNDEFINED
Note:
A/BAx: Address A of bank x RD: READ Dxy: Data y to bank x RC: Row cycle time RL: READ latency.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Read Basic Information
Figure 19: READ followed by WRITE, BL = 2, RL = 4, WL = 5, Configuration 1
0 CK# CK CMD RD WR WR NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0
A BA1
A BA2 RL = 4 WL = 5
DKx# DKx DQ Q0a Q0b D1a D1b D2a D2b
QVLD
QKx QKx#
DON’T CARE UNDEFINED
Figure 20:
READ followed by WRITE, BL = 4, RL = 4, WL = 5, Configuration 1
0 CK# CK CMD RD NOP WR NOP NOP NOP NOP NOP 1 2 3 4 5 6 7
ADDR
A BA0
A BA1 WL = 5 RL = 4
DKx# DKx
Q0a Q0b Q0c Q0d
DQ QVLD
D1a
D1b
QKx QKx#
DON’T CARE UNDEFINED
Note:
A/BAx: Address A of bank x WR: WRITE command Dxy: data y to bank x WL: Write latency RD: READ command Qxy: Data y from bank x RL: READ latency.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II AUTO REFRESH Command (AREF)
AUTO REFRESH Command (AREF)
AREF is used to perform a REFRESH cycle on one row in a specific bank. The row addresses are generated by an internal refresh counter for each bank; external address balls are “Don’t Care.” The delay between the AREF command and a subsequent command to the same bank must be at least tRC. Within a period of 32ms (tREF), the entire memory must be refreshed. Figure 22 illustrates an example of a continuous refresh sequence. Other refresh strategies, such as burst refresh, are also possible. Figure 21: AUTO REFRESH Command
CK# CK CS#
WE#
REF#
A(20:0)
BA(2:0)
BA
DON’T CARE
Note:
BA: Bank address.
Figure 22:
AUTO REFRESH Cycle
CK# CK CMD ARFx ACy ACx ACy ARFx ACy
tRC
DON’T CARE
Notes: 1. ACx: Any command on bank x ARFx: Auto refresh bank x ACy: Any command on different bank. 2. tRC is configuration-dependent. Refer to Table 11 on page 18.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II On-Die Termination
On-Die Termination
On-die termination (ODT) is enabled by setting A9 to “1” during a MRS command. With ODT on, all the DQs and DM are terminated to VTT with a resistance RTT. The command, address, and clock signals are not terminated. Figure 23 below shows the equivalent circuit of a DQ receiver with ODT. ODTs are dynamically switched off during READ commands and are designed to be off prior to the RLDRAM driving the bus. Similarly, ODTs are designed to switch on after the RLDRAM has issued the last piece of data. Table 12: On-Die Termination DC Parameters
Description Termination Voltage On-Die Termination Symbol VTT RTT Min 0.95 X VREF 135 Max 1.05 X VREF 165 Units V Ω Notes 1, 2 3
Notes: 1. All voltages referenced to VSS (GND). 2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. The RTT value is measured at 70°C TC.
Figure 23:
On-Die Termination-Equivalent Circuit
VTT
sw
RTT DQ Receiver
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II On-Die Termination
Figure 24: READ Burst with ODT: BL = 2, Configuration 1
0 CK# CK CMD RD RD RD NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8
ADDR
A BA0
A BA1
A BA2 RL = 4
QKx QKx#
QVLD
DQ
Q0a Q0b Q1a Q1b Q2a Q2b
ODT
ODT ON
ODT OFF
ODT ON
DON’T CARE
UNDEFINED
Note:
A/BAx: address A of bank x RD: READ Qxy: Data y to bank x RL: READ latency.
Figure 25:
READ NOP READ with ODT: BL = 2, Configuration 1
0 1 2 3 4 5 6 7 8
CK# CK CMD RD NOP RD NOP NOP NOP NOP NOP NOP
ADDR
A BA0
A BA2 RL = 4
QKx QKx#
QVLD
DQ
Q0a Q0b
Q2a Q2b
ODT
ODT ON
ODT OFF
ODT ON
ODT OFF
ODT ON
DON’T CARE
UNDEFINED
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II On-Die Termination
Figure 26: READ NOP NOP READ with ODT: BL = 2, Configuration 1
0 CK# CK CMD RD NOP NOP RD NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0 RL = 4
A BA2
QKx QKx#
QVLD
DQ
Q0a Q0b
Q2a Q2b
ODT
ODT ON
ODT OFF
ODT ON
ODT OFF
DON’T CARE
ODT ON
UNDEFINED
Note:
A/BAx: address A of bank x RD: READ Qxy:Data y to bank x RL: READ latency.
Figure 27:
READ followed by WRITE with ODT: BL = 2, Configuration 1
0 CK# CK CMD RD WR WR NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0
A BA1
A BA2 RL = 4 WL = 5
DKx# DKx DQ QKx QKx# Q0a Q0b D1a D1b D2a D2b
ODT
ODT ON
ODT OFF
ODT ON
DON’T CARE
UNDEFINED
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Operation with Multiplexed Addresses
Figure 28: WRITE followed by READ with ODT: BL = 2, Configuration 1
0 CK# CK CMD WR NOP RD RD NOP NOP NOP NOP NOP NOP 1 2 3 4 5 6 7 8 9
ADDR
A BA0
A BA1
A BA2 RL = 4
WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b
QKx QKx#
ODT
ODT ON
ODT OFF
ODT ON
DON’T CARE
UNDEFINED
Note:
A/BAx: Address A of bank x WR: WRITE command Dxy: data y to bank x WL: WRITE latency RD: READ command Qxy: Data y from bank x RL: READ latency.
Operation with Multiplexed Addresses
In multiplexed address mode, the address can be provided to the RLDRAM in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage that a maximim of 11 address balls are required to control the RLDRAM, reducing the number of balls on the controller side. The data bus efficiency in continuous burst mode is not affected for BL = 4 and BL = 8 since at least two clocks are required to read the data out of the memory. The bank addresses are delivered to the RLDRAM at the same time as the write command and the first address part, Ax. This option is available by setting bit A5 to “1” in the mode register. Once this bit is set, the READ, WRITE, and MRS commands follow the format described in Figure 29. See Figure 31 on page 32 for the power-up sequence.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Operation with Multiplexed Addresses
Figure 29: Command Description in Multiplexed Address Mode
READ
CK# CK CS#
WRITE
MRS
WE#
REF#
A
Ax
Ay
Ax
Ay
Ax
Ay
BA
BA
BA
BA
DON’T CARE
Notes: 1. Ax, Ay: Address BA: Bank Address. 2. The minimum setup and hold times of the two address parts are defined tAS and tAH.
Figure 30:
Mode Register Set Command in Multiplexed Address Mode
Ax Ay A9 A8 A9 A8 A5 A4 A3 A4 A3 A0
Impedance On-Die Termination Matching On-Die Termination A9x Termination 0 1 Disabled (default) Enabled Impedance Matching A8x 0 1 Resistor Internal 50Ω4 (default) External
DLL Reset
Unused
Address Mux
Burst Length
Configuration
DLL Reset A9y 0 1 DLL Reset DLL reset (default) DLL enabled
Burst Length A4x A3x 0 0 1 1 0 1 0 1 BL 2 (default) 4 83 Not valid
Configuration A4y A3y A0x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 RLDRAM Configuration 13 (default) 13 2 3 Reserved Reserved Reserved Reserved
A5x 0 1
Address Mux Nonmultiplexed (default) Address multiplexed
Notes: 1. The addresses A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in the multiplexed address mode 2. Bits A(17:10) must be set to zero. 3. BL = 8 is not available for configuration 1. 4. ±15% temperature variation.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Operation with Multiplexed Addresses
Figure 31:
VEXT VDD VDDQ VREF VTT CK# CK CMD NOP NOP MRS MRS MRS NOP MRS NOP RF0 RF1 RF7 AC
Power-Up Sequence in Multiplexed Address Mode
ADD
A3
Ax4
Ay
200µs MIN
1 cycle MIN
1 cycle MIN
tMRSC
tMRSC
2,048 cycles 6 × 2,048 MIN cycles MIN
tRC
DON’T CARE
Notes: 1. The above sequence must be respected in order to power up the RLDRAM in the multiplexed address mode. 2. MRS: MRS command RFx: REFRESH Bank x AC: any command. 3. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is in normal mode of operation). 4. Address A5 must be set HIGH (muxed address mode setting when RLDRAM is already in muxed address mode).
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Address Mapping
Address Mapping
The address mapping is described in Table 13 as a function of data width and burst length. Table 13: Address Mapping in Multiplexed Address Mode
Note 1 Data Width x36 Burst Length BL = 2 BL = 4 x18 BL = 2 BL = 4 BL = 8 x9 BL = 2 BL = 4 BL = 8 Address Ball Ax Ay Ax Ay Ax Ay Ax Ay Ax Ay Ax Ay Ax Ay Ax Ay A02 A0 X A0 X A0 X A0 X A0 X A0 A20 A0 X A0 X A3 A3 A1 A3 A1 A3 A1 A3 A1 A3 A1 A3 A1 A3 A1 A3 A1 A4 A4 A2 A4 A2 A4 A2 A4 A2 A4 A2 A4 A2 A4 A2 A4 A2 A53 A5 X A5 X A5 X A5 X A5 X A5 X A5 X A5 X A8 A8 A6 A8 A6 A8 A6 A8 A6 A8 A6 A8 A6 A8 A6 A8 A6 A9 A9 A7 A9 A7 A9 A7 A9 A7 A9 A7 A9 A7 A9 A7 A9 A7 A10 A10 X A10 X A10 A19 A10 X A10 X A10 A19 A10 A19 A10 X A13 A13 A11 A13 A11 A13 A11 A13 A11 A13 A11 A13 A11 A13 A11 A13 A11 A14 A14 A12 A14 A12 A14 A12 A14 A12 A14 A12 A14 A12 A14 A12 A14 A12 A17 A17 A16 A17 A16 A17 A16 A17 A16 A17 A16 A17 A16 A17 A16 A17 A16 A18 A18 A15 X A15 A18 A15 A18 A15 X A15 A18 A15 A18 A15 A18 A15
Notes: 1. X means “Don’t Care.” 2. Reserved for A20 expansion in multiplexed mode. 3. Reserved for A21 expansion in multiplexed mode.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Configuration Table
Configuration Table
In multiplexed address mode, the read and write latencies are increased by one clock cycle. The RLDRAM cycle time remains the same, as described in Table 14. Table 14: Configuration Table In Multiplexed Address Mode
Configuration Frequency Symbol RC t RL t WL t RC tRL tWL tRC tRL tWL tRC tRL tWL
t
1
1
2 6 7 8
3 8 9 10 20.0 22.5 25.0 26.7 30.0 33.3 40.0 45.0 50.0
Unit cycles cycles cycles ns ns ns ns ns ns ns ns ns
4 5 6
400 MHz
300 MHz
200 MHz
20.0 25.0 35.0
20.0 23.3 26.7 30.0 35.0 40.0
Notes: 1. BL = 8 is not available for configuration 1.
REFRESH Command in Multiplexed Address Mode
Similar to other commands, the REFRESH command is executed on the next rising clock edge when in the multiplexed address mode. However, since only bank address is required for AREF, the next command can be applied on the following clock. The operation of the AREF command and any other command is represented in Figure 32. Figure 32: Burst REFRESH Operation
0 CK# CK CMD AC AREF AREF AREF AREF AREF AREF AREF AREF AC 1 2 3 4 5 6 7 8 9 10 11
ADDR
Ax
Ay
Ax
Ay
BADDR
BAk
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BAk
DON’T CARE
Note:
AREF: AUTO REFRESH AC: Any command Ax: First part Ax of address Ay: Second part Ay of address BAk: Bank k; k is chosen so that tRC is met.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II REFRESH Command in Multiplexed Address Mode
Figure 33: WRITE Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, WL = 6
0 CK# CK CMD WR NOP WR NOP WR NOP WR NOP WR 1 2 3 4 5 6 7 8
ADDR
Ax BA0
Ay
Ax BA1
Ay
Ax BA2
Ay
Ax BA3
Ay
Ax BA0
WL = 6 DKx# DKx
DQ
D0a
D0b
D0c
D0d
D1a
D1
DON’T CARE
Figure 34:
READ Burst Basic Sequence: BL = 4, with Multiplexed Addresses, Configuration 1, RL = 5
0 CK# CK CMD RD NOP RD NOP RD NOP RD NOP RD 1 2 3 4 5 6 7 8
ADDR
Ax BA0
Ay
Ax BA1
Ay
Ax BA2
Ay
Ax BA0
Ay
Ax BA1
RL = 5 QKx QKx#
QVLD
DQ
Q0a Q0b Q0c Q0d Q1a Q1b Q1c
DON’T CARE
UNDEFINED
Note:
Ax/BAk: Address Ax of bank k Ay: Address Ay of bank k WR: WRITE Djk: Data k to bank j WL: WRITE latency Qjk: Data k to bank j RD: READ RL: READ latency.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II IEEE 1149.1 Serial Boundary Scan (JTAG)
IEEE 1149.1 Serial Boundary Scan (JTAG)
RLDRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-2001. The TAP operates using logic levels associated with the VDDQ supply. RLDRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
Disabling the JTAG Feature
It is possible to operate RLDRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 35 on page 37. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register (see Figure 36 on page 37).
Test Data-Out (TDO)
The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Figure 35). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register (see Figure 36).
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Test Access Port (TAP)
Figure 35: TAP Controller State Diagram
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
Figure 36:
TAP Controller Block Diagram
0 Bypass Register
76543210
TDI
Selection Circuitry
Instruction Register
31 30 29 . . .210
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK TMS
TAP Controller
x = 112 for all configurations.
Note:
Performing a TAP RESET
A reset is performed by forcing TMS HIGH (VDDQ) for five rising edges of TCK. This RESET does not affect the operation of the RLDRAM and may be performed while the RLDRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the RLDRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II TAP Instruction Set Instruction Register
Eight-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls, as shown in Figure 36. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the RLDRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the RLDRAM. Several balls are also included in the scan register to reserved balls. The RLDRAM has a 113-bit register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The Boundary Scan Order tables (see Table 21 on page 43) show the order in which the bits are connected. Each bit corresponds to one of the balls on the RLDRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the RLDRAM and can be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other information described in the Identification Register Definitions table on page 42.
TAP Instruction Set
Overview
Many different instructions (28) are possible with the 8-bit instruction register. All used combinations are listed in Table 20, Instruction Codes, on page 42. These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used in this RLDRAM is fully compliant to the 1149.1 convention. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II TAP Instruction Set EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instrucion. Thus, during the Update-IR state of EXTEST, the output driver is turned on and the PRELOAD data is driven onto the output balls.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
High-Z
The High-z instruction causes the boundary scan register to be connected between the TDI and TDO. This places all RLDRAM outputs into a High-Z state.
CLAMP
When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the RLDRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the correct value of a signal, the RLDRAM signal must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The RLDRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
Reserved for Future Use
The remaining 22 instructions are not implemented but are reserved for future use. Do not use these instructions.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II TAP Instruction Set
Figure 37: TAP Timing
1 Test Clock (TCK)
tMVTH
2
3
4
5
6
tTHTL tTHMX
t TLTH
tTHTH
Test Mode Select (TMS)
tDVTH tTHDX
Test Data-In (TDI)
tTLOV tTLOX
Test Data-Out (TDO) DON’T CARE UNDEFINED
Table 15:
Description
TAP AC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted Symbol VIH VIL Min VREF + 0.3 VSSQ - 0.3 Max VDD + 0.3 VREF - 0.3 Units V V Notes 1, 2 1, 2
Input high (Logic 1) voltage Input low (Logic 0) voltage
Table 16:
Description
TAP AC Electrical Characteristics
Note 1; +0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V Symbol
tTHTH fTF t t
Min 20
Max
Units ns MHz ns ns ns ns ns ns ns ns ns ns
Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times TCK LOW to TDO unknown TCK LOW to TDO valid TDI valid to TCK HIGH TCK HIGH to TDI invalid Setup Times TMS setup Capture setup Hold Times TMS hold Capture hold
50 10 10 0 10 5 5 5 5 5 5
THTL TLTH
tTLOX tTLOV t
DVTH t THDX
tMVTH tCS tTHMX tCH
Notes: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
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Table 17:
Description Input high (Logic 1) voltage Input low (Logic 0) voltage Input leakage current Output leakage current Output low voltage Output low voltage Output high voltage Output high voltage
TAP DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted Condition Symbol VIH VIL ILI ILO VOL1 VOL2 VOH1 VOH2 Min VREF + 0.15 VSSQ - 0.3 -5.0 -5.0 Max VDD + 0.3 VREF - 0.15 5.0 5.0 0.2 0.4 VDDQ - 0.2 VDDQ - 0.4 Units V V µA µA V V V V Notes 1, 2 1, 2
0V ≤ VIN ≤ VDD Output disabled, 0V ≤ VIN ≤ VDDQ IOLC = 100µA IOLT = 2mA |IOHC| = 100µA |IOHT| = 2mA
1 1 1 1
Notes: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ -0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD.
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Table 18: Identification Register Definitions
All Devices abcd 00jkidef10100111 Description ab = die revision cd = 10 for x36, 01 for x18, 00 for x9. def = 000 for 288M, 001 for 576M, 010 for 1G. i = 0 for common I/O, 1 for separate I/O. jk = 00 for RLDRAM, 01 for RLDRAM II. Allows unique identification of RLDRAM vendor. Indicates the presence of an ID register.
Instruction Field Revision Number (31:28) Device ID (27:12) Micron JEDEC ID Code (11:1) ID Register Presence Indicator (0)
00000101100 1
Table 19:
Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size 8 1 32 113
Table 20:
Instruction Extest ID Code
Instruction Codes
Code 0000 0000 0010 0001 0000 0101 0000 0111 0000 0011 1111 1111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This operation does not affect RLDRAM operations. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect RLDRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Selects the bypass register to be connected between TDI and TDO. Data driven by output balls are determined from values held in the boundary scan register. Selects the bypass register to be connected between TDI and TDO. All ouputs are forced into high impedance state. Places the bypass register between TDI and TDO. This operation does not affect RLDRAM operations.
Sample/Preload Clamp High-Z Bypass
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II TAP Instruction Set
Table 21:
Bit# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Boundary Scan (Exit) Order
µBGA Ball K1 K2 L2 L1 M1 M3 M2 N1 P1 N3 N3 N2 N2 P3 P3 P2 P2 R2 R3 T2 T2 T3 T3 U2 U2 U3 U3 V2 U10 U10 U11 U11 T10 T10 T11 T11 R10 R10 Bit# 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 µBGA Ball R11 R11 P11 P11 P10 P10 N11 N11 N10 N10 P12 N12 M11 M10 M12 L12 L11 K11 K12 J12 J11 H11 H12 G12 G10 G11 E12 F12 F10 F10 F11 F11 E10 E10 E11 E11 D11 D10 Bit# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 – µBGA Ball C11 C11 C10 C10 B11 B11 B10 B10 B3 B3 B2 B2 C3 C3 C2 C2 D3 D3 D2 D2 E2 E2 E3 E3 F2 F2 F3 F3 E1 F1 G2 G3 G1 H1 H2 J2 J1 –
Notes: 1. Any unused balls that are in the order will read as a logic “0.”
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Electrical Characteristics
Electrical Characteristics
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Figure 38:
Parameter Storage temperature I/O voltage Voltage on VEXT supply relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Junction temperature
Absolute Maximum Ratings
Min -55 -0.3V -0.3 -0.3 -0.3 Max +150 VDDQ + 0.3 +2.8 +2.1 +2.1 110 Units °C V V V V °C Notes
1
Notes: 1. Junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow.
Table 22:
Description
DC Electrical Characteristics and Operating Conditions
+0°C ≤ TC ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted Condition Symbol VEXT VDD VDDQ VREF VTT VIH VIL IOH IOL ILC ILI ILO IREF Min Max Units V V V V V V V mA mA µA µA µA µA Notes 1 1, 4 1, 4, 5 1–3, 8 9, 10 1, 4 1, 4 6, 7, 11 6, 7, 11
Supply voltage Supply voltage Isolated output ouffer supply Reference voltage Termination voltage Input high (Logic 1) voltage Input low (Logic 0) voltage Output high current Output low current Clock input leakage current Input leakage current Output leakage current Reference voltage current
VOH = VDDQ/2 VOL = VDDQ/2 0V ≤ VIN ≤ VDD 0V ≤ VIN ≤ VDD 0V ≤ VIN ≤ VDDQ
2.38 2.63 1.7 1.9 1.4 VDD 0.49 × VDDQ 0.51 × VDDQ 0.95 × VREF 1.05 × VREF VREF + 0.1 VDDQ + 0.3 VSSQ - 0.3 VREF - 0.1 (VDDQ/2) / (VDDQ/2) / (1.15 × RQ/5) (0.85 × RQ/5) (VDDQ/2) / (VDDQ/2) / (1.15 × RQ/5) (0.85 × RQ/5) -5 5 -5 5 -5 5 -5 5
Notes: 1. All voltages referenced to VSS (GND). 2. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 3. Peak-to-peak AC noise on VREF must not exceed ±2% VREF(DC). 4. Overshoot: VIH(AC) ≤ VDD + 0.7V for t ≤ tCK/2. Undershoot: VIL(AC) ≥ -0.5V for t ≤ tCK/2. During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tCK/2 or operate at frequencies exceeding tCK (MAX). 5. VDDQ can be set to a nominal 1.5V + 0.1V or 1.8V + 0.1V supply. 6. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device.
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Electrical Characteristics
7. If MRS bit A8 is 0, use RQ = 250Ω in the equation in lieu of presence of an external impedance matched resistor. 8. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2% of the DC value. Thus, from VDDQ/2, VREF is allowed ±2%VDDQ/2 for DC error and an additional ±2%VDDQ/2 for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. 9. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. 10. On-die termination may be selected using mode register bit 9 (see Figure 8 on page 18). A resistance RTT from each data input signal to the nearest VTT can be enabled. RTT = 150Ω (±10%) at 70°C TC. 11. For VOL and VOH, refer to the RLDRMA II HSpice or IBIS driver models.
Table 23:
AC Electrical Characteristics and Operating Conditions
+0°C ≤ Tc ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, unless otherwise noted Description Conditions Matched impedance mode Matched impedance mode Symbol VIH VIL Min VREF + 0.2 VSSQ - 0.3 Max VDDQ + 0.3 VREF - 0.2 Units V V
Input high (Logic 1) voltage Input low (Logic 0) voltage
Table 24:
Capacitance
Description Conditions TA = 25°C; f = 1 MHz Symbol CI CO CCK Min 1.5 3.5 2.0 Max 2.5 5.0 3.0 Units pF pF pF
Address/Control input capacitance I/O capacitance (DQ, DM, QK) Clock capacitance
Figure 39:
Output Test Conditions
VTT 50Ω
DQ
Test point 10pF
Figure 40:
Input Waveform
VDDQ VIH(AC) MIN VSWING VIL(AC) MAX GND Rise Time: 2 V/ns Fall Time: 2 V/ns
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288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Electrical Characteristics
Table 25: IDD Operating Conditions and Maximum Limits
Notes 1–6 on page 47 Max Description Standby current Condition CK = Idle All banks idle, no inputs toggling CS# = 1 No commands, half bank/address/data change once every four clock cycles BL = 2, sequential bank access, bank transitions once every tRC, half address transitions once every tRC, read followed by write sequence, continous data during WRITE commands. BL = 4, sequential bank access, bank transitions once every tRC, half address transitions once every tRC, read followed by write sequence, continous data during WRITE commands. BL = 8, sequential bank access, bank transitions once every tRC, half address transitions once every tRC, read followed by write sequence, continous data during WRITE commands. Eight bank cyclic refresh, continous address/ data, command bus remains in refresh for all eight banks. Single bank refresh, sequential bank access, half address transitions once every tRC, continous data. BL = 2, cyclic bank access, half of address bits change every clock cycle, continuous data, measurement is taken during continuous WRITE. BL = 4, cyclic bank access, half of address bits change every two clocks, continuous data, measurement is taken during continuous WRITE. BL = 8, cyclic bank access, half of address bits change every four clock cycles, continuous data, measurement is taken during continuous WRITE. BL = 2, cyclic bank access, half of address bits change every clock cycle, measurement is taken during continuous READ. BL = 4, cyclic bank access, half of address bits change every two clocks, measurement is taken during continuous READ. BL = 8, cyclic bank access, half of address bits change every four clock cycles, measurement is taken during continuous READ.
t
Symbol ISB1 (VDD) X36 ISB1 (VDD) X18/X9 ISB1 (VEXT) ISB2 (VDD) X36 ISB2 (VDD) X18/X9 ISB2 (VEXT) IDD1 (VDD) X36 IDD1 (VDD) X18/X9 IDD1 (VEXT) IDD 2 (VDD) X36 IDD2 (VDD) X18/X9 IDD2 (VEXT) IDD 3 (VDD) X36 IDD3 (VDD) X18/X9 IDD3 (VEXT) IREF1 (VDD) X36 IREF1 (VDD) X18/X9 IREF1 (VEXT) IREF2 (VDD) X36 IREF2 (VDD) X18/X9 IREF2 (VEXT) IDD2W (VDD) X36 IDD2W (VDD) X18/ X9 IDD2W (VEXT) IDD4W (VDD) X36 IDD4W (VDD) X18/ X9 IDD4W (VEXT) IDD8W (VDD) X36 IDD8W (VDD) X18/ X9 IDD8W (VEXT) IDD2R (VDD) X36 IDD2R (VDD) X18/X9 IDD2R (VEXT) IDD4R (VDD) X36 IDD4R (VDD) X18/X9 IDD4R (VEXT) IDD8R(VDD) X36 IDD8R (VDD) X18/X9 IDD8R (VEXT)
-25 48 48 26 288 288 26 374 348 41 418 362 48 NA 408 55 685 680 133 326 325 48 990 970 100 882 779 88 NA 668 60 920 902 100 764 724 88 NA 621 60
-33 48 48 26 233 233 26 343 305 36 389 319 42 NA 368 48 545 530 111 281 267 42 914 819 90 790 609 77 NA 525 51 850 761 90 734 566 77 NA 488 51
-5 48 48 26 189 189 26 292 255 36 339 269 42 NA 286 48 375 367 105 227 221 42 676 597 69 567 439 63 NA 364 40 628 555 69 527 408 63 NA 338 40
Units mA
Active standby current Operational current
mA
mA
Operational current
mA
Operational current
mA
Burst refresh current Distributed refresh current Operating burst write current example Operating burst write current example Operating burst write current example Operating burst read current example Operating burst read current example Operating burst read current example
mA
mA
mA
mA
mA
mA
mA
mA
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36_2.fm - Rev. H 8/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Electrical Characteristics
Notes: 1. IDD specifications are tested after the device is prop erly initialized. +0°C ≤ Tc ≤ +95°C; +1.7V ≤ VDD ≤ +1.9V, +2.38V ≤ VEXT ≤ +2.63V, +1.4V ≤ VDDQ ≤ +1.6V, VREF = VDDQ/2. 2. tCK = tDK = MIN, tRC = MIN. 3. Input slew rate is specified in Table 22, DC Electrical Characteristics and Operating Conditions, on page 44. 4. Definitions for IDD conditions: a. LOW is defined as VIN ≤ VIL(AC) MAX. b. HIGH is defined as VIN ≤ VIH(AC) MAX. c. Stable is defined as inputs remaining at a HIGH or LOW level. d. Floating is defined as inputs at VREF = VDDQ/2. e. Continous data is defined as half the DQ signals changing between HIGH and LOW every half clock cycle (twice per clock). f. Continous address is defined as half the address signals changing between HIGH and LOW every clock cycle (once per clock). g. Sequential bank access is defined as the bank address incrementing by one ever tRC. h. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL = 4 this is every other clock. 5. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transistions more tha n once per clock cycle. 6. IDD parameters are specified with ODT disabled.
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36_2.fm - Rev. H 8/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Package Dimensions
Package Dimensions
Figure 41: 144-Ball µBGA
10.70 CTR 10º TYP SEATING PLANE 0.08 A 144X ∅ 0.45 DIMENSIONS APPLY TO SOLDER BALLS POST REFLOW. THE PRE-REFLOW BALL DIAMETER IS 0.50 ON A 0.40 SMD BALL PAD. A 2.40 CTR 0.08 MAX 0.44 ±0.05 0.26 ±0.05 0.39 ±0.05 0.80 TYP BALL A12 BALL A1 BALL A1 ID
8.80
BALL A1 ID
1.00 TYP
17.00 15.40
18.50 ±0.10
17.90 CTR
8.50
9.25 ±0.05
4.40
5.50 ±0.05
11.00 ±0.10
MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb, 2%Ag OR 96.5% Sn, 3%Ag, 0.5% Cu
Notes: 1. All dimensions in millimeters.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. RLDRAM is a trademark of Infineon Technologies AG in various countries, and is used by Micron Technology, Inc. under license from Infineon. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36_2.fm - Rev. H 8/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
288Mb: x36, x18, x9 2.5V VEXT, 1.8V VDD, HSTL, RLDRAM II Package Dimensions
Rev. J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/05 • Updated Table 25, IDD Operating Conditions and Maximum Limits, on page 46. • Added operating temperature ranges. • Updated package drawing to include unleaded information. • Updated template. Rev H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/04 • Production status. Rev G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 09/04 • Added updated note to BS table • QK, QK# description updated (Page 10). • JTAG logic levels update (Pages 10, 35). • Timing parameters (Power-up sequence in Figure 7 updated (Page 14). • Clock Considerations “DLL auto reset” removed (Page 15). • Figure 8 Vid(DC) and Vid(AC) updated (Page 16). • Figure 16 QVLD signal corrected (Page 21).On-die termination text updated to include DM pin (Page 27). • Measured temperature for RTT changed to 70°C Tc (Pages 27, 41). • Figure 27 QVLD signal corrected (Page 27). • Figure 33 text and notes updated to correct Address bits (Page 31). • Power-up sequence in Figure 34 updated (Page 31). • Measured temperatures and range changed to +0°C ≤ Tc ≤ +95°C (Pages 37, 38, 41,42, 43). • TAP DC parameters (VOL1, VOL2, VOH1, VOH2) updated (Page 38). • I/O Capacitance updated (Page 42). •
PDF: 09005aef80a41b46/Source: 09005aef809f284b MT49H8M36_2.fm - Rev. H 8/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002 Micron Technology, Inc. All rights reserved.
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