MT4LC16M4T8TG-6S

16 MEG x 4 FPM DRAM DRAM FEATURES • Single +3.3V ±0.3V power supply • Industry-standard x4 pinout, timing, functions, and packages • 13 row, 11 column addresses (A7) 12 row, 12 column addresses (T8) • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • FAST-PAGE-MODE (FPM) access • 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention MT4LC16M4A7, MT4LC16M4T8 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html PIN ASSIGNMENT (Top View) 32-Pin SOJ VCC DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5 VCC 32-Pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS DQ3 DQ2 NC NC NC CAS# OE# A12/NC** A11 A10 A9 A8 A7 A6 VSS OPTIONS • Refresh Addressing 4,096 (4K) rows 8,192 (8K) rows • Plastic Packages 32-pin SOJ (400 mil) 32-pin TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rates Standard Refresh Self Refresh (128ms period) MARKING T8 A7 DJ TG -5 -6 None S* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC VSS DQ0 DQ3 DQ1 DQ2 NC NC NC NC NC NC NC WE# CAS# RAS# OE# A0 A12/NC** A1 A11 A2 A10 A3 A9 A4 A5 A8 VCC A7 A6 VSS **A12 on A7 version and NC on T8 version 16 MEG x 4 FPM DRAM PART NUMBERS PART NUMBER MT4LC16M4A7DJ-x MT4LC16M4A7DJ-x S MT4LC16M4A7TG-x MT4LC16M4A7TG-x S MT4LC16M4T8DJ-x MT4LC16M4T8DJ-x S MT4LC16M4T8TG-x MT4LC16M4T8TG-x S x = speed REFRESH ADDRESSING PACKAGE REFRESH 8K 8K 8K 8K 4K 4K 4K 4K SOJ SOJ TSOP TSOP SOJ SOJ TSOP TSOP Standard Self Standard Self Standard Self Standard Self NOTE: 1. The 16 Meg x 4 FPM DRAM base number differentiates the offerings in one place— MT4LC16M4A7. The fifth field distinguishes various options: A7 designates an 8K refresh and T8 designates a 4K refresh for FPM DRAMs. 2. The # symbol indicates signal is active LOW. *Contact factory for availability Part Number Example: GENERAL DESCRIPTION The 16 Meg x 4 DRAMs are high-speed CMOS, dynamic random-access memory devices contain-ing 67,108,864 bits organized in a x4 configuration. The MT4LC16M4A7 and MT4LC16M4T8 are functionally organized as 16,777,216 locations containing four bits each. The 16,777,216 memory locations are arranged in 8,192 rows by 2,048 columns for the MT4LC16M4A7 or 4,096 rows by 4,096 columns for the MT4LC16M4T8. During READ or WRITE cycles, each location is uniquely MT4LC16M4A7DJ KEY TIMING PARAMETERS SPEED -5 -6 tRC tRAC tPC tAA tCAC 90ns 110ns 50ns 60ns 30ns 35ns 25ns 30ns 13ns 15ns 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FUNCTIONAL BLOCK DIAGRAM MT4LC16M4A7 (13 row addresses) WE# CAS# DATA-IN BUFFER 4 CONTROL LOGIC NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 4 4 DQ0 DQ1 DQ2 DQ3 OE# COLUMNADDRESS BUFFER(11) REFRESH CONTROLLER ROW SELECT 13 ROWADDRESS BUFFERS (13) COMPLEMENT SELECT ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 11 11 COLUMN DECODER 2,048 SENSE AMPLIFIERS I/O GATING 4 REFRESH COUNTER 13 2,048 13 8,192 8,192 8,192 x 2,048 x 4 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS FUNCTIONAL BLOCK DIAGRAM MT4LC16M4T8 (12 row addresses) WE# CAS# DATA-IN BUFFER 4 CONTROL LOGIC NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 4 4 DQ0 DQ1 DQ2 DQ3 OE# COLUMNADDRESS BUFFER(12) REFRESH CONTROLLER ROW SELECT 12 ROWADDRESS BUFFERS (12) COMPLEMENT SELECT ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 12 12 COLUMN DECODER 4,096 SENSE AMPLIFIERS I/O GATING 4 REFRESH COUNTER 12 4,096 12 4,096 4,096 4,096 x 4,096 x 4 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM GENERAL DESCRIPTION (continued) addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address by CAS#. Both devices provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY-WRITE) within a given row. The MT4LC16M4A7 and MT4LC16M4T8 must be refreshed periodically in order to retain stored data. whereas the MT4LC16M4T8 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR refresh will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method only one row is refreshed at a time; so for the MT4LC16M4A7, 8,192 RAS#-ONLY REFRESH cycles must be executed every 64ms to cover all rows. Some compatibility issues may become apparent. JEDEC strongly recommends the use of CBR REFRESH for this device. An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows for an extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes RAS#-ONLY or burst CBR refresh sequence, all rows must be refreshed within the average internal refresh rate prior to the resumption of normal operation. FAST PAGE MODE ACCESS Each location in the DRAM is uniquely addressable as mentioned in the General Description. The data for each location is accessed via the four I/O pins (DQ0DQ3). The WE# signal must be activated to execute a WRITE operation; otherwise, a READ operation will be performed. The OE# signal must be activated to enable the DQ output drivers for a read access and can be deactivated to disable output data if necessary. FAST-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation. DRAM REFRESH The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (A7) or all 4,096 rows (T8) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC16M4A7 internally refreshes two rows for every CBR cycle, STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Relative to VSS ................ -1V to +4.6V Voltage on NC, Inputs or I/O Pins Relative to VSS ..................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0°C to +70°C Storage Temperature (plastic) ............ -55°C to +150°C Power Dissipation ................................................... 1W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA OUTPUT LOW VOLTAGE: IOUT = 2mA OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II MIN 3 2 -0.3 -2 MAX 3.6 VCC + 0.3 0.8 2 UNITS NOTES V V V µA 26 26 VOH VOL IOZ 2.4 – -5 – 0.4 5 V V µA 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (RAS# = CAS# VCC - 0.2V, DQs may be left open, other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: FAST PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open) SYMBOL ICC1 SPEED ALL 4K 8K REFRESH REFRESH UNITS NOTES 1 1 mA ICC2 ICC3 ALL -5 -6 -5 -6 -5 -6 -5 -6 500 170 160 100 90 170 160 170 160 500 130 120 100 90 130 120 130 120 µA mA 25 ICC4 mA 25 ICC5 mA 22 ICC6 mA 4, 7 ICC7 ALL 400 400 µA 4, 7 ICC8 ALL 400 400 µA 4, 7 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM CAPACITANCE (Note: 2) PARAMETER Input Capacitance: Address pins Input Capacitance: RAS#, CAS#, WE#, OE# Input/Output Capacitance: DQ SYMBOL CI 1 CI 2 CIO MAX 5 7 7 UNITS pF pF pF AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Access time from column address Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z CAS# precharge time (FAST PAGE MODE) Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during READ-MODIFY-WRITE cycle Output buffer turn-off delay OE# setup prior to RAS# during HIDDEN REFRESH cycle FAST-PAGE-MODE READ or WRITE cycle time FAST-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLZ tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOFF tORD tPC tPRWC tRAC tRAD -6 MAX 25 MIN 45 0 0 55 13 15 10 15 15 15 3 10 5 60 5 40 15 10 0 3 15 13 3 0 35 85 50 60 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES MIN 40 0 0 48 8 13 15 15 3 8 5 50 5 36 13 8 0 3 13 3 0 30 76 13 18 10,000 4 13 30 35 4 18 19 19 23, 24 20 24 17, 23 13 13 15 15 15 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM AC ELECTRICAL CHARACTERISTICS (Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V) AC CHARACTERISTICS PARAMETER Row-address hold time RAS# pulse width RAS# pulse width (FAST PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period Refresh period (4,096 cycles) “S” version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time WRITE command pulse width WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWP tWRH tWRP MIN 8 50 50 100 90 18 0 0 MAX 10,000 125,000 MIN 10 60 60 100 110 20 0 0 -6 MAX 10,000 125,000 UNITS ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 23 14 16 22 4 64 128 30 0 90 0 13 131 73 13 2 8 40 0 8 10 10 40 0 105 0 15 155 85 15 2 10 45 0 10 10 10 64 128 16 18 50 50 18 4, 23 4, 23 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM NOTES 1. All voltages referenced to VSS. 2. This parameter is sampled. VCC = +3.3V; f = 1 MHz. 3. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured. 6. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 5ns. 8. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 9. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 10. If CAS# = VIH, data output is High-Z. 11. If CAS# = VIL, data output may contain data from the last valid READ cycle. 12. Measured with a load equivalent to two TTL gates, 100pF and VOL = 0.8V and VOH = 2V. 13. If CAS# is LOW at the falling edge of RAS#, output data will be maintained from the previous cycle. To initiate a new cycle and clear the dataout buffer, CAS# must be pulsed HIGH for tCP. 14. The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 15. The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 16. Either tRCH or tRRH must be satisfied for a READ cycle. 17. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 18. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. If tWCS > tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. tRWD, tAWD, and tCWD define READ-MODIFY-WRITE cycles. Meeting these limits allows for reading and disabling output data and then applying input data. The values shown were calculated for reference allowing 10ns for the external latching of read data and application of write data. OE# held HIGH and WE# taken LOW after CAS# goes LOW result in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 19. These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 20. If OE# is tied permanently LOW, LATE WRITE or READ-MODIFY-WRITE operations are not possible. 21. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# = LOW and OE# = HIGH. 22. RAS#-ONLY REFRESH requires that all 8,192 rows of the MT4LC16M4A7 or all 4,096 rows of the MT4LC16M4T8 be refreshed at least once every 64ms. CBR REFRESH for either device requires that at least 4,096 cycles be completed every 64ms. 23. The DQs open during READ cycles once tOD or tOFF occur. If CAS# goes HIGH before OE#, the DQs will open regardless of the state of OE#. If CAS# stays LOW while OE# is brought HIGH, the DQs will open. If OE# is brought back LOW (CAS# still LOW), the DQs will provide the previously read data. 24. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. If OE# is taken back LOW while CAS# remains LOW, the DQs will remain open. 25. Column address changed once each cycle. 26. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM READ CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRRH tRP RAS# CAS# ADDR ROW tRCS COLUMN tRCH ROW WE# V IH V IL tAA tRAC tCAC tCLZ tOFF V DQ V IOH IOL OPEN VALID DATA OPEN DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCRP tCSH tOD tOE -6 MAX 25 MIN 45 0 0 13 15 10 15 3 5 60 13 13 3 15 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 3 13 8 50 90 18 0 0 30 0 13 MAX 13 50 MIN 3 15 10 60 110 20 0 0 40 0 15 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 3 5 50 3 10,000 10,000 10,000 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM EARLY WRITE CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tRCD tCAS tRP RAS# CAS# ROW COLUMN tCWL tRWL tWCS tWCR tWCH tWP ROW WE# V IH V IL tDS tDH V DQ V IOH IOL VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCRP tCSH tCWL tDH tDS tRAD -6 MAX MIN 45 0 0 10 15 5 60 15 10 0 15 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 8 50 90 18 30 13 13 8 40 0 8 MAX 10,000 MIN 10 60 110 20 40 15 15 10 45 0 10 -6 MAX 10,000 UNITS ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 5 50 13 8 0 13 10,000 10,000 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS V IH V IL tCSH tRSH tCAS tRP RAS# tCRP V IH V IL tAR tRAD tRAH tRCD CAS# tASR ADDR V IH V IL tASC tCAH ROW COLUMN tRWD tCWD tAWD tCWL tRWL tWP ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH V DQ V IOH IOL OPEN VALID D IN tOEH OPEN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCRP tCSH tCWD tCWL tDH tDS -6 MAX 25 MIN 45 0 0 55 13 15 10 10,000 15 3 5 60 40 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP -5 MIN 3 13 50 13 8 50 18 0 30 13 131 73 13 8 15 10 60 20 0 40 15 155 85 15 10 MAX 13 13 MIN 3 15 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 48 8 13 3 5 50 36 13 8 0 10,000 10,000 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP V IH V IL tAR tASR ADDR V IH V IL tRAD tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ROW COLUMN COLUMN tRCS tRCH COLUMN tRCS ROW tRRH tRCS WE# V IH V IL tRCH tRCH tAA tRAC tCAC tCLZ DQ V IOH V IOL OPEN tOE V IH V IL VALID DATA tOD tOFF tCLZ tAA tCPA tCAC tOFF tCLZ VALID DATA tOD tAA tCPA tCAC tOFF tOE tOE VALID DATA tOD OPEN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tOD -6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 3 10 5 13 60 3 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 3 30 13 8 50 18 0 0 30 0 13 125,000 MAX 13 13 50 15 10 60 20 0 0 40 0 15 MIN 3 35 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns 125,000 ns ns ns ns ns ns ns MIN 40 0 0 8 13 3 8 5 50 3 30 35 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE EARLY WRITE CYCLE tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tASC tCAH tASC tCAH tASC tCAH tRCD tCAS tPC tCP tCAS tCP tRSH tCAS tCP tRP RAS# CAS# ROW COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP ROW tWCS tWCS tWCS WE# V IH V IL tDS tWCR tDH tDS tDH tDS tRWL tDH V DQ V IOH IOL V IH V IL VALID DATA VALID DATA VALID DATA OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAR tASC tASR tCAH tCAS tCP tCRP tCSH tCWL tDH tDS tPC -6 MAX MIN 45 0 0 10 15 10 5 60 15 10 0 35 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 13 8 50 18 30 13 13 8 40 0 8 MAX MIN 15 10 60 20 40 15 15 10 45 0 10 -6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 8 5 50 13 8 0 30 125,000 125,000 10,000 10,000 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tRAH tRCD tCAS NOTE 1 tCP tPC tPRWC tCAS tRSH tCP tCAS tCP tRP RAS# CAS# tASR ADDR V IH V IL tASC tCAH tASC tCAH tASC tCAH ROW COLUMN tRWD tRCS tCWL tWP tAWD tCWD COLUMN COLUMN tRWL tCWL tAWD tCWD tWP ROW tCWL tWP tAWD tCWD WE# V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID D OUT VALID DIN VALID D OUT VALID D IN tAA tDH tDS tCPA tCAC tCLZ VALID D OUT VALID D IN tDH tDS DQ V IOH V IOL OPEN OPEN tOD tOE OE# V IH V IL tOE tOD tOE tOD tOEH DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH tDS -6 MAX 25 MIN 45 0 0 55 13 15 10 10,000 15 3 10 5 60 40 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOD tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP -5 MIN 3 13 30 76 50 13 8 50 18 0 30 13 73 13 8 125,000 15 10 60 20 0 40 15 85 15 10 MAX 13 13 15 35 85 MIN 3 -6 MAX 15 15 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 48 8 13 3 8 5 50 36 13 8 0 60 125,000 30 35 NOTE: 1. tPC is for LATE WRITE only. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM FAST-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP V IH V IL t RSH t CSH t CRP CAS# V IH V IL t AR t RAD t ASR ADDR V IH V IL t RAH t ASC t CAH t ASC t CAH t RCD t CAS t CP t PC t CAS t CP t RP RAS# ROW COLUMN COLUMN t CWL ROW t RCS t WCS WE# V IH V IL t CAC t CLZ V OH V OL NOTE 1 t OFF t DS VALID DATA t AA t RAC t RWL t WP t WCH t DH DQ OPEN VALID DATA DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLZ tCP tCRP tCSH tCWL tDH tDS -6 MAX 25 MIN 45 0 0 13 15 10 10,000 15 3 10 5 60 15 10 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWL tWCH tWCS tWP -5 MIN 3 30 50 13 8 50 18 0 30 13 13 8 0 8 125,000 15 10 60 20 0 40 15 15 10 0 10 MAX 13 MIN 3 35 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 40 0 0 8 13 3 8 5 50 13 8 0 125,000 NOTE: 1. Do not drive input data prior to output data going High-Z. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP RAS# CAS# ROW ROW V DQ V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# V IH V IL tRPC tCP CAS# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS DQ DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH -6 MAX MIN 0 15 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC tRP tRPC tWRH tWRP -5 MIN 50 90 30 0 10 10 MAX 10,000 MIN 60 110 40 0 10 10 -6 MAX 10,000 UNITS ns ns ns ns ns ns MIN 0 15 8 5 5 8 NOTE: 1. End of CBR REFRESH cycle. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM HIDDEN REFRESH CYCLE 1 (WE# = HIGH; OE# = LOW) tRAS RAS# V IH V IL tCRP CAS# V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS ADDR ROW COLUMN tAA tRAC tCAC tCLZ tOFF V DQ V IOH IOL OPEN tOE VALID DATA tOD OPEN OE# V IH V IL tORD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD -6 MAX 25 MIN 45 0 0 13 15 10 15 3 5 13 3 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH -5 MIN 3 0 13 8 50 18 30 13 10,000 MAX 13 13 50 15 10 60 20 40 15 3 0 MIN -6 MAX 15 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns MIN 40 0 0 8 15 3 5 3 NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2 RAS# tRPC tCP tRPC tCP (( )) CAS# V IH V IL V DQ V OH OL V WE# V IH IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCP tCSR tRASS tRP MIN 15 8 5 100 30 MAX MIN 15 10 5 100 40 -6 MAX UNITS ns ns ns µs ns SYMBOL tRPC tRPS tWRH tWRP MIN 0 90 10 10 -5 MAX MIN 0 105 10 10 -6 MAX UNITS ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed, if RAS#-only or burst CBR refresh is used. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM 32-PIN PLASTIC SOJ (400 mil) .829 (21.05) .823 (20.90) .750[19.05] (TYP) .050[1.27] (TYP) .405 (10.29) .399 (10.13) .445 (11.31) .435 (11.05) .145 (3.68) .132 (3.35) PIN #1 INDEX .037 [0.95] MAX DAMBAR PROTRUSION .024 [0.61] .032 (0.82) .026 (0.67) .095 (2.42) .080 (2.03) .030 [0.76] MIN SEATING PLANE .020 (0.51) .015 (0.38) .040 (1.02) .030 (0.77) R .380 (9.65) .360 (9.14) NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 16 MEG x 4 FPM DRAM 32-PIN PLASTIC TSOP (400 mil) 20.96 ±0.08 SEE DETAIL A 1.27 TYP 0.95 11.76 ±0.10 10.16 ±0.08 PIN 1 ID 0.43 +0.07 -0.13 0.15 +0.03 -0.02 0.25 0.10 1.20 MAX 0.10 +0.10 -0.05 GAGE PLANE 0.80 TYP 0.50 ±0.10 DETAIL A NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 16 Meg x 4 FPM DRAM D21_2.p65 – Rev. 5/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.