MT4LC1M16E5TG-5

16Mb: 1 MEG x16 EDO DRAM EDO DRAM MT4C1M16E5 – 1 Meg x 16, 5V MT4LC1M16E5 – 1 Meg x 16, 3.3V For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/datasheets/sdramds.html FEATURES • JEDEC- and industry-standard x16 timing, functions, pinouts, and packages • High-performance CMOS silicon-gate process • Single power supply (+3.3V ±0.3V or 5V ±10%) • All inputs, outputs and clocks are TTL-compatible • Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS# (CBR), HIDDEN; optional self refresh (S) • BYTE WRITE access cycles • 1,024-cycle refresh (10 row, 10 column addresses) • Extended Data-Out (EDO) PAGE MODE access • 5V-tolerant inputs and I/Os on 3.3V devices PIN ASSIGNMENT (Top View) 44/50-Pin TSOP VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC 1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC 42-Pin SOJ VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS OPTIONS • Voltages 1 3.3V 5V • Refresh Addressing 1,024 (1K) rows • Packages Plastic SOJ (400 mil) Plastic TSOP (400 mil) • Timing 50ns access 60ns access • Refresh Rates Standard Refresh (16ms period) Self Refresh (128ms period) • Operating Temperature Range Commercial (0oC to +70oC) Extended (-20oC to +80oC) Part Number Example: MARKING LC C E5 DJ TG -5 -6 None S2 None ET NC NC WE# RAS# NC NC A0 A1 A2 A3 VCC 15 16 17 18 19 20 21 22 23 24 25 36 35 34 33 32 31 30 29 28 27 26 NC CASL# CASH# OE# A9 A8 A7 A6 A5 A4 VSS NOTE: The "#" symbol indicates signal is active LOW. 1 MEG x 16 EDO DRAM PART NUMBERS PART NUMBER MT4LC1M16E5DJ-x MT4LC1M16E5DJ-x S MT4LC1M16E5TG-x MT4LC1M16E5TG-x S MT4C1M16E5DJ-x MT4C1M16E5TG-x Vcc REFRESH PACKAGE REFRESH 3.3V 1K 400-SOJ Standard 3.3V 1K 400-SOJ Self 3.3V 1K 400-TSOP Standard 3.3V 1K 400-TSOP Self 5V 1K 400-SOJ Standard 5V 1K 400-TSOP Standard NOTE: “-x” indicates speed grade marking under timing options. MT4LC1M16E5TG-6 NOTE: 1. The third field distinguishes the low voltage offering: LC designates Vcc = 3.3V and C designates Vcc = 5V. 2. Available only on MT4LC1M16E5 (3.3V) GENERAL DESCRIPTION The 1 Meg x 16 is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x16 configuration. The 1 Meg x 16 has both BYTE WRITE and WORD WRITE access cycles via two CAS# pins (CASL# and CASH#). These function like a single CAS# found on other DRAMs in that either CASL# or CASH# will generate an internal CAS#. The CAS# function and timing are determined by the first CAS# (CASL# or CASH#) to transition LOW and the last CAS# to transition back HIGH. Using only one KEY TIMING PARAMETERS SPEED -5 -6 tRC tRAC tPC tAA tCAC tCAS 84ns 104ns 50ns 60ns 20ns 25ns 25ns 30ns 15ns 17ns 8ns 10ns 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 1 ©2001, Micron Technology, Inc PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 16Mb: 1 MEG x16 EDO DRAM GENERAL DESCRIPTION (continued) of the two signals results in a BYTE WRITE cycle. CASL# transitioning LOW selects an access cycle for the lower byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15). Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are entered 10 bits (A0-A9) at a time. RAS# is used to latch the first 10 bits and CAS#, the latter 10 bits. The CAS# function also determines whether the cycle will be a refresh cycle (RAS# ONLY) or an active cycle (READ, WRITE or READ-WRITE) once RAS# goes LOW. The CASL# and CASH# inputs internally generate a CAS# signal that functions like the single CAS# input on other DRAMs. The key difference is each CAS# input (CASL# and CASH#) controls its corresponding eight DQ inputs during WRITE accesses. CASL# controls DQ0-DQ7, and CASH# controls DQ8-DQ15. The two CAS# controls give the 1 Meg x 16 both BYTE READ and BYTE WRITE cycle capabilities. A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE or CAS# (CASL# or CASH#), whichever occurs last. An EARLY WRITE occurs when WE is taken LOW prior to either CAS# falling. A LATE WRITE or READ-MODIFYWRITE occurs when WE falls after CAS# (CASL# or CASH#) was taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READMODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location. The 16 data inputs and 16 data outputs are routed through 16 pins using common I/O. Pin direction is controlled by OE# and WE#. The 1 Meg x 16 DRAM must be refreshed periodically in order to retain stored data. RAS# V IH V IL CASL#/CASH# V IH V IL ADDR V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) DQ V IOH V IOL OPEN VALID DATA (A) tOD tOES VALID DATA (A) VALID DATA (B) tOD tOEHC VALID DATA (C) tOD VALID DATA (D) OE# V IH V IL tOE tOEP The DQs go back to Low-Z if tOES is met. The DQs remain High-Z until the next CAS# cycle if tOEHC is met. The DQs remain High-Z until the next CAS# cycle if tOEP is met. DON’T CARE UNDEFINED Figure 1 OE# Control of DQs 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM PAGE ACCESS Page operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a rowaddress-defined page boundary. The page cycle is always initiated with a row address strobed in by RAS#, followed by a column address strobed in by CAS#. Additional columns may be accessed by providing valid column addresses, strobing CAS# and holding RAS# LOW, thus executing faster memory cycles. Returning RAS# HIGH terminates the page mode of operation, i.e., closes the page. while RAS# remains LOW, data will transition to and remain High-Z (refer to Figure 1). WE# can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2. During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle banks of DRAMs. Alternatively, pulsing WE# to the idle banks during CAS# HIGH time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is referenced from the rising edge of RAS# or CAS#, whichever occurs last. EDO PAGE MODE The 1 Meg x 16 provides EDO PAGE MODE, which is an accelerated FAST-PAGE-MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# returns HIGH. EDO provides for CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control provides for pipelined READs. FAST-PAGE-MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO-PAGE-MODE DRAMs operate like FAST-PAGE-MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, provided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH BYTE ACCESS CYCLE The BYTE WRITEs and BYTE READs are determined by the use of CASL# and CASH#. Enabling CASL# selects a lower BYTE access (DQ0-DQ7). Enabling CASH# selects an upper BYTE access (DQ8-DQ15). Enabling both CASL# and CASH# selects a WORD WRITE cycle. The 1 Meg x 16 may be viewed as two 1 Meg x 8 DRAMs that have common input controls, with the exception of the CAS# inputs. Figure 3 illustrates the BYTE WRITE and WORD WRITE cycles. Additionally, both bytes must always be of the same mode of operation if both bytes are active. A CAS# precharge must be satisfied prior to changing modes of operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE on the other byte are not allowed during the same cycle. RAS# V IH V IL CASL#/CASH# V IH V IL ADDR V IH V IL ROW COLUMN (A) COLUMN (B) COLUMN (C) COLUMN (D) DQ V IOH V IOL OPEN VALID DATA (A) tWHZ VALID DATA (B) tWHZ INPUT DATA (C) WE# V IH V IL V IH V IL tWPZ OE# The DQs go to High-Z if WE# falls, and if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated). DON‘T CARE UNDEFINED Figure 2 WE# Control of DQs 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM However, an EARLY WRITE on one byte and a LATE WRITE on the other byte, after a CAS# precharge has been satisfied, are permissible. distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode. The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-toHIGH transition. If the DRAM controller uses a distributed refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller utilizes a RAS#-ONLY or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation. DRAM REFRESH Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all 1,024 combinations of RAS# addresses are executed within tREF (MAX), regardless of sequence. The CBR, EXTENDED and SELF REFRESH cycles will invoke the internal refresh counter for automatic RAS# addressing. An optional self refresh mode is available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125µs per row, when using a WORD WRITE RAS# STANDBY Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time. LOWER BYTE WRITE CASL# CASH# WE# STORED DATA 1 1 0 INPUT DATA 0 0 1 0 0 0 0 0 INPUT DATA STORED DATA 0 0 1 0 0 0 0 0 STORED DATA 0 0 1 0 0 0 0 0 INPUT DATA 1 1 0 1 1 1 1 1 INPUT DATA STORED DATA 1 1 0 1 1 1 1 1 LOWER BYTE (DQ0-DQ7) OF WORD 1 1 1 1 1 UPPER BYTE (DQ8-DQ15) OF WORD 0 1 0 1 0 0 0 0 X X X X X X X X ADDRESS 0 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 X X X X X X X X ADDRESS 1 1 0 1 0 1 1 1 1 X = NOT EFFECTIVE (DON'T CARE) Figure 3 WORD and BYTE WRITE Example 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM FUNCTIONAL BLOCK DIAGRAM WE# CASL# CASH# DQ0 16 NO. 2 CLOCK GENERATOR DATA-OUT BUFFER 10 CAS# DATA-IN BUFFER DQ15 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10 COLUMNADDRESS BUFFER REFRESH CONTROLLER COLUMN DECODER 16 1,024 OE# 16 SENSE AMPLIFIERS I/O GATING REFRESH COUNTER 10 ROW DECODER 1,024 x 16 ROWADDRESS BUFFERS (10) 10 1,024 1,024 x 1,024 x 16 MEMORY ARRAY RAS# NO. 1 CLOCK GENERATOR VDD VSS 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VCC Pin Relative to VSS 3.3V ......................................................... -1V to +4.6V 5V ............................................................... -1V to +7V Voltage on NC, Inputs or I/O Pins Relative to Vss: 3.3V ......................................................... -1V to +5.5V 5V ............................................................... -1V to +7V Operating Temperature TA (commercial) .................................. 0ºC to +70ºC TA (extended) ................................... -20ºC to +80ºC Storage Temperature (plastic) ........... -55ºC to +150ºC Power Dissipation ........................................................ 1W Short Circuit Output Current ................................ 50mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1; notes appear on pages 10-11) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Valid Logic 1; All inputs, I/Os and any NC INPUT LOW VOLTAGE: Valid Logic 0; All inputs, I/Os and any NC INPUT LEAKAGE CURRENT: Any input at VIN (0V £ VIN £ VIH[MAX]); All other pins not under test = 0V OUTPUT HIGH VOLTAGE: IOUT = -2mA(3.3V), -5mA(5V) OUTPUT LOW VOLTAGE: IOUT = 2mA(3.3V), 4.2mA(5V) OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V £ VOUT £ 5.5V); DQ is disabled and in High-Z state SYMBOL VCC VIH VIL II 3.3V MIN MAX 3.0 2.0 -1.0 -2 3.6 5.5 0.8 2 5V MIN 4.5 2.4 -0.5 -2 MAX 5.5 VCC + 1 0.8 2 UNITS NOTES V V V µA 4 VOH VOL IOZ 2.4 – -5 – 0.4 5 2.4 – -5 – 0.4 5 V V µA 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM ICC OPERATING CONDITIONS AND MAXIMUM LIMITS (Notes: 1, 2, 3, 5, 8; notes appear on pages 10-11); (VCC[MIN] £ VCC £ VCC[MAX]) PARAMETER/CONDITION STANDBY CURRENT: TTL (RAS# = CAS# = VIH) STANDBY CURRENT: CMOS (non-“S” version only) (RAS# = CAS# = other inputs = VDD - 0.2V) STANDBY CURRENT: CMOS (“S” version only) (RAS# = CAS# = other inputs = VDD - 0.2V) OPERATING CURRENT: Random READ/WRITE Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) OPERATING CURRENT: EDO PAGE MODE Average power supply current (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN]) REFRESH CURRENT: RAS#-ONLY Average power supply current (RAS# cycling, CAS# = VIH: tRC = tRC [MIN]) REFRESH CURRENT: CBR Average power supply current (RAS#, CAS#, address cycling: tRC = tRC [MIN]) REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; RAS# = tRAS (MIN); WE# = VDD - 0.2V; A0-A10, OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open); tRC = 125µs REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS# tRASS (MIN) and CAS# held LOW; WE# = VDD - 0.2V; A0-A10, OE# and DIN = VDD - 0.2V or 0.2V (DIN may be left open) SYMBOL SPEED ICC1 ICC2 ICC2 ICC3 ALL ALL ALL -5 -6 -5 -6 -5 -6 -5 -6 ALL 3.3V 1 500 150 180 170 140 130 180 170 180 170 300 5V 2 500 150 190 180 150 140 190 180 180 170 300 UNITS NOTES mA µA µA mA 6 ICC4 mA 6 ICC5 mA ICC6 mA 7, 9 ICC7 µA 7, 9 ICC8 ALL 300 300 µA 7, 9 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM CAPACITANCE (Notes: 1, 2, 3, 5, 8; notes appear on pages 10-11) PARAMETER Input Capacitance: Addresses Input Capacitance: RAS#, CASL#,CASH#, WE#, OE# Input/Output Capacitance: DQ SYMBOL MAX UNITS NOTES CI1 CI2 CIO 5 7 7 pF pF pF AC ELECTRICAL CHARACTERISTICS (Notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (VCC[MIN] £ VCC £ VCC[MAX]) AC CHARACTERISTICS PARAMETER Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) Last CAS# going LOW to first CAS# to return HIGH CAS# to output in Low-Z Data output hold after next CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable OE# hold time from WE# during READ-MODIFY-WRITE cycle OE# HIGH hold from CAS# HIGH OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay -5 SYMBOL tAA tACH tAR tASC tASR tAWD tCAC tCAH tCAS tCHD tCHR tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tCSR tCWD tCWL tDH tDS tOD tOE tOEH tOEHC tOEP tOES tOFF -6 MAX 25 MIN 15 45 0 0 49 13 15 10 10 15 10 5 0 3 10 5 45 5 35 10 10 0 0 10 10 5 5 0 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES MIN 12 38 0 0 42 8 8 15 8 5 0 3 8 5 38 5 28 8 8 0 0 8 5 5 4 0 10,000 25 25 13 14, 25 25 27 7, 26 28 26 15, 30 26 26 26 7, 25 13, 25 26 16, 25 16, 25 17 18 18 28 35 12 12 15 15 12 15 20, 26 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM AC ELECTRICAL CHARACTERISTICS (continued) (Notes: 2, 3, 9, 10, 11, 12; notes appear on pages 10-11); (VCC[MIN] £ VCC £ VCC[MAX]) AC CHARACTERISTICS PARAMETER OE# setup prior to RAS# during HIDDEN REFRESH cycle EDO-PAGE-MODE READ or WRITE cycle time EDO-PAGE-MODE READ-WRITE cycle time Access time from RAS# RAS# to column-address delay time Row address hold time RAS# pulse width RAS# pulse width (EDO PAGE MODE) RAS# pulse width during Self Refresh Random READ or WRITE cycle time RAS# to CAS# delay time READ command hold time (referenced to CAS#) READ command setup time Refresh period (1,024 cycles) Refresh period (1,024 cycles) S version RAS# precharge time RAS# to CAS# precharge time RAS# precharge time exiting Self Refresh READ command hold time (referenced to RAS#) RAS# hold time READ-WRITE cycle time RAS# to WE# delay time WRITE command to RAS# lead time Transition time (rise or fall) WRITE command hold time WRITE command hold time (referenced to RAS#) WE# command setup time Output disable delay from WE# WRITE command pulse width WE# pulse to disable at CAS# HIGH WE# hold time (CBR Refresh) WE# setup time (CBR Refresh) -5 SYMBOL tORD tPC tPRWC tRAC tRAD tRAH tRAS tRASP tRASS tRC tRCD tRCH tRCS tREF tREF tRP tRPC tRPS tRRH tRSH tRWC tRWD tRWL tT tWCH tWCR tWCS tWHZ tWP tWPZ tWRH tWRP -6 MAX MIN 0 25 56 50 60 12 10 60 60 100 104 14 0 0 MAX UNITS NOTES ns ns ns ns ns ns ns ns µs ns ns ns ns ms ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 31 31 19 21 MIN 0 20 47 9 9 50 50 100 84 11 0 0 10,000 125,000 10,000 125,000 22, 25 23, 27 25 16 128 30 5 90 0 13 116 67 13 2 8 38 0 0 5 10 8 8 40 5 105 0 15 140 79 15 2 10 45 0 0 5 10 10 10 16 128 23 32 13 50 50 32 13, 25 12 15 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM NOTES 1. All voltages referenced to VSS. 2. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0ºC £ TA £ 70ºC for commercial) and (-20ºC £ TA £ 80ºC for extended) is ensured. 3. An initial pause of 100µs is required after powerup, followed by eight RAS# refresh cycles (RAS#ONLY or CBR with WE# HIGH), before proper device operation is ensured. The eight RAS# cycle wake-ups should be repeated any time the tREF refresh requirement is exceeded. 4. NC pins are assumed to be left floating and are not tested for leakage. 5. ICC is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. Column address changed once each cycle. 7. Enables on-chip refresh and address counters. 8. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 9. AC characteristics assume tT = 2.5ns. 10.VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL (or between VIL and VIH). 11.In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 12.Measured with a load equivalent to two TTL gates and 100pF; and VOL = 0.8V and VOH = 2V. 13. tWCS, tRWD, tAWD, and tCWD are not restrictive operating parameters. tWCS applies to EARLY WRITE cycles. tRWD, tAWD and tCWD apply to READ-MODIFY-WRITE cycles. If tWCS tWCS (MIN), the cycle is an EARLY WRITE cycle and the data output will remain an open circuit throughout the entire cycle. If tWCS < tWCS (MIN) and tRWD tRWD (MIN), tAWD tAWD (MIN) and tCWD tCWD (MIN), the cycle is a READMODIFY-WRITE and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of data-out is indeterminate. OE# held HIGH and WE# taken LOW after CAS# goes LOW results in a LATE WRITE (OE#-controlled) cycle. tWCS, tRWD, tCWD and tAWD are not applicable in a LATE WRITE cycle. 14.Assumes that tRCD tRCD (MAX). 15.If CAS# is LOW at the falling edge of RAS#, Q will be maintained from the previous cycle. To initiate a new cycle and clear the data-out buffer, CAS# must be pulsed HIGH for tCP. 16.These parameters are referenced to CAS# leading edge in EARLY WRITE cycles and WE# leading edge in LATE WRITE or READ-MODIFY-WRITE cycles. 17.If OE# is tied permanently LOW, LATE WRITE, or READ-MODIFY-WRITE operations are not permissible and should not be attempted. Additionally, WE# must be pulsed during CAS# HIGH time in order to place I/O buffers in High-Z. 18.LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE# HIGH during WRITE cycle) in order to ensure that the output buffers will be open during the WRITE cycle. The DQs will provide the previously read data if CAS# remains LOW and OE# is taken back LOW after tOEH is met. If CAS# goes HIGH prior to OE# going back LOW, the DQs will remain open. 19.Assumes that tRCD < tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by the amount that tRCD exceeds the value shown. 20. tOFF (MAX) defines the time at which the output achieves the open circuit condition and is not referenced to VOH or VOL. It is referenced from the rising edge of RAS# or CAS#, whichever occurs last. 21.The tRAD (MAX) limit is no longer specified. tRAD (MAX) was specified as a reference point only. If tRAD was greater than the specified tRAD (MAX) limit, then access time was controlled exclusively by tAA (tRAC and tCAC no longer applied). With or without the tRAD (MAX) limit, tAA, tRAC, and tCAC must always be met. 22.The tRCD (MAX) limit is no longer specified. tRCD (MAX) was specified as a reference point only. If tRCD was greater than the specified tRCD (MAX) limit, then access time was controlled exclusively by tCAC (tRAC [MIN] no longer applied). With or without the tRCD limit, tAA and tCAC must always be met. 23.Either tRCH or tRRH must be satisfied for a READ cycle. 24.The first CAS#x edge to transition LOW. 25.Output parameter (DQx) is referenced to corresponding CAS# input; DQ0-DQ7 by CASL# and DQ8-DQ15 by CASH#. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM NOTES (continued) 26.Each CAS#x must meet minimum pulse width. 27.The last CAS#x edge to transition HIGH. 28.Last falling CAS#x edge to first rising CAS#x edge. 29.Last rising CAS#x edge to first falling CAS#x edge. 30.Last rising CAS#x edge to next cycle’s last rising CAS#x edge. 31.Last CAS#x to go LOW. 32.A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM READ CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP V IH V IL tAR tASR tRAD tRAH tASC tCAH tACH ADDR V IH V IL ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL COLUMN tRCH ROW tRCD tCAS tCLCH tRRH tRP RAS# CASL#/CASH# NOTE 1 tOFF OPEN tOE VALID DATA tOD OPEN OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tOD -6 MAX 25 MIN 15 45 0 0 13 15 10 10 5 0 5 12 45 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tRAC tRAD tRAH tRAS tRC tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 0 9 9 50 84 11 0 0 30 0 13 10,000 MAX 12 12 50 0 12 10 60 104 14 0 0 40 0 15 MIN -6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 0 5 38 0 10,000 10,000 NOTE: 1. tOFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM EARLY WRITE CYCLE tRC tRAS V IH V IL tCSH tRSH tCRP CASL#/CASH# V IH V IL tRAD tASR ADDR V IH V IL ROW tRAH COLUMN tCWL tRWL tWCS tWCR tWCH tWP WE# V IH V IL tDS V DQ V IOH IOL V IH V IL tDH tAR tASC tCAH tACH ROW tRCD tCAS tCLCH tRP RAS# VALID DATA OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCLCH tCRP tCSH tCWL tDH tDS -6 MAX MIN 15 45 0 0 10 10,000 10 5 5 45 10 10 0 10,000 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tRAD tRAH tRAS tRC tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 9 9 50 84 11 30 13 13 8 38 0 5 10,000 MAX MIN 12 10 60 104 14 40 15 15 10 45 0 5 -6 MAX UNITS ns ns 10,000 ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 5 38 8 8 0 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRWC tRAS V IH V IL tCSH tRSH tCAS, t CLCH tRP RAS# tCRP V IH V IL tAR tRAD tRAH tRCD CASL#/CASH# tASR ADDR V IH V IL tASC tCAH tACH ROW ROW COLUMN tRWD tCWD tAWD tCWL tRWL tWP tRCS WE# V IH V IL tAA tRAC tCAC tCLZ tDS VALID D OUT tOE V IH V IL tOD tDH V DQ V IOH IOL OPEN VALID D IN tOEH OPEN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tAWD tASR tCAC tCAH tCAS tCLCH tCLZ tCRP tCSH tCWD tCWL tDH -6 MAX 25 MIN 15 45 0 49 0 13 15 10 10,000 10 5 0 5 45 35 10 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tOD tOE tOEH tRAC tRAD tRAH tRAS tRCD tRCS tRP tRSH tRWC tRWD tRWL tWP -5 MIN 0 0 8 50 9 9 50 11 0 30 13 116 67 13 5 10,000 12 10 60 14 0 40 15 140 79 15 5 MAX 12 12 MIN 0 0 10 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 42 0 8 8 5 0 5 38 28 8 8 10,000 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM EDO-PAGE-MODE READ CYCLE tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tACH tRAD tRAH ROW tRCS WE# V IH V IL tAA tRAC tCAC tCLZ DQ V OH V OL OPEN tOE OE# V IH V IL tOES tOEP VALID DATA tAA tCPA tCAC tCOH VALID DATA tOD tOE tOES tCLZ tOEHC VALID DATA tOD tACH tACH tRCD tCAS, t CLCH tPC tCP tCAS, t CLCH tCP tRSH tCAS, t CLCH tCP tRP RAS# tASR ADDR V IH V IL tASC COLUMN tCAH tASC tCAH tASC tCAH ROW tRCH tRRH COLUMN COLUMN tAA tCPA tCAC tOFF OPEN DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCOH tCP tCPA tCRP tCSH tOD -6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 5 0 3 10 28 35 5 12 45 0 15 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOEHC tOEP tOES tOFF tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRRH tRSH -5 MIN 5 5 4 0 20 9 9 50 11 0 0 30 0 13 125,000 12 50 12 10 60 14 0 0 40 0 15 MAX 12 MIN 10 5 5 0 25 -6 MAX 15 UNITS ns ns ns ns 15 60 ns ns ns ns 1ns 125,000 ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 0 3 8 5 38 0 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM EDO-PAGE-MODE EARLY WRITE CYCLE tRASP V IH V IL tCSH tCRP V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH tACH tASC tCAH tACH tASC tCAH tACH tASC tCAH tRCD tCAS, t CLCH tPC tCP tCAS, t CLCH tCP tRSH tCAS, t CLCH tCP tRP RAS# CASL#/CASH# ROW COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP COLUMN tCWL tWCH tWP ROW tWCS tWCS tWCS WE# V IH V IL tWCR tDS tDH tDS tDH tDS tRWL tDH V DQ V IOH IOL V IH V IL VALID DATA VALID DATA VALID DATA OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tACH tAR tASC tASR tCAH tCAS tCLCH tCP tCRP tCSH tCWL tDH tDS -6 MAX MIN 15 45 0 0 10 10 5 10 5 45 10 10 0 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tPC tRAD tRAH tRASP tRCD tRP tRSH tRWL tWCH tWCR tWCS tWP -5 MIN 20 9 9 50 11 30 13 13 8 38 0 5 MAX MIN 25 12 10 60 14 40 15 15 10 45 0 5 -6 MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 8 5 38 8 8 0 125,000 125,000 10,000 10,000 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE cycles) tRASP V IH V IL tCSH tCRP CASL#/CASH# V IH V IL tAR tRAD tRAH tRCD tCAS, tCLCH tCP tPC tPRWC NOTE 1 tCAS, tCLCH tCP tRSH tCAS, tCLCH tCP tRP RAS# tASR ADDR V IH V IL tASC tCAH tASC tCAH tASC tCAH ROW COLUMN tRWD tRCS tCWL tWP tAWD tCWD COLUMN COLUMN tRWL tCWL tAWD tCWD tWP ROW tCWL tWP tAWD tCWD WE# V IH V IL tAA tRAC tDH tDS tCAC tCLZ tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD tOE tOE VALID VALID D OUT D IN tOD tOE tDH tDS tAA tCPA tCAC tCLZ VALID VALID D OUT D IN tOD tOEH OPEN tDH tDS DQ V IOH V IOL OPEN OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tAWD tCAC tCAH tCAS tCLCH tCLZ tCP tCPA tCRP tCSH tCWD tCWL tDH -6 MAX 25 MIN 45 0 0 49 13 15 10 10 5 0 10 28 35 5 45 35 10 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tOD tOE tOEH tPC tPRWC tRAC tRAD tRAH tRASP tRCD tRCS tRP tRSH tRWD tRWL tWP -5 MIN 0 0 8 20 47 50 9 9 50 11 0 30 13 67 13 5 125,000 12 10 60 14 0 40 15 79 15 5 MAX 12 12 MIN 0 0 10 25 56 -6 MAX 15 15 UNITS ns ns ns ns ns 60 ns ns ns ns ns ns ns ns ns ns ns ns MIN 38 0 0 42 8 8 5 0 8 5 38 28 8 8 10,000 125,000 NOTE: 1. tPC is for LATE WRITE cycles only. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM EDO-PAGE-MODE READ EARLY WRITE CYCLE (Pseudo READ-MODIFY-WRITE) t RASP RAS# V IH V IL t CSH tPC tCRP CASL#/CASH# V IH V IL tAR tRAD tASR ADDR V IH V IL tRAH ROW tASC tCAH t ASC t CAH tASC t ACH t CAH t RCD t CAS, tCLCH t CP t CAS, tCLCH tPC t CP tRSH t CAS, tCLCH t CP t RP COLUMN (A) tRCS COLUMN (B) tRCH COLUMN (N) tWCS tWCH ROW WE# V IH V IL tRAC tAA tCPA tCAC tAA tCAC tCOH t WHZ VALID DOUT t DS t DH DQ V IOH V IOL V IH V IL OPEN tOE VALID DOUT VALID DIN OE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tACH tAR tASC tASR tCAC tCAH tCAS tCLCH tCOH tCP tCPA tCRP tCSH tDH -6 MAX 25 MIN 15 45 0 0 13 15 10 10,000 10 5 3 10 28 35 5 45 10 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL tDS tOE tPC tRAC tRAD tRAH tRASP tRCD tRCH tRCS tRP tRSH tWCH tWCS tWHZ -5 MIN 0 12 20 50 9 9 50 11 0 0 30 13 8 0 0 125,000 12 10 60 14 0 0 40 15 10 0 0 25 MAX MIN 0 -6 MAX 15 60 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MIN 12 38 0 0 8 8 5 3 8 5 38 8 125,000 12 15 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM READ CYCLE (with WE#-controlled disable) RAS# V IH V IL tCSH tCRP V IH V IL tAR tASR V IH V IL tRAD tRAH tASC tCAH tASC tRCD tCAS, t CLCH tCP CASL#/CASH# ADDR ROW tRCS COLUMN tRCH tWPZ tRCS COLUMN WE# V IH V IL tAA tRAC tCAC tCLZ tWHZ tCLZ V DQ V OH OL OPEN tOE VALID DATA tOD OPEN OE# V IH V IL DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCAS tCLCH tCLZ tCP tCRP -6 MAX 25 MIN 45 0 0 13 15 10 10,000 10 5 0 10 5 10,000 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns ns SYMBOL tCSH tOD tOE tRAC tRAD tRAH tRCD tRCH tRCS tWHZ tWPZ -5 MIN 38 0 MAX 12 12 50 MIN 45 0 -6 MAX 15 15 60 UNITS ns ns ns ns ns ns ns ns ns 15 ns ns MIN 38 0 0 8 8 5 0 8 5 9 9 11 0 0 0 10 12 12 10 14 0 0 0 10 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM RAS#-ONLY REFRESH CYCLE (OE# and WE# = DON’T CARE) tRC tRAS V IH V IL tCRP V IH V IL tASR ADDR V IH V IL tRAH tRPC tRP RAS# CASL#/CASH# ROW ROW V Q V OH OL OPEN CBR REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP RAS# V IH V IL tRPC tCP CASL#/CASH# V IH V IL V OH V OL tWRP WE# V IH V IL tWRH OPEN tWRP tWRH tCSR tCHR tRPC tCSR tCHR tRAS NOTE 1 tRP tRAS DQ DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tASR tCHR tCP tCRP tCSR tRAH -6 MAX MIN 0 10 10 5 5 10 MAX UNITS ns ns ns ns ns ns SYMBOL tRAS tRC tRP tRPC tWRH tWRP -5 MIN 50 84 30 5 8 8 MAX 10,000 MIN 60 104 40 5 10 10 -6 MAX 10,000 UNITS ns ns ns ns ns ns MIN 0 8 8 5 5 9 NOTE: 1. End of first CBR REFRESH cycle. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM HIDDEN REFRESH CYCLE (WE# = HIGH; OE# = LOW) tRC tRAS RAS# V IH V IL tCRP V IH V IL tAR tRAD tASR V IH V IL tRAH tASC tCAH tRCD tRSH tCHR tRP tRAS CASL#/CASH# ADDR ROW COLUMN tAA tRAC tCAC tCLZ tOFF DQx V IOH V IOL OPEN tOE VALID DATA tOD OPEN OE# V IH V IL tORD DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tAA tAR tASC tASR tCAC tCAH tCHR tCLZ tCRP tOD -6 MAX 25 MIN 45 0 0 13 15 10 10 0 5 12 0 15 MAX 30 UNITS ns ns ns ns ns ns ns ns ns ns SYMBOL tOE tOFF tORD tRAC tRAD tRAH tRAS tRCD tRP tRSH -5 MIN 0 0 9 9 50 11 30 13 10,000 MAX 12 12 50 12 10 60 14 40 15 0 0 MIN -6 MAX 15 15 60 UNITS ns ns ns ns ns ns 10,000 ns ns ns ns MIN 38 0 0 8 8 0 5 0 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) tRP V IH V IL tRASS NOTE 1 (( )) (( )) tCSR tCHD (( )) (( )) (( )) tWRP tWRH (( )) (( )) OPEN tWRP tWRH tRPS NOTE 2 RAS# tRPC tCP tRPC tCP (( )) CASL#/ CASH# V IH V IL V OH V OL V IH V IL DQ WE# DON’T CARE UNDEFINED TIMING PARAMETERS -5 SYMBOL tCHD tCLCH tCP tCSR tRASS MIN 15 5 8 5 100 MAX MIN 15 5 10 5 100 -6 MAX UNITS ns ns ns ns µs SYMBOL tRP tRPC tRPS tWRH tWRP MIN 30 5 90 8 8 -5 MAX MIN 40 5 105 10 10 -6 MAX UNITS ns ns ns ns ns NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM 44/50-PIN PLASTIC TSOP (400 mil) .828 (21.04) .822 (20.88) 50 SEE DETAIL A .029 (0.75) TYP .467 (11.86) .459 (11.66) .402 (10.21) .398 (10.11) 1 PIN #1 INDEX .031 (0.80) TYP .018 (0.45) .012 (0.30) 25 .007 (0.18) .005 (0.13) .004 (0.10) .047 (1.20) MAX SEATING PLANE .008 (0.20) .002 (0.05) DETAIL A .010 (0.25) .024 (0.60) .016 (0.40) .032 (0.80) TYP NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc 16Mb: 1 MEG x16 EDO DRAM 42-PIN PLASTIC SOJ (400 mil) 1.079 (27.41) 1.073 (27.25) .405 (10.29) .399 (10.13) .445 (11.30) .435 (11.05) PIN #1 INDEX .050 (1.27) TYP 1.000 (25.40) .032 (0.81) .026 (0.66) .148 (3.76) .138 (3.51) .095 (2.40) .080 (2.02) SEATING PLANE .037 (0.94) MAX DAMBAR PROTRUSION .020 (0.51) .015 (0.38) .380 (9.65) .360 (9.14) .030 (0.76) MIN NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and the M logos are trademarks of Micron Technology, Inc. 1 Meg x 16 EDO DRAM D52_B.p65 – Rev. B; Pub. 3/01 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2001, Micron Technology, Inc