4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
4Mb
ZBT® SRAM
MT55L256L18P1, MT55L256V18P1,
MT55L128L32P1, MT55L128V32P1,
MT55L128L36P1, MT55L128V36P1
3.3V VDD, 3.3V or 2.5V I/O
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
100-Pin TQFP1
High frequency and 100 percent bus utilization
Fast cycle times: 6ns, 7.5ns and 10ns
Single +3.3V ±5% power supply (VDD)
Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
Advanced control logic for minimum control signal
interface
Individual BYTE WRITE controls may be tied LOW
Single R/W# (read/write) control pin
CKE# pin to enable clock and suspend operations
Three chip enables for simple depth expansion
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed, fully coherent WRITE
Internally self-timed, registered outputs to
eliminate the need to control OE#
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Linear or interleaved burst modes
Burst feature (optional)
Pin/function compatibility with 2Mb, 8Mb, and
16Mb ZBT SRAM family
Automatic power-down
165-pin FBGA package
100-pin TQFP package
OPTIONS
165-Pin FBGA
MARKING
• Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Package
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
-6
-7.5
-10
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
MT55L256L18P1
MT55L128L32P1
MT55L128L36P1
GENERAL DESCRIPTION
MT55L256V18P1
MT55L128V32P1
MT55L128V36P1
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 4Mb ZBT SRAMs integrate a 256K x 18,
128K x 32, or 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.
These SRAMs are optimized for 100 percent bus utilization, eliminating any turnaround cycles when
transitioning from READ to WRITE, or vice versa. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
T
F*
None
IT
Part Number Example:
MT55L256L18P1T-10
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
1
©2003, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
18
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
MODE
CLK
CKE#
16
18
ADDRESS
REGISTER 0
SA0, SA1, SA
ADV/LD#
K
K
18
WRITE ADDRESS
REGISTER 2
WRITE ADDRESS
REGISTER 1
18
S
E
N
S
E
ADV/LD#
256K x 9 x 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa#
WRITE
DRIVERS
36
BWb#
O
U
T
P
U
T
MEMORY
ARRAY
R
E
G
I
S
T
E
R
S
A
M
P
S
R/W#
36
OE#
CE#
CE2
CE2#
B
U
F
F
E
R
S
S
T
E
E
R
I
N
G
E
INPUT
REGISTER 1 E
O
U
T
P
U
T
D
A
T
A
36
DQPa
DQPb
E
36
INPUT
REGISTER 0 E
READ LOGIC
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
SA0, SA1, SA
17
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
MODE
CLK
CKE#
15
17
ADDRESS
REGISTER 0
ADV/LD#
K
K
WRITE ADDRESS
REGISTER 1
17
WRITE ADDRESS
REGISTER 2
17
ADV/LD#
BWa#
BWb#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
128K x 8 x 4
(x32)
36
BWc#
WRITE
DRIVERS
128K x 9 x 4
(x36)
MEMORY
ARRAY
BWd#
R/W#
O
U
T
P
U
T
S
E
N
S
E
R
E
G
I
S
T
E
R
S
A
M
P
S
E
INPUT
REGISTER 1 E
OE#
CE#
CE2
CE2#
36
D
A
T
A
S
T
E
E
R
I
N
G
INPUT
REGISTER 0 E
O
U
T
P
U
T
B
U
F
F
E
R
S
36
DQs
DQPa
DQPb
DQPc
DQPd
E
36
READ LOGIC
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
GENERAL DESCRIPTION (continued)
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a LATE LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# controls DQa pins; BWb# controls DQb pins; BWc# controls
DQc pins; and BWd# controls DQd pins. Cycle types
can only be defined when an address is loaded, i.e.,
when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions.
Micron’s 4Mb ZBT SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are LVTTLcompatible. Users can choose either a 2.5V or 3.3V I/O
version. The device is ideally suited for systems requiring high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#) and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which may
be tied LOW if unused). There is also a burst mode pin
(MODE) that selects between interleaved and linear
burst modes. MODE may be tied HIGH, LOW or left
unconnected if burst is unused. The data-out (Q), enabled by OE#, is registered by the rising edge of CLK.
WRITE cycles can be from one to four bytes wide as
controlled by the write control inputs.
All READ, WRITE and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst addresses can be internally generated as controlled by
the burst advance pin (ADV/LD#). Use of burst mode
is optional. It is allowable to give an address for each
individual READ and WRITE cycle. BURST cycles wrap
around after the fourth access from a base address.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN ASSIGNMENT TABLE
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NC
x32
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VDD
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
x36
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
PIN# x18
x32
x36
26
VSS
27
VDDQ
28
NC
DQd
DQd
29
NC
DQd
DQd
30
NC
NC
DQd
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
VSS
41
VDD
42
DNU
43
DNU
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
PIN#
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
NC
x32
NC
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
x36
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
PIN# x18
x32
x36
76
VSS
77
VDDQ
78
NC
DQb
DQb
79
NC
DQb
DQb
80
SA
NC
DQb
81
SA
82
SA
83
NF*
84
NF*
85
ADV/LD#
86
OE# (G#)
87
CKE#
88
R/W#
89
CLK
90
VSS
91
VDD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc# BWc#
96
NC
BWd# BWd#
97
CE2
98
CE#
99
SA
100
SA
* Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
SA
NC
NC
VDDQ
VSS
NC
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VDD
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
Pin Assignment (Top View)
100-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x18
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC/DQb*
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VDD
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC/DQa*
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD
VDD
VDD
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
NC
VSS
VDDQ
NC
NC
NC
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x32/x36
SA
SA
SA
SA
SA
SA
SA
DNU
DNU
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NC/DQc*
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VDD
VDD
VDD
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC/DQd*
SA
SA
NF**
NF**
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 83 and 84 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
37
37
36
36
32–35, 44–50, 32–35, 44–50,
80–82, 99, 100 81, 82, 99, 100
SYMBOL
SA0
SA1
SA
TYPE
Input
93
94
–
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
89
89
CLK
Input
98
98
CE#
Input
92
92
CE2#
Input
97
97
CE2
Input
86
86
OE#
(G#)
Input
85
85
ADV/LD#
Input
87
87
CKE#
Input
64
64
ZZ
Input
DESCRIPTION
Synchronous Address Inputs: These inputs are registered
and must meet the setup and hold times around the
rising edge of CLK. Pins 83 and 84 are reserved as address
bits for higher-density 8Mb and 16Mb ZBT SRAMs,
respectively. SA0 and SA1 are the two least significant
bits (LSB) of the address field and set the internal burst
counter if burst is desired.
Synchronous Byte Write Enables: These active LOW
inputs allow individual bytes to be written when a
WRITE cycle is active and must meet the setup and hold
times around the rising edge of CLK. BYTE WRITEs need
to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data.
BWa# controls DQa pins; BWb# controls DQb pins; BWc#
controls DQc pins; BWd# controls DQd pins.
Clock: This signal registers the address, data, chip
enables, byte write enables and burst control inputs on
its rising edge. All synchronous inputs must meet setup
and hold times around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used
to enable the device and is sampled only when a new
external address is loaded (ADV/LD# LOW). This input
can be used for memory depth expansion.
Output Enable: This active LOW, asynchronous input
enables the data I/O output drivers. G# is the JEDECstandard term for OE#.
Synchronous Address Advance/Load: When HIGH, this
input is used to advance the internal burst counter,
controlling burst access after the external address is
loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW
on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Clock Enable: This active LOW input
permits CLK to propagate throughout the device. When
CKE# is HIGH, the device ignores the CLK input and
effectively internally extends the previous CLK cycle. This
input must meet setup and hold times around the rising
edge of CLK.
Snooze Enable: This active HIGH, asynchronous input
causes the device to enter a low-power standby mode in
which all data in the memory array is retained. When ZZ
is active, all other inputs are ignored.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
88
x32/x36
88
(a) 58, 59, 62,
(a) 52, 53,
63, 68, 69,
56–59, 62, 63
72–74
(b) 8, 9, 12, 13,
(b) 68, 69,
18, 19, 22–24 72–75, 78, 79
(c) 2, 3, 6–9,
12, 13
(d) 18, 19,
22–25, 28, 29
N/A
51
80
1
30
31
31
SYMBOL
R/W#
TYPE
Input
DQa
Input/
Output
DQb
DESCRIPTION
Read/Write: This input determines the cycle type when
ADV/LD# is LOW and is the only means for determining
READs and WRITEs. READ cycles may not be converted
into WRITEs (and vice versa) other than by loading a
new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs
occur if all byte write enables are LOW.
SRAM Data I/Os: Byte “a” is DQa pins; Byte “b” is DQb
pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input
data must meet setup and hold times around the rising
edge of CLK.
DQc
DQd
NC/DQa
NC/DQb
NC/DQc
NC/DQd
MODE
(LBO#)
NC/
I/O
Input
No Connect/Data Bits: On the x32 version, these pins are
no connect (NC) and can be left floating or connected
to GND to minimize thermal impedance. On the x36
version, these bits are DQs.
Mode: This input selects the burst sequence. A LOW on
this pin selects linear burst. NC or HIGH on this pin selects
interleaved burst. Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
1-3, 6, 7, 25,
28–30, 51–53,
56, 57, 75, 78,
79, 95, 96
N/A
NC
NC
No Connect: These pins can be left floating or connected
to GND to minimize thermal impedance.
83, 84
83, 84
NF
–
38, 39, 42, 43
38, 39, 42, 43
DNU
–
14, 15, 16, 41,
65, 66, 91
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 17, 21,
26, 40, 55, 60,
67, 71, 76, 90
14, 15, 16, 41,
65, 66, 91
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 17, 21,
26, 40, 55, 60,
67, 71, 76, 90
VDD
Supply
VDDQ
Supply
V SS
Supply
No Function: These are internally connected to the die
and will have the capacitance of input pins. It is
allowable to leave these pins unconnected or driven by
signals. Reserved for address expansion, pin 83 becomes
an SA at 8Mb density and pin 84 becomes an SA at
16Mb density.
Do Not Use: These signals may either be unconnected or
wired to GND to minimize thermal impedance.
Power Supply: See DC Electrical Characteristics and
Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical
Characteristics and Operating Conditions for range.
Ground: GND.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
PIN LAYOUT (Top View)
165-Pin FBGA
x18
x32/x36
10
11
CKE# ADV/LD# NC
SA
SA
R/W# OE# (G#)
NC
SA
NC
VSS
VDDQ
NC
DQPa
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQPb
NC
VDDQ
VSS
NC
NC
VDD
VSS
VDDQ
NC
NC
NC
NC
SA
SA
DNU
SA1
DNU
SA
SA
SA
NC
MODE
(LBO#)
NC
SA
SA
DNU
SA0
DNU
SA
SA
SA
SA
1
2
3
4
5
6
7
NC
SA
CE#
BWb#
NC
CE2#
NC
SA
CE2
NC
BWa#
CLK
NC
NC
VDDQ
VSS
VSS
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
NC
DQb
VDDQ
VDD
NC
DQb
VDDQ
VDD
VDD
DQb
8
9
A
A
B
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
NC/DQPd*
NC
VDDQ
VSS
NC
NC
VDD
VSS
VDDQ
NC
NC/DQPa*
NC
NC
SA
SA
DNU
SA1
DNU
SA
SA
SA
NC
MODE
(LBO#)
NC
SA
SA
DNU
SA0
DNU
SA
SA
SA
SA
NC/DQPc*
NC
VDDQ
VSS
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
DQc
DQc
VDDQ
VDD
DQc
DQc
VDDQ
VDD
VDD
DQd
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/DQPb*
CLK
M
N
P
NC
BWd# BWa#
L
M
N
VDDQ
CE2
K
L
M
VSS
SA
A
J
K
L
NC
NC
9
H
J
K
SA
CE2#
8
G
H
J
NC
BWc# BWb#
7
F
G
H
R/W# OE# (G#)
CE#
6
E
F
G
NC
SA
5
D
E
F
SA
NC
4
C
D
E
CKE# ADV/LD# NC
3
B
C
D
11
2
A
B
C
10
1
N
P
R
P
R
R
TOP VIEW
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: 1. Pins 9A, and 9B reserved for address pin expansion; 8Mb, and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
6R
6R
6P
6P
2A, 2B, 3P, 3R, 2A, 2B, 3P, 3R,
4P, 4R, 8P, 8R, 4P, 4R, 8P, 8R,
9P, 9R, 10A,
9P, 9R, 10A,
10B, 10P,
10B, 10P,
10R, 11A, 11R
10R, 11R
SYMBOL
TYPE
SA0
SA1
SA
Input
Synchronous Address Inputs: These inputs are registered and must
meet the setup and hold times around the rising edge of CLK.
DESCRIPTION
5B
4A
–
–
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
6B
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device. CE# is sampled only when a new external address is
loaded.
6A
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
7A
7A
CKE#
Input
11H
11H
ZZ
Input
Synchronous Clock Enable: This active LOW input permits CLK to
propagate throughout the device. When CKE# is HIGH, the device
ignores the CLK input and effectively internally extends the
previous CLK cycle. This input must meet setup and hold times
around the rising edge of CLK.
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
7B
7B
R/W#
Input
3B
3B
CE2
Input
8B
8B
OE#(G#)
Input
Read/Write: This input determines the cycle type when ADV/LD# is
LOW and is the only means for determining READs and WRITEs.
READ cycles may not be converted into WRITEs (and vice versa)
other than by loading a new address. A LOW on this pin permits
BYTE WRITE operations and must meet the setup and hold times
around the rising edge of CLK. Full bus-width WRITEs occur if all
byte write enables are LOW.
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
8A
8A
ADV/LD#
Input Synchronous Address Advance/Load: When HIGH, this input is
used to advance the internal burst counter, controlling burst
access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new
address at the CLK rising edge.
1R
1R
MODE
(LB0#)
(a) 10J, 10K, (a) 10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b) 1J, 1K,
(b) 10D, 10E,
1L, 1M, 2D, 10F, 10G, 11D,
2E, 2F, 2G
11E, 11F, 11G
(c) 1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
DQa
DQb
Input
DESCRIPTION
Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQa’s;
Output Byte “b” is associated with DQb’s. For the x32 and x36 versions,
Byte “a” is associated with DQa’s; Byte “b” is associated with DQb's;
Byte “c” is associated with DQc’s; Byte “d” is associated with DQd’s.
Input data must meet setup and hold times around the rising edge
of CLK.
DQc
DQd
11C
1N
–
–
11N
11C
1C
1N
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
1H, 2H, 4D,
4E, 4F, 4G,
4H, 4J, 4K,
4L, 4M, 7N,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
1H, 2H, 4D,
4E, 4F, 4G,
4H, 4J, 4K,
4L, 4M, 7N,
8D, 8E, 8F,
8G, 8H, 8J,
8K, 8L, 8M
VDD
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
VDDQ
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”
parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
Operating Conditions for range.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
4C, 4N, 5C,
4C, 4N, 5C,
5D, 5E 5F,
5D, 5E 5F,
5G, 5H, 5J,
5G, 5H, 5J,
5K, 5L, 5M,
5K, 5L, 5M,
6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,
6G, 6H, 6J,
6G, 6H, 6J,
6K, 6L, 6M,
6K, 6L, 6M,
7C, 7D, 7E,
7C, 7D, 7E,
7F, 7G, 7H,
7F, 7G, 7H,
7J, 7K, 7L,
7J, 7K, 7L,
7M, 8C, 8N
7M, 8C, 8N
VSS
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
NC
–
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
dissipation. Pins 9A, and 9B reserved for address pin
expansion; 8Mb, and 16Mb respectively.
1A, 1B, 1C,
1D, 1E, 1F,
1G, 1P, 2C,
2J, 2K, 2L,
2M, 2N, 2P,
2R, 3H, 4B,
5A, 5N, 6N,
9A, 9B, 9H,
10C, 10D,
10E, 10F,
10G, 10H,
10N, 11B,
11J, 11K,
11L, 11M,
11N, 11P
1A, 1B, 1P,
2C, 2N,
2P, 2R, 3H,
5N, 6N, 9A,
9B, 9H, 10C,
10H, 10N,
11A, 11B,
11P
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
Supply Ground: GND.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)
FUNCTION
R/W#
BWa#
BWb#
READ
H
X
X
WRITE Byte “a”
WRITE Byte “b”
WRITE All Bytes
WRITE ABORT/NOP
L
L
L
L
L
H
L
H
H
L
L
H
NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may
be written.
PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)
FUNCTION
READ
R/W#
H
BWa#
X
BWb#
X
BWc#
X
BWd#
X
WRITE Byte “a”
WRITE Byte “b”
WRITE Byte “c”
WRITE Byte “d”
WRITE All Bytes
L
L
L
L
L
L
H
H
H
L
H
L
H
H
L
H
H
L
H
L
H
H
H
L
L
WRITE ABORT/NOP
L
H
H
H
H
NOTE: Using R/W# and BYTE WRITE(s), any one or more bytes may be written.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
State Diagram for ZBT SRAM
DS
BURST
DS
DS
DESELECT
W
D
TE
RI
A
RE
READ
S
WRITE
BEGIN
READ
READ
D
DS
READ
BURST
BURST
AD
RE
E
RIT
W
BURST
KEY:
BURST
READ
COMMAND
DS
READ
WRITE
BURST
BEGIN
WRITE
WRITE
WRITE
BURST
WRITE
BURST
OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE, or
CONTINUE DESELECT
NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TRUTH TABLE
(Notes 5–10)
OPERATION
DESELECT Cycle
DESELECT Cycle
DESELECT Cycle
CONTINUE DESELECT Cycle
READ Cycle
(Begin Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle
(Begin Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK EDGE
(Stall)
SNOOZE MODE
ADDRESS
USED CE# CE2# CE2 ZZ
None
H
X
X
L
None
X
H
X
L
None
X
X
L
L
None
X
X
X
L
External L
L
H
L
ADV/
LD# R/W# BWx OE# CKE# CLK
DQ
NOTES
L
X
X
X
L
L→H High-Z
L
X
X
X
L
L→H High-Z
L
X
X
X
L
L→H High-Z
H
X
X
X
L
L→H High-Z
1
L
H
X
L
L
L→H
Q
Next
X
X
X
L
H
X
X
L
L
L→H
Q
1, 11
External
L
L
H
L
L
H
X
H
L
L→H High-Z
2
Next
X
X
X
L
H
X
X
H
L
L→H High-Z
External
L
L
H
L
L
L
L
X
L
L→H
D
1, 2,
11
3
Next
X
X
X
L
H
X
L
X
L
L→H
D
None
L
L
H
L
L
L
H
X
L
L→H High-Z
Next
X
X
X
L
H
X
H
X
L
L→H High-Z
Current
X
X
X
L
X
X
X
X
H
L→H
–
None
X
X
X
H
X
X
X
X
X
X
High-Z
1, 3,
11
2, 3
1, 2,
3, 11
4
NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or
WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle
is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A
WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off
the output drivers during a WRITE cycle. Some users may use OE# when the bus turn-on and turn-off times do not meet
their requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it occurs
during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE CLOCK
EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to Byte “a” (DQas); BWb# enables WRITEs to Byte “b” (DQbs); BWc# enables WRITEs to
Byte “c” (DQcs); BWd# enables WRITEs to Byte “d” (DQds).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.
11. The address counter is incremented for all CONTINUE BURST cycles.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Junction temperature depends upon package type,
cycle time, loading, ambient temperature and airflow.
See Micron Technical Note TN-05-14 for more
information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS .................................... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS ........................................ -0.5V to VDD
VIN .................................................. -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ........... -55°C to +150°C
Junction Temperature** ..................................... +150°C
Short Circuit Output Current .............................. 100mA
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = 3.3V ±0.165 unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
CONDITIONS
SYMBOL
VIH
MIN
2.0
MAX
VDD + 0.3
UNITS
V
NOTES
1, 2
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
DQ pins
VIH
VIL
ILI
ILO
2.0
-0.3
-1.0
VDD + 0.3
0.8
1.0
V
V
µA
1, 2
1, 2
3
-1.0
1.0
µA
VOH
VOL
2.4
0.4
V
V
1, 4
1, 4
VDD
VDDQ
3.135
3.135
3.465
VDD
V
V
1
1, 5
Output High Voltage
Output Low Voltage
0V ≤ VIN ≤ VDD
Output(s) disabled,
0V ≤ VIN ≤ VDD
IOH = -4.0mA
IOL = 8.0mA
Supply Voltage
Isolated Output Buffer Supply
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot: VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up:
VIH ≤ +3.465V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O
curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply for 3.3V I/O
operation.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
CONDITIONS
Data bus (DQx)
SYMBOL
VIHQ
MIN
1.7
Inputs
VIH
1.7
VDD + 0.3
V
1, 2
VIL
ILI
ILO
-0.3
-1.0
-1.0
0.7
1.0
1.0
V
µA
µA
1, 2
3
0V ≤ VIN ≤ VDD
Output(s) disabled,
0V ≤ VIN ≤ VDDQ (DQx)
MAX
UNITS
VDDQ + 0.3
V
NOTES
1, 2
Output High Voltage
IOH = -2.0mA
VOH
1.7
–
V
1
Output Low Voltage
IOH = -1.0mA
IOL = 2.0mA
VOH
VOL
2.0
–
–
0.7
V
V
1
1
IOL = 1.0mA
VOL
VDD
VDDQ
–
3.135
0.4
3.6
V
V
1
1
2.375
2.9
V
1
CONDITIONS
TA = 25°C; f = 1 MHz
SYMBOL
CI
TYP
3
MAX
4
UNITS
pF
NOTES
4
VDD = 3.3V
CO
CA
CCK
4
3
3
5
3.5
3.5
pF
pF
pF
4
4
4
Supply Voltage
Isolated Output Buffer Supply
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
Clock Capacitance
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
Address/Control Input Capacitance
Output Capacitance (Q)
TA = 25°C; f = 1 MHz
Clock Capacitance
SYMBOL
TYP
MAX
UNITS
NOTES
CI
2.5
3.5
pF
4
CO
4
5
pF
4
CCK
2.5
3.5
pF
4
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH ≤ +4.6V for t ≤ tKHKH/2 for I ≤ 20mA
Undershoot: VIL ≥ -0.7V for t ≤ tKHKH/2 for I ≤ 20mA
Power-up:
VIH ≤ +3.465V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. This parameter is sampled.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V unless otherwise noted)
MAX
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
Power Supply
Current:
Operating
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ tKC (MIN);
VDD = MAX; Outputs open
IDD
200
500
400
300
mA
2, 3, 4
Power Supply
Current: Idle
Device selected; VDD = MAX;
CKE# ≥ VIH;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
Cycle time ≥ tKC (MIN)
IDD1
10
25
25
20
mA
2, 3, 4
CMOS Standby
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2;
All inputs static; CLK frequency = 0
ISB2
0.5
10
10
10
mA
3, 4
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH;
All inputs static; CLK frequency = 0
ISB3
6
25
25
25
mA
3, 4
Device deselected; VDD = MAX;
ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2
or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN)
ISB4
45
120
75
60
mA
3, 4
ZZ ≥ VIH
ISB2Z
0.5
10
10
10
mA
4
TTL Standby
Clock Running
SNOOZE MODE
UNITS NOTES
NOTE: 1. VDDQ = +3.3V ±0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O
configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device
is active (not in deselected mode).
4. Typical values are measured at 3.3V, 25°C and 10ns cycle time.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
46
°C/W
1
θJC
2.8
°C/W
1
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1, 2
θJC
9
°C/W
1, 2
θJB
17
°C/W
1, 2
FBGA THERMAL RESISTANCE
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s)
Junction to Case (Top)
Junction to Pins
(Bottom)
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
AC ELECTRICAL CHARACTERISTICS
(Notes 6, 8, 9) (0°C ≤ TA ≤ +70°C; VDD = +3.3V ±0.165V; ZBT mode)
-6
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Clock enable (CKE#)
Control signals
Data-in
Hold Times
Address
Clock enable (CKE#)
Control signals
Data-in
SYMBOL
MIN
tKHKH
6.0
fKF
tKHKL
tKLKH
tKHQX1
tKHQZ
0
tGHQZ
tAVKH
tEVKH
tCVKH
tDVKH
tKHAX
tKHEX
tKHCX
tKHDX
100
3.2
3.2
4.2
1.5
1.5
1.5
3.5
4.2
0
3.5
MAX
10
2.0
2.0
3.5
3.5
MIN
133
3.5
1.5
1.5
1.5
-10
MAX
7.5
1.7
1.7
tGLQV
tGLQX
MIN
166
tKHQV
tKHQX
-7.5
MAX
5.0
1.5
1.5
1.5
3.5
5.0
0
4.2
5.0
UNITS
NOTES
ns
MHz
ns
ns
1
1
ns
ns
ns
ns
ns
ns
ns
2
2, 3, 4, 5
2, 3, 4, 5
6
2, 3, 4, 5
2, 3, 4, 5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
ns
ns
ns
ns
7
7
7
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
7
7
7
7
NOTE: 1.
2.
3.
4.
5.
6.
7.
This parameter is sampled.
Measured as HIGH above VIH and LOW below VIL.
Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.
This parameter is sampled.
This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
Transition is measured ±200mV from steady state voltage.
OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for
turnaround timing.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when they are being registered into the device. All other synchronous inputs must meet the setup and hold times with
stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising
edge of CLK when ADV/LD# is LOW to remain enabled.
9. Test conditions as specified with output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V ±0.165V) and Figure 3 for
2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).
10. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is
defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
3.3V I/O AC TEST CONDITIONS
2.5V I/O AC TEST CONDITIONS
Input pulse levels ................................... VSS to 3.3V
Input pulse levels ................................... VSS to 2.5V
Input rise and fall times ..................................... 1ns
Input rise and fall times ..................................... 1ns
Input timing reference levels .......................... 1.5V
Input timing reference levels ........................ 1.25V
Output reference levels ................................... 1.5V
Output reference levels ................................. 1.25V
Output load ............................. See Figures 1 and 2
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
Q
Q
Z O= 50Ω
Z O= 50Ω
50Ω
50Ω
VT = 1.25V
VT = 1.5V
Figure 1
Figure 3
+3.3V
+2.5V
225Ω
317
Q
Q
5pF
351
5pF
225Ω
Figure 2
Figure 4
LOAD DERATING CURVES
The Micron 256K x 18, 128K x 32, and 128K x 36 ZBT
SRAM timing is dependent upon the capacitive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time the ZZ pin is in a HIGH
state. After the device enters SNOOZE MODE, all inputs except ZZ become disabled and all outputs go to
High-Z.
The ZZ pin is an asynchronous, active HIGH input
that causes the device to enter SNOOZE MODE. When
the ZZ pin becomes a logic HIGH, ISB2Z is guaranteed
after the time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE
is not guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tRZZ, only a DESELECT or
READ cycle should be given.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MAX
UNITS
Current during SNOOZE MODE
ZZ ≥ VIH
ISB2Z
10
mA
Current during SNOOZE MODE
(P Version)
ZZ ≥ VIH
ISB2ZP
1
mA
0
2(tKHKH)
ns
1
0
2(tKHKH)
ns
1
2(tKHKH)
ns
1
ns
1
tZZ
ZZ active to input ignored
ZZ inactive to input sampled
tRZZ
ZZ active to snooze current
tZZI
tRZZI
ZZ inactive to exit snooze current
MIN
0
NOTES
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t ZZ
ZZ
I
t
t RZZ
ZZI
SUPPLY
I ISB2Z
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
READ/WRITE TIMING
1
2
3
t KHKH
4
5
6
A3
A4
7
8
9
10
A5
A6
A7
CLK
tEVKH tKHEX
tKHKL tKLKH
CKE#
tCVKH
tKHCX
CE#
ADV/LD#
R/W#
BWx#
A1
ADDRESS
A2
tKHQV
tDVKH
tAVKH tKHAX
DQ
tKHDX
D(A1)
tKHQX
tKHQX1
D(A2)
Q(A3)
D(A2+1)
tGLQV
tKHQZ
Q(A4+1)
Q(A4)
D(A5)
Q(A6)
tGHQZ
tKHQX
tGLQX
OE#
COMMAND
WRITE
D(A1)
WRITE
D(A2)
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
WRITE
D(A5)
READ
Q(A6)
WRITE
D(A7)
DON’T CARE
DESELECT
UNDEFINED
READ/WRITE TIMING PARAMETERS
-6
SYM
tKHKH
fKF
MIN
6.0
tKHKL
1.7
1.7
tKLKH
tKHQX1
tKHQZ
1.5
tGLQV
NOTE: 1.
2.
3.
4.
0
-10
MAX
100
4.2
1.5
0
-6
MAX
3.2
3.2
1.5
1.5
3.5
3.5
MIN
10
133
2.0
2.0
3.5
1.5
1.5
tGLQX
MIN
7.5
166
tKHQV
tKHQX
-7.5
MAX
5.0
1.5
1.5
3.5
4.2
1.5
0
3.5
5.0
-7.5
MIN
MAX
4.2
1.7
-10
UNITS
ns
MHz
SYM
tGHQZ
tAVKH
MIN
2.0
UNITS
ns
ns
ns
ns
tEVKH
1.5
1.5
1.7
1.7
2.0
2.0
ns
ns
ns
ns
ns
tDVKH
1.5
0.5
0.5
1.7
0.5
0.5
2.0
0.5
0.5
ns
ns
ns
ns
ns
tKHCX
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
tCVKH
tKHAX
tKHEX
tKHDX
1.5
MAX
3.5
MIN
MAX
5.0
ns
For this waveform, ZZ is tied LOW.
Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
NOP, STALL, AND DESELECT CYCLES
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CKE#
CE#
ADV/LD#
R/W#
BWx#
ADDRESS
A5
tKHQZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tKHQX
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DON’T CARE
DESELECT
CONTINUE
DESELECT
UNDEFINED
NOP, STALL, AND DESELECT TIMING PARAMETERS
-6
SYM
tKHQX
tKHQZ
MIN
1.5
1.5
MAX
3.5
-7.5
MIN
MAX
1.5
1.5
3.5
-10
MIN
1.5
1.5
MAX
3.5
UNITS
ns
ns
NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For this waveform, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
+0.10
-0.20
20.10 ±0.10
22.10
0.65 TYP
0.32
+0.06
-0.10
0.625
SEE DETAIL A
14.00 ±0.10
16.00 ±0.20
PIN #1 ID
0.15
+0.03
-0.02
1.40 ±0.05
GAGE PLANE
1.60 MAX
0.10
0.10
+0.10
-0.05
0.60 ±0.15
1.00 TYP
0.25
DETAIL A
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
165-PIN FBGA
0.85 ±0.075
0.12 C
SEATING PLANE
C
BALL A11
165X Ø 0.45
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
10.00
BALL A1
PIN A1 ID
1.00
TYP
1.20 MAX
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
6.50 ±0.05
SUBSTRATE: PLASTIC LAMINATE
5.00 ±0.05
SOLDER BALL MATERIAL:
EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
DATA SHEET DESIGNATIONS
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron, the Micron logo, and M logo are trademarks and/or service marks of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc., and Motorola, Inc.
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED ZBT SRAM
REVISION HISTORY
Updated package drawings ................................................................................................................................... January 9/03
Removed “Preliminary Package Data” from front page .............................................................................. February 22/02
Removed 119-pin PBGA package and references ........................................................................................ February 14/02
Removed note “Not Recommended for New Designs,” Rev. 6/01 ...................................................................... June 7/01
Added Industrial Temperature note and references, Rev. 3/01, FINAL ......................................................... March 6/01
Added 119-pin PBGA package, Rev. 1/01, FINAL ........................................................................................... January 10/01
Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .............................................................................. August 22/00
Changed FBGA capacitance values, REV 8/00, FINAL ....................................................................................... August 7/00
CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF
CO; TYP 4pF from 6pF; MAX. 5pF from 7pF
CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF
Added FBGA Part Marking Guide, Rev. 7/00, Preliminary ................................................................................... July 13/00
Removed 119-pin PBGA package and references
Added 165-pin FBGA package, Rev. 6/00, Preliminary ........................................................................................ May 23/00
Removed all “Smart ZBT” references
4Mb: 256K x 18, 128K x 32/36 Pipelined ZBT SRAM
MT55L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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