18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
18Mb ZBT® SRAM
MT55L1MY18P, MT55V1MV18P,
MT55L512Y32P, MT55V512V32P,
MT55L512Y36P, MT55V512V36P
3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O
Features
Figure 1: 100-Pin TQFP
• High frequency and 100 percent bus utilization
• Single 3.3V ±5 percent or 2.5V ±5 percent power supply
• Separate 3.3V ±5 percent or 2.5V ±5 percent isolated
output buffer supply (VDDQ)
• Advanced control logic for minimum control signal
interface
• Individual byte write controls may be tied LOW
• Single R/W# (read/write) control pin/ball
• CKE# pin/ball to enable clock and suspend operations
• Three chip enables for simple depth expansion
• Clock-controlled and registered addresses, data
I/Os, and control signals
• Internally self-timed, fully coherent WRITE
• Internally self-timed, registered outputs to eliminate
the need to control OE#
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Linear or Interleaved Burst Modes
• Burst feature (optional)
• Pin and ball/function compatibility with 2Mb, 4Mb,
and 8Mb ZBT SRAM
JEDEC-Standard MS-026 BHA (LQFP)
Figure 2: 165-Ball FBGA
JEDEC-Standard MS-216 (Var. CAB-1)
TQFP
Marking
Options
• Timing (Access/Cycle/MHz)
3.2ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.2ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V VDD, 3.3V, or 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
2.5V VDD, 2.5V I/O
1 Meg x 18
512K x 32
512K x 36
• Packages
100-pin TQFP
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0ºC £ TA £ +70ºC)
Industrial (-40ºC £ TA £ +85ºC)
-5
-6
-7.5
-10
MT55L1MY18P
MT55L512Y32P
MT55L512Y36P
Part Number Example:
MT55L512Y36PT-10
MT55V1MV18P
MT55V512V32P
MT55V512V36P
General Description
The Micron® Zero Bus Turnaround™ (ZBT®) SRAM
family employs high-speed, low-power CMOS designs
using an advanced CMOS process.
Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,
512K x 32, or 512K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables
T
F1
None
IT2
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide.
2. Contact Factory for availability of Industrial Temperature
devices.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
1
©2003 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc# and BWd#), and
read/write (R/W#).
Asynchronous inputs include the output enable
(OE#, which may be tied LOW for control signal minimization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin/ball (MODE) that selects between interleaved and
linear burst modes. MODE may be tied HIGH, LOW or
left unconnected if burst is unused. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to four
bytes wide as controlled by the write control inputs.
All READ, WRITE, and DESELECT cycles are initiated by the ADV/LD# input. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin/ball (ADV/LD#). Use of burst
mode is optional. It is allowable to give an address for
each individual READ and WRITE cycle. BURST cycles
wrap around after the fourth access from a base
address.
To allow for continuous, 100 percent use of the data
bus, the pipelined ZBT SRAM uses a late LATE WRITE
cycle. For example, if a WRITE cycle begins in clock
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The data associated with the address is
required two cycles later, or on the rising edge of clock
cycle three.
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed write
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# controls DQa pins/balls; BWb# controls DQb pins/balls;
BWc# controls DQc pins/balls; and BWd# controls
DQd pins/balls. Cycle types can only be defined when
an address is loaded, i.e., when ADV/LD# is LOW. Parity/ECC bits are only available on the x18 and x36 versions.
The device is ideally suited for systems requiring
high bandwidth and zero bus turnaround delays.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
Dual Voltage I/O
The 3.3V VDD device is tested for 3.3V and 2.5V I/O
function. The 2.5V VDD device is tested for only 2.5V
I/O function.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 3: Functional Block Diagram
1 Meg x 18
20
20
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
MODE
ADV/LD#
K
K
CLK
CKE#
18
20
ADDRESS
REGISTER 0
SA0, SA1, SA
WRITE ADDRESS
REGISTER 1
20
WRITE ADDRESS
REGISTER 2
20
ADV/LD#
1 Meg x 9 x 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
BWa#
WRITE
DRIVERS
18
18
BWb#
MEMORY
ARRAY
O
U
T
P
U
T
S
E
N
S
E
18
A
M
P
S
R
E
G
I
S
T
E
R
S
18
R/W#
O
U
T
P
U
T
D
A
T
A
18
S
T
E
E
R
I
N
G
18
E
B
U
F
F
E
R
S
18
DQs
DQPa
DQPb
E
18
INPUT
REGISTER 1 E
OE#
CE#
CE2
CE2#
INPUT
REGISTER 0 E
READ LOGIC
Figure 4: Functional Block Diagram
512K x 32/36
19
SA0, SA1, SA
19
SA1
SA1'
D1
Q1
SA0
SA0'
BURST
D0
Q0
LOGIC
MODE
CLK
CKE#
17
19
ADDRESS
REGISTER 0
ADV/LD#
K
K
WRITE ADDRESS
REGISTER 1
19
WRITE ADDRESS
REGISTER 2
19
ADV/LD#
BWa#
BWb#
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
512K x 8 x 4
(x32)
36
WRITE
DRIVERS
BWc#
36 512K x 9 x 4 36
(x36)
MEMORY
ARRAY
BWd#
R/W#
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
36
R
E
G
I
S
T
E
R
S
O
U
T
P
U
T
D
A
T
A
36
S
T
E
E
R
I
N
G
36
E
36
OE#
CE#
CE2
CE2#
E
INPUT
REGISTER 1
B
U
F
F
E
R
S
36
DQs
DQPa
DQPb
DQPc
DQPd
E
E
INPUT
REGISTER 0
READ LOGIC
NOTE:
1. Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and timing diagrams for detailed information.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
SA
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
VDD2
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
Figure 5: Pin Layout (Top View)
100-Pin TQFP
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
SA
SA
SA
SA
SA
DNU3
DNU3
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
x18
NF/DQPb1
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
VDD2
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NF/DQPa1
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD2
VDD
VDD2
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
x32/x36
SA
SA
SA
SA
SA
SA
SA
DNU3
DNU3
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
(LBO#)
NF/DQPc1
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VDD2
VDD
VDD2
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NF/DQPd1
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Pins 14, 16, and 66 do not have to be connected directly to VDD if the input voltage is ³ VIH.
3. Pins 43 and 42 are reserved for address expansion; 36Mb and 72Mb, respectively.
.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 1:
TQFP Pin Descriptions
SYMBOL
TYPE
DESCRIPTION
ADV/LD#
Input
BWa#
BWb#
BWc#
BWd#
Input
CE#
Input
CE2#
Input
CE2
Input
CKE#
Input
CLK
Input
MODE (LBO#)
Input
OE# (G#)
Input
R/W#
Input
SA0
SA1
SA
ZZ
Input
Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the
device. When CKE# is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup and hold times around the rising
edge of CLK.
Clock: This signal registers the address, data, chip enables, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or
HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.
LBO# is the JEDEC-standard term for MODE.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#
is the JEDEC-standard term for OE#.
Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times around the rising edge of CLK. Full buswidth WRITEs occur if all byte write enables are LOW.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of
the address field and set the internal burst counter if burst is desired.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.
SRAM Data I/Os: Byte “a” associated with is DQa pins; byte “b” is associated with DQb pins;
byte “c” is associated with DQc pins; byte “d” is associated withDQd pins. Input data must
meet setup and hold times around the rising edge of CLK.
Input
DQa
DQb
DQc
DQd
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
VDD
VDDQ
Input/
Output
VSS
Supply
NF
I/O
No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
Supply
Supply
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
Ground: GND.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 1:
TQFP Pin Descriptions (continued)
SYMBOL
TYPE
DNU
–
NC
–
NF
–
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
DESCRIPTION
Do Not Use: These pins are internally connected to the die. They may be left floating or
connected to ground to improve package heat dissipation.
No Connect: These pins are not internally connected to the die. They may be left floating,
driven by signals, or connected to ground to improve package heat dissipation.
No Function: These pins are internally connected to the die and have the capacitance of an
input pin. They may be left floating, driven by signals, or connected to ground to improve
package heat dissipation.
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 6: Ball Layout (Top View)
165-Ball FBGA
x18
x32/x36
10
11
CKE# ADV/L D# SA
SA
SA
R/W# OE# (G#)
SA
SA
NC
VSS
VDDQ
NC
DQPa
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQPb
NC
VDDQ
VSS
NC
NF
VDD
VSS
VDDQ
NC
NC
NC
NC2
SA
SA
TDI
SA1
TDO
SA
SA
SA
NF
MODE
(LBO#)
NC2
SA
SA
TMS
SA0
TCK
SA
SA
SA
SA
1
2
3
4
5
6
NC
SA
CE#
BWb#
NC
CE2#
NC
SA
CE2
NC
BWa#
CLK
NC
NC
VDDQ
VSS
VSS
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
NC
DQb
VDDQ
VDD
NC
DQb
VDDQ
VDD
VDD
DQb
7
8
9
A
VDD
VDDQ
DQb
DQb
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
NF/DQPd1
NC
VDDQ
VSS
NC
NF
VDD
VSS
VDDQ
NC
NF/DQPa1
NC
NC2
SA
SA
TDI
SA1
TDO
SA
SA
SA
NF
MODE
(LBO#)
NC2
SA
SA
TMS
SA0
TCK
SA
SA
SA
SA
NC
VDDQ
VSS
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
DQc
DQc
VDDQ
VDD
DQc
DQc
VDDQ
VDD
VDD
DQd
C
D
E
F
G
H
J
K
L
M
N
P
P
R
VSS
NF/DQPc1
B
N
N
P
NF/DQPb1
CLK
M
M
N
NC
BWd# BWa#
L
L
M
VDDQ
CE2
K
K
L
VSS
SA
A
J
J
K
NC
NC
9
H
H
J
SA
CE2#
8
G
G
H
SA
BWc# BWb#
7
F
F
G
R/W# OE# (G#)
CE#
6
E
E
F
NC
SA
5
D
D
E
SA
NC
4
C
C
D
CKE# ADV/LD# SA
3
B
B
C
11
2
A
A
B
10
1
P
R
R
R
TOP VIEW
TOP VIEW
NOTE:
1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Balls 2R and 2P are reserved for address expansion; 36Mb and 72Mb, respectively.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 2:
FBGA Ball Descriptions
SYMBOL
TYPE
DESCRIPTION
ADV/LD#
Input
BWa#
BWb#
BWc#
BWd#
Input
CE#
Input
CE2#
Input
CE2
Input
CKE#
Input
CLK
Input
MODE (LBO#)
Input
OE# (G#)
Input
R/W#
Input
SA0
SA1
SA
TMS
TDI
TCK
ZZ
Input
Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa balls; BWb#
controls DQb balls; BWc# controls DQc balls; BWd# controls DQd balls.
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).
Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.
Synchronous Clock Enable: This active LOW input permits CLK to propogate throughout the
device. When CKE# is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet the setup and hold times around the
rising edge of CLK.
Clock: This signal registers the address, data, chip enables, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Mode: This input selects the burst sequence. A LOW on this input selects “linear burst.” NC or
HIGH on this input selects “interleaved burst.” Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#
is the JEDEC-standard term for OE#.
Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this ball permits BYTE WRITE
operations to meet the setup and hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of
the address field and set the internal burst counter if burst is desired.
IEEE 1149.1 Test Inputs: JEDEC-standard 3.3V and 2.5V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.
DQa
DQb
DQc
DQd
Input
Input
Input/
Output
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This ball has an internal pull-down and can be left unconnected.
SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa balls; byte “b” is
associated with DQb balls. For the x32 and x36 versions, byte “a” is associated with DQa
balls; byte “b” is associated with DQb balls; byte “c” is associated with DQc balls; byte “d” is
associated with DQd balls. Input data must meet setup and hold times around the rising
edge of CLK.
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 2:
FBGA Ball Descriptions (continued)
SYMBOL
TYPE
DESCRIPTION
NF/DQPa
NF/DQPb
NF/DQPc
NF/DQPd
TDO
VDD
VDDQ
NF
I/O
No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity
is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.
Output
Supply
Supply
VSS
NC
Supply
–
NF
–
IEEE 1149.1 Test Output: JEDEC-standard 3.3V and 2.5V I/O levels.
Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.
Ground: GND.
No Connect: These balls are not internally connected to the die. They may be left floating,
driven by signals, or connected to ground to improve package heat dissipation.
No Function: These balls are internally connected to the die and have the capacitance of an
input ball. They may be left floating, driven by signals, or connected to ground to improve
package heat dissipation.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 3:
Interleaved Burst Address Table (Mode = NC or HIGH)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
Table 4:
Linear Burst Address Table (Mode = LOW)
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
Table 5:
Partial Truth Table For READ/WRITE Commands (x18)
FUNCTION
READ
WRITE Byte “a”
WRITE Byte “b”
WRITE All Byte
WRITE ABORT/NOP
R/W#
BWa#
BWb#
H
L
L
L
L
X
L
H
L
H
X
H
L
L
H
NOTE:
Using R/W# and byte write(s), any one or more bytes may be written.
Table 6:
Partial Truth Table For READ/WRITE Commands (x32/x36)
FUNCTION
R/W#
BWa#
BWb#
BWc#
BWd#
READ
WRITE Byte “a”
WRITE Byte “b”
WRITE Byte “c”
WRITE Byte “d”
WRITE All Byte
WRITE ABORT/NOP
H
L
L
L
L
L
L
X
L
H
H
H
L
H
X
H
L
H
H
L
H
X
H
H
L
H
L
H
X
H
H
H
L
L
H
NOTE:
Using R/W# and byte write(s), any one or more bytes may be written.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 7:
State Diagram For ZBT SRAM
DS
BURST
DS
DS
DESELECT
W
D
TE
RI
A
RE
READ
S
WRITE
BEGIN
READ
READ
D
DS
READ
BURST
BURST
AD
RE
E
RIT
W
BURST
KEY:
BURST
READ
COMMAND
DS
READ
WRITE
BURST
BEGIN
WRITE
WRITE
WRITE
BURST
WRITE
BURST
OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE, or
CONTINUE DESELECT
NOTE:
1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the
clock (CLK) input and does not change the state of the device.
2. States change on the rising edge of the clock (CLK).
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 7:
Truth Table
Notes: 5–10
OPERATION
DESELECT CYCLE
DESELECT Cycle
DESELECT Cycle
CONTINUE
DESELECT Cycle
READ Cycle (Begin
Burst)
READ Cycle
(Continue Burst)
NOP/DUMMY READ
(Begin Burst)
DUMMY READ
(Continue Burst)
WRITE Cycle (Begin
Burst)
WRITE Cycle
(Continue Burst)
NOP/WRITE ABORT
(Begin Burst)
WRITE ABORT
(Continue Burst)
IGNORE CLOCK
EDGE (Stall)
SNOOZE MODE
ADDRESS
USED
CE#
CE2#
CE2
ZZ
ADV/
LD# R/W# BWx
None
None
None
None
H
X
X
X
X
H
X
X
X
X
L
X
L
L
L
L
L
L
L
H
X
X
X
X
External
L
L
H
L
L
Next
X
X
X
L
External
L
L
H
Next
X
X
External
L
Next
OE#
CKE#
CLK
DQ
NOTES
X
X
X
X
X
X
X
X
L
L
L
L
L®H
L®H
L®H
L®H
High-Z
High-Z
High-Z
High-Z
1
H
X
L
L
L®H
Q
H
X
X
L
L
L®H
Q
1, 11
L
L
H
X
H
L
L®H
High-Z
2
X
L
H
X
X
H
L
L®H
High-Z 1, 2, 11
L
H
L
L
L
L
X
L
L®H
D
3
X
X
X
L
H
X
L
X
L
L®H
D
1, 3, 11
None
L
L
H
L
L
L
H
X
L
L®H
High-Z
2, 3
Next
X
X
X
L
H
X
H
X
L
L®H
High-Z
Current
X
X
X
L
X
X
X
X
H
L®H
–
1, 2, 3,
11
4
None
X
X
X
H
X
X
X
X
X
X
High-Z
NOTE:
1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ
or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT
cycle is executed first.
2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation. A WRITE ABORT means a WRITE command is given, but no operation is performed.
3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn
off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet
an application’s requirements.
4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it
occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the
IGNORE CLOCK EDGE cycle.
5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,
BWc#, and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.
6. BWa# enables WRITEs to byte “a” (DQa pins/balls); BWb# enables WRITEs to byte “b” (DQb pins/balls); BWc#
enables WRITEs to byte “c” (DQc pins/balls); BWd# enables WRITEs to byte “d” (DQd pins/balls).
7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.
10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
11. The address counter is incremented for all CONTINUE BURST cycles.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Absolute Maximum Ratings
3.3V VDD
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Junction temperature depends upon package type,
cycle time, loading, ambient temperature, and airflow.
Voltage on VDD Supply
Relative to VSS .................................. -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .................................... -0.5V to VDD
VIN (Inputs) ............................. -0.5V to VDD + 0.5V
VIN (DQs) .............................. -0.5V to VDDQ + 0.5V
Storage Temperature (TQFP).................-55ºC to +150ºC
Storage Temperature (FBGA).................-55ºC to +125ºC
Junction Temperature .......................................... +150ºC
Short Circuit Output Current ...............................100mA
2.5V VDD
Voltage on VDD Supply
Relative to VSS .................................. -0.3V to +3.6V
Voltage on VDDQ Supply Relative
to VSS ................................................ -0.3V to +3.6V
VIN (Inputs) ............................. -0.3V to VDD + 0.3V
VIN (DQs) .............................. -0.3V to VDDQ + 0.3V
Storage Temperature (TQFP).................-55ºC to +150ºC
Storage Temperature (FBGA).................-55ºC to +125ºC
Junction Temperature .......................................... +150ºC
Short Circuit Output Current ...............................100mA
Table 8:
3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; VDD and VDDQ = 3.3V ±0.165V unless otherwise
noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
CONDITIONS
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDD
IOH = -4.0mA
IOL = 8.0mA
13
SYMBOL
MIN
MAX
UNITS
NOTES
VIH
VIL
ILI
ILO
2.0
-0.3
-1.0
-1.0
VDD + 0.3
0.8
1.0
1.0
V
V
µA
µA
1, 2
1, 2
4
VOH
VOL
VDD
VDDQ
2.4
0.4
3.465
VDD
V
V
V
V
1
1
1
1, 5
3.135
3.135
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 9:
3.3V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V and VDDQ = 2.5V ±0.125V unless
otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Data bus (DQx)
Inputs
VIHQ
VIH
VIL
ILI
ILO
1.7
1.7
-0.3
-1.0
-1.0
VDDQ + 0.3
VDD + 0.3
0.7
1.0
1.0
V
V
V
µA
µA
1, 2
1, 2
1, 2
4
VOH
VOH
VOL
VOL
VDD
VDDQ
1.7
2.0
–
–
3.135
2.375
–
–
0.7
0.4
3.465
2.625
V
V
V
V
V
V
1
1
1
1
1
1, 5
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDDQ
(DQX)
IOH = -2.0mA
IOH = -1.0mA
IOL = 2.0mA
IOL = 1.0mA
Supply Voltage
Isolated Output Buffer Supply
Table 10: 2.5V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; VDD and VDDQ = 2.5V ±0.125V unless otherwise
noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Data bus (DQx)
Inputs
VIHQ
VIH
VIL
ILI
ILO
1.7
1.7
-0.3
-1.0
-1.0
VDDQ + 0.3
VDD + 0.3
0.7
1.0
1.0
V
V
V
µA
µA
1, 3
1, 3
1, 3
4
VOH
VOH
VOL
VOL
VDD
VDDQ
1.7
2.0
–
–
2.375
2.375
–
–
0.7
0.4
2.625
2.625
V
V
V
V
V
V
1
1
1
1
1
1, 5
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDDQ
(DQX)
IOH = -2.0mA
IOH = -1.0mA
IOL = 2.0mA
IOL = 1.0mA
Supply Voltage
Isolated Output Buffer Supply
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 11: TQFP Capacitance
Note 10; notes appear following parameter tables on page 18
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Input Capacitance
Clock Capacitance
CONDITIONS
SYMBOL
TYP
MAX
UNITS
TA = 25°C; f = 1 MHz
VDD = 3.3V
CI
CO
CA
CCK
4.2
3.5
4
4.2
5
4
5
5
pF
pF
pF
pF
CONDITIONS
SYMBOL
TYP
MAX
UNITS
TA = 25°C; f = 1 MHz
VDD = 3.3V
CI
CO
CA
CCK
4
4
4
5
5
4.5
5
5.5
pF
pF
pF
pF
Table 12: FBGA Capacitance
Note 10; notes appear following parameter tables on page 18
DESCRIPTION
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Input Capacitance
Clock Capacitance
Table 13: TQFP Thermal Resistance
Note 10; notes appear following parameter tables on page 18
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s, two-layer
board)
Thermal Resistance
Junction to Case (Top)
CONDITIONS
SYMBOL
TYP
UNITS
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
qJA
28.9
°C/W
qJC
4.2
°C/W
SYMBOL
TYP
UNITS
qJA
32
°C/W
qJC
1.7
°C/W
qJB
10.4
°C/W
Table 14: FBGA Thermal Resistance
Note 10; notes appear following parameter tables on page 18
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s, two-layer
board)
Junction to Case (Top)
CONDITIONS
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
Junction to Board (Bottom)
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 15: 3.3V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 32/36)
Notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; VDD and VDDQ = 3.3V ±0.165V or 2.5V ±0.125V
unless otherwise noted
MAX
DESCRIPTION
CONDITIONS
Power Supply
Current:
Operating
Device selected; All inputs £ VIL
or ³ VIH; Cycle time ³ tKC (MIN);
VDD = MAX; Outputs open
Device selected; VDD = MAX;
CKE# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³ tKC (MIN)
Device deselected; VDD = MAX;
All inputs £ VSS + 0.2 or ³ VDD - 0.2;
All inputs static; CLK frequency = 0
Device deselected; VDD = MAX;
ADV/LD# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³ tKC (MIN)
ZZ ³ VIH
Power Supply
Current: Idle
CMOS Standby
Clock Running
Snooze Mode
SYM
TYP
-5
-6
-7.5
-10
UNITS NOTES
IDD
300
420
380
340
300
mA
6, 7, 8
IDD1
120
180
170
160
150
mA
6, 7, 8
ISB2
8
30
30
30
30
mA
7, 8
ISB4
120
180
170
160
150
mA
7, 8
ISB2Z
8
30
30
30
30
mA
8
Table 16: 2.5V VDD, IDD Operating Conditions and Maximum Limits
(1 Meg x 18 and 512K x 32/36)
Notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; VDD and VDDQ = 2.5V ±0.125V unless otherwise
noted
MAX
DESCRIPTION
CONDITIONS
Power Supply
Current:
Operating
Device selected; All inputs £ VIL
or ³ VIH; Cycle time ³ tKC (MIN);
VDD = MAX; Outputs open
Device selected; VDD = MAX;
CKE# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³ tKC (MIN)
Device deselected; VDD = MAX;
All inputs £ VSS + 0.2 or ³ VDD - 0.2;
All inputs static; CLK frequency = 0
Device deselected; VDD = MAX;
ADV/LD# ³ VIH; All inputs £ VSS + 0.2
or ³ VDD - 0.2; Cycle time ³ tKC (MIN)
ZZ ³ VIH
Power Supply
Current: Idle
CMOS Standby
Clock Running
Snooze Mode
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
SYM
TYP
-5
-6
-7.5
-10
IDD
250
370
330
290
250
mA
6, 7, 9
IDD1
100
170
150
130
120
mA
6, 7, 9
ISB2
8
30
30
30
30
mA
7, 9
ISB4
100
170
150
130
120
mA
7, 9
ISB2Z
8
30
30
30
30
mA
9
16
UNITS NOTES
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 17: AC Electrical Characteristics and Recommended Operating Conditions
Notes 11-13 ; notes appear following parameter tables on page 18; 0ºC £ TA £ +70ºC; TJ £ 95ºC (commercial); TJ £ 110ºC
(industrial); VDD = 3.3V ±0.165V unless otherwise noted
-5
DESCRIPTION
Clock
Clock cycle time
SYMBOL
t
KHKH
Clock frequency
MIN
-6
MAX
5.0
MIN
KF
MAX
6.0
200
f
-7.5
MIN
-10
MAX
7.5
166
MIN
MAX UNITS
10.0
133
NOTES
ns
100
MHz
Clock HIGH time
t
2.0
2.2
3.0
3.2
ns
14
Clock LOW time
t
2.0
2.2
3.0
3.2
ns
14
Output Times
Clock to output valid
t
Clock to output invalid
t
Clock to output in Low-Z
KHKL
KLKH
3.2
KHQV
3.5
4.2
5.0
ns
KHQX
1.0
1.5
1.5
1.5
ns
15
KHQX1
1.0
1.5
1.5
1.5
ns
10, 15, 16
t
Clock to output in High-Z
t
OE# to output valid
t
OE# to output in
Low-Z
OE# to output in
High-Z
Setup Times
Address
t
KHQZ
GLQV
GLQX
3.5
3.5
ns
10, 15, 16
3.0
3.5
4.2
5.0
ns
11
ns
10, 15, 16
ns
10, 15, 16
0
3.2
GHQZ
AVKH
3.5
0
t
t
3.0
0
3.5
0
3.5
5.0
1.4
1.5
1.5
2.0
ns
17
1.4
1.5
1.5
2.0
ns
17
Clock enable (CKE#)
t
Control signals
t
CVKH
1.4
1.5
1.5
2.0
ns
17
Data-in
t
DVKH
1.4
1.5
1.5
2.0
ns
17
Hold Times
Address
t
KHAX
0.4
0.5
0.5
0.5
ns
17
Clock enable (CKE#)
t
KHEX
0.4
0.5
0.5
0.5
ns
17
Control signals
t
KHCX
0.4
0.5
0.5
0.5
ns
17
Data-in
t
KHDX
0.4
0.5
0.5
0.5
ns
17
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
EVKH
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Notes
1. All voltages referenced to VSS (GND).
2. For 3.3V VDD:
Overshoot:
VIH £ +4.6V for t £ tKHKH/2 for
I £ 20mA
Undershoot: VIL ³ -0.7V for t £ tKHKH/2 for
I £ 20mA
Power-up: VIH £ +3.6V and VDD £ 3.135V for
t £ 200ms
3. For 2.5V VDD:
Overshoot: VIH £ +3.6V for t £ tKHKH/2 for
I £ 20mA
Undershoot: VIL ³ -0.5V for t £ tKHKH/2 for
I £ 20mA
Power-up:
VIH £ +2.65V and VDD £ 2.375V for
t £ 200ms
4. The MODE and ZZ pins/balls have an internal
pull-up/pull-down and input leakage = ±10µA.
5. VDDQ should never exceed VDD. VDD and VDDQ
can be externally wired together to the same
power supply.
6. IDD is specified with no output current and
increases with faster cycle times. IDDQ increases
with faster cycle times and greater output loading.
7. “Device deselected” means device is in powerdown mode as defined in the truth table. “Device
selected” means device is active (not in powerdown mode).
8. Typical values are measured at 3.3V, 25ºC, and
10ns cycle time.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
9. Typical values are measured at 2.5V, 25ºC, and
10ns cycle time.
10. This parameter is sampled.
11. OE# can be considered a “Don’t Care” during
WRITEs; however, controlling OE# can help finetune a system for turnaround timing.
12. Test conditions as specified with the output loading shown in Figures 11 and 12 for 3.3V I/O and
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.
13. A WRITE cycle is defined by R/W# LOW, having
been registered into the device at ADV/LD# LOW.
A READ cycle is defined by R/W# HIGH with ADV/
LD# LOW. Both cases must meet setup and hold
times.
14. Measured as HIGH above VIH and LOW below VIL.
15. Refer to Technical Note TN-55-01, “Designing
with ZBT SRAMs,” for a more thorough discussion
of these parameters.
16. This parameter is measure with the output loading shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.
17. This is a synchronous device. All addresses must
meet the specified setup and hold times with stable logic levels for all rising edges of CLK when the
chip is enabled. To remain enabled, chip enable
must be valid at each rising edge of CLK when
ADV/LD# is LOW.
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 8:
READ/WRITE Timing
1
2
tKHKH
3
4
5
6
7
8
9
A5
A6
A7
10
CLK
tEVKH
tKHEX
tCVKH
tKHCX
tKHKL tKLKH
CKE#
CE#
ADV/LD#
R/W#
BWx#
ADDRESS
A1
A2
A3
A4
tKHQV
tAVKH tKHAX
tKHQX
tKHQX1
DQ
D(A1)
D(A2)
D(A2+1)
Q(A3)
tGLQV
Q(A4)
Q(A4+1)
tGLQX
OE#
WRITE
D(A1)
WRITE
D(A2)
D(A5)
Q(A6)
D(A7)
WRITE
D(A7)
DESELECT
tGHQZ
tDVKH tKHDX
COMMAND
tKHQZ
BURST
WRITE
D(A2+1)
READ
Q(A3)
READ
Q(A4)
BURST
READ
Q(A4+1)
tKHQX
WRITE
D(A5)
READ
Q(A6)
DON’T CARE
UNDEFINED
NOTE:
1. For these waveforms, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 9:
NOP, STALL, and DESELECT Cycles
1
2
A1
A2
3
4
5
A3
A4
6
7
8
9
10
CLK
CKE#
CE#
ADV/LD#
R/W#
BWx#
ADDRESS
A5
tKHQZ
D(A1)
DQ
Q(A2)
Q(A3)
D(A4)
Q(A5)
tKHQX
COMMAND
WRITE
D(A1)
READ
Q(A2)
STALL
READ
Q(A3)
WRITE
D(A4)
STALL
NOP
READ
Q(A5)
DON’T CARE
DESELECT
CONTINUE
DESELECT
UNDEFINED
NOTE:
1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not
performed during this cycle.
2. For these waveforms, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most
recent data may be from the input data register.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
SNOOZE MODE
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time the ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs
except ZZ become disabled and all outputs go
to High-Z.
The ZZ is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When the
ZZ becomes a logic HIGH, ISB2Z is guaranteed after the
time tZZI is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pending operations are completed. Similarly, when exiting
SNOOZE MODE during tRZZ, only a DESELECT or
READ cycle should be given.
Table 18: SNOOZE MODE Electrical CharacteristicS
DESCRIPTION
Current during SNOOZE MODE
ZZ active to input ignored
CONDITIONS
SYMBOL
ZZ ³ VIH
ISB2Z
t
ZZ inactive to input sampled
t
ZZ active to snooze current
t
MIN
t
RZZI
NOTES
30
mA
ns
1
ns
1
t
2( KHKH)
t
ZZI
ZZ inactive to exit snooze current
UNITS
2(tKHKH)
ZZ
RZZ
MAX
2( KHKH)
0
ns
1
ns
1
NOTE:
1. This parameter is sampled.
Figure 10:
SNOOZE MODE Waveform
CLK
t ZZ
ZZ
I
t RZZ
t ZZI
SUPPLY
I ISB2Z
t RZZI
ALL INPUTS
(except ZZ)
DESELECT or READ Only
Outputs (Q)
High-Z
DON’T CARE
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V VDD, 3.3V I/O AC Test Conditions
2.5V VDD, 2.5V I/O AC Test Conditions
Input pulse levels ........................VIH = (VDD/2.2) + 1.5V
......................... VIL = (VDD/2.2) - 1.5V
Input rise and fall times ............................................. 1ns
Input timing reference levels............................. VDD/2.2
Output reference levels ....................................VDDQ/2.2
Output load................................... See Figures 11 and 12
Input pulse levels..........................VIH = (VDD/2) + 1.25V
.......................... VIL = (VDD/2) - 1.25V
Input rise and fall times ............................................. 1ns
Input timing reference levels.................................VDD/2
Output reference levels .......................................VDDQ/2
Output load................................... See Figures 13 and 14
3.3V VDD, 2.5V I/O AC Test Conditions
Input pulse levels ....................VIH = (VDD/2.64) + 1.25V
..................... VIL = (VDD/2.64) - 1.25V
Input rise and fall times ..............................................1ns
Input timing reference levels............................VDD/2.64
Output reference levels .......................................VDDQ/2
Output load................................... See Figures 13 and 14
3.3V I/O Output Load Equivalent
2.5V I/O Output Load Equivalent
Figure 11:
Figure 13:
VT = VDDQ/2.2
VT = VDDQ/2
50Ω
50Ω
Q
Q
Z O= 50Ω
Z O= 50Ω
30pF
Figure 12:
Figure 14:
+2.5V
+3.3V
225Ω
317
Q
351
30pF
Q
5pF
225Ω
5pF
NOTE:
For Figures 11 and 13, 30pF = distributive test jig capacitance.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP)
Test Clock (TCK)
The SRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-In (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 15. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most significant bit (MSB) of any register. (See Figure 16.)
Disabling the JTAG Feature
These balls can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon powerup, the device will come up in a reset state which will
not interfere with the operation of the device.
Figure 15:
TAP Controller State Diagram
Test Data-Out (TDO)
1
The TDO output ball is used to serially clock dataout from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 15.) The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 16.)
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
Figure 16:
TAP Controller Block Diagram
1
0
PAUSE-DR
0
0
PAUSE-IR
1
0
Bypass Register
1
EXIT2-DR
0
2 1 0
EXIT2-IR
1
TDI
0
Instruction Register
.
Selection
Circuitry
TDO
. 2 1 0
Identification Register
UPDATE-IR
1
Selection
Circuitry
31 30 29 .
1
UPDATE-DR
1
0
1
EXIT1-DR
0
1
x .
0
.
.
.
. 2 1 0
Boundary Scan Register*
NOTE:
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
TCK
TMS
TAP CONTROLLER
NOTE:
X = 74 for all configurations.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Performing a TAP Reset
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
A RESET is performed by forcing TMS HIGH (VDD)
for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
Instruction Register
Three-bit instructions can be serially loaded into
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 16. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two LSBs are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test
data path.
TAP Instruction Set
Overview
Eight different instructions are possible with the
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the
input and bidirectional balls on the SRAM. The SRAM
as a 75 bit-long register.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction register through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.
The user must be aware that the TAP controller
clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CLK captured in the
boundary scan register.
Once the data is captured, it is possible to shift out
the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction will have the same effect as the Pause-DR command.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller, and therefore this device is not
compliant to 1149.1.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is
one difference between the two instructions. Unlike
the SAMPLE/PRELOAD instruction, EXTEST places
the SRAM outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
BYPASS
When the BYPASS instruction is loaded in the
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when
multiple devices are connected together on a board.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
Reserved
These instructions are not implemented but are
reserved for future use. Do not use these instructions.
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 17:
TAP Timing
1
2
Test Clock
(TCK)
3
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
4
5
6
tTHTH
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
Table 19: TAP AC Electrical Characteristics
Notes 1, 2; 0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V or 2.5V ±0.125V
DESCRIPTION
SYMBOL
Clock
Clock cycle time
t
THTH
f
Clock frequency
MIN
MAX
100
ns
10
TF
UNITS
MHz
Clock HIGH time
t
40
ns
Clock LOW time
t
TLTH
40
ns
Output Times
TCK LOW to TDO unknown
t
TLOX
0
ns
TCK LOW to TDO valid
t
TLOV
TDI valid to TCK HIGH
t
10
ns
TCK HIGH to TDI invalid
t
THDX
10
ns
Setup Times
TMS setup
t
MVTH
10
ns
CS
10
ns
THMX
10
ns
10
ns
THTL
DVTH
Capture setup
t
Hold Times
TMS hold
t
t
Capture hold
CH
20
ns
NOTE:
1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the loads in Figures Table 18 and 19.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
3.3V TAP AC Test Conditions
2.5V TAP AC Test Conditions
Input Pulse Levels .......................................... Vss to 3.0V
Input rise and fall times ..............................................1ns
Input timing reference levels.................................... 1.5V
Output reference levels ............................................. 1.5V
Test load termination supply voltage ...................... 1.5V
Input Pulse Levels........................................... Vss to 2.5V
Input rise and fall times ............................................. 1ns
Input timing reference levels.................................. 1.25V
Output reference levels ........................................... 1.25V
Test load termination supply voltage .................... 1.25V
Figure 18:
3.3V TAP AC Output Load Equivalent
Figure 19:
2.5V TAP AC Output Load Equivalent
1.25V
1.5V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
Z O= 50Ω
20pF
20pF
Table 20: 3.3V VDD, TAP DC Electrical Characteristics and Operating Conditions
0ºC £ TA £ +70ºC; VDD = 3.3V ±0.165V unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
CONDITIONS
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDD (TDO)
IOLC = 100µA
IOLT = 2mA
IOHC = -100µA
IOHT = -2mA
SYMBOL
MIN
MAX
UNITS
NOTES
VIH
VIL
ILI
ILO
2.0
-0.3
-10
-10
VDD + 0.3
0.8
10
10
V
V
µA
µA
1, 2
1, 2
2
2
0.7
0.8
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VOL1
VOL2
VOH1
VOH2
2.9
2.0
Table 21: 2.5V VDD, TAP DC Electrical Characteristics and Operating Conditions
0ºC £ TA £ +70ºC; VDD = 2.5V ±0.125V unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
CONDITIONS
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDD (TDO)
IOLC = 100µA
IOLT = 2mA
IOHC = -100µA
IOHT = -2mA
SYMBOL
MIN
MAX
UNITS
NOTES
VIH
VIL
ILI
ILO
1.7
-0.3
-10
-10
VDD + 0.3
0.7
10
10
V
V
µA
µA
1, 2
1, 2
2
2
0.2
0.7
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VOL1
VOL2
VOH1
VOH2
2.1
1.7
NOTE:
1. All voltages referenced to VSS (GND).
2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and
Operation Conditions tables.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 22: Identification Register Definitions
BIT
CONFIGURATION
INSTRUCTION FIELD
0000
Revision Number
(31:28)
Device Depth
(27:23)
Device Width
(22:18)
Micron Device ID
(17:12)
Micron JEDEC ID Code
(11:1)
ID Register Presence
Indicator (0)
00111
00110
00011
00100
xxxxxx
00000101100
1
DESCRIPTION
Reserved for version number.
Defines depth of 1Mb.
Defines depth of 512K.
Defines width of x18 bits.
Defines width of x 32 or x36 bits.
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Table 23: Scan Register Sizes
REGISTER NAME
BIT SIZE
3
1
32
75
Instruction
Bypass
ID
Boundary Scan: x18, x32, x36
Table 24: Instruction Codes
INSTRUCTION
CODE
EXTEST
000
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 25: 165-Ball FBGA Boundary Scan Order (x18)
BIT#
SIGNAL NAME
BALL ID
BIT#
SIGNAL NAME
BALL ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
MODE (LBO#)
NF
NF
SA
SA
SA
SA
SA
SA
SA
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
SA
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
1R
6N
11P
8R
8P
9R
9P
10R
10P
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10B
10A
9A
9B
8A
8B
7A
7B
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
CLK
NC
NC
CE2#
BWa#
NC
BWb#
NC
CE2
CE#
SA
SA
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
SA
SA
SA
SA
SA1
SA0
6B
11B
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
1N
2K
2L
2M
2J
3P
3R
4P
4R
6P
6R
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 26: 165-Ball FBGA Boundary Scan Order (x32)
BIT#
SIGNAL NAME
BALL ID
BIT#
SIGNAL NAME
BALL ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
MODE (LB0#)
NF
NF
SA
SA
SA
SA
SA
SA
SA
ZZ
NF
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
NF
NC
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
1R
6N
11P
8R
8P
9R
9P
10R
10P
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10B
10A
9A
9B
8A
8B
7A
7B
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
CLK
NC
NC
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
NC
NF
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
NF
SA
SA
SA
SA
SA1
SA0
6B
11B
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
2J
2K
2L
2M
1N
3P
3R
4P
4R
6P
6R
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Table 27: 165-Ball FBGA Boundary Scan Order (x36)
BIT#
SIGNAL NAME
BALL ID
BIT#
SIGNAL NAME
BALL ID
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
MODE (LB0#)
NF
NF
SA
SA
SA
SA
SA
SA
SA
ZZ
DQPa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
SA
SA
SA
SA
ADV/LD#
OE# (G#)
CKE#
R/W#
1R
6N
11P
8R
8P
9R
9P
10R
10P
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
10G
10F
10E
10D
11C
11A
10B
10A
9A
9B
8A
8B
7A
7B
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
CLK
NC
NC
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
NC
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
SA
SA
SA
SA
SA1
SA0
6B
11B
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
2J
2K
2L
2M
1N
3P
3R
4P
4R
6P
6R
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
31
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 20: 100-Pin Plastic TQFP
(JEDEC LQFP)
+0.10
-0.20
20.10 ±0.10
22.10
0.65 TYP
0.32
+0.06
-0.10
0.625
SEE DETAIL A
14.00 ±0.10
16.00 ±0.20
PIN #1 ID
0.15
+0.03
-0.02
1.40 ±0.05
GAGE PLANE
1.60 MAX
0.10
0.10
+0.10
-0.05
0.60 ±0.15
1.00 TYP
0.25
DETAIL A
NOTE:
1. All dimensions in inches (millimeters)
MAX
-------------MIN
or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
32
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Figure 21:
165-Ball FBGA
0.85 ±0.075
0.12 C
SEATING PLANE
C
BALL A11
165X Ø 0.45
LL DIAMETER REFERS
EFLOW CONDITION. THE
W DIAMETER IS Ø 0.40
10.00
BALL A1
PIN A1 ID
1.00
TYP
1.20 MAX
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
6.50 ±0.05
SUBSTRATE: PLASTIC LAMINATE
5.00 ±0.05
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36%
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
NOTE:
1. All dimensions in inches (millimeters)
MAX
-------------MIN
or typical where noted.
Data Sheet Designation
No Marking: This data sheet contains minimum and maximum limits specified over the complete power
supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc.,
and Motorola, Inc.
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
18Mb: 1 MEG x 18, 512K x 32/36
PIPELINED ZBT SRAM
Document Revision History
• Rev D; Pub. 2/03..........................................................................................................................................................2/03
Changed designation from Preliminary to Production
• Rev C; Pub. 12/02 ......................................................................................................................................................12/02
Added TJ specifications to the AC Electrical Characteristics table
Corrected Boundary Scan errors
Updated TQFP and FBGA Thermal Resistance values
Corrected grammatical errors
• Rev B; PRELIMINARY ...............................................................................................................................................11/02
Changed designation from ADVANCE to PRELIMINARY
Corrected grammatical errors
• New ADVANCE data sheet for 0.16µm process; Rev A; Pub. 6/02 ...........................................................................6/02
18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM
MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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