2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
18Mb DDRII CIO SRAM
4-WORD BURST
MT57W2MH8J
MT57W1MH18J
MT57W512H36J
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DLL circuitry for accurate output data placement
Pipelined, double data rate operation
Common data input/output bus
Fast clock to valid data times
Full data coherency, providing most current data
Four-tick burst for reduced-address frequency
Two input clocks (K and K#) for precise DDR timing
at clock rising edges only
Two output clocks (C and C#) for precise flight time
and clock skew matching—clock and data delivered
together to receiving device
Optional-use echo clocks (CQ and CQ#) for flexible
receive data synchronization
Simple control logic for easy depth expansion
Internally self-timed, registered writes
Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.5V to VDD
(±0.1V) HSTL
Clock-stop capability with µs restart
13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA
package
User-programmable impedance output
JTAG boundary scan
Options
• Clock Cycle Timing
3ns (333 MHz)
3.3ns (300 MHz)
4ns (250 MHz)
5ns (200 MHz)
6ns (167 MHz)
7.5ns (133 MHz)
• Configurations
2 Meg x 8
1 Meg x 18
512K x 36
• Package
165-ball, 13mm x 15mm FBGA
• Operating Temperature Range
Commercial (0°C £ TA £ +70°C)
Figure 1: 165-Ball FBGA
.
Table 1:
Marking1
PART NUMBER
DESCRIPTION
MT57W2MH8JF-xx
MT57W1MH18JF-xx
MT57W512H36JF-xx
2 Meg x 8, DDRIIb4 FBGA
1 Meg x 18, DDRIIb4 FBGA
512K x 36, DDRIIb4 FBGA
General Description
The Micron® DDRII synchronous, pipelined burst
SRAM employs high-speed, low-power CMOS designs
using an advanced 6T CMOS process.
The DDR SRAM integrates an SRAM core with
advanced synchronous peripheral circuitry and a burst
counter. All synchronous inputs pass through registers
controlled by an input clock pair (K and K#) and are
latched on the rising edge of K and K#. The synchronous inputs include all addresses, all data inputs,
active LOW load (LD#), read/write (R/W#), and active
LOW byte writes or nibble writes (BWx# or NWx#).
Write data is registered on the rising edges of both K
and K#. Read data is driven on the rising edge of C and
C#, if provided, or on the rising edge of K and K# if C
and C# are not provided.
Asynchronous inputs include impedance match
(ZQ). Synchronous data outputs (Q, sharing the same
physical balls as the data inputs D) are tightly matched
-3
-3.3
-4
-5
-6
-7.5
MT57W2MH8J
MT57W1MH18J
MT57W512H36J
F
None
NOTE:
1. A Part Marking Guide for the FBGA devices can be found on
Micron’s Web site—http://www.micron.com/numberguide
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
Valid Part Numbers
1
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
to the output data clocks C and C#, eliminating the
need for separately capturing data from each individual DDR SRAM in the system design.
Additional write registers are incorporated to
enhance pipelined WRITE cycles and reduce READ-toWRITE turnaround time. WRITE cycles are self-timed.
Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
The device can be used in HSTL systems by supplying an appropriate reference voltage (VREF ). The
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
The SRAM operates from a 1.8V power supply, and
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP, and other applications that benefit from a very
wide, high-speed data bus.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
If a READ occurs after a WRITE cycle, address and
data for the write are stored in registers. The write
information must be stored because the SRAM cannot
perform the last word write to the array without conflicting with the read. The data stays in this register
until the next WRITE cycle occurs. On the first WRITE
cycle after the READ(s), the stored data from the earlier
WRITE will be written into the SRAM array. This is
called a posted write.
A read can be made immediately to an address even
if that address was written in the previous cycle. During this READ cycle, the SRAM array is bypassed, and
data is read instead from the data register storing the
recently written data. This is transparent to the user.
This feature facilitates system data coherency.
The DDR SRAM differs in some ways from its predecessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. The need
for echo clocks is reduced or eliminated by the two single-ended input clocks (C and C#), although tightly
controlled echo clocks (CQ and CQ#) are provided. The
SRAM synchronizes its output data to these data clock
rising edges, if provided. No differential clocks are used
in this device. This clocking scheme provides greater
system tuning capability than Claymore SRAMs and
reduces the number of input clocks required by the
bus master.
DDR Operation
PARTIAL WRITE Operations
The DDR SRAM enables high performance operation through high clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
no-operation (NOP) cycle when transitioning from a
READ to a WRITE cycle. At higher frequencies, a second NOP cycle may be required to prevent bus contention. NOP cycles are not required when switching from
a WRITE to a READ.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
BYTE WRITE operations are supported, except for
x8 devices in which nibble write is supported. The
active LOW write controls, BWx# (NWx#), are registered coincident with their corresponding data. This
feature can eliminate the need for some READ-MODIFY-WRITE cycles, collapsing it to a single BYTE/NIBBLE WRITE operation in some instances.
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Programmable Impedance Output
Buffer
Clock Considerations
This device utilizes internal delay-locked loops for
maximum output, data valid window. It can be placed
into a stopped-clock state to minimize power with a
modest restart time of 1,024 clock cycles. Circuitry
automatically resets the DLL when the absence of
input clock is detected. See Micron Technical Note TN54-02 for more information on clock DLL start-up procedures.
The DDR SRAM is equipped with programmable
impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the
resistor must be five times the desired impedance. For
example, a 350W resistor is required for an output
impedance of 70W . To ensure that output impedance
is one-fifth the value of RQ (within 15 percent), the
range of RQ is 175W to 350W . Alternately, the ZQ ball
can be connected directly to VDDQ, which will place
the device in a minimum impedance mode.
Output impedance updates may be required
because, over time, variations may occur in supply
voltage and temperature. The device samples the value
of RQ. Impedance updates are transparent to the system; they do not affect device operation, and all data
sheet timing and current specifications are met during
an update.
The device will power up with an output impedance
set at 50W . To guarantee optimum output driver
impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.
Single Clock Mode
The SRAM can be used with the single K, K# clock
pair by tying C and C# HIGH. In this mode, the SRAM
will use K and K# in place of C and C#. This mode provides the most rapid data output but does not compensate for system clock skew and flight times.
The output echo clocks are precise references to
output data. CQ and CQ# are both rising edge and falling edge accurate and are 180° out of phase. Either or
both may be used for output data capture. K or C rising
edge triggers CQ rising and CQ# falling edge. CQ rising
edge indicates first data response for QDRI and DDRI
(version 1, non-DLL) SRAM, while CQ# rising edge
indicates first data response for QDRII and DDRII (version 2, DLL) SRAM.
Depth Expansion
Depth expansion requires replicating the LD# control signal for each bank. All other control signals can
be common between banks as appropriate.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Figure 2: Functional Block Diagram
2 Meg x 8; 1 Meg x 18; 512K x 36
n
n
SA
LD#
E
n-2
n
ADDRESS
REGISTER
n
READ
SA1
SA1’
D1
Q1
SA0
SA0’
BURST
D0
Q0
LOGIC
CLK
COMPARE
(NOTE 1)
(NOTE 2)
WRITE#
n
WRITE#
a
SA’
INPUT
REGISTER
K#
E
SA0'''
SA0#’
a
SA0’
CLK
a
INPUT
REGISTER
C#
SA0’
E
a
OUTPUT
CONTROL
LOGIC
C
n
WRITE
E ADDRESS
REGISTER
K
SA0''
a
a
a
WRITE
DRIVER
WRITE
REGISTER
SA0#’
a
SA0’
a
2n x a
MEMORY
ARRAY
a
a
a
SENSE
AMPS
a
C
a
a
OUTPUT
REGISTER
a
ZQ
0
2:1
MUX
2
a
1
CQ, CQ#
a
OUTPUT
BUFFER
a
DQ
E
0
a
1
SA0''’
a
NWx#
BWx#
R/W#
R/W#
E REGISTER
WRITE#
OE
REGISTER
C
NOTE:
1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.
2. The compare width is n – 2 bits. The compare is performed only if a WRITE is pending and a READ cycle is requested.
If the address matches, data is routed directly to the device outputs, bypassing the memory array.
3. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing
diagrams for detailed information.
4. For 2 Meg x 8, n = 21, a = 8; NWx# = 2 separate nibble writes.
For 1 Meg x 18, n = 20, a = 18; BWx# = 2 separate byte writes.
For 512K x 36, n = 19, a = 36; BWx# = 4 separate byte writes.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Figure 3: Application Example
R = 250Ω
R = 250Ω
ZQ
CQ
CQ#
SRAM 1
DQ
SA
LD# R/W# C C# K K#
SRAM 2
DQ
SA
ZQ
CQ
CQ#
LD# R/W# C C# K K#
Vt
DQ
Address
Cycle Start#
R/W#
R
Vt
SRAM 1 Input CQ
BUS SRAM 1 Input CQ#
MASTER SRAM 2 Input CQ
(CPU SRAM 2 Input CQ#
or
Source K
ASIC)
Source K#
Delayed K
Delayed K#
R
R = 50Ω Vt = VREF
NOTE:
1. In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets setup
and hold times at the bus master.
2. Consult Micron Technical Notes for more thorough discussions of clocking schemes.
3. Data capture is possible using only one of the two signals. CQ and CQ# clocks are optional use outputs.
4. For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended
over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 2:
2 Meg x 8 Ball Layout (Top View)
165-Ball FBGA
1
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
VSS/SA1
NC
NC
NC
NC
NC
NC
VREF
NC
NC
DQ6
NC
NC
NC
TCK
3
SA
NC
NC
NC
DQ4
NC
DQ5
VDDQ
NC
NC
NC
NC
NC
DQ7
SA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NOTE:
1. Expansion address: 2A for 72Mb
2. NW1# controls writes to DQ4:DQ7
3. Expansion address: 7A for 144Mb
4. Expansion address: 10A for 36Mb
5. Expansion address: 5B for 288Mb
6. NW0# controls writes to DQ0:DQ3
4
R/W#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
5
NW1#2
NC5
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
C#
7
NC3
NW0#6
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
VSS/SA4
NC
NC
NC
NC
NC
NC
VREF
DQ1
NC
NC
NC
NC
NC
TMS
11
CQ
DQ3
NC
NC
DQ2
NC
NC
ZQ
NC
NC
DQ0
NC
NC
NC
TDI
Note that the x8 does not permit random start address on the two least-significant address bits. SA and SA1 = 0 at
the start of each address.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 3:
1 Meg x 18 Ball Layout (Top View)
165-Ball FBGA
1
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
VSS/SA1
DQ9
NC
NC
NC
DQ12
NC
VREF
NC
NC
DQ15
NC
NC
NC
TCK
3
SA
NC
NC
DQ10
DQ11
NC
DQ13
VDDQ
NC
DQ14
NC
NC
DQ16
DQ17
SA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NOTE:
1. Expansion address: 2A for 72Mb
2. BW1#controls writes to DQ9:DQ17
3. Expansion address: 7A for 144Mb
4. Expansions address: 10A for 36Mb
5. Expansion address: 5B for 288Mb
6. BW0# controls writes to DQ0:DQ8
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
4
R/W#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
5
BW1#2
NC/SA5
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
C#
7
7
NC/SA3
BW06#
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
VSS/SA4
NC
DQ7
NC
NC
NC
NC
VREF
DQ4
NC
NC
DQ1
NC
NC
TMS
11
CQ
DQ8
NC
NC
DQ6
DQ5
NC
ZQ
NC
DQ3
DQ2
NC
NC
DQ0
TDI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 4:
512K x 36 Ball Layout (Top View)
165-Ball FBGA
1
CQ#
NC
NC
NC
NC
NC
NC
DLL#
NC
NC
NC
NC
NC
NC
TDO
2
VSS/SA1
DQ27
NC
DQ29
NC
DQ30
DQ31
VREF
NC
NC
DQ33
NC
DQ35
NC
TCK
3
NC/SA2
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
VDDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NOTE:
1. Expansion address: 2A for 144Mb
2. Expansion address: 3A for 36Mb
3. BW2# controls writes to DQ18:DQ26
4. BW1# controls writes to DQ9:DQ17
5. Expansion address: 10A for 72Mb
6. BW3# controls writes to DQ27:DQ35
7. BW0# controls writes to DQ0:DQ8
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
4
R/W#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
5
BW2#3
BW3#6
SA
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
6
K#
K
SA0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SA
C
C#
8
7
BW1#4
BW0#7
SA1
VSS
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
SA
SA
SA
8
LD#
SA
VSS
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VSS
VSS
SA
SA
9
SA
NC
NC
NC
NC
NC
NC
VDDQ
NC
NC
NC
NC
NC
NC
SA
10
VSS/SA5
NC
DQ17
NC
DQ15
NC
NC
VREF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 5:
Ball Descriptions
SYMBOL
TYPE
DESCRIPTION
BW_#
NW_#
Input
C
C#
Input
DLL#
Input
K
K#
Input
LD#
Input
R/W#
Input
SA0
SA1
SA
Input
TCK
Input
TMS
TDI
VREF
Input
ZQ
Input
DQ_
Input/
Output
CQ#, CQ
Output
TDO
VDD
VDDQ
Output
Supply
Supply
VSS
Supply
Synchronous Byte Writes (or Nibble Writes on x8): When LOW, these inputs cause their respective
bytes or nibbles to be registered and written if W# had initiated a WRITE cycle. These signals must
meet setup and hold times around the rising edges of K and K# for each of the four rising edges
comprising the WRITE cycle. See Ball Layout figures for signal to data relationships.
Output Clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C# is used as the output timing reference for first and third output data. The rising
edge of C is used as the output reference for second and fourth output data. Ideally, C# is 180
degrees out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output
reference clocks instead of having to provide C and C# clocks. If tied HIGH, these inputs may not be
allowed to toggle during device operation.
DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency
operation.
Input Clock: This input clock pair registers address and control inputs on the rising edge of K and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.
Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of four data
(two clock periods of bus activity).
Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when
R/W# is HIGH; WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and
hold times around the rising edge of K.
Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Layout figures for address expansion inputs. All transactions
operate on a burst of four words (two clock periods of bus activity). SA0 and SA1 are used as the
lowest two address bits for BURST READ and BURST WRITE operations, permitting a random burst
start address on the x18 and x36 devices. These inputs are ignored when both ports are deselected.
IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to VSS if the JTAG function is not used
in the circuit.
IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left as No Connects if the JTAG function is
not used in the circuit.
HSTL Input Reference Voltage: Nominally VDDQ/2. Provides a reference voltage for the HSTL input
buffer trip points.
Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this
ball to ground. Alternately, this ball can be connected directly to VDDQ to enable the minimum
impedance mode. This ball cannot be connected directly to GND or left unconnected.
Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K
and K#. Output data is synchronized to the respective C and C# data clocks or to K and K#, if C and
C# are tied HIGH. See Ball Layout figures for ball site location of individual signals. The x8 device
uses DQ0-DQ7. Remaining signals are NC. The x18 device uses DQ0-DQ17. Remaining signals are NC.
The x36 device uses DQ0-DQ35. Remaining signals are NC.
Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the
synchronous data outputs and can be used as data valid indication. These signals run freely and do
not stop when DQ tri-states.
IEEE 1149.1 Test Output: 1.8V I/O level.
Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range.
Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC
Electrical Characteristics and Operating Conditions for range.
Power Supply: GND.
Input
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 5:
Ball Descriptions (continued)
SYMBOL
TYPE
NC
–
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
DESCRIPTION
No Connect: These balls are internally connected to the die, but have no function and may be left
not connected to the board to minimize ball count.
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 6:
Burst Address Table
x 18, x 36 only
FIRST ADDRESS
(EXTERNAL)
SECOND ADDRESS
(INTERNAL)
THIRD ADDRESS
(INTERNAL)
FOURTH ADDRESS
(INTERNAL)
X . . . X00
X . . . X01
X . . . X10
X . . . X11
X . . . X01
X . . . X10
X . . . X11
X . . .X00
X . . . X10
X . . . X11
X . . . X00
X . . . X01
X . . . X11
X . . . X00
X . . . X01
X . . . X10
Figure 4:
Bus Cycle State Diagram
L
L#, Count=4
always
READ DOUBLE
Count=Count+2
Count=2
ADVANCE ADDRESS
BY TWO1
NOP
L#
L, Count=4
R
LOAD NEW ADDRESS
Count=0
Supply
voltage
provided
L#, Count=4
L, Count=4
W
always
WRITE DOUBLE
Count=Count+2
Count=2
ADVANCE ADDRESS
BY TWO1
POWER-UP
NOTE:
1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst
count = 4.
2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW).
3. State machine, control timing sequence is controlled by K.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 7:
Truth Table
Notes 1–6
OPERATION
WRITE Cycle:
Load address, input write data on
two consecutive K and K# rising
edges
READ Cycle:
Load address, read data on two
consecutive C and C# rising edges
NOP: No operation
STANDBY: Clock stopped
Table 8:
LD#
R/W#
K
DQ
DQ
DQ
DQ
L
L
L®H
DIN(A0)
at
K(t)
DIN(A0 + 1)
at
K#(t + 1)
DIN(A0 + 2)
at
K(t + 2)
DIN(A0 + 3)
at
K#(t + 3)
L
H
L®H
H
X
X
X
L®H
Stopped
QOUT(A0)
at
C#(t)
High-Z
Previous
State
QOUT(A0 + 1)
at
C(t + 1)
High-Z
Previous
State
QOUT(A0 + 2)
at
C#(t + 2)
High-Z
Previous
State
QOUT(A0 + 3)
at
C(t + 3)
High-Z
Previous
State
BYTE WRITE Operation
Notes 7, 8
OPERATION
K
K#
BW0#
BW1#
L®H
0
0
WRITE D0:17 at K rising edge
L®H
0
0
WRITE D0:17 at K# rising edge
L®H
0
1
WRITE D0:8 at K rising edge
L®H
0
1
WRITE D0:8 at K# rising edge
L®H
1
0
WRITE D9:17 at K rising edge
L®H
1
0
WRITE D9:17 at K# rising edge
L®H
1
1
WRITE nothing at K rising edge
L®H
1
1
WRITE nothing at K# rising edge
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW. means rising edge; ¯ means falling edge.
2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges except if C
and C# are HIGH, then data outputs are delivered at K and K# rising edges.
3. R/W# and LD# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the
rising edge of K.
4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification. A0 + 1 refers to the address input during a WRITE or
READ cycle. A0 + 2 refers to the next internal burst address in accordance with the burst sequence.
6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by
overcoming transmission line charging symmetrically.
7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation
provided that the setup and hold requirements are satisfied.
8. This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2#
(controls DQ18:DQ26) and BW3# (controls DQ27:DQ35). The x8 device operation is similar, except that NW0# controls DQ0:DQ3, and NW1# controls DQ4:DQ7.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Absolute Maximum Ratings
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
Maximum Junction Temperature depends upon
package type, cycle time, loading, ambient temperature, and airflow.
Voltage on VDD Supply
Relative to VSS ......................................... -0.5V to 2.8V
Voltage on VDDQ Supply
Relative to Vss ......................................... -0.5V to VDD
VIN ....................................................... -0.5V to VDD +0.5V
Storage Temperature .............................. -55°C to +125°C
Junction Temperature .......................................... +125°C
Short Circuit Output Current .............................. ±70mA
Table 9:
DC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 17; 0°C £ TA £ +70°C; VDD = 1.8V ±0.1V unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Signal Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
CONDITIONS
0V £ VIN £ VDDQ
Output(s) disabled,
0V £ VIN £ VDDQ (Q)
|IOH| £ 0.1mA
Note 1
IOL £ 0.1mA
Note 2
Supply Voltage
Isolated Output Buffer Supply
Reference Voltage
SYMBOL
MIN
MAX
UNITS
NOTES
VIH(DC)
VIL(DC)
VIN
ILI
ILO
VREF + 0.1
-0.3
-0.3
-5
-5
VDDQ + 0.3
VREF - 0.1
VDDQ + 0.3
5
5
V
V
V
µA
µA
3, 4
3, 4
3, 4
V
V
V
V
V
V
V
3, 5, 6
3, 5, 6
3, 5, 6
3, 5, 6
3
3, 7
3
VOH (LOW)
VOH
VOL (LOW)
VOL
VDD
VDDQ
VREF
VDDQ - 0.2
VDDQ
VDDQ/2 - 0.12 VDDQ/2 + 0.12
VSS
0.2
VDDQ/2 - 0.12 VDDQ/2 + 0.12
1.7
1.9
1.4
VDD
0.68
0.95
Table 10: AC Electrical Characteristics and Operating Conditions
Notes appear following parameter tables on page 17; 0°C £ TA £ +70°C; VDD = 1.8V ±0.1V unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 1) Voltage
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
VIH(AC)
VIL(AC)
VREF + 0.2
-
VREF - 0.2
V
V
3, 4, 8
3, 4, 8
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 11: IDD Operating Conditions and Maximum Limits
Notes appear following parameter tables on page 17; 0°C £ TA £ +70°C; VDD = 1.8V ±0.1V unless otherwise noted
MAX
DESCRIPTION
Operating Supply
Current: DDR
Standby Supply
Current: NOP
CONDITIONS
SYMBOL
TYP
-3
-3.3
-4
-5
-6
-7.5
UNITS
NOTES
mA
9, 10
mA
10, 11
mA
12
All inputs £ VIL or ³
VIH; Cycle time ³ tKHKH
(MIN); Outputs open;
x:1 ratio for READs to
WRITEs; 50% address
and data bits toggling
on each clock cycle
KHKH = tKHKH (MIN);
Device in NOP state;
All addresses/data
static
TBD
IDD
x8, x18
x36
390
520
355
475
300
400
250
330
215
285
180
240
255
265
235
245
200
210
170
180
150
160
125
135
42
95
189
38
85
170
32
71
142
25
57
142
21
47
95
17
38
76
t
Output Supply
Current: DDR
(Information only)
CL = 15pF
ISB1
x8, x18
x36
IDDQ
x8
x18
x36
TBD
TBD
Table 12: Capacitance
Note 13; notes appear following parameter tables on page 17
DESCRIPTION
Address/Control Input Capacitance
Input, Output Capacitance (DQ)
Clock Capacitance
CONDITIONS
SYMBOL
TYP
MAX
UNITS
TA = 25°C; f = 1 MHz
CI
CO
CCK
4.5
6
5.5
5.5
7
6.5
pF
pF
pF
SYMBOL
TYP
UNITS
NOTES
qJA
19.4
°C/W
14
qJC
1.0
°C/W
qJB
9.6
°C/W
Table 13: Thermal Resistance
Note 13; notes appear following parameter tables on page 17
DESCRIPTION
CONDITIONS
Junction to Ambient (Airflow of 1m/s)
Junction to Case (Top)
Junction to Balls (Bottom)
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
Soldered on a 4.25 x 1.125 inch,
4-layer printed circuit board
14
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 14: AC Electrical Characteristics and Recommended Operating Conditions
Notes 16-19; 22; notes appear following parameter tables on page 17; °C £ TA £ +70°C; TJ £ +95°C; VDD = 1.8V ±0.1V
SYM
-3
-3.3
-4
-5
-6
-7.5
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
KHKH
3.00
DESCRIPTION
Clock
Clock cycle time
(K, K#, C, C#)
Clock phase
jitter (K, K#, C,
C#)
Clock HIGH time
(K, K#, C, C#)
Clock LOW time
(K, K#, C, C#)
Clock to clock#
(K®K#,
C®C#) at
t
t
KC var
3.47
3.30
0.20
4.20
4.00
0.20
5.25
5.00
0.20
6.30
6.00
0.20
7.80
7.50
0.20
8.40
ns
20
0.20
ns
21
t
1.20
1.32
1.60
2.00
2.40
3.00
ns
t
1.20
1.32
1.60
2.00
2.40
3.00
ns
KHK#H 1.35
1.49
1.80
2.20
2.70
3.38
ns
1.49
1.80
2.20
2.70
3.38
ns
KHKL
KLKH
t
t
KHKH minimum
Clock# to clock
(K#®K,
t
K#HKH 1.35
C#®C)at
t
KHKH minimum
Clock to data
t
clock (K®C,
KHCH 0.00
K#®C#)
DLL lock time (K, t
KC lock 1,024
C)
t
K static to DLL
KC
30
reset
reset
Output Times
C, C# HIGH to
t
CHQV
output valid
C, C# HIGH to
t
CHQX -0.45
output hold
C, C# HIGH to
t
CHCQV
echo clock valid
C, C# HIGH to
t
CHCQX -0.45
echo clock hold
CQ, CQ# HIGH to t
CQHQV
output valid
CQ, CQ# HIGH to t
CQHQX -0.25
output hold
C HIGH to
t
CHQZ
output High-Z
C HIGH to
t
CHQX1 -0.45
output Low-Z
Setup Times
Address valid to t
AVKH 0.40
K rising edge
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
1.30
0.00
1.45
0.00
1.80
0.00
2.30
0.00
2.80
0.00
3.55
ns
1,024
1,024
1,024
1,024
1,024
cycles
30
30
30
30
30
ns
0.45
0.45
-0.45
0.45
0.45
-0.45
0.45
-0.45
0.25
0.45
0.27
0.45
-0.45
-0.45
-0.27
0.45
0.45
0.30
0.45
-0.50
-0.45
-0.30
0.50
0.50
0.35
0.45
-0.50
-0.50
-0.35
0.50
-0.50
-0.40
0.45
ns
ns
0.40
-0.40
0.50
ns
ns
0.50
0.40
ns
ns
0.50
23
23
ns
-0.45
-0.45
-0.45
-0.50
-0.50
ns
0.40
0.50
0.60
0.70
0.70
ns
15
22
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 14: AC Electrical Characteristics and Recommended Operating Conditions
(continued)
DESCRIPTION
SYM
Control inputs
valid to K rising tIVKH
edge
Data-in valid to t
DVKH
K, K# rising edge
Hold Times
K rising edge to t
KHAX
address hold
K rising edge to
t
KHIX
control inputs
hold
K, K# rising edge t
KHDX
to data-in hold
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
-3
-3.3
-4
-5
-6
-7.5
UNITS NOTES
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
0.40
0.40
0.50
0.60
0.70
0.70
ns
16
0.28
0.30
0.35
0.40
0.50
0.50
ns
16
0.40
0.40
0.50
0.60
0.70
0.70
ns
16
0.40
0.40
0.50
0.60
0.70
0.70
ns
16
0.28
0.30
0.35
0.40
0.50
0.50
ns
16
16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Notes
1. Outputs are impedance-controlled. |IOH| =
(VDDQ/2)/(RQ/5) for values of 175W £ RQ £ 350W .
2. Outputs are impedance-controlled. IOL = (VDDQ/
2)/(RQ/5) for values of 175W £ RQ £ 350W .
3. All voltages referenced to VSS (GND).
4. Overshoot: VIH(AC) £ VDD + 0.7V for t £ tKHKH/2
Undershoot: VIL(AC) ³ -0.5V for t £ tKHKH/2
Power-up: VIH £ VDDQ + 0.3V and VDD £ 1.7V
and VDDQ £ 1.4V for t £ 200ms
During normal operation, VDDQ must not exceed
VDD. Control input signals may not have pulse
widths less than tKHKL (MIN) or operate at cycle
rates less than tKHKH (MIN).
5. AC load current is higher than the shown DC values. AC I/O curves are available upon request.
6. HSTL outputs meet JEDEC HSTL Class I and Class
II standards.
7. The nominal value of VDDQ may be set within the
range of 1.5V to 1.8V DC, and the variation of
VDDQ must be limited to ±0.1V DC.
8. To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current AC
level through the target AC level, VIL(AC) or
VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC) or
VIH(DC).
9. IDD is specified with no output current. IDD is linear with frequency. Typical value is measured at
6ns cycle time.
10. Typical values are measured at VDD = 1.8V, VDDQ =
1.5V, and temperature = 25°C.
11. NOP currents are valid when entering NOP after
all pending READ and WRITE cycles are completed.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
12. Average I/O current and power is provided for
informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with CL (in farads), f = input clock frequency, half
of outputs toggle at each transition (n = 18 for the
x36), CO = 6pF, VDDQ = 1.5V and uses the equations: Average I/O Power as dissipated by the
SRAM is: P = 0.5 × n × f × VDDQ2 x (CL + 2CO).
Average IDDQ = n × f × VDDQ x (CL + CO).
13. This parameter is sampled.
14. Average thermal resistance between the die and
the case top surface per MIL SPEC 883 Method
1012.1.
15. Junction temperature is a function of total device
power dissipation and device mounting environment. Measured per SEMI G38-87.
16. This is a synchronous device. All addresses, data,
and control lines must meet the specified setup
and hold times for all latching clock edges.
17. Test conditions as specified with the output loading as shown in Figure 5 unless otherwise noted.
18. Control input signals may not be operated with
pulse widths less than tKHKL (MIN).
19. If C and C# are tied HIGH, then K and K# become
the references for C and C# timing parameters.
20. The device will operate at clock frequencies
slower than tKHKH (MAX). See Micron Technical
Note TN-54-02 for more information.
21. Clock phase jitter is the variance from clock rising
edge to the next expected clock rising edge.
22. VDD slew rate must be less than 0.1V DC per 50ns
for DLL lock retention. DLL lock time begins once
VDD and input clock are stable.
23. Echo clock is tightly controlled to data valid/data
hold. By design, there is a ±0.1ns variation from
echo clock to data. The data sheet parameters
reflect tester guardbands and test setup variations.
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
AC Test Conditions
Figure 5:
Output Load Equivalent
Input pulse levels ................................ 0.25V to 1.25V
Input rise and fall times...................................... 0.7ns
Input timing reference levels .............................0.75V
Output reference levels................................... VDDQ/2
ZQ for 50W impedance ....................................... 250W
Output load ..............................................See Figure 5
VDDQ/2
0.75V
VREF
50Ω
SRAM
Z O = 50Ω
250Ω
ZQ
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Figure 6:
READ/WRITE Timing
NOP
READ
(burst of 4)
1
2
READ
(burst of 4)
3
NOP
4
5
NOP
(Note 3)
7
6
WRITE
(burst of 4)
8
WRITE
(burst of 4)
9
10
READ
(burst of 4)
12
11
13
K
tKHKL tKLKH
tKHKH
tKHK#H
K#
LD#
tIVKH
tKHIX
R/W#
A
A0
A1
A2
A3
tKHDX
tAVKH tKHAX
(Note 1)
DQ Qx2
Q00
tKHCH
tKHCH
tCHQV
tCHQX1
tDVKH
Q01
Q02
tCHQV
tCHQX
Q03
Q10
Q11
Q12
Q13
A4
tKHDX
tDVKH
D20
D21
D22
D23
D30
D31
D33
Q40
DON’T CARE
UNDEFINED
D32
tCQHQV
tCQHQX
tCHQX
tCHQZ
C
tKHKL tKLKH tKHKH
tKHK#H
C#
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ#
NOTE:
1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e.,
A0 + 1.
2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be
required to prevent bus contention.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
IEEE 1149.1 Serial Boundary Scan (JTAG)
Test Access Port (TAP)
Test Clock (TCK)
The SRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully-compliant TAPs. The TAP operates using
JEDEC-standard 1.8V I/O logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register, and
ID register.
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.
Test Data-in (TDI)
The TDI ball is used to serially input information
into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most significant bit (MSB) of any register, as illustrated in Figure 8.
Disabling The JTAG Feature
It is possible to operate the SRAM without using the
JTAG feature. To disable the TAP controller, TCK must
be tied LOW (VSS) to prevent clocking of the device.
TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
VDD through a pull-up resistor. TDO should be left
unconnected. Upon power-up, the device will come up
in a reset state, which will not interfere with the operation of the device.
Figure 8:
TAP Controller Block Diagram
Figure 7:
TAP Controller State Diagram
0
Bypass Register
1
TEST-LOGIC
RESET
2 1 0
0
0
RUN-TEST/
IDLE
Selection
Circuitry
TDI
1
SELECT
DR-SCAN
1
SELECT
IR-SCAN
0
1
0
TDO
. 2 1 0
x .
.
.
.
. 2 1 0
Boundary Scan Register
SHIFT-IR
1
.
Selection
Circuitry
Identification Register
CAPTURE-IR
0
SHIFT-DR
0
1
EXIT1-DR
1
EXIT1-IR
0
1
TCK
0
PAUSE-IR
1
TAP CONTROLLER
TMS
0
PAUSE-DR
0
1
EXIT2-DR
0
EXIT2-IR
1
NOTE:
1
UPDATE-DR
1
31 30 29 .
0
1
CAPTURE-DR
0
0
1
Instruction Register
0
X = 106.
UPDATE-IR
1
0
NOTE:
The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Test Data-out (TDO)
Boundary Scan Register
The TDO output ball is used to serially clock dataout from the registers. The output is active depending
upon the current state of the TAP state machine illustrated in Figure 7. The output changes on the falling
edge of TCK. TDO is connected to the least significant
bit (LSB) of any register, as depicted in Figure 8.
The boundary scan register is connected to all the
input and bidirectional balls on the SRAM. Several no
connect (NC) balls are also included in the scan register to reserve balls. The SRAM has a 107-bit-long register.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.
The Boundary Scan Order table shows the order in
which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.
Performing a TAP RESET
A RESET is performed by forcing TMS HIGH (VDD)
for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.
At power-up, the TAP is reset internally to ensure
that TDO comes up in a High-Z state.
TAP Registers
Registers are connected between the TDI and TDO
balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register at a time can be
selected through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.
Instruction Register
Three-bit instructions can be serially loaded into
the instruction register. This register is loaded when it
is placed between the TDI and TDO balls, as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two LSBs are loaded with a binary “01” pattern to
allow for fault isolation of the board-level serial test
data path.
TAP Instruction Set
Overview
Eight different instructions are possible with the
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (Vss) when
the BYPASS instruction is executed.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
EXTEST
SAMPLE/PRELOAD
EXTEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller; therefore, this device is not
1149.1-compliant.
The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a
SAMPLE/PRELOAD instruction has been loaded.
EXTEST does not place the SRAM outputs (including
CQ and CQ#) in a High-Z state.
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP into the UpdateDR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
BYPASS
When the BYPASS instruction is loaded in the
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
Reserved
These instructions are not implemented but are
reserved for future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction causes the boundary
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Figure 9: TAP Timing
1
2
Test Clock
(TCK)
3
tTHTL
tMVTH
tTHMX
tDVTH
tTHDX
t
TLTH
4
5
6
tTHTH
Test Mode Select
(TMS)
Test Data-In
(TDI)
tTLOV
tTLOX
Test Data-Out
(TDO)
DON’T CARE
UNDEFINED
NOTE:
Timing for SRAM inputs and outputs is congruent with TDI and TDO, respectively, as shown in Figure 9.
Table 15: TAP AC Electrical Characteristics
Notes 1, 2; 0°C £ TA £ +70°C; VDD = 1.8V ±0.1V
DESCRIPTION
SYMBOL
Clock
Clock cycle time
t
THTH
MIN
100
TF
UNITS
ns
10
f
Clock frequency
MAX
MHz
Clock HIGH time
t
40
ns
Clock LOW time
t
TLTH
40
ns
Output Times
TCK LOW to TDO unknown
t
TLOX
0
ns
THTL
20
ns
TCK LOW to TDO valid
t
TDI valid to TCK HIGH
t
10
ns
TCK HIGH to TDI invalid
t
10
ns
Setup Times
TMS setup
t
TLOV
DVTH
THDX
10
ns
CS
10
ns
THMX
10
ns
10
ns
MVTH
t
Capture setup
Hold Times
TMS hold
t
Capture hold
t
CH
NOTE:
1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 10.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
23
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
TAP AC Test Conditions
Figure 10:
TAP AC Output Load Equivalent
Input pulse levels ....................................... VSS to 1.8V
Input rise and fall times......................................... 1ns
Input timing reference levels ...............................0.9V
Output reference levels.........................................0.9V
Test load termination supply voltage .................0.9V
0.9V
50Ω
TDO
Z O= 50Ω
20pF
Table 16: TAP DC Electrical Characteristics and Operating Conditions
Note 2; 0°C £ TA £ +70°C; VDD = 1.8V ±0.1V unless otherwise noted
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output Low Voltage
Output High Voltage
Output High Voltage
CONDITIONS
0V £ VIN £ VDD
Output(s) disabled,
0V £ VIN £ VDD
IOLC = 100µA
IOLT = 2mA
|IOHC| = 100µA
|IOHT| = 2mA
SYMBOL
MIN
MAX
UNITS
NOTES
VIH
VIL
ILI
ILO
1.3
-0.3
-5.0
-5.0
VDD + 0.3
0.5
5.0
5.0
V
V
µA
µA
1, 2
1, 2
2
2
0.2
0.4
V
V
V
V
1, 2
1, 2
1, 2
1, 2
VOL1
VOL2
VOH1
VOH2
1.6
1.4
NOTE:
1. All voltages referenced to VSS (GND).
2. This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have
the DC values as defined in Table 9, “DC Electrical Characteristics and Operating Conditions,” on page 13.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 17: Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
000
REVISION NUMBER
(31:29)
DEVICE ID
(28:12)
00def0wx0t0q0b0s0
00000101100
MICRON JEDEC ID
CODE (11:1)
ID Register Presence
Indicator (0)
1
DESCRIPTION
Revision number.
def = 010 for 36Mb density
def = 001 for 18Mb density
wx = 11 for x36 width
wx = 10 for x18 width
wx = 01 for x8 width
t = 1 for DLL version
t = 0 for non-DLL version
q = 1 for QDR
q = 0 for DDR
b = 1 for 4-word burst
b = 0 for 2-word burst
s = 1 for separate I/O
s = 0 for common I/O
Allows unique identification of SRAM vendor.
Indicates the presence of an ID register.
Table 18: Scan Register Size
REGISTER NAME
BIT SIZE
3
1
32
107
Instruction
Bypass
ID
Boundary Scan
Table 19: Instruction Codes
INSTRUCTION
CODE
EXTEST
000
IDCODE
001
SAMPLE Z
010
RESERVED
SAMPLE/
PRELOAD
011
100
RESERVED
RESERVED
BYPASS
101
110
111
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
DESCRIPTION
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces
all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction does not implement 1149.1 preload function and is therefore not 1149.1compliant.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Table 20: Boundary Scan (Exit) Order
BIT#
FBGA BALL
BIT#
FBGA BALL
BIT#
FBGA BALL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
6R
6P
6N
7P
7N
7R
8R
8P
9R
11P
10P
10N
9P
10M
11N
9M
9N
11L
11M
9L
10L
11K
10K
9J
9K
10J
11J
11H
10G
9G
11F
11G
9F
10F
11E
10E
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
10D
9E
10C
11D
9C
9D
11B
11C
9B
10B
11A
10A
9A
8B
7C
6C
8A
7A
7B
6B
6A
5B
5A
4A
5C
4B
3A
2A
1A
2B
3B
1C
1B
3D
3C
1D
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
2C
3E
2D
2E
1E
2F
3F
1G
1F
3G
2G
1J
2J
3K
3J
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
2N
2P
1P
3R
4R
4P
5P
5N
5R
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Figure 11:
165-Ball FBGA
0.85 ±0.075
0.12 C
SEATING PLANE
C
BALL A11
165X Ø 0.45
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
10.00
BALL A1
PIN A1 ID
1.00
TYP
1.20 MAX
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
6.50 ±0.05
SUBSTRATE: PLASTIC LAMINATE
5.00 ±0.05
SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
NOTE:
1. All dimensions are in millimeters.
Data Sheet Designation
No Marking: This data sheet contains minimum and maximum limits specified over the complete power
supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
27
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
2 MEG X 8, 1 MEG X 18, 512K X 36
1.8V VDD, HSTL, DDRIIb4 SRAM
Document Revision History
Rev. H, Pub 3/03 ..............................................................................................................................................................3/03
• Updated JTAG Section
• Removed Preliminary Status
Rev. G, Pub 2/03...............................................................................................................................................................2/03
• Added definitive notes to Figure 3
• Added definitive note to Table 9
• Added definitive note concerning bit# 64 to Table 19
• Removed Errata specifications
• Updated AC timing values with new codevelopment values
• Updated JTAG description to reflect 1149.1 specification compliance with EXTEST feature
• Added definitive note concerning SRAM (DQ) I/O balls used for JTAG DC values and timing
• Changed process information in header to die revision indicator
• Updated Thermal Resistance Values to Table 12:
CI = 4.5 TYP; 5.5 MAX
CO = 6 TYP; 7 MAX
CCK = 5.5 TYP; 6.5 MAX
• Updated Thermal Resistance values to Table 12:
JA = 19.4 TYP
JC = 1.0 TYP
JB = 9.6 TYP
• Added TJ £ +95°C to Table 13
•
•
•
•
•
•
Modified Figure 2 regarding depth, configuration, and byte controls
Added definitive notes regarding I/O behavior during JTAG operation
Added definitive notes regarding IDD test conditions for read to write ratio
Removed note regarding AC derating information for full I/O range
Remove references to JTAG scan chain logic levels being at logic zero for NC pins in Tables 5 and 19
Revised ball description for NC balls:
These balls are internally connected to the die, but have no function and may be left not connected to the
board to minimize ball count.
Rev. 6, Pub 9/02 ...............................................................................................................................................................9/02
• Reverted data sheet to PRELIMINARY designation
Rev. 5, Pub 9/02 ...............................................................................................................................................................9/02
• Added new Output Times values
• Added Errata to back of data sheet
• Removed ADVANCE designation
• Removed TJ references
Rev. 4, Pub 8/02, ADVANCE........................................................................................................................................8/02
• Update format
Rev. 3, Pub. 12/01, ADVANCE...................................................................................................................................12/01
• Changed AC Timing
Rev. 2, Pub. 11/01, ADVANCE...................................................................................................................................11/01
• New ADVANCE data sheet
18Mb: 1.8V VDD, HSTL, DDRIIb4 SRAM
MT57W1MH18J_H.fm – Rev. H, Pub. 3/03
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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