4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
4Mb SYNCBURST™
SRAM
MT58L256L18P1, MT58L128L32P1,
MT58L128L36P1; MT58L256V18P1,
MT58L128V32P1, MT58L128V36P1
3.3V VDD, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
FEATURES
100-PIN TQFP1
• Fast clock and OE# access times
• Single +3.3V +0.3V/-0.165V power supply (VDD)
• Separate +3.3V or +2.5V isolated output buffer
supply (VDDQ)
• SNOOZE MODE for reduced-power standby
• Single-cycle deselect (Pentium® BSRAM-compatible)
• Common data inputs and data outputs
• Individual BYTE WRITE control and GLOBAL WRITE
• Three chip enables for simple depth expansion
and address pipelining
• Clock-controlled and registered addresses, data
I/Os and control signals
• Internally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down for portable applications
• 165-pin FBGA package
• 100-pin TQFP package
• Low capacitive bus loading
• x18, x32, and x36 versions available
OPTIONS
165-BALL FBGA
MARKING
• Timing (Access/Cycle/MHz)
2.6ns/4.4ns/225 MHz
2.8ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
• Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
• Packages
100-pin TQFP
165-pin FBGA
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)**
-4.4
-5
-6
-7.5
-10
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
MT58L256L18P1
MT58L128L32P1
MT58L128L36P1
* A Part Marking Guide for the FBGA devices can be found on Micron’s
Web site—http://www.micron.com/support/index.html.
** Industrial temperature range offered in specific speed grades and
configurations. Contact factory for more information.
MT58L256V18P1
MT58L128V32P1
MT58L128V36P1
GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs
high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a
256K x 18, 128K x 32, or 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
T
F*
None
IT
Part Number Example:
MT58L256L18P1T-6
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
1
©2003, Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FUNCTIONAL BLOCK DIAGRAM
256K x 18
18
SA0, SA1, SA
16
18
ADDRESS
REGISTER
2
MODE
SA0, SA1
SA1'
BINARY Q1
COUNTER AND
LOGIC
CLR
Q0
ADV#
CLK
18
SA0'
ADSC#
ADSP#
BYTE “b”
WRITE REGISTER
BWb#
9
9
BYTE “a”
WRITE REGISTER
BWa#
BYTE “b”
WRITE DRIVER
BYTE “a”
WRITE DRIVER
9
256K x 9 x 2
MEMORY
ARRAY
18
OUTPUT 18
REGISTERS
SENSE 18
AMPS
OUTPUT
BUFFERS
18
E
9
DQs
DQPa
DQPb
BWE#
GW#
INPUT
REGISTERS
18
ENABLE
REGISTER
CE#
CE2
CE2#
PIPELINED
ENABLE
2
OE#
FUNCTIONAL BLOCK DIAGRAM
128K x 32/36
17
ADDRESS
REGISTER
SA0, SA1, SA
15
17
17
SA0, SA1
MODE
SA1'
Q1
BINARY
COUNTER
SA0'
CLR
Q0
ADV#
CLK
ADSC#
ADSP#
BWd#
BYTE “d”
WRITE REGISTER
9
BYTE “d”
WRITE DRIVER
9
BWc#
BYTE “c”
WRITE REGISTER
9
BYTE “c”
WRITE DRIVER
9
128K x 9 x 4
(x36)
BWb#
BYTE “b”
WRITE REGISTER
9
BYTE “b”
WRITE DRIVER
9
BYTE “a”
WRITE REGISTER
9
BYTE “a”
WRITE DRIVER
9
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
ENABLE
REGISTER
128K x 8 x 4
(x32)
36
SENSE
AMPS
36
OUTPUT
REGISTERS 36
MEMORY
ARRAY
OUTPUT
BUFFERS
E
DQs
DQPa
36
DQPd
36
PIPELINED
ENABLE
INPUT
REGISTERS
4
NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams
for detailed information.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
GENERAL DESCRIPTION (continued)
pins and DQPb. During WRITE cycles on the x32 and
x36 devices, BWa# controls DQa pins and DQPa; BWb#
controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. GW#
LOW causes all bytes to be written. Parity bits are only
available on the x18 and x36 versions.
This device incorporates a single-cycle deselect feature during READ cycles. If the device is immediately
deselected after a READ cycle, the output bus goes to a
High-Z state tKQHZ nanoseconds after the rising edge
of clock.
Micron’s 4Mb SyncBurst SRAMs operate from a +3.3V
VDD power supply, and all inputs and outputs are TTLcompatible. Users can choose either a 3.3V or 2.5V I/O
version. The device is ideally suited for Pentium and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is
also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bitwide applications.
Please refer to Micron’s Web site (www.micron.com/
sramds) for the latest data sheet.
(CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is
also a burst mode input (MODE) that selects between
interleaved and linear burst modes. The data-out (Q),
enabled by OE#, is also asynchronous. WRITE cycles
can be from one to two bytes wide (x18) or from one to
four bytes wide (x32/x36), as controlled by the write
control inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be
internally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During WRITE cycles on the x18 device,
BWa# controls DQa pins and DQPa; BWb# controls DQb
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN ASSIGNMENT TABLE
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
x18
NC
NC
NC
x32/x36
NC/DQPc*
DQc
DQc
VDDQ
VSS
NC
DQc
NC
DQc
DQb
DQc
DQb
DQc
VSS
VDDQ
DQb
DQc
DQb
DQc
VDD
VDD
NC
VSS
DQb
DQd
DQb
DQd
VDDQ
VSS
DQb
DQd
DQb
DQd
DQPb
DQd
NC
DQd
PIN #
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
x18
x32/x36
VSS
VDDQ
NC
DQd
NC
DQd
NC
NC/DQPd*
MODE
SA
SA
SA
SA
SA1
SA0
DNU
DNU
VSS
VDD
NF**
NF**
SA
SA
SA
SA
SA
SA
SA
PIN #
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
x18
NC
NC
NC
x32/x36
NC/DQPa*
DQa
DQa
VDDQ
VSS
NC
DQa
NC
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
ZZ
VDD
NC
VSS
DQa
DQb
DQa
DQb
VDDQ
VSS
DQa
DQb
DQa
DQb
DQPa
DQb
NC
DQb
PIN #
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
x18
NC
NC
SA
NC
NC
x32/x36
VSS
VDDQ
DQb
DQb
NC/DQPb*
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
SA
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
SA
ADV#
ADSP#
ADSC#
OE#
BWE#
GW#
CLK
VSS
VDD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
50
81
49
82
48
83
47
84
46
85
45
86
44
87
43
88
42
89
41
90
40
91
39
92
38
93
37
94
36
95
35
96
34
97
33
98
32
99
31
100
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/DQPb*
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC/DQPa*
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
VDD
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
x18
SA
SA
SA
SA
SA
SA
SA
NF**
NF**
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
NC/DQPc*
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
VDD
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC/DQPd*
x32/x36
SA
SA
SA
SA
SA
SA
SA
NF**
NF**
VDD
VSS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
**Pins 43 and 42 are reserved for address expansion, 8Mb and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS
x18
x32/x36
37
37
36
36
32–35, 44–50, 32–35, 44–50,
80–82, 99,
81, 82, 99,
100
100
SYMBOL
TYPE
SA0
SA1
SA
Input
Synchronous Address Inputs: These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK.
DESCRIPTION
93
94
–
–
93
94
95
96
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
87
87
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
88
88
GW#
Input
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
89
89
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
98
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
92
92
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
97
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
86
OE#
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
83
83
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on this pin effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge
of the first clock after an ADSP# cycle is initiated.
84
84
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36
85
85
ADSC#
Input Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to
be registered. A READ or WRITE is performed using the new
address if CE# is LOW. ADSC# is also used to place the chip into
power-down state when CE# is HIGH.
31
31
MODE
Input Mode: This input selects the burst sequence. A LOW on this pin
selects “linear burst.” NC or HIGH on this pin selects “interleaved
burst.” Do not alter input state while device is operating.
64
64
ZZ
Input Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in
the memory array is retained. When ZZ is active, all other inputs
are ignored.
(a) 58, 59,
(a) 52, 53,
62, 63, 68, 69, 56–59, 62, 63
72, 73
(b) 8, 9, 12,
(b) 68, 69
13, 18, 19, 22, 72–75, 78, 79
23
(c) 2, 3, 6-9,
12, 13
(d) 18, 19,
22–25, 28, 29
74
24
–
–
51
80
1
30
SYMBOL TYPE
DQa
DQb
DESCRIPTION
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte
Output “b” is DQb pins. For the x32 and x36 versions, Byte “a” is DQa
pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is
DQd pins. Input data must meet setup and hold times around
the rising edge of CLK.
DQc
DQd
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these pins are
No Connect (NC). On the x18 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is
DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d”
parity is DQPd.
14, 15, 41, 65, 14, 15, 41, 65,
91
91
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
4, 11, 20, 27, 4, 11, 20, 27,
54, 61, 70, 77 54, 61, 70, 77
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
and Operating Conditions for range.
5, 10, 17, 21, 5, 10, 17, 21,
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
VSS
Supply Ground: GND.
38, 39
38, 39
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1–3, 6, 7, 16,
25, 28–30,
51–53, 56, 57,
66, 75, 78, 79,
95, 96
16, 66
NC
–
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
dissipation.
42, 43
42, 43
NF
–
No Function: These pins are internally connected to the die and
have the capacitance of input pins. It is allowable to leave these
pins unconnected or driven by signals. Reserved for address
expansion; pin 43 becomes an SA at 8Mb density and pin 42
becomes an SA at 16Mb density.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
x18
x32/x36
10
11
BWE# ADSC# ADV#
SA
SA
GW# OE# (G#) ADSP#
SA
NC
VSS
VSS
VDDQ
NC
DQPa
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQa
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQb
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
NC
DQPb
NC
VDDQ
VSS
NC
NC
VSS
VSS
VDDQ
NC
NC
NC
NC
SA
SA
DNU
SA1
DNU
SA
SA
SA
NC
MODE
(LBO#)
NC
SA
SA
DNU
SA0
DNU
SA
SA
SA
SA
1
2
3
4
5
6
NC
SA
CE#
BWb#
NC
CE2#
NC
SA
CE2
NC
BWa#
CLK
NC
NC
VDDQ
VSS
VSS
VSS
NC
DQb
VDDQ
VDD
VSS
NC
DQb
VDDQ
VDD
NC
DQb
VDDQ
NC
DQb
VDD
7
8
9
A
A
B
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQb
DQb
VSS
NC
VDD
VSS
VSS
VSS
VDD
NC
NC
ZZ
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
DQd
DQd
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQa
DQa
NC/DQPd*
NC
VDDQ
VSS
NC
NC
VSS
VSS
VDDQ
NC
NC/DQPa*
NC
NC
SA
SA
DNU
SA1
DNU
SA
SA
SA
NC
MODE
(LBO#)
NC
SA
SA
DNU
SA0
DNU
SA
SA
SA
SA
NC/DQPc*
NC
VDDQ
VSS
VSS
VSS
DQc
DQc
VDDQ
VDD
VSS
DQc
DQc
VDDQ
VDD
DQc
DQc
VDDQ
DQc
DQc
VDD
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/DQPb*
CLK
M
N
P
NC
BWd# BWa#
L
M
N
VDDQ
CE2
K
L
M
VSS
SA
A
J
K
L
VSS
NC
9
H
J
K
NC
CE2#
8
G
H
J
SA
BWc# BWb#
7
F
G
H
GW# OE# (G#) ADSP#
CE#
6
E
F
G
NC
SA
5
D
E
F
SA
NC
4
C
D
E
BWE# ADSC# ADV#
3
B
C
D
11
2
A
B
C
10
1
N
P
R
P
R
R
TOP VIEW
TOP VIEW
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
NOTE: 1. Pins 11P, and 6N reserved for address pin expansion; 8Mb, and 16Mb respectively.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS
x18
x32/x36
6R
6R
6P
6P
2A, 2B, 3P,
2A, 2B, 3P,
3R, 4P, 4R,
3R, 4P, 4R,
8P, 8R, 9P, 9R, 8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11R 10P, 10R, 11R
SYMBOL
TYPE
SA0
SA1
SA
Input
Synchronous Address Inputs: These inputs are registered and
must meet the setup and hold times around the rising edge of
CLK.
DESCRIPTION
5B
4A
–
–
5B
5A
4A
4B
BWa#
BWb#
BWc#
BWd#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
individual bytes to be written and must meet the setup and hold
times around the rising edge of CLK. A byte write enable is LOW
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For
the x32 and x36 versions, BWa# controls DQas and DQPa; BWb#
controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. Parity is only available on the x18 and x36
versions.
7A
7A
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
7B
7B
GW#
Input
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
6B
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock’s rising
edge.
3A
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
6A
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
11H
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
3B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B
8B
OE#(G#)
Input
Output Enable: This active LOW, asynchronous input enables the
data I/O output drivers.
9A
9A
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of correct
address during a WRITE cycle, ADV# must be HIGH at the rising edge
of the first clock after an ADSP# cycle is initiated.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
9B
9B
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH.
8A
8A
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
1R
1R
MODE
(LB0#)
Input
Mode: This input selects the burst sequence. A LOW on this input
selects “linear burst.” NC or HIGH on this input selects “interleaved
burst.” Do not alter input state while device is operating.
(a) 10J, 10K, (a) 10J, 10K,
10L, 10M, 11D, 10L, 10M, 11J,
11E, 11F, 11G 11K, 11L, 11M
(b) 1J, 1K,
(b) 10D, 10E,
1L, 1M, 2D, 10F, 10G, 11D,
2E, 2F, 2G
11E, 11F, 11G
(c) 1D, 1E,
1F, 1G, 2D,
2E, 2F, 2G
(d) 1J, 1K, 1L,
1M, 2J, 2K,
2L, 2M
11C
1N
–
–
11N
11C
1C
1N
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
4G, 4H, 4J,
4G, 4H, 4J,
4K, 4L, 4M,
4K, 4L, 4M,
8D, 8E, 8F,
8D, 8E, 8F,
8G, 8H, 8J,
8G, 8H, 8J,
8K, 8L, 8M
8K, 8L, 8M
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
3C, 3D, 3E,
3F, 3G, 3J,
3K, 3L, 3M,
3N, 9C, 9D,
9E, 9F, 9G,
9J, 9K, 9L,
9M, 9N
DQa
DQb
DESCRIPTION
Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;
Output Byte “b” is associated with DQbs. For the x32 and x36 versions,
Byte “a” is associated with DQas; Byte “b” is associated with
DQbs; Byte “c” is associated with DQcs; Byte “d” is associated
with DQds. Input data must meet setup and hold times around
the rising edge of CLK.
DQc
DQd
NC/DQPa
NC/DQPb
NC/DQPc
NC/DQPd
NC/
I/O
No Connect/Parity Data I/Os: On the x32 version, these are No
Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte
“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;
Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is
DQPd.
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating
Conditions for range.
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics
and Operating Conditions for range.
(continued on next page)
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C,
5D, 5E 5F,
5D, 5E 5F,
5G, 5H, 5J,
5G, 5H, 5J,
5K, 5L, 5M,
5K, 5L, 5M,
6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,
6G, 6H, 6J,
6G, 6H, 6J,
6K, 6L, 6M,
6K, 6L, 6M,
7C, 7D, 7E,
7C, 7D, 7E,
7F, 7G, 7H,
7F, 7G, 7H,
7J, 7K, 7L,
7J, 7K, 7L,
7M, 7N, 8C, 8N 7M, 7N, 8C, 8N
VSS
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R
DNU
–
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
NC
–
No Connect: These signals are not internally connected and
may be connected to ground to improve package heat
dissipation. Pins 11P, and 6N reserved for address pin
expansion; 8Mb, and 16Mb respectively.
1A, 1B, 1C,
1D, 1E, 1F,
1G, 1P, 2C,
2J, 2K,
2L, 2M, 2N,
2P, 2R, 3H,
4B, 5A, 5N,
6N, 9H, 10C,
10D, 10E, 10F,
10G, 10H,
10N, 11B,
11J, 11K,
11L, 11M,
11N, 11P
1A, 1B, 1P,
2C, 2N,
2P, 2R, 3H,
5N, 6N,
9H, 10C,
10H, 10N,
11A, 11B,
11P
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
Supply Ground: GND.
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
GW#
BWE#
BWa#
BWb#
READ
H
H
X
X
READ
H
L
H
H
WRITE Byte “a”
H
L
L
H
WRITE Byte “b”
H
L
H
L
WRITE All Bytes
H
L
L
L
WRITE All Bytes
L
X
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
GW#
BWE#
BWa#
BWb#
BWc#
BWd#
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte “a”
H
L
L
H
H
H
WRITE All Bytes
H
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TRUTH TABLE
OPERATION
ADDRESS
USED
CE# CE2# CE2
DESELECT Cycle, Power-Down
None
H
X
X
DESELECT Cycle, Power-Down
None
L
X
L
ZZ
L
L
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
None
None
ADSP# ADSC# ADV# WRITE# OE#
X
L
X
X
X
L
X
X
X
X
CLK
L-H
L-H
DQ
High-Z
High-Z
L
L
H
X
X
L
L
L
L
H
X
L
X
X
X
X
X
X
L-H
L-H
High-Z
High-Z
DESELECT Cycle, Power-Down
None
SNOOZE MODE, Power-Down
None
READ Cycle, Begin Burst
External
L
X
L
H
X
L
X
X
H
L
H
L
H
X
L
L
X
X
X
X
X
X
X
X
X
X
L
L-H
X
L-H
High-Z
High-Z
Q
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
External
External
External
L
L
L
L
L
L
H
H
H
L
L
L
L
H
H
X
L
L
X
X
X
X
L
H
H
X
L
L-H
L-H
L-H
High-Z
D
Q
READ Cycle, Begin Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
External
Next
Next
L
X
X
L
X
X
H
X
X
L
L
L
H
H
H
L
H
H
X
L
L
H
H
H
H
L
H
L-H
L-H
L-H
High-Z
Q
High-Z
READ Cycle, Continue Burst
READ Cycle, Continue Burst
Next
Next
H
H
X
X
X
X
L
L
X
X
H
H
L
L
H
H
L
H
L-H
L-H
Q
High-Z
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
Next
Next
Current
X
H
X
X
X
X
X
X
X
L
L
L
H
X
H
H
H
H
L
L
H
L
L
H
X
X
L
L-H
L-H
L-H
D
D
Q
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
Current
Current
X
H
X
X
X
X
L
L
H
X
H
H
H
H
H
H
H
L
L-H
L-H
High-Z
Q
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
Current
Current
Current
H
X
H
X
X
X
X
X
X
L
L
L
X
H
X
H
H
H
H
H
H
H
L
L
H
X
X
L-H
L-H
L-H
High-Z
D
D
NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s
and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH
throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Maximum junction temperature depends upon
package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14
for more information.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply
Relative to VSS .................................... -0.5V to +4.6V
Voltage on VDDQ Supply
Relative to VSS .................................... -0.5V to +4.6V
VIN -0.5V to VDDQ + 0.5V
Storage Temperature (plastic) ........... -55°C to +150°C
Junction Temperature** ..................................... +150°C
Short Circuit Output Current .............................. 100mA
3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Input Leakage Current
Output Leakage Current
Output High Voltage
Output Low Voltage
Supply Voltage
Isolated Output Buffer Supply
CONDITIONS
0V ≤ VIN ≤ VDD
Output(s) disabled,
0V ≤ VIN ≤ VDD
IOH = -4.0mA
IOL = 8.0mA
SYMBOL
VIH
MIN
2.0
MAX
VDD + 0.3
UNITS
V
NOTES
1, 2
VIL
ILI
ILO
-0.3
-1.0
0.8
1.0
V
µA
1, 2
3
-1.0
1.0
µA
VOH
VOL
VDD
VDDQ
2.4
–
3.135
–
0.4
3.6
V
V
V
1, 4
1, 4
1
3.135
3.6
V
1, 5
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH ≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA
Undershoot: VIL ≥ -0.7V for t ≤ tKC/2 for I ≤ 20mA
Power-up:
VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
14
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP CAPACITANCE
DESCRIPTION
Control Input Capacitance
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
TA = 25°C; f = 1 MHz;
CI
3
4
pF
1
VDD = 3.3V
CO
4
5
pF
1
Address Capacitance
CA
3
3.5
pF
1
Clock Capacitance
C CK
3
3.5
pF
1
Input/Output Capacitance (DQ)
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
Address/Control Input Capacitance
Output Capacitance (Q)
TA = 25°C; f = 1 MHz
Clock Capacitance
SYMBOL
TYP
MAX
UNITS
NOTES
CI
2.5
3.5
pF
1, 2
CO
4
5
pF
1, 2
CCK
2.5
3.5
pF
1, 2
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
15
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Data bus (DQx)
Inputs
VIHQ
VIH
1.7
1.7
VDDQ + 0.3
VDD + 0.3
V
V
1, 2
1, 2
Input Low (Logic 0) Voltage
VIL
-0.3
0.7
V
1, 2
Input Leakage Current
0V ≤ VIN ≤ VDD
ILI
-1.0
1.0
µA
3
Output Leakage Current
Output(s) disabled,
0V ≤ VIN ≤ VDDQ (DQx)
ILO
-1.0
1.0
µA
Output High Voltage
IOH = -2.0mA
IOH = -1.0mA
VOH
VOH
1.7
2.0
–
–
V
V
1, 4
1, 4
Output Low Voltage
IOL = 2.0mA
IOL = 1.0mA
VOL
VOL
–
–
0.7
0.4
V
V
1, 4
1, 4
VDD
3.135
3.6
V
1
VDDQ
2.375
2.9
V
1
Supply Voltage
Isolated Output Buffer Supply
NOTE: 1. All voltages referenced to VSS (GND).
2. Overshoot:
VIH ≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA
Undershoot: VIL ≥ -0.7V for t ≤ tKC/2 for I ≤ 20mA
Power-up:
VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms
3. MODE has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
16
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©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
TQFP THERMAL RESISTANCE
DESCRIPTION
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Top of Case)
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
46
°C/W
1
θJC
2.8
°C/W
1
FBGA THERMAL RESISTANCE
DESCRIPTION
Junction to Ambient
(Airflow of 1m/s)
Junction to Case (Top)
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Test conditions follow standard test methods
and procedures for measuring thermal
impedance, per EIA/JESD51.
θJA
40
°C/W
1, 2
θJC
9
°C/W
1, 2
θJB
17
°C/W
1, 2
Junction to Pins
(Bottom)
NOTE: 1. This parameter is sampled.
2. Preliminary package data.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
17
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
MAX
DESCRIPTION
CONDITIONS
Power Supply
Current:
Operating
Device selected; All inputs ≤ VIL
or ≥ VIH; Cycle time ≥ tKC (MIN);
VDD = MAX; Outputs open
SYMB O L TYP -4.4 -5
Device selected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
VIH; All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
Cycle time ≥ tKC (MIN)
CMOS Standby
Device deselected; VDD = MAX;
All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
All inputs static; CLK frequency = 0
Power Supply
Current: Idle
TTL Standby
Clock Running
Device deselected; VDD = MAX;
All inputs ≤ VIL or ≥ VIH;
All inputs static; CLK frequency = 0
Device deselected; VDD = MAX;
ADSC#, ADSP#, GW#, BWx#, ADV# ≥
VIH; All inputs ≤ VSS + 0.2 or ≥ VDDQ - 0.2;
Cycle time ≥ tKC (MIN)
-6 -7.5 -10 UNITS NOTES
IDD
225 575 525 475 375 300
mA
2, 3, 4
IDD1
55 130 120 110 90
85
mA
2, 3, 4
ISB2
0.4 10
25
10
10
10
10
mA
3, 4
25
25
ISB3
8
25
25
mA
3, 4
ISB4
55 130 120 110 90
85
mA
3, 4
NOTE: 1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and
greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device
is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C, and 10ns cycle time.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
18
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C ≤ TA ≤ +70°C; VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
-4.4
-5
-6
-7.5
-10
SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS
tKC
4.4
fKF
tKH
tKL
1.7
1.7
tKQ
tKQX
tKQLZ
2.6
0
tOEHZ
tAS
tADSS
tAAS
tWS
tDS
tCES
tAH
tADSH
tAAH
tWH
tDH
tCEH
2.8
0
3.5
0
100
3.0
3.0
4.0
1.5
0
3.5
3.5
2.8
10
133
2.5
2.5
1.5
0
2.8
2.8
2.6
7.5
166
2.3
2.3
1.0
0
2.6
2.6
tOEQ
6.0
200
2.0
2.0
1
0
tKQHZ
tOELZ
5.0
225
5.0
1.5
1.5
4.2
4.2
0
3.5
5.0
5.0
0
4.2
4.5
NOTES
ns
MHz
ns
ns
2
2
ns
ns
ns
ns
ns
ns
ns
3
3, 4, 5, 6
3, 4, 5, 6
7
3, 4, 5, 6
3, 4, 5, 6
1
1
1
1
1.3
1.3
1.3
1.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
ns
ns
ns
8,
8,
8,
8,
9
9
9
9
1
1
1.3
1.3
1.5
1.5
1.5
1.5
2.0
2.0
ns
ns
8, 9
8, 9
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8,
8,
8,
8,
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
9
9
9
9
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) and
Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V) unless otherwise noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times.
A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup
and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
19
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
3.3V I/O AC TEST CONDITIONS
2.5V I/O AC TEST CONDITIONS
Input pulse levels ................. VIH = (VDD/2.2) + 1.5V
Input pulse levels ............. VIH = (VDD/2.64) + 1.25V
.................... VIL = (VDD/2.2) - 1.5V
................ VIL = (VDD/2.64) - 1.25V
Input rise and fall times ..................................... 1ns
Input rise and fall times ..................................... 1ns
Input timing reference levels ..................... VDD/2.2
Input timing reference levels ................... VDD/2.64
Output reference levels ............................ VDDQ/2.2
Output reference levels ............................... VDDQ/2
Output load ............................. See Figures 1 and 2
Output load ............................. See Figures 3 and 4
3.3V I/O Output Load Equivalents
2.5V I/O Output Load Equivalents
Q
Q
Z O= 50Ω
Z O= 50Ω
50Ω
50Ω
VT = 1.25V
VT = 1.5V
Figure 1
Figure 3
+2.5V
+3.3V
225Ω
317
Q
Q
5pF
351
5pF
225Ω
Figure 2
Figure 4
LOAD DERATING CURVES
Micron 256K x 18, 128K x 32, and 128K x 36 SyncBurst
SRAM timing is dependent upon the capacitive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
20
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
SNOOZE MODE
ZZ is an asynchronous, active HIGH input that
causes the device to enter SNOOZE MODE. When ZZ
becomes a logic HIGH, ISB2Z is guaranteed after the
setup time tZZ is met. Any READ or WRITE operation
pending when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pending operations are completed.
SNOOZE MODE is a low-current, “power-down”
mode in which the device is deselected and current is
reduced to ISB2Z. The duration of SNOOZE MODE is
dictated by the length of time ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
Current during SNOOZE MODE
CONDITIONS
SYMBOL
ZZ ≥ VIH
ZZ active to input ignored
MAX
UNITS
ISB2Z
10
mA
tZZ
2(tKC)
ns
1
ns
1
ns
1
ns
1
ZZ inactive to input sampled
tRZZ
ZZ active to snooze current
tZZI
tRZZI
ZZ inactive to exit snooze current
MIN
2(tKC)
2(tKC)
0
NOTES
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
CLK
t ZZ
ZZ
I
t RZZ
t ZZI
SUPPLY
I ISB2Z
t RZZI
ALL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
21
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ TIMING3
(READ timing parameters are contained on the following page.)
t KC
CLK
tKH
tKL
tADSS tADSH
ADSP#
tADSS
tADSH
ADSC#
tAS
ADDRESS
tAH
A1
A2
tWS
A3
Burst continued with
new base address.
tWH
GW#, BWE#,
BWa#-BWd#
tCES
Deselect
cycle.
tCEH
CE#
(NOTE 2)
tAAS
(NOTE 4)
tAAH
ADV#
ADV#
suspends
burst.
OE#
(NOTE 3)
t OEHZ
t KQLZ
Q
Q(A1)
High-Z
tOEQ
tKQ
t OELZ
tKQX
Q(A2)
t KQHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t KQ
(NOTE 1)
Single READ
BURST READ
Burst wraps around
to its initial state.
DON’T CARE
UNDEFINED
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to
be driven until after the following clock rising edge.
4. Outputs are disabled within one clock cycle after deselect.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
22
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ TIMING PARAMETERS
-4.4
SYMBOL
tKC
MIN
-5
MAX
4.4
fKF
MIN
tKH
1.7
2.0
tKL
1.7
2.0
tKQ
2.6
1
1.0
tKQLZ
0
0
2.6
tOEQ
tOELZ
tAS
tWS
tCES
tAH
tADSH
tAAH
tWH
tCEH
fKF
tKH
2.3
2.5
ns
ns
ns
tKL
2.3
2.5
tKQX
1.5
1.5
1.5
ns
ns
tKQLZ
0
0
1.5
ns
ns
ns
tOEQ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAS
2.8
0
2.6
1
tADSS
tAAS
tKC
MHz
ns
2.8
2.6
0
tOEHZ
ns
200
2.8
tKQX
tKQHZ
UNITS
5.0
225
1
1
1
0.3
0.3
0.3
0.3
0.3
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2.8
1.3
1.3
1.3
1.3
1.3
0.5
0.5
0.5
0.5
0.5
SYMBOL
-6
-7.5
-10
MIN MAX MIN MAX MIN MAX UNITS
MAX
6.0
tKQ
tOEHZ
tADSS
tAAS
tWS
tCES
tAH
tADSH
tAAH
tWH
tCEH
23
3.0
5.0
5.0
4.2
0
3.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
3.0
4.2
3.5
5.0
0
4.2
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
ns
100
4.0
3.5
0
10
133
3.5
tKQHZ
tOELZ
7.5
166
4.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING
(WRITE timing parameters are contained on the following page.)
t KC
CLK
tKH
tKL
tADSS tADSH
ADSP#
ADSC# extends burst.
tADSS tADSH
tADSS tADSH
ADSC#
tAS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP# initiates burst.
BWE#,
BWa#-BWd#
tWS
tWS
tWH
tWH
(NOTE 5)
GW#
tCES
tCEH
CE#
(NOTE 2)
tAAS tAAH
ADV#
ADV# suspends burst.
(NOTE 4)
OE#
(NOTE 3)
tDS
D
tDH
D(A1)
High-Z
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
tOEHZ
(NOTE 1)
Q
BURST READ
Single WRITE
BURST WRITE
Extended BURST WRITE
DON’T CARE
UNDEFINED
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output
data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW#
HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
WRITE TIMING PARAMETERS
-4.4
SYMBOL
tKC
MIN
-5
MAX
4.4
fKF
MIN
-6
MAX
UNITS
200
MHz
ns
5.0
225
tKH
1.7
2.0
tKL
1.7
2.0
SYMBOL
tKC
fKF
ns
-7.5
-10
MIN MAX MIN MAX MIN MAX UNITS
6.0
7.5
10
ns
166
133
100
MHz
tKH
2.3
2.5
3.0
tKL
2.3
2.5
3.0
ns
tAS
1
1.3
ns
ns
ns
tADSS
1
1
1.3
1.3
ns
ns
tADSS
1.5
1.5
1.5
1.5
2.0
2.0
ns
ns
ns
tAAS
1.5
1.5
2.0
ns
1
1
1
1.3
1.3
1.3
ns
ns
ns
tWS
1.5
1.5
2.0
ns
tDS
0.3
0.3
0.3
0.3
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
tAH
1.5
1.5
0.5
1.5
1.5
0.5
2.0
2.0
0.5
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
tOEHZ
tAAS
tWS
tDS
tCES
tAH
tADSH
tAAH
tWH
tDH
tCEH
2.6
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
2.8
tOEHZ
tAS
tCES
tADSH
tAAH
tWH
tDH
tCEH
25
3.5
4.2
ns
4.5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ/WRITE TIMING6
(READ/WRITE timing parameters are contained on the following page.)
tKC
CLK
tKL
tKH
tADSS
tADSH
ADSP#
ADSC#
tAS
ADDRESS
BWE#,
BWa#-BWd#
(NOTE 4)
A1
tAH
A2
tCES
A3
tWS
tWH
tDS
tDH
A4
A5
A6
D(A5)
D(A6)
tCEH
CE#
(NOTE 2)
ADV#
OE#
tKQ
D
tOELZ
High-Z
tKQLZ
Q
High-Z
Q(A1)
Back-to-Back READs
(NOTE 5)
tOEHZ
D(A3)
(NOTE 1)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
Back-to-Back
WRITEs
DON’T CARE
UNDEFINED
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE#
is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
READ/WRITE TIMING PARAMETERS
-4.4
SYMBOL
tKC
MIN
-5
MAX
4.4
fKF
MIN
tKH
1.7
2.0
tKL
1.7
2.0
tKQ
2.6
0
0
tOELZ
0
0
tAS
tADSS
tWS
tDS
tCES
tAH
tADSH
tWH
tDH
tCEH
ns
tKC
200
MHz
ns
fKF
tKH
2.3
2.5
ns
ns
ns
tKL
2.3
2.5
tKQLZ
0
0
ns
ns
tOELZ
0
0
2.8
tKQLZ
tOEHZ
UNITS
5.0
225
2.6
2.8
SYMBOL
6.0
ns
ns
ns
tAS
1
1
0.3
0.3
0.3
0.3
0.3
1.3
1.3
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
tDS
tADSS
tWS
tCES
tAH
tADSH
tWH
tDH
tCEH
27
10
133
3.5
tOEHZ
1.3
1.3
1.3
7.5
166
tKQ
1
1
1
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
-6
-7.5
-10
MIN MAX MIN MAX MIN MAX UNITS
MAX
3.0
3.0
4.0
3.5
ns
100
5.0
1.5
0
4.2
4.5
MHz
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
ns
ns
ns
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
100-PIN PLASTIC TQFP (JEDEC LQFP)
+0.10
22.10
-0.20
20.10 ±0.10
0.65 TYP
0.32
+0.06
-0.10
0.625
SEE DETAIL A
14.00 ±0.10
16.00 ±0.20
PIN #1 ID
0.15
+0.03
-0.02
1.40 ±0.05
GAGE PLANE
1.60 MAX
0.10
0.10
+0.10
-0.05
0.60 ±0.15
1.00 TYP
0.25
DETAIL A
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
28
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
165-PIN FBGA
0.85 ±0.075
0.12 C
SEATING PLANE
C
BALL A11
165X Ø 0.45
SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40
10.00
BALL A1
PIN A1 ID
1.00
TYP
1.20 MAX
PIN A1 ID
7.50 ±0.05
14.00
15.00 ±0.10
7.00 ±0.05
1.00
TYP
MOLD COMPOUND: EPOXY NOVOLAC
6.50 ±0.05
SUBSTRATE: PLASTIC LAMINATE
5.00 ±0.05
SOLDER BALL MATERIAL:
EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm
13.00 ±0.10
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
DATA SHEET DESIGNATIONS
No Marking: This data sheet contains minimum and maximum limits specified over the complete power supply
and temperature range for production devices. Although considered final, these specifications are
subject to change, as further product development and data characterization sometimes occur.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron, the Micron logo, M logo, and SyncBurst are trademarks and/or service marks of Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
29
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
REVISION HISTORY
Updated package drawings ................................................................................................................................... January 9/03
Removed "Preliminary Package Data" from front page .............................................................................. February 22/02
Removed -4 speed grade
Removed 119-pin PBGA package and references .......................................................................................... February 2/02
Removed note "Not Recommended for New Designs," Rev. 6/01 ...................................................................... June 7/01
Added Industrial Temperature note and reference, Rev. 3/01 ........................................................................ March 6/01
Added 119-pin PBGA package, Rev. 1/01, FINAL ........................................................................................... January 10/01
Removed FBGA Part Marking Guide, REV 8/00-A, FINAL .............................................................................. August 22/00
Changed FBGA capacitance values, REV 8/00, FINAL ....................................................................................... August 7/00
CI; TYP 2.5pF from 4pF; MAX. 3.5pF from 5pF
CO; TYP 4pF from 6pF; MAX. 5pF from 7pF
CCK; TYP 2.5pF from 5pF; MAX. 3.5pF from 6pF
Added FBGA Part Marking Guide, Rev. 7/00, Preliminary .................................................................................. June 13/00
Added FBGA Part Marking References
Removed 119-Pin PBGA package and references
Removed industrial temperature references
Added 165-pin FBGA package, Rev. 6/00, Preliminary ........................................................................................ May 23/00
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_F.p65 – Rev. F, Pub. 1/03 EN
30
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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