MT58L256L32DS-7.5

8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 8Mb SYNCBURST™ SRAM MT58L512L18D, MT58L256L32D, MT58L256L36D 3.3V VDD, 3.3V I/O, Pipelined, DoubleCycle Deselect FEATURES • • • • • • • • • • • • • • • Fast clock and OE# access times Single +3.3V +0.3V/-0.165V power supply (VDD) Separate +3.3V isolated output buffer supply (VDDQ) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-pin TQFP package 165-pin FBGA package Low capacitive bus loading x18, x32, and x36 versions available OPTIONS 100-Pin TQFP** 165-Pin FBGA MARKING • Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz • Configurations 512K x 18 256K x 32 256K x 36 -6 -7.5 -10 MT58L512L18D MT58L256L32D MT58L256L36D • Packages 100-pin TQFP (2-chip enable) 100-pin TQFP (3-chip enable) 165-pin, 13mm x 15mm FBGA • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C)** NOTE: 1. JEDEC-standard MS-026 BHA (LQFP). T S F* GENERAL DESCRIPTION The Micron® SyncBurst™ SRAM family employs highspeed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version. None IT Part Number Example MT58L512L18DT-7.5 * A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/support/index.html. ** Industrial temperature range offered in specific speed grades and configurations. Contact factory for more information. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 512K x 18 19 SA0, SA1, SA 17 19 ADDRESS REGISTER 2 MODE SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 ADV# CLK 19 SA0' ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE DRIVER 9 BYTE “a” WRITE REGISTER BWa# BYTE “b” WRITE DRIVER 9 9 512K x 9 x 2 MEMORY ARRAY OUTPUT 18 REGISTERS SENSE 18 AMPS 18 OUTPUT BUFFERS DQs DQPa DQPb 18 E 9 BWE# GW# INPUT REGISTERS 18 ENABLE REGISTER CE# CE2 CE2# PIPELINED ENABLE 2 OE# FUNCTIONAL BLOCK DIAGRAM 256K x 32/36 18 SA0, SA1, SA ADDRESS REGISTER 18 16 SA0-SA1 MODE SA1' Q1 BINARY COUNTER SA0' CLR Q0 ADV# CLK ADSC# ADSP# BWd# BYTE “d” WRITE REGISTER 9 BYTE “d” WRITE DRIVER 9 BWc# BYTE “c” WRITE REGISTER 9 BYTE “c” WRITE DRIVER 9 BYTE “b” WRITE REGISTER 9 BYTE “b” WRITE DRIVER 9 BYTE “a” WRITE REGISTER 9 BYTE “a” WRITE DRIVER 9 BWb# BWa# BWE# GW# CE# CE2 CE2# OE# ENABLE REGISTER 256K x 8 x 4 (x32) 256K x 9 x 4 (x36) 36 SENSE AMPS 36 OUTPUT REGISTERS 36 MEMORY ARRAY 36 PIPELINED ENABLE OUTPUT BUFFERS E DQs DQPa 36 DQPd INPUT REGISTERS 4 NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams for detailed information. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM GENERAL DESCRIPTION (continued) This device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTLcompatible. The device is ideally suited for Pentium® and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. Please refer to Micron’s Web site (www.micron.com/ sramds) for the latest data sheet. Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 TQFP PINOUTS At the time of the writing of this data sheet, there are two pinouts in the industry. Micron will support both pinouts for this part. 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x18 NC NC NC x32/x36 NF/DQPc* DQc DQc VDDQ VSS NC DQc NC DQc DQb DQc DQb DQc VSS VDDQ DQb DQc DQb DQc VDD VDD NC VSS DQb DQd DQb DQd VDDQ VSS DQb DQd DQb DQd DQPb DQd NC DQd PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NF/DQPd* MODE SA SA SA SA SA1 SA0 DNU DNU VSS VDD NF NF (T Version) SA (S Version) SA SA SA SA SA SA SA PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x18 NC NC NC x32/x36 NF/DQPa* DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x18 x32/x36 VSS VDDQ NC DQb NC DQb SA NF/DQPb* SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA (T Version) CE2# (S Version) BWa# BWb# NC BWc# NC BWd# CE2 CE# SA SA *No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC Pin Assignment (Top View) 100-Pin TQFP, 2-Chip Enable, T Version 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 SA SA SA SA SA SA SA NF NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE NF/DQPb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NF/DQPa* NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x32/x36 SA SA SA SA SA SA SA NF NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE NF/DQPc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NF/DQPd* SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA BWa# BWb# BWc# BWd# CE2 CE# SA SA *No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC Pin Assignment (Top View) 100-Pin TQFP, 3-Chip Enable, S Version 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC NC x18 SA SA SA SA SA SA SA SA NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE NF/DQPb* NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb NC DQb DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb VDD VSS VDD NC VDD NC ZZ VSS DQa DQb DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ DQa NC DQa NC NF/DQPa* SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x32/x36 SA SA SA SA SA SA SA SA NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE NF/DQPc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NF/DQPd* SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA *No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS x18 x32/x36 37 37 36 36 32-35, 44-50, 32-35, 44-50, 80-82, 99, 81, 82, 99, 100 100 92 (T Version) 92 (T Version) 43 (S Version) 43 (S Version) SYMBOL TYPE SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Two different pinouts are available for the TQFP package. DESCRIPTION 93 94 – – 93 94 95 96 BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. 87 87 BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. 88 88 GW# Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. 89 89 CLK Input Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. 98 98 CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 92 (S Version) 92 (S Version) CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. CE2# is only available on the S Version. 64 64 ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 97 97 CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 86 86 OE# Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. 83 83 ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS (CONTINUED) x18 x32/x36 SYMBOL TYPE DESCRIPTION 84 84 ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. 85 85 ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. 31 31 MODE Input Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or HIGH on this pin selects “interleaved burst.” Do not alter input state while device is operating. (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69 13, 18, 19, 22, 72-75, 78, 79 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 74 24 – – 51 80 1 30 DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b” Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NF/DQPa NF/DQPb NF/DQPc NF/DQPd 14, 15, 41, 65, 14, 15, 41, 65, 91 91 VDD 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 VDDQ 5, 10, 17, 21, 5, 10, 17, 21, 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 VSS NF/ I/O No Function/Parity Data I/Os: On the x32 version, these pins are No Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND. 38, 39 38, 39 DNU – Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. 1-3, 6, 7, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 16, 66 NC – No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. NF – No Function: These pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. On the S Version, pin 42 is reserved as an address upgrade pin for the 16Mb SyncBurst SRAM. 42 42 43 (T Version) 43 (T Version) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM PIN LAYOUT (Top View) 165-Pin FBGA x18 x32/x36 10 11 BWE# ADSC# ADV# SA SA GW# OE# (G#) ADSP# SA NC VSS VSS VDDQ NC DQPa VSS VSS VDD VDDQ NC DQa VSS VSS VSS VDD VDDQ NC DQa VDD VSS VSS VSS VDD VDDQ NC DQa VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQb NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC DQPb NC VDDQ VSS NC NC VSS VSS VDDQ NC NC NC NC SA SA DNU SA1 DNU SA SA SA SA MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA 1 2 3 4 5 6 NC SA CE# BWb# NC CE2# NC SA CE2 NC BWa# CLK NC NC VDDQ VSS VSS VSS NC DQb VDDQ VDD VSS NC DQb VDDQ VDD NC DQb VDDQ NC DQb VDD 7 8 9 A A B VSS VSS VDD VDDQ DQb DQb VSS VSS VSS VDD VDDQ DQb DQb VDD VSS VSS VSS VDD VDDQ DQb DQb VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa NF/DQPd NC VDDQ VSS NC NC VSS VSS VDDQ NC NF/DQPa NC NC SA SA DNU SA1 DNU SA SA SA SA MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA CE2 BWd# BWa# CLK NF/DQPc NC VDDQ VSS VSS VSS DQc DQc VDDQ VDD VSS DQc DQc VDDQ VDD DQc DQc VDDQ DQc DQc VDD B C D E F G H J K L M N P R NF/DQPb SA M N P NC NC A L M N VDDQ CE2# K L M VSS BWc# BWb# J K L VSS CE# 9 H J K NC SA 8 G H J SA NC 7 F G H GW# OE# (G#) ADSP# 6 E F G NC 5 D E F SA 4 C D E BWE# ADSC# ADV# 3 B C D 11 2 A B C 10 1 N P R P R R TOP VIEW TOP VIEW *No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version. NOTE: Pin 6N reserved for address pin expansion; 18Mb. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS x18 x32/x36 6R 6R 6P 6P 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, 10P, 10R, 11P, 11R 11R SYMBOL TYPE SA0 SA1 SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. DESCRIPTION 5B 4A – – 5B 5A 4A 4B BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For the x32 and x36 versions, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. Parity is only available on the x18 and x36 versions. 7A 7A BWE# Input Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. 7B 7B GW# Input Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. 6B 6B CLK Input Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. 3A 3A CE# Input Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. 6A 6A CE2# Input Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. 11H 11H ZZ Input Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. 3B 3B CE2 Input Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. 8B 8B OE#(G#) Input Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL TYPE 9A 9A ADV# Input Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. 9B 9B ADSP# Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. 8A 8A ADSC# Input Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. 1R 1R MODE (LB0#) Input Mode: This input selects the burst sequence. A LOW on this input selects “linear burst.” NC or HIGH on this input selects “interleaved burst.” Do not alter input state while device is operating. (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, 1L, 1M, 2D, 2E, 2F, 2G 11C 1N – – (b) 10D, 10E, 10F, 10G, 11D, 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M 11N 11C 1C 1N 1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F, 4G, 4H, 4J, 4G, 4H, 4J, 4K, 4L, 4M, 4K, 4L, 4M, 8D, 8E, 8F, 8D, 8E, 8F, 8G, 8H, 8J, 8G, 8H, 8J, 8K, 8L, 8M 8K, 8L, 8M DQa DQb DESCRIPTION Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas; Output Byte “b” is associated with DQbs. For the x32 and x36 versions, Byte “a” is associated with DQas; Byte “b” is associated with DQbs; Byte “c” is associated with DQcs; Byte “d” is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NF/DQPa NF/DQPb NF/DQPc NF/DQPd VDD NF/ I/O No Funciton/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd. Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N VDDQ TYPE DESCRIPTION Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. 2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 7N, 8C, 8N 7M, 7N, 8C, 8N VSS 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R DNU – Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. NC – No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. Pin 6N reserved for address pin expansion; 18Mb. NF I/O 1A, 1B, 1C, 1A, 1B, 1P, 1D, 1E, 1F, 2C, 2N, 1G, 1P, 2C, 2P, 2R, 3H, 2J, 2K, 5N, 6N, 2L, 2M, 2N, 9H, 10C, 2P, 2R, 3H, 10H, 10N, 4B, 5A, 5N, 11A, 11B, 6N, 9H, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 Supply Ground: GND. No Function: These pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X00 X...X11 X...X10 X...X10 X...X11 X...X00 X...X01 X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 X...X01 X...X10 X...X11 X...X00 X...X10 X...X11 X...X00 X...X01 X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) FUNCTION GW# BWE# BWa# BWb# READ H H X X READ H L H H WRITE Byte “a” H L L H WRITE Byte “b” H L H L WRITE All Bytes H L L L WRITE All Bytes L X X X PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36) FUNCTION GW# BWE# BWa# BWb# BWc# BWd# READ H H X X X X READ H L H H H H WRITE Byte “a” H L L H H H WRITE All Bytes H L L L L L WRITE All Bytes L X X X X X NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TRUTH TABLE OPERATION Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down ADDRESS USED None None None Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst CE# CE2# CE2 ZZ ADSP# ADSC# ADV# WRITE# OE# CLK DQ H L L X X H X L X L L L X L L L X X X X X X X X X X X L-H L-H L-H High-Z High-Z High-Z None None None External External L L X L L X H X L L L X X H H L L H L L H H X L L L L X X X X X X X X X X X X X X X X L H L-H L-H X L-H L-H High-Z High-Z High-Z Q High-Z WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst External External External Next L L L X L L L X H H H X L L L L H H H H L L L H X X X L L H H H X L H L L-H L-H L-H L-H D Q High-Z Q READ Cycle, Continue Burst READ Cycle, Continue Burst Next Next X H X X X X L L H X H H L L H H H L L-H L-H High-Z Q READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst Next Next Next H X H X X X X X X L L L X H X H H H L L L H L L H X X L-H L-H L-H High-Z D D READ Cycle, Suspend Burst READ Cycle, Suspend Burst Current Current X X X X X X L L H H H H H H H H L H L-H L-H Q High-Z READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Current Current Current Current H H X H X X X X X X X X L L L L X X H X H H H H H H H H H H L L L H X X L-H L-H L-H L-H Q High-Z D D NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM Junction Temperature** ............................................... +150°C Short Circuit Output Current ........................................ 100mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply ........................................................................... Relative to VSS -0.5V to +4.6V Voltage on VDDQ Supply ........................................................................... Relative to VSS -0.5V to +4.6V VIN (DQx) ............................................ -0.5V to VDDQ + 0.5V VIN (inputs) ............................................ -0.5V to VDD + 0.5V Storage Temperature (plastic) ....................... -55°C to +150°C Storage Temperature (FBGA) ....................... -55°C to +125°C DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage SYMBOL VIH MIN 2.0 MAX VDD + 0.3 UNITS V NOTES 1, 2 VIL ILI ILO -0.3 -1.0 -1.0 0.8 1.0 1.0 V µA µA 1, 2 3 VOH 2.4 – V 1, 4 VOL VDD VDDQ – 3.135 0.4 3.6 V V 1, 4 1 3.135 3.6 V 1, 5 CONDITIONS SYMBOL TYP MAX UNITS NOTES TA = 25°C; f = 1 MHz; CI 3 4 pF 6 VDD = 3.3V CO 4 5 pF 6 Address Capacitance CA 3 3.5 pF 6 Clock Capacitance CCK 3 3.5 pF 6 Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS 0V ≤ VIN ≤ VDD Output(s) disabled, 0V ≤ VIN ≤ VDD IOH = -4.0mA IOL = 8.0mA TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA Undershoot: VIL ≥ -0.7V for t ≤ tKC/2 for I ≤ 20mA Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms 3. MODE has an internal pull-up, and input leakage = ±10µA. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 6. This parameter is sampled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA CAPACITANCE DESCRIPTION CONDITIONS SYMBOL TYP MAX UNITS NOTES CI 2.5 3.5 pF 2 Address/Control Input Capacitance Output Capacitance (Q) TA = 25°C; f = 1 MHz Clock Capacitance CO 4 5 pF 2 CCK 2.5 3.5 pF 2 TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS SYMBOL TYP θJA 40 °C/W 1 θJC 8 °C/W 1 CONDITIONS SYMBOL TYP Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. θJA 40 °C/W 2 θJC 9 °C/W 2 θJB 17 °C/W 2 Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 1-layer UNITS NOTES FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) UNITS NOTES NOTE: 1. This parameter is sampled. 2. FBGA preliminary package data. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (0°C ≤ TA ≤ 70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) MAX DESCRIPTION CONDITIONS SYMBOL TYP -6 -7.5 -10 Power Supply Current: Operating Device selected; All inputs ≤ VIL or ≥ VIH; Cycle time ≥ tKC (MIN); VDD = MAX; Outputs open IDD 225 475 375 300 mA 1, 2, 3 Power Supply Current: Idle Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN) Device deselected; VDD = MAX; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; All inputs static; CLK frequency = 0 IDD1 55 110 90 85 mA 1, 2, 3 ISB2 0.4 10 10 10 mA 2, 3 ISB3 8 25 25 25 mA 2, 3 ISB4 55 110 90 85 mA 2, 3 CMOS Standby TTL Standby Clock Running Device deselected; VDD = MAX; All inputs ≤ VIL or ≥ VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN) UNITS NOTES NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25°C and 10ns cycle time. 4. This parameter is sampled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ TA ≤ 70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) -6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) SYMBOL MIN tKC 6.0 fKF tKH tKL tKQLZ 3.5 0 tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH 100 3.0 3.0 4.0 5.0 1.5 1.5 4.2 4.2 0 3.5 MAX 10 1.5 0 3.5 3.5 tOEHZ -10 MIN 133 2.5 2.5 1.5 0 tOEQ -7.5 MAX 7.5 2.3 2.3 tKQHZ tOELZ MIN 166 tKQ tKQX MAX 5.0 5.0 0 4.2 4.5 UNITS NOTES ns MHz ns ns 2 2 ns ns ns ns ns ns ns 3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 1.5 1.5 1.5 1.5 2.0 2.0 ns ns 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns 8, 9 8, 9 8, 9 8, 9 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 8, 9 8, 9 NOTE: 1. 2. 3. 4. 5. 6. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. Measured as HIGH above VIH and LOW below VIL. This parameter is measured with the output loading shown in Figure 2. This parameter is sampled. Transition is measured ±500mV from steady state voltage. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters. 7. OE# is a “Don’t Care” when a byte write enable is sampled LOW. 8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TEST CONDITIONS Q Z O= 50 Input pulse levels .................. VIH = (VDD/2.2) + 1.5V 50 .................... VIL = (VDD/2.2) - 1.5V VT = 1.5V Input rise and fall times ..................................... 1ns Figure 1 3.3V I/O OUTPUT LOAD EQUIVALENT Input timing reference levels ...................... VDD/2.2 Output reference levels ............................ VDDQ/2.2 Output load ............................. See Figures 1 and 2 +3.3V 317 LOAD DERATING CURVES Q Micron 512K x 18, 256K x 32, and 256K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 351 5pF Figure 2 3.3V I/O OUTPUT LOAD EQUIVALENT 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM SNOOZE MODE ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE CONDITIONS SYMBOL ZZ ≥ VIH ZZ active to input ignored MAX UNITS ISB2Z 10 mA tZZ 2(tKC) ns 1 ns 1 ns 1 ns 1 ZZ inactive to input sampled tRZZ ZZ active to snooze current tZZI tRZZI ZZ inactive to exit snooze current MIN 2(tKC) 2(tKC) 0 NOTES NOTE: 1. This parameter is sampled. SNOOZE MODE WAVEFORM CLK t ZZ ZZ I t RZZ t ZZI SUPPLY I ISB2Z t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM READ TIMING 3 tKC CLK tKL tKH tADSS tADSH ADSP# tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 tWS A3 Burst continued with new base address. tWH GW#, BWE#, BWa#-BWd# tCES Deselect (NOTE 4) cycle. tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst. OE# tOEQ tKQ t OELZ tKQX (NOTE 3) t KQLZ Q t OEHZ Q(A2) Q(A1) High-Z t KQHZ Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) t KQ Burst wraps around to its initial state. (NOTE 1) Single READ BURST READ DON’T CARE UNDEFINED READ TIMING PARAMETERS -6 SYMBOL tKC fKF MIN 6.0 tKH 2.3 2.3 tKL tKQLZ tOEHZ 2.5 2.5 1.5 0 tAS 1.5 1.5 2.0 tADSS 1.5 1.5 2.0 ns ns ns tAAS ns ns ns tCES 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 ns ns ns 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 5.0 5.0 ns ns tAAH tCEH 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns 4.5 ns ns 0.5 0.5 0.5 5.0 4.2 4.2 0 4.2 tWS tAH tADSH tWH MAX MIN -10 MIN 100 UNITS ns MHz -7.5 SYMBOL 1.5 1.5 0 3.5 -6 MAX 3.0 3.0 1.5 0 0 MIN 10 4.0 3.5 3.5 tOEQ -10 MAX 133 3.5 tKQHZ tOELZ MIN 7.5 166 tKQ tKQX -7.5 MAX MAX MIN MAX UNITS ns NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM WRITE TIMING t KC CLK tKH tKL tADSS tADSH ADSP# ADSC# extends burst. tADSS tADSH tADSS tADSH ADSC# tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP# initiates burst. tWS tWH BWE#, BWa#-BWd# (NOTE 5) tWS tWH GW# tCES tCEH CE# (NOTE 2) tAAS tAAH ADV# ADV# suspends burst. (NOTE 4) OE# (NOTE 3) tDS D tDH D(A2) D(A1) High-Z D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) tOEHZ (NOTE 1) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED WRITE TIMING PARAMETERS -6 SYMBOL tKC fKF MIN 6.0 tKH 2.3 2.3 tKL tADSS tAAS tWS MIN 7.5 166 tOEHZ tAS -7.5 MAX -10 MAX MIN 10 133 2.5 2.5 -6 MAX 100 3.0 3.0 UNITS ns MHz -7.5 MIN tDS 1.5 1.5 1.5 1.5 2.0 2.0 ns ns 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns tCES ns ns tAH tADSH MAX MIN -10 SYMBOL MAX MIN MAX UNITS 1.5 1.5 2.0 2.0 ns ns ns tAAH 1.5 1.5 tDH 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 1.5 1.5 1.5 1.5 2.0 2.0 ns ns tCEH 0.5 0.5 0.5 ns 3.5 4.2 4.5 tWH NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM READ/WRITE TIMING 3 tKC CLK tKL tKH tADSS tADSH ADSP# ADSC# tAS A1 ADDRESS tAH A3 A2 BWE#, BWa#-BWd# (NOTE 4) tCES A4 tWS tWH tDS tDH A5 A6 D(A5) D(A6) tCEH CE# (NOTE 2) ADV# OE# tKQ tOELZ D High-Z Q Q(A1) High-Z D(A3) tOEHZ tKQLZ Q(A2) Q(A4) Back-to-Back READs Single WRITE Q(A4+1) Q(A4+2) Q(A4+3) BURST READ Back-to-Back WRITEs (NOTE 5) DON’T CARE UNDEFINED READ/WRITE TIMING PARAMETERS -6 SYMBOL MIN tKC 6.0 fKF tKH tKL tOELZ MIN 133 3.5 4.0 MIN tADSS 100 ns MHz 1.5 1.5 1.5 1.5 2.0 2.0 ns ns tDS 5.0 ns ns ns 1.5 1.5 0.5 1.5 1.5 0.5 2.0 2.0 0.5 ns ns ns ns ns tADSH 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 4.2 ns ns tDH 0.5 0.5 0.5 0.5 0.5 0.5 ns ns 4.5 2.0 tWS tCES tAH tWH tCEH MAX MIN -10 SYMBOL 1.5 0 1.5 -7.5 UNITS 3.0 3.0 0 0 3.5 -6 MAX 10 2.5 2.5 0 0 1.5 -10 MAX 7.5 2.3 2.3 tOEHZ tAS MIN 166 tKQ tKQLZ -7.5 MAX MAX MIN MAX UNITS NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 ID 22.10 +0.10 -0.15 0.15 +0.03 -0.02 0.32 +0.06 -0.10 0.65 20.10 ±0.10 DETAIL A 0.62 1.50 ±0.10 0.10 14.00 ±0.10 16.00 +0.20 -0.05 0.25 0.10 +0.10 -0.05 GAGE PLANE 1.00 (TYP) 0.60 ±0.15 1.40 ±0.05 DETAIL A NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 165-PIN FBGA 0.85 ±0.075 0.12 C SEATING PLANE C BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 10.00 BALL A1 PIN A1 ID 1.00 TYP 1.20 MAX PIN A1 ID 7.50 ±0.05 14.00 15.00 ±0.10 7.00 ±0.05 1.00 TYP MOLD COMPOUND: EPOXY NOVOLAC 6.50 ±0.05 SUBSTRATE: PLASTIC LAMINATE 5.00 ±0.05 SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: Ø .33mm 13.00 ±0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark and the Micron logo and M logo are registered trademarks of Micron Technology, Inc. SyncBurst is a trademark of Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM REVISION HISTORY Removed "Preliminary Package Data" from front page ......................................................................... February 22/02 Removed 119-pin PBGA package and references .................................................................................. February 14/02 Removed note "Not Recommended for New Designs," Rev. 6/01 ................................................................. June 7/01 Added industrial temperature references and notes, Rev. 3/01 ................................................................ March 19/01 Changed 16Mb references to 18Mb Changed NC/DQPx to NF/DQPx Added 119-pin PBGA package, Rev. 1/01, FINAL .................................................................................... January 10/01 Added FBGA Part Marking Guide, Rev 7/00 ................................................................................................................... 7/18/00 Added Revision History Removed 119-Pin PBGA and References Removed Industrial Temperature References Added 165-pin FBGA Package .......................................................................................................................................... 6/13/00 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_D.p65 – Rev. 2/02 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2002, Micron Technology, Inc.