MT58L256L36D

8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 8Mb SYNCBURST™ SRAM FEATURES • • • • • • • • • • • • • • • Fast clock and OE# access times Single +3.3V +0.3V/-0.165V power supply (VDD) Separate +3.3V isolated output buffer supply (VDDQ) SNOOZE MODE for reduced-power standby Common data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-pin TQFP package 165-pin FBGA package Low capacitive bus loading x18, x32, and x36 versions available MT58L512L18D, MT58L256L32D, MT58L256L36D 3.3V VDD, 3.3V I/O, Pipelined, DoubleCycle Deselect 100-Pin TQFP* 165-Pin FBGA (Preliminary Package Data) OPTIONS • Timing (Access/Cycle/MHz) 3.5ns/6ns/166 MHz 4.0ns/7.5ns/133 MHz 5ns/10ns/100 MHz • Configurations 512K x 18 256K x 32 256K x 36 • Packages 100-pin TQFP (2-chip enable) 100-pin TQFP (3-chip enable) 165-pin, 13mm x 15mm FBGA • Operating Temperature Range Commercial (0°C to +70°C) Part Number Example MARKING -6 -7.5 -10 MT58L512L18D MT58L256L32D MT58L256L36D T S F None *JEDEC-standard MS-026 BHA (LQFP). GENERAL DESCRIPTION The Micron® SyncBurst™ SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process. Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion (CE2, CE2#), burst control inputs (ADSC#, ADSP#, MT58L512L18DT-7.5 * A Part Marking Guide for the FBGA devices can be found on Micron’s web site—http://www.micron.com/support/index.html. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 512K x 18 18 SA0, SA1, SA MODE ADV# CLK ADDRESS REGISTER 18 16 18 2 SA0-SA1 SA1' BINARY Q1 COUNTER AND LOGIC CLR Q0 SA0' ADSC# ADSP# BYTE “b” WRITE REGISTER 9 BYTE “b” WRITE DRIVER 9 256K x 9 x 2 MEMORY ARRAY 9 18 SENSE 18 AMPS BWb# OUTPUT 18 REGISTERS OUTPUT BUFFERS E 18 BWa# BWE# GW# CE# CE2 CE2# OE# BYTE “a” WRITE REGISTER 9 BYTE “a” WRITE DRIVER DQs DQPa DQPb ENABLE REGISTER 18 PIPELINED ENABLE 2 INPUT REGISTERS FUNCTIONAL BLOCK DIAGRAM 256K x 32/36 17 SA0, SA1, SA ADDRESS REGISTER 17 SA0-SA1 17 MODE ADV# CLK Q1 BINARY COUNTER SA0' CLR Q0 SA1' ADSC# ADSP# BWd# BYTE “d” WRITE REGISTER BYTE “c” WRITE REGISTER 9 BYTE “d” WRITE DRIVER BYTE “c” WRITE DRIVER BYTE “b” WRITE DRIVER BYTE “a” WRITE DRIVER 9 BWc# 9 9 128K x 8 x 4 (x32) 128K x 9 x 4 (x36) 36 SENSE AMPS 36 OUTPUT REGISTERS 36 BWb# BYTE “b” WRITE REGISTER 9 9 MEMORY ARRAY OUTPUT BUFFERS E DQs DQPa 36 DQPd BWa# BWE# GW# CE# CE2 CE2# OE# BYTE “a” WRITE REGISTER 9 9 ENABLE REGISTER 36 PIPELINED ENABLE 4 INPUT REGISTERS NOTE: Functional block diagrams illustrate simplified device operation. See truth tables, pin descriptions, and timing diagrams for detailed information. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM GENERAL DESCRIPTION (CONTINUED) ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version. Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs. Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#). Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions. This device incorporates an additional pipelined enable register which delays turning off the output buffer an additional cycle when a deselect is executed. This feature allows depth expansion without penalizing system performance. Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. The device is ideally suited for Pentium® and PowerPC pipelined systems and systems that benefit from a very wide, high-speed data bus. The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications. Please refer to Micron’s Web site (www.micron.com/ products/datasheets/syncds.html) for the latest data sheet. TQFP PINOUTS At the time of the writing of this data sheet, there are two pinouts in the industry. Micron will support both pinouts for this part. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN ASSIGNMENT TABLE PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 x32/x36 NC/DQPc* DQc DQc VDDQ VSS NC DQc NC DQc DQb DQc DQb DQc VSS VDDQ DQb DQc DQb DQc VDD VDD NC VSS DQb DQd DQb DQd VDDQ VSS DQb DQd DQb DQd DQPb DQd NC DQd x18 NC NC NC PIN # 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 x18 x32/x36 VSS VDDQ NC DQd NC DQd NC NC/DQPd* MODE SA SA SA SA SA1 SA0 DNU DNU VSS VDD NF NF (T Version) SA (S Version) SA SA SA SA SA SA SA PIN # 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 x32/x36 NC/DQPa* DQa DQa VDDQ VSS NC DQa NC DQa DQa DQa VSS VDDQ DQa DQa ZZ VDD NC VSS DQa DQb DQa DQb VDDQ VSS DQa DQb DQa DQb DQPa DQb NC DQb x18 NC NC NC PIN # 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 x32/x36 VSS VDDQ NC DQb NC DQb SA NC/DQPb* SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA (T Version) CE2# (S Version) BWa# BWb# NC BWc# NC BWd# CE2 CE# SA SA x18 *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM PIN ASSIGNMENT (TOP VIEW) 100-PIN TQFP, 2-CHIP ENABLE, T VERSION SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 SA SA SA SA SA SA SA NF NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD SA BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC/DQPb* DQb DQb VDDQ VSS DQb DQb DQb DQb VSS VDDQ DQb DQb VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa DQa DQa VSS VDDQ DQa DQa NC/DQPa* NC NC NC VDDQ VSS NC NC DQb DQb VSS VDDQ DQb DQb VDD VDD NC VSS DQb DQb VDDQ VSS DQb DQb DQPb NC VSS VDDQ NC NC NC x32/x36 SA SA SA SA SA SA SA NF NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 NC/DQPc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd* 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM PIN ASSIGNMENT (TOP VIEW) 100-PIN TQFP, 3-CHIP ENABLE, S VERSION SA NC NC VDDQ VSS NC DQPa DQa DQa VSS VDDQ DQa DQa VSS NC VDD ZZ DQa DQa VDDQ VSS DQa DQa NC NC VSS VDDQ NC NC NC SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# NC NC CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x18 SA SA SA SA SA SA SA SA NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE SA SA ADV# ADSP# ADSC# OE# BWE# GW# CLK VSS VDD CE2# BWa# BWb# BWc# BWd# CE2 CE# SA SA 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 49 82 48 83 47 84 46 85 45 86 44 87 43 88 42 89 41 90 40 91 39 92 38 93 37 94 36 95 35 96 34 97 33 98 32 99 31 100 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC/DQPb* NC DQb NC DQb VDDQ VDDQ VSS VSS NC DQb NC DQb DQb DQb DQb DQb VSS VSS VDDQ VDDQ DQb DQb DQb DQb VDD VSS VDD NC VDD NC ZZ VSS DQa DQb DQa DQb VDDQ VDDQ VSS VSS DQa DQb DQa DQb DQa DQPb DQa NC VSS VSS VDDQ VDDQ DQa NC DQa NC NC/DQPa* NC NC x32/x36 SA SA SA SA SA SA SA SA NF VDD VSS DNU DNU SA0 SA1 SA SA SA SA MODE *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 NC/DQPc* DQc DQc VDDQ VSS DQc DQc DQc DQc VSS VDDQ DQc DQc VDD VDD NC VSS DQd DQd VDDQ VSS DQd DQd DQd DQd VSS VDDQ DQd DQd NC/DQPd* 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. Two different pinouts are available for the TQFP package. 37 37 36 36 32-35, 44-50, 32-35, 44-50, 80-82, 99, 81, 82, 99, 100 100 92 (T Version) 92 (T Version) 43 (S Version) 43 (S Version) 93 94 – – 93 94 95 96 BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb. For the x32 and x36 versions, BWa# controls DQa pins and DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins and DQPc; BWd# controls DQd pins and DQPd. Parity is only available on the x18 and x36 versions. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. CE2# is only available on the S Version. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on this pin effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. 87 87 BWE# Input 88 88 GW# Input 89 89 CLK Input 98 98 CE# Input 92 (S Version) 64 92 (S Version) 64 CE2# Input ZZ Input 97 97 CE2 Input 86 83 86 83 OE# ADV# Input Input (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TQFP PIN DESCRIPTIONS (CONTINUED) x18 84 x32/x36 84 SYMBOL ADSP# TYPE Input DESCRIPTION Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2 and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Mode: This input selects the burst sequence. A LOW on this pin selects “linear burst.” NC or HIGH on this pin selects “interleaved burst.” Do not alter input state while device is operating. 85 85 ADSC# Input 31 31 MODE Input (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72, 73 (b) 8, 9, 12, (b) 68, 69 13, 18, 19, 22, 72-75, 78, 79 23 (c) 2, 3, 6-9, 12, 13 (d) 18, 19, 22-25, 28, 29 74 24 – – 51 80 1 30 DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa pins; Byte “b” Output is DQb pins. For the x32 and x36 versions, Byte “a” is DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD VDDQ VSS NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these pins are No Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd. 14, 15, 41, 65, 14, 15, 41, 65, 91 91 4, 11, 20, 27, 4, 11, 20, 27, 54, 61, 70, 77 54, 61, 70, 77 5, 10, 17, 21, 5, 10, 17, 21, 26, 40, 55, 60, 26, 40, 55, 60, 67, 71, 76, 90 67, 71, 76, 90 38, 39 1-3, 6, 7, 16, 25, 28-30, 51-53, 56, 57, 66, 75, 78, 79, 95, 96 38, 39 16, 66 Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Supply Ground: GND. DNU NC – – Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. 42 42 43 (T Version) 43 (T Version) NF – No Function: These pins are internally connected to the die and have the capacitance of an input pin. It is allowable to leave these pins unconnected or driven by signals. On the S Version, pin 42 is reserved as an address upgrade pin for the 16Mb SyncBurst SRAM. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM PIN LAYOUT (TOP VIEW) 165-PIN FBGA x18 1 2 3 4 5 6 7 8 9 10 11 1 2 3 4 x32/x36 5 6 7 8 9 10 11 A NC B NC C NC D NC E NC F NC G NC H VDD J DQb K DQb L DQb M DQb N DQPb P NC R MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA NC SA SA DNU SA1 DNU SA SA SA SA NC VDDQ VSS NC NC VSS VSS VDDQ NC NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC NC VDDQ VDD VSS VSS VSS VDD VDDQ DQa NC VSS NC VDD VSS VSS VSS VDD NC NC ZZ DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa DQb VDDQ VDD VSS VSS VSS VDD VDDQ NC DQa NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPa SA CE2 NC BWa# CLK GW# OE# (G#) ADSP# SA NC SA CE# BWb# NC CE2# BWE# ADSC# ADV# SA SA A A NC SA CE# BWc# BWb# CE2# BWE# ADSC# ADV# SA NC A B B NC SA CE2 BWd# BWa# CLK GW# OE# (G#) ADSP# SA NC B C C NC/DQPc C NC VDDQ VSS VSS VSS VSS VSS VDDQ NC NC/DQPb D D DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb D E E DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb E F F DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb F G G DQc DQc VDDQ VDD VSS VSS VSS VDD VDDQ DQb DQb G H H VDD VSS NC VDD VSS VSS VSS VDD NC NC ZZ H J J DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa J K K DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa K L L DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa L M M DQd DQd VDDQ VDD VSS VSS VSS VDD VDDQ DQa DQa M N N NC/DQPd N NC VDDQ VSS NC NC VSS VSS VDDQ NC NC/DQPa P P NC NC SA SA DNU SA1 DNU SA SA SA SA P R R MODE (LBO#) NC SA SA DNU SA0 DNU SA SA SA SA R TOP VIEW TOP VIEW *No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. NOTE: Pin 6N reserved for address pin expansion; 16Mb. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL SA0 SA1 SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. 6R 6R 6P 6P 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 3R, 4P, 4R, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, 10P, 10R, 11P, 11R 11R 5B 4A – – 5B 5A 4A 4B BWa# BWb# BWc# BWd# Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. For the x18 version, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb. For the x32 and x36 versions, BWa# controls DQas and DQPa; BWb# controls DQbs and DQPb; BWc# controls DQcs and DQPc; BWd# controls DQds and DQPd. Parity is only available on the x18 and x36 versions. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 18-, 32- or 36-bit WRITE to occur independent of the BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables, and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP#. CE# is sampled only when a new external address is loaded. Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When ZZ is active, all other inputs are ignored. Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled only when a new external address is loaded. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. 7A 7A BWE# Input 7B 7B GW# Input 6B 6B CLK Input 3A 3A CE# Input 6A 6A CE2# Input 11H 11H ZZ Input 3B 3B CE2 Input 8B 8B OE#(G#) Input (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 9A x32/x36 9A SYMBOL ADV# TYPE Input DESCRIPTION Synchronous Address Advance: This active LOW input is used to advance the internal burst counter, controlling burst access after the external address is loaded. A HIGH on ADV# effectively causes wait states to be generated (no address advance). To ensure use of correct address during a WRITE cycle, ADV# must be HIGH at the rising edge of the first clock after an ADSP# cycle is initiated. Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Powerdown state is entered if CE2 is LOW or CE2# is HIGH. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE# is LOW. ADSC# is also used to place the chip into power-down state when CE# is HIGH. Mode: This input selects the burst sequence. A LOW on this input selects “linear burst.” NC or HIGH on this input selects “interleaved burst.” Do not alter input state while device is operating. 9B 9B ADSP# Input 8A 8A ADSC# Input 1R 1R MODE (LB0#) Input (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, 1K, 1L, 1M, 2D, 2E, 2F, 2G (b) 10D, 10E, 10F, 10G, 11D, 11E, 11F, 11G (c) 1D, 1E, 1F, 1G, 2D, 2E, 2F, 2G (d) 1J, 1K, 1L, 1M, 2J, 2K, 2L, 2M 11N 11C 1C 1N DQa DQb Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas; Output Byte “b” is associated with DQbs. For the x32 and x36 versions, Byte “a” is associated with DQas; Byte “b” is associated with DQbs; Byte “c” is associated with DQcs; Byte “d” is associated with DQds. Input data must meet setup and hold times around the rising edge of CLK. DQc DQd 11C 1N – – NC/DQPa NC/DQPb NC/DQPc NC/DQPd VDD NC/ I/O No Connect/Parity Data I/Os: On the x32 version, these are No Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd. 1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F, 4G, 4H, 4J, 4G, 4H, 4J, 4K, 4L, 4M, 4K, 4L, 4M, 8D, 8E, 8F, 8D, 8E, 8F, 8G, 8H, 8J, 8G, 8H, 8J, 8K, 8L, 8M 8K, 8L, 8M Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. (continued on next page) 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA PIN DESCRIPTIONS (continued) x18 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N x32/x36 3C, 3D, 3E, 3F, 3G, 3J, 3K, 3L, 3M, 3N, 9C, 9D, 9E, 9F, 9G, 9J, 9K, 9L, 9M, 9N SYMBOL VDDQ TYPE DESCRIPTION Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. 2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C, 5D, 5E 5F, 5D, 5E 5F, 5G, 5H, 5J, 5G, 5H, 5J, 5K, 5L, 5M, 5K, 5L, 5M, 6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F, 6G, 6H, 6J, 6G, 6H, 6J, 6K, 6L, 6M, 6K, 6L, 6M, 7C, 7D, 7E, 7C, 7D, 7E, 7F, 7G, 7H, 7F, 7G, 7H, 7J, 7K, 7L, 7J, 7K, 7L, 7M, 7N, 8C, 8N 7M, 7N, 8C, 8N 5P, 5R, 7P, 7R 5P, 5R, 7P, 7R 1A, 1B, 1C, 1A, 1B, 1P, 1D, 1E, 1F, 2C, 2N, 1G, 1P, 2C, 2P, 2R, 3H, 2J, 2K, 5N, 6N, 2L, 2M, 2N, 9H, 10C, 2P, 2R, 3H, 10H, 10N, 4B, 5A, 5N, 11A, 11B, 6N, 9H, 10C, 10D, 10E, 10F, 10G, 10H, 10N, 11B, 11J, 11K, 11L, 11M, 11N VSS Supply Ground: GND. DNU NC – – Do Not Use: These signals may either be unconnected or wired to GND to improve package heat dissipation. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. Pin 6N reserved for address pin expansion; 16Mb. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X00 X...X11 X...X10 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X10 X...X01 X...X00 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) X...X00 X...X01 X...X10 X...X11 SECOND ADDRESS (INTERNAL) X...X01 X...X10 X...X11 X...X00 THIRD ADDRESS (INTERNAL) X...X10 X...X11 X...X00 X...X01 FOURTH ADDRESS (INTERNAL) X...X11 X...X00 X...X01 X...X10 PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18) FUNCTION READ READ WRITE Byte “a” WRITE Byte “b” WRITE All Bytes WRITE All Bytes GW# H H H H H L BWE# H L L L L X BWa# X H L H L X BWb# X H H L L X PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36) FUNCTION READ READ WRITE Byte “a” WRITE All Bytes WRITE All Bytes GW# H H H H L BWE# H L L L X BWa# X H L L X BWb# X H H L X BWc# X H H L X BWd# X H H L X NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TRUTH TABLE OPERATION Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst ADDRESS USED None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE# CE2# CE2 H L L L L X L L L L L X X H H X H X X H H X H X X H X H X L L L L L X X X X X X X X X X X X X L X L X X H H H H H X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP# ADSC# ADV# WRITE# OE# X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L X X X X X X L H X L H L H L H X X L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Q High-Z D D NOTE: 1. X means “Don’t Care.” # means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH. 3. BWa# enables WRITEs to DQa’s and DQPa. BWb# enables WRITEs to DQb’s and DQPb. BWc# enables WRITEs to DQc’s and DQPc. BWd# enables WRITEs to DQd’s and DQPd. DQPa and DQPb are only available on the x18 and x36 versions. DQPc and DQPd are only available on the x36 version. 4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS .............................. -0.5V to +4.6V Voltage on VDDQ Supply Relative to VSS .............................. -0.5V to +4.6V VIN (DQx) ................................. -0.5V to VDDQ + 0.5V VIN (inputs) ................................. -0.5V to VDD + 0.5V Storage Temperature (plastic) ............ -55°C to +150°C Storage Temperature (FBGA) ............. -55°C to +125°C Junction Temperature** ................................... +150°C Short Circuit Output Current .......................... 100mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature and airflow. See Micron Technical Note TN-05-14 for more information. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (0°C ≤ TA ≤ +70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply CONDITIONS SYMBOL VIH VIL ILI ILO VOH VOL VDD VDDQ MIN 2.0 -0.3 -1.0 -1.0 2.4 – 3.135 3.135 MAX VDD + 0.3 0.8 1.0 1.0 – 0.4 3.6 3.6 UNITS V V µA µA V V V V NOTES 1, 2 1, 2 3 0V ≤ VIN ≤ VDD Output(s) disabled, 0V ≤ VIN ≤ VDD IOH = -4.0mA IOL = 8.0mA 1, 4 1, 4 1 1, 5 TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance CONDITIONS TA = 25°C; f = 1 MHz; VDD = 3.3V SYMBOL CI CO CA CCK TYP 3 4 3 3 MAX 4 5 3.5 3.5 UNITS pF pF pF pF NOTES 6 6 6 6 NOTE: 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH ≤ +4.6V for t ≤ tKC/2 for I ≤ 20mA Undershoot: VIL ≥ -0.7V for t ≤ tKC/2 for I ≤ 20mA Power-up: VIH ≤ +3.6V and VDD ≤ 3.135V for t ≤ 200ms 3. MODE has an internal pull-up, and input leakage = ±10µA. 4. The load used for VOH, VOL testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O curves are available upon request. 5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together. 6. This parameter is sampled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance TA = 25°C; f = 1 MHz CONDITIONS SYMBOL CI CO CCK TYP 2.5 4 2.5 MAX 3.5 5 3.5 UNITS pF pF pF NOTES 2 2 2 TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Top of Case) CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 1-layer SYMBOL θJA θJC TYP 40 8 UNITS NOTES °C/W °C/W 1 1 FBGA THERMAL RESISTANCE DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Pins (Bottom) NOTE: 1. This parameter is sampled. 2. FBGA preliminary package data. CONDITIONS Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. SYMBOL θJA θJC θJB TYP 40 9 17 UNITS NOTES °C/W °C/W °C/W 2 2 2 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM IDD OPERATING CONDITIONS AND MAXIMUM LIMITS (0°C ≤ TA ≤ 70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) MAX DESCRIPTION Power Supply Current: Operating Power Supply Current: Idle CONDITIONS Device selected; All inputs ≤ VIL or ≥ VIH; Cycle time ≥ tKC (MIN); VDD = MAX; Outputs open Device selected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN) Device deselected; VDD = MAX; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs ≤ VIL or ≥ VIH; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; ADSC#, ADSP#, GW#, BWx#, ADV# ≥ VIH; All inputs ≤ VSS + 0.2 or ≥ VDD - 0.2; Cycle time ≥ tKC (MIN) SYMBOL IDD TYP 225 -6 475 -7.5 375 -10 300 UNITS NOTES mA 1, 2, 3 IDD1 55 110 90 85 mA 1, 2, 3 CMOS Standby ISB2 0.4 10 10 10 mA 2, 3 TTL Standby ISB3 8 25 25 25 mA 2, 3 Clock Running ISB4 55 110 90 85 mA 2, 3 NOTE: 1. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and greater output loading. 2. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25°C and 10ns cycle time. 4. This parameter is sampled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Note 1) (0°C ≤ TA ≤ 70°C; VDD, VDDQ = +3.3V +0.3V/-0.165V unless otherwise noted) -6 DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to output in Low-Z Clock to output in High-Z OE# to output valid OE# to output in Low-Z OE# to output in High-Z Setup Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) Hold Times Address Address status (ADSC#, ADSP#) Address advance (ADV#) Write signals (BWa#-BWd#, BWE#, GW#) Data-in Chip enables (CE#, CE2#, CE2) NOTE: 1. 2. 3. 4. 5. 6. SYMBOL tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tAAS tWS tDS tCES tAH tADSH tAAH tWH tDH tCEH MIN 6.0 MAX MIN 7.5 -7.5 MAX -10 MIN 10 MAX UNITS ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns NOTES 166 2.3 2.3 3.5 1.5 0 3.5 3.5 0 3.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0 1.5 0 2.5 2.5 133 3.0 3.0 4.0 1.5 1.5 4.2 4.2 0 4.2 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 100 2 2 5.0 5.0 5.0 4.5 3 3, 4, 5, 6 3, 4, 5, 6 7 3, 4, 5, 6 3, 4, 5, 6 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 8, 9 Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted. Measured as HIGH above VIH and LOW below VIL. This parameter is measured with the output loading shown in Figure 2. This parameter is sampled. Transition is measured ±500mV from steady state voltage. Refer to Technical Note TN-58-09, “Synchronous SRAM Bus Contention Design Considerations,” for a more thorough discussion on these parameters. 7. OE# is a “Don’t Care” when a byte write enable is sampled LOW. 8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the required setup and hold times. 9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM TEST CONDITIONS Input pulse levels .................. VIH = (VDD/2.2) + 1.5V .................... VIL = (VDD/2.2) - 1.5V Input rise and fall times ..................................... 1ns Input timing reference levels ...................... VDD/2.2 Output reference levels ............................ VDDQ/2.2 Output load ............................. See Figures 1 and 2 +3.3V Q Z O= 50 50 VT = 1.5V Figure 1 3.3V I/O OUTPUT LOAD EQUIVALENT LOAD DERATING CURVES Micron 512K x 18, 256K x 32, and 256K x 36 SyncBurst SRAM timing is dependent upon the capacitive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 317 Q 351 5pF Figure 2 3.3V I/O OUTPUT LOAD EQUIVALENT 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE ELECTRICAL CHARACTERISTICS DESCRIPTION Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current NOTE: 1. This parameter is sampled. CONDITIONS ZZ ≥ VIH SYMBOL ISB2Z tZZ tRZZ tZZI tRZZI MIN MAX 10 2(tKC) UNITS mA ns ns ns ns NOTES 1 1 1 1 2(tKC) 2(tKC) 0 SNOOZE MODE WAVEFORM CLK t ZZ t RZZ ZZ t ZZI I SUPPLY I ISB2Z t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM READ TIMING 3 tKC CLK tKH tADSS tADSH tKL ADSP# tADSS tADSH ADSC# tAS tAH ADDRESS A1 tWS tWH A2 A3 Burst continued with new base address. GW#, BWE#, BWa#-BWd# tCES tCEH Deselect (NOTE 4) cycle. CE# (NOTE 2) ADV# tAAS tAAH ADV# suspends burst. OE# (NOTE 3) t KQLZ t OEHZ tOEQ t OELZ tKQ tKQX t KQHZ Q High-Z Q(A1) t KQ Q(A2) (NOTE 1) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) Single READ BURST READ Burst wraps around to its initial state. DON’T CARE UNDEFINED READ TIMING PARAMETERS -6 SYMBOL tKC fKF tKH tKL tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ -7.5 MAX 166 MIN 7.5 2.5 2.5 3.5 4.0 1.5 0 3.5 3.5 4.2 4.2 0 3.5 4.2 0 1.5 1.5 MAX 133 3.0 3.0 MIN 10 -10 MAX 100 UNITS ns MHz ns ns ns ns ns ns ns ns ns SYMBOL tAS tADSS tAAS tWS tCES tAH tADSH tAAH tWH tCEH -6 MIN 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 MAX MIN 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 -7.5 MAX MIN 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 -10 MAX UNITS ns ns ns ns ns ns ns ns ns ns MIN 6.0 2.3 2.3 1.5 0 5.0 5.0 5.0 4.5 0 NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q to be driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM WRITE TIMING t KC CLK tKH tADSS tADSH tKL ADSP# tADSS tADSH ADSC# extends burst. tADSS tADSH ADSC# tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP# initiates burst. A3 tWS tWH BWE#, BWa#-BWd# (NOTE 5) tWS tWH GW# tCES tCEH CE# (NOTE 2) ADV# (NOTE 4) OE# (NOTE 3) tDS tDH tAAS tAAH ADV# suspends burst. D High-Z tOEHZ D(A1) D(A2) D(A2 + 1) (NOTE 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Q BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED WRITE TIMING PARAMETERS -6 SYMBOL tKC fKF tKH tKL tOEHZ tAS tADSS tAAS tWS -7.5 MAX 166 MIN 7.5 2.5 2.5 3.5 4.2 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 MAX 133 3.0 3.0 MIN 10 -10 MAX 100 UNITS ns MHz ns ns 4.5 ns ns ns ns ns SYMBOL tDS tCES tAH tADSH tAAH tWH tDH tCEH -6 MIN 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 MAX MIN 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -7.5 MAX MIN 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 -10 MAX UNITS ns ns ns ns ns ns ns ns MIN 6.0 2.3 2.3 1.5 1.5 1.5 1.5 NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/ output data contention for the time period prior to the byte write enable inputs being sampled. 4. ADV# must be HIGH to permit a WRITE to the loaded address. 5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM READ/WRITE TIMING 3 tKC CLK tKH tADSS tADSH tKL ADSP# ADSC# tAS tAH ADDRESS BWE#, BWa#-BWd# (NOTE 4) CE# (NOTE 2) ADV# A1 A2 A3 tWS tWH A4 A5 A6 tCES tCEH OE# tKQ tDS tDH tOELZ D High-Z tKQLZ tOEHZ D(A3) D(A5) D(A6) Q High-Z Q(A1) Back-to-Back READs (NOTE 5) Q(A2) Single WRITE Q(A4) Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs DON’T CARE UNDEFINED READ/WRITE TIMING PARAMETERS -6 SYMBOL tKC fKF tKH tKL tKQ tKQLZ tOELZ tOEHZ tAS -7.5 MAX 166 MIN 7.5 133 2.5 2.5 3.5 4.0 0 0 3.5 4.2 1.5 2.0 1.5 0 3.0 3.0 MAX MIN 10 -10 MAX 100 UNITS ns MHz ns ns ns ns ns ns ns SYMBOL tADSS tWS tDS tCES tAH tADSH tWH tDH tCEH -6 MIN 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 MAX MIN 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 -7.5 MAX MIN 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 -10 MAX UNITS ns ns ns ns ns ns ns ns ns MIN 6.0 2.3 2.3 0 0 1.5 5.0 4.5 NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4. 2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When CE# is HIGH, CE2# is HIGH and CE2 is LOW. 3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) PIN #1 ID 0.15 +0.03 -0.02 0.32 +0.06 -0.10 22.10 +0.10 -0.15 0.65 20.10 ±0.10 DETAIL A 0.62 14.00 ±0.10 +0.20 -0.05 GAGE PLANE 1.50 ±0.10 0.10 16.00 0.25 0.10 +0.10 -0.05 1.00 (TYP) 0.60 ±0.15 DETAIL A 1.40 ±0.05 NOTE: 1. All dimensions in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM 165-PIN FBGA 0.85 ±0.075 0.10 A SEATING PLANE A 10.00 BALL A11 165X Ø 0.45 1.00 (TYP) BALL A1 PIN A1 ID 1.20 MAX PIN A1 ID 7.50 ±0.05 15.00 ±0.10 14.00 7.00 ±0.05 1.00 (TYP) MOLD COMPOUND: EPOXY NOVOLAC 6.50 ±0.05 5.00 ±0.05 13.00 ±0.10 SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb SOLDER BALL PAD: Ø .33mm NOTE: 1. All dimensions in millimeters MAX or typical where noted. MIN 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. SyncBurst is a trademark of Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc. 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, PIPELINED, DCD SYNCBURST SRAM REVISION HISTORY Added FBGA Part Marking Guide, Rev 7/00 ................................................................................................. 7/18/00 Added Revision History Removed 119-Pin PBGA and References Removed Industrial Temperature References Added 165-pin FBGA Package ....................................................................................................................... 6/13/00 8Mb: 512K x 18, 256K x 32/36 3.3V I/O, Pipelined, DCD SyncBurst SRAM MT58L512L18D_2.p65 – Rev. 8/00 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2000, Micron Technology, Inc.