16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Features
DDR3L SDRAM 1.5U RDIMM
MT72KGF2G72PZ – 16GB
MT72KGF4G72PZ – 32GB
Features
Figure 1: 240-Pin 1.5U RDIMM
• DDR3L functionality and operations supported as
defined in the component data sheet
• 240-pin, registered 42mm dual in-line memory
module (1.5U RDIMM)
• Fast data transfer rates: PC3-10600, PC3-8500, or
PC3-6400
• 16GB (2 Gig x 72), 32GB (4 Gig x 72)
• VDD = 1.35V (1.283–1.45V)
• VDD = 1.5V (1.425–1.575V)
• Backward compatible with standard 1.5V DDR3
systems
• VDDSPD = 3.0–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Quad-rank, using 2Gb, 1.35V DDR3L devices
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Module height: 42mm (1.65in)
Options
Marking
• Operating temperature1
– Commercial (0°C ≤ T A ≤ +70°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
Note:
None
Z
-1G4
-1G1
1. Contact Micron for industrial temperature
module offerings.
Table 1: Key Timing Parameters
Data Rate (MT/s)
tRCD
tRP
tRC
Speed
Grade
Industry
Nomenclature
CL = 10
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
(ns)
(ns)
(ns)
-1G4
PC3-10600
1333
1333
1066
1066
800
667
13.125
13.125
49.125
-1G1
PC3-8500
–
–
1066
1066
800
667
13.125
13.125
50.625
-1G0
PC3-8500
–
–
1066
–
800
667
15
15
52.5
-80B
PC3-6400
–
–
–
–
800
667
15
15
52.5
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Features
Table 2: Addressing
Parameter
16GB
32GB
8K
8K
32K A[14:0]
64K A[15:0]
Device bank address
8 BA[2:0]
8 BA[2:0]
Device configuration
2Gb (512 Meg x 4)
4Gb (1 Gig x 4)
2K A[11, 9:0]
2K A[11, 9:0]
4 S#[3:0]
4 S#[3:0]
Refresh count
Row address
Column address
Module rank address
Table 3: Part Numbers and Timing Parameters – 16GB Modules
Base device: MT41K512M4,1 2Gb 1.35V DDR3L SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT72KGF2G72PZ-1G4__
16GB
2 Gig x 72
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT72KGF2G72PZ-1G1__
16GB
2 Gig x 72
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 4: Part Numbers and Timing Parameters – 32GB Modules
Base device: MT41K1G4,1 4Gb 1.35V DDR3L SDRAM
Module
Part Number2
Density
Configuration
MT72KGF4G72PZ-1G4__
32GB
4 Gig x 72
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT72KGF4G72PZ-1G1__
32GB
4 Gig x 72
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MT72KGF4G72PZ-1G4E1.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Pin Assignments
Pin Assignments
Table 5: Pin Assignments
240-Pin DDR3 RDIMM Front
240-Pin DDR3 RDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
VREFDQ
31
DQ25
61
A2
91
DQ41
121
VSS
151
VSS
181
A1
211
VSS
2
VSS
32
VSS
62
VDD
92
VSS
122
DQ4
152
DQS12
182
VDD
212
DQS14
DQS14#
3
DQ0
33
DQS3#
63
NF
93
DQS5#
123
DQ5
153
DQS12#
183
VDD
213
4
DQ1
34
DQS3
64
NF
94
DQS5
124
VSS
154
VSS
184
CK0
214
VSS
5
VSS
35
VSS
65
VDD
95
VSS
125
DQS9
155
DQ30
185
CK0#
215
DQ46
6
DQS0#
36
DQ26
66
VDD
96
DQ42
126
DQS9#
156
DQ31
186
VDD
216
DQ47
7
DQS0
37
DQ27
67
VREFCA
97
DQ43
127
VSS
157
VSS
187
EVENT#
217
VSS
8
VSS
38
VSS
68
Par_In
98
VSS
128
DQ6
158
CB4
188
A0
218
DQ52
9
DQ2
39
CB0
69
VDD
99
DQ48
129
DQ7
159
CB5
189
VDD
219
DQ53
10
DQ3
40
CB1
70
A10
100
DQ49
130
VSS
160
VSS
190
BA1
220
VSS
11
VSS
41
VSS
71
BA0
101
VSS
131
DQ12
161
DQS17
191
VDD
221
DQS15
12
DQ8
42
DQS8#
72
VDD
102
DQS6#
132
DQ13
162
DQS17#
192
RAS#
222
DQS15#
13
DQ9
43
DQS8
73
WE#
103
DQS6
133
VSS
163
VSS
193
S0#
223
VSS
14
VSS
44
VSS
74
CAS#
104
VSS
134
DQS10
164
CB6
194
VDD
224
DQ54
15
DQS1#
45
CB2
75
VDD
105
DQ50
135
DQS10#
165
CB7
195
ODT0
225
DQ55
16
DQS1
46
CB3
76
S1#
106
DQ51
136
VSS
166
VSS
196
A13
226
VSS
17
VSS
47
VSS
77
ODT1
107
VSS
137
DQ14
167
NC
197
VDD
227
DQ60
18
DQ10
48
VTT
78
VDD
108
DQ56
138
DQ15
168
RESET#
198
S3#
228
DQ61
19
DQ11
49
VTT
79
S2#
109
DQ57
139
VSS
169
CKE1
199
VSS
229
VSS
20
VSS
50
CKE0
80
VSS
110
VSS
140
DQ20
170
VDD
200
DQ36
230
DQS16
21
DQ16
51
VDD
81
DQ32
111
DQS7#
141
DQ21
171
A15
201
DQ37
231
DQS16#
22
DQ17
52
BA2
82
DQ33
112
DQS7
142
VSS
172
A14
202
VSS
232
VSS
23
VSS
53
Err_Out#
83
VSS
113
VSS
143
DQS11
173
VDD
203
DQS13
233
DQ62
24
DQS2#
54
VDD
84
DQS4#
114
DQ58
144
DQS11#
174
A12
204
DQS13#
234
DQ63
25
DQS2
55
A11
85
DQS4
115
DQ59
145
VSS
175
A9
205
VSS
235
VSS
26
VSS
56
A7
86
VSS
116
VSS
146
DQ22
176
VDD
206
DQ38
236
VDDSPD
27
DQ18
57
VDD
87
DQ34
117
SA0
147
DQ23#
177
A8
207
DQ39
237
SA1
28
DQ19
58
A5
88
DQ35
118
SCL
148
VSS
178
A6
208
VSS
238
SDA
29
VSS
59
A4
89
VSS
119
SA2
149
DQ28
179
VDD
209
DQ44
239
VSS
30
DQ24
60
VDD
90
DQ40
120
VTT
150
DQ29
180
A3
210
DQ45
240
VTT
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© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
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© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Pin Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event: The EVENT# pin is asserted by the temperature sensor when crit(open drain) ical temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The
component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DQ Map
DQ Map
Table 7: Component-to-Module DQ Map, Front
Component
Reference
Number
Component
DQ
U1
U2
U3
U4
U5
U7
U8
U9
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
1
4
U20
0
5
123
1
0
3
1
4
122
2
3
10
2
7
129
3
2
9
3
6
128
0
8
12
0
13
132
1
9
13
1
12
131
2
11
19
2
15
138
3
10
18
3
14
137
0
16
21
0
20
140
1
17
22
1
21
141
2
19
28
2
23
147
3
18
27
3
22
146
0
24
30
0
28
149
1
25
31
1
29
150
2
27
37
2
31
156
3
26
36
3
30
155
0
CB0
39
0
CB4
158
1
CB1
40
1
CB5
159
2
CB3
46
2
CB7
165
3
CB2
45
3
CB6
164
0
33
82
0
37
201
1
32
81
1
36
200
2
35
88
2
39
207
3
34
87
3
38
206
0
41
91
0
45
210
1
40
90
1
44
209
2
43
97
2
47
216
3
42
96
3
46
215
0
49
100
0
53
219
1
48
99
1
52
218
2
51
106
2
55
225
3
50
105
3
54
224
U21
U22
U23
U24
U26
U27
U28
6
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© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DQ Map
Table 7: Component-to-Module DQ Map, Front (Continued)
Component
Reference
Number
Component
DQ
U10
U11
U12
U13
U14
U15
U16
U17
U18
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
57
109
U29
0
61
228
1
56
108
1
60
227
2
59
115
2
63
234
3
58
114
3
62
233
0
1
4
0
5
123
1
0
3
1
4
122
2
3
10
2
7
129
3
2
9
3
6
128
0
8
12
0
13
132
1
9
13
1
12
131
2
11
19
2
15
138
3
10
18
3
14
137
0
16
21
0
20
140
1
17
22
1
21
141
2
19
28
2
23
147
3
18
27
3
22
146
0
24
30
0
28
149
1
25
31
1
29
150
2
27
37
2
31
156
3
26
36
3
30
155
0
CB0
39
0
CB4
158
1
CB1
40
1
CB5
159
2
CB3
46
2
CB7
165
3
CB2
45
3
CB6
164
0
33
82
0
37
201
1
32
81
1
36
200
2
35
88
2
39
207
3
34
87
3
38
206
0
41
91
0
45
210
1
40
90
1
44
209
2
43
97
2
47
216
3
42
96
3
46
215
0
49
100
0
53
219
1
48
99
1
52
218
2
51
106
2
55
225
3
50
105
3
54
224
U30
U31
U32
U33
U34
U35
U36
U37
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DQ Map
Table 7: Component-to-Module DQ Map, Front (Continued)
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
U19
0
57
109
U38
0
61
228
1
56
108
1
60
227
2
59
115
2
63
234
3
58
114
3
62
233
Table 8: Component-to-Module DQ Map, Back
Component
Reference
Number
Component
DQ
U39
U40
U41
U42
U43
U44
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
56
108
U57
0
60
227
1
57
109
1
61
228
2
58
114
2
62
233
3
59
115
3
63
234
0
48
99
0
52
218
1
49
100
1
53
219
2
50
105
2
54
224
3
51
106
3
55
225
0
40
90
0
44
209
1
41
91
1
45
210
2
42
96
2
46
215
3
43
97
3
47
216
0
32
81
0
36
200
1
33
82
1
37
201
2
34
87
2
38
206
3
35
88
3
39
207
0
CB1
40
0
CB5
195
1
CB0
39
1
CB4
158
2
CB2
45
2
CB6
164
3
CB3
46
3
CB7
165
0
25
31
0
29
150
1
24
30
1
28
149
2
26
36
2
30
155
3
27
37
3
31
156
U58
U59
U60
U62
U63
8
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© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DQ Map
Table 8: Component-to-Module DQ Map, Back (Continued)
Component
Reference
Number
Component
DQ
U45
U46
U47
U48
U49
U50
U51
U52
U53
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
17
22
U64
0
21
141
1
16
21
1
20
140
2
18
27
2
22
146
3
19
28
3
23
147
0
9
13
0
12
131
1
8
12
1
13
132
2
10
18
2
14
137
3
11
19
3
15
138
0
0
3
0
4
122
1
1
4
1
5
123
2
2
9
2
6
128
3
7
129
0
60
227
U65
U66
3
3
10
0
56
108
1
57
109
1
61
228
2
58
114
2
62
233
3
59
115
3
63
234
0
48
99
0
52
218
1
49
100
1
53
219
2
50
105
2
54
224
3
51
106
3
55
225
0
40
90
0
44
209
1
41
91
1
45
210
2
42
96
2
46
215
3
43
97
3
47
216
0
32
81
0
36
200
1
33
82
1
37
201
2
34
87
2
38
206
3
35
88
3
39
207
0
CB1
40
0
CB5
195
1
CB0
39
1
CB4
158
2
CB2
45
2
CB6
164
3
CB3
46
3
CB7
165
0
25
31
0
29
150
1
24
30
1
28
149
2
26
36
2
30
155
3
27
37
3
31
156
U67
U68
U69
U70
U71
U72
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DQ Map
Table 8: Component-to-Module DQ Map, Back (Continued)
Component
Reference
Number
Component
DQ
U54
U55
U56
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
17
22
U73
0
21
141
1
16
21
1
20
140
2
18
27
2
22
146
3
19
28
3
23
147
0
9
13
0
12
131
1
8
12
1
13
132
2
10
18
2
14
137
3
11
19
3
15
138
0
0
3
0
4
122
1
1
4
1
5
123
2
2
9
2
6
128
3
3
10
3
7
129
U74
U75
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
VSS
RS0#
RS1#
RS2#
RS3#
DQS0
DQS0#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
DQ48
DQ49
DQ50
DQ51
DQS7
DQS7#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
CB0
CB1
CB2
CB3
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
ZQ
U47
ZQ
VSS
U11
ZQ
VSS
U56
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
ZQ
U46
ZQ
VSS
U12
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U45
ZQ
VSS
U13
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U44
ZQ
VSS
U14
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U42
ZQ
VSS
U16
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U41
ZQ
VSS
U17
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U40
ZQ
VSS
U18
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U39
ZQ
VSS
U19
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U43
ZQ
VSS
U15
VSS
ZQ
CK0
CK0#
S0#: Rank 0
S1#: Rank 1
S2#: Rank 2
S3#: Rank 3
BA[2:0]: DDR3 SDRAM
A[15/14:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: Rank 0, Rank 2
CKE1: Rank 1, Rank 3
ODT0: Rank 0, Rank 1 tied to VDD
ODT1: Rank 2, Rank 3 tied to VDD
Err_Out#
R
e
g
i
s
t
e
r
a
n
d
P
L
L
CK
DDR3 SDRAM
CK#
RESET#
VSS
U52
ZQ
VSS
U25, U61 (Mirrored)
S0#
S1#
S#2
S3#
BA[2:0]
A[15:0]
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
Par_In
VSS
U48
DM CS# DQS DQS#
U5
VSS
U49
DM CS# DQS DQS#
U10
VSS
U50
DM CS# DQS DQS#
U9
VSS
U51
DM CS# DQS DQS#
U8
VSS
U53
DM CS# DQS DQS#
U7
VSS
U54
DM CS# DQS DQS#
U4
VSS
U55
DM CS# DQS DQS#
U3
DQS9
DQS9#
Rank 0:
Rank 1:
Rank 2:
Rank 3:
VSS
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
CB4
CB5
CB6
CB7
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U20
ZQ
U66
ZQ
VSS
U30
ZQ
VSS
U75
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U21
ZQ
U65
ZQ
VSS
U31
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U22
ZQ
U64
ZQ
VSS
U32
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U63
ZQ
VSS
U33
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U60
ZQ
VSS
U35
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U59
ZQ
VSS
U36
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U58
ZQ
VSS
U37
ZQ
VSS
ZQ
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U57
ZQ
VSS
U38
ZQ
VSS
ZQ
VSS
DM CS# DQS DQS#
DM CS# DQS DQS#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
VSS
U62
ZQ
U34
ZQ
VSS
DDR3 SDRAM
VTT
DDR3 SDRAM
VREFCA
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
VSS
U71
VSS
ZQ
VSS
U6
SPD EEPROM & Temp Sensor
VDD
VSS
U67
DM CS# DQS DQS#
U24
VSS
U68
VSS
DM CS# DQS DQS#
U29
VSS
U69
VSS
DM CS# DQS DQS#
U28
VSS
U70
VSS
DM CS# DQS DQS#
U27
VSS
U72
VSS
DM CS# DQS DQS#
U26
VSS
U73
VSS
DM CS# DQS DQS#
U23
VSS
U74
VSS
DM CS# DQS DQS#
VDDSPD
SPD EEPROM/
Temperature
sensor
SCL
EVT A0
SDA
A1 A2
SA0 SA1 SA2
EVENT#
Command, control, address, and clock line terminations:
S#[3:0], CKE[1:0],
A[15/14:0], RAS#, CAS#,
WE#, ODT[1:0], BA[2:0]
DDR3
SDRAM
VTT
DDR3
SDRAM
CK
CK#
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U1–U5, U7–U10, U20–U24, U26–U29
U39–U47, U57–U60, U62–U66
U11–19, U30–U38
U48–U56, U67–U75
DDR3 SDRAM
Note:
DM CS# DQS DQS#
VDD
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
Registering Clock Driver Operation
Registered DDR3 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC standard
"Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications."
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The
register(s) and PLL reduce clock, control, command, and address signals loading by isolating DRAM from the system controller.
Parity Operations
The registering clock driver includes an even parity function for checking parity. The
memory controller accepts a parity bit at the Par_In input and compares it with the data
received on A[15:0], BA[2:0], RAS#, CAS#, and WE#. Valid parity is defined as an even
number of ones (1s) across the address and command inputs (A[15:0], BA[2:0], RAS#,
CAS#, and WE#) combined with Par_In. Parity errors are flagged on Err_Out#.
Address and command parity is checked during all DRAM operations and during control word WRITE operations to the registering clock driver. For SDRAM operations, the
address is still propagated to the SDRAM even when there is a parity error. When writing to the internal control words of the registering clock driver, the write will be ignored
if parity is not valid. For this reason, systems must connect the Par_In pins on the
DIMM and provide correct parity when writing to the registering clock driver control
word configuration registers.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converts into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,
"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by
the customer. System READ/WRITE operations between the master (system logic) and
the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock)
SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently
disabling hardware write protection. For further information refer to Micron technical
note TN-04-42, "Memory Module Serial Presence-Detect."
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 10: Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
VDD supply voltage
1.283
1.35
1.45
V
1.425
1.5
1.575
V
VREFCA(DC) Input reference voltage command/
address bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
VREFDQ(DC) I/O reference voltage DQ bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
–600
–
600
mA
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
TBD
TBD
TBD
µA
VDD
IVTT
Termination reference current from
VTT
VTT
Termination reference voltage (DC) –
command/address bus
II
Input leakage current;
Any input 0V ≤ VIN ≤
VDD; VREF input 0V ≤ VIN
≤ 0.95V (All other pins
not under test = 0V)
Address inputs, RAS#,
CAS#, WE#,
S#, CKE, ODT,
BA, CK, CK#
IOZ
Output leakage current; DQ, DQS,
0V ≤ VOUT ≤ VDD;
DQS#
DQ and ODT are
disabled; ODT is HIGH
–20
0
20
µA
IVREF
VREF supply leakage current;
VREFDQ = VDD/2 or VREFCA = VDD/2
(All other pins not under test = 0V)
–72
0
72
µA
Notes
1
2
TA
Module ambient
operating temperature
Commercial
0
–
70
°C
3, 4
TC
DDR3 SDRAM component case operating
temperature
Commercial
0
–
95
°C
3, 4, 5
Notes:
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
1. Module is backward-compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
2. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. TA and TC are simultaneous requirements.
14
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Electrical Specifications
4. For further information, refer to technical note TN-00-08: “Thermal Applications,”
available on Micron’s Web site.
5. The refresh rate is required to double when 85°C < TC ≤ 95°C.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
15
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown below.
Table 11: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
IDD Specifications
IDD Specifications
Table 12: DDR3 IDD Specifications and Conditions – 16GB (Die Revision M)
Values are for the MT41K512M4 DDR3L SDRAM only and are computed from values specified in the 2Gb 1.35V (512 Meg x
4) component data sheet
Parameter
Symbol
1333
1066
Units
IDD01
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
1
2
Precharge power-down current: Slow exit
IDD2P0
1638
1548
mA
1908
1818
mA
864
864
mA
Precharge power-down current: Fast exit
IDD2P1
2
2016
1656
mA
Precharge quiet standby current
IDD2Q2
2016
1656
mA
2
2160
1800
mA
2
1278
1188
mA
Precharge standby current
IDD2N
Precharge standby ODT current
IDD2NT
Active power-down current
IDD3P
2
3024
2664
mA
Active standby current
IDD3N2
3384
3024
mA
Burst read operating current
IDD4R1
2628
2358
mA
Burst write operating current
IDD4W
1
2448
2178
mA
Refresh current
IDD5B1
3978
3888
mA
Self refresh temperature current: MAX TC = 85°C
IDD62
864
864
mA
IDD6ET
1080
1080
mA
1
4338
4068
mA
1
1008
1008
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
IDD7
Reset current
IDD8
Notes:
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
2
1. One module rank in the active IDD, the other ranks in IDD2P0 (slow exit).
2. All ranks in this IDD condition.
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
IDD Specifications
Table 13: DDR3 IDD Specifications and Conditions – 32GB (Die Revision E)
Values are for the MT41K1G4 DDR3L SDRAM only and are computed from values specified in the 4Gb 1.35V (1 Gig x 4)
component data sheet
Parameter
Symbol
1333
1066
Units
IDD01
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
1
2
Precharge power-down current: Slow exit
IDD2P0
1710
1656
mA
1890
1818
mA
1152
1152
mA
Precharge power-down current: Fast exit
IDD2P1
2
2016
1872
mA
Precharge quiet standby current
IDD2Q2
1800
1584
mA
2
1800
1728
mA
2
1404
1350
mA
Precharge standby current
IDD2N
Precharge standby ODT current
IDD2NT
Active power-down current
IDD3P
2
2520
2304
mA
Active standby current
IDD3N2
2520
2304
mA
Burst read operating current
IDD4R1
3204
2898
mA
1
2718
2430
mA
Burst write operating current
IDD4W
Refresh current
IDD5B1
3528
3456
mA
Self refresh temperature current: MAX TC = 85°C
IDD62
1440
1440
mA
IDD6ET
1800
1800
mA
1
4284
3744
mA
1
1296
1296
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
IDD7
Reset current
IDD8
Notes:
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
2
1. One module rank in the active IDD, the other ranks in IDD2P0 (slow exit).
2. All ranks in this IDD condition.
18
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Registering Clock Driver Specifications
Registering Clock Driver Specifications
Table 14: Registering Clock Driver Electrical Characteristics
SSTE32882 devices or equivalent
Parameter
Symbol
Pins
Min
Nom
Max
Units
DC supply voltage
VDD
–
1.425
1.5
1.575
V
DC reference voltage
VREF
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
DC termination
voltage
VTT
–
0.49 × VDD - 20mV
0.5 × VDD
0.51 × VDD + 20mV
V
AC high-level input
voltage
VIH(AC)
Control, command,
address
VREF + 175mV
–
VDD + 400mV
V
AC low-level input
voltage
VIL(AC)
Control, command,
address
–0.4
–
VREF - 175mV
V
DC high-level input
voltage
VIH(DC)
Control, command,
address
VREF + 100mV
–
VDD + 0.4
V
DC low-level input
voltage
VIL(DC)
Control, command,
address
–0.4
–
VREF - 100mV
V
High-level input
voltage
VIH(CMOS)
RESET#, MIRROR
0.65 × VDD
–
VDD
V
Low-level input
voltage
VIL(CMOS)
RESET#, MIRROR
0
–
0.35 × VDD
V
Differential input
crosspoint voltage
range
VIX(AC)
CK, CK#, FBIN, FBIN#
0.5 × VDD - 175mV
0.5 × VDD
0.5 × VDD + 175mV
V
Differential input
voltage
VID(AC)
CK, CK#
350
–
VDD + TBD
mV
High-level output
current
IOH
Err_Out#
–
–
TBD
mA
Low-level output
current
IOL
Err_Out#
TBD
–
TBD
mA
Note:
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
1. Timing and switching specifications for the register listed are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for
the specific device used on the module.
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC
standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with
Temperature Sensor."
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 15: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
Supply current: VDD = 3.3V
IDD
–
2.0
mA
Input high voltage: Logic 1; SCL, SDA
VIH
1.45
VDDSPD + 1
V
Supply voltage
Input low voltage: Logic 0; SCL, SDA
VIL
–
0.55
V
Output low voltage: IOUT = 2.1mA
VOL
–
0.4
V
Input current
IIN
–5.0
5.0
µA
Temperature sensing range
–
–40
125
°C
Temperature sensor accuracy (class B)
–
–1.0
1.0
°C
Table 16: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition
Symbol
Min
Max
Units
tBUF
4.7
–
µs
SDA fall time
tF
20
300
ns
SDA rise time
tR
–
1000
ns
tHD:DAT
200
900
ns
Time bus must be free before a new transition can
start
Data hold time
Start condition hold time
tH:STA
4.0
–
µs
Clock HIGH period
tHIGH
4.0
50
µs
Clock LOW period
tLOW
4.7
–
µs
tSCL
10
100
kHz
Data setup time
tSU:DAT
250
–
ns
Start condition setup time
tSU:STA
4.7
–
µs
Stop condition setup time
tSU:STO
4.0
–
µs
SCL clock frequency
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
EVENT# Pin
The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD
EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be
set up in the sensor’s configuration register.
EVENT# has three defined modes of operation: interrupt mode, compare mode, and
critical temperature mode. Event thresholds are programmed in the 0x01 register using
a hysteresis. The alarm window provides a comparison window, with upper and lower
limits set in the alarm upper boundary register and the alarm lower boundary register,
respectively. When the alarm window is enabled, EVENT# will trigger whenever the
temperature is outside the MIN or MAX values set by the user.
The interrupt mode enables software to reset EVENT# after a critical temperature
threshold has been detected. Threshold points are set in the configuration register by
the user. This mode triggers the critical temperature limit and both the MIN and MAX of
the temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and returns to the logic HIGH state only when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
16GB, 32GB (x72, ECC, QR) 240-Pin 1.35V DDR3L 1.5U RDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR3 RDIMM
Front view
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
U1
U2
U3
U4
U5
U11
U12
U13
U14
U15
U6
U7
U8
U9
U10
U16
U17
U18
U19
42.15 (1.66)
41.85 (1.648)
U25
0.75 (0.03) R
(8X)
U20
U21
U22
U23
U24
U26
U27
U28
U29
2.50 (0.098) D
(2X)
U30
U31
U32
U33
U34
U35
U36
U37
U38
17.3 (0.68)
TYP
2.30 (0.091) TYP
0.76 (0.030) R
Pin 1
2.20 (0.087) TYP
1.0 (0.039)
TYP
1.45 (0.057) TYP
9.5 (0.374)
TYP
0.80 (0.031)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 120
54.68 (2.15)
TYP
123.0 (4.84)
TYP
Back view
27.7 (0.972)
TYP
U39
U40
U41
U42
U48
U49
U50
U51
45°, 4X
U43
U44
U45
U46
U47
U52
U53
U54
U55
U56
U61
U57
U58
U59
U60
U62
U63
U64
U65
U66
U67
U68
U69
U70
U71
U72
U73
U74
U75
3.0 (0.118) 4X TYP
3.05 (0.12) TYP
Pin 240
Notes:
Pin 121
5.0 (0.197) TYP
47.0 (1.85)
TYP
71.0 (2.79)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef84971887
kgf72c2g_4gx72pz.pdf – Rev. B 5/12 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2011 Micron Technology, Inc. All rights reserved.
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