MT8LSDT3264AY-133G1

256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Features Synchronous DRAM Module MT8LSDT3264A(I) - 256MB MT16LSDT6464A(I) - 512MB For the latest data sheet, please refer to the Micron® Web site: www.micron.com/products/modules Features Figure 1: • PC100- and PC133-compliant • 168-pin, dual in-line memory module (DIMM) • Utilizes 125 MHz and 133 MHz SDRAM components • Unbuffered • 256MB (32 Meg x 64), 512MB (64 Meg x 64) • Single +3.3V ±0.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, including Concurrent Auto Precharge, and Auto Refresh Modes • 64ms, 8,192 cycle Auto Refresh cycle • Self Refresh Mode • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) • Gold edge contacts Table 1: Access Time Clock Frequency CL = 2 CL = 3 Setup Time Hold Time -13E -133 -10E 133 MHz 133 MHz 100 MHz 5.4ns – 9ns – 5.4ns 7.5ns 1.5 1.5 2ns 0.8 0.8 1ns Table 2: Low Profile 1.125in. (28.575mm) Options Marking • Package 168-pin DIMM (standard) 168-pin DIMM (lead-free) • Operating Temperature Range Commercial (0°C to +70°C) Industrial (-40°C to +85°C) • Memory Clock/CAS Latency (133 MHz)/CL = 2 (133 MHz)/CL = 3 (100 MHz)/CL = 2 • PCB Low profile 1.125in. (28.575mm) Timing Parameters Module Marking 168-Pin DIMM (MO–161) G Y1 None I1, 2 -13E -133 -10E1 See page 2 note Notes: 1. Consult Micron for product availability. 2. Industrial Temperature Option available in 133 speed only. Address Table Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 256MB 512MB 8K 4 (BA0, BA1) 256Mb (32 Meg x 8) 8K (A0–A12) 1K (A0–A9) 1 (S0,S2) 8K 4 (BA0, BA1) 256Mb (32 Meg x 8) 8K (A0–A12) 1K (A0–A9) 2 (S0,S2; S1,S3) 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Pin Assignments and Descriptions Table 3: Part Numbers Part Number MT8LSDT3264AG-13E_ MT8LSDT3264AY-13E_ MT8LSDT3264A(I))G-133_ MT8LSDT3264A(I)Y-133_ MT8LSDT3264AG-10E_ MT8LSDT3264AY-10E_ MT16LSDT6464AAG-13E_ MT16LSDT6464AY-13E_ MT16LSDT6464A(I)G-133_ MT16LSDT6464A(I)Y-133_ MT16LSDT6464AG-10E_ MT16LSDT6464AY-10E_ Note: Module Density Configuration System Bus Speed 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT3264AG-133D2. Pin Assignments and Descriptions Table 4: Pin Assignment (168-Pin DIMM Front) PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC VSS NC NC VDD WE# DQMB0 DQMB1 S0# NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CK0 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VSS NC S2# DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC SDA SCL VDD 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Pin Assignments and Descriptions Table 5: Pin Assignment (168-Pin DIMM Back) Figure 2: Pin Symbol Pin Symbol Pin Symbol Pin Symbol 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 NC VSS NC NC VDD CAS# DQMB4 DQMB5 S1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VDD CK1 A12 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 VSS CKE0 S3# DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD Pin Locations (168-Pin DIMM) Front View U10 U2 U1 U3 U4 U6 U7 U8 U9 1.125 inches 28.57 millimeters PIN 41 PIN 1 PIN 84 Back View (Populated only for dual rank, 512MB module) U11 U12 U13 U14 U17 Indicates a VDD pin U18 U19 PIN 85 PIN 125 PIN 168 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN U16 Indicates a VSS pin 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 2 for for information Pin Number Symbol Type Description 27, 111, 115 Input 42, 79, 125, 163 RAS#, CAS#, WE# CK0–CK3 63, 128 CKE0, CKE1 Input 30, 45,114, 129 S0#–S3# Input 28, 29, 46, 47, 112, 113, 130, 131 DQMB0–DQMB7 Input 39, 122 BA0, BA1 Input 33–38, 117–121, 123, 126 A0–A12 Input 83 SCL Input 165–167 SA0–SA2 Input 2–5, 7–11, 13–17, 19–20, 55–58, 60, 65–67, 69–72, 74–77, 86–89, 91–95, 97–101, 103–104, 139–142, 144, 149–151, 153–156,158–161 82 DQ0–DQ63 Input/ Output Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle) or CLOCK SUSPEND OPERATION (burst access in progress). CKE is synchronous except after the device enters power- down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (twoclock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto prcharge bit (A10) for READ/WRITE commands, to select one location out of the memory arrary in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Data I/O: Data bus. SDA Input/ Output PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN Input Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and out of the presencedetect portion of the module. 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Pin Assignments and Descriptions Table 6: Pin Descriptions (Continued) Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 2 for for information Pin Number Symbol Type 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 21–22, 24–25, 31, 44, 48, 50–53, 61–62, 80, 81, 105– 106, 108–109, 132, 134–137, 145–147, 164 VDD Supply Power Supply: +3.3V ±0.3V. VSS Supply Ground. NC – PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN Description Not Connected: These pins are not connected on these modules. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Functional Block Diagram Functional Block Diagram All resistor values are 10Ω unless otherwise specified. Per industry standard, Micron modules use various component speed grades as referenced in the module part numbering guide at: www.micron.com/numberguide. Standard modules use the following SDRAM device: MT48LC32M8A2TG; Lead-free modules use the following SDRAM device: MT48LC32M8A2P. Contact Micron for Industrial Temp. device information. Figure 3: Single Rank S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ DQ DQ DQ U1 DQ DQ DQ DQ DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQM CS# DQ DQ DQ U2 DQ DQ DQ DQ DQ DQMB5 DQM CS# DQ DQ DQ DQ U3 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS# DQ DQ DQ U4 DQ DQ DQ DQ DQ S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ DQ DQ DQ U7 DQ DQ DQ DQ DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 RAS# CAS# CKE0 WE# A0–A12 BA0 BA1 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM CS# DQ DQ DQ DQ U6 DQ DQ DQ DQ DQMB7 DQM CS# DQ DQ DQ DQ U9 DQ DQ DQ DQ VDD RAS#: SDRAMs CAS#: SDRAMs VSS CKE0: SDRAMs WE#: SDRAMs A0–A12: SDRAMs SCL WP BA0: SDRAMs BA1: SDRAMs DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDRAMs DQM CS# DQ DQ DQ DQ U8 DQ DQ DQ DQ CK0 U1 U2 U3 U4 U5 SDA CK2 U6 U7 U8 U9 SDRAMs SPD U10 A0 A1 A2 SA0 SA1 SA2 3.3pF CK1, CK3 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 6 10pF Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Functional Block Diagram Figure 4: Dual Rank S0# S1# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ DQ DQ DQ U1 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U19 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U3 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U17 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ DQ DQ U2 DQ DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U18 DQ DQ DQ DQ DQM CS# DQ DQ DQ U4 DQ DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U16 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U6 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U14 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U8 DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U12 DQ DQ DQ DQ DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# S3# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ DQ DQ U7 DQ DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U13 DQ DQ DQ DQ DQM CS# DQ DQ DQ U9 DQ DQ DQ DQ DQ DQM CS# DQ DQ DQ DQ U11 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 VDD 10K Ω CKE1 CKE0 CAS# RAS# WE# A0–A12 BA0 BA1 CKE: SDRAMs U11–U19 CKE: SDRAMs U1–U9 CAS#: SDRAMs RAS#: SDRAMs WE#: SDRAMs A0–A12: SDRAMs BA0: SDRAMs BA1: SDRAMs VDD SDRAMs VSS SDRAMs DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U1 U2 U3 U4 U5 CK0 U6 U7 U8 U9 CK2 3.3pF SCL WP U15 U16 U17 U18 U19 CK1 U11 U12 U13 U14 CK3 3.3pF SPD U10 A0 A1 A2 SDA SA0 SA1 SA2 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM General Description General Description The MT8LSDT3264A and MT16LSDT6464A are high-speed CMOS, dynamic randomaccess, 256MB and 512MB memory modules organized in a x64 configuration. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of the clock signals CK). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. SDRAM modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, randomaccess operation. SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 256Mb SDRAM component data sheets. Serial Presence-Detect Operation SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Mode Register Definition SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, Command Inhibit or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one Command Inhibit or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in the Mode Register Definition Diagram. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode register bits M0–M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. The mode register must be loaded when all device banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Burst Length Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the Burst Definition Table. The block is uniquely selected by A1–A9 when the burst length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in Table 7, Burst Definitions, on page 11. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 7, Burst Definitions, on page 11. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Mode Register Definition Figure 5: Mode Register Definition Diagram A12 A11 A10 12 11 10 Reserved* A9 9 A8 8 A6 A7 6 7 WB Op Mode A5 A4 5 A3 4 CAS Latency 3 1 2 BT A1 A2 Address Bus A0 0 Mode Register (Mx) Burst Length *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved M3 Burst Type 0 Sequential 1 Interleaved M6 M5 M4 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6–M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access 10 All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Mode Register Definition Table 7: Burst Definitions Burst Length Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 2 4 8 Full Page (y) A1 0 0 1 1 A2 A1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 n = A0–A9 (location 0 - y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... ...Cn-1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Notes: 1. For full-page accesses: y = 1,024 2. For a burst length of two, A1–A9 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2–A9 select the block of four burst; A0–A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block of eight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and Mode Register bit M3 is ignored. For a full-page burst, the full row is selected and A0–A8 select the starting column. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Mode Register Definition Figure 6: CAS Latency Diagram T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of the accesses within a burst is determined by the burst length, the burst type, and the starting column adress, as shown in Table 7, Burst Definitions, . CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS Latency Table, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Operating Mode The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Commands Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When M9 = 0, the burst length programmed via M0–M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 8: CAS Latency Table Allowable Operating Clock Frequency (MHz) Speed CAS Latency = 2 CAS Latency = 3 -13E -133 -10E ≤ 133 ≤ 100 ≤ 100 ≤ 143 ≤ 133 NA Commands The Truth Table provides a quick reference of available commands. This is followed by written description of each command. For a more detailed descrip-tion of commands and operations, refer to the 256Mb SDRAM component data sheet. Table 9: Truth Table – SDRAM Commands and DQMB Operation CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table Name (Function) CS# COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z ADDR DQ H L L L L L L L RAS# CAS# WE# DQMB X H L H H H L L X H H L L H H L X H H H L L L H X X X L/H L/H X X X X X Bank/Row Bank/Col Bank/Col X Code X X X X X Valid Active X X Notes 3 4, 5 L – – L – – L – – L – – X L H Op-code – – X Active High-Z 6 7 7 1 2 2 Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active. 2. A0–A9 provide column address; A10 HIGH enables the auto-precharge feature (nonpersistent), while A10 LOW disables the auto-precharge feature; BA0-BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 10: Absolute Maximum Ratings Parameter Voltage on VDD, VDDQ Supply Relative to VSS Voltage on Inputs NC or I/O Pins Relative to VSS Operating Temperature TA (Commercial) TA (Industrial) Storage Temperature (plastic) Table 11: MIN MAX Units -1 -1 +4.6 +4.6 V V 0 -40 -55 +65 +85 +150 °C °C °C DC Electrical Characteristics and Operating Conditions – 256MB Module Notes: 1, 5, 6; notes appear on page 19; VDD, VDDQ = +3.3V ±0.3V Parameter/Condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs Command and Address INPUT LEAKAGE CURRENT: Inputs, CKE Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) CK, S# DQ, DQMB OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) Table 12: Symbol MIN MAX Units Notes VDD, VDDQ VIH VIL II 3 2 -0.3 -40 3.6 VDD + 0.3 0.8 40 V V V µA 22 22 33 IOZ -20 -5 -5 20 5 5 µA µA µA 33 VOH VOL 2.4 – – 0.4 V V DC Electrical Characteristics and Operating Conditions – 512MB Module Notes: 1, 5, 6; notes appear on page 19; VDD, VDDQ = +3.3V ±0.3V Parameter/Condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs Command and Address INPUT LEAKAGE CURRENT: Inputs, CKE Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) CK, S# DQ, DQMB OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 14 Symbol MIN MAX Units Notes VDD, VDDQ VIH VIL II 3 2 -0.3 -80 3.6 VDD + 0.3 0.8 80 V V V µA 22 22 33 IOZ -20 -10 -10 20 10 10 µA µA µA 33 VOH VOL 2.4 – – 0.4 V V Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Electrical Specifications Table 13: IDD Specifications and Conditions – 256MB Notes: 1, 5, 6, 11, 13; notes appear on page 19; VDD, VDDQ = +3.3v ±0.3v; SDRAM component values only MAX Parameter/Condition OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; t RC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode;CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active t RFC = tRFC (MIN) AUTO REFRESH CURRENT tRFC = 7.8125µs CKE = HIGH; CS# = HIGH SELF REFRESH CURRENT: CKE ≤ 0.2V Table 14: Symbol -13E -133 -10E Units Notes IDD1 1,080 1,080 1,080 mA IDD2 16 16 16 mA 3, 18,19, 22 22 IDD3 320 320 320 mA IDD4 1,080 1,080 1,080 mA IDD5 IDD6 2,280 28 2,160 28 2,160 28 mA mA IDD7 20 20 20 mA 3, 12, 19, 22 3, 18, 19, 22 3, 12 18, 19, 22, 30 4 IDD Specifications and Conditions – 512MB Notes: 1, 6, 11, 13; notes appear on page 19; VDD, VDDQ = +3.3V ±0.3V; SDRAM component values only MAX Parameter/Condition Symbol -13E -133 -10E Units Notes IDD1a 1,096 1,016 1,016 mA IDD2b 32 32 32 mA 3, 18,19, 22 22 IDD3a 336 336 336 mA OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) AUTO REFRESH CURRENT t RFC = 7.8125µs CKE = HIGH; CS# = HIGH IDD4a 1,096 1,096 1,096 mA IDD5b IDD6b 4,560 56 4,320 56 4,320 56 mA mA SELF REFRESH CURRENT: CKE ≤ 0.2V IDD7b 40 40 40 mA 3, 12, 19, 22 3, 18, 19, 22 3, 12 18, 19, 22, 30 4 a - Value calculated as one module bank in this condition, and all other module banks in power-down mode (IDD2). b - Value calculated reflects all module banks in this condition. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Electrical Specifications Table. 15: Capacitance – 256MB Note 2; notes appear on page 19 Parameter Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2–4, 6, 7 Input Capacitance: DQMB1 Input/Output Capacitance: DQ, CB Table 16: Symbol MIN MAX Units CI1 CI2 CI2 CI3 CI3 CI4 CI5 CI6 CIO 22.5 12.5 13.3 12.5 10 22.5 2.5 5 4 34.2 17.5 17.3 19 15.2 34.2 3.8 7.6 6 pF pF pF pF pF pF pF pF pF Symbol MIN MAX Units CI1 CI2 CI2 CI3 CI3 CI4 CI5 CI6 CIO 45 12.5 13.3 12.5 10 22.5 5 7.5 8 68.4 17.5 17.3 19 15.2 34.2 7.6 11.4 12 pF pF pF pF pF pF pF pF pF Capacitance – 512MB Note 2; notes appear on page 19 Parameter Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2–4, 6, 7 Input Capacitance: DQMB1 Input/Output Capacitance: DQ, CB PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Electrical Specifications Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11, 22; notes appear on page 19 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC Characteristics Parameter Access timefrom CLK (pos.edge) CL=3 CL=2 Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL=3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (8,192 rows) AUTOREFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time WRITE recovery time Exit SELF REFRESH to ACTIVE command PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN -13E Symbol MIN MAX t AC(3) AC(2) t AH t AS tCH t CL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOH N tRAS tRC tRCD tREF tRFC tRP tRRD t WR tXSR MIN 5.4 5.4 t tT -133 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 MAX 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 120,000 1 3 1.8 44 66 20 120,000 1.2 17 0.3 1 CLK +7.5ns 15 75 Units Notes 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 27 6 6 1 3 1.8 50 70 20 64 66 20 15 0.3 1 CLK +7ns 14 67 MAX 1 2 3 3 8 10 1 2 1 2 1 2 5.4 6 64 66 15 14 MIN 5.4 6 5.4 5.4 1 3 1.8 37 60 15 -10E 120,000 64 70 20 20 1.2 0.3 1 CLK +7ns 15 80 1.2 23 23 10 10 28 31 ns ns 7 24 ns ns 25 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Electrical Specifications Table. 18: AC Functional Characteristics Notes: 5, 6, 7, 8, 9, 11, 22; notes appear on page 19 Parameter Symbol READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQMto data high-impedance during READs WRITE command to input data delay Data-into ACTIVE command Data-into PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Lastdata-into PRECHARGE command LOADMODEREGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE CL = 3 command CL = 2 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 18 t CCD CKED t PED t DQD tDQM t DQZ t DWD t DAL t DPL t BDL t CDL tRDL tMRD tROH(3) tROH(2) t -13E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 -133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -10E 1 1 1 0 0 2 0 4 2 1 1 2 2 3 2 Units t CK CK t CK t CK tCK t CK t CK t CK t CK t CK t CK tCK tCK tCK tCK t Notes 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Notes Notes 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; TA = 25°C; pin under test biased at 1.4; f = 1 MHz. 3. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (Commercial Temperature: 0°C ≤ TA +70°C and Industrial Temperature: -40°C ≤ ΤΑ ≤ +85°C). 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for -133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Notes 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and t CK = 7.5ns. 30. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is actually a nominal value and does not result in a fail value. 31. The value of tRAS used in -13E speed grade module SPDs is calculated from tRC - tRP = 45ns. 32. Refer to device data sheet for timing waveforms. 33. Leakage number reflects the worst-case leakage possible through the module pin, not what each memory device contributes. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure 8, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SPD Acknowledge Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 9, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. Figure 7: Data Validity SCL SDA DATA STABLE PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN DATA CHANGE 21 DATA STABLE Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Figure 8: Definition of Start and Stop SCL SDA START BIT Figure 9: STOP BIT Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first Device Type Identifier Memory Area Select Code (two arrays) Protection Register Select Code Table 20: Chip Enable RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW EEPROM Operating Modes Mode Current Address Read RandomAddressRead Sequential Read Byte Write Page Write Figure 10: RW Bit WC Bytes 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 ≥1 1 ≤ 16 Initial Sequence Start, Device Select, RW = 1 Start, Device Select, RW= 0, Address RESTART, Device Select, RW= 1 Similar to Current or Random Address Read START, Device Select, RW = 0 START, Device Select, RW = 0 SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/Condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% POWER SUPPLY CURRENT: SCL Clock frequency = 100 KHz Table 22: Symbol MIN MAX Units VDD VIH VIL VOL ILI ILO ICCS 3 VDD x 0.7 -1 – – – – 3.6 VDD + 0.5 VDD x 0.3 0.4 10 10 30 V V V V µA µA µA ICC Write ICC Read – – 3 1 mA Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V Parameter/Condition SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time Symbol MIN MAX Units Notes tAA 0.9 µs µs 1 tBUF 0.2 1.3 tDH 200 tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA tSU:STO tWRC 100 0.6 0.6 10 ns ns µs µs µs ns µs µs KHz ns µs µs ms 2 2 3 4 Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Table 23: Serial Presence-Detect Matrix VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Description 0 1 2 3 4 5 6 7 8 9 Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Module Banks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK (CAS Latency = 3) 10 25 26 27 SDRAM Access from CLK, tAC (CAS Latency = 3) Module Configuration Type Refresh Rate/Type Sdram Width (Primary SDRAM) Error-checking SDRAM Data Width Minimum Clock Delay From Back-to-Back Random Column Addresses, tCCD Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK (CAS Latency = 2) 10 (-133/-10E) A0 SDRAM Access from CLK, tAC (CAS Latency = 2) SDRAM Cycle Time, tCK, (CAS Latency = 1) SDRAM Access From CLK, tAC, (CAS Latency = 1) Minimum Row Precharge Time, tRP 28 Minimum Row Active to Row Active, tRRD 29 Minimum RAS# to CAS# Delay, tRCD 30 Minimum RAS# Pulse Width, tRAS (See note 1) 31 32 Module Bank Density Command And Address Setup Time, tAS, tCMS 11 12 13 14 15 16 17 18 19 20 21 22 23 24 PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 25 Entry (Version MT8LSDT3264A MT16LSDT6464A 128 256 SDRAM 13 10 1 or 2 64 0 LVTTL 7ns (-13E) 7.5ns (-133) 8ns (-10E) 5.4ns (-13E/-133) 6ns (-10E) NONPARITY 7.8125µs/SELF 8 NONE 1 80 08 04 0D 0A 01 40 00 01 70 75 80 54 60 00 82 08 00 01 80 08 04 0D 0A 02 40 00 01 70 75 80 54 60 00 82 08 00 01 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5ns (13E) 10ns (-133/-10E) 5.4ns (-13E) 6ns (-133/-10E) 8F 04 06 01 01 00 0E 75 A0 54 60 00 00 0F 14 0E 0F 14 0F 14 2D 2C 32 40 15 20 8F 04 06 01 01 00 0E 75 A0 54 60 00 00 0F 14 0E 0F 14 0F 14 2D 2C 32 40 15 20 15ns (-13E) 20ns (-133/-10E) 14ns (-13E) 15ns (-133) 20ns (-10E) 15ns (-13E) 20ns (-133/-10E) 45ns (-13E) 44ns (133) 50ns (-10E) 256MB 1.5ns (-13E/-133) 2ns (-10E) Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Serial Presence-Detect Table 23: Serial Presence-Detect Matrix VDD = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” Byte Entry (Version Description 33 Command And Address Hold Time, 34 Data Signal Input Setup Time, tDS 35 Data Signal Input Hold Time, tDH tAH, tCMH 36-40 41 Reserved Device Minimum Active/Auto-Refresh Time, tRC 42-61 62 63 Reserved SPD Revision Checksum For Bytes 0–62 64 65-71 72 73-90 91 92 93 94 95-98 99-125 126 Manufacturer’s JEDEC ID Code Manufacturer’s JEDEC ID Code (Cont.) Manufacturing Location Module Part Number (ASCII) Pcb Identification Code Identification Code (Cont.) Year of Manufacture In BCD Week of Manufacture In BCD Module Serial Number Manufacturer-specific Data (RSVD) System Frequency 127 0.8ns (-13E/-133) 1ns (-10E) 1.5ns (-13E/-133) 2ns (-10E) 0.8ns (-13E/-133) 1ns (-10E) 60ns (-13E) 66ns (-133) 70ns (10E) REV. 1.2 (-13E) (-133) (-10E) MICRON 0 100 MHz (-13E/ -133/-10E) Sdram Component & Clock Detail MT8LSDT3264A MT16LSDT6464A 08 10 15 20 08 10 00 3C 42 46 00 12 B7 03 4F 2C FF 01 - 06 Variable Data 01-04 00 Variable Data Variable Data Variable Data 08 10 15 20 08 10 00 3C 42 46 00 12 B8 04 50 2C FF 01 - 06 Variable Data 01-04 00 Variable Data Variable Data Variable Data 64 64 AF FF Notes: 1. The value of tRAS used for -13E modules is calculated from tRC - tRP. Actual device spec. value is 37ns. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Module Dimensions Module Dimensions All dimensions are in inches (millimeters); MAX or typical where noted. MIN Figure 11: 168-Pin Single Rank Module FRONT VIEW 0.125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U10 U1 U2 U3 U4 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM Module Dimensions Figure 12: 168-Pin Dual Rank Module 0.157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) FRONT VIEW 0.079 (2.00) R (2X) U10 U1 U3 U2 U4 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U12 U11 U13 U14 U17 U16 PIN 168 U18 U19 PIN 85 ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved.