MT8VDDT1664HG-265B2

128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM DDR SDRAM SMALLOUTLINE DIMM MT8VDDT1664H – 128MB MT8VDDT3264H – 256MB MT8VDDT6464H – 512MB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 200-Pin SODIMM (MO-224) • 200-pin, small-outline, dual in-line memory module (SODIMM) • Fast data transfer rates: PC2100 or PC2700 • Utilizes 266 MT/s and 333 MT/s DDR SDRAM components • 128MB (16 Meg x 64), 256MB (32 Meg x 64), or 512MB (64 Meg x 64) • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2 compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths: 2, 4, or 8 • Auto precharge option • Serial Presence Detect (SPD) with EEPROM • Programmable READ CAS latency • Auto Refresh and Self Refresh Modes • 15.625µs (128MB), 7.8125µs (256MB, 512MB) maximum average periodic refresh interval • Gold edge contacts Table 1: 1.25in. (31.75mm) OPTIONS MARKING • Package 200-pin SODIMM (standard) 200-pin SODIMM (lead-free)1 • Memory Clock, Speed, CAS Latency2 6ns (166 MHz), 333 MT/s, CL = 2.5 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2.5 • PCB 1.25in. (31.75mm) NOTE: G Y -335 -2621 -26A1 -265 1. Contact Micron for product availability. 2. CL = CAS (READ) Latency Address Table Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 128MB 256MB 512MB 4K 4K (A0–A11) 4 (BA0, BA1) 128Mb (16 Meg x 8) 1K (A0–A9) 1 (S0#) 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (32 Meg x 8) 1K (A0–A9) 1 (S0#) 8K 8K (A0–A12) 4 (BA0, BA1) 512Mb (64 Meg x 8) 2K (A0–A9, A11) 1 (S0#) 1 ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MT8VDDT1664HG-335__ MT8VDDT1664HY-335__ MT8VDDT1664HG-262__ MT8VDDT1664HY-262__ MT8VDDT1664HG-26A__ MT8VDDT1664HY-26A__ MT8VDDT1664HG-265__ MT8VDDT1664HY-265__ MT8VDDT3264HG-335__ MT8VDDT3264HY-335__ MT8VDDT3264HG-262__ MT8VDDT3264HY-262__ MT8VDDT3264HG-26A__ MT8VDDT3264HY-26A__ MT8VDDT3264HG-265__ MT8VDDT3264HY-265__ MT8VDDT6464HG-335__ MT8VDDT6464HY-335__ MT8VDDT6464HG-262__ MT8VDDT6464HY-262__ MT8VDDT6464HG-26A__ MT8VDDT6464HY-26A__ MT8VDDT6464HG-265__ MT8VDDT6464HY-265__ MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - tRCD - tRP) 128MB 128MB 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 256MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 64 Meg x 64 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3264HG-265A1. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 3: Pin Assignment (200-Pin SODIMM Front) Table 4: Pin Assignment (200-Pin SODIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0# VSS DQ16 DQ17 VDD DQS2 DQ18 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 DQ27 VDD DNU DNU VSS DNU DNU VDD DNU NC VSS DNU DNU VDD DNU NC NC/A12 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 A9 VSS A7 A5 A3 A1 VDD A10 BA0 WE# S0# NC VSS DQ32 DQ33 VDD DQS4 DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS 151 DQ42 153 DQ43 155 VDD 157 VDD 159 VSS 161 VSS 163 DQ48 165 DQ49 167 VDD 169 DQS6 171 DQ50 173 VSS 175 DQ51 177 DQ56 179 VDD 181 DQ57 183 DQS7 185 VSS 187 DQ58 189 DQ59 191 VDD 193 SDA 195 SCL 197 VDDSPD 199 NC VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS DQ20 DQ21 VDD DM2 DQ22 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 DQ31 VDD DNU DNU VSS DNU DNU VDD DNU NC VSS VSS VDD VDD CKE0 NC A11 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 A8 VSS A6 A4 A2 A0 VDD BA1 RAS# CAS# DNU NC VSS DQ36 DQ37 VDD DM4 DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 DQ46 DQ47 VDD CK1# CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 NC NOTE: Pin 99 is No Connect for 128MB, A12 for 256MB and 512MB. Figure 2: Module Layout Front View Back View U9 U1 PIN 1 U2 U3 (all odd pins) U4 U8 PIN 199 PIN 200 Indicates a VDD or VDDQ pin pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 3 U7 U6 (all even pins) U5 PIN 2 Indicates a VSS pin Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 118, 119, 120 WE#, CAS#, RAS# TYPE DESCRIPTION Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. 35, 37, 158, 160 CK0, CK0#, Input Clock: CK, CK# are differential clock inputs. All address and CK1, CK1#, control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#. 96 CKE0 Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWERDOWN (row ACTIVE in any device bank).CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. 121 S0# Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. 116, 117 BA0, BA1 Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. A0–A11 (128MB) Input Address Inputs: Provide the row address for ACTIVE 99 (256MB, 512MB), 100, 101, 102, 105, 106, 107, A0–A12 (256MB, 512MB) commands, and the column address and auto precharge bit 108, 109, 110, 111, 112, (A10) for READ/WRITE commands, to select one location out 115 of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. 11, 25, 47, 61, 133, 147, DQS0–DQS7 Input/ Data Strobe: Output with READ data, input with WRITE data. 169, 183 Output DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. 12, 26, 48, 62, 134, 148, DM0–DM7 Input Data Write Mask. DM LOW allows WRITE operation. DM HIGH 170, 184 blocks WRITE operation. DM lines do not affect READ operation. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS SYMBOL 5, 6, 7, 8, 13, 14, 17, 18, 19, 20, 23, 24, 29, 30, 31, 32, 41, 42, 43, 44, 49, 50, 53, 54, 55, 56, 59, 60, 65, 66, 67, 68, 127, 128, 129, 130, 135, 136, 139, 140, 141, 142, 145, 146, 151, 152, 153, 154, 163, 164, 165, 166, 171, 172, 175, 176, 177, 178, 181, 182, 187, 188, 189, 190 195 DQ0–DQ63 194, 196, 198 SA0–SA2 193 SDA 1, 2 9, 10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 3, 4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 197 71, 72, 73, 74, 77, 78, 79, 80, 83, 84, 95, 122 85, 97, 99 (128MB), 123, 199, 98, 124, 200 VREF VDD Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presencedetect portion of the module. Supply SSTL_2 reference voltage. Supply Power Supply: +2.5V ±0.2V. VSS Supply Ground. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN SCL VDDSPD DNU NC TYPE DESCRIPTION Input/ Data I/Os: Data bus. Output Supply Serial EEPROM positive power supply: +2.3V to +3.6V. — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. — No Connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Figure 3: Functional Block Diagram S0# DQS0 DQS1 DM0 DM1 DM CS# DQS DQ DQ DQ DQ U1 DQ DQ DQ DQ DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM CS# DQS DQ DQ DQ DQ U5 DQ DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM CS# DQS DQ DQ DQ DQ U6 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ U7 DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ U8 DQ DQ DQ DQ DQS3 DM2 DM3 DM CS# DQS DQ DQ DQ DQ U2 DQ DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS4 DQS5 DM4 DM5 DM CS# DQS DQ DQ DQ DQ U3 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS6 DQS7 DM6 DM7 DM CS# DQS DQ DQ DQ DQ U4 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 BA0, BA1 120 BA0, BA1: DDR SDRAMs A0-A11 (128MB) A0-A11: DDR SDRAMs A0-A12 (256MB, 512MB) A0-A12: DDR SDRAMs RAS# WE# RAS#: DDR SDRAMs CKE0 CKE0: DDR SDRAMs CAS# CAS#: DDR SDRAMs 120 CK1 CK1# WE#: DDR SDRAMs SERIAL PD SCL WP A0 U9 A1 A2 SDA DDR SDRAMs U1, U2, U5, U6 CK0 CK0# DDR SDRAMs U3, U4, U7, U8 VDDSPD SPD/EEPROM VDD DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS SA0 SA1 SA2 NOTE: 1. Unless otherwise stated, all resistors are 22Ω. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT46V64M8TG (512MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M8P (128MB); MT46V32M8P (256MB); MT46V64M8P (512MB) 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM General Description thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheets. The MT8VDDT1664H, MT8VDDT3264H, and MT8VDDT6464H are high-speed CMOS, dynamic random-access, 128MB, 256MB, and 512MB memory modules organized in x64 configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0–A11 select device row (128MB), A0–A12 select device row (256MB, 512MB). The address bits registered coincident with the READ or WRITE command are used to select the device bank and the starting device column location for the burst access. DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 4, Mode Register Definition Diagram, on page 8. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–A11 (128MB) or A7–A12 (256MB, 512MB) specify the operating mode. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Burst Length Figure 4: Mode Register Definition Diagram Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–Ai when the burst length is set to two, by A2–Ai when the burst length is set to four and by A3–Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration; see Note 5 for Figure 6, Burst Definition Table, on page 9). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. 128MB Module Address Bus BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Operating Mode CAS Latency BT Burst Length 0* 0* Mode Register (Mx) * M13 and M12 (BA1and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). 256MB, 512MB Module Address Bus BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 6 5 4 3 2 1 0 CAS Latency BT Burst Length * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). Mode Register (Mx) Burst Length Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Figure 6, Burst Definition Table, on page 9. M3 = 0 M3 = 1 0 0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type M3 0 Sequential 1 Interleaved CAS Latency M6 M5 M4 Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 7, CAS Latency (CL) Table, on page 9, indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 8 Address Bus M2 M1 M0 Burst Type pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN Address Bus M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 6: STARTING COLUMN ADDRESS BURST LENGTH A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 4 8 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND TYPE = INTERLEAVED NOP CL = 2 DQS 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 DQ CK# T0 T1 T2 READ NOP NOP T2n T3 T3n CK COMMAND NOP CL = 2.5 DQS 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A11 (128MB), or A7–A12 (256MB, 512MB) each set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A11 (128MB), or A7 and A9–A12 (256MB, 512MB) each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7–A11 (128MB), or A7–A12 (256MB, 512MB) are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. 1. For a burst length of two, A1–Ai select the two-dataelement block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four-dataelement block; A0–A1 select the first access within the block. 3. For a burst length of eight, A3–Ai select the eight-dataelement block; A0–A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9 (128MB, 256MB) i = 9, 11 (512MB) CAS Latency (CL) Table ALLOWABLE OPERATING CLOCK FREQUENCY (MHZ) SPEED CL = 2 CL = 2.5 -335 -262 -26A -265 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 100 75 ≤ f ≤ 166 75 ≤ f ≤133 75 ≤ f ≤133 75 ≤ f ≤ 133 pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN DON’T CARE Operating Mode NOTE: Table 7: T0 CK# ORDER OF ACCESSES WITHIN A BURST TYPE = SEQUENTIAL 2 Figure 5: CAS Latency Diagram Burst Definition Table Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in Figure 6, Extended Mode Register Definition Diagram, on page 10. The extended mode 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Figure 6: Extended Mode Register Definition Diagram register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. 128MB Module BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 13 12 11 10 9 8 7 6 5 4 Operating Mode 01 11 3 2 1 0 Address Bus Extended Mode Register (Ex) DS DLL 256MB, 512MB Modules BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 4 3 2 1 0 DS DLL Extended Mode Register (Ex) E0 DLL 0 Enable 1 Disable E1 Drive Strength 0 Normal E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 Valid Normal Operation – – – – – – – – – – – All other states reserved NOTE: 1. BA1 and BA0 (E13 and E12 for 128MB or E14 and E13 for 256MB and 512MB) must be “0, 1” to select the Extended Mode Register (vs. the base Mode Register). 2. QFC# is not supported. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Commands Figure 8, Commands Truth Table, and Figure 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: of commands and operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component data sheet. Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved NAME (FUNCTION) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select device bank and activate row) READ (Select device bank and column, and start READ burst) WRITE (Select device bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in device bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# RAS# H L L L L L L L L X H L H H H L L L CAS# WE# X H H L L H H L L X H H H L L L H L ADDR NOTES X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide row address. 3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide column address; A10 HIGH enables the auto precharge feature (non-persistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 11 DM DQS L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Short Circuit Output Current. . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1–5, 14; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ VDD, Vref pin 0V ≤ VIN ≤ 1.35V (All other pins not under test = 0V) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) Command/Address, RAS#, CAS#, WE#, CKE, S# CK, CK# DM DQ, DQS OUTPUT LEAKAGE CURRENT (DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ) OUTPUT LEVELSHigh Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) MIN MAX UNITS NOTES V V V V V V 32, 36 32, 36, 39 6, 39 7, 39 25 25 µA 46 2.3 2.7 2.3 2.7 0.49 × VDDQ 0.51 × VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -16 16 II IOZ -8 -2 -5 8 2 5 µA 46 IOH IOL -16.8 16.8 – – mA mA 33, 34 Table 11: AC Input Operating Conditions Notes: 1–5, 12, 48; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN SYMBOL MIN MAX UNITS NOTES VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 – 0.49 × VDDQ – VREF - 0.310 0.51 × VDDQ V V V 25, 35 25, 35 6 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 12: IDD Specifications and Conditions – 128MB DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 15.625µs SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands IDD0 1,000 880 840 mA 20, 41 IDD1 1,080 960 960 mA 20, 41 IDD2P 24 24 24 mA IDD2F 360 360 360 mA 21, 28, 43 44 IDD3P 200 200 160 mA IDD3N 400 400 360 mA 21, 28, 43 20 IDD4R 1,120 1,040 1,000 mA 20, 41 IDD4W 1,120 1,000 960 mA 20, 41 IDD5 IDD5A IDD6 IDD7 2,120 40 24 2,840 1,760 40 24 2,640 1,760 40 16 2,600 mA mA mA mA 24, 43 24, 43 9 20, 42 pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 13 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 13: IDD Specifications and Conditions – 256MB DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125µs SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands IDD0 1,000 1,000 960 mA 20, 41 IDD1 1,360 1,280 1,160 mA 20, 41 IDD2P 32 32 32 mA IDD2F 400 360 360 mA 21, 28, 43 44 IDD3P 240 200 200 mA IDD3N 480 400 400 mA 21, 28, 43 20 IDD4R 1,400 1,200 1,200 mA 20, 41 IDD4W 1,400 1,200 1,200 mA 20, 41 IDD5 IDD5A IDD6 IDD7 2,040 48 32 3,280 1,880 48 32 2,800 1,880 48 32 2,800 mA mA mA mA 24, 43 24, 43 9 20, 42 pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 14 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 14: IDD Specifications and Conditions – 512MB DDR SDRAM component values only Notes: 1–5, 8, 10, 12, 47; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYM -335 -262 -26A/ -265 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM andDQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125µs SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ or WRITE commands IDD0 1,040 1,040 920 mA 20, 41 IDD1 1,280 1,280 1,160 mA 20, 41 IDD2P 40 40 40 mA IDD2F 360 360 320 mA 21, 28, 43 44 IDD3P 280 280 240 mA IDD3N 400 400 360 mA 21, 28, 43 20 IDD4R 1,320 1,320 1,160 mA 20, 41 IDD4W 1,400 1,240 1,080 mA 20, 41 IDD5 IDD5A IDD6 IDD7 2,320 80 40 3,240 2,320 80 40 3,200 2,240 80 40 2,800 mA mA mA mA 24, 43 24, 43 9 20, 42 pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 15 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 15: Capacitance Note: 11; notes appearon pages 18–21 PARAMETER SYMBOL MIN MAX UNITS CIO CI1 CI2 4 16 8 5 24 12 pF pF pF Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 16: Electrical Characteristics and Recommended AC Operating Conditions DDR SDRAM Components only Notes: 1–5, 12-15, 29; notes appear on pages 18–21; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS PARAMETER -335 -26A/-265 SYMBOL MIN MAX MIN MAX MIN tAC -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 +0.75 0.55 0.55 13 13 -0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 +0.75 0.55 0.55 13 13 -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 +0.75 0.55 0.55 13 13 -0.60 0.35 0.35 +0.60 -0.75 0.35 0.35 +0.75 -0.75 0.35 0.35 +0.75 Access window of DQs from CK/CK# tCH CK high-level width tCL CK low-level width tCK (2.5) Clock cycle time CL = 2.5 tCK (2) CL = 2 tDH DQ and DM input hold time relative to DQS tDS DQ and DM input setup time relative to DQS tDIPW DQ and DM input pulse width (for each input) tDQSCK Access window of DQS from CK/CK# tDQSH DQS input high pulse width tDQSL DQS input low pulse width tDQSQ DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSS Write command to first DQS latching transition tDSS DQS falling edge to CK rising - setup time t DSH DQS falling edge from CK rising - hold time t HP Half clock period tHZ Data-out high-impedance window from CK/ CK# t LZ Data-out low-impedance window from CK/ CK# tIH Address and control input hold time (fast F slew rate) t ISF Address and control input setup time (fast slew rate) tIH Address and control input hold time (slow S slew rate) tIS Address and control input setup time (slow S slew rate) tIPW Address and Control input pulse width (for each input) tMRD LOAD MODE REGISTER command cycle time pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN -262 0.45 0.75 1.25 0.2 0.2 t CH, tCL +0.70 0.5 0.75 1.25 0.2 0.2 t CH, tCL +0.75 0.75 MAX UNITS NOTES ns tCK tCK ns ns ns ns ns 26 26 40, 45 40, 45 23, 27 23, 27 27 ns tCK tCK 0.5 ns 1.25 tCK 0.2 0.2 t CH, tCL +0.75 22, 23 tCK t CK ns ns 30 16, 37 -0.70 -0.75 -0.75 ns 16, 37 0.75 0.90 0.90 ns 12 0.75 0.90 0.90 ns 12 0.80 1 1 ns 12 0.80 1 1 ns 12 2.2 2.2 2.2 ns 12 15 15 ns 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 16: Electrical Characteristics and Recommended AC Operating Conditions (Continued) DDR SDRAM Components only AC CHARACTERISTICS PARAMETER DQ-DQS hold, DQS to first DQ to go nonvalid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command 128MB interval 256MB, 512MB Average periodic refresh interval 128MB 256MB, 512MB Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN -335 SYMBOL tQH MIN -262 MAX MIN MAX -26A/-265 MIN tHP tHP tHP t t t QHS tQHS QHS 0.55 70,000 0.75 120,000 MAX UNITS NOTES QHS 0.75 120,000 ns 22, 23 ns ns 31, 48 t RAS 42 tRAP 15 15 20 ns tRC 60 65 65 ns tRFC tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR na tREFC tVTD tXSRD 40 72 15 15 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 70.3 75 15 15 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 70.3 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 70.3 ns ns ns tCK tCK ns tCK ns tCK ns tCK ns µs µs 15.6 7.8 15.6 7.8 15.6 7.8 µs µs tREFI tXSNR 40 0 75 200 17 0 75 200 0 75 200 43 38 38 18, 19 17 22 21 21 ns ns tCK Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: the fact that they are matched in loading. 12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If the slew rate exceeds 4.5 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns. 13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 14. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW. 15. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 16. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the “Don’t Care” state after completion of the postamble is that the DQS-driven signal should either be HIGH, LOW, or High-Z and that any signal transition within the input switching region must follow valid input requirements. If DQS transitions HIGH, above DC VIH (MIN) then it must not transition LOW, below DC VIH, prior to t DQSH (MIN). 18. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 21. The refresh period is 64ms. This equates to an average refresh rate of 15.625µs (128MB) or 7.8125µs (256MB, 512MB). However, an AUTO REFRESH command must be asserted at least once every 140.6µs (128MB) or 70.3µs (256MB, VTT Output (VOUT) 50Ω Reference Point 30pF 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (ACV) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM 22. 23. 24. 25. 512MB); burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 7, Derating Data Valid Window (tQH - tDQSQ), shows the derating curves for duty cycles ranging between 50/50 and 45/55. Each byte lane has a corresponding DQS. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: 26. 27. 28. 29. a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be added to tDS and t DH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4 V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns. VDD must not vary more than 4 percent if CKE is not active while any device bank is active. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. Figure 7: Derating Data Valid Window (tQH - tDQSQ) 3.8 3.750 3.700 3.6 3.650 3.600 3.550 3.500 3.4 3.450 3.400 3.350 3.2 3.300 3.250 tCK NA -335 @ = 6ns -262/-26A/-265 @ tCK = 10ns -262/-26A/-265 @ tCK = 7.5ns ns 3.0 2.8 2.6 2.500 2.463 2.425 2.388 2.4 2.350 2.313 2.275 2.238 2.200 2.163 2.2 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM 30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during device bank active. 31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. 32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V minimum, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 8, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. t HZ (MAX) will prevail over tDQSCK (MAX) + t RPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. t RPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between the VTT supply and the input pin. 34. 35. 36. 37. 38. 39. Figure 8: Pull-Down Characteristics Figure 9: Pull-Up Characteristics 160 0 140 -20 m imu Max IOUT (mA) 80 Nominal low 60 -80 -100 Nom inal low -120 -140 Minimum 40 Nominal high -60 high IOUT (mA) Nominal 100 Maximum -40 120 Mi nim -160 20 um -180 0 -200 0.0 0.5 1.0 1.5 2.0 2.5 0.0 VOUT (V) pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM 40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 41. Random addressing changing and 50 percent of data changing at every transfer. 42. Random addressing changing and 100 percent of data changing at every transfer. 43. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. 44. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 45. 46. 47. 48. 21 address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic low. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Initialization Figure 10: Initialization Flow Diagram To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power to VDD and VDDQ. 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 200µs. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). 10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 11. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. 12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 13. Issue a PRECHARGE ALL command. 14. Wait at least tRP time, only NOPs or DESELECT commands are allowed. 15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. 20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL Reset) and any READ command. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN Step 22 1 VDD and VDDQ Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 200us 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for tRP time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 Configure Load Mode Register and reset DLL 12 Assert NOP or DESELECT for tMRD time 13 PRECHARGE ALL 14 Assert NOP or DESELECT for tRP time 15 Issue AUTO REFRESH command 16 Assert NOP or DESELECT commands for tRFC 17 Issue AUTO REFRESH command 18 Assert NOP or DESELECT for tRFC time 19 Optional LMR command to clear DLL bit 20 Assert NOP or DESELECT for tMRD time 21 DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data Validity, and Figure 12, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 13, Acknowledge Response from Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 11: Data Validity Figure 12: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 13: Acknowledge Response from Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 17: EEPROM Device Select Code Most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 18: EEPROM Operating Modes MODE RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ≥1 1 ≤ 16 Current Address Read Random Address Read Sequential Read Byte Write Page Write INITIAL SEQUENCE START, Device Select, RW = ‘1’ START, Device Select, RW = ‘0’, Address reSTART, Device Select, RW = ‘1’ Similar to Current or Random Address Read START, Device Select, RW = ‘0’ START, Device Select, RW = ‘0’ Figure 14: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 19: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SYMBOL SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VSS or VDD POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz VDDSPD VIH VIL VOL ILI ILO ISB ICC MIN MAX 2.3 3.6 VDDSPD × 0.7 VDDSPD + 0.5 -1 VDDSPD × 0.3 – 0.4 – 10 – 10 – 30 – 2 UNITS V V V V µA µA µA mA Table 20: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL MIN MAX UNITS NOTES tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA t SU:STO tWRC 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 21: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix BYTE DESCRIPTION ENTRY (VERSION) 0 1 2 3 Number of SPD Bytes Used by Micron Total Number of Bytes in SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK, CAS Latency = 2.5 (see note 1) 128 256 DDR SDRAM 12, 13 80 08 07 0C 80 08 07 0D 80 08 07 0D 10, 11 0A 0A 0B 1 64 0 SSTL 2.5V 6ns(-335) 7ns (-262/-26A) 7.5ns (-265) 0.7ns (-335) 0.75ns (-262/-26A/-265) None 15.62µs, 7.8µs/SELF 8 01 40 00 04 60 70 75 70 75 00 80 08 01 40 00 04 60 70 75 70 75 00 82 08 01 40 00 04 60 70 75 70 75 00 82 08 None 00 00 00 1 clock 01 01 01 2, 4, 8 4 0E 04 0E 04 0E 04 2, 2.5 0 1 Unbuffered/Diff. Clock Fast/Concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265) 0.7ns (-335) 0.75ns (-262/-26A/-265) N/A 0C 01 02 20 C0 75 A0 70 75 00 0C 01 02 20 C0 75 A0 70 75 00 0C 01 02 20 C0 75 A0 70 75 00 N/A 00 00 00 18ns (-335) 15ns (-262) 20ns (-26A/-265) 12ns (-335) 15ns (-262/-26A/-265) 18ns (-335) 15ns (-262) 20ns (-26A/-265) 48 3C 50 30 3C 48 3C 50 48 3C 50 30 3C 48 3C 50 48 3C 50 30 3C 48 3C 50 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SDRAM Access From Clock, tAC, CAS Latency = 2.5 Module Configuration Type Refresh Rate/Type SDRAM Device Width (Primary DDR SDRAM) Error-checking DDR SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on DDR SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK, CAS Latency =2 SDRAM Access from Clock, tAC, CAS Latency = 2 SDRAM Cycle Time, tCK, CAS Latency = 1.5 SDRAM Access from CK , tAC, CAS Latency = 1.5 Minimum Row Precharge Time, tRP (see note 4) Minimum Row Active to Row Active, tRRD Minimum RAS# to CAS# Delay, tRCD (see note 4) pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 26 MT8VDDT1664H MT8VDDT3264H MT8VDDT6464H Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Table 21: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear following matrix BYTE 30 31 32 33 34 35 36-40 41 42 43 44 45 46 47 48–61 62 63 64 65-71 72 73-90 91 92 93 94 95-98 99-127 DESCRIPTION ENTRY (VERSION) t 42ns (-335) 45ns (-262/-26A/-265) 128MB, 256MB, 512MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 0.8ns (-335) 1.0ns (-262/-26A/-265) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.45ns (-335) Data/Data Mask Input Hold Time, tDH 0.5ns (-262/-26A/-265) Reserved 60ns (-335/-262) Min Active Auto Refresh Time tRC 65ns (-26A/-265) 72ns (-335) Minimum Auto Refresh to Active/ 75ns (-262-26A/-265) Auto Refresh Command Period, tRFC 12ns (-335) SDRAM Device Max Cycle Time, tCKMAX 13ns (-262-26A/265) 0.45ns (-335) SDRAM Device Max DQS-DQ Skew 0.5ns (-262/-26A/-265) Time, tDQSQ 0.55ns (-335) SDRAM Device Max Read Data Hold 0.75ns (-262/-26A/-265) Skew Factor, tQHS Reserved DIMM Height Reserved Release 1.0 SPD Revision -335 Checksum for Bytes 0-62 -262 -26A -265 MICRON Manufacturer’s JEDEC ID Code (Continued) Manufacturer’s JEDEC IDCode 01–12 Manufacturing Location Module Part Number (ASCII) 1–9 PCB Identification Code 0 Identification Code (Continued) Year of Manufacture in BCD Week of Manufacturein BCD Module Serial Number Manufacturer-Specific Data (RSVD) Minimum RAS# Pulse Width, RAS, (see note 2) Module Rank Density Address and Command Setup Time, t IS, (see note 3) Address and Command Hold Time, t IH, (see note 3) Data/Data Mask Input Setup Time, tDS MT8VDDT1664H MT8VDDT3264H MT8VDDT6464H 2A 2D 20 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 04 D7 04 34 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data – 2A 2D 40 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 27 BA E7 17 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data – 2A 2D 80 80 A0 80 A0 45 50 45 50 00 3C 41 48 4B 30 34 2D 32 55 75 00 01 00 10 68 FB 28 58 2C FF 01–0C Variable Data 01–09 00 Variable Data Variable Data Variable Data – NOTE: 1. Value for -262 and -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns. 2. The value of tRAS used for -262/-26A/-265 modules is calculated from tRC - tRP. Actual device spec. value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. 4. The value of tRP, tRCD, and tRAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 128MB, 256MB, 512MB (x64, SR) 200-PIN DDR SODIMM Figure 15: 200-Pin DDR SODIMM Dimensions FRONT VIEW 0.150 (3.80) MAX 2.667(67.75) 2.656 (67.45) U9 0.079 (2.00) R (2X) U1 U2 U3 U4 1.256 (31.90) 1.244 (31.60) 0.071 (1.80) (2X) 0.787 (20.00) TYP 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.043 (1.10) 0.035 (0.90) 0.039 (0.99) TYP 0.018 (0.46) TYP 0.024 (0.61) TYP PIN 199 PIN 1 2.504 (63.60) TYP BACK VIEW U8 U7 U6 U5 PIN 200 PIN 2 NOTE: MAX All dimensions are in inches (millimeters); MIN or typical where noted. Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temrperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef8092973f, source: 09005aef80921669 DD8C16_32_64x64HG.fm - Rev. B 9/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved.