MT9HVF6472PKZ-667G1

512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Features DDR2 SDRAM VLP Mini-RDIMM MT9HVF6472PKZ – 512MB MT9HVF12872PKZ – 1GB Features Figure 1: 244-Pin VLP Mini-RDIMM Module height: 18.2mm (0.72 in) • 244-pin, very low profile, mini registered dual in-line memory module • Fast data transfer rates: PC2-6400, PC2-5300, PC2-4200, or PC2-3200 • 512MB (64 Meg x 72) or 1GB (128 Meg x 72) • Supports ECC error detection and correction • VDD = V DDQ = 1.8V • VDDSPD = 1.7–3.6V • JEDEC-standard 1.8V I/O (SSTL_18-compatible) • Differential data strobe (DQS, DQS#) option • 4n-bit prefetch architecture • Multiple internal device banks for concurrent operation • Programmable CAS latency (CL) • Posted CAS additive latency (AL) • WRITE latency = READ latency - 1 tCK • Programmable burst lengths: 4 or 8 • Adjustable data-output drive strength • 64ms, 8192-cycle refresh • On-die termination (ODT) • Serial presence-detect (SPD) with EEPROM • Gold edge contacts • Single rank • Halogen-free Options Marking • Parity • Operating temperature – Commercial (0°C ≤ T A ≤ +70°C) – Industrial (-40°C ≤ T A ≤ +85°C)1 • Package – 244-pin DIMM (halogen-free) • Frequency/CL2 – 2.5ns @ CL = 5 (DDR2-800) – 2.5ns @ CL = 6 (DDR2-800) – 3.0ns @ CL = 5 (DDR2-667) Notes: P None I Z -80E -800 -667 1. Contact Micron for industrial temperature module offerings. 2. CL = CAS (READ) latency; registered mode will add one clock cycle to CL. Table 1: Key Timing Parameters Data Rate (MT/s) tRCD tRP tRC (ns) (ns) (ns) 12.5 12.5 55 15 15 55 400 15 15 55 553 400 15 15 55 400 400 15 15 55 Speed Grade Industry Nomenclature CL = 6 CL = 5 CL = 4 CL = 3 -80E PC2-6400 800 800 533 400 -800 PC2-6400 800 667 533 400 -667 PC2-5300 – 667 553 -53E PC2-4200 – – -40E PC2-3200 – – PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Features Table 2: Addressing 512MB 1GB 8K 8K 16K A[13:0] 16K A[13:0] Device bank address 4 BA[1:0] 8 BA[2:0] Device configuration 512Mb (64 Meg x 8) 1Gb (128 Meg x 8) 1K A[9:0] 1K A[9:0] 1 S0# 1 S0# Refresh count Row address Column address Module rank address Table 3: Part Numbers and Timing Parameters – 512MB Base device: MT47H64M8,1 512Mb DDR2 SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT9HVF6472PK(I)Z-80E__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT9HVF6472PK(I)Z-800__ 512MB 64 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 MT9HVF6472PK(I)Z-667__ 512MB 64 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) Table 4: Part Numbers and Timing Parameters – 1GB Base device: MT47H128M8,1 1Gb DDR2 SDRAM Module Part Number2 Density MT9HVF12872PK(I)Z-80E__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 5-5-5 MT9HVF12872PK(I)Z-800__ 1GB 128 Meg x 72 6.4 GB/s 2.5ns/800 MT/s 6-6-6 MT9HVF12872PK(I)Z-667__ 1GB 128 Meg x 72 5.3 GB/s 3.0ns/667 MT/s 5-5-5 Notes: 1. Data sheets for the base devices can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9HVF12872KZ-80EM1. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Assignments Pin Assignments Table 5: Pin Assignments 244-Pin VLP Mini-RDIMM Front 244-Pin VLP Mini-RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 32 VSS 63 VDDQ 94 DQS5# 123 VSS 154 DQ28 185 A3 216 NF/ RDQS5# 2 VSS 33 DQ24 64 A2 95 DQS5 124 DQ4 155 DQ29 186 A1 217 VSS 3 DQ0 34 DQ25 65 VDD 96 VSS 125 DQ5 156 VSS 187 VDD 218 DQ46 4 DQ1 35 VSS 66 VSS 97 DQ42 126 VSS 157 DM3/ RDQS3 188 CK0 219 DQ47 5 VSS 36 DQS3# 67 VSS 98 DQ43 127 DM0/ RDQS0 158 NF/ 189 RDQS3# CK0# 220 VSS 6 DQS0# 37 DQS3 68 Par_In 99 VSS 128 NF/ 159 RDQS0# 7 DQS0 38 VSS 69 VDD 100 DQ48 129 VSS 8 VSS 39 DQ26 70 A10 101 DQ49 130 9 DQ2 40 DQ27 71 BA0 102 VSS 10 DQ3 41 VSS 72 VDD 103 SA2 VSS 190 VDD 221 DQ52 160 DQ30 191 A0 222 DQ53 DQ6 161 DQ31 192 BA1 223 VSS 131 DQ7 162 VSS 193 VDD 224 RFU 132 VSS 163 CB4 194 RAS# 225 RFU 11 VSS 42 CB0 73 WE# 104 NC 133 DQ12 164 CB5 195 VDDQ 226 VSS 12 DQ8 43 CB1 74 VDDQ 105 VSS 134 DQ13 165 VSS 196 S0# 227 DM6/ RDQS6 13 DQ9 44 VSS 75 CAS# 106 DQS6# 135 VSS 166 DM8/ RDQS8 197 VDDQ 228 NF/ RDQS6# 14 VSS 45 DQS8# 76 VDDQ 107 DQS6 136 DM1/ RDQS1 167 NF/ 198 RDQS8# ODT0 229 VSS 15 DQS1# 46 DQS8 77 NC 108 VSS 137 NF/ 168 RDQS1# 16 DQS1 47 VSS 78 NC 109 DQ50 138 VSS 17 VSS 48 CB2 79 VDDQ 110 DQ51 139 18 RESET# 49 CB3 80 NC 111 VSS 19 NC 50 VSS 81 VSS 112 DQ56 VSS 199 A13 230 DQ54 169 CB6 200 VDD 231 DQ55 RFU 170 CB7 201 NC 232 VSS 140 RFU 171 VSS 202 VSS 233 DQ60 141 VSS 172 NC 203 DQ36 234 DQ61 20 VSS 51 NC 82 DQ32 113 DQ57 142 DQ14 173 VDDQ 204 DQ37 235 VSS 21 DQ10 52 VDDQ 83 DQ33 114 VSS 143 DQ15 174 NC 205 VSS 236 DM7/ RDQS7 22 DQ11 53 CKE0 84 VSS 115 DQS7# 144 VSS 175 VDD 206 DM4/ RDQS4 237 NF/ RDQS7# 23 VSS 54 VDD 85 DQS4# 116 DQS7 145 DQ20 176 NC 207 NF/ 238 RDQS4# 24 DQ16 55 NF/BA21 86 DQS4 117 VSS 146 DQ21 177 NC 208 25 DQ17 56 Err_Out# 87 VSS 118 DQ58 147 VSS 178 VDDQ 209 26 VSS 57 VDDQ 88 DQ34 119 DQ59 148 DM2/ RDQS2 179 A12 210 27 DQS2# 58 A11 89 DQ35 120 VSS 149 NF/ 180 RDQS2# A9 211 28 DQS2 59 A7 90 VSS 121 SA0 150 VDD 212 PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 3 VSS 181 VSS VSS 239 DQ62 DQ38 240 DQ63 DQ39 241 VSS VSS 242 SDA DQ44 243 SCL Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Assignments Table 5: Pin Assignments (Continued) 244-Pin VLP Mini-RDIMM Front 244-Pin VLP Mini-RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 29 VSS 60 VDD 91 DQ40 151 DQ22 182 A8 213 DQ45 30 DQ18 61 A5 92 DQ41 152 DQ23 183 A6 214 VSS 31 DQ19 62 A4 93 VSS 153 VSS 184 VDDQ 215 DM5/ RDQS5 Note: PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 122 SA1 244 VDDSPD 1. Pin 55 is NF for 512MB, BA2 for 1GB. 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR2 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 6: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. CKx, CK#x Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DDR2 SDRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR2 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can be used during power-up to ensure that CKE is LOW and DQ are High-Z. S#x Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the SPD EEPROM address range on the I2C bus. SCL Input Serial clock for SPD EEPROM: Used to synchronize communication to and from the SPD EEPROM on the I2C bus. CBx I/O Check bits. Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQS#x I/O Data strobe: Travels with the DQ and is used to capture DQ at the DRAM or the controller. Output with read data; input with write data for source synchronous operation. DQS# is only used when differential data strobe mode is enabled via the LOAD MODE command. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Pin Descriptions Table 6: Pin Descriptions (Continued) Symbol Type SDA I/O Serial data: Used to transfer addresses and data into and out of the SPD EEPROM on the I2C bus. RDQSx, RDQS#x Output Redundant data strobe (x8 devices only): RDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When RDQS is enabled, RDQS is output with read data only and is ignored during write data. When RDQS is disabled, RDQS becomes data mask (see DMx). RDQS# is only used when RDQS is enabled and differential data strobe mode is enabled. Err_Out# Description Output Parity error output: Parity error found on the command and address bus. (open drain) VDD/VDDQ Supply Power supply: 1.8V ±0.1V. The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply SPD EEPROM power supply: 1.7–3.6V. VREF Supply Reference voltage: VDD/2. VSS Supply Ground. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. NU – Not used: These pins are not used in specific module configurations/operations. RFU – Reserved for future use. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS0# DQS4 DQS4# DM4/DQS13 NF/DQS13# DQS0 DQS0# DM0/DQS9 NF/DQS9# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# RDQS# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U1 NF/ CS# DQS DQS# RDQS# U6 SCL WP A0 VSS DQS5 DQS5# DM5/DQS14 NF/DQS14# DQS1 DQS1# DM1/DQS10 NF/DQS10# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# RDQS# DQS2 DQS2# DM2/DQS11 NF/DQS11# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 U13 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# RDQS# U9 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ U2 CK0 CK0# DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# RDQS# U3 DQS8 DQS8# DM8/DQS17 NF/DQS17# DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 SDA PLL DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM DDR2 SDRAM REGISTER x2 NF/ CS# DQS DQS# RDQS# U7 VDDSPD DQS7 DQS7# DM7/DQS16 NF/DQS16# DQS3 DQS3# DM3/DQS12 NF/DQS12# A2 SA0 SA1 SA2 U5 RESET# DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 A1 NF/ CS# DQS DQS# RDQS# DQS6 DQS6# DM6/DQS15 NF/DQS15# DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 U10 Serial PD NF/ CS# DQS DQS# RDQS# U8 Serial PD VDD DDR2 SDRAM VDDQ DDR2 SDRAM VREF DDR2 SDRAM VSS DDR2 SDRAM U4, U11 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM/ RDQS DQ DQ DQ DQ DQ DQ DQ DQ NF/ CS# DQS DQS# RDQS# U12 S0# BA[2:0] A[13;0] RAS# CAS# WE# CKE0 ODT0 PAR_IN RESET# PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 7 R E G I S T E R S RS0#: DDR2 SDRAM RBA[2/1:0]: DDR2 SDRAM RA[13:0]: DDR2 SDRAM RRAS#: DDR2 SDRAM RCAS#: DDR2 SDRAM RWE#: DDR2 SDRAM RCKE0: DDR2 SDRAM RODT0: DDR2 SDRAM ERR_OUT Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM General Description General Description DDR2 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 4 or 8-bank DDR2 SDRAM devices. DDR2 SDRAM modules use DDR architecture to achieve high-speed operation. DDR2 architecture is essentially a 4n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR2 SDRAM module effectively consists of a single 4n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR2 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM device during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. DDR2 SDRAM modules operate from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Serial Presence-Detect EEPROM Operation DDR2 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. Register and PLL Operation DDR2 SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR2 SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL) on the module receives and redrives the differential clock signals (CK, CK#) to the DDR2 SDRAM devices. The registers and PLL minimize system and clock loading. PLL clock timing is defined by JEDEC specifications and ensured by use of the JEDEC clock reference board. Registered mode will add one clock cycle to CL. Parity Operations The registering clock driver can accept a parity bit from the system’s memory controller, providing even parity for the control, command, and address bus. Parity errors are flagged on the Err_Out# pin. Systems not using parity are expected to function without issue if Par_In and Err_Out# are left as no connects (NC) to the system. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the DRAM devices on the module. This is a stress rating only, and functional operation of the module at these or any other conditions above those indicated in each device’s data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD/VDDQ VDD/VDDQ supply voltage relative to VSS –0.5 2.3 V VIN, VOUT Voltage on any pin relative to VSS –0.5 2.3 V –5 5 µA Input leakage current; Any input 0V ≤ VIN ≤ VDD; Command/address VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under RAS#, CAS#, WE#, S#, test = 0V) CKE, ODT, BA II CK, CK# IOZ IVREF TA Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQs and ODT are disabled –250 250 DM –5 5 DQ, DQS, DQS# –5 5 µA –18 18 µA VREF leakage current; VREF = valid VREF level Module ambient operating temperature Commercial Industrial 1 TC DDR2 SDRAM component case operating temperature2 Notes: PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN Commercial Industrial 0 70 °C –40 85 °C 0 85 °C –40 95 °C 1. Refresh rate is required to double when 85°C < TC ≤ 95°C. 2. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR2 component data sheets. Component specifications are available on Micron's Web site. Module speed grades correlate with component speed grades. Table 8: Module and Component Speed Grades DDR2 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -1GA -187E -80E -25E -800 -25 -667 -3 -53E -37E -40E -5E Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM IDD Specifications IDD Specifications Table 9: IDD Specifications and Conditions – 512MB (Die Revision G) Values shown for MT47H64M8 DDR2 SDRAM only and are computed from values specified in the 512Mb (64 Meg x 8) component data sheet -80E Parameter/Condition Symbol -800 -667 Units Operating one bank active-precharge current: tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address DD bus inputs are switching; Data bus inputs are switching IDD0 585 540 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 675 630 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2P 63 63 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 216 198 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2N 252 225 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD3P 162 135 mA 81 81 mA Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 297 270 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1125 1035 mA Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1080 990 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5 855 810 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid DD DD DD commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 1350 1260 mA PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM IDD Specifications Table 10: IDD Specifications and Conditions – 1GB (Die Revision H) Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet -80E Parameter/Condition Symbol -800 -667 Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address DD bus inputs are switching; Data bus inputs are switching IDD0 585 540 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 675 630 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2P 63 63 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 216 216 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2N 252 216 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD3P 180 135 mA 90 90 mA Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 297 270 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1125 1035 mA Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1080 990 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5 1305 1260 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid DD DD DD commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 1890 1665 mA PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM IDD Specifications Table 11: IDD Specifications and Conditions – 1GB (Die Revision M) Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet -80E Parameter/Condition Symbol -800 -667 Units Operating one bank active-precharge current:tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (I ); CKE is HIGH, S# is HIGH between valid commands; Address DD bus inputs are switching; Data bus inputs are switching IDD0 585 540 mA Operating one bank active-read-precharge current: IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data pattern is same as IDD4W IDD1 675 630 mA Precharge power-down current: All device banks idle; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD2P 90 90 mA Precharge quiet standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs are floating IDD2Q 216 216 mA Precharge standby current: All device banks idle; tCK = tCK (IDD); CKE is HIGH, S# is HIGH; Other control and address bus inputs are switching; Data bus inputs are switching IDD2N 252 216 mA Active power-down current: All device banks open; tCK = tCK (IDD); CKE is LOW; Other control and address bus inputs are stable; Data bus inputs are floating IDD3P 270 252 mA 180 180 mA Fast PDN exit MR[12] = 0 Slow PDN exit MR[12] = 1 Active standby current: All device banks open; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD3N 297 270 mA Operating burst write current: All device banks open; Continuous burst writes; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4W 1125 1035 mA Operating burst read current: All device banks open; Continuous burst reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching; Data bus inputs are switching IDD4R 1080 990 mA Burst refresh current:tCK = tCK (IDD); REFRESH command at every tRFC (IDD) interval; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus inputs are switching; Data bus inputs are switching IDD5 1395 1350 mA Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus inputs are floating; Data bus inputs are floating IDD6 63 63 mA Operating bank interleave read current: All device banks interleaving reads; IOUT = 0mA; BL = 4, CL = CL (IDD), AL = tRCD (IDD) - 1 × tCK (IDD); tCK = tCK (IDD), tRC = tRC (I ), tRRD = tRRD (I ), tRCD = tRCD (I ); CKE is HIGH, S# is HIGH between valid DD DD DD commands; Address bus inputs are stable during deselects; Data bus inputs are switching IDD7 1890 1665 mA PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Register and PLL Specifications Table 12: Register Specifications SSTU32866 devices or equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH(DC) Control, command, address SSTL_18 VREF(DC) + 125 VDDQ + 250 mV DC low-level input voltage VIL(DC) Control, command, address SSTL_18 0 VREF(DC) - 125 mV AC high-level input voltage VIH(AC) Control, command, address SSTL_18 VREF(DC) + 250 – mV AC low-level input voltage VIL(AC) Control, command, address SSTL_18 – VREF(DC) - 250 mV Output high voltage VOH Parity output LVCMOS 1.2 – V Output low voltage VOL Parity output LVCMOS – 0.5 V Input current II All pins VI = VDD or VSS – ±0.5 µA Static standby IDD All pins RESET# = VSSQ (IO = 0) – 100 µA Static operating IDD All pins RESET# = VSS; VI = VIH(AC) or VIL(DC) IO = 0 – 40 mA Dynamic operating (clock tree) IDDD N/A RESET# = VDD; VI = VIH(DC) or VIL(AC), IO = 0; CK and CK# switching 50% duty cycle – Varies by manufacturer µA Dynamic operating (per each input) IDDD N/A RESET# = VDD; VI = VIH(AC) or VIL(DC), IO = 0; CK and CK# switching 50% duty cycle; One data in/out switching at tCK/2, 50% duty cycle – Varies by manufacturer µA Input capacitance (per device, per pin) CIN All inputs except RESET# VI = VREF ±250mV; VDD = 1.8V 2.5 3.5 pF Input capacitance (per device, per pin) CIN RESET# VI = VDD or VSS Varies by manufacturer Varies by manufacturer pF Note: PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC standard JESD82. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Register and PLL Specifications Table 13: PLL Specifications CU877 device or equivalent Parameter Symbol Pins Condition Min Max Units DC high-level input voltage VIH RESET# LVCMOS 0.65 × VDD – V DC low-level input voltage VIL RESET# LVCMOS – 0.35 × VDD V Input voltage (limits) VIN RESET#, CK, CK# – - 0.3 VDD + 0.3 V DC high-level input voltage VIH CK, CK# Differential input 0.65 × VDD – V DC low-level input voltage VIL CK, CK# Differential input – 0.35 × VDD V Input differential-pair cross voltage VIX CK, CK# Differential input (VDDQ/2) - 0.15 (VDD/2) + 0.15 V Input differential voltage VID(DC) CK, CK# Differential input 0.3 VDD + 0.4 V Input differential voltage VID(AC) CK, CK# Differential input 0.6 VDD + 0.4 V RESET# VI = VDD or VSS –10 10 µA CK, CK# VI = VDD or VSS –250 250 µA Input current II Output disabled current IODL RESET# = VSS; VI = VIH(AC) or VIL(DC) 100 – µA Static supply current IDDLD CK = CK# = LOW – 500 µA Dynamic supply IDD N/A CK, CK# = 270 MHz, all outputs open (not connected to PCB) – 300 mA Input capacitance CIN Each input VI = VDD or VSS 2 3 pF Table 14: PLL Clock Driver Timing Requirements and Switching Characteristics Parameter Symbol Min Max Units tL – 15 μs slr(i) 1.0 4.0 V/ns SSC modulation frequency – 30 33 kHz SSC clock input frequency deviation – 0.0 –0.5 % PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz Stabilization time Input clock slew rate Note: PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 1. PLL timing and switching specifications are critical for proper operation of the DDR2 DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information is available in JEDEC standard JESD82. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Serial Presence-Detect Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Table 15: SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 1.7 3.6 V Input high voltage: logic 1; All inputs VIH VDDSPD × 0.7 VDDSPD + 0.5 V Input low voltage: logic 0; All inputs VIL –0.6 VDDSPD × 0.3 V Output low voltage: IOUT = 3mA Supply voltage VOL – 0.4 V Input leakage current: VIN = GND to VDD ILI 0.1 3 µA Output leakage current: VOUT = GND to VDD ILO 0.05 3 µA Standby current ISB 1.6 4 µA Power supply current, READ: SCL clock frequency = 100 kHz ICCR 0.4 1 mA Power supply current, WRITE: SCL clock frequency = 100 kHz ICCW 2 3 mA Table 16: SPD EEPROM AC Operating Conditions Parameter/Condition Symbol Min Max Units Notes SCL LOW to SDA data-out valid tAA 0.2 0.9 µs 1 Time bus must be free before a new transition can start tBUF 1.3 – µs Data-out hold time tDH 200 – ns SDA and SCL fall time tF – 300 ns 2 SDA and SCL rise time tR – 300 ns 2 Data-in hold time tHD:DAT 0 – µs Start condition hold time tHD:STA 0.6 – µs tHIGH 0.6 – µs tI – 50 ns tLOW 1.3 – µs tSCL – 400 kHz Data-in setup time tSU:DAT 100 – ns Start condition setup time tSU:STA 0.6 – µs Stop condition setup time tSU:STO 0.6 – µs tWRC – 10 ms Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SCL clock frequency WRITE cycle time Notes: PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 3 4 1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a restart condition or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistance, and the EEPROM does not respond to its slave address. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM Module Dimensions Module Dimensions Figure 3: 244-Pin DDR2 VLP Mini-RDIMM Front view 3.8 (0.15) MAX 82.127 (3.233) 81.873 (3.223) 1.0 (0.039) R X2 U1 U2 U5 U3 U6 U7 U4 1.8 (0.071) D X2 10.0 (0.394) TYP 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP 0.6 (0.024) Pin 1 TYP 0.5 (0.02) R 0.45 (0.018) TYP 42.9 (1.689) TYP Pin 122 18.3 (0.72) 18.1(0.713) 1.1 (0.043) 0.9 (0.035) 78.0 (3.071) TYP Back view 45° X4 U10 U8 U9 U13 U12 U11 3.3 (0.13) TYP 3.6 (0.142) TYP Pin 244 3.2 (0.126) TYP 33.6 (1.323) TYP Notes: Pin 123 38.4 (1.512) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for complete design dimensions. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef83d09b45 hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved.