MT9LSDT872G-10E

ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SYNCHRONOUS DRAM MODULE FEATURES • JEDEC-standard 168-pin, dual in-line memory module (DIMM) • PC133- and PC100-compliant • Registered inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • Utilizes 133 MHz and 125 MHz SDRAM components • ECC-optimized pinout • 64MB (8 Meg x 72) and 128MB (16 Meg x 72) • Single +3.3V ±0.3V power supply • Fully synchronous; all signals registered on positive edge of PLL clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge and Auto Refresh Modes • Self Refresh Mode • 64ms, 4,096-cycle refresh • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) MT9LSDT872, MT9LSDT1672 For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/datasheet.html PIN ASSIGNMENT (FRONT VIEW) 168-PIN DIMM OPTIONS • Package 168-pin DIMM (gold) • Frequency/CAS Latency* 133 MHz/CL = 2 (7.5ns, 133 MHz SDRAMs) 133 MHz/CL = 3 (7.5ns, 133 MHz SDRAMs) 100 MHz/CL = 2 (8ns, 125 MHz SDRAM) MARKING G -13E -133 -10E *Device latency only; extra clock cycle required due to input register. KEY SDRAM COMPONENT TIMING PARAMETERS MODULE MARKING -13E -133 -10E SPEED GRADE -7E -75 -8E CAS LATENCY 2 3 2 ACCESS TIME 5.4ns 5.4ns 6ns SETUP TIME 1.5ns 1.5ns 2ns HOLD TIME 0.8ns 0.8ns 1ns PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 SYMBOL V SS DQ0 DQ1 DQ2 DQ3 V DD DQ4 DQ5 DQ6 DQ7 DQ8 V SS DQ9 DQ10 DQ11 DQ12 DQ13 V DD DQ14 DQ15 CB0 CB1 V SS NC NC V DD WE# DQMB0 DQMB1 S0# DNU V SS A0 A2 A4 A6 A8 A10 BA1 V DD V DD CK0 PIN SYMBOL 43 V SS 44 DNU 45 S2# 46 DQMB2 47 DQMB3 48 DNU 49 V DD 50 NC 51 NC 52 CB2 53 CB3 54 V SS 55 DQ16 56 DQ17 57 DQ18 58 DQ19 59 V DD 60 DQ20 61 NC 62 NC 63 RFU (CKE1) 64 V SS 65 DQ21 66 DQ22 67 DQ23 68 V SS 69 DQ24 70 DQ25 71 DQ26 72 DQ27 73 V DD 74 DQ28 75 DQ29 76 DQ30 77 DQ31 78 V SS 79 CK2 80 NC 81 WP 82 SDA 83 SCL 84 V DD PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 SYMBOL V SS DQ32 DQ33 DQ34 DQ35 V DD DQ36 DQ37 DQ38 DQ39 DQ40 V SS DQ41 DQ42 DQ43 DQ44 DQ45 V DD DQ46 DQ47 CB4 CB5 V SS NC NC V DD CAS# DQMB4 DQMB5 RFU (S1#) RAS# V SS A1 A3 A5 A7 A9 BA0 A11 V DD CK1 RFU (A12) PIN 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 SYMBOL V SS CKE0 RFU (S3#) DQMB6 DQMB7 RFU (A13) V DD NC NC CB6 CB7 V SS DQ48 DQ49 DQ50 DQ51 V DD DQ52 NC NC REGE V SS DQ53 DQ54 DQ55 V SS DQ56 DQ57 DQ58 DQ59 V DD DQ60 DQ61 DQ62 DQ63 V SS CK3 NC SA0 SA1 SA2 V DD NOTE: Symbols in parentheses are not used on these modules but may be used for other modules in this product family. They are for reference only. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs PART NUMBERS PART NUMBER MT9LSDT872G-13E__ MT9LSDT872G-133__ MT9LSDT872G-10E__ MT9LSDT1672G-13E__ MT9LSDT1672G-133__ MT9LSDT1672G-10E__ CONFIGURATION 8 Meg x 72 8 Meg x 72 8 Meg x 72 16 Meg x 72 16 Meg x 72 16 Meg x 72 SYSTEM BUS SPEED 133 MHz 133 MHz 100 MHz 133 MHz 133 MHz 100 MHz NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9LSDT1672G-133B1 clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation. These modules are designed to operate in 3.3V, lowpower memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 64Mb and 128Mb SDRAM data sheets. GENERAL DESCRIPTION The MT9LSDT872 and MT9LSDT1672 are high-speed CMOS, dynamic random-access, 64MB and 128MB memories organized in a x72 configuration. These modules use internally configured quad-bank SDRAMs with a synchronous interface (all signals are registered on the positive edge of clock signals CK0). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. These modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. These modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every PLL AND REGISTER OPERATION These modules can be operated in either registered mode (REGE pin HIGH), where the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (REGE pin LOW) where the input signals pass through the register/buffer to the SDRAM devices on the same clock. A phase-lock loop (PLL) on the modules is used to redrive the clock signals to the SDRAM devices to minimize system clock loading (CK0 is connected to the PLL, and CK1, CK2 and CK3 are terminated). SERIAL PRESENCE-DETECT OPERATION These modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide eight unique DIMM/EEPROM addresses. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL SCL SDA DATA STABLE DATA CHANGE DATA STABLE SDA START BIT STOP BIT Figure 1 Data Validity Figure 2 Definition of Start and Stop SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge Figure 3 Acknowledge Response from Receiver 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs FUNCTIONAL BLOCK DIAGRAM MT9LSDT872 (64MB) AND MT9LSDT1672 (128MB) RS0# RDQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ0 DQ1 U2 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U12 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB6 DQM CS# DQ0 DQ1 U3 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U4 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 RDQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQM CS# DQ0 DQ1 U10 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U11 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 RDQMB4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 RDQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM CS# DQ0 DQ1 U13 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM CS# DQ0 DQ1 U14 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 RS2# RDQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 RDQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 U5, U7 RAS# CAS# CKE0 WE# A0-A11 BA0 BA1 S0#, S2# DQMB0-DQMB7 PLL CLK 10K VDD REGE U8 R E G I S T E R RRAS#: SDRAMs U0-U8 RCAS#: SDRAMs U0-U8 RCKE0: SDRAMs U0-U8 RWE#: SDRAMs U0-U8 RA0-RA11: SDRAMs U0-U8 RBA0: SDRAMs U0-U8 RBA1: SDRAMs U0-U8 RS0#, RS2# RDQMB0-RDQMB7 VDD SCL WP 47K SPD U9 A0 A1 A2 SA0 SA1 SA2 VSS SDA CK1-CK3 CK0 U6 PLL 12pF SDRAM x 3 SDRAM x 3 SDRAM x 3 REGISTER x 2 12pF SDRAMs U0-U8 SDRAMs U0-U8 U0-U8 = MT48LC8M8A2TG SDRAMs for 64MB U0-U8 = MT48LC16M8A2TG SDRAMs for 128MB NOTE: 1. All resistor values are 10 ohms unless otherwise specified. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs PIN DESCRIPTIONS PIN NUMBERS 27, 111, 115 42, 79, 125, 163 128 SYMBOL WE#, CAS#, RAS# CK0-CK3 CKE0 TYPE Input Input Input DESCRIPTION Command Inputs: WE#, RAS#, and CAS# (along with S0#, S2#) define the command being entered. Clock: CK0 is distributed through an on-board PLL to all devices. CK1-CK3 are terminated. Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the CK0 signal. Deactivating the clock provides POWER-DOWN and SELF REFRESH operation (all banks idle) or CLOCK SUSPEND operation (burst access in progress). CKE0 is synchronous except after the device enters power-down and self refresh modes, where CKE0 becomes asynchronous until after exiting the same mode. The input buffers, including CK0, are disabled during power-down and self refresh modes, providing low standby power. Chip Select: S0#, S2# enable (registered LOW) and disable (registered HIGH) the command decoder. All commands are masked when S0#, S2# are registered HIGH. S0#, S2# are considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. Address Inputs: A0-A11 are sampled during the ACTIVE command (row-address A0-A11) and READ/WRITE command (column-address A0-A8/A9, with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if both banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Write Protect: Serial presence-detect hardware write protect. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Register Enable. Data I/Os: Data bus. 30, 45 S0#, S2# Input 28-29, 46-47, 112-113, 130-131 DQMB0DQMB7 Input 122, 39 33, 117, 34, 118, 35, 119, 36, 120, 37, 121, 38, 123 BA0, BA1 A0-A11 Input Input 81 83 165-167 147 2-5, 7-11, 13-17, 19-20, 55-58, 60, 65-67, 69-72, 74-77, 86-89, 91-95, 97-101, 103-104, 139-142, 144, 149-151, 153-156, 158-161 21-22,0 52-53, 105-106, 136-137 WP SCL SA0-SA2 REGE DQ0-DQ63 Input Input Input Input Input/ Output CB0-CB7 Input/ Output Check Bits. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs PIN DESCRIPTIONS (continued) PIN NUMBERS 82 SYMBOL SDA TYPE Input/ Output Supply DESCRIPTION Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. Power Supply: +3.3V ±0.3V. 6, 18, 26, 40-41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 63, 114, 126, 129, 132 31, 44, 48 V DD VSS Supply Ground. RFU DNU – – Reserved for Future Use: These pins are not connected on this module but are assigned pins on other SDRAM versions. Do Not Use: These pins are not connected on this module but are assigned pins on the compatible DRAM version. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX BYTE 0 1 2 3 4 5 6 7 8 9 DESCRIPTION NUMBER OF BYTES USED BY MICRON TOTAL NUMBER OF SPD MEMORY BYTES MEMORY TYPE NUMBER OF ROW ADDRESSES NUMBER OF COLUMN ADDRESSES NUMBER OF BANKS MODULE DATA WIDTH MODULE DATA WIDTH (continued) MODULE VOLTAGE INTERFACE LEVELS SDRAM CYCLE TIME, tCK (CAS LATENCY = 3) SDRAM ACCESS FROM CLOCK, tAC (CAS LATENCY = 3) MODULE CONFIGURATION TYPE REFRESH RATE/TYPE SDRAM WIDTH (PRIMARY SDRAM) ERROR-CHECKING SDRAM DATA WIDTH MIN. CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES, tCCD BURST LENGTHS SUPPORTED NUMBER OF BANKS ON SDRAM DEVICE CAS LATENCIES SUPPORTED CS LATENCY WE LATENCY SDRAM MODULE ATTRIBUTES SDRAM DEVICE ATTRIBUTES: GENERAL SDRAM CYCLE TIME, tCK (CAS LATENCY = 2) SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 2) SDRAM CYCLE TIME, tCK (CAS LATENCY = 1) SDRAM ACCESS FROM CLK, tAC (CAS LATENCY = 1) MINIMUM ROW PRECHARGE TIME, tRP ENTRY (VERSION) 128 256 SDRAM 12 9 or 10 1 72 0 LVTTL 7 (-13E) 7.5 (-133) 8 (-10E) 5.4 (-13E/-133) 6 (-10E) ECC 15.6µs/SELF 8 8 1 1, 2, 4, 8, PAGE 4 2, 3 0 0 -13E/-133 -10E 0E 7.5 (-13E) 10 (-133/-10E) 5.4 (-13E) 6 (-10E) – – 15 (-13E) 20 (-133/-10E) 14 (-13E) 14 (-13E) 15 (-133) 20 (-10E) 15 (-13E) 20 (-133/-10E) 37 (-13E) MT9LSDT872 80 08 04 0C 09 01 48 00 01 70 75 80 54 60 02 80 08 08 01 8F 04 06 01 01 1F 16 0E 75 A0 54 60 00 00 0F 14 0E 0E 0F 14 0F 14 25 MT9LSDT1672 80 08 04 0C 0A 01 48 00 01 70 75 80 54 60 02 80 08 08 01 8F 04 06 01 01 1F 16 0E 75 A0 54 60 00 00 0F 14 0E 0E 0F 14 0F 14 25 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 MINIMUM ROW ACTIVE TO ROW ACTIVE, tRRD MINIMUM RAS# TO CAS# DELAY, tRCD 29 NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT MATRIX (continued) BYTE 30 DESCRIPTION MINIMUM RAS# PULSE WIDTH, (tRAS MODULE = tRC - tRP) MODULE BANK DENSITY COMMAND AND ADDRESS SETUP TIME, tAS, tCMS COMMAND AND ADDRESS HOLD TIME, tAH, tCMH DATA SIGNAL INPUT SETUP TIME, tDS DATA SIGNAL INPUT HOLD TIME, tDH RESERVED SPD REVISION CHECKSUM FOR BYTES 0-62 ENTRY (VERSION) 45 (-13E) 44 (-133) 50 (-10E) 64MB/128MB 1.5 (-13E/-133) 2 (-10E) 0.8 (--13E/133) 1 (-10E) 1.5 (-13E/-133) 2 (-10E) 0.8 (-13E/-133) 1 (-10E) REV. 1.2 -13E -133 -10E MICRON MT9LSDT872 2D 2C 32 10 15 20 08 10 15 20 08 10 00 12 88 C5 0D 2C FF 01 02 03 04 05 06 07 08 09 xx 31 32 33 34 35 36-61 62 63 64 65-71 72 MANUFACTURER’S JEDEC ID CODE MANUFACTURER’S JEDEC ID CODE (CONT.) MANUFACTURING LOCATION MT9LSDT1672 2D 2C 32 20 15 20 08 10 15 20 08 10 00 12 99 CE 16 2C FF 01 02 03 04 05 06 07 08 09 xx 73-90 91 MODULE PART NUMBER (ASCII) PCB IDENTIFICATION CODE 92 93 94 95-98 99-125 126 127 IDENTIFICATION CODE (CONT.) YEAR OF MANUFACTURE IN BCD WEEK OF MANUFACTURE IN BCD MODULE SERIAL NUMBER MANUFACTURER-SPECIFIC DATA (RSVD) SYSTEM FREQUENCY SDRAM COMPONENT AND CLOCK DETAIL 1 2 3 4 5 6 7 8 9 0 01 02 03 04 05 06 07 08 09 00 xx xx xx 01 02 03 04 05 06 07 08 09 00 xx xx xx 100/133 MHz – 64 8F – 64 8F NOTE: 1. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW.” 2. x = Variable Data. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs Commands Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. For a more detailed description of commands and operations refer to the 64Mb, 128Mb x4, x8, x16 SDRAM datasheets. TRUTH TABLE 1 – COMMANDS AND DQMB OPERATION (Note: 1) NAME (FUNCTION) COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z NOTE: 1. 2. 3. 4. 5. 6. 7. 8. CS# RAS# CAS# WE# DQMB H L L L L L L L L – – X H L H H H L L L – – X H H L L H H L L – – X H H H L L L H L – – X X X L/H8 L/H8 X X X X L H ADDR X X Bank/Row Bank/Col X Code X Op-Code – – DQs NOTES X X X X Active X X X Active High-Z 5 6, 7 2 8 8 3 4 4 Bank/Col Valid CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register. A0-A11 provide row address, and BA0, BA1 determine which bank is made active. A0-A8/A9 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0, BA1 are “Don’t Care.” This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus Table 1 Burst Definition Burst Length 2 1 2 4 8 12 11 10 9 8 7 6 5 4 3 BT 2 1 0 Mode Register (Mx) Unused Reserved* WB Op Mode CAS Latency Burst Length Starting Column Address A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0-9/8 (location 0-y) Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn+1, Cn+2 Cn+3, Cn+4... …Cn-1, Cn… 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 *Should program M11, M10 = “0, 0” to ensure compatibility with future devices. M2 M1 M0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Burst Length M3 = 0 1 2 4 8 Reserved Reserved Reserved Full Page M3 = 1 4 Reserved Reserved Reserved Reserved M3 0 1 Burst Type Sequential Interleaved 8 M6 M5 M4 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 0 1 0 1 CAS Latency Reserved 2 3 Reserved Reserved Reserved Reserved Full Page (y) Not supported M8 0 - M7 0 - M6-M0 Defined - Operating Mode Standard Operation All other states reserved M9 0 1 Write Burst Mode Programmed Burst Length Single Location Access Figure 4 Mode Register Definition NOTE: 1. For full-page accesses: y = 1,024 (128MB), y = 512 (64MB) 2. For a burst length of two, A1-A9/A8 select the block of two burst; A0 selects the starting column within the block. 3. For a burst length of four, A2-A9/A8 select the block of four burst; A0-A1 select the starting column within the block. 4. For a burst length of eight, A3-A9/A8 select the block of eight burst; A0-A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0-A9/A8 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0-A9/A8 select the unique column to be accessed, and Mode Register bit M3 is ignored. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply Relative to VSS . -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS ...................................... -1V to +4.6V Operating Temperature, TA (ambient) ... 0°C to +70°C Storage Temperature (plastic) .......... -55°C to +125°C Power Dissipation ................................................ 18W *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDD OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) SYMBOL VDD VIH VIL II1 MIN 3 2 -0.5 -5 MAX 3.6 VDD + 0.3 0.8 5 UNITS NOTES V V V µA 3 3 4 IOZ VOH VOL -5 2.4 – 5 – 0.4 µA V V NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. VIH overshoot: VIH (MAX) = VDD + 2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 10ns, and the pulse width cannot be greater than one third of the cycle rate. 4. Input leakage values based on register electrical characteristics, VDD = 3.6V. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs IDD SPECIFICATIONS AND CONDITIONS (Notes: 1-4) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN); CAS latency = 3 STANDBY CURRENT: Power-Down Mode; CKE = LOW; All banks idle STANDBY CURRENT: Active Mode; S0#, S2# = HIGH; CKE = HIGH;All banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All banks active; CAS latency = 3 AUTO REFRESH CURRENT: CKE = HIGH; S0#, S2# = HIGH tRC = tRC (MIN); MAX SYMBOL IDD1 IDD2 IDD3 SIZE 64MB 128MB 64MB 128MB 64MB 128MB IDD4 IDD5 IDD6 IDD7 64MB 128MB 64MB 128MB 64MB 128MB 64MB 128MB -13E 1,125 1,440 18 18 405 450 1,350 1,485 2,070 2,970 27 27 9 18 -133 1,035 1,350 18 18 405 450 1,260 1,350 1,890 2,790 27 27 9 18 -10E 855 1,260 18 18 315 360 1,080 1,260 1,710 2,430 27 27 9 18 mA mA mA mA 10 5, 6, 7, 8 5, 6, 7, 8, 9 UNITS mA mA mA NOTES 5, 6, 7, 8 8 5, 7, 8, 9 CL = 3 tRC = 15.625µs; CL = 3 SELF REFRESH CURRENT: CKE ≤ 0.2V NOTE: 1. All voltages referenced to VSS. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC timing and IDD test have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 4. IDD specifications are tested after the device is properly initialized. 5. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 6. The IDD current will decrease as the CAS latency is reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced. 7. Address transitions average one transition every two clocks. 8. tCK = 7ns for -13E; tCK = 7.5ns for -133; tCK = 10ns for -10E. 9. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 10. Enables on-chip refresh and address counters. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs CAPACITANCE PARAMETER Input Capacitance: A0-A11, BA0, BA1, RAS#, CAS#, WE# Input Capacitance: S0#, S2#, CKE0, DQMB0#-DQMB7# Input Capacitance: CK0 Input Capacitance: REGE Input Capacitance: SCL, SA0-SA2, WP Input/Output Capacitance: DQ0-DQ63, CB0-CB7, SDA NOTE: This parameter is sampled. VDD = +3.3V; f = 1 MHz. SYMBOL CI1 CI2 CI3 CI4 CI5 CI O MAX UNITS 8 8 6 5 12 8 pF pF pF pF pF pF SDRAM COMPONENT* AC ELECTRICAL CHARACTERISTICS (Notes: 2, 3, 4, 5, 6, 7) AC CHARACTERISTICS PARAMETER Access time from CLK (positive edge) Address hold time Address setup time CLK high level width CLK low level width Clock cycle time -13E MAX 5.4 5.4 -133 MIN MAX 5.4 6 MIN -10E MAX 6 6 UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns ns – ns ns NOTES 8 CL = 3 CL = 2 CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (4,096 cycles) ` AUTO REFRESH PERIOD PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time SYMBOL tAC tAC tAH t AS tCH t CL t CK t CK tCKH t CKS tCMH t CMS tDH t DS t HZ t HZ t LZ t OH t OH N tRAS tRC tRCD t REF tRFC tRP tRRD tT t WR MIN 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 1 2.7 1.8 37 60 15 66 15 14 0.3 1 CLK + 7ns 14 67 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 1 2.7 1.8 44 66 20 66 20 15 0.3 1 CLK + 7.5ns 15 75 1 2 3 3 8 10 1 2 1 2 1 2 6 7 1 3 1.8 50 70 20 70 20 20 0.3 1 CLK + 7ns 15 80 9 9 10 10 11 120,000 120,000 120,000 64 64 64 1.2 1.2 1.2 12 13 14 Exit SELF REFRESH to ACTIVE command t XSR *Specifications for the SDRAM components used on the module. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs NOTE: 1. This parameter is sampled. VDD = +3.3V; f = 1 MHz. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is ensured. 6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z. 11. AC timing and IDD test have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 24. There will be an added one-clock latency at the system level due to the register requiring an added clock cycle. 26. Auto precharge mode only. The precharge timing budget (tRP) begins 7.5ns/7ns after the first clock delay, after the last WRITE is executed. 27. Precharge mode only. 28. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 30. tAC for -133 at CL = 3 with no load is 4.6ns and is guaranteed by design. 32. Parameter guaranteed by design. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs AC FUNCTIONAL CHARACTERISTICS (Notes: 1-7) PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to PRECHARGE command Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command SYMBOL tCCD tCKED tPED tDQD tDQM tDQZ tDWD tDAL tDPL tBDL tCDL tRDL tMRD tROH tROH -133 1 1 1 0 0 2 0 5 2 1 1 2 2 3 2 -13E/-10E UNITS tCK 1 tCK 1 tCK 1 tCK 0 tCK 0 tCK 2 tCK 0 tCK 4 tCK 2 tCK 1 tCK 1 tCK 2 tCK 2 tCK 3 tCK 2 NOTES 8 9 9 8 8 8 8 10, 11 11, 12 8 8 11, 12 13 8 8 CL = 3 CL = 2 NOTE: 1. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ +70°C) is ensured. 2. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 3. AC characteristics assume tT = 1ns. 4. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. Outputs measured at 1.5V with equivalent load: Q 50pF 6. AC timing and IDD test have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1ns, then the timing is referenced at VIL (MAX) and VIL (MIN) and no longer at the 1.5V crossover point. 7. There will be an added one-clock latency at the system level due to the register requiring an added clock cycle. 8. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 9. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 10. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 11. Based on tCK = 143 MHz for -13E, tCK = 133 MHz for -133, 100 MHz for -10E. 12. Timing actually specified by tWR. 13. JEDEC and PC100 specify three clocks. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V +10% POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL V DD V IH VIL V OL I LI I LO I SB I DD MIN 3 -1 – – – – – MAX 3.6 VDD x 0.3 0.4 10 10 30 2 UNITS V V V V µA µA µA mA VDD x 0.7 VDD + 0.5 SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (Note: 1) (VDD = +3.3V ±0.3V) PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA tHIGH tI tLOW tR tSCL tSU:DAT tSU:STA tSU:STO tWRC MIN 0.3 4.7 300 0 4 4 100 4.7 1 100 250 4.7 4.7 10 MAX 3.5 UNITS µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms NOTES 300 2 NOTE: 1. All voltages referenced to VSS. 2. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs SPD EEPROM tF t LOW t HIGH tR SCL t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT UNDEFINED SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS SYMBOL tAA tBUF tDH tF tHD:DAT tHD:STA MIN 0.3 4.7 300 0 4 MAX 3.5 UNITS µs µs ns ns µs µs SYMBOL tHIGH tLOW tR tSU:DAT tSU:STA tSU:STO MIN 4 4.7 250 4.7 4.7 MAX UNITS µs µs µs ns µs µs 1 300 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc. ADVANCE 8, 16 MEG x 72 REGISTERED SDRAM DIMMs 168-PIN DIMM (64MB/128MB) FRONT VIEW 5.256 (133.50) 5.244 (133.20) .157 (4.00) MAX .079 (2.00) R (2X) 1.505 (38.23) 1.495 (37.97) .118 (3.00) (2X) .118 (3.00) .700 (17.78) .250 (6.35) .118 (3.00) .054 (1.37) .046 (1.17) .039 (1.00) R(2X) .040 (1.02) .050 (1.27) PIN 1 4.550 (115.57) PIN 84 BACK VIEW .128 (3.25) (2X) .118 (3.00) 1.661 (42.18) 2.625 (66.68) PIN 168 PIN 85 NOTE: 1. All dimensions in inches (millimeters) MAX or typical where noted. MIN 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992 Micron is a registered trademark of Micron Technology, Inc. 8, 16 Meg x 72 PC133/PC100 Registered SDRAM DIMMs ZM28_3.p65 – Rev. 4/00 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©1999, Micron Technology, Inc.