16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Features
DDR4 SDRAM LRDIMM
MTA36ASF2G72LZ – 16GB
Features
Figure 1: 288-Pin LRDIMM (MO-309, R/C-B)
• DDR4 functionality and operations supported as
defined in the component data sheet
• 288-pin, command/address/control registered, data
buffered dual in-line, load reduced memory module(LRDIMM)
• Fast data transfer rates: PC4-2400, or PC4-2133
• 16GB (2 Gig x 72)
• VDD = 1.20V (NOM)
• VPP = 2.5V (NOM)
• VDDSPD = 2.5V (NOM)
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Low-power auto self refresh (LPASR)
• Data bus inversion (DBI) for data bus
• On-die internal, adjustable, V REFDQ generation
• Dual-rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 16 internal banks; 4 groups of 4 banks each
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Multiplexed command, and address bus
• Terminated control, command and address bus
Module height: 31.25mm (1.23in)
Options
Marking
• Operating temperature
– Commercial (0°C ≤ T OPER ≤ 95°C)
• Package
– 288-pin DIMM (halogen-free)
• Frequency/CAS latency
– 0.83ns @ CL = 17 (DDR4-2400)
– 0.93ns @ CL = 15 (DDR4-2133)
None
Z
-2G3
-2G1
Table 1: Key Timing Parameters
Data Rate (MT/s)
Industry
Speed NomenGrade clature
CL =
20,
CL =
19
CL =
18
CL =
17
CL =
16
CL =
15
CL =
14
CL = CL =
13
12
CL =
11
CL =
10
tRCD
tRC
(ns)
(ns)
-2G6
PC4-2666
2666
2666
2400
2133
2133
1866
1866 1600
–
1333
–
14.16 14.16
46.16
-2G4
PC4-2400
–
2400
2400
2400
2133
1866
1866 1600
1600
–
1333
13.32 13.32
45.32
-2G3
PC4-2400
–
2400
2400
2133
2133
1866
1866 1600
1600
1333
–
14.16 14.16
46.16
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
1
CL = 9 (ns)
tRP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Features
Table 1: Key Timing Parameters (Continued)
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
CL =
20,
CL =
19
-2G1
PC4-2133
–
CL =
18
CL =
17
CL =
16
CL =
15
CL =
14
CL = CL =
13
12
CL =
11
CL =
10
–
–
2133
2133
1866
1866 1600
1600
–
tRCD
CL = 9 (ns)
1333
13.5
tRP
(ns)
tRC
(ns)
13.5
46.5
Table 2: Addressing
Parameter
16GB
Row address
64K A[15:0]
Column address
1K A[9:0]
Device bank group address
4 BG[1:0]
Device bank address per group
4 BA[1:0]
Device configuration
4Gb (1 Gig x 4), 16 banks
Module rank address
2 CS_n[1:0]
Table 3: Part Numbers and Timing Parameters – 16GB Modules
Base device: MT40A1G4,1 4Gb DDR4 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MTA36ASF2G72LZ-2G3__
16GB
2 Gig x 72
19.2 GB/s
0.83ns/2400 MT/s
17-17-17
MTA36ASF2G72LZ-2G1__
16GB
2 Gig x 72
17.0 GB/s
0.93ns/2133 MT/s
15-15-15
Notes:
1. The data sheet for the base device can be found on micron.com.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions.
Consult factory for current revision codes. Example: MTA36ASF2G72LZ-2G3A1.
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asf36c2gx72lz.pdf - Rev. D 9/15 EN
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© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Pin Assignments
Pin Assignments
Table 4: Pin Assignments
288-Pin DDR4 LRDIMM Front
288-Pin DDR4 LRDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
NC
37
VSS
73
VDD
109
Vss
145
NC
181
DQ29
217
VDD
253
DQ41
2
VSS
38
DQ24
74
CK0_t
110
DQS14_t
146
VREFCA
182
VSS
218
CK1_t
254
VSS
3
DQ4
39
VSS
75
CK0_c
111
DQS14_c
147
VSS
183
DQ25
219
CK1_c
255
DQS5_c
4
VSS
40
DQS12_t
76
VDD
112
VSS
148
DQ5
184
VSS
220
VDD
256
DQS5_t
5
DQ0
41
DQS12-c
77
VTT
113
DQ46
149
VSS
185
DQS3_c
221
VTT
257
VSS
6
VSS
42
VSS
78
EVENT_n
114
VSS
150
DQ1
186
DQS3_t
222
PARITY
258
DQ47
7
DQS9_t
43
DQ30
79
A0
115
DQ42
151
VSS
187
VSS
223
VDD
259
VSS
8
DQS09_c
44
VSS
80
VDD
116
VSS
152
DQS0_c
188
DQ31
224
BA1
260
DQ43
9
VSS
45
DQ26
81
BA0
117
DQ52
153
DQS0_t
189
VSS
225
A10_AP
261
VSS
10
DQ6
46
VSS
82
RAS_n/
A16
118
VSS
154
VSS
190
DQ27
226
VDD
262
DQ53
11
VSS
47
CB4
83
VDD
119
DQ48
155
DQ7
191
VSS
227
NC
263
VSS
12
DQ2
48
VSS
84
S0_n
120
VSS
156
VSS
192
CB5
228
WE_n/
A14
264
DQ49
13
VSS
49
CB0
85
VDD
121
DQS15_t
157
DQ3
193
VSS
229
VDD
265
VSS
14
DQ12
50
VSS
86
CAS_n/
A15
122
DQS15_c
158
VSS
194
CB1
230
NC
266
DQS6_c
15
VSS
51
DQS17_t
87
ODT0
123
VSS
159
DQ13
195
VSS
231
VDD
267
DQS6_t
16
DQ8
52
DQS17_c
88
VDD
124
DQ54
160
VSS
196
DQS8_c
232
A13
268
VSS
17
VSS
53
VSS
89
S1_n
125
VSS
161
DQ9
197
DQS8_t
233
VDD
269
DQ55
18
DQS10_t
54
CB6
90
VDD
126
DQ50
162
VSS
198
VSS
234
A17
270
VSS
19
DQS10_c
55
VSS
91
ODT1
127
VSS
163
DQS1_c
199
CB7
235
NF
271
DQ51
20
VSS
56
CB2
92
VDD
128
DQ60
164
DQS1_t
200
VSS
236
VDD
272
VSS
21
DQ14
57
VSS
93
S2_n
129
VSS
165
VSS
201
CB3
237
S3_n
273
DQ61
22
VSS
58
RESET_n
94
VSS
130
DQ56
166
DQ15
202
VSS
238
SA2
274
VSS
23
DQ10
59
VDD
95
DQ36
131
VSS
167
VSS
203
CKE1
239
VSS
275
DQ57
24
VSS
60
CKE0
96
VSS
132
DQS16_t
168
DQ11
204
VDD
240
DQ37
276
VSS
25
DQ20
61
VDD
97
DQ32
133
DQS16_c
169
VSS
205
NC
241
VSS
277
DQS7_c
26
VSS
62
ACT_n
98
VSS
134
VSS
170
DQ21
206
VDD
242
DQ33
278
DQS7_t
27
DQ16
63
BG0
99
DQS13_t
135
DQ62
171
VSS
207
BG1
243
VSS
279
VSS
28
VSS
64
VDD
100
DQS13_c
136
VSS
172
DQ17
208
ALERT_n
244
DQS4_c
280
DQ63
29
DQS11_t
65
A12
101
VSS
137
DQ58
173
VSS
209
VDD
245
DQS4_t
281
VSS
30
DQS11_c
66
A9
102
DQ38
138
VSS
174
DQS2_c
210
A11
246
VSS
282
DQ59
31
VSS
67
VDD
103
Vss
139
SA0
175
DQS2_t
211
A7
247
DQ39
283
VSS
32
DQ22
68
A8
104
DQ34
140
SA1
176
VSS
212
VDD
248
VSS
284
VDDSPD
33
VSS
69
A6
105
VSS
141
SCL
177
DQ23
213
A5
249
DQ35
285
SDA
34
DQ18
70
VDD
106
DQ44
142
VPP
178
VSS
214
A4
250
VSS
286
VPP
35
VSS
71
A3
107
VSS
143
VPP
179
DQ19
215
VDD
251
DQ45
287
VPP
36
DQ28
72
A1
108
DQ40
144
NC
180
VSS
216
A2
252
VSS
288
VPP
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for DDR4
modules. All pins listed may not be supported on this module. See Functional Block Diagram for pins specific to this module.
Table 5: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVATE commands and the column address for
READ/WRITE commands in order to select one location out of the memory array in the respective bank (A10/AP, A12/BC_n, WE_n/A14, CAS_n/A15, and RAS_n/A16 have additional functions;
see individual entries in this table). The address inputs also provide the op-code during the
MODE REGISTER SET command. A17 is only defined for x4 SDRAM.
A10/AP
Input
Auto precharge: A10 is sampled during READ and WRITE commands to determine whether an
auto precharge should be performed on the accessed bank after a READ or WRITE operation
(HIGH = auto precharge; LOW = no auto precharge). A10 is sampled during a PRECHARGE command to determine whether the precharge applies to one bank (A10 LOW) or all banks (A10
HIGH). If only one bank is to be precharged, the bank is selected by the bank group and bank
addresses.
A12/BC_n
Input
Burst chop: A12/BC_n is sampled during READ and WRITE commands to determine if burst
chop (on-the-fly) will be performed (HIGH = no burst chop; LOW = burst- chopped). See Command Truth Table in the DDR4 component data sheet.
ACT_n
Input
Command input: ACT_n defines the ACTIVATE command being entered along with CS_n. The
input into RAS_n/A16, CAS_n/A15, and WE_n/A14 are considered as row address A16, A15, and
A14. See Command Truth Table.
BAx
Input
Bank address inputs: Define the bank (with a bank group) to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command.
BGx
Input
Bank group address inputs: Define the bank group to which a REFRESH, ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. Also determine which mode register is to be
accessed during a MODE REGISTER SET command. BG[1:0] are used in the x4 and x8 configurations. x16-based SDRAM only has BG0.
C0, C1, C2
Input
Chip ID: These inputs are used only when devices are stacked; that is, 2H, 4H, and 8H stacks for
x4 and x8 configurations using through-silicon vias (TSVs). These pins are not used in the x16
configuration. Some DDR4 modules support a traditional DDP package, which uses CS1_n,
CKE1, and ODT1 to control the second die. All other stack configurations, such as a 4H or 8H,
are assumed to be single-load (master/slave) type configurations where C0, C1, and C2 are used
as chip ID selects in conjunction with a single CS_n, CKE, and ODT. Chip ID is considered part of
the command code.
CKx_t
CKx_c
Input
Clock: Differential clock inputs. All address, command, and control input signals are sampled
on the crossing of the positive edge of CK_t and the negative edge of CK_c.
CKEx
Input
Clock enable: CKE HIGH activates and CKE LOW deactivates the internal clock signals, device
input buffers, and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and
SELF REFRESH operations (all banks idle), or active power-down (row active in any bank). CKE is
asynchronous for self refresh exit. After VREFCA has become stable during the power-on and initialization sequence, it must be maintained during all operations (including SELF REFRESH). CKE
must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK_t,
CK_c, ODT, RESET_n, and CKE) are disabled during power-down. Input buffers (excluding CKE
and RESET#) are disabled during self refresh.
CSx_n
Input
Chip select: All commands are masked when CS_n is registered HIGH. CS_n provides external
rank selection on systems with multiple ranks. CS_n is considered part of the command code
(CS2_n and CS3_n are not used on UDIMMs).
(RDIMM/LRDIMM only)
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
Description
ODTx
Input
On-die termination: ODT (registered HIGH) enables termination resistance internal to the
DDR4 SDRAM. When enabled, ODT (RTT) is applied only to each DQ, DQS_t, DQS_c, DM_n/
DBI_n/TDQS_t, and TDQS_c signal for x4 and x8 configurations (when the TDQS function is enabled via the mode register). For the x16 configuration, RTT is applied to each DQ, DQSU_t,
DQSU_c, DQSL_t, DQSL_c, UDM_n, and LDM_n signal. The ODT pin will be ignored if the mode
registers are programmed to disable RTT.
PARITY
Input
Parity for command and address: This function can be enabled or disabled via the mode
register. When enabled in MR5, the DRAM calculates parity with ACT_n, RAS_n/A16, CAS_n/A15,
WE_n/A14, BG[1:0], BA[1:0], A[16:0]. Input parity should be maintained at the rising edge of the
clock and at the same time as command and address with CS_n LOW.
RAS_n/A16
CAS_n/A15
WE_n/A14
Input
Command inputs: RAS_n/A16, CAS_n/A15, and WE_n/A14 (along with CS_n) define the command and/or address being entered and have multiple functions. For example, for activation
with ACT_n LOW, these are addresses like A16, A15, and A14, but for a non-activation command with ACT_n HIGH, these are command pins for READ, WRITE, and other commands defined in Command Truth Table.
RESET_n
CMOS Input
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range
on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to
and from the temperature sensor/SPD EEPROM on the I2C bus.
DQx, CBx
I/O
Data input/output and check bit input/output: Bidirectional data bus. DQ represents
DQ[3:0], DQ[7:0], and DQ[15:0] for the x4, x8, and x16 configurations, respectively. If cyclic redundancy checksum (CRC) is enabled via the mode register, the CRC code is added at the end of
the data burst. Any one or all of DQ0, DQ1, DQ2, or DQ3 may be used for monitoring of internal VREF level during test via mode register setting MR[4] A[4] = HIGH; training times change
when enabled.
DM_n/DBI_n/
TDQS_t (DMU_n,
DBIU_n), (DML_n/
DBIl_n)
I/O
Input data mask and data bus inversion: DM_n is an input mask signal for write data. Input
data is masked when DM_n is sampled LOW coincident with that input data during a write access. DM_n is sampled on both edges of DQS. DM is multiplexed with the DBI function by the
mode register A10, A11, and A12 settings in MR5. For a x8 device, the function of DM or TDQS
is enabled by the mode register A11 setting in MR1. DBI_n is an input/output identifying
whether to store/output the true or inverted data. If DBI_n is LOW, the data will be stored/
output after inversion inside the DDR4 device and not inverted if DBI_n is HIGH. TDQS is only
supported in x8 SDRAM configurations (TDQS is not valid for UDIMMs).
SDA
I/O
Serial Data: Bidirectional signal used to transfer data in or out of the EEPROM or EEPROM/TS
combo device.
DQS_t
DQS_c
DQSU_t
DQSU_c
DQSL_t
DQSL_c
I/O
Data strobe: Output with read data, input with write data. Edge-aligned with read data, centered-aligned with write data. For x16 configurations, DQSL corresponds to the data on
DQ[7:0], and DQSU corresponds to the data on DQ[15:8]. For the x4 and x8 configurations, DQS
corresponds to the data on DQ[3:0] and DQ[7:0], respectively. DDR4 SDRAM supports a differential data strobe only and does not support a single-ended data strobe.
ALERT_n
Output
Alert output: Possesses functions such as CRC error flag and command and address parity error
flag as output signal. If a CRC error occurs, ALERT_n goes LOW for the period time interval and
returns HIGH. If an error occurs during a command address parity check, ALERT_n goes LOW until the on-going DRAM internal recovery transaction is complete. During connectivity test mode,
this pin functions as an input. Use of this signal is system-dependent. If not connected as signal,
ALERT_n pin must be connected to VDD on DIMMs.
EVENT_n
Output
Temperature event: The EVENT_n pin is asserted by the temperature sensor when critical temperature thresholds have been exceeded. This pin has no function (NF) on modules without
temperature sensors.
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Active LOW asynchronous reset: Reset is active when RESET_n is LOW and inactive when RESET_n is HIGH. RESET_n must be HIGH during normal operation.
5
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© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Pin Descriptions
Table 5: Pin Descriptions (Continued)
Symbol
Type
Description
TDQS_t
TDQS_c
Output
Termination data strobe: When enabled via the mode register, the DRAM device enables the
same RTT termination resistance on TDQS_t and TDQS_c that is applied to DQS_t and DQS_c.
When the TDQS function is disabled via the mode register, the DM/TDQS_t pin provides the data mask (DM) function, and the TDQS_c pin is not used. The TDQS function must be disabled in
the mode register for both the x4 and x16 configurations. The DM function is supported only in
x8 and x16 configurations. DM, DBI, and TDQS are a shared pin and are enabled/disabled by
mode register settings. For more information about TDQS, see the DDR4 DRAM component data sheet (TDQS_t and TDQS_c are not valid for UDIMMs).
VDD
Supply
Module power supply: 1.2V (TYP).
VPP
Supply
DRAM activating power supply: 2.5V –0.125V / +0.250V.
VREFCA
Supply
Reference voltage for control, command, and address pins.
VSS
Supply
Ground.
(x8 DRAM-based
RDIMM only)
VTT
Supply
Power supply for termination of address, command, and control VDD/2.
VDDSPD
Supply
Power supply used to power the I2C bus for SPD.
RFU
–
Reserved for future use.
NC
–
No connect: No internal electrical connection is present.
NF
–
No function: May have internal connection present, but has no function.
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
DQ Map
DQ Map
Table 6: Component-to-Module DQ Map, Front
Component
Reference
Number
Component
DQ
Module DQ
U1
0
1
2
U3
U5
U8
U10
U12
U14
U17
U19
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asf36c2gx72lz.pdf - Rev. D 9/15 EN
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
5
U2
0
10
23
2
12
1
8
16
1
150
2
11
168
3
3
157
3
9
161
0
22
32
0
31
188
1
21
170
1
29
181
2
23
177
2
30
43
3
20
25
3
28
36
0
CB6
54
0
34
104
1
CB5
192
1
32
97
2
CB7
199
2
35
249
3
CB4
47
3
33
242
0
40
108
0
50
126
1
42
115
1
48
119
2
41
253
2
51
271
3
43
260
3
49
264
0
60
128
0
7
155
1
62
135
1
5
148
2
61
273
2
6
10
3
63
280
3
4
3
0
14
21
0
17
172
1
12
14
1
19
179
2
15
166
2
16
27
3
13
159
3
18
34
0
25
183
0
CB0
49
1
27
190
1
CB3
201
2
24
38
2
CB1
194
3
26
45
3
CB2
56
0
38
102
0
46
113
1
36
95
1
44
106
2
39
247
2
47
258
3
37
240
3
45
251
0
52
117
0
58
137
1
54
124
1
57
275
2
53
262
2
59
282
3
55
269
3
56
130
U4
U7
U9
U11
U13
U15
U18
U20
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© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
DQ Map
Table 7: Component-to-Module DQ Map, Back
Component
Reference
Number
Component
DQ
U21
U23
U25
U27
U29
U31
U33
U35
U37
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
62
135
U22
0
48
119
1
60
128
1
50
126
2
63
280
2
49
264
3
61
273
3
51
271
0
42
115
0
32
97
1
40
108
1
34
104
2
43
260
2
33
242
3
41
253
3
35
249
0
CB5
192
0
29
181
1
CB5
54
1
31
188
2
CB4
47
2
28
36
3
CB7
199
3
30
43
0
21
170
0
8
16
1
22
32
1
10
23
2
20
25
2
9
161
3
23
177
3
11
168
0
2
12
0
57
275
1
0
5
1
58
137
2
3
157
2
56
130
3
1
150
3
59
282
0
54
124
0
44
106
1
52
117
1
46
113
2
55
269
2
45
251
3
53
262
3
47
258
0
36
95
0
CB3
201
1
38
102
1
CB0
49
2
37
240
2
CB2
56
3
39
247
3
CB1
194
0
27
190
0
19
179
1
25
183
1
17
172
2
26
45
2
18
34
3
24
38
3
16
27
0
12
14
0
5
148
1
14
21
1
7
155
2
13
159
2
4
3
3
15
166
3
6
10
U24
U26
U28
U30
U32
U34
U36
U38
8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
CS0A, CS0B
CS1A, CS1B
Data Buffers
Data Buffers
CS0A
DQ0
DQ1
DQ2
DQ3
U47
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
DQS9_t
DQS9_c
VDD
DQ4
DQ5
DQ6
DQ7
VSS
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U38
ZQ
VSS
VSS
VSS
DQ8
DQ9
DQ10
DQ11
U46
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
ZQ
VDD
DQ12
DQ13
DQ14
DQ15
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U37
ZQ
VSS
VSS
VSS
DQ16
DQ17
DQ18
DQ19
U45
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U13
ZQ
DQS11_t
DQS11_c
ALERT_N ZQCAL
VDD
DQ20
DQ21
DQ22
DQ23
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U3
U27
ZQ
VSS
ZQ
VSS
DQ24
DQ25
DQ26
DQ27
U44
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
ZQ
ALERT_N ZQCAL
VDD
DQ28
DQ29
DQ30
DQ31
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U4
U26
ZQ
VSS
VSS
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U18
U32
ZQ
ZQ
VSS
VSS
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U9
U22
ZQCAL
DQ52
DQ53
DQ54
DQ55
VSS
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U19
ZQ
CB0
CB1
CB2
CB3
U43
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U15
ZQCAL
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U20
ZQ
CB4
CB5
CB6
CB7
VSS
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
ZQ
U25
CS_n DQS_t DQS_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
EVT A0
SDA
A1 A2
SA0 SA1 SA2
EVENT_N
U21
ZQ
SPD EEPROM/Temp Sensor,
Register
VDD
DDR4 SDRAM, Register,
Data Buffers
VTT
Control, command and
address termination
VSS
Command, control, address, and clock line terminations:
CS_n[3:0]A/B, BA[1:0]A/B, BG[1:0]A/B,
ACT_nA/B, A[17, 13:0]A/B, RAS_n/A16A/B,
CAS_n/A15A/B, WE_n/A14A/B,
PAR-A/B, CKE[1:0]A/B, ODT[1:0]A/B
CK0[A:D]_t
CK0[A:D]_c
DDR4
SDRAM
VTT
DDR4
SDRAM
VDD
DDR4 SDRAMs, Register
BVREF
ZQ
U6
SPD EEPROM/
Temperature
sensor
SCL
VSS
VREFCA
VSS
Note:
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
VSS
CS_n DQS_t DQS_c
CK1t
CK1c
VSS
ZQ
ZQ
VSS
DQS17_t
DQS17_c
ZQCAL
ZQ
U10
DDR4 SDRAM
(U1–U5, U7–U15, U17–U38)
DATA BUFFERS
(U39–U47)
CKDB_t
QRST_N: DDR4 SDRAM
U30
VSS
VDDSPD
CK0[A:D]_t
CK0[A:D]_c
RESET_CONN_N
VSS
DQ
DQ
DQ
DQ
VSS
VREFCA: DDR4 SDRAM
BVREF: DATA BUFFERS
CKDB_c
ZQ
Rank 0: U1–U5, U7–U15, U17–U20
Rank 1: U21–U38
U34
VREFCA_CONN
VSS
VSS
DQ60
DQ61
DQ62
DQ63
BODT: DATA BUFFERS
BCKE: DATA BUFFERS
C
O
N
T
R
O
L
DQS7_t
DQS7_c
DQ56
DQ57
DQ58
DQ59
BCOM0: DATA BUFFERS
BCOM1: DATA BUFFERS
BCOM2: DATA BUFFERS
BCOM3: DATA BUFFERS
U31
ZQ
VDD
SA0
SA1
SA2
SCL
SDA
ZQ
DQ
DQ
DQ
DQ
VSS
CS0A/B: Rank 0
CS1A/B: Rank 1
BA[1:0]A/B: DDR4 SDRAM
BG[1:0]A/B: DDR4 SDRAM
ACTA/B: DDR4 SDRAMS
A[17,13:0]A/B: DDR4 SDRAM
RAS_n/A16A/B: DDR4 SDRAM
CAS_n/A15A/B: DDR4 SDRAM
WE_n/A14A/B: DDR4 SDRAM
CKE0A/B: Rank 0, Rank 2
CKE1A/B: Rank 1, Rank 3
ODT0A/B: Rank 0, Rank 2 tied to VSS
ODT1A/B: Rank 1, Rank 3 tied to VSS
PARA/B: DDR4 SDRAM
C[2:0]: DDR4 SDRAM
ALERT_N: DDR4 SDRAM
R
E
G
I
S
T
E
R
–
P
L
L
–
B
U
F
F
E
R
CK0t
CK0c
VSS
DQS16_t
DQS16_c
ALERT_N
ZQ
VSS
VSS
DQS8_t
DQS8_c
DQS8_t
DQS8_c
DQS17_t
DQS17_c
ALERT_N ZQCAL
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQS15_t
DQS15_c
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
U23
VSS
DQ48
DQ49
DQ50
DQ51
DQS7_t
DQS7_c
DQS16_t
DQS16_c
ZQ
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U8
VSS
U39
VSS
DQS12_t
DQS12_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
CS0
CS1
BA[1:0]
BG[1:0]
ACT_n
A[17,13:0]
RAS_n/A16
CAS_n/A15
WE_n/A14
CKE0
CKE1
ODT0
ODT1
PAR_IN
C[2:0]
ALERT_CONN_N
DQS6_t
DQS6_c
VDD
U35
VSS
ZQ
ALERT_N
DQS3_t
DQS3_c
DQS3_t
DQS3_c
DQS12_t
DQS12_c
ZQCAL
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
VSS
ZQ
VSS
DQ44
DQ45
DQ46
DQ47
U40
ZQ
U33
ZQ
DQS6_t
DQS6_c
DQS15_t
DQS15_c
U36
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U17
ZQ
DQ40
DQ41
DQ42
DQ43
VDD
DQS2_t
DQS2_c
DQS2_t
DQS2_c
DQS11_t
DQS11_c
CS_n DQS_t DQS_c
DQS14_t
DQS14_c
ALERT_N
ZQ
VSS
DQS5_t
DQS5_c
DQ40
DQ41
DQ41
DQ43
DQ44
DQ45
DQ46
DQ47
VSS
ZQ
DQ
DQ
DQ
DQ
VSS
DQS5_t
DQS5_c
DQS14_t
DQS14_c
ZQ
DQ
DQ
DQ
DQ
U12
ZQCAL
U16
U24
VSS
DQ36
DQ37
DQ38
DQ39
U41
VSS
DQS10_t
DQS10_c
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
U7
DQS13_t
DQS13_c
VDD
U28
CS_n DQS_t DQS_c
DQ
DQ
DQ
DQ
ZQ
ALERT_N
ZQ
DQS1_t
DQS1_c
DQS1_t
DQS1_c
DQS10_t
DQS10_c
ALERT_N ZQCAL
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
ZQ
DQ
DQ
DQ
DQ
U11
DQ32
DQ33
DQ34
DQ35
U42
VSS
CS1B
DQS4_t
DQS4_c
DQS4_t
DQS4_c
DQS13_t
DQS13_c
U29
ZQ
ALERT_N ZQCAL
CS0B
DQS0_t
DQS0_c
DQS0_t
DQS0_c
DQS9_t
DQS9_c
VDD
CS1A
Data Buffers
VPP
DDR4 SDRAM
VSS
DDR4 SDRAM, Register,
Data Buffer
1. The ZQ ball on each DDR4 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
General Description
General Description
High-speed DDR4 SDRAM modules use DDR4 SDRAM devices with two or four internal
memory bank groups. DDR4 SDRAM modules utilizing 4- and 8-bit-wide DDR4 SDRAM
devices have four internal bank groups consisting of four memory banks each, providing a total of 16 banks. 16-bit-wide DDR4 SDRAM devices have two internal bank
groups consisting of four memory banks each, providing a total of eight banks. DDR4
SDRAM modules benefit from DDR4 SDRAM's use of an 8n-prefetch architecture with
an interface designed to transfer two data words per clock cycle at the I/O pins. A single
READ or WRITE operation for the DDR4 SDRAM effectively consists of a single 8n-bitwide, four-clock data transfer at the internal DRAM core and eight corresponding n-bitwide, one-half-clock-cycle data transfers at the I/O pins.
DDR4 modules use two sets of differential signals: DQS_t and DQS_c to capture data
and CK_t and CK_c to capture commands, addresses, and control signals. Differential
clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals.
Fly-By Topology
DDR4 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR4.
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
10
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Address Mapping to DRAM
Address Mapping to DRAM
Address Mirroring
To achieve optimum routing of the address bus on DDR4 multi rank modules, the address bus will be wired as shown in the table below, or mirrored. For quad rank modules, ranks 1 and 3 are mirrored and ranks 0 and 2 are non-mirrored. Highlighted address pins have no secondary functions allowing for normal operation when crosswired. Data is still read from the same address it was written. However, Load Mode operations require a specific address. This requires the controller to accommodate for a
rank that is "mirrored." Systems may reference DDR4 SPD to determine if the module
has mirroring implemented or not. See the JEDEC DDR4 SPD specification for more details.
Table 8: Address Mirroring
Edge Connector Pin
DRAM Pin, Non-mirrored
DRAM Pin, Mirrored
A0
A0
A0
A1
A1
A1
A2
A2
A2
A3
A3
A4
A4
A4
A3
A5
A5
A6
A6
A6
A5
A7
A7
A8
A8
A8
A7
A9
A9
A9
A10
A10
A10
A11
A11
A13
A13
A13
A11
A12
A12
A12
A14
A14
A14
A15
A15
A15
A16
A16
A16
A17
A17
A17
BA0
BA0
BA1
BA1
BA1
BA0
BG0
BG0
BG1
BG1
BG1
BG0
Registering Clock Driver Operation
Registered DDR4 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC DDR4 RCD01
Specification.
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asf36c2gx72lz.pdf - Rev. D 9/15 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Data Buffer Operation and Description
To reduce the electrical load on the host memory controller's command, address, and
control bus, Micron's RDIMMs utilize a DDR4 registering clock driver (RCD). The RCD
presents a single load to the controller while redriving signals to the DDR4 SDRAM devices, which helps enable higher densities and increase signal integrity. The RCD also
provides a low-jitter, low-skew PLL that redistributes a differential clock pair to multiple
differential pairs of clock outputs.
Control Words
The RCD device(s) used on DDR4 RDIMMs and LRDIMMs contain configuration registers known as control words, which the host uses to configure the RCD based on criteria
determined by the module design. Control words can be set by the host controller
through either the DRAM address and control bus or the I2C bus interface. The RCD I 2C
bus interface resides on the same I2C bus interface as the module temperature sensor
and EEPROM.
Parity Operations
The RCD includes a parity-checking function that can be enabled or disabled in control
word RC0E. The RCD receives a parity bit at the DPAR input from the memory controller and compares it with the data received on the qualified command and address inputs; it indicates on its open-drain ALERT_n pin whether a parity error has occurred. If
parity checking is enabled, the RCD forwards commands to the SDRAM when no parity
error has occurred. If the parity error function is disabled, the RCD forwards sampled
commands to the SDRAM regardless of whether a parity error has occurred. Parity is also checked during control word WRITE operations unless parity checking is disabled.
Rank Addressing
The chip select pins (CS_n) on Micron's modules are used to select a specific rank of
DRAM. The RDIMM is capable of selecting ranks in one of three different operating
modes, dependant on setting DA[1:0] bits in the DIMM configuration control word located within the RCD. Direct DualCS mode is utilized for single- or dual-rank modules.
For quad-rank modules, either direct or encoded QuadCS mode is used.
Data Buffer Operation and Description
Data buffers operate as 4-bit bidirectional data registers with differential strobes, designed for 1.2 V DD operation. Each buffer has a dual 4-bit host bus interface connected
to the memory controller and a dual 4-bit DRAM interface connected to two x4 DRAM
devices. Each buffer has an input-only 4-bit control bus interface consisting of two
dedicated control signals, a voltage reference input, and a differential clock signal.
All DQ inputs are pseudo-differentiated with an internal voltage reference. All DQ outputs are V DD-terminated drivers that are optimized to drive single- or dual-terminated
traces in DDR4 LRDIMM applications. The differential DQS strobes are used to sample
the DQ inputs and are regenerated internally to drive the DQ outputs on the opposite
side of the device.
Control inputs are sampled by the clock inputs, and each data buffer supports ZQ calibration for parity (with dedicated pins) and sequence error alerts.
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
12
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Temperature Sensor With SPD EEPROM Operation
Temperature Sensor With SPD EEPROM Operation
Thermal Sensor Operations
The integrated thermal sensor continuously monitors the temperature of the module
PCB directly below the device and updates the temperature data register. Temperature
data may be read from the bus host at any time, which provides the host real-time feedback of the module's temperature. Multiple programmable and read-only temperature
registers can be used to create a custom temperature-sensing solution based on system
requirements and JEDEC JC-42.2.
EVENT_n Pin
The temperature sensor also adds the EVENT_n pin (open-drain), which requires a pullup to V DDSPD. EVENT_n is a temperature sensor output used to flag critical events that
can be set up in the sensor’s configuration registers. EVENT_n is not used by the serial
presence-detect (SPD) EEPROM.
EVENT_n has three defined modes of operation: interrupt, comparator, and TCRIT. In
interrupt mode, the EVENT_n pin remains asserted until it is released by writing a 1 to
the clear event bit in the status register. In comparator mode, the EVENT_n pin clears
itself when the error condition is removed. Comparator mode is always used when the
temperature is compared against the TCRIT limit. In TCRIT only mode, the EVENT_n
pin is only asserted if the measured temperature exceeds the TCRIT limit; it then remains asserted until the temperature drops below the TCRIT limit minus the TCRIT
hysteresis.
SPD EEPROM Operation
DDR4 SDRAM modules incorporate SPD. The SPD data is stored in a 512-byte, JEDEC
JC-42.4-compliant EEPROM that is segregated into four 128-byte, write-protectable
blocks. The SPD content is aligned with these blocks as shown in the table below.
Block
Range
Description
0
0–127
1
128–255
080h–0FFh
Module parameters
2
256–319
100h–13Fh
Reserved (all bytes coded as 00h)
320–383
140h–17Fh
Manufacturing information
384–511
180h–1FFh
End-user programmable
3
000h–07Fh
Configuration and DRAM parameters
The first 384 bytes are programmed by Micron to comply with JEDEC standard JC-45,
"Appendix X: Serial Presence Detect (SPD) for DDR4 SDRAM Modules." The remaining
128 bytes of storage are available for use by the customer.
The EEPROM resides on a two-wire I2C serial interface and is not integrated with the
memory bus in any manner. It operates as a slave device in the I2C bus protocol, with all
operations synchronized by the serial clock. Transfer rates of up to 1 MHz are achievable at 2.5V (NOM).
Micron implements reversible software write protection on DDR4 SDRAM-based modules. This prevents the lower 384 bytes (bytes 0 to 383) from being inadvertently programmed or corrupted. The upper 128 bytes remain available for customer use and are
unprotected.
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
13
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
Notes
VDD
VDD supply voltage relative to VSS
–0.4
1.5
V
1
VDDQ
VDDQ supply voltage relative to VSS
–0.4
1.5
V
1
Voltage on VPP pin relative to VSS
–0.4
3.0
V
2
VIN, VOUT Voltage on any pin relative to VSS
–0.4
1.5
V
VPP
Table 10: Operating Conditions
Symbol
Parameter
Min
Nom
Max
Units
Notes
VDD
VDD supply voltage
1.14
1.20
1.26
V
1
VPP
DRAM activating power supply
2.375
2.5
2.75
V
2
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
3
–750
–
750
mA
0.49 × VDD 20mV
0.5 × VDD
0.51 × VDD +
20mV
V
4
–
µA
5
VREFCA(DC) Input reference voltage –
command/address bus
IVTT
Termination reference current from VTT
VTT
Termination reference voltage (DC) –
command/address bus
II
Input leakage current; any input excluding ZQ; 0V <
VIN < 1.1V
–
–
II
Input leakage current; ZQ
–3
–
3
µA
6, 7
DQ leakage; 0V < VIN < VDD
–4
–
4
µA
7
IOZpd
Output leakage current; VOUT = VDD; DQ is disabled
–
–
5
µA
IOZpu
Output leakage current; VOUT = VSS; DQ and ODT
are disabled; ODT is disabled with ODT input HIGH
–
–
50
µA
VREFCA leakage; VREFCA = VDD/2 (after DRAM is initialized)
–2
–
2
µA
II/O
IVREFCA
Notes:
PDF: 09005aef8581805b
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7
1. VDDQ balls on DRAM are tied to VDD.
2. VPP must be greater than or equal to VDD at all times.
3. VREFCA must not be greater than 0.6 × VDD. When VDD is less than 500mV, VREF may be
less than or equal to 300mV.
4. VTT termination voltages in excess of specification limit adversely affect command and
address signals' voltage margins and reduce timing margins.
5. Command and address inputs are terminated to VDD/2 in the registering clock driver. Input current is dependent on termination resistance set in the registering clock driver.
6. Tied to ground. Not connected to edge connector.
7. Multiply by number of DRAM die on module.
14
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Electrical Specifications
Table 11: Thermal Characteristics
Symbol
Parameter/Condition
Value
Units
Notes
TC
Commercial operating case temperature
0 to 85
°C
1, 2, 3
>85 to 95
°C
1, 2, 3, 4
0 to 85
°C
5, 7
TC
TOPER
Normal operating temperature range
TOPER
Extended temperature operating range (optional)
>85 to 95
°C
5, 7
TSTG
Non-operating storage temperature
-55 to 100
°C
6
5 to 95
%
20
°C/hour
RHSTG
NA
Non-operating Storage Relative Humidity (non-condensing)
Change Rate of Storage Temperature
Notes:
PDF: 09005aef8581805b
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1. Maximum operating case temperature; TC is measured in the center of the package.
2. A thermal solution must be designed to ensure the DRAM device does not exceed the
maximum TC during operation.
3. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.
4. If TC exceeds 85°C, the DRAM must be refreshed externally at 2X refresh, which is a 3.9µs
interval refresh rate.
5. The refresh rate must double when 85°C < TOPER ≤ 95°C.
6. Storage temperature is defined as the temperature of the top/center of the DRAM and
does not reflect the storage temperatures of shipping trays.
7. For additional information, refer to technical note TN-00-08: "Thermal Applications"
available at micron.com.
15
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© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR4 component data sheets.
Component specifications are available at micron.com. Module speed grades correlate
with component speed grades, as shown below.
Table 12: Module and Component Speed Grades
DDR4 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G6
-075
-2G4
-083E
-2G3
-083
-2G1
-093E
-1G9
-107E
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the edge connector of the module, not at the DRAM.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
IDD Specifications
IDD Specifications
Table 13: DDR4 IDD Specifications and Conditions – 16GB (Die Revision A)
Values are for the MT40A1G4 DDR4 SDRAM only and are computed from values specified in the 4Gb (1 Gig x 4) component data sheet
Parameter
Symbol
2400 2133 Units
IDD01
One bank ACTIVATE-PRECHARGE current
One bank ACTIVATE-PRECHARGE, word line boost, IPP current
One bank ACTIVATE-READ-PRECHARGE current
1728
1620
mA
1
126
126
mA
1
1800
1710
mA
IPP0
IDD1
Precharge standby current
IDD2N
2
1800
1656
mA
Precharge standby ODT current
IDD2NT1
1620
1512
mA
Precharge power-down current
IDD2P2
1152
1080
mA
Precharge quite standby current
IDD2Q2
1476
1404
mA
2
Active standby current
IDD3N
2412
2268
mA
Active standby IPP current
IPP3N2
108
108
mA
Active power-down current
IDD3P2
1584
1584
mA
1
Burst read current
IDD4R
3436
3240
mA
Burst read IDDQ current
IDDQ4R
1
1296
1188
mA
Burst write current
IDD4W1
3816
3420
mA
1
4032
3960
mA
1
450
450
mA
Burst refresh current (1 x REF)
IDD5B
Burst refresh IPP current (1 x REF)
IPP5B
Self refresh current: Normal temperature range (0–85°C)
IDD6N
2
720
720
mA
Self refresh current: Extended temperature range (0–95°C)
IDD6E2
972
972
mA
Self refresh current: Reduced temperature range (0–45°C)
IDD6R2
360
360
mA
2
324
324
mA
Auto self refresh current (25°C)
IDD6A
Auto self refresh current (45°C)
IDD6A
2
360
360
mA
Auto self refresh current (75°C)
IDD6A2
576
576
mA
Bank interleave read current
IDD71
Bank interleave read IPP current
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
3870
mA
306
270
mA
2
648
648
mA
IPP7
Maximum power-down current
Notes:
4356
1
IDD8
1. One module rank in the active IDD/PP, the other rank in IDD2P/PP3N.
2. All ranks in this IDD/PP condition.
17
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© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Registering Clock Driver Specifications
Registering Clock Driver Specifications
Table 14: Registering Clock Driver Electrical Characteristics
DDR4 RCD01 devices or equivalent
Parameter
Symbol
Pins
Min
Nom
Max
Units
DC supply voltage
VDD
–
1.14
1.2
1.26
V
DC reference voltage
VREF
VREFCA
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
DC termination
voltage
VTT
–
VREF - 40mV
VREF
VREF + 40mV
V
High-level input
voltage
VIH. CMOS
DRST_n
0.65 × VDD
–
VDD
V
Low-level input
voltage
VIL. CMOS
0
–
0.35 × VDD
V
DRST_n pulse width
tINIT_Power_stable
–
1.0
–
–
µs
AC high-level output
voltage
VOH(AC)
All outputs except
ALERT_n
VTT + (0.15 × VDD)
–
–
V
AC low-level output
voltage
VOL(AC)
–
–
VTT + (0.15 x VDD)
V
AC differential output high measurement level (for output slew rate)
VOHdiff(AC)
–
0.3 × VDD
–
mV
AC differential output low measurement level (for output slew rate)
VOLdiff(AC)
–
–0.3 × VDD
–
mV
Note:
PDF: 09005aef8581805b
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Yn_t - Yn_c, BCK_t BCK_c
1. Timing and switching specifications for the register listed are critical for proper operation of DDR4 SDRAM RDIMMs. These are meant to be a subset of the parameters for the
specific device used on the module. See the JEDEC RCD01 specification for complete operating electrical characteristics. Registering clock driver parametric values are specified
for device default control word settings, unless otherwise stated. The RC0A control
word setting does not affect parametric values.
18
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Data Buffer Specifications
Data Buffer Specifications
Table 15: Data Buffer Electrical Characteristics
DDR4 DB01 devices or equivalent
Parameter
Symbol
DC supply voltage
Pins
Min
Nom
Max
Unit
V
VDD
–
1.14
1.2
1.26
DC reference voltage
BVREFCA
BVREF
0.49 × VDD
0.5 × VDD
0.51 × VDD
Low-level
input voltage
VIL(static)
BCK_t,
BCK_c
(during
clock stop)
0
–
0.35 × VDD
Differential input
cross point voltage
range
VIX(BCK)
–120
–
120
Extended
differential input
cross point voltage
range
VIX_EX(BCK)
–150
–
150
Average common
mode DC voltage
VCM(DC)
0.46 × VDD
0.5 × VDD
0.54 × VDD
V
DDR4-1866, 2133
(VDD/2) + 90
DDR4-2400 (VDD/2)
+ 75
–
–
mV
–
–
DDR4-1866, 2133
(VDD/2) - 90
DDR4-2400 (VDD/2) 75
DDR4-1866, 2133
BVREFCA + 90
DDR4-2400 BVREFCA
+ 75
–
–
–
–
DDR4-1866, 2133
BVREFCA - 90
DDR4-2400 BVREFCA 75
DDR4-1866, 2133;
130
DDR4-2400; 100
–
–
–
–
DDR4-1866, 2133;
–130
DDR4-2400; –100
Single-ended
high level
VSEH
Single-ended
low level
VSEL
AC input high
VIH(AC)
BCK_t,
BCK_c
BCK_t,
BCK_c
BCK_t,
BCK_c
BCK_t,
BCK_c
BCK_t,
BCK_c
AC input low
VIL(AC)
BCK_t,
BCK_c
Differential input
high
VIH,diff
Differential input low
VIL,diff
AC differential input
high
VIH,diff(AC)
BCK_t,
BCK_c
2 x (VIH(AC).MIN BVREFCA )
–
–
AC differential input
low
VIL,diff(AC)
BCK_t,
BCK_c
–
–
2 x (VIL(AC).MAX BVREFCA)
PDF: 09005aef8581805b
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BCK_t,
BCK_c
BCK_t,
BCK_c
19
mV
mV
mV
mV
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Data Buffer Specifications
Table 15: Data Buffer Electrical Characteristics (Continued)
DDR4 DB01 devices or equivalent
Parameter
Symbol
Pins
Min
Nom
Max
Unit
V
AC output high
VOH(AC)
–
(0.7 + 0.15) x VDD
–
AC output low
VOL(AC)
–
(0.7 - 0.15) x VDD
–
DC output high
VOH(DC)
DC output mid
VOM(DC)
DC output low
VOL(DC)
AC differential
output high
VOH,diff(AC)
AC differential
output low
VOL,diff(AC)
Junction
temperature
All outputs
except
ALERT_n
–
1.1 x VDD
–
–
0.8 x VDD
–
–
0.5 x VDD
–
–
0.3 x VDD
–
–
–0.3 x VDD
–
Tj
–
0
–
125
TCASE
–
–
–
TBD
Input clamp current
IIK
–
–
–
–50
output clamp
current
IOK
–
–
–
±50
Continuous output
current
IO
–
–
–
±50
Continuous output
current each VDD or
VSS pin
ICCC
–
–
–
±100
Case temperature
Note:
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
V
V
C°
mA
1. Data buffer parametric values are specified for the device default control word settings,
unless otherwise stated.
20
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Temperature Sensor With SPD EEPROM
Temperature Sensor With SPD EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the serial presence-detect (SPD) EEPROM. Refer to JEDEC JC-42.4 EE1004 and TSE2004 device specifications for complete
details.
SPD Data
For the latest SPD data, refer to Micron's SPD page: micron.com/SPD.
Table 16: Temperature Sensor With SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Nom
Max
Units
VDDSPD
–
2.5
–
V
Input low voltage: logic 0; all inputs
VIL
–0.5
–
VDDSPD × 0.3
V
Input high voltage: logic 1; all inputs
VIH
VDDSPD × 0.7
–
VDDSPD + 0.5
V
Output low voltage: 3mA sink current VDDSPD > 2V
Supply voltage
VOL
–
–
0.4
V
Input leakage current: (SCL, SDA) VIN = VDDSPD or VSSSPD
ILI
–
–
±5
µA
Output leakage current: VOUT = VDDSPD or VSSSPD, SDA in High-Z
ILO
–
–
±5
µA
Table 17: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition
Min
Max
Units
fSCL
10
1000
kHz
Clock pulse width HIGH time
tHIGH
260
–
ns
Clock pulse width LOW time
tLOW
500
–
ns
tTIMEOUT
Clock frequency
Detect clock LOW timeout
Symbol
25
35
ms
SDA rise time
tR
–
120
ns
SDA fall time
tF
–
120
ns
Data-in setup time
tSU:DAT
50
–
ns
Data-in hold time
tHD:DI
ns
0
–
Data out hold time
tHD:DAT
0
350
ns
Start condition setup time
tSU:STA
260
–
ns
Start condition hold time
tHD:STA
260
–
ns
Stop condition setup time
tSU:STO
260
–
ns
tBUF
500
–
ns
Time the bus must be free before a new transition can start
Write time
Warm power cycle time off
Time from power on to first command
PDF: 09005aef8581805b
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tW
–
5
ms
tPOFF
1
–
ms
tINIT
10
–
ms
21
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16GB (x72, ECC, DR) 288-Pin DDR4 LRDIMM
Module Dimensions
Module Dimensions
Figure 3: 288-Pin DDR4 LRDIMM
Front view
3.9 (0.153)
MAX
133.48 (5.255)
133.22 (5.244)
45.85 (1.8) TYP (2X)
7.18 (0.283) TYP (2X)
U1
0.50 (0.02) R
(4X)
0.75 (0.03) R
(8X)
U3
U2
U11
27.3 (1.1) TYP
U4
U13
U12
U14
U6
U5
U7
U8
U16
U15
U18
U17
U10
U9
24.6 (0.97)
TYP
U20
U19
2.50 (0.098) D
(2X)
31.40 (1.236)
31.10 (1.224)
16.1 (0.63)
9.5 (0.374) TYP
TYP
4.8 (0.189) TYP
1.5 (0.059)
1.3 (0.051)
0.75 (0.030) R
Pin 1
2.20 (0.087) TYP
0.85 (0.033)
TYP
3.35 (0.132) TYP
(2X)
0.60 (0.0236)
TYP
Pin 144
72.25 (2.84)
TYP
126.65 (4.99)
TYP
1.0 (0.039) R (4X)
Back view
U21
23.05 (0.91)
TYP
U30
14.6 (0.57)
TYP 8.0 (0.315)
U39
U23
U22
U32
U31
U40
U41
U24
U33
U25
U34
U26
U35
U42
U43
U27
U36
U29
U28
U38
U37
U44
1.25 (0.049) x 45° (2X)
U45
U46
3.1 (0.122) (2X) TYP
3.0 (0.118) (4X) TYP
U47
TYP
0.5 (0.0197) TYP
3.15 (0.124)
TYP
Pin 288
22.95 (0.90)
TYP
10.2 (0.4)
TYP
5.95 (0.234) TYP
22.95 (0.9)
TYP
25.5 (1.0)
TYP
28.9 (1.14)
TYP
64.6 (2.54)
TYP
56.10 (2.21)
TYP
Notes:
10.2 (0.4)
TYP
Pin 145
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef8581805b
asf36c2gx72lz.pdf - Rev. D 9/15 EN
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