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Features
e.MMC Memory
MTFC8GAM, MTFC16GAP, MTFC32GAP, MTFC64GAP, MTFC128GAP
Features
Options
• Density
– 8GB
– 16GB
– 32GB
– 64GB
– 128GB
• NAND component
– 64GB
– 128GB
• Controller
• Packages – JEDEC-standard,
RoHS-compliant
– 153-ball TFBGA 11.5 x 13 x 1.1 (mm)
– 153-ball TFBGA 11.5 x 13 x 1.2 (mm)
• Operating temperature range
– From –40°C to +85°C
MultiMediaCard (MMC) controller and NAND Flash
• JEDEC/MMC standard version 5.1-compliant
(JEDEC Standard No. JESD84-B51)1
• VCC: 2.7–3.6V
• VCCQ (dual voltage): 1.70–1.95V; 2.7–3.6V
• Supported Bus Features:
– Advanced 12-signal interface
– ×1, ×4, and ×8 I/Os, selectable by host
– e.MMC I/F boot frequency: 0 to 52 MHz
– e.MMC I/F clock frequency: 0 to 200 MHz
– HS200/HS400 mode
• Supported Functions:
– Command classes: class 0 (basic); class 2 (block
read); class 4 (block write); class 5 (erase);
class 6 (write protection); class 7 (lock card)
– Command queue
– BKOPS control
– Temporary write protection
– Boot operation (high-speed boot)
– Sleep mode
– Replay-protected memory block (RPMB)
– Hardware reset signal
– Multiple partitions with enhanced attribute
– Permanent and power-on write protection
– High-priority interrupt (HPI)
– Data strobe pin
– Field firmware update (FFU)
– Device health report
– Sleep notification
– Background operation
– Reliable write
– Discard and sanitize
– Power-off notification
– Backward compatible with previous MMC
– ECC and block management implemented
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
Note:
1
Marking
8G
16G
32G
64G
128G
AM
AP
AL
BH
NS
IT
1. The JEDEC specification is available at
www.jedec.org/sites/default/files/docs/
JESD84-B51.pdf.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
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Features
Part Numbering Information
Micron® e.MMC memory devices are available in different configurations and densities.
Figure 1: e.MMC Part Numbering
MT FC
xx
xx
xx
xx - xx
xxx xx
Production Status
Micron Technology
Blank = Production
Product Family
ES = Engineering sample
FC = NAND Flash + controller
QS = Qualification sample
NAND Density
Operating Temperature Range
NAND Component
Special Options
Controller ID
Package Codes
All packages are Pb free
Table 1: Ordering Information
Base Part Number
Density
Package
Shipping
MTFC8GAMALBH-IT
8GB
153-ball TFBGA
11.5mm × 13mm × 1.1mm
Tape and reel
MTFC16GAPALBH-IT
MTFC32GAPALBH-IT
MTFC64GAPALBH-IT
MTFC128GAPALNS-IT
16GB
32GB
64GB
128GB
Tray
153-ball TFBGA
11.5mm × 13mm × 1.1mm
Tray
Tape and reel
153-ball TFBGA
11.5mm × 13mm × 1.1mm
Tape and reel
Tray
153-ball TFBGA
11.5mm × 13mm × 1.1mm
Tray
Tape and reel
153-ball TFBGA
11.5mm × 13mm × 1.2mm
Tape and reel
Tray
Device Marking
Due to the size of the package, the Micron-standard part number is not printed on the top of the device. Instead,
an abbreviated device mark consisting of a 5-digit alphanumeric code is used. The abbreviated device marks are
cross-referenced to the Micron part numbers at the FBGA Part Marking Decoder site: www.micron.com/decoder.
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
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Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
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General Performance
General Performance
e.MMC Performance
Performance in the following tables is retrieved with these conditions:
• Bus in x8 I/O
• Temperature 25°C
• Sequential access of 512KB chunk, cache on (write), command queueing enabled with queue depth 8 commands in HS400
Additional performance data, such as system performance on a specific application board, will be provided in a
separate document upon customer request.
Table 2: HS400 Performance
Typical Values
Condition
8GB
16GB
32/64/128GB
Unit
Sequential write
40
60
120
MB/s
Sequential read
280
320
320
MB/s
Table 3: HS200 Performance
Typical Values
Condition
8GB
16GB
32/64/128GB
Unit
Sequential write
40
60
100
MB/s
Sequential read
180
180
180
MB/s
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
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General Performance
e.MMC Current Consumption
Current consumption in the following tables are retrieved with these conditions:
•
•
•
•
Bus in x8 I/O. V CC = 3.6V and V CCQ = 1.95V
Temperature 25°C
Measurements done as average RMS current consumption
ICCQ in READ operation measurements with tester load disconnected
Table 4: HS400 Current Consumption
Typical Values (ICC/ICCQ)
Condition
8GB
16GB
32GB
Write1
60/90
60/90
110/90
Read1
100/140
120/140
120/140
Sleep
0/100
0/100
0/100
Auto-standby
60/110
80/110
80/110
Note:
64GB
128GB
Unit
110/90
110/90
mA
120/140
150/140
mA
0/100
0/100
µA
120/110
250/110
µA
1. Command queueing enabled with queue depth 8 commands.
Table 5: HS200 Current Consumption
Typical Values (ICC/ICCQ)
Condition
8GB
16GB
32GB
64GB
128GB
Unit
Write1
50/80
50/80
100/80
100/80
100/80
mA
Read1
70/110
80/110
80/110
80/110
90/110
mA
Sleep
0/100
0/100
0/100
0/100
0/100
µA
Auto-standby
60/110
80/110
80/110
120/110
250/110
µA
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. Command queueing enabled with queue depth 8 commands.
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General Description
General Description
Micron e.MMC is a communication and mass data storage device that includes a MultiMediaCard (MMC) interface, a NAND Flash component, and a controller on an advanced 12-signal bus, which is compliant with the MMC system specification. Its cost
per bit, small package sizes, and high reliability make it an ideal choice for industrial
applications like infrastructure and networking equipment, PC and servers, a variety of
other industrial products.
The nonvolatile e.MMC draws no power to maintain stored data, delivers high performance across a wide range of operating temperatures, and resists shock and vibration disruption.
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emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
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Signal Descriptions
Signal Descriptions
Table 6: Signal Descriptions
Symbol
Type
CLK
Input
Clock: each cycle of the clock directs a transfer on the command line and on the data line(s). The
frequency can vary between the minimum and the maximum clock frequency.
RST_n
Input
Reset: the RST_n signal is used by the host for resetting the device, moving the device to the preidle state. By default, the RST_n signal is temporarily disabled in the device. The host must set ECSD
register byte 162, bits[1:0] to 0x1 to enable this functionality before the host can use it.
CMD
I/O
Command: this signal is a bidirectional command channel used for command and response transfers. The CMD signal has two bus modes: open-drain mode and push-pull mode (see Operating
Modes). Commands are sent from the MMC host to the device, and responses are sent from the
device to the host.
DAT[7:0]
I/O
Data I/O: these are bidirectional data signals. The DAT signals operate in push-pull mode. By default, after power-on or assertion of the RST_n signal, only DAT0 is used for data transfer. The
MMC controller can configure a wider data bus for data transfer either using DAT[3:0] (4-bit mode)
or DAT[7:0] (8-bit mode). e·MMC includes internal pull-up resistors for data lines DAT[7:1]. Immediately after entering the 4-bit mode, the device disconnects the internal pull-up resistors on the
DAT[3:1] lines. Upon entering the 8-bit mode, the device disconnects the internal pull-ups on the
DAT[7:1] lines.
DS
Output
Data strobe: generated by the device and used for data output and CRC status response output in
HS400 mode. The frequency of this signal follows the frequency of CLK. For data output, each cycle
of this signal directs two bits transfer (2x) on the data, one bit for the positive edge and the other
bit for the negative edge. For CRC status response output, the CRC status is latched on the positive
edge only, and is "Don't Care" on the negative edge.
VSF[7:1]
Input/
output
Vendor specific function: VSF1, VSF2, VSF3, VSF4, VSF5, VSF6, and VSF7 are internally connected.
VCC
Supply
VCC: NAND interface (I/F) I/O and NAND Flash power supply.
VCCQ
Supply
VCCQ: e·MMC controller core and e·MMC I/F I/O power supply.
1
Supply
VSS: NAND I/F I/O and NAND Flash ground connection.
Supply
VSSQ: e·MMC controller core and e·MMC I/F ground connection.
VSS
1
VSSQ
VDDIM
Description
Internal voltage node: at least a 0.1μF capacitor is required to connect VDDIM to ground. A 1μF capacitor is recommended; do not tie to supply voltage or ground.
NC
–
No connect: no internal connection is present.
RFU
–
Reserved for future use: no internal connection is present; leave it floating externally.
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. VSS and VSSQ are connected internally.
7
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153-Ball Signal Assignments
153-Ball Signal Assignments
Figure 2: 153 Ball (Top View, Ball Down)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
NC
NC
DAT0
DAT1
DAT2
VSS
RFU
NC
NC
NC
NC
NC
NC
NC
A
B
NC
DAT3
DAT4
DAT5
DAT6
DAT7
NC
NC
NC
NC
NC
NC
NC
NC
B
C
NC
VDDIM
NC
VSSQ
NC
VCCQ
NC
NC
NC
NC
NC
NC
NC
NC
C
D
NC
NC
NC
NC
NC
NC
NC
D
E
NC
NC
NC
RFU
VSF3
NC
NC
NC
E
F
NC
NC
NC
VCC
VSF4
NC
NC
NC
F
G
NC
NC
NC
VSS
VSF5
NC
NC
NC
G
H
NC
NC
NC
DS
VSS
NC
NC
NC
H
J
NC
NC
NC
VSS
VCC
NC
NC
NC
J
K
NC
NC
NC
RST_n
VSF6
NC
NC
NC
K
L
NC
NC
NC
NC
NC
NC
L
M
NC
NC
NC
VCCQ
CMD
CLK
NC
NC
NC
NC
NC
NC
NC
NC
M
N
NC
VSSQ
NC
VCCQ
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
N
P
NC
NC
VCCQ
VSSQ
VCCQ
VSSQ
NC
NC
NC
VSF7
NC
NC
NC
NC
P
1
2
3
4
5
6
7
8
9
10
11
12
13
14
VCC
RFU
VSS
VSF1
RFU
VSS
VSF2
VCC
Top View
Notes:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. Some previous versions of the JEDEC product or mechanical specification had defined
reserved for future use (RFU) balls as no connect (NC) balls. NC balls assigned in the previous specifications could have been connected to ground on the system board. To enable new feature introduction, some of these balls are assigned as RFU in the v4.4 mechanical specification. Any new PCB footprint implementations should use the new ball
assignments and leave the RFU balls floating on the system board.
2. VCC, VCCQ, VSS, and VSSQ balls must all be connected on the system board.
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Package Dimensions
Package Dimensions
Figure 3: 153-Ball TFBGA – 11.5mm x 13.0mm x 1.1mm (Package Code BH)
Seating plane
A
153X Ø0.319
Dimensions
apply to solder
balls post-reflow
on Ø0.30 SMD
ball pads.
0.08 A
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
6.5 CTR
13 ±0.1
0.5 TYP
0.5 TYP
1 ±0.1
6.5 CTR
0.214 ±0.04
11.5 ±0.1
56X Ø0.27 test pads.
Au plated on pitch.
No solder balls.
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. Dimensions are in millimeters.
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Package Dimensions
Figure 4: 153-Ball TFBGA – 11.5mm x 13.0mm x 1.2mm (Package Code NS)
Seating plane
A
153X Ø0.319
Dimensions
apply to solder
balls post-reflow
on Ø0.30 SMD
ball pads.
0.08 A
Ball A1 ID
(covered by SR)
Ball A1 ID
14 12 10 8 6 4 2
13 11 9 7 5 3 1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
6.5 CTR
13 ±0.1
0.5 TYP
1.1 ±0.1
— 0.08
0.5 TYP
6.5 CTR
11.5 ±0.1
0.164 MIN
56X Ø0.27 on 0.5 pitch.
Ni/Au plated test pads.
No solder balls.
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. Dimensions are in millimeters.
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Architecture
Architecture
Figure 5: e.MMC Functional Block Diagram
e.MMC
MMC
controller
DS
RST_n
VDDIM
VCCQM
Registers
CMD
CLK
VCCM
DAT[7:0]
OCR
CSD
RCA
CID
ECSD
DSR
VSS1
VSSQ1
NAND Flash
1. VSS and VSSQ are internally connected.
Note:
MMC Protocol Independent of NAND Flash Technology
The MMC specification defines the communication protocol between a host and a device. The protocol is independent of the NAND flash features included in the device.
The device has an intelligent onboard controller that manages the MMC communication protocol.
The controller also handles block management functions, such as logical block allocation and wear leveling. These management functions require complex algorithms and
depend entirely on NAND flash technology (generation or memory cell type). The device handles these management functions internally, making them invisible to the host
processor.
Defect and Error Management
Micron e.MMC incorporates advanced technology for defect and error management. If
a defective block is identified, the device completely replaces it with a spare block. This
process is invisible to the host and does not affect user-allocated data space.
The device also includes a built-in error correction code (ECC) algorithm to ensure data
integrity is maintained. To best implement these advanced technologies and ensure
proper data loading and storage over the life of the device, the host must follow these
precautions:
• Check the status after WRITE, READ, and ERASE operations.
• Avoid power-down during WRITE and ERASE operations.
As best practice, Micron recommends the usage of Power Off Notification (PON) and refresh mechanism.
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OCR Register
OCR Register
The 32-bit operation conditions register (OCR) stores the voltage profile of the card and
the access mode indication. In addition, this register includes a status information bit.
Table 7: OCR Parameters
OCR Bits
OCR Value
[31]
1b (ready)/0b (busy)1
[30:29]
10b
[28:24]
0 0000b
[23:15]
1 1111 1111b
2.7–3.6V voltage range
[14:8]
000 0000b
2.0–2.7V voltage range
[7]
1b
[6:0]
000 0000b
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
Description
Device power-on status bit
Sector mode
Reserved
1.70–1.95V voltage range
Reserved
1. OCR = C0FF8080h after the device has completed power-up.
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CID Register
CID Register
The card identification (CID) register is 128 bits wide. It contains the device identification information used during the card identification phase as required by e.MMC protocol. Each device is created with a unique identification number.
Table 8: CID Register Field Parameters
Name
Field
Width
CID Bits
CID Value
Manufacturer ID
MID
8
[127:120]
13h
Reserved
–
6
[119:114]
–
Card/BGA
CBX
2
[113:112]
1h
OEM/application ID
OID
8
[111:104]
–
Product name
PNM
48
[103:56]
8GB: S0J35X
16GB: S0J56X
32GB: S0J57X
64GB: S0J58X
128GB: S0J59X
Product revision
PRV
8
[55:48]
–
Product serial number
PSN
32
[47:16]
–
Manufacturing date
MDT
8
[15:8]
–
CRC7 checksum
CRC
7
[7:1]
–
–
1
[0]
–
Not used; always 1
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CSD Register
CSD Register
The card-specific data (CSD) register provides information about accessing the device
contents. The CSD register defines the data format, error correction type, maximum data access time, and data transfer speed, as well as whether the DS register can be used.
The programmable part of the register (entries marked with W or E in the following table) can be changed by the PROGRAM_CSD (CMD27) command.
Table 9: CSD Register Field Parameters
Size
Cell
Density (Bits) Type1
CSD
Bits
CSD Value
R
[127:126]
3h
4
R
[125:122]
4h
–
2
–
[121:120]
–
Name
Field
CSD structure
CSD_STRUCTURE
–
2
System specification version
SPEC_VERS
–
Reserved2
–
Data read access time 1
TAAC
–
8
R
[119:112]
7Fh
Data read access time 2 in CLK
cycles (NSAC × 100)
NSAC
–
8
R
[111:104]
01h
Maximum bus clock frequency
TRAN_SPEED
–
8
R
[103:96]
32h
Card command classes
CCC
–
12
R
[95:84]
8F5h
Maximum read data block
length
READ_BL_LEN
–
4
R
[83:80]
9h
Partial blocks for reads supported
READ_BL_PARTIAL
–
1
R
[79]
0h
Write block misalignment
WRITE_BLK_MISALIGN
–
1
R
[78]
0h
Read block misalignment
READ_BLK_MISALIGN
–
1
R
[77]
0h
DSR implemented
DSR_IMP
–
1
R
[76]
0h
–
2
–
[75:74]
–
Reserved
–
Device size
C_SIZE
–
12
R
[73:62]
FFFh
Maximum read current at
VDD,min
VDD_R_CURR_MIN
–
3
R
[61:59]
0h
Maximum read current at
VDD,max
VDD_R_CURR_MAX
–
3
R
[58:56]
0h
Maximum write current at
VDD,min
VDD_W_CURR_MIN
–
3
R
[55:53]
0h
Maximum write current at
VDD,max
VDD_W_CURR_MAX
–
3
R
[52:50]
0h
Device size multiplier
C_SIZE_MULT
–
3
R
[49:47]
7h
Erase group size
ERASE_GRP_SIZE
–
5
R
[46:42]
1Fh
Erase group size multiplier
ERASE_GRP_MULT
–
5
R
[41:37]
1Fh
Write protect group size
WP_GRP_SIZE
–
5
R
[36:32]
0Fh
Write protect group enable
WP_GRP_ENABLE
–
1
R
[31]
1h
Manufacturer default ECC
DEFAULT_ECC
–
2
R
[30:29]
0h
Write-speed factor
R2W_FACTOR
–
3
R
[28:26]
1h
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
14
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© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
CSD Register
Table 9: CSD Register Field Parameters (Continued)
Size
Cell
Density (Bits) Type1
CSD
Bits
CSD Value
R
[25:22]
9h
1
R
[21]
0h
–
4
–
[20:17]
–
Name
Field
Maximum write data block
length
WRITE_BL_LEN
–
4
Partial blocks for writes supported
WRITE_BL_PARTIAL
–
Reserved
–
Content protection application
CONTENT_PROT_APP
–
1
R
[16]
0h
File-format group
FILE_FORMAT_GRP
–
1
R/W
[15]
0h
Copy flag (OTP)
COPY
–
1
R/W
[14]
0h
Permanent write protection
PERM_WRITE_PROTECT
–
1
R/W
[13]
0h
Temporary write protection
TMP_WRITE_PROTECT
–
1
R/W/E
[12]
0h
File format
FILE_FORMAT
–
2
R/W
[11:10]
0h
ECC
ECC
–
2
R/W/E
[9:8]
0h
CRC
CRC
–
7
R/W/E
[7:1]
–
–
1
–
[0]
–
Reserved
–
Notes:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. R = Read-only;
R/W = One-time programmable and readable;
R/W/E = Multiple writable with value kept after a power cycle, assertion of the RST_n
signal, and any CMD0 reset, and readable
2. Reserved bits should be read as 0.
15
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© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
ECSD Register
The 512-byte extended card-specific data (ECSD) register defines device properties and
selected modes. The most significant 320 bytes are the properties segment. This segment defines device capabilities and cannot be modified by the host. The lower 192
bytes are the modes segment. The modes segment defines the configuration in which
the device is working. The host can change the properties of modes segments using the
SWITCH command.
Table 10: ECSD Register Field Parameters
Name
Size
Density (Bytes)
Field
Cell
Type1
ECSD
Bytes
ECSD
Value
Properties Segment
Reserved2
–
–
6
–
[511:506]
–
Extended security error support EXT_SECURITY_ERR
–
1
R
[505]
00h
Supported command sets
S_CMD_SET
–
1
R
[504]
01h
HPI features
HPI_FEATURES
–
1
R
[503]
01h
Background operations support BKOPS_SUPPORT
–
1
R
[502]
01h
Max-packed READ commands
MAX_PACKED_READS
–
1
R
[501]
00h
Max-packed WRITE commands
MAX_PACKED_WRITES
–
1
R
[500]
00h
Data tag support
DATA_TAG_SUPPORT
–
1
R
[499]
01h
Tag unit size
TAG_UNIT_SIZE
–
1
R
[498]
03h
Tag resources size
TAG_RES_SIZE
–
1
R
[497]
00h
Context management capabilities
CONTEXT_CAPABILITIES
–
1
R
[496]
05h
Large unit size
LARGE_UNIT_SIZE_M1
–
1
R
[495]
03h
Extended partitions attribute
support
EXT_SUPPORT
–
1
R
[494]
03h
Supported modes
SUPPORTED_MODES
–
1
R
[493]
01h
Field firmware update features
FFU_FEATURES
–
1
R
[492]
00h
Operation code timeout
OPERATION_CODE_TIMEOUT
–
1
R
[491]
00h
Field firmware update arguments
FFU_ARG
–
4
R
[490:487]
0000FFFFh
Barrier support
BARRIER_SUPPORT
–
1
R
[486]
01h
Reserved
–
–
177
–
[485:309]
–
CMD queuing support
CMDQ_SUPPORT
–
1
R
[308]
01h
CMD queuing depth
CMDQ_DEPTH
–
1
R
[307]
1Fh
–
1
–
[306]
–
Reserved
–
Number of firmware sectors
correctly programmed
NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED
–
4
R
[305:302]
00h
Vendor proprietary health report
VENDOR_PROPRIETARY_HEALTH_REPORT
–
32
R
[301:270]
00h
–
1
R
[269]
01h
Device life time estimate type B DEVICE_LIFE_TIME_EST_TYP_B
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Name
Size
Density (Bytes)
Field
Cell
Type1
ECSD
Bytes
ECSD
Value
Device life time estimate type A DEVICE_LIFE_TIME_EST_TYP_A
–
1
R
[268]
01h
Pre-end-of-life information
PRE_EOL_INFO
–
1
R
[267]
01h
Optimal read size
OPTIMAL_READ_SIZE
–
1
R
[266]
00h
Optimal write size
OPTIMAL_WRITE_SIZE
–
1
R
[265]
40h
Optimal trim unit size
OPTIMAL_TRIM_UNIT_SIZE
–
1
R
[264]
00h
Device version
DEVICE_VERSION
–
2
R
[263:262]
0000h
Firmware version
FIRMWARE_VERSION
–
8
R
[261:254]
–
Power class for 200 MHz
DDR at VCC = 3.6V
PWR_CL_DDR_200_360
–
1
R
[253]
00h
Cache size
CACHE_SIZE
8GB
4
R
[252:249]
00000200h
16GB
00000400h
32GB
00000800h
64GB
128GB
Generic CMD6 timeout
GENERIC_CMD6_TIME
–
1
R
[248]
0Ah
Power-off notification (long)
timeout
POWER_OFF_LONG_TIME
–
1
R
[247]
32h
Background operations status
BKOPS_STATUS
–
1
R
[246]
00h
Number of correctly programmed sectors
CORRECTLY_PROG_SECTORS_NUM
–
4
R
[245:242]
00000000h
First initialization time after
partitioning (first CMD1 to device ready)
INI_TIMEOUT_AP
–
1
R
[241]
0Ah
Cache flushing policy
CACHE_FLUSH_POLICY
–
1
R
[240]
01h
Power class for 52 MHz, DDR at PWR_CL_DDR_52_360
3.6V
–
1
R
[239]
00h
Power class for 52 MHz, DDR at PWR_CL_DDR_52_195
1.95V
–
1
R
[238]
00h
Power class for 200 MHz at
1.95V
PWR_CL_200_195
–
1
R
[237]
00h
Power class for 200 MHz, at
1.3V
PWR_CL_200_130
–
1
R
[236]
00h
Minimum write performance
for 8-bit at 52 MHz in DDR
mode
MIN_PERF_DDR_W_8_52
–
1
R
[235]
00h
Minimum read performance for MIN_PERF_DDR_R_8_52
8-bit at 52 MHz in DDR mode
–
1
R
[234]
00h
Reserved
–
1
–
[233]
–
–
TRIM multiplier
TRIM_MULT
–
1
R
[232]
01h
Secure feature support
SEC_FEATURE_SUPPORT
–
1
R
[231]
51h
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Size
Density (Bytes)
Cell
Type1
ECSD
Bytes
ECSD
Value
1
R
[230]
01h
–
1
R
[229]
01h
–
1
R
[228]
07h
Name
Field
Secure erase multiplier
SEC_ERASE_MULT
–
Secure trim multiplier
SEC_TRIM_MULT
Boot information
BOOT_INFO
Reserved
–
1
–
[227]
–
Boot partition size3
BOOT_SIZE_MULT
–
–
1
R
[226]
FCh
Access size
ACC_SIZE
–
1
R
[225]
00h
High-capacity erase unit size
HC_ERASE_GRP_SIZE
–
1
R
[224]
01h
High-capacity erase timeout
ERASE_TIMEOUT_MULT
–
1
R
[223]
01h
Reliable write-sector count
REL_WR_SEC_C
–
1
R
[222]
01h
High-capacity write protect
group size
HC_WP_GRP_SIZE
8GB
1
R
[221]
10h
16GB
32GB
64GB
20h
128GB
40h
Sleep current (VCC)
S_C_VCC
–
1
R
[220]
00h
Sleep current (VCCQ)
S_C_VCCQ
–
1
R
[219]
00h
Production state awareness
timeout
PRODUCTION_STATE_AWARENESS_TIMEOUT
–
1
R
[218]
00h
Sleep/awake timeout
S_A_TIMEOUT
–
1
R
[217]
14h
Sleep notification timeout
SLEEP_NOTIFICATION_TIME
–
1
R
[216]
0Eh
Sector count
SEC_COUNT
8GB
4
R
[215:212]
00E90000h
16GB
01DA4000h
32GB
03B48000h
64GB
07690000h
128GB
0ED20000h
Secure write protect Information
SECURE_WP_INFO
–
1
R
[211]
01h
Minimum write performance
for 8-bit at 52 MHz
MIN_PERF_W_8_52
–
1
R
[210]
00h
Minimum read performance for MIN_PERF_R_8_52
8-bit at 52 MHz
–
1
R
[209]
00h
Minimum write performance
MIN_PERF_W_8_26_4_52
for 8-bit at 26 MHz and 4-bit at
52 MHz
–
1
R
[208]
00h
Minimum read performance for MIN_PERF_R_8_26_4_52
8-bit at 26 MHz and 4-bit at 52
MHz
–
1
R
[207]
00h
Minimum write performance
for 4-bit at 26 MHz
–
1
R
[206]
00h
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
MIN_PERF_W_4_26
18
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Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Name
Size
Density (Bytes)
Field
Cell
Type1
ECSD
Bytes
ECSD
Value
Minimum read performance for MIN_PERF_R_4_26
4-bit at 26 MHz
–
1
R
[205]
00h
Reserved
–
1
–
[204]
–
–
Power class for 26 MHz at 3.6V
PWR_CL_26_360
–
1
R
[203]
00h
Power class for 52 MHz at 3.6V
PWR_CL_52_360
–
1
R
[202]
00h
Power class for 26 MHz at 1.95V PWR_CL_26_195
–
1
R
[201]
00h
Power class for 52 MHz at 1.95V PWR_CL_52_195
–
1
R
[200]
00h
Partition switching timing
PARTITION_SWITCH_TIME
–
1
R
[199]
01h
Out-of-interrupt busy timing
OUT_OF_INTERRUPT_TIME
–
1
R
[198]
0Fh
I/O driver strength
DRIVER_STRENGTH
–
1
R
[197]
1Fh
Device type
DEVICE_TYPE
–
1
R
[196]
57h
–
–
1
–
[195]
–
CSD_STRUCTURE
–
1
R
[194]
02h
–
–
1
–
[193]
–
–
1
R
[192]
08h
–
1
R/W/E_P
[191]
00h
–
1
–
[190]
–
–
1
R
[189]
00h
–
1
–
[188]
–
–
1
R/W/E_P
[187]
00h
–
1
–
[186]
–
Reserved
CSD structure version
Reserved
Extended CSD revision
EXT_CSD_REV
Modes Segment
Command set
CMD_SET
Reserved
Command set revision
–
CMD_SET_REV
Reserved
Power class
–
POWER_CLASS
Reserved
–
High-speed interface timing
HS_TIMING
–
1
R/W/E_P
[185]
00h
Strobe support
STROBE_SUPPORT
–
1
R
[184]
00h
Bus width mode
BUS_WIDTH
–
1
W/E_P
[183]
00h
–
1
–
[182]
–
–
1
R
[181]
00h
–
1
–
[180]
–
Reserved
Erased memory content
Reserved
–
ERASED_MEM_CONT
–
Partition configuration
PARTITION_CONFIG
–
1
R/W/E,
R/W/E_P
[179]
00h
Boot configuration protection
BOOT_CONFIG_PROT
–
1
R/W,
R/W/C_P
[178]
00h
Boot bus conditions
BOOT_BUS_CONDITIONS
–
1
R/W/E
[177]
00h
–
1
–
[176]
–
High-density erase group defini- ERASE_GROUP_DEF
tion
–
1
R/W/E_P
[175]
00h
Boot write protection status
registers
–
1
R
[174]
00h
Reserved
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
–
BOOT_WP_STATUS
19
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Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Name
Size
Density (Bytes)
Field
Boot area write protection reg- BOOT_WP
ister
Reserved
–
User write protection register
USER_WP
Reserved
–
Cell
Type1
ECSD
Bytes
ECSD
Value
–
1
R/W,
R/W/C_P
[173]
00h
–
1
–
[172]
–
–
1
R/W,
R/W/C_P,
R/W/E_P
[171]
00h
–
1
–
[170]
–
Firmware configuration
FW_CONFIG
–
1
R/W
[169]
00h
RPMB size
RPMB_SIZE_MULT
–
1
R
[168]
20h
Write reliability setting
WR_REL_SET
Write reliability parameter reg- WR_REL_PARAM
ister
–
1
R/W
[167]
1Fh
–
1
R
[166]
15h
SANITIZE START operation
SANITIZE_START
–
1
W/E_P
[165]
00h
Manually start background operations
BKOPS_START
–
1
W/E_P
[164]
00h
Enable background operations
handshake
BKOPS_EN
–
1
R/W
[163]
00h
Hardware reset function
RST_n_FUNCTION
–
1
R/W
[162]
00h
HPI management
HPI_MGMT
–
1
R/W/E_P
[161]
00h
Partitioning support
PARTITIONING_SUPPORT
–
1
R
[160]
07h
Maximum enhanced area size
MAX_ENH_SIZE_MULT
8GB
3
R
[159:157]
0001C9h
register4
16GB
0003ABh
32GB
000760h
64GB
000764h
128GB
000766h
Partitions attribute
PARTITIONS_ATTRIBUTE
–
1
R/W
[156]
00h
Partitioning setting
PARTITION_SETTING_COMPLETED
–
1
R/W
[155]
00h
General-purpose partition size
GP_SIZE_MULT
–
12
R/W
[154:143]
00h
Enhanced user data area size
ENH_SIZE_MULT
–
3
R/W
[142:140]
000000h
Enhanced user data start address
ENH_START_ADDR
–
4
R/W
[139:136]
00000000h
Reserved
–
1
–
[135]
–
Bad block management mode
SEC_BAD_BLK_MGMNT
–
1
R/W
[134]
00h
Production state awareness
PRODUCTION_STATE_AWARENESS
–
1
R/W/E
[133]
00h
Package case temperature is
controlled
TCASE_SUPPORT
–
1
W/E_P
[132]
00h
Periodic wake-up
PERIODIC_WAKEUP
–
1
R/W/E
[131]
00h
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
–
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Size
Density (Bytes)
Name
Field
Program CID/CSD in DDR mode
support
PROGRAM_CID_CSD_DDR_SUPPORT
Reserved
–
Cell
Type1
ECSD
Bytes
ECSD
Value
–
1
R
[130]
01h
–
2
–
[129:128]
–
[127:64]
–
Vendor specific fields
VENDOR_SPECIFIC_FIELD
–
64
Native sector size
NATIVE_SECTOR_SIZE
–
1
R
[63]
00h
Sector size emulation
USE_NATIVE_SECTOR
–
1
R/W
[62]
00h
Sector size
DATA_SECTOR_SIZE
–
1
R
[61]
00h
First initialization after disabling sector size emulation
INI_TIMEOUT_EMU
–
1
R
[60]
00h
Class 6 commands control
CLASS_6_CTRL
–
1
R/W/E_P
[59]
00h
Number of addressed group to
be released
DYNCAP_NEEDED
–
1
R
[58]
00h
Exception events control
EXCEPTION_EVENTS_CTRL
–
2
R/W/E_P
[57:56]
0000h
Exception events status
EXCEPTION_EVENTS_STATUS
–
2
R
[55:54]
0000h
Extended partitions attribute
EXT_PARTITIONS_ATTRIBUTE
–
2
R/W
[53:52]
0000h
Context configuration
CONTEXT_CONF
–
15
R/W/E_P
[51:37]
00h
Packed command status
PACKED_COMMAND_STATUS
–
1
R
[36]
00h
Packed command failure index
PACKED_FAILURE_INDEX
–
1
R
[35]
00h
Power-off notification
POWER_OFF_NOTIFICATION
–
1
R/W/E_P
[34]
00h
Control to turn the cache on/off CACHE_CTRL
–
1
R/W/E_P
[33]
00h
Flushing of the cache
FLUSH_CACHE
–
1
W/E_P
[32]
00h
Control to turn the barrier
on/off
BARRIER_CTRL
–
1
R/W
[31]
00h
Mode configuration
MODE_CONFIG
–
1
R/W/E_P
[30]
00h
Mode operation codes
MODE_OPERATION_CODES
–
1
W/E_P
[29]
00h
–
2
–
[28:27]
–
–
1
R
[26]
00h
–
4
R/W/E_P
[25:22]
00h
8GB
4
R
[21:18]
005D3310h
Reserved
–
Field firmware update status
FFU_STATUS
Pre-loading data size
PRE LOADING DATA SIZE
Maximum pre-loading data size MAX_PRE_LOADING_DATA_SIZE
16GB
00BDB320h
32GB
017B6640h
64GB
02F6CCA8h
128GB
05ED9978h
Product state awareness enable- PRODUCT_STATE_AWAREment
NESS_ENABLEMENT
–
1
R/W/E, R
[17]
03h
Secure removal type
SECURE_REMOVAL_TYPE
–
1
R/W, R
[16]
01h
Command queue mode enable
CMDQ_MODE_EN
–
1
R/W/E_P
[15]
00h
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
21
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© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
ECSD Register
Table 10: ECSD Register Field Parameters (Continued)
Name
Size
Density (Bytes)
Field
Reserved
–
Notes:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
–
15
Cell
Type1
ECSD
Bytes
ECSD
Value
–
[14:0]
–
1. R = Read-only;
R/W = One-time programmable and readable;
R/W/E = Multiple writable with the value kept after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable;
R/W/C_P = Writable after the value is cleared by a power cycle and assertion of the
RST_n signal (the value not cleared by CMD0 reset) and readable;
R/W/E_P = Multiple writable with the value reset after a power cycle, assertion of the
RST_n signal, and any CMD0 reset, and readable;
W/E_P = Multiple writable with the value reset after power cycle, assertion of the RST_n
signal, and any CMD0 reset, and not readable
2. Reserved bits should be read as 0.
3. Boot partition size is configurable by host. Refer to local Micron support for information.
4. Micron has tested power failure under best-application knowledge conditions with positive results. Customers may request a dedicated test for their specific application condition. Micron set this register during factory test and used the one-time programming
option.
22
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© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
DC Electrical Specifications – Device Power
DC Electrical Specifications – Device Power
The device current consumption for various device configurations is defined in the
power class fields of the ECSD register.
VCC is used for the NAND Flash device and its interface voltage; V CCQ is used for the
controller and the e.MMC interface voltage.
Figure 6: Device Power Diagram
VCC
VCCQ
C3
C4
C1
C2
RST_n
DS
Core regulator
NAND
control signals
CLK
CMD
DAT[7:0]
C6
NAND Flash
NAND
I/O block
C5
MMC
I/O block
VDDIM
Core
logic block
NAND
data bus
VCCQ
MMC controller
VCCQ
Table 11: Absolute Maximum Ratings
Parameters
Symbol
Min
Max
Unit
Voltage input
VIN
–0.6
4.6
V
VCC supply
VCC
–0.6
4.6
V
VCCQ supply
VCCQ
–0.6
4.6
V
Storage temperature
TSTG
–40
85
°C
Note:
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
1. Voltage on any pin relative to VSS.
23
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Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
Product features
Table 12: Capacitor and Resistance Specifications
Parameter
Pull-up resistance: CMD
Pull-up resistance: DAT[7:0]
Pull-up resistance: RST_n
Symbol
Min
Max
Typ
Units
Notes
R_CMD
4.7
50
10
kΩ
1
R_DAT
10
50
50
kΩ
1
R_RST_n
4.7
50
50
kΩ
2
45
55
50
Ω
3
0
47
22
Ω
CLK/CMD/DS/DAT[7:0] impedance
Serial resistance on CLK
SR_CLK
Serial resistance on DS
SR_DS
0
47
22
Ω
Pull-down resistance: DS
R_DS
10
100
–
kΩ
C1
2.2
4.7
2.2
µF
5
C2
0.1
0.22
0.1
C3
2.2
4.7
2.2
µF
6
C4
0.1
0.22
0.1
C5
1
4.7
1
µF
7
C6
0.1
0.1
0.1
VCCQ capacitor
VCC capacitor
VDDIM capacitor (Creg)
4
1. Used to prevent bus floating.
2. If host does not use H/W RESET (RST_n), pull-up resistance is not needed on RST_n line
(Extended_CSD[162] = 00h).
3. Impedance match.
4. Recommended to compensate eventual impedance mismatch on the PCB.
5. The coupling capacitor should be connected with VCCQ and VSSQ as closely as possible.
6. The coupling capacitor should be connected with VCC and VSS as closely as possible.
7. The coupling capacitor should be connected with VDDIM and VSS as closely as possible.
Notes:
Product features
The list below shows the JEDEC features not supported. See the full JEDEC/MMC
Standard No. 84-B51 available at www.jedec.org/sites/files/docs/JESD84-B51.pdf:
•
•
•
•
•
•
•
•
Packed CMDs
Context ID/Data tag (this feature is implemented at the protocol level)
Dynamic device capacity
Thermal spec
Large sector size – 4KB
Extended security protocol
Secure erase/secure trim*
Forced erase*
* The feature implements as logical erase mode: it moves the mapped host address
range to the unmapped host address range. When the operation is complete, the data
still exists, but the mapped device address range behaves as if overwritten with all 0s.
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
Micron Confidential and Proprietary
8GB, 16GB, 32GB, 64GB, 128GB: e.MMC (Industrial)
Revision History
Revision History
Rev. D – 5/20
• Added MPN 8GB to the list
Rev. C – 3/19
• Updated legal status to Production
Rev. B – 12/18
• Updated table format
Rev. A – 8/18
• Initial preliminary version release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
CCM005-841846911-10468
emmc_industrial_8_128GB_v5_1.pdf - Rev. D 05/20 EN
25
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2020 Micron Technology, Inc. All rights reserved.
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