N25Q128A13ESFC0G

128Mb, 3V, Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q128A Features • • • • • • • • • • • • • Write protection – Software write protection applicable to every 64KB sector via volatile lock bit – Hardware write protection: protected area size defined by five nonvolatile bits (BP0, BP1, BP2, BP3, and TB) – Additional smart protections, available upon request • Electronic signature – JEDEC-standard 2-byte signature (BA18h) – Unique ID code (UID): 17 read-only bytes, including: SPI-compatible serial bus interface 108 MHz (MAX) clock frequency 2.7–3.6V single supply voltage Dual/quad I/O instruction provides increased throughput up to 432 MHz Supported protocols – Extended SPI, dual I/O, and quad I/O Execute-in-place (XIP) mode for all three protocols – Configurable via volatile or nonvolatile registers – Enables memory to work in XIP mode directly after power-on PROGRAM/ERASE SUSPEND operations Continuous read of entire memory via a single command – Fast read – Quad or dual output fast read – Quad or dual I/O fast read Flexible to fit application – Configurable number of dummy cycles – Output buffer configurable Software reset 64-byte, user-lockable, one-time programmable (OTP) dedicated area Erase capability – Subsector erase 4KB uniform granularity blocks – Sector erase 64KB uniform granularity blocks – Full-chip erase 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN • Two additional extended device ID (EDID) bytes to identify device factory options • Customized factory data (14 bytes) • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages JEDEC standard, all RoHS compliant – F7 = V-PDFN-8 6mm x 5mm Sawn (MLP8 6mm x 5mm) – F8 = V-PDFN-8 8mm x 6mm (MLP8 8mm x 6mm) – 12 = T-PBGA-24b05 6mm x 8mm – 14 = T-PBGA-24b05 6mm x 8mm, 4x6 ball array – SF = SOP2-16 300 mils body width (SO16W) – SE = SOP2-8 208 mils body width (SO8W) 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb, 3V, Multiple I/O Serial Flash Memory Features Contents Important Notes and Warnings ......................................................................................................................... 6 Device Description ........................................................................................................................................... 7 Features ....................................................................................................................................................... 7 Operating Protocols ...................................................................................................................................... 7 XIP Mode ..................................................................................................................................................... 7 Device Configurability .................................................................................................................................. 8 Signal Assignments ........................................................................................................................................... 9 Signal Descriptions ......................................................................................................................................... 11 Memory Organization .................................................................................................................................... 13 Memory Configuration and Block Diagram .................................................................................................. 13 Memory Map – 128Mb Density ....................................................................................................................... 14 Device Protection ........................................................................................................................................... 15 Serial Peripheral Interface Modes .................................................................................................................... 17 SPI Protocols .................................................................................................................................................. 20 Nonvolatile and Volatile Registers ................................................................................................................... 21 Status Register ............................................................................................................................................ 22 Nonvolatile and Volatile Configuration Registers .......................................................................................... 23 Enhanced Volatile Configuration Register .................................................................................................... 26 Flag Status Register ..................................................................................................................................... 27 Command Definitions .................................................................................................................................... 29 READ REGISTER and WRITE REGISTER Operations ........................................................................................ 31 READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 31 READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 31 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 32 WRITE STATUS REGISTER Command ......................................................................................................... 32 WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 33 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 33 READ LOCK REGISTER Command .............................................................................................................. 34 WRITE LOCK REGISTER Command ............................................................................................................ 35 CLEAR FLAG STATUS REGISTER Command ................................................................................................ 36 READ IDENTIFICATION Operations ............................................................................................................... 37 READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 37 READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 38 READ MEMORY Operations ............................................................................................................................ 41 PROGRAM Operations .................................................................................................................................... 45 WRITE Operations .......................................................................................................................................... 49 WRITE ENABLE Command ......................................................................................................................... 49 WRITE DISABLE Command ........................................................................................................................ 49 ERASE Operations .......................................................................................................................................... 51 SUBSECTOR ERASE Command ................................................................................................................... 51 SECTOR ERASE Command ......................................................................................................................... 51 BULK ERASE Command ............................................................................................................................. 52 PROGRAM/ERASE SUSPEND Command ..................................................................................................... 53 PROGRAM/ERASE RESUME Command ...................................................................................................... 55 ONE TIME PROGRAMMABLE Operations ....................................................................................................... 56 READ OTP ARRAY Command ...................................................................................................................... 56 PROGRAM OTP ARRAY Command .............................................................................................................. 56 XIP Mode ....................................................................................................................................................... 58 Activate or Terminate XIP Using Volatile Configuration Register ................................................................... 58 Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. 58 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Features Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. Terminating XIP After a Controller and Memory Reset ................................................................................. Power-Up and Power-Down ............................................................................................................................ Power-Up and Power-Down Requirements .................................................................................................. Power Loss Rescue Sequence ...................................................................................................................... AC Reset Specifications ................................................................................................................................... Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics and Operating Conditions .................................................................................................. AC Characteristics and Operating Conditions – Standard ................................................................................. AC Characteristics and Operating Conditions – Enhanced ................................................................................ Package Dimensions ....................................................................................................................................... Part Number Ordering Information ................................................................................................................. Revision History ............................................................................................................................................. Rev. T – 02/2018 .......................................................................................................................................... Rev. S – 11/2014 .......................................................................................................................................... Rev. R - 07/2014 .......................................................................................................................................... Rev. Q – 05/2014 ......................................................................................................................................... Rev. P – 06/2013 .......................................................................................................................................... Rev. O – 04/2013 ......................................................................................................................................... Rev. N – 01/2013 ......................................................................................................................................... Rev. M – 07/2012 ........................................................................................................................................ Rev. L – 06/2012 .......................................................................................................................................... Rev. K – 02/2012 ......................................................................................................................................... Rev. J – 12/2011 .......................................................................................................................................... Rev. I – 10/2011 .......................................................................................................................................... Rev. H – 08/2011 ......................................................................................................................................... Rev. G – 08/2011 ......................................................................................................................................... Rev. F – 02/2011 .......................................................................................................................................... Rev. E – 01/2011 .......................................................................................................................................... Rev. D – 10/2010 ......................................................................................................................................... Rev. C – 02/2010 ......................................................................................................................................... Rev. B – 05/2009 ......................................................................................................................................... Rev. A – 01/2009 .......................................................................................................................................... 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 3 59 59 60 60 61 62 67 69 70 71 73 79 81 81 81 81 81 81 81 81 81 81 81 81 82 82 82 82 82 82 82 82 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 8 Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) ......................................................................... 9 Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) .................................................................................. 9 Figure 4: 24-Ball TBGA (Balls Down) .............................................................................................................. 10 Figure 5: 24-Ball TBGA , 4x6 (Balls Down) ....................................................................................................... 10 Figure 6: Block Diagram ................................................................................................................................ 13 Figure 7: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18 Figure 8: Bus Master and Memory Devices on the SPI Bus ............................................................................... 19 Figure 9: SPI Modes ....................................................................................................................................... 19 Figure 10: Internal Configuration Register ...................................................................................................... 21 Figure 11: READ REGISTER Command .......................................................................................................... 31 Figure 12: WRITE REGISTER Command ......................................................................................................... 33 Figure 13: READ LOCK REGISTER Command ................................................................................................. 35 Figure 14: WRITE LOCK REGISTER Command ............................................................................................... 36 Figure 15: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 38 Figure 16: READ Command ........................................................................................................................... 42 Figure 17: FAST READ Command ................................................................................................................... 42 Figure 18: DUAL OUTPUT FAST READ ........................................................................................................... 43 Figure 19: DUAL INPUT/OUTPUT FAST READ Command .............................................................................. 43 Figure 20: QUAD OUTPUT FAST READ Command ......................................................................................... 44 Figure 21: QUAD INPUT/OUTPUT FAST READ Command ............................................................................. 44 Figure 22: PAGE PROGRAM Command .......................................................................................................... 46 Figure 23: DUAL INPUT FAST PROGRAM Command ...................................................................................... 46 Figure 24: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 47 Figure 25: QUAD INPUT FAST PROGRAM Command ..................................................................................... 47 Figure 26: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 48 Figure 27: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 50 Figure 28: SUBSECTOR and SECTOR ERASE Command .................................................................................. 52 Figure 29: BULK ERASE Command ................................................................................................................ 53 Figure 30: READ OTP Command .................................................................................................................... 56 Figure 31: PROGRAM OTP Command ............................................................................................................ 57 Figure 32: XIP Mode Directly After Power-On .................................................................................................. 58 Figure 33: Power-Up Timing .......................................................................................................................... 60 Figure 34: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 63 Figure 35: Reset Enable ................................................................................................................................. 63 Figure 36: Serial Input Timing ........................................................................................................................ 63 Figure 37: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 64 Figure 38: Hold Timing .................................................................................................................................. 65 Figure 39: Output Timing .............................................................................................................................. 66 Figure 40: V PPH Timing .................................................................................................................................. 66 Figure 41: AC Timing Input/Output Reference Levels ...................................................................................... 68 Figure 42: V-PDFN-8 6mm x 5mm Sawn (MLP8) – Package Code: F7 ................................................................ 73 Figure 43: V-PDFN-8 8mm x 6mm (MLP8) – Package Code: F8 ........................................................................ 74 Figure 44: T-PBGA-24b05 6mm x 8mm – Package Code: 12 .............................................................................. 75 Figure 45: T-PBGA-24b05 6mm x 8mm – Package Code: 14 .............................................................................. 76 Figure 46: SOP2-16 (300 mils body width) – Package Code: SF ......................................................................... 77 Figure 47: SOP2-8 (208 mils body width) – Package Code: SE ........................................................................... 78 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Features List of Tables Table 1: Signal Descriptions ........................................................................................................................... Table 2: Sectors[255:0] ................................................................................................................................... Table 3: Data Protection using Device Protocols ............................................................................................. Table 4: Memory Sector Protection Truth Table .............................................................................................. Table 5: Protected Area Sizes – Upper Area ..................................................................................................... Table 6: Protected Area Sizes – Lower Area ...................................................................................................... Table 7: SPI Modes ........................................................................................................................................ Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ Table 9: Status Register Bit Definitions ........................................................................................................... Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... Table 11: Volatile Configuration Register Bit Definitions .................................................................................. Table 12: Sequence of Bytes During Wrap ....................................................................................................... Table 13: Supported Clock Frequencies .......................................................................................................... Table 14: Enhanced Volatile Configuration Register Bit Definitions .................................................................. Table 15: Flag Status Register Bit Definitions .................................................................................................. Table 16: Command Set ................................................................................................................................. Table 17: Lock Register .................................................................................................................................. Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... Table 19: Read ID Data Out ............................................................................................................................ Table 20: Extended Device ID, First Byte ......................................................................................................... Table 21: Serial Flash Discovery Parameter – Header Structure ........................................................................ Table 22: Parameter ID .................................................................................................................................. Table 23: Command/Address/Data Lines for READ MEMORY Commands ....................................................... Table 24: Data/Address Lines for PROGRAM Commands ................................................................................ Table 25: Suspend Parameters ....................................................................................................................... Table 26: Operations Allowed/Disallowed During Device States ...................................................................... Table 27: OTP Control Byte (Byte 64) .............................................................................................................. Table 28: XIP Confirmation Bit ....................................................................................................................... Table 29: Effects of Running XIP in Different Protocols .................................................................................... Table 30: Power-Up Timing and V WI Threshold ............................................................................................... Table 31: AC RESET Conditions ...................................................................................................................... Table 32: Absolute Ratings ............................................................................................................................. Table 33: Operating Conditions ...................................................................................................................... Table 34: Input/Output Capacitance .............................................................................................................. Table 35: AC Timing Input/Output Conditions ............................................................................................... Table 36: DC Current Characteristics and Operating Conditions ...................................................................... Table 37: DC Voltage Characteristics and Operating Conditions ...................................................................... Table 38: AC Characteristics and Operating Conditions – Standard Specifications ............................................ Table 39: AC Characteristics and Operating Conditions – Enhanced Specifications .......................................... Table 40: Part Number Information ................................................................................................................ Table 41: Package Details ............................................................................................................................... 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 5 11 14 15 15 15 16 17 20 22 23 24 26 26 26 27 29 34 37 37 37 39 39 41 45 54 54 57 59 59 61 62 67 67 67 68 69 69 70 71 79 80 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Important Notes and Warnings Important Notes and Warnings Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions. This document supersedes and replaces all information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized by Micron. Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage resulting from any use of non-automotive-grade products in automotive applications. Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage ("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron component for any critical application, customer and distributor shall indemnify and hold harmless Micron and its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims, costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the Micron product. Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems, applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component. Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort, warranty, breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly authorized representative. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. Features The memory is organized as 256 (64KB) main sectors that are further divided into 16 subsectors each (4096 subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole. The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections The device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. Operating Protocols The memory can be operated with three different protocols: • Extended SPI (standard SPI protocol upgraded with dual and quad operations) • Dual I/O SPI • Quad I/O SPI The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines. XIP Mode XIP mode requires only an address (no instruction) to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution. All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Device Description Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following: • • • • • • Number of dummy cycles for the fast READ commands Output buffer impedance SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI) Required XIP mode Enabling/disabling HOLD (RESET function) Enabling/disabling wrap mode Figure 1: Logic Diagram VCC DQ0 DQ1 C S# VPP/W#/DQ2 HOLD#/DQ3 VSS Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for more details. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments Signal Assignments Figure 2: 8-Pin, VDFPN8 – MLP8 and SOP2 – SO8W (Top View) Notes: S# 1 8 VCC DQ1 2 7 HOLD#/DQ3 W#/VPP/DQ2 3 6 C VSS 4 5 DQ0 1. On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB. 2. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Figure 3: 16-Pin, Plastic Small Outline – SO16 (Top View) Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN HOLD#/DQ3 1 16 C VCC 2 15 DQ0 DNU 3 14 DNU DNU 4 13 DNU DNU 5 12 DNU DNU 6 11 DNU S# 7 10 VSS DQ1 8 9 W#/VPP/DQ2 1. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Signal Assignments Figure 4: 24-Ball TBGA (Balls Down) 1 2 3 4 5 NC NC NC NC NC C VSS VCC NC NC S# NC W#/VPP/DQ2 NC NC DQ1 DQ0 HOLD#/DQ3 NC NC NC A B C D E Note: NC NC NC 1. See Part Number Ordering Information for complete package names and details. Figure 5: 24-Ball TBGA , 4x6 (Balls Down) 1 2 3 4 NC NC NC NC NC C VSS VCC NC S# NC W#/VPP/DQ2 NC DQ1 DQ0 HOLD#/DQ3 NC NC NC NC NC NC NC NC A B C D E F Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. See Part Number Ordering Information for complete package names and details. 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1: Signal Descriptions Symbol Type Description C Input Clock: Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock. S# Input Chip select: When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode (not deep power-down mode). Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. DQ0 Input and I/O Serial data: Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations: DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ1 Output and I/O Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations: DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage (VPP). In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ2 Input and I/O DQ2: When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally (to avoid unnecessary switching current) and float the signals before the memory device drives data on them. DQ3 Input and I/O DQ3: When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected. RESET# Control Input RESET: This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Signal Descriptions Table 1: Signal Descriptions (Continued) Symbol Type HOLD# Control Input HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a DTR operation is recognized. W# Control Input Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low (0V to VCC), the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits 3:0. W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. VPP Power Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to 0. In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. VCC Power Device core power supply: Source voltage. VSS Ground DNU – Do not use. NC – No connect. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN Description Ground: Reference for the VCC supply voltage. 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Memory Organization Memory Organization Memory Configuration and Block Diagram Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 16,777,216 bytes (8 bits each); 256 sectors (64KB each); 4096 subsectors (4KB each); and 65,536 pages (256 bytes each); and 64 OTP bytes are located outside the main memory array. Figure 6: Block Diagram HOLD# W#/VPP High voltage generator Control logic 64 OTP bytes S# C DQ0 DQ1 DQ2 DQ3 I/O shift register Address register and counter Status register 256 byte data buffer Y decoder 00FFFFFF 0000000h 00000FFh 256 bytes (page size) X decoder 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Memory Map – 128Mb Density Memory Map – 128Mb Density Table 2: Sectors[255:0] Address Range Sector Subsector Start End 255 4095 00FF F000h 00FF FFFFh ⋮ ⋮ ⋮ 4080 00FF 0000h 00FF 0FFFh ⋮ ⋮ ⋮ ⋮ 127 2047 007F F000h 007F FFFFh ⋮ ⋮ ⋮ 2032 007F 0000h 007F 0FFFh ⋮ ⋮ ⋮ ⋮ 63 1023 003F F000h 003F FFFFh ⋮ ⋮ ⋮ 1008 003F 0000h 003F 0FFFh ⋮ ⋮ ⋮ ⋮ 0 15 0000 F000h 0000 FFFFh ⋮ ⋮ ⋮ 0 0000 0000h 0000 0FFFh 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Device Protection Device Protection Table 3: Data Protection using Device Protocols Note 1 applies to the entire table Protection by: Description Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is outside the operating specification. Command execution check Ensures that the number of clock pulses is a multiple of one byte before executing a PROGRAM or ERASE command, or any command that writes to the device registers. WRITE ENABLE operation Ensures that commands modifying device data must be preceded by a WRITE ENABLE command, which sets the write enable latch bit in the status register. Note: 1. Extended, dual, and quad SPI protocol functionality ensures that device data is protected from excessive noise. Table 4: Memory Sector Protection Truth Table Note 1 applies to the entire table Sector Lock Register Sector Lock Down Bit Sector Write Lock Bit 0 0 Sector unprotected from PROGRAM and ERASE operations. Protection status reversible. 0 1 Sector protected from PROGRAM and ERASE operations. Protection status reversible. 1 0 Sector unprotected from PROGRAM and ERASE operations. Protection status not reversible except by power cycle or reset. 1 1 Sector protected from PROGRAM and ERASE operations. Protection status not reversible except by power cycle or reset. Note: Memory Sector Protection Status 1. Sector lock register bits are written to when the WRITE LOCK REGISTER command is executed. The command will not execute unless the sector lock down bit is cleared (see the WRITE LOCK REGISTER command). Table 5: Protected Area Sizes – Upper Area Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Upper 256th Sectors (0 to 254) 0 0 0 1 0 Upper 128th Sectors (0 to 253) 0 0 0 1 1 Upper 64th Sectors (0 to 251) 0 0 1 0 0 Upper 32th Sectors (0 to 247) 0 0 1 0 1 Upper 16nd Sectors (0 to 239) 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Device Protection Table 5: Protected Area Sizes – Upper Area (Continued) Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 0 0 1 1 0 Upper 8th Sectors (0 to 223) 0 0 1 1 1 Upper quarter Sectors (0 to 191) 0 1 0 0 0 Upper half Sectors (0 to 127) 0 1 0 0 1 All sectors None 0 1 0 1 0 All sectors None 0 1 0 1 1 All sectors None 0 1 1 0 0 All sectors None 0 1 1 0 1 All sectors None 0 1 1 1 0 All sectors None 0 1 1 1 1 All sectors None Note: 1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits. Table 6: Protected Area Sizes – Lower Area Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 1 0 0 0 0 None All sectors 1 0 0 0 1 Lower 256th Sectors (1 to 255) 1 0 0 1 0 Lower 128th Sectors (2 to 255) 1 0 0 1 1 Lower 64th Sectors (4 to 255) 1 0 1 0 0 Lower 32th Sectors (8 to 255) 1 0 1 0 1 Lower 16nd Sectors (16 to 255) 1 0 1 1 0 Lower 8th Sectors (32 to 255) 1 0 1 1 1 Lower quarter Sectors (64 to 255) 1 1 0 0 0 Lower half Sectors (128 to 255) 1 1 0 0 1 All sectors None 1 1 0 1 0 All sectors None 1 1 0 1 1 All sectors None 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All sectors None Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Serial Peripheral Interface Modes The device can be driven by a microcontroller while its serial peripheral interface is in either of the two modes shown here. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. Input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock. Table 7: SPI Modes Note: Note 1 applies to the entire table SPI Modes Clock Polarity CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0) CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1) 1. The listed SPI modes are supported in extended, dual, and quad SPI protocols. Shown below is an example of three memory devices in extended SPI protocol in a simple connection to an MCU on an SPI bus. Because only one device is selected at a time, that one device drives DQ1, while the other devices are High-Z. Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus master might enter a state in which all input/output is High-Z simultaneously, such as when the bus master is reset. Therefore, the serial clock must be connected to an external pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW. This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp = parasitic capacitance of the bus line), is shorter than the time the bus master leaves the SPI bus in High-Z. Example: Cp = 50pF, that is R × Cp = 5μs. The application must ensure that the bus master never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and HOLD# should be driven either HIGH or LOW, as appropriate. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Figure 7: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface: (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI bus master DQ1 DQ0 R CS3 SPI memory device VCC C VSS R DQ1 DQ0 SPI memory device VCC C VSS R DQ1 DQ0 VSS SPI memory device CS2 CS1 S# 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN W# HOLD# 18 S# W# HOLD# S# W# HOLD# Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Figure 8: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface: (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI bus master DQ1 DQ0 R CS3 SPI memory device VCC C VSS R DQ1 DQ0 SPI memory device VCC C VSS R DQ1 DQ0 VSS SPI memory device CS2 CS1 S# HOLD# S# HOLD# S# HOLD# Figure 9: SPI Modes CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN MSB 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory SPI Protocols SPI Protocols Table 8: Extended, Dual, and Quad SPI Protocols Protocol Name Command Input Extended DQ0 Multiple DQn lines, depending on the command Dual DQ[1:0] DQ[1:0] Address Input Data Input/Output Description Multiple DQn Device default protocol from the factory. Additional comlines, depending mands extend the standard SPI protocol and enable address on the command or data transmission on multiple DQn lines. DQ[1:0] Volatile selectable: When the enhanced volatile configuration register bit 6 is set to 0 and bit 7 is set to 1, the device enters the dual SPI protocol immediately after the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the default protocol after the next power-on. In addition, the device can return to default protocol using the rescue sequence or through new WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, without power-off or power-on. Nonvolatile selectable: When nonvolatile configuration register bit 2 is set, the device enters the dual SPI protocol after the next power-on. Once this register bit is set, the device defaults to the dual SPI protocol after all subsequent power-on sequences until the nonvolatile configuration register bit is reset to 1. Quad1 DQ[3:0] DQ[3:0] DQ[3:0] Volatile selectable: When the enhanced volatile configuration register bit 7 is set to 0, the device enters the quad SPI protocol immediately after the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the default protocol after the next power-on. In addition, the device can return to default protocol using the rescue sequence or through new WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, without poweroff or power-on. Nonvolatile selectable: When nonvolatile configuration register bit 3 is set to 0, the device enters the quad SPI protocol after the next power-on. Once this register bit is set, the device defaults to the quad SPI protocol after all subsequent power-on sequences until the nonvolatile configuration register bit is reset to 1. Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. In quad SPI protocol, all command/address input and data I/O are transmitted on four lines except during a PROGRAM and ERASE cycle performed with VPP. In this case, the device enters the extended SPI protocol to temporarily allow the application to perform a PROGRAM/ERASE SUSPEND operation or to check the write-in-progress bit in the status register or the program/erase controller bit in the flag status register. Then, when VPP goes LOW, the device returns to the quad SPI protocol. 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Nonvolatile and Volatile Registers The device features the following volatile and nonvolatile registers that users can access to store device parameters and operating configurations: • • • • • Status register Nonvolatile and volatile configuration registers Enhanced volatile configuration register Flag status register Lock register Note: The lock register is defined in READ LOCK REGISTER Command. In addition to these user-accessible registers, the working condition of memory is set by an internal configuration register that is not directly accessible to users. As shown below, parameters in the internal configuration register are loaded from the nonvolatile configuration register during each device boot phase or power-on reset. In this sense, then, the nonvolatile configuration register contains the default settings of memory. Also, during the life of an application, each time a WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER command executes to set configuration parameters in these respective registers, these new settings are copied to the internal configuration register. Therefore, memory settings can be changed in real time. However, at the next power-on reset, the memory boots according to the memory settings defined in the nonvolatile configuration register parameters. Figure 10: Internal Configuration Register Nonvolatile configuration register Register download is executed only during the power-on phase or after a reset, overwriting configuration register settings on the internal configuration register. Volatile configuration register and enhanced volatile configuration register Internal configuration register Register download is executed after a WRITE VOLATILE OR ENHANCED VOLATILE CONFIGURATION REGISTER command, overwriting configuration register settings on the internal configuration register. Device behavior 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Status Register Table 9: Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Status register 0 = Enabled write enable/disable 1 = Disabled Nonvolatile bit: Used with the W#/VPP signal to enable or disable writing to the status register. A one-time programmable bit used to lock permanently the entire status register. 2 5 Top/bottom 0 = Top 1 = Bottom Nonvolatile bit: Determines whether the protected memory area defined by the block protect bits starts from the top or bottom of the memory array. 3 6, 4:2 Block protect 3–0 See Protected Area Sizes – Upper Area and Lower Area tables in Device Protection Nonvolatile bit: Defines memory to be software protected against PROGRAM or ERASE operations. When one or more block protect bits is set to 1, a designated memory area is protected from PROGRAM and ERASE operations. 3 1 Write enable latch 0 = Cleared (Default) Volatile bit: The device always powers up with this bit 1 = Set cleared to prevent inadvertent WRITE STATUS REGISTER, PROGRAM, or ERASE operations. To enable these operations, the WRITE ENABLE operation must be executed first to set this bit. 4 0 Write in progress 0 = Ready 1 = Busy Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN Volatile bit: Indicates if one of the following command cycles is in progress: WRITE STATUS REGISTER WRITE NONVOLATILE CONFIGURATION REGISTER PROGRAM ERASE 4 1. Bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REGISTER commands, respectively. 2. The status register write enable/disable bit, combined with the W#/VPP signal as described in the Signal Descriptions, provides hardware data protection for the device as follows: When the enable/disable bit is set to 1, and the W#/VPP signal is driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REGISTER operation will not execute. The only way to exit this hardware-protected mode is to drive W#/VPP HIGH.This one-time programmable status register bit can be set to 1 only once. Afterward, the status register is set permanently to read-only, and the area protected by the status register block protect bits also is set permanently to read-only. 3. See Protected Area Sizes tables in Device Protection. The BULK ERASE command is executed only if all bits are 0. 4. Volatile bits are cleared to 0 by a power cycle or reset. 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Nonvolatile and Volatile Configuration Registers Table 10: Nonvolatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 15:12 Number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 Sets the number of dummy clock cycles subsequent to all FAST READ commands. The default setting targets the maximum allowed frequency and guarantees backward compatibility. 11:9 XIP mode at power-on reset 000 = XIP: Fast Read 001 = XIP: Dual Output Fast Read 010 = XIP: Dual I/O Fast Read 011 = XIP: Quad Output Fast Read 100 = XIP: Quad I/O Fast Read 101 = Reserved 110 = Reserved 111 = Disabled (Default) Enables the device to operate in the selected XIP mode immediately after power-on reset. 8:6 Output driver 000 = Reserved strength 001 = 90 Ohms 010 = 60 Ohms 011 = 45 Ohms 100 = Reserved 101 = 20 Ohms 110 = 15 Ohms 111 = 30 (Default) Optimizes impedance at VCC/2 output voltage. 5 Reserved X "Don't Care." 4 Reset/hold 0 = Disabled 1 = Enabled (Default) Enables or disables hold or reset. (Available on dedicated part numbers.) 3 Quad I/O pro- 0 = Enabled Enables or disables quad I/O protocol. tocol 1 = Disabled (Default, Extended SPI protcocol) 4 2 Dual I/O protocol 0 = Enabled 1 = Disabled (Default, Extended SPI protocol) Enables or disables dual I/O protocol. 4 1:0 Reserved X "Don't Care." 1:0 Reserved X "Don't Care." 1 Reserved X "Don't Care." 0 Lock 0 = Disabled nonvolatile 1 = Enabled (Default) configuration register Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 2, 3 When this bit is set to 0, the nonvolatile configuration register becomes permanently write protected and any WRITE NONVOLATILE CONFIGURATION REGISTER command is ignored. 1. Settings determine device memory configuration after power-on. The device ships from the factory with all bits erased to 1 (FFFFh). The register is read from or written to by 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURATION REGISTER commands, respectively. 2. The 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility. 3. If the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. The number of cycles must be set according to and sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Frequencies table. 4. If bits 2 and 3 are both set to 0, the device operates in quad I/O. When bits 2 or 3 are reset to 0, the device operates in dual I/O or quad I/O respectively, after the next poweron. Table 11: Volatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings 7:4 Description Notes Number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 Sets the number of dummy clock cycles subsequent to all FAST READ commands. The default setting targets maximum allowed frequency and guarantees backward compatibility. 3 XIP 0 = Enable 1 = Disable (default) Enables or disables XIP. For device part numbers with feature digit equal to 2 or 4, this bit is always "Don’t Care," so the device operates in XIP mode without setting this bit. 2 Reserved X = Default 0b = Fixed value. Wrap 00 = 16-byte boundary aligned 16-byte wrap: Output data wraps within an aligned 16byte boundary starting from the 3-byte address issued after the command code. 01 = 32-byte boundary aligned 32-byte wrap: Output data wraps within an aligned 32byte boundary starting from the 3-byte address issued after the command code. 10 = 64-byte boundary aligned 64-byte wrap: Output data wraps within an aligned 64byte boundary starting from the 3-byte address issued after the command code. 11 = sequential (default) Continuous reading (default): All bytes are read sequentially. 1:0 Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 2, 3 4 1. Settings determine the device memory configuration upon a change of those settings by the WRITE VOLATILE CONFIGURATION REGISTER command. The register is read from or written to by READ VOLATILE CONFIGURATION REGISTER or WRITE VOLATILE CONFIGURATION REGISTER commands respectively. 2. The 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility. 3. If the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. The number of cycles must be set according to and be sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Frequencies table. 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers 4. See the Sequence of Bytes During Wrap table. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 12: Sequence of Bytes During Wrap Starting Address 16-Byte Wrap 32-Byte Wrap 64-Byte Wrap 0 0-1-2- . . . -15-0-1- . . 0-1-2- . . . -31-0-1- . . 0-1-2- . . . -63-0-1- . . 1 1-2- . . . -15-0-1-2- . . 1-2- . . . -31-0-1-2- . . 1-2- . . . -63-0-1-2- . . 15 15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . . 15-16-17- . . . -63-0-1- . . 31 31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . . 31-32-33- . . . -63-0-1- . . 63 63-48-49- . . . -63-48-49- . . 63-32-33- . . . -63-32-33- . . 63-0-1- . . . -63-0-1- . . Table 13: Supported Clock Frequencies Note 1 applies to entire table Number of Dummy Clock Cycles FAST READ DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ 1 90 80 50 43 30 2 100 90 70 60 40 3 108 100 80 75 50 4 108 105 90 90 60 5 108 108 100 100 70 6 108 108 105 105 80 7 108 108 108 108 86 8 108 108 108 108 95 9 108 108 108 108 105 10 108 108 108 108 108 Note: Unit MHz 1. Values are guaranteed by characterization and not 100% tested in production. Enhanced Volatile Configuration Register Table 14: Enhanced Volatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Quad I/O protocol 0 = Enabled Enables or disables quad I/O protocol. 1 = Disabled (Default, extended SPI protocol) 2 6 Dual I/O protocol 0 = Enabled Enables or disables dual I/O protocol. 1 = Disabled (Default, extended SPI protocol) 2 5 Reserved X = Default 0b = Fixed value. 4 Reset/hold 0 = Disabled 1 = Enabled (Default) Enables or disables hold or reset. (Available on dedicated part numbers.) 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 14: Enhanced Volatile Configuration Register Bit Definitions (Continued) Note 1 applies to entire table Bit Name 3 VPP accelerator 2:0 Settings Description 0 = Enabled 1 = Disabled (Default) Enables or disables VPP acceleration for QUAD INPUT FAST PROGRAM and QUAD INPUT EXTENDED FAST PROGRAM OPERATIONS. Output driver strength 000 = Reserved 001 = 90 Ohms 010 = 60 Ohms 011 = 45 Ohms 100 = Reserved 101 = 20 Ohms 110 = 15 Ohms 111 = 30 (Default) Notes: Notes Optimizes impedance at VCC/2 output voltage. 1. Settings determine the device memory configuration upon a change of those settings by the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The register is read from or written to in all protocols by READ ENHANCED VOLATILE CONFIGURATION REGISTER or WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands, respectively. 2. If bits 6 and 7 are both set to 0, the device operates in quad I/O. When either bit 6 or 7 is reset to 0, the device operates in dual I/O or quad I/O, respectively, following the next WRITE ENHANCED VOLATILE CONFIGURATION command. Flag Status Register Table 15: Flag Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Program or erase controller 0 = Busy 1 = Ready Status bit: Indicates whether a PROGRAM, ERASE, WRITE STATUS REGISTER, or WRITE NONVOLATILE CONFIGURATION command cycle is in progress. 2, 3 6 Erase suspend 0 = Not in effect 1 = In effect Status bit: Indicates whether an ERASE operation has been or is going to be suspended. 3 5 Erase 0 = Clear 1 = Failure or protection error Error bit: Indicates whether an ERASE operation has succeeded or failed. 4, 5 4 Program 0 = Clear 1 = Failure or protection error Error bit: Indicates whether a PROGRAM operation has succeeded or failed. Also indicates an attempt to program a 0 to a 1 when VPP = VPPH and the data pattern is a multiple of 64 bits. 4, 5 3 VPP 0 = Enabled 1 = Disabled (Default) Error bit: Indicates an invalid voltage on VPP during a PROGRAM or ERASE operation. 4, 5 2 Program suspend 0 = Not in effect 1 = In effect Status bit: Indicates whether a PROGRAM operation has been or is going to be suspended. 3 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 15: Flag Status Register Bit Definitions (Continued) Note 1 applies to entire table Bit Name Settings Description Notes 1 Protection 0 = Clear 1 = Failure or protection error Error bit: Indicates whether an ERASE or a PROGRAM operation has attempted to modify the protected array sector, or whether a PROGRAM operation has attempted to access the locked OTP space. 0 Reserved Reserved Reserved Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 4, 5 1. Register bits are read by READ FLAG STATUS REGISTER command. All bits are volatile. 2. These program/erase controller settings apply only to PROGRAM or ERASE command cycles in progress, or to the specific WRITE command cycles in progress as shown here. 3. Status bits are reset automatically. 4. Error bits must be reset by CLEAR FLAG STATUS REGISTER command. 5. Typical errors include operation failures and protection errors caused by issuing a command before the error bit has been reset to 0. 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Command Definitions Command Definitions Table 16: Command Set Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes RESET ENABLE 66h Yes Yes Yes 0 2 RESET MEMORY 99h Command RESET Operations IDENTIFICATION Operations READ ID 9E/9Fh Yes No No 1 to 20 2 MULTIPLE I/O READ ID AFh No Yes Yes 1 to 3 2 READ SERIAL FLASH DISCOVERY PARAMETER 5Ah Yes Yes Yes 1 to ∞ 3 READ 03h Yes No No 1 to ∞ 4 FAST READ 0Bh Yes Yes Yes DUAL OUTPUT FAST READ 3Bh Yes Yes No DUAL INPUT/OUTPUT FAST READ 0Bh 3Bh BBh Yes Yes No QUAD OUTPUT FAST READ 6Bh Yes No Yes QUAD INPUT/OUTPUT FAST READ 0Bh 6Bh EBh Yes No Yes WRITE ENABLE 06h Yes Yes Yes 0 2 WRITE DISABLE 04h Yes Yes Yes 1 to ∞ 2 1 2, 8 READ Operations 5 1 to ∞ 5 5, 6 1 to ∞ 5 5, 7 WRITE Operations REGISTER Operations READ STATUS REGISTER 05h WRITE STATUS REGISTER 01h READ LOCK REGISTER E8h WRITE LOCK REGISTER E5h READ FLAG STATUS REGISTER 70h CLEAR FLAG STATUS REGISTER 50h READ NONVOLATILE CONFIGURATION REGISTER B5h WRITE NONVOLATILE CONFIGURATION REGISTER B1h READ VOLATILE CONFIGURATION REGISTER 85h WRITE VOLATILE CONFIGURATION REGISTER 81h 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN Yes Yes Yes Yes Yes Yes 1 to ∞ 4 1 4, 8 1 to ∞ 2 0 Yes Yes Yes 2 2 2, 8 Yes 29 Yes Yes 1 to ∞ 2 1 2, 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory Command Definitions Table 16: Command Set (Continued) Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes READ ENHANCED VOLATILE CONFIGURATION REGISTER 65h Yes Yes Yes 1 to ∞ 2 WRITE ENHANCED VOLATILE CONFIGURATION REGISTER 61h Yes Yes Yes 1 2, 8 PAGE PROGRAM 02h Yes Yes Yes 1 to 256 4, 8 DUAL INPUT FAST PROGRAM A2h Yes Yes No 1 to 256 4, 8 EXTENDED DUAL INPUT FAST PROGRAM 02h A2h D2h Yes Yes No QUAD INPUT FAST PROGRAM 32h Yes No Yes EXTENDED QUAD INPUT FAST PROGRAM 02h 32h 12h Yes No Yes SUBSECTOR ERASE 20h Yes Yes Yes SECTOR ERASE D8h 4, 8 BULK ERASE C7h 2, 8 PROGRAM/ERASE RESUME 7Ah PROGRAM/ERASE SUSPEND 75h Command PROGRAM Operations 4, 6, 8 1 to 256 4, 8 4, 7, 8 ERASE Operations 0 4, 8 Yes Yes Yes 0 2, 8 Yes Yes Yes 1 to 64 5 ONE-TIME PROGRAMMABLE (OTP) Operations READ OTP ARRAY 4Bh PROGRAM OTP ARRAY 42h Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 4 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. 2. Address bytes = 0. Dummy clock cycles = 0. 3. Address bytes = 3. Dummy clock cycles default = 8. 4. Address bytes default = 3. Dummy clock cycles = 0. 5. Address bytes default = 3. Dummy clock cycles default = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy clock cycles is configurable by the user. 6. When the device is in dual SPI protocol, the command can be entered with any of these three codes. The different codes enable compatibility between dual SPI and extended SPI protocols. 7. When the device is in quad SPI protocol, the command can be entered with any of these three codes. The different codes enable compatibility between quad SPI and extended SPI protocols. 8. The WRITE ENABLE command must be issued first before this command can be executed. 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations READ REGISTER and WRITE REGISTER Operations READ STATUS REGISTER or FLAG STATUS REGISTER Command To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. The status register can be read continuously and at any time, including during a PROGRAM, ERASE, or WRITE operation. The flag status register can be read continuously and at any time, including during an ERASE or WRITE operation. If one of these operations is in progress, checking the write in progress bit or P/E controller bit is recommended before executing the command. Figure 11: READ REGISTER Command Extended 0 7 9 8 10 11 12 13 14 15 C LSB Command DQ0 MSB LSB DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dual 0 3 4 5 6 7 C LSB LSB DOUT DOUT Command DQ[1:0] MSB DOUT DOUT DOUT MSB Quad 0 1 2 3 C LSB Command DQ[3:0] MSB Notes: DOUT LSB DOUT DOUT Don’t Care MSB 1. Supports all READ REGISTER commands except READ LOCK REGISTER. 2. A READ NONVOLATILE CONFIGURATION REGISTER operation will output data starting from the least significant byte. READ NONVOLATILE CONFIGURATION REGISTER Command To execute a READ NONVOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. The nonvolatile configuration register can be read continuously. After all 16 bits of the register have been read, a 0 is output. All reserved fields output a value of 1. READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command To execute a READ VOLATILE CONFIGURATION REGISTER command or a READ ENHANCED VOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. When the register is read continuously, the same byte is output repeatedly. WRITE STATUS REGISTER Command To issue a WRITE STATUS REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tW. This command is used to write new values to status register bits 7:2, enabling software data protection. The status register can also be combined with the W# signal to provide hardware data protection. The WRITE STATUS REGISTER command has no effect on status register bits 1:0. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0, whether the operation is successful or not. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Figure 12: WRITE REGISTER Command Extended 0 7 8 9 10 11 12 13 15 14 C LSB LSB DIN Command DQ0 MSB DIN DIN DIN DIN DIN DIN DIN DIN MSB Dual 0 3 4 5 6 7 C LSB LSB DIN Command DQ[1:0] MSB DIN DIN DIN DIN MSB Quad 0 1 2 3 C LSB LSB Command DQ[3:0] DIN DIN DIN MSB MSB Notes: 1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER. 2. Waveform must be extended for each protocol, to 23 for extended, 11 for dual, and 5 for quad. 3. A WRITE NONVOLATILE CONFIGURATION REGISTER operation requires data being sent starting from least significant byte. WRITE NONVOLATILE CONFIGURATION REGISTER Command To execute the WRITE NONVOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the 16th bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by two data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tWNVCR. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0, whether the operation is successful or not. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command To execute a WRITE VOLATILE CONFIGURATION REGISTER command or a WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command code is input on 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. If S# is not driven HIGH, the command is not executed, the flag status register error bits are not set and the write enable latch remains set to 1. Reserved bits are not affected by this command. READ LOCK REGISTER Command To execute the READ LOCK REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, followed by three address bytes that point to a location in the sector. For dual SPI protocol, the command code is input on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. Each address bit is latched in during the rising edge of the clock. For extended SPI protocol, data is shifted out on DQ1 at a maximum frequency fC during the falling edge of the clock. For dual SPI protocol, data is shifted out on DQ[1:0], and for quad SPI protocol, data is shifted out on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. When the register is read continuously, the same byte is output repeatedly. Any READ LOCK REGISTER command that is executed while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected with no affect on the cycle in progress. Table 17: Lock Register Note 1 applies to entire table Bit Name 7:2 Settings Description Bit values are 0. Reserved 0 1 Sector lock down 0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared, 1 = Set which means sector lock down and sector write lock bits can be set. When this bit set, neither of the lock register bits can be written to until the next power cycle. 0 Sector write lock 0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared, 1 = Set which means that PROGRAM and ERASE operations in this sector can be executed and sector content modified. When this bit is set, PROGRAM and ERASE operations in this sector will not be executed. Note: 1. Sector lock register bits 1:0 are written to by the WRITE LOCK REGISTER command. The command will not execute unless the sector lock down bit is cleared. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Figure 13: READ LOCK REGISTER Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ[0] MSB A[MAX] DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB Quad A[MAX] 0 1 MSB 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] Note: LSB DOUT DOUT Don’t Care MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2). For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4). WRITE LOCK REGISTER Command To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQn, followed by three address bytes that point to a location in the sector, and then one data byte that contains the desired settings for lock register bits 0 and 1. Each address bit is latched in during the rising edge of the clock. When execution is complete, the write enable latch bit is cleared within tSHSL2 and no error bits are set. Because lock register bits are volatile, change to the bits is immediate. WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in effect. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Figure 14: WRITE LOCK REGISTER Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] Note: DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2). For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4). CLEAR FLAG STATUS REGISTER Command To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits (erase, program, and protection), S# is driven LOW. For extended SPI protocol, the command code is input on DQ0. For dual SPI protocol, the command code is input on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation is terminated by driving S# HIGH at any time. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations READ IDENTIFICATION Operations READ ID and MULTIPLE I/O READ ID Commands To execute the READ ID or MULTIPLE I/O READ ID commands, S# is driven LOW and the command code is input on DQn. The device outputs the information shown in the tables below. If an ERASE or PROGRAM cycle is in progress when the command is executed, the command is not decoded and the command cycle in progress is not affected. When S# is driven HIGH, the device goes to standby. The operation is terminated by driving S# HIGH at any time during data output. Table 18: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands Command Name READ ID MULTIPLE I/O READ ID Note: Data In Data Out Unique ID is Output Extended Dual Quad DQ0 DQ0 Yes Yes No No DQ[3:0] DQ[1:0] No No Yes Yes 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. Table 19: Read ID Data Out Size (Bytes) Name Content Value 1 Manufacturer ID 20h JEDEC 2 Device ID Memory Type BAh Manufacturer Memory Capacity 18h (128Mb) 17 Assigned by Unique ID 1 Byte: Length of data to follow 10h 2 Bytes: Extended device ID and device configuration information ID and information such as uniform architecture, and HOLD or RESET functionality 14 Bytes: Customized factory data Unique ID code (n read-only bytes) Note: Factory 1. The 17 bytes of information in the unique ID is read by the READ ID command, but cannot be read by the MULTIPLE I/O READ ID command. Table 20: Extended Device ID, First Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved 1 = Reserved 0 = Standard BP scheme Volatile configuration register, XIP bit setting: 0 = Required 1 = Not required HOLD#/RESET#: 0 = HOLD 1 = RESET Addressing: 0 = by byte 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 37 Bit 1 Bit 0 Architecture: 00 = Uniform Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Figure 15: READ ID and MULTIPLE I/O Read ID Commands Extended (READ ID) 0 7 16 15 8 31 32 C LSB DQ0 Command MSB LSB DOUT DOUT High-Z DQ1 MSB DOUT MSB Manufacturer identification Dual (MULTIPLE I/O READ ID ) 0 LSB DOUT 3 MSB UID Device identification 8 7 4 LSB DOUT DOUT 15 C LSB DQ[1:0] LSB DOUT DOUT Command MSB MSB DOUT MSB Manufacturer identification Quad (MULTIPLE I/O READ ID ) 0 LSB DOUT 1 Device identification 4 3 2 7 C LSB DQ[3:0] Command MSB DOUT LSB DOUT MSB LSB DOUT MSB Manufacturer identification Note: DOUT Device identification Don’t Care 1. The READ ID command is represented by the extended SPI protocol timing shown first. The MULTIPLE I/O READ ID command is represented by the dual and quad SPI protocols are shown below extended SPI protocol. READ SERIAL FLASH DISCOVERY PARAMETER Command To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven LOW. The command code is input on DQ0, followed by three address bytes and 8 dummy clock cycles in extended or dual SPI protocol, 10 dummy clock cycles in quad SPI protocol. The device outputs the information starting from the specified address. When the 2048-byte boundary is reached, the data output wraps to address 0 of the serial Flash discovery parameter table. The operation is terminated by driving S# HIGH at any time during data output. The operation always executes in continuous mode so the read burst wrap setting in the volatile configuration register does not apply. Note: Data to be stored in the serial Flash discovery parameter area is still in the definition phase. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 38 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 21: Serial Flash Discovery Parameter – Header Structure Description Byte Address Bits Data 128Mb 00h 7:0 53h 01h 7:0 46h 02h 7:0 44h SFDP signature 03h 7:0 50h Minor 04h 7:0 00h Major 05h 7:0 01h Number of parameter headers 06h 7:0 00h Unused 07h 7:0 FFh Parameter ID (0) 08h 7:0 00h Parameter minor revision 09h 7:0 00h Parameter major revision 0Ah 7:0 01h Parameter length (in DW) 0Bh 7:0 09h Parameter table pointer 0Ch 7:0 30h 0Dh 7:0 00h 0Eh 7:0 00h 0Fh 7:0 FFh SFDP revision Unused Note: 1. Locations 10h to 2Fh contain FFh. Table 22: Parameter ID Description Minimum block/sector erase sizes Byte Address Bits Data 128Mb 30h 1:0 01b Write granularity 2 1 WRITE ENABLE command required for writing to volatile status registers 3 0 WRITE ENABLE command code select for writing to volatile status register 4 0 Unused 7:5 111b 4KB ERASE command code 31h 7:0 20h Supports 1-1-2 fast read 32h 0 1 2:1 00b Supports double transfer rate clocking 3 0 Supports 1-2-2 fast read 4 1 Supports 1-4-4 fast read 5 1 Supports 1-1-4 fast read 6 1 Address bytes Unused Reserved 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 33h 39 7 1 7:0 FFh Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 22: Parameter ID (Continued) Description Flash size (in bits) 1-4-4 FAST READ DUMMY cycle count Byte Address Bits Data 128Mb 34h 7:0 FFh 35h 7:0 FFh 36h 7:0 FFh 37h 7:0 07h 38h 4:0 01001b 7:5 001b 1-4-4 fast read number of mode bits 1-4-4 FAST READ command code 39h 7:0 EBh 1-1-4 FAST READ DUMMY cycle count 3Ah 4:0 00111b 7:5 001b 1-1-4 fast read number of mode bits 1-1-4 FAST READ command code 3Bh 7:0 6Bh 1-1-2 FAST READ DUMMY cycle count 3Ch 4:0 01000b 1-1-2 fast read number of mode bits 7:5 000b 1-1-2 FAST READ command code 3Dh 7:0 3Bh 1-2-2 FAST READ DUMMY cycle count 3Eh 4:0 00111b 7:5 001b 1-2-2 fast read number of mode bits 1-2-2 Instruction opcode 3Fh 7:0 BBh Supports 2-2-2 fast read 40h 0 1 3:1 111b 4 1 Reserved Supports 4-4-4 fast read Reserved 7:5 111b Reserved 43:41h FFFFFFh FFFFFFh Reserved 45:44h FFFFh FFFFh 46h 4:0 00111b 2-2-2 FAST READ DUMMY cycle count 2-2-2 fast read number of mode bits 2-2-2 FAST READ command code Reserved 4-4-4 FAST READ DUMMY cycle count 7:5 001b 47h 7:0 BBh 49:48h FFFFh FFFFh 4Ah 4:0 01001b 4-4-4 fast read number of mode bits 7:5 001b 4-4-4 FAST READ command code 4Bh 7:0 EBh Sector type 1 size 4Ch 7:0 0Ch Sector type 1 command code 4Dh 7:0 20h Sector type 2 size 4Eh 7:0 10h Sector type 2 command code 4Fh 7:0 D8h Sector type 3 size 50h 7:0 00h Sector type 3 command code 51h 7:0 00h Sector type 4 size 52h 7:0 00h Sector type 4 command code 53h 7:0 00h 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ MEMORY Operations READ MEMORY Operations The device supports default reading and writing to an A[MAX:MIN] of A[23:0]. To execute READ MEMORY commands, S# is driven LOW. The command code is input on DQn, followed by input on DQn of three address bytes. Each address bit is latched in during the rising edge of the clock. The addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, the entire memory can be read with a single command. The operation is terminated by driving S# HIGH at any time during data output. Table 23: Command/Address/Data Lines for READ MEMORY Commands Note 1 applies to entire table Command Name DUAL QUAD DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT FAST READ FAST READ FAST READ FAST READ READ FAST READ 03 0B 3B BB 6B EB Supported Yes Yes Yes Yes Yes Yes Command Input DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 Address Input DQ0 DQ0 DQ0 DQ[1:0] DQ0 DQ[3:0] Data Output DQ1 DQ1 DQ[1:0] DQ[1:0] DQ[3:0] DQ[3:0] Extended SPI Protocol Dual SPI Protocol Supported No Yes Yes Yes No No Command Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Address Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Data Output – DQ[1:0] DQ[1:0] DQ[1:0] – – No Yes No No Yes Yes Command Input – DQ[3:0] – – DQ[3:0] DQ[3:0] Address Input – DQ[3:0] – – DQ[3:0] DQ[3:0] Data Output – DQ[3:0] – – DQ[3:0] DQ[3:0] Quad SPI Protocol Supported Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Yes in the "Supported" row for each protocol indicates that the command in that column is supported; when supported, a command's functionality is identical for the entire column regardless of the protocol. For example, a FAST READ functions the same for all three protocols even though its data is input/output differently depending on the protocol. 2. FAST READ is similar to READ, but requires dummy clock cycles following the address bytes and can operate at a higher frequency (fC). 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 16: READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ[0] MSB A[MAX] DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1). Figure 17: FAST READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] MSB Don’t Care Dummy cycles Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN LSB DOUT DOUT 1. For extended protocol, Cx = 7 + (A[MAX] + 1); For dual protocol, Cx = 3 + (A[MAX] + 1)/2; For quad protocol, Cx = 1 + (A[MAX] + 1)/4. 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 18: DUAL OUTPUT FAST READ Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT A[MAX] High-Z DQ1 DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT MSB Dummy cycles Note: 1. Cx = 7 + (A[MAX] + 1). Figure 19: DUAL INPUT/OUTPUT FAST READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB High-Z DQ1 A[MAX] DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT MSB Dummy cycles Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Cx = 7 + (A[MAX] + 1)/2. 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 20: QUAD OUTPUT FAST READ Command Extended 0 7 8 Cx C LSB A[MIN] DOUT LSB DOUT DOUT High-Z DOUT DOUT DOUT ‘1’ DOUT DOUT DOUT Command DQ0 MSB DQ[2:1] A[MAX] DQ3 MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Dummy cycles Note: 1. Cx = 7 + (A[MAX] + 1). Figure 21: QUAD INPUT/OUTPUT FAST READ Command Extended 0 7 8 Cx C LSB DQ0 Command DOUT LSB DOUT DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT A[MIN] MSB DQ[2:1] ‘1’ DQ3 A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Dummy cycles Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Cx = 7 + (A[MAX] + 1)/4. 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory PROGRAM Operations PROGRAM Operations PROGRAM commands are initiated by first executing the WRITE ENABLE command to set the write enable latch bit to 1. S# is then driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by input on DQ[n] of address bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tPP. If the bits of the least significant address, which is the starting address, are not all zero, all data transmitted beyond the end of the current page is programmed from the starting address of the same page. If the number of bytes sent to the device exceed the maximum page size, previously latched data is discarded and only the last maximum pagesize number of data bytes are guaranteed to be programmed correctly within the same page. If the number of bytes sent to the device is less than the maximum page size, they are correctly programmed at the specified addresses without any effect on the other bytes of the same page. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. An operation can be paused or resumed by the PROGRAM/ERASE SUSPEND or PROGRAM/ERASE RESUME command, respectively. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected sector, the command is not executed, the write enable latch bit remains set to 1, and flag status register bits 1 and 4 are set. Table 24: Data/Address Lines for PROGRAM Commands Note 1 applies to entire table Command Name PAGE PROGRAM Data In Address In Extended Dual Quad DQ0 DQ0 Yes Yes Yes DUAL INPUT FAST PROGRAM DQ[1:0] DQ0 Yes Yes No EXTENDED DUAL INPUT FAST PROGRAM DQ[1:0] DQ[1:0] Yes Yes No QUAD INPUT FAST PROGRAM DQ[3:0] DQ0 Yes No Yes EXTENDED QUAD INPUT FAST PROGRAM DQ[3:0] DQ[3:0] Yes No Yes Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory PROGRAM Operations Figure 22: PAGE PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). Note: For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. Figure 23: DUAL INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB MSB DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN A[MAX] High-Z DQ1 LSB A[MIN] Command DQ0 MSB Dual 0 3 4 Cx C LSB A[MIN] LSB DIN Command DQ[1:0] MSB Note: A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory PROGRAM Operations Figure 24: EXTENDED DUAL INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB High-Z DQ1 A[MAX] Dual 0 3 MSB 4 Cx C A[MIN] LSB LSB Command DQ[1:0] MSB Note: A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/2. For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. Figure 25: QUAD INPUT FAST PROGRAM Command Extended 0 7 8 Cx C A[MIN] LSB DQ0 DIN DIN DIN DIN DIN DIN DIN DIN A[MAX] MSB DQ[3:1] LSB Command High-Z MSB Quad 0 1 2 Cx C LSB MSB Note: A[MIN] LSB Command DQ[3:0] A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/4. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory PROGRAM Operations Figure 26: EXTENDED QUAD INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] LSB DIN DIN DIN High-Z DIN DIN DIN ‘1’ DIN DIN DIN DIN DIN Command MSB DQ[2:1] DQ3 A[MAX] Quad 0 1 MSB 2 Cx C LSB MSB Note: A[MIN] LSB Command DQ[3:0] A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/4. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory WRITE Operations WRITE Operations WRITE ENABLE Command The WRITE ENABLE operation sets the write enable latch bit. To execute a WRITE ENABLE command, S# is driven LOW and held LOW until the eighth bit of the command code has been latched in, after which it must be driven HIGH. The command code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on DQ[3:0] for quad SPI protocol. The write enable latch bit must be set before every PROGRAM, ERASE, and WRITE command. If S# is not driven HIGH after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch remains cleared to its default setting of 0. WRITE DISABLE Command The WRITE DISABLE operation clears the write enable latch bit. To execute a WRITE DISABLE command, S# is driven LOW and held LOW until the eighth bit of the command code has been latched in, after which it must be driven HIGH. The command code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on DQ[3:0] for quad SPI protocol. If S# is not driven HIGH after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory WRITE Operations Figure 27: WRITE ENABLE and WRITE DISABLE Command Sequence Extended 0 1 2 3 4 5 6 7 C S# Command Bits DQ0 0 0 0 0 0 LSB 1 1 0 MSB High-Z DQ1 Dual 0 1 2 3 C S# Command Bits DQ0 DQ1 LSB 0 0 1 0 0 0 0 1 MSB Quad 0 1 C S# Command Bits LSB DQ0 0 0 DQ1 0 1 DQ2 0 1 DQ3 0 0 Don’t Care MSB Note: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. Shown here is the WRITE ENABLE command code, which is 06h or 0000 0110 binary. The WRITE DISABLE command sequence is identical, except the WRITE DISABLE command code is 04h or 0000 0100 binary. 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ERASE Operations ERASE Operations SUBSECTOR ERASE Command To execute the SUBSECTOR ERASE command (and set the selected subsector bits set to FFh), the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by three address bytes; any address within the subsector is valid. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tSSE. The operation can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respectively. If the write enable latch bit is not set, the device ignores the SUBSECTOR ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected subsector, the command is not executed. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. SECTOR ERASE Command To execute the SECTOR ERASE command (and set selected sector bits to FFh), the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by three address bytes; any address within the sector is valid. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tSE. The operation can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respectively. If the write enable latch bit is not set, the device ignores the SECTOR ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1 and the write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected sector, the command is not executed. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ERASE Operations Figure 28: SUBSECTOR and SECTOR ERASE Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] Command MSB Dual A[MAX] 0 3 4 Cx C LSB DQ0[1:0] A[MIN] Command MSB Quad A[MAX] 0 1 2 Cx C LSB MSB Note: A[MIN] Command DQ0[3:0] A[MAX] 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. BULK ERASE Command To initiate the BULK ERASE command, the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0. When S# is driven HIGH, the operation, which is selftimed, is initiated; its duration is tBE. If the write enable latch bit is not set, the device ignores the BULK ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1 and the write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, the flag status register error bits are not set, and the write enable latch remains set to 1. The command is not executed if any sector is locked. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ERASE Operations Figure 29: BULK ERASE Command Extended 0 7 C LSB Command DQ0 MSB Dual 0 3 C LSB Command DQ[1:0] MSB Quad 0 1 C LSB Command DQ[3:0] MSB PROGRAM/ERASE SUSPEND Command To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The command code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RESUME command. PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt and suspend an array PROGRAM or ERASE operation within the program/erase latency. If a SUSPEND command is issued during a PROGRAM operation, then the flag status register bit 2 is set to 1. After erase/program latency time, the flag status register bit 7 is also set to 1, showing the device to be in a suspended state, waiting for any operation (see the Operations Allowed/Disallowed During Device States table). If a SUSPEND command is issued during an ERASE operation, then the flag status register bit 6 is set to 1. After erase/program latency time, the flag status register bit 7 is also set to 1, showing that device to be in a suspended state, waiting for any operation (see the Operations Allowed/Disallowed During Device States table). If the time remaining to complete the operation is less than the suspend latency, the device completes the operation and clears the flag status register bits 2 or 6, as applicable. Because the suspend state is volatile, if there is a power cycle, the suspend state information is lost and the flag status register powers up as 80h. During an ERASE SUSPEND operation, a PROGRAM or READ operation is possible in any sector except the one in a suspended state. Reading from a sector that is in a suspended state will output indeterminate data. The device ignores a PROGRAM command to a sector that is in an ERASE SUSPEND state; it also sets the flag status register bit 4 to 1: program failure/protection error, and leaves the write enable latch bit unchanged. The commands allowed during an erase suspend state include the WRITE LOCK REGISTER command, the WRITE VOLATILE CONFIGURATION REGISTER com- 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ERASE Operations mand, and the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. When the ERASE operation resumes, it does not check the new lock status of the WRITE LOCK REGISTER command. During a PROGRAM SUSPEND operation, a READ operation is possible in any page except the one in a suspended state. Reading from a page that is in a suspended state will output indeterminate data. The commands allowed during a program suspend state include the WRITE VOLATILE CONFIGURATION REGISTER command and the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. It is possible to nest a PROGRAM/ERASE SUSPEND operation inside a PROGRAM/ ERASE SUSPEND operation just once. Issue an ERASE command and suspend it. Then issue a PROGRAM command and suspend it also. With the two operations suspended, the next PROGRAM/ERASE RESUME command resumes the latter operation, and a second PROGRAM/ERASE RESUME command resumes the former (or first) operation. Table 25: Suspend Parameters Parameter Condition Typ Max Units Notes Erase to suspend Sector erase or erase resume to erase suspend 150 – µs 1 Program to suspend Program resume to program suspend 5 – µs 1 Subsector erase to suspend Subsector erase or subsector erase resume to erase suspend 50 – µs 1 Suspend latency Program 7 – µs 2 Suspend latency Subsector erase 15 – µs 2 Suspend latency Erase 15 – µs 3 Notes: 1. Timing is not internally controlled. 2. Any READ command accepted. 3. Any command except the following are accepted: SECTOR, SUBSECTOR, or BULK ERASE; WRITE STATUS REGISTER; WRITE NONVOLATILE CONFIGURATION REGISTER; and PROGRAM OTP. Table 26: Operations Allowed/Disallowed During Device States Note 1 applies to entire table Standby Operation State Program or Erase State Subsector Erase Suspend or Program Suspend State Erase Suspend State Notes READ Yes No Yes Yes 2 PROGRAM Yes No No Yes/No 3 ERASE Yes No No No 4 WRITE Yes No No No 5 WRITE Yes No Yes Yes 6 READ Yes Yes Yes Yes 7 SUSPEND No Yes No No 8 Notes: 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 1. The device can be in only one state at a time. Depending on the state of the device, some operations are allowed (Yes) and others are not (No). For example, when the device is in the standby state, all operations except SUSPEND are allowed in any sector. For all device states except the erase suspend state, if an operation is allowed or disallowed 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ERASE Operations 2. 3. 4. 5. 6. 7. 8. in one sector, it is allowed or disallowed in all other sectors. In the erase suspend state, a PROGRAM operation is allowed in any sector except the one in which an ERASE operation has been suspended. All READ operations except READ STATUS REGISTER and READ FLAG REGISTER. When issued to a sector or subsector that is simultaneously in an erase suspend state, the READ operation is accepted, but the data output is not guaranteed until the erase has completed. All PROGRAM operations except PROGRAM OTP. In the erase suspend state, a PROGRAM operation is allowed in any sector (Yes) except the sector (No) in which an ERASE operation has been suspended. Applies to the SECTOR ERASE or SUBSECTOR ERASE operation. Applies to the following operations: WRITE STATUS REGISTER, WRITE NONVOLATILE CONFIGURATION REGISTER, PROGRAM OTP, and BULK ERASE. Applies to the following operations: WRITE ENABLE, WRITE DISABLE, CLEAR FLAG STATUS REGISTER, WRITE LOCK REGISTER, WRITE VOLATILE, and ENHANCED VOLATILE CONFIGURATION REGISTER. Applies to the READ STATUS REGISTER or READ FLAG STATUS REGISTER operation. Applies to the PROGRAM SUSPEND or ERASE SUSPEND operation. PROGRAM/ERASE RESUME Command To initiate the PROGRAM/ERASE RESUME command, S# is driven LOW. The command code is input on DQ0. The operation is terminated by driving S# HIGH. When this command is executed, the status register write in progress bit is set to 1, and the flag status register program erase controller bit is set to 0. This command is ignored if the device is not in a suspended state. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations ONE TIME PROGRAMMABLE Operations READ OTP ARRAY Command To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is input on DQ0, followed by three bytes and dummy clock cycles. Each address bit is latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the specified address and at a maximum frequency of fC (MAX) on the falling edge of the clock. The address increments automatically to the next address after each byte of data is shifted out. There is no rollover mechanism; therefore, if read continuously, after location 40h, the device continues to output data at location 40h. The operation is terminated by driving S# HIGH at any time during data output. Figure 30: READ OTP Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Don’t Care Dummy cycles Note: 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. PROGRAM OTP ARRAY Command To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY command is ignored and flag status register bits are not set. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by three bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tPOTP. There is no rollover mechanism; therefore, after a maximum of 65 bytes are latched in and subsequent bytes are discarded. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one OTP control byte. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not, and the status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. The OTP control byte (byte 64) is used to permanently lock the OTP memory array. Table 27: OTP Control Byte (Byte 64) Bit Name 0 OTP control byte Settings Description 0 = Locked 1 = Unlocked (Default) Used to permanently lock the OTP array (byte 64). When bit 0 = 1, the OTP array can be programmed. When bit 0 = 0, the OTP array is read only. Once bit 0 has been programmed to 0, it can no longer be changed to 1. PROGRAM OTP ARRAY is ignored, write enable latch bit remains set, and flag status register bits 1 and 4 are set. Figure 31: PROGRAM OTP Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] Note: DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef845665fe n25q_128mb_3v_65nm.pdf - Rev. T 02/18 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb, 3V, Multiple I/O Serial Flash Memory XIP Mode XIP Mode Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode offers maximum flexibility to the application, saves instruction overhead, and reduces random access time. Activate or Terminate XIP Using Volatile Configuration Register Applications that boot in SPI and must switch to XIP use the volatile configuration register. XIP provides faster memory READ operations by requiring only an address to execute, rather than a command code and an address. To activate XIP requires two steps. First, enable XIP by setting volatile configuration register bit 3 to 0. Next, drive the XIP confirmation bit to 0 during the next FAST READ operation. XIP is then active. Once in XIP, any command that occurs after S# is toggled requires only address bits to execute; a command code is not necessary, and device operations use the SPI protocol that is enabled. XIP is terminated by driving the XIP confirmation bit to 1. The device automatically resets volatile configuration register bit 3 to 1. Note: For devices with basic XIP, indicated by a part number feature set digit of 2 or 4, it is not necessary to set the volatile configuration register bit 3 to 0 to enable XIP. Instead, it is enabled by setting the XIP confirmation bit to 0 during the first dummy clock cycle after any FAST READ command. Activate or Terminate XIP Using Nonvolatile Configuration Register Applications that must boot directly in XIP use the nonvolatile configuration register. To enable a device to power-up in XIP using the nonvolatile configuration register, set nonvolatile configuration register bits [11:9]. Settings vary according to protocol, as explained in the Nonvolatile Configuration Register section. Because the device boots directly in XIP, the confirmation bit is already set to 0, and after the next power cycle, XIP is active. Once in XIP, a command code is unnecessary, and device operations use the SPI protocol currently enabled. XIP is terminated by driving the XIP confirmation bit to 1. Figure 32: XIP Mode Directly After Power-On Mode 3 C tVSI VCC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mode 0 (