N25Q256A33EF840F

1.8V, 256Mb: Multiple I/O Serial Flash Memory Features Micron Serial NOR Flash Memory 1.8V, Multiple I/O, 4KB Sector Erase N25Q256A Features • • • • • • • • • • • • • • • • Write protection – Software write protection applicable to every 64KB sector via volatile lock bit – Hardware write protection: protected area size defined by five nonvolatile bits (BP0, BP1, BP2, BP3, and TB) – Additional smart protections, available upon request • Electronic signature – JEDEC-standard 2-byte signature (BB19h) – Unique ID of 17 read-only bytes including: additional extended device ID (EDID) to identify device factory options; customized factory data • Minimum 100,000 ERASE cycles per sector • More than 20 years data retention • Packages JEDEC standard, all RoHS compliant – V-PDFN-8/8mm x 6mm (also known as SON, DFPN, MLP, MLF) – SOP2-16/300 mil (also known as SO16W, SO16Wide, SOIC-16) – T-PBGA-24b05/6mm x 8mm (also known as TBGA24) SPI-compatible serial bus interface Double transfer rate (DTR) mode 1.7–2.0V single supply voltage 108 MHz (MAX) clock frequency supported for all protocols in single transfer rate (STR) mode 54 MHz (MAX) clock frequency supported for all protocols in DTR mode Dual/quad I/O instruction provides increased throughput up to 54 MB/s Supported protocols – Extended SPI, dual I/O, and quad I/O – DTR mode supported on all Execute-in-place (XIP) mode for all three protocols – Configurable via volatile or nonvolatile registers – Enables memory to work in XIP mode directly after power-on PROGRAM/ERASE SUSPEND operations Continuous read of entire memory via a single command – Fast read – Quad or dual output fast read – Quad or dual I/O fast read Flexible to fit application – Configurable number of dummy cycles – Output buffer configurable Software reset – Additional RESET# pin for selected part numbers 3-byte and 4-byte addressability mode supported 64-byte, user-lockable, one-time programmable (OTP) dedicated area Erase capability – Subsector erase 4KB uniform granularity blocks – Sector erase 64KB uniform granularity blocks – Full-chip erase 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Features Contents Device Description ........................................................................................................................................... 6 Features ....................................................................................................................................................... 6 3-Byte Address and 4-Byte Address Modes ..................................................................................................... 6 Operating Protocols ...................................................................................................................................... 6 XIP Mode ..................................................................................................................................................... 6 Device Configurability .................................................................................................................................. 7 Signal Assignments ........................................................................................................................................... 8 Signal Descriptions ......................................................................................................................................... 10 Memory Organization .................................................................................................................................... 12 Memory Configuration and Block Diagram .................................................................................................. 12 Memory Map – 256Mb Density ....................................................................................................................... 13 Device Protection ........................................................................................................................................... 14 Block Protection Areas ................................................................................................................................ 15 Serial Peripheral Interface Modes .................................................................................................................... 17 SPI Protocols .................................................................................................................................................. 19 Nonvolatile and Volatile Registers ................................................................................................................... 20 Status Register ............................................................................................................................................ 21 Nonvolatile and Volatile Configuration Registers .......................................................................................... 21 Extended Address Register .......................................................................................................................... 25 Enhanced Volatile Configuration Register .................................................................................................... 26 Flag Status Register ..................................................................................................................................... 27 Command Definitions .................................................................................................................................... 28 READ REGISTER and WRITE REGISTER Operations ........................................................................................ 32 READ STATUS REGISTER or FLAG STATUS REGISTER Command ................................................................ 32 READ NONVOLATILE CONFIGURATION REGISTER Command ................................................................... 32 READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command .................................. 33 READ EXTENDED ADDRESS REGISTER Command ..................................................................................... 33 WRITE STATUS REGISTER Command ......................................................................................................... 33 WRITE NONVOLATILE CONFIGURATION REGISTER Command ................................................................. 34 WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command ................................. 34 WRITE EXTENDED ADDRESS REGISTER Command ................................................................................... 35 READ LOCK REGISTER Command .............................................................................................................. 35 WRITE LOCK REGISTER Command ............................................................................................................ 36 CLEAR FLAG STATUS REGISTER Command ................................................................................................ 37 READ IDENTIFICATION Operations ............................................................................................................... 38 READ ID and MULTIPLE I/O READ ID Commands ...................................................................................... 38 READ SERIAL FLASH DISCOVERY PARAMETER Command ......................................................................... 39 READ MEMORY Operations ............................................................................................................................ 43 3-Byte Address ........................................................................................................................................... 43 4-Byte Address ........................................................................................................................................... 45 READ MEMORY Operations Timing – Single Transfer Rate ........................................................................... 46 READ MEMORY Operations Timing – Double Transfer Rate ......................................................................... 50 PROGRAM Operations .................................................................................................................................... 53 WRITE Operations .......................................................................................................................................... 57 WRITE ENABLE Command ......................................................................................................................... 57 WRITE DISABLE Command ........................................................................................................................ 57 ERASE Operations .......................................................................................................................................... 59 SUBSECTOR ERASE Command ................................................................................................................... 59 SECTOR ERASE Command ......................................................................................................................... 59 BULK ERASE Command ............................................................................................................................. 60 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Features PROGRAM/ERASE SUSPEND Command ..................................................................................................... PROGRAM/ERASE RESUME Command ...................................................................................................... RESET Operations .......................................................................................................................................... RESET ENABLE and RESET MEMORY Command ........................................................................................ RESET Conditions ...................................................................................................................................... ONE TIME PROGRAMMABLE Operations ....................................................................................................... READ OTP ARRAY Command ...................................................................................................................... PROGRAM OTP ARRAY Command .............................................................................................................. ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ................................................................. ENTER or EXIT 4-BYTE ADDRESS MODE Command ................................................................................... ENTER or EXIT QUAD Command ................................................................................................................ XIP Mode ....................................................................................................................................................... Activate or Terminate XIP Using Volatile Configuration Register ................................................................... Activate or Terminate XIP Using Nonvolatile Configuration Register ............................................................. Confirmation Bit Settings Required to Activate or Terminate XIP .................................................................. Terminating XIP After a Controller and Memory Reset ................................................................................. Power Up and Power Down ............................................................................................................................. Power Up and Power Down Requirements ................................................................................................... Power Loss Recovery Sequence ................................................................................................................... Initial Delivery Status ..................................................................................................................................... AC Reset Specifications ................................................................................................................................... Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics and Operating Conditions .................................................................................................. AC Characteristics and Operating Conditions .................................................................................................. Package Dimensions ....................................................................................................................................... Part Number Ordering Information ................................................................................................................. Revision History ............................................................................................................................................. Rev. O – 11/16 ............................................................................................................................................. Rev. N – 05/16 ............................................................................................................................................. Rev. M – 03/14 ............................................................................................................................................ Rev. L – 01/14 ............................................................................................................................................. Rev. K – 09/13 ............................................................................................................................................. Rev. J – 01/13 .............................................................................................................................................. Rev. I – 07/12 .............................................................................................................................................. Rev. H – 06/12 ............................................................................................................................................. Rev. G, Production – 02/12 .......................................................................................................................... Rev. F, Production – 02/12 ........................................................................................................................... Rev. E, Production – 01/12 ........................................................................................................................... Rev. D, Production – 09/11 .......................................................................................................................... Rev. C – 11/10 ............................................................................................................................................. Rev. B – 08/10 ............................................................................................................................................. Rev. A – 06/10 ............................................................................................................................................. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 3 61 63 64 64 64 65 65 65 68 68 68 69 69 69 70 71 72 72 73 73 74 78 80 81 83 86 88 88 88 88 88 88 88 88 88 89 89 89 89 89 89 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Features List of Figures Figure 1: Logic Diagram ................................................................................................................................... 7 Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) .................................................................................................. 8 Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) ............................................................................... 8 Figure 4: 24-Ball TBGA (Balls Down) ................................................................................................................ 9 Figure 5: Block Diagram ................................................................................................................................ 12 Figure 6: Bus Master and Memory Devices on the SPI Bus ............................................................................... 18 Figure 7: SPI Modes ....................................................................................................................................... 18 Figure 8: Internal Configuration Register ........................................................................................................ 20 Figure 9: Upper and Lower 128Mb Memory Array Segments ........................................................................... 25 Figure 10: READ REGISTER Command .......................................................................................................... 32 Figure 11: WRITE REGISTER Command ......................................................................................................... 34 Figure 12: READ LOCK REGISTER Command ................................................................................................. 36 Figure 13: WRITE LOCK REGISTER Command ............................................................................................... 37 Figure 14: READ ID and MULTIPLE I/O Read ID Commands .......................................................................... 39 Figure 15: READ Command ........................................................................................................................... 46 Figure 16: FAST READ Command ................................................................................................................... 46 Figure 17: DUAL OUTPUT FAST READ Command – STR ................................................................................. 47 Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR ..................................................................... 47 Figure 19: QUAD OUTPUT FAST READ Command – STR ................................................................................ 48 Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR .................................................................... 48 Figure 21: FAST READ Command – DTR ......................................................................................................... 50 Figure 22: DUAL OUTPUT FAST READ Command – DTR ................................................................................ 51 Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR .................................................................... 51 Figure 24: QUAD OUTPUT FAST READ Command – DTR ............................................................................... 52 Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR ................................................................... 52 Figure 26: PAGE PROGRAM Command .......................................................................................................... 54 Figure 27: DUAL INPUT FAST PROGRAM Command ...................................................................................... 54 Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command ................................................................... 55 Figure 29: QUAD INPUT FAST PROGRAM Command ..................................................................................... 55 Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command ................................................................... 56 Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence ............................................................ 58 Figure 32: SUBSECTOR and SECTOR ERASE Command .................................................................................. 60 Figure 33: BULK ERASE Command ................................................................................................................ 61 Figure 34: RESET ENABLE and RESET MEMORY Command ........................................................................... 64 Figure 35: READ OTP Command .................................................................................................................... 65 Figure 36: PROGRAM OTP Command ............................................................................................................ 67 Figure 37: XIP Mode Directly After Power-On .................................................................................................. 70 Figure 38: Power-Up Timing .......................................................................................................................... 72 Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle ........................................................................ 75 Figure 40: Reset Enable ................................................................................................................................. 75 Figure 41: Serial Input Timing ........................................................................................................................ 75 Figure 42: Write Protect Setup and Hold During WRITE STATUS REGISTER Operation (SRWD = 1) ................... 76 Figure 43: Hold Timing .................................................................................................................................. 76 Figure 44: Output Timing .............................................................................................................................. 77 Figure 45: V PPH Timing .................................................................................................................................. 77 Figure 46: AC Timing Input/Output Reference Levels ...................................................................................... 79 Figure 47: V-PDFN-8/8mm x 6mm ................................................................................................................. 83 Figure 48: SOP2-16/300 mils .......................................................................................................................... 84 Figure 49: T-PBGA-24b05/6mm x 8mm .......................................................................................................... 85 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Features List of Tables Table 1: Signal Descriptions ........................................................................................................................... Table 2: Sectors[511:0] ................................................................................................................................... Table 3: Data Protection using Device Protocols ............................................................................................. Table 4: Memory Sector Protection Truth Table .............................................................................................. Table 5: Protected Area Sizes – Upper Area ..................................................................................................... Table 6: Protected Area Sizes – Lower Area ...................................................................................................... Table 7: SPI Modes ........................................................................................................................................ Table 8: Extended, Dual, and Quad SPI Protocols ............................................................................................ Table 9: Status Register Bit Definitions ........................................................................................................... Table 10: Nonvolatile Configuration Register Bit Definitions ........................................................................... Table 11: Volatile Configuration Register Bit Definitions .................................................................................. Table 12: Sequence of Bytes During Wrap ....................................................................................................... Table 13: Supported Clock Frequencies – STR ................................................................................................. Table 14: Supported Clock Frequencies – DTR ................................................................................................ Table 15: Extended Address Register Bit Definitions ........................................................................................ Table 16: Enhanced Volatile Configuration Register Bit Definitions .................................................................. Table 17: Flag Status Register Bit Definitions .................................................................................................. Table 18: Command Set ................................................................................................................................. Table 19: Lock Register .................................................................................................................................. Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands ....................................... Table 21: Read ID Data Out ............................................................................................................................ Table 22: Extended Device ID, First Byte ......................................................................................................... Table 23: Serial Flash Discovery Parameter Data Structure .............................................................................. Table 24: Parameter ID .................................................................................................................................. Table 25: Command/Address/Data Lines for READ MEMORY Commands ....................................................... Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address ............................. Table 27: Data/Address Lines for PROGRAM Commands ................................................................................ Table 28: Suspend Parameters ....................................................................................................................... Table 29: Operations Allowed/Disallowed During Device States ...................................................................... Table 30: Reset Command Set ........................................................................................................................ Table 31: OTP Control Byte (Byte 64) .............................................................................................................. Table 32: XIP Confirmation Bit ....................................................................................................................... Table 33: Effects of Running XIP in Different Protocols .................................................................................... Table 34: Power-Up Timing and V WI Threshold ............................................................................................... Table 35: AC RESET Conditions ...................................................................................................................... Table 36: Absolute Ratings ............................................................................................................................. Table 37: Operating Conditions ...................................................................................................................... Table 38: Input/Output Capacitance .............................................................................................................. Table 39: AC Timing Input/Output Conditions ............................................................................................... Table 40: DC Current Characteristics and Operating Conditions ...................................................................... Table 41: DC Voltage Characteristics and Operating Conditions ...................................................................... Table 42: AC Characteristics and Operating Conditions ................................................................................... Table 43: Part Number Information ................................................................................................................ Table 44: Package Details ............................................................................................................................... 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 5 10 13 14 14 15 15 17 19 21 22 23 24 24 24 25 26 27 28 35 38 38 38 40 41 43 45 53 62 63 64 66 70 70 73 74 78 78 78 79 80 80 81 86 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Device Description Device Description The N25Q is the first high-performance multiple input/output serial Flash memory device manufactured on 65nm NOR technology. It features execute-in-place (XIP) functionality, advanced write protection mechanisms, and a high-speed SPI-compatible bus interface. The innovative, high-performance, dual and quad input/output instructions enable double or quadruple the transfer bandwidth for READ and PROGRAM operations. Features The memory is organized as 512 (64KB) main sectors that are further divided into 16 subsectors each (8192 subsectors in total). The memory can be erased one 4KB subsector at a time, 64KB sectors at a time, or as a whole. The memory can be write protected by software through volatile and nonvolatile protection features, depending on the application needs. The protection granularity is of 64KB (sector granularity) for volatile protections The device has 64 one-time programmable (OTP) bytes that can be read and programmed with the READ OTP and PROGRAM OTP commands. These 64 bytes can also be permanently locked with a PROGRAM OTP command. The device also has the ability to pause and resume PROGRAM and ERASE cycles by using dedicated PROGRAM/ERASE SUSPEND and RESUME instructions. 3-Byte Address and 4-Byte Address Modes The device features 3-byte or 4-byte address modes to access memory beyond 128Mb. When 4-byte address mode is enabled, all commands requiring an address must be entered and exited with a 4-byte address mode command: ENTER 4-BYTE ADDRESS MODE command and EXIT 4-BYTE ADDRESS MODE command. The 4-byte address mode can also be enabled through the nonvolatile configuration register. See Registers for more information. Operating Protocols The memory can be operated with three different protocols: • Extended SPI (standard SPI protocol upgraded with dual and quad operations) • Dual I/O SPI • Quad I/O SPI The standard SPI protocol is extended and enhanced by dual and quad operations. In addition, the dual SPI and quad SPI protocols improve the data access time and throughput of a single I/O device by transmitting commands, addresses, and data across two or four data lines. Each protocol contains unique commands to perform READ operations in DTR mode. This enables high data throughput while running at lower clock frequencies. XIP Mode XIP mode requires only an address (no instruction) to output data, improving random access time and eliminating the need to shadow code onto RAM for fast execution. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Device Description All protocols support XIP operation. For flexibility, multiple XIP entry and exit methods are available. For applications that must enter XIP mode immediately after powering up, XIP mode can be set as the default mode through the nonvolatile configuration register bits. Device Configurability The N25Q family offers additional features that are configured through the nonvolatile configuration register for default and/or nonvolatile settings. Volatile settings can be configured through the volatile and volatile-enhanced configuration registers. These configurable features include the following: • • • • • • Number of dummy cycles for the fast READ commands Output buffer impedance SPI protocol types (extended SPI, DIO-SPI, or QIO-SPI) Required XIP mode Enabling/disabling HOLD (RESET function) Enabling/disabling wrap mode Figure 1: Logic Diagram VCC DQ1 DQ0 C S# RESET2 VPP/W#/DQ2 HOLD#/DQ3 VSS Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for more details. 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Signal Assignments Signal Assignments Figure 2: 8-Lead, VDFPN8 – MLP8 (Top View) Notes: S# 1 8 VCC DQ1 2 7 HOLD#/DQ3 W#/VPP/DQ2 3 6 C VSS 4 5 DQ0 1. On the underside of the MLP8 package, there is an exposed central pad that is pulled internally to VSS and must not be connected to any other voltage or signal line on the PCB. 2. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. Figure 3: 16-Lead, Plastic Small Outline – SO16 (Top View) Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN HOLD#/DQ3 1 16 C VCC 2 15 DQ0 RESET/DNU2 3 14 DNU DNU 4 13 DNU DNU 5 12 DNU DNU 6 11 DNU S# 7 10 VSS DQ1 8 9 W#/VPP/DQ2 1. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. 2. Pin 3 is DNU for devices that do not have the dedicated RESET# pin. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Signal Assignments Figure 4: 24-Ball TBGA (Balls Down) 1 2 3 4 5 NC NC RESET/NC NC NC C VSS VCC NC NC S# NC W#/VPP/DQ2 NC NC DQ1 DQ0 HOLD#/DQ3 NC NC NC A B C D E Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN NC NC NC 1. Reset functionality is available in devices with a dedicated part number. See Part Number Ordering Information for complete package names and details. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for the N25 family devices. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 1: Signal Descriptions Symbol Type Description C Input Clock: Provides the timing of the serial interface. Commands, addresses, or data present at serial data inputs are latched on the rising edge of the clock. Data is shifted out on the falling edge of the clock. S# Input Chip select: When S# is HIGH, the device is deselected and DQ1 is at High-Z. When in extended SPI mode, with the device deselected, DQ1 is tri-stated. Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress, the device enters standby power mode (not deep power-down mode). Driving S# LOW enables the device, placing it in the active power mode. After power-up, a falling edge on S# is required prior to the start of any command. DQ0 Input and I/O Serial data: Transfers data serially into the device. It receives command codes, addresses, and the data to be programmed. Values are latched on the rising edge of the clock. DQ0 is used for input/output during the following operations: DUAL OUTPUT FAST READ, QUAD OUTPUT FAST READ, DUAL INPUT/OUTPUT FAST READ, and QUAD INPUT/OUTPUT FAST READ. When used for output, data is shifted out on the falling edge of the clock. In DIO-SPI, DQ0 always acts as an input/output. In QIO-SPI, DQ0 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with VPP. The device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ1 Output and I/O Serial data:Transfers data serially out of the device. Data is shifted out on the falling edge of the clock. DQ1 is used for input/output during the following operations: DUAL INPUT FAST PROGRAM, QUAD INPUT FAST PROGRAM, DUAL INPUT EXTENDED FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. When used for input, data is latched on the rising edge of the clock. In DIO-SPI, DQ1 always acts as an input/output. In QIO-SPI, DQ1 always acts as an input/output, with the exception of the PROGRAM or ERASE cycle performed with the enhanced program supply voltage (VPP). In this case the device temporarily enters the extended SPI protocol and then returns to QIO-SPI as soon as VPP goes LOW. DQ2 Input and I/O DQ2: When in QIO-SPI mode or in extended SPI mode using QUAD FAST READ commands, the signal functions as DQ2, providing input/output. All data input drivers are always enabled except when used as an output. Micron recommends customers drive the data signals normally (to avoid unnecessary switching current) and float the signals before the memory device drives data on them. DQ3 Input and I/O DQ3: When in quad SPI mode or in extended SPI mode using quad FAST READ commands, the signal functions as DQ3, providing input/output. HOLD# is disabled and RESET# is disabled if the device is selected. RESET# Control Input RESET: This is a hardware RESET# signal. When RESET# is driven HIGH, the memory is in the normal operating mode. When RESET# is driven LOW, the memory enters reset mode and output is High-Z. If RESET# is driven LOW while an internal WRITE, PROGRAM, or ERASE operation is in progress, data may be lost. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Signal Descriptions Table 1: Signal Descriptions (Continued) Symbol Type HOLD# Control Input HOLD: Pauses any serial communications with the device without deselecting the device. DQ1 (output) is High-Z. DQ0 (input) and the clock are "Don't Care." To enable HOLD, the device must be selected with S# driven LOW. HOLD# is used for input/output during the following operations: QUAD OUTPUT FAST READ, QUAD INPUT/OUTPUT FAST READ, QUAD INPUT FAST PROGRAM, and QUAD INPUT EXTENDED FAST PROGRAM. In QIO-SPI, HOLD# acts as an I/O (DQ3 functionality), and the HOLD# functionality is disabled when the device is selected. When the device is deselected (S# is HIGH) in parts with RESET# functionality, it is possible to reset the device unless this functionality is not disabled by means of dedicated registers bits. The HOLD# functionality can be disabled using bit 4 of the NVCR or bit 4 of the VECR. On devices that include DTR mode capability, the HOLD# functionality is disabled as soon as a DTR operation is recognized. W# Control Input Write protect: W# can be used as a protection control input or in QIO-SPI operations. When in extended SPI with single or dual commands, the WRITE PROTECT function is selectable by the voltage range applied to the signal. If voltage range is low (0V to VCC), the signal acts as a write protection control input. The memory size protected against PROGRAM or ERASE operations is locked as specified in the status register block protect bits 3:0. W# is used as an input/output (DQ2 functionality) during QUAD INPUT FAST READ and QUAD INPUT/OUTPUT FAST READ operations and in QIO-SPI. VPP Power Supply voltage: If VPP is in the voltage range of VPPH, the signal acts as an additional power supply, as defined in the AC Measurement Conditions table. During QIFP, QIEFP, and QIO-SPI PROGRAM/ERASE operations, it is possible to use the additional VPP power supply to speed up internal operations. However, to enable this functionality, it is necessary to set bit 3 of the VECR to 0. In this case, VPP is used as an I/O until the end of the operation. After the last input data is shifted in, the application should apply VPP voltage to VPP within 200ms to speed up the internal operations. If the VPP voltage is not applied within 200ms, the PROGRAM/ERASE operations start at standard speed. The default value of VECR bit 3 is 1, and the VPP functionality for quad I/O modify operations is disabled. VCC Power Device core power supply: Source voltage. VSS Ground DNU – Do not use. NC – No connect. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Description Ground: Reference for the VCC supply voltage. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Memory Organization Memory Organization Memory Configuration and Block Diagram Each page of memory can be individually programmed. Bits are programmed from one through zero. The device is subsector, sector, or bulk-erasable, but not page-erasable. Bits are erased from zero through one. The memory is configured as 33,554,432 bytes (8 bits each); 512 sectors (64KB each); 8192 subsectors (4KB each); and 131,072 pages (256 bytes each); and 64 OTP bytes are located outside the main memory array. Figure 5: Block Diagram HOLD# W#/VPP High voltage generator Control logic 64 OTP bytes S# C DQ0 DQ1 DQ2 DQ3 I/O shift register Address register and counter Status register 256 byte data buffer Y decoder 01FFFFFFh 0000000h 00000FFh 256 bytes (page size) X decoder 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Memory Map – 256Mb Density Memory Map – 256Mb Density Table 2: Sectors[511:0] Address Range Sector Subsector Start End 511 8191 01FF F000h 01FF FFFFh ⋮ ⋮ ⋮ 8176 01FF 0000h 01FF 0FFFh ⋮ ⋮ ⋮ ⋮ 255 4095 00FF F000h 00FF FFFFh ⋮ ⋮ ⋮ 4080 00FF 0000h 00FF 0FFFh ⋮ ⋮ ⋮ ⋮ 127 2047 007F F000h 007F FFFFh ⋮ ⋮ ⋮ 2032 007F 0000h 007F 0FFFh ⋮ ⋮ ⋮ ⋮ 63 1023 003F F000h 003F FFFFh ⋮ ⋮ ⋮ 1008 003F 0000h 003F 0FFFh ⋮ ⋮ ⋮ ⋮ 0 15 0000 F000h 0000 FFFFh ⋮ ⋮ ⋮ 0 0000 0000h 0000 0FFFh 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Device Protection Table 3: Data Protection using Device Protocols Note 1 applies to the entire table Protection by: Description Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is outside the operating specification. Command execution check Ensures that the number of clock pulses is a multiple of one byte before executing a PROGRAM or ERASE command, or any command that writes to the device registers. WRITE ENABLE operation Ensures that commands modifying device data must be preceded by a WRITE ENABLE command, which sets the write enable latch bit in the status register. Note: 1. Extended, dual, and quad SPI protocol functionality ensures that device data is protected from excessive noise. Table 4: Memory Sector Protection Truth Table Note 1 applies to the entire table Sector Lock Register Sector Lock Down Bit Sector Write Lock Bit 0 0 Sector unprotected from PROGRAM and ERASE operations. Protection status reversible. 0 1 Sector protected from PROGRAM and ERASE operations. Protection status reversible. 1 0 Sector unprotected from PROGRAM and ERASE operations. Protection status not reversible except by power cycle or reset. 1 1 Sector protected from PROGRAM and ERASE operations. Protection status not reversible except by power cycle or reset. Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Memory Sector Protection Status 1. Sector lock register bits are written to when the WRITE LOCK REGISTER command is executed. The command will not execute unless the sector lock down bit is cleared (see the WRITE LOCK REGISTER command). The sector lock register is programmed to have all protection registers activated at power-up. 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Block Protection Areas Table 5: Protected Area Sizes – Upper Area Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 0 0 0 0 0 None All sectors 0 0 0 0 1 Sector 511 Sectors (0 to 510) 0 0 0 1 0 Sectors (510 to 511) Sectors (0 to 509) 0 0 0 1 1 Sectors (508 to 511) Sectors (0 to 507) 0 0 1 0 0 Sectors (504 to 511) Sectors (0 to 503) 0 0 1 0 1 Sectors (496 to 511) Sectors (0 to 495) 0 0 1 1 0 Sectors (480 to 511) Sectors (0 to 479) 0 0 1 1 1 Sectors (448 to 511) Sectors (0 to 447) 0 1 0 0 0 Sectors (384 to 511) Sectors (0 to 383) 0 1 0 0 1 Sectors (256 to 511) Sectors (0 to 255) 0 1 0 1 0 All sectors None 0 1 0 1 1 All sectors None 0 1 1 0 0 All sectors None 0 1 1 0 1 All sectors None 0 1 1 1 0 All sectors None 0 1 1 1 1 All sectors None Note: 1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits. Table 6: Protected Area Sizes – Lower Area Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 1 0 0 0 0 None All sectors 1 0 0 0 1 Sector 0 Sectors (1 to 511) 1 0 0 1 0 Sectors (0 to 1) Sectors (2 to 511) 1 0 0 1 1 Sectors (0 to 3) Sectors (4 to 511) 1 0 1 0 0 Sectors (0 to 7) Sectors (8 to 511) 1 0 1 0 1 Sectors (0 to 15) Sectors (16 to 511) 1 0 1 1 0 Sectors (0 to 31) Sectors (32 to 511) 1 0 1 1 1 Sectors (0 to 63) Sectors (64 to 511) 1 1 0 0 0 Sectors (0 to 127) Sectors (128 to 511) 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Device Protection Table 6: Protected Area Sizes – Lower Area (Continued) Note 1 applies to the entire table Status Register Content Memory Content Top/ Bottom Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area 1 1 0 0 1 Sectors (0 to 255) Sectors (256 to 511) 1 1 0 1 0 All sectors None 1 1 0 1 1 All sectors None 1 1 1 0 0 All sectors None 1 1 1 0 1 All sectors None 1 1 1 1 0 All sectors None 1 1 1 1 1 All sectors None Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. See the Status Register for details on the top/bottom bit and the BP 3:0 bits. 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Serial Peripheral Interface Modes The device can be driven by a microcontroller while its serial peripheral interface is in either of the two modes shown here. The difference between the two modes is the clock polarity when the bus master is in standby mode and not transferring data. Input data is latched in on the rising edge of the clock, and output data is available from the falling edge of the clock. Table 7: SPI Modes Note: Note 1 applies to the entire table SPI Modes Clock Polarity CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0) CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1) 1. The listed SPI modes are supported in extended, dual, and quad SPI protocols. Shown below is an example of three memory devices in extended SPI protocol in a simple connection to an MCU on an SPI bus. Because only one device is selected at a time, that one device drives DQ1, while the other devices are High-Z. Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus master might enter a state in which all input/output is High-Z simultaneously, such as when the bus master is reset. Therefore, the serial clock must be connected to an external pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW. This ensures that S# and the serial clock are not HIGH simultaneously and that tSHCH is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp = parasitic capacitance of the bus line), is shorter than the time the bus master leaves the SPI bus in High-Z. Example: Cp = 50pF, that is R × Cp = 5μs. The application must ensure that the bus master never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and HOLD# should be driven either HIGH or LOW, as appropriate. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Serial Peripheral Interface Modes Figure 6: Bus Master and Memory Devices on the SPI Bus VSS VCC R SDO SPI interface: (CPOL, CPHA) = (0, 0) or (1, 1) SDI SCK VCC C SPI bus master DQ1 DQ0 R CS3 SPI memory device VCC C VSS R DQ1 DQ0 SPI memory device VCC C VSS R DQ1 DQ0 VSS SPI memory device CS2 CS1 S# W# HOLD# S# W# HOLD# S# W# HOLD# Figure 7: SPI Modes CPOL CPHA 0 0 C 1 1 C DQ0 MSB DQ1 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN MSB 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory SPI Protocols SPI Protocols Table 8: Extended, Dual, and Quad SPI Protocols Protocol Name Command Input Extended DQ0 Multiple DQn lines, depending on the command Dual DQ[1:0] DQ[1:0] Address Input Data Input/Output Description Multiple DQn Device default protocol from the factory. Additional comlines, depending mands extend the standard SPI protocol and enable address on the command or data transmission on multiple DQn lines. DQ[1:0] Volatile selectable: When the enhanced volatile configuration register bit 6 is set to 0 and bit 7 is set to 1, the device enters the dual SPI protocol immediately after the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the default protocol after the next power-on. In addition, the device can return to default protocol using the rescue sequence or through new WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, without power-off or power-on. Nonvolatile selectable: When nonvolatile configuration register bit 2 is set, the device enters the dual SPI protocol after the next power-on. Once this register bit is set, the device defaults to the dual SPI protocol after all subsequent power-on sequences until the nonvolatile configuration register bit is reset to 1. Quad1 DQ[3:0] DQ[3:0] DQ[3:0] Volatile selectable: When the enhanced volatile configuration register bit 7 is set to 0, the device enters the quad SPI protocol immediately after the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The device returns to the default protocol after the next power-on. In addition, the device can return to default protocol using the rescue sequence or through new WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, without poweroff or power-on. Nonvolatile selectable: When nonvolatile configuration register bit 3 is set to 0, the device enters the quad SPI protocol after the next power-on. Once this register bit is set, the device defaults to the quad SPI protocol after all subsequent power-on sequences until the nonvolatile configuration register bit is reset to 1. Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. In quad SPI protocol, all command/address input and data I/O are transmitted on four lines except during a PROGRAM and ERASE cycle performed with VPP. In this case, the device enters the extended SPI protocol to temporarily allow the application to perform a PROGRAM/ERASE SUSPEND operation or to check the write-in-progress bit in the status register or the program/erase controller bit in the flag status register. Then, when VPP goes LOW, the device returns to the quad SPI protocol. 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Nonvolatile and Volatile Registers The device features the following volatile and nonvolatile registers that users can access to store device parameters and operating configurations: • • • • • • Status register Nonvolatile and volatile configuration registers Extended address register Enhanced volatile configuration register Flag status register Lock register Note: The lock register is defined in READ LOCK REGISTER Command. The working condition of memory is set by an internal configuration register that is not directly accessible to users. As shown below, parameters in the internal configuration register are loaded from the nonvolatile configuration register during each device boot phase or power-on reset. In this sense, then, the nonvolatile configuration register contains the default settings of memory. Also, during the life of an application, each time a WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER command executes to set configuration parameters in these respective registers, these new settings are copied to the internal configuration register. Therefore, memory settings can be changed in real time. However, at the next power-on reset, the memory boots according to the memory settings defined in the nonvolatile configuration register parameters. Figure 8: Internal Configuration Register Nonvolatile configuration register Register download is executed only during the power-on phase or after a reset, overwriting configuration register settings on the internal configuration register. Volatile configuration register and enhanced volatile configuration register Internal configuration register Register download is executed after a WRITE VOLATILE OR ENHANCED VOLATILE CONFIGURATION REGISTER command, overwriting configuration register settings on the internal configuration register. Device behavior 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Status Register Table 9: Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Status register 0 = Enabled write enable/disable 1 = Disabled Nonvolatile bit: Used with the W/VPP signal to enable or disable writing to the status register. 3 5 Top/bottom 0 = Top 1 = Bottom Nonvolatile bit: Determines whether the protected memory area defined by the block protect bits starts from the top or bottom of the memory array. 4 6, 4:2 Block protect 3–0 See Protected Area Sizes – Upper Area and Lower Area tables in Device Protection Nonvolatile bit: Defines memory to be software protected against PROGRAM or ERASE operations. When one or more block protect bits is set to 1, a designated memory area is protected from PROGRAM and ERASE operations. 4 1 Write enable latch 0 = Cleared (Default) Volatile bit: The device always powers up with this bit 1 = Set cleared to prevent inadvertent WRITE STATUS REGISTER, PROGRAM, or ERASE operations. To enable these operations, the WRITE ENABLE operation must be executed first to set this bit. 2 0 Write in progress 0 = Ready 1 = Busy Notes: Volatile bit: Indicates if one of the following command cycles is in progress: WRITE STATUS REGISTER WRITE NONVOLATILE CONFIGURATION REGISTER PROGRAM ERASE 2 1. Bits can be read from or written to using READ STATUS REGISTER or WRITE STATUS REGISTER commands, respectively. 2. Volatile bits are cleared to 0 by a power cycle or reset. 3. The status register write enable/disable bit, combined with the W#/VPP signal as described in the Signal Descriptions, provides hardware data protection for the device as follows: When the enable/disable bit is set to 1, and the W#/VPP signal is driven LOW, the status register nonvolatile bits become read-only and the WRITE STATUS REGISTER operation will not execute. The only way to exit this hardware-protected mode is to drive W#/VPP HIGH. 4. See Protected Area Sizes tables. The BULK ERASE command is executed only if all bits are 0. Nonvolatile and Volatile Configuration Registers 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 10: Nonvolatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 15:12 Number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 Sets the number of dummy clock cycles subsequent to all FAST READ commands. The default setting targets the maximum allowed frequency and guarantees backward compatibility. 11:9 XIP mode at power-on reset 000 = XIP: Fast Read 001 = XIP: Dual Output Fast Read 010 = XIP: Dual I/O Fast Read 011 = XIP: Quad Output Fast Read 100 = XIP: Quad I/O Fast Read 101 = Reserved 110 = Reserved 111 = Disabled (Default) Enables the device to operate in the selected XIP mode immediately after power-on reset. 8:6 Output driver 000 = Reserved strength 001 = 90 Ohms 010 = 60 Ohms 011 = 45 Ohms 100 = Reserved 101 = 20 Ohms 110 = 15 Ohms 111 = 30 (Default) Optimizes impedance at VCC/2 output voltage. 5 Reserved X "Don't Care." 4 Reset/hold 0 = Disabled 1 = Enabled (Default) Enables or disables hold or reset. (Available on dedicated part numbers.) 3 Quad I/O pro- 0 = Enabled tocol 1 = Disabled (Default, Extended SPI protocol) Enables or disables quad I/O protocol. 4 2 Dual I/O protocol 0 = Enabled 1 = Disabled (Default, Extended SPI protocol) Enables or disables dual I/O protocol. 4 1 128Mb segment select 0 = Upper 128Mb segment 1 = Lower 128Mb segment (Default) Selects a 128Mb segment as default for 3B address operations. See also the extended address register. 0 Address bytes 0 = Enable 4B address 1 = Enable 3B address (Default) Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 2, 3 Defines the number of address bytes for a command. 1. Settings determine device memory configuration after power-on. The device ships from the factory with all bits erased to 1 (FFFFh). The register is read from or written to by READ NONVOLATILE CONFIGURATION REGISTER or WRITE NONVOLATILE CONFIGURATION REGISTER commands, respectively. 2. The 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility. 22 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers 3. If the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. The number of cycles must be set according to and sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Frequencies table. 4. If bits 2 and 3 are both set to 0, the device operates in quad I/O. When bits 2 or 3 are reset to 0, the device operates in dual I/O or quad I/O respectively, after the next poweron. Table 11: Volatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings 7:4 Description Notes Number of dummy clock cycles 0000 (identical to 1111) 0001 0010 . . 1101 1110 1111 Sets the number of dummy clock cycles subsequent to all FAST READ commands. The default setting targets maximum allowed frequency and guarantees backward compatibility. 3 XIP 0 1 Enables or disables XIP. For device part numbers with feature digit equal to 2 or 4, this bit is always "Don’t Care," so the device operates in XIP mode without setting this bit. 2 Reserved x = Default 0b = Fixed value. Wrap 00 = 16-byte boundary aligned 16-byte wrap: Output data wraps within an aligned 16byte boundary starting from the 3-byte address issued after the command code. 01 = 32-byte boundary aligned 32-byte wrap: Output data wraps within an aligned 32byte boundary starting from the 3-byte address issued after the command code. 10 = 64-byte boundary aligned 64-byte wrap: Output data wraps within an aligned 64byte boundary starting from the 3-byte address issued after the command code. 11 = sequential (default) Continuous reading (default): All bytes are read sequentially. 1:0 Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 2, 3 4 1. Settings determine the device memory configuration upon a change of those settings by the WRITE VOLATILE CONFIGURATION REGISTER command. The register is read from or written to by READ VOLATILE CONFIGURATION REGISTER or WRITE VOLATILE CONFIGURATION REGISTER commands respectively. 2. The 0000 and 1111 settings are identical in that they both define the default state, which is the maximum frequency of fc = 108 MHz. This ensures backward compatibility. 3. If the number of dummy clock cycles is insufficient for the operating frequency, the memory reads wrong data. The number of cycles must be set according to and be sufficient for the clock frequency, which varies by the type of FAST READ command, as shown in the Supported Clock Frequencies table. 4. See the Sequence of Bytes During Wrap table. 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Table 12: Sequence of Bytes During Wrap Starting Address 16-Byte Wrap 32-Byte Wrap 64-Byte Wrap 0 0-1-2- . . . -15-0-1- . . 0-1-2- . . . -31-0-1- . . 0-1-2- . . . -63-0-1- . . 1 1-2- . . . -15-0-1-2- . . 1-2- . . . -31-0-1-2- . . 1-2- . . . -63-0-1-2- . . 15 15-0-1-2-3- . . . -15-0-1- . . 15-16-17- . . . -31-0-1- . . 15-16-17- . . . -63-0-1- . . 31 31-16-17- . . . -31-16-17- . . 31-0-1-2-3- . . . -31-0-1- . . 31-32-33- . . . -63-0-1- . . 63 63-48-49- . . . -63-48-49- . . 63-32-33- . . . -63-32-33- . . 63-0-1- . . . -63-0-1- . . Table 13: Supported Clock Frequencies – STR Note 1 applies to entire table Number of Dummy Clock Cycles FAST READ DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ 1 90 80 50 60 30 2 100 90 70 75 40 3 108 100 80 90 50 4 108 105 90 100 60 5 108 108 100 94 70 6 108 108 105 105 80 7 108 108 108 108 86 8 108 108 108 108 95 9 108 108 108 108 105 10 108 108 108 108 108 Note: 1. Values are guaranteed by characterization and not 100% tested in production. Table 14: Supported Clock Frequencies – DTR Number of Dummy Clock Cycles FAST READ DUAL OUTPUT FAST READ DUAL I/O FAST READ QUAD OUTPUT FAST READ QUAD I/O FAST READ 1 45 40 25 30 15 2 50 45 35 38 20 3 54 50 40 45 25 4 54 53 45 47 30 5 54 54 50 50 35 6 54 54 53 53 40 7 54 54 54 54 43 8 54 54 54 54 48 9 54 54 54 54 53 10 54 54 54 54 54 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 24 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Extended Address Register For devices whose A[MAX:MIN] equals A[23:0], N25Q includes an extended address register that provides a fourth address byte A[31:24], enabling access to memory beyond 128Mb. Extended address register bit 0 is used to select the upper 128Mb segment or the lower 128Mb segment of the memory array. Figure 9: Upper and Lower 128Mb Memory Array Segments Upper 128Mb 01FFFFFFh Bottom 128Mb EAR = A = 1 00FFFFFFh 01000000h 00000000h EAR = A = 0 The PROGRAM and ERASE operations act upon the 128Mb segment selected in the extended address register. The BULK ERASE operation erases the entire device. The READ operation begins reading in the selected 128Mb segment, but is not bound by it. In a continuous READ, when the last byte of the segment is read, the next byte output is the first byte of the other segment as the operation wraps to 0000000h; Therefore, a download of the whole array is possible with one READ operation. The value of the extended address register does not change when a READ operation crosses the selected 128Mb boundary. Table 15: Extended Address Register Bit Definitions Bit 7 Name Settings Description A[31:25] 0 = Reserved – 6 5 4 3 2 1 0 A[24] 0 = Lower 128Mb segment (default) 1 = Upper 128Mb segment Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Enables 128Mb segmentation selection. The default setting for this bit is determined by the nonvolatile configuration register bit 1. However, this setting can be changed with the WRITE EXTENDED ADDRESS REGISTER command. 1. Bit 0 enables 128Mb segmentation selection. If 4-byte addressing is enabled, extended address register settings are ignored. 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Enhanced Volatile Configuration Register Table 16: Enhanced Volatile Configuration Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Quad I/O protocol 0 = Enabled Enables or disables quad I/O protocol. 1 = Disabled (Default, extended SPI protocol) 2 6 Dual I/O protocol 0 = Enabled Enables or disables dual I/O protocol. 1 = Disabled (Default, extended SPI protocol) 2 5 Reserved x = Default 0b = Fixed value. 4 Reset/hold 0 = Disabled 1 = Enabled (Default) Enables or disables hold or reset. (Available on dedicated part numbers.) 3 VPP accelerator 0 = Enabled 1 = Disabled (Default) Enables or disables VPP acceleration for QUAD INPUT FAST PROGRAM and QUAD INPUT EXTENDED FAST PROGRAM OPERATIONS. 2:0 Output driver strength 000 = Reserved 001 = 90 Ohms 010 = 60 Ohms 011 = 45 Ohms 100 = Reserved 101 = 20 Ohms 110 = 15 Ohms 111 = 30 (Default) Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Optimizes impedance at VCC/2 output voltage. 1. Settings determine the device memory configuration upon a change of those settings by the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. The register is read from or written to in all protocols by READ ENHANCED VOLATILE CONFIGURATION REGISTER or WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands, respectively. 2. If bits 6 and 7 are both set to 0, the device operates in quad I/O. When either bit 6 or 7 is reset to 0, the device operates in dual I/O or quad I/O respectively following the next WRITE ENHANCED VOLATILE CONFIGURATION command. 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Nonvolatile and Volatile Registers Flag Status Register Table 17: Flag Status Register Bit Definitions Note 1 applies to entire table Bit Name Settings Description Notes 7 Program or erase controller 0 = Busy 1 = Ready Status bit: Indicates whether a PROGRAM, ERASE, WRITE STATUS REGISTER, or WRITE NONVOLATILE CONFIGURATION command cycle is in progress. 2, 3 6 Erase suspend 0 = Not in effect 1 = In effect Status bit: Indicates whether an ERASE operation has been or is going to be suspended. 3 5 Erase 0 = Clear 1 = Failure or protection error Error bit: Indicates whether an ERASE operation has succeeded or failed. 4, 5 4 Program 0 = Clear 1 = Failure or protection error Error bit: Indicates whether a PROGRAM operation has succeeded or failed. Also indicates an attempt to program a 0 to a 1 when VPP = VPPH and the data pattern is a multiple of 64 bits. 4, 5 3 VPP 0 = Enabled 1 = Disabled (Default) Error bit: Indicates an invalid voltage on VPP during a PROGRAM or ERASE operation. 4, 5 2 Program suspend 0 = Not in effect 1 = In effect Status bit: Indicates whether a PROGRAM operation has been or is going to be suspended. 3 1 Protection 0 = Clear 1 = Failure or protection error Error bit: Indicates whether a PROGRAM or ERASE operation has attempted to modify the protected array sector. Also indicates whether a PROGRAM operation has attempted to access the locked OTP space. 4, 5 0 Addressing 0 = 3 bytes addressing 1 = 4 bytes addressing Status bit: Indicates whether 3-byte or 4-byte address mode is enabled. 3 Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Register bits are read by READ STATUS REGISTER command. All bits are volatile. 2. These program/erase controller settings apply only to PROGRAM or ERASE command cycles in progress; they do not apply to a WRITE command cycle in progress. 3. Status bits are reset automatically. 4. Error bits must be reset by CLEAR FLAG STATUS REGISTER command. 5. Typical errors include operation failures and protection errors caused by issuing a command before the error bit has been reset to 0. 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Command Definitions Table 18: Command Set Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes RESET ENABLE 66h Yes Yes Yes 0 2 RESET MEMORY 99h Command RESET Operations IDENTIFICATION Operations READ ID 9E/9Fh Yes No No 1 to 20 2 MULTIPLE I/O READ ID AFh No Yes Yes 1 to 3 2 READ SERIAL FLASH DISCOVERY PARAMETER 5Ah Yes Yes Yes 1 to ∞ 3 READ 03h Yes No No 1 to ∞ 4 FAST READ 0Bh Yes Yes Yes DUAL OUTPUT FAST READ 3Bh Yes Yes No DUAL INPUT/OUTPUT FAST READ 0Bh 3Bh BBh Yes Yes No QUAD OUTPUT FAST READ 6Bh Yes No Yes QUAD INPUT/OUTPUT FAST READ 0Bh 6Bh EBh Yes No Yes FAST READ – DTR 0Dh Yes Yes Yes 1 to ∞ 6 DUAL OUTPUT FAST READ – DTR 3Dh Yes Yes No 1 to ∞ 6 DUAL INPUT/OUTPUT FAST READ – DTR 0Dh 3Dh BDh Yes Yes No 1 to ∞ 6 QUAD OUTPUT FAST READ – DTR 6Dh Yes No Yes 1 to ∞ 6 QUAD INPUT/OUTPUT FAST READ – DTR 0Dh 6Dh EDh Yes No Yes 1 to ∞ 7 4-BYTE READ 13h Yes Yes Yes 1 to ∞ 8 4-BYTE FAST READ 0Ch 4-BYTE DUAL OUTPUT FAST READ 3Ch Yes Yes No 1 to ∞ 4-BYTE DUAL INPUT/OUTPUT FAST READ BCh Yes Yes No 4-BYTE QUAD OUTPUT FAST READ 6Ch Yes No Yes 4-BYTE QUAD INPUT/OUTPUT FAST READ ECh Yes No Yes READ Operations 5 1 to ∞ 5 5, 11 1 to ∞ 5 5, 12 9 9 9, 11 1 to ∞ 9 10, 12 WRITE Operations 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 28 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Table 18: Command Set (Continued) Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes WRITE ENABLE 06h Yes Yes Yes 0 2 WRITE DISABLE 04h Yes Yes Yes 1 to ∞ 2 1 2, 13 Command REGISTER Operations READ STATUS REGISTER 05h WRITE STATUS REGISTER 01h READ LOCK REGISTER E8h WRITE LOCK REGISTER E5h READ FLAG STATUS REGISTER 70h CLEAR FLAG STATUS REGISTER 50h READ NONVOLATILE CONFIGURATION REGISTER B5h WRITE NONVOLATILE CONFIGURATION REGISTER B1h READ VOLATILE CONFIGURATION REGISTER 85h WRITE VOLATILE CONFIGURATION REGISTER 81h READ ENHANCED VOLATILE CONFIGURATION REGISTER 65h WRITE ENHANCED VOLATILE CONFIGURATION REGISTER 61h READ EXTENDED ADDRESS REGISTER C8h WRITE EXTENDED ADDRESS REGISTER C5h Yes Yes Yes 1 to ∞ 4 1 4, 13 Yes Yes Yes 1 to ∞ 2 0 Yes Yes Yes 2 2 2, 13 Yes Yes Yes Yes Yes Yes Yes Yes Yes 1 to ∞ 2 1 2, 13 1 to ∞ 2 1 2, 13 1 to ∞ 2 1 2, 14 PROGRAM Operations PAGE PROGRAM 02h Yes Yes Yes 1 to 256 4, 13 4-BYTE PAGE PROGRAM 12h Yes Yes Yes 1 to 256 4, 13, 15 DUAL INPUT FAST PROGRAM A2h Yes Yes No 1 to 256 4, 13 EXTENDED DUAL INPUT FAST PROGRAM 02h A2h D2h Yes Yes No QUAD INPUT FAST PROGRAM 32h Yes No Yes 4-BYTE QUAD INPUT FAST PROGRAM 34h Yes No Yes 4, 13, 15 02h 32h 12h/38h Yes No Yes 4, 12, 13, 16 SUBSECTOR ERASE 20h Yes Yes Yes 4-BYTE SUBSECTOR ERASE 21h EXTENDED QUAD INPUT FAST PROGRAM 4, 11, 13 1 to 256 4, 13 ERASE Operations 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 0 4, 13 4, 13, 15 29 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions Table 18: Command Set (Continued) Note 1 applies to entire table Code Extended Dual I/O Quad I/O Data Bytes Notes SECTOR ERASE D8h Yes Yes Yes 0 4, 13 4-BYTE SECTOR ERASE DCh Command 4, 13, 15 BULK ERASE C7h Yes Yes Yes 0 4, 13 PROGRAM/ERASE RESUME 7Ah Yes Yes Yes 0 2, 13 PROGRAM/ERASE SUSPEND 75h Yes Yes Yes 1 to 64 ONE-TIME PROGRAMMABLE (OTP) Operations READ OTP ARRAY 4Bh PROGRAM OTP ARRAY 42h 5 4, 13 4-BYTE ADDRESS MODE Operations ENTER 4-BYTE ADDRESS MODE B7h EXIT 4-BYTE ADDRESS MODE E9h Yes Yes Yes 0 2, 14 Yes Yes Yes 0 2, 15 QUAD Operations ENTER QUAD 35h EXIT QUAD F5h 2, 15 DEEP POWER-DOWN Operations ENTER DEEP POWER-DOWN B9h RELEASE from DEEP POWER-DOWN ABh Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Yes Yes Yes 0 2 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. 2. Address bytes = 0. Dummy clock cycles = 0. 3. Address bytes = 3. Dummy clock cycles default = 8. 4. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles = 0. 5. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles default = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user. 6. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles default = 6. Dummy clock cycles default = 8 when quad SPI protocol is enabled. Dummy clock cycles are configurable by the user. 7. Address bytes default = 3; address bytes = 4 (extended address). Dummy clock cycles default = 8. Dummy clock cycles are configurable by the user. 8. Address bytes = 4. Dummy clock cycles = 0. 9. Address bytes = 4. Dummy clock cycles default = 8. Dummy clock cycles default = 10 (when quad SPI protocol is enabled). Dummy clock cycles are configurable by the user. 10. Address bytes = 4. Dummy clock cycles default = 10. Dummy clock cycles is configurable by the user. 11. When the device is in dual SPI protocol, the command can be entered with any of these three codes. The different codes enable compatibility between dual SPI and extended SPI protocols. 12. When the device is in quad SPI protocol, the command can be entered with any of these three codes. The different codes enable compatibility between quad SPI and extended SPI protocols. 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory Command Definitions 13. The WRITE ENABLE command must be issued first before this command can be executed. 14. Except for line items that enable the additional RESET# pin, the WRITE ENABLE command must be issued first before this command can be executed. 15. These commands are only available for line items that enable the additional RESET# pin. 16. The code 38h is only valid for line items that enable the additional RESET# pin; otherwise, code 12h is valid. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations READ REGISTER and WRITE REGISTER Operations READ STATUS REGISTER or FLAG STATUS REGISTER Command To initiate a READ STATUS REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. The status register can be read continuously and at any time, including during a PROGRAM, ERASE, or WRITE operation. The flag status register can be read continuously and at any time, including during an ERASE or WRITE operation. If one of these operations is in progress, checking the write in progress bit or P/E controller bit is recommended before executing the command. Figure 10: READ REGISTER Command Extended 0 7 9 8 10 11 12 13 14 15 C LSB Command DQ0 MSB LSB DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dual 0 3 4 5 6 7 C LSB LSB DOUT DOUT Command DQ[1:0] MSB DOUT DOUT DOUT MSB Quad 0 1 2 3 C LSB Command DQ[3:0] MSB Notes: DOUT LSB DOUT DOUT Don’t Care MSB 1. Supports all READ REGISTER commands except READ LOCK REGISTER. 2. A READ NONVOLATILE CONFIGURATION REGISTER operation will output data starting from the least significant byte. READ NONVOLATILE CONFIGURATION REGISTER Command To execute a READ NONVOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 32 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. The nonvolatile configuration register can be read continuously. After all 16 bits of the register have been read, a 0 is output. All reserved fields output a value of 1. READ VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command To execute a READ VOLATILE CONFIGURATION REGISTER command or a READ ENHANCED VOLATILE CONFIGURATION REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. When the register is read continuously, the same byte is output repeatedly. READ EXTENDED ADDRESS REGISTER Command To initiate a READ EXTENDED ADDRESS REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, and output on DQ1. For dual SPI protocol, the command code is input on DQ[1:0], and output on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0], and is output on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. When the register is read continuously, the same byte is output repeatedly. WRITE STATUS REGISTER Command To issue a WRITE STATUS REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tW. This command is used to write new values to status register bits 7:2, enabling software data protection. The status register can also be combined with the W#/V PP signal to provide hardware data protection. The WRITE STATUS REGISTER command has no effect on status register bits 1:0. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0, whether the operation is successful or not. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 33 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Figure 11: WRITE REGISTER Command Extended 0 7 8 9 10 11 12 13 15 14 C LSB LSB DIN Command DQ0 MSB Dual DIN DIN DIN DIN DIN DIN DIN MSB 0 3 4 5 6 7 C LSB MSB Quad LSB DIN Command DQ[1:0] DIN DIN DIN DIN MSB 0 1 2 3 C LSB LSB Command DQ[3:0] MSB Notes: DIN DIN DIN MSB 1. Supports all WRITE REGISTER commands except WRITE LOCK REGISTER. 2. Waveform must be extended for each protocol, to 23 for extended, 11 for dual, and 5 for quad. 3. A WRITE NONVOLATILE CONFIGURATION REGISTER operation requires data being sent starting from least significant byte. WRITE NONVOLATILE CONFIGURATION REGISTER Command To execute the WRITE NONVOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the 16th bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by two data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tNVCR. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0, whether the operation is successful or not. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER Command To execute a WRITE VOLATILE CONFIGURATION REGISTER command or a WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. For extended SPI protocol, the command code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 34 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. DIN 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Because register bits are volatile, change to the bits is immediate. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. Reserved bits are not affected by this command. WRITE EXTENDED ADDRESS REGISTER Command To initiate a WRITE EXTENDED ADDRESS REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. Note: The WRITE ENABLE command is not necessary on line items that enable the additional RESET# pin. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by the data bytes. For dual SPI protocol, the command code is input on DQ[1:0], followed by the data bytes. For quad SPI protocol, the command code is input on DQ[3:0], followed by the data bytes. Because register bits are volatile, change to the bits is immediate. If S# is not driven HIGH, the command is not executed, the flag status register error bits are not set, and the write enable latch remains set to 1. Reserved bits are not affected by this command. READ LOCK REGISTER Command To execute the READ LOCK REGISTER command, S# is driven LOW. For extended SPI protocol, the command code is input on DQ0, followed by address bytes that point to a location in the sector. For dual SPI protocol, the command code is input on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. Each address bit is latched in during the rising edge of the clock. For extended SPI protocol, data is shifted out on DQ1 at a maximum frequency fC during the falling edge of the clock. For dual SPI protocol, data is shifted out on DQ[1:0], and for quad SPI protocol, data is shifted out on DQ[3:0]. The operation is terminated by driving S# HIGH at any time during data output. When the register is read continuously, the same byte is output repeatedly. Any READ LOCK REGISTER command that is executed while an ERASE, PROGRAM, or WRITE cycle is in progress is rejected with no affect on the cycle in progress. Table 19: Lock Register Note 1 applies to entire table Bit Name 7:2 1 Settings Description Reserved 0 Bit values are 0. Sector lock down 0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared, 1 = Set which means sector lock down and sector write lock bits can be set. When this bit set, neither of the lock register bits can be written to until the next power cycle. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 35 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations Table 19: Lock Register (Continued) Note 1 applies to entire table Bit Name 0 Settings Sector write lock Note: Description 0 = Cleared (Default) Volatile bit: the device always powers-up with this bit cleared, 1 = Set which means that PROGRAM and ERASE operations in this sector can be executed and sector content modified. When this bit is set, PROGRAM and ERASE operations in this sector will not be executed. 1. Sector lock register bits 1:0 are written by the WRITE LOCK REGISTER command. The command will not execute unless the sector lock down bit is cleared. Figure 12: READ LOCK REGISTER Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ[0] MSB A[MAX] DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB Quad A[MAX] 0 1 MSB 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] Note: LSB DOUT DOUT Don’t Care MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2). For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4). WRITE LOCK REGISTER Command To initiate the WRITE LOCK REGISTER command, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQn, followed by address bytes that point to a location in the sector, and then one data byte that contains the desired settings for lock register bits 0 and 1. Each address bit is latched in during the rising edge of the clock. When execution is complete, the write enable latch bit is cleared within tSHSL2 and no error bits are set. Because lock register bits are volatile, change to the bits is immediate. WRITE LOCK REGISTER can be executed when an ERASE SUSPEND operation is in ef- 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 36 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ REGISTER and WRITE REGISTER Operations fect. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. Figure 13: WRITE LOCK REGISTER Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] Note: DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + ((A[MAX] + 1)/2). For quad SPI protocol, Cx = 1 + ((A[MAX] + 1)/4). CLEAR FLAG STATUS REGISTER Command To execute the CLEAR FLAG STATUS REGISTER command and reset the error bits (erase, program, and protection), S# is driven LOW. For extended SPI protocol, the command code is input on DQ0. For dual SPI protocol, the command code is input on DQ[1:0]. For quad SPI protocol, the command code is input on DQ[3:0]. The operation is terminated by driving S# HIGH at any time. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 37 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations READ IDENTIFICATION Operations READ ID and MULTIPLE I/O READ ID Commands To execute the READ ID or MULTIPLE I/O READ ID commands, S# is driven LOW and the command code is input on DQn. The device outputs the information shown in the tables below. If an ERASE or PROGRAM cycle is in progress when the command is executed, the command is not decoded and the command cycle in progress is not affected. When S# is driven HIGH, the device goes to standby. The operation is terminated by driving S# HIGH at any time during data output. Table 20: Data/Address Lines for READ ID and MULTIPLE I/O READ ID Commands Command Name READ ID MULTIPLE I/O READ ID Note: Data In Data Out Unique ID is Output Extended Dual Quad DQ0 DQ0 Yes Yes No No DQ[3:0] DQ[1:0] No No Yes Yes 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. Table 21: Read ID Data Out Size (Bytes) Name Content Value 1 Manufacturer ID 20h (selected by READ MANUFACTURER ID) 2 Device ID 17 Memory Type BBh Memory Capacity 19h (256Mb) Assigned by JEDEC Manufacturer Unique ID 1 Byte: Length of data to follow 10h 2 Bytes: Extended device ID and device configuration information ID and information such as uniform architecture, and HOLD or RESET functionality 14 Bytes: Customized factory data Optional Note: Factory 1. The 17 bytes of information in the unique ID is read by the READ ID command, but cannot be read by the MULTIPLE I/O READ ID command. Table 22: Extended Device ID, First Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Reserved Reserved 1 = Alternate BP scheme 0 = Standard BP scheme Volatile configuration register bit setting: 0 = Required 1 = Not required HOLD#/RESET#: 0 = HOLD 1 = RESET Addressing: 0 = by byte 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 38 Bit 1 Bit 0 Architecture: 00 = Uniform Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Figure 14: READ ID and MULTIPLE I/O Read ID Commands Extended (READ ID) 0 7 16 15 8 31 32 C LSB DQ0 Command MSB LSB DOUT DOUT High-Z DQ1 MSB DOUT 0 3 UID Device identification 8 7 4 LSB DOUT DOUT MSB MSB Manufacturer identification Dual (MULTIPLE I/O READ ID ) LSB DOUT 15 C LSB DQ[1:0] LSB DOUT DOUT Command MSB MSB DOUT MSB Manufacturer identification Quad (MULTIPLE I/O READ ID ) 0 LSB DOUT 1 Device identification 4 3 2 7 C LSB DQ[3:0] Command MSB DOUT LSB DOUT MSB LSB DOUT MSB Manufacturer identification Note: DOUT Device identification Don’t Care 1. The READ ID command is represented by the extended SPI protocol timing shown first. The MULTIPLE I/O READ ID command is represented by the dual and quad SPI protocols are shown below extended SPI protocol. READ SERIAL FLASH DISCOVERY PARAMETER Command To execute READ SERIAL FLASH DISCOVERY PARAMETER command, S# is driven LOW. The command code is input on DQ0, followed by three address bytes and eight dummy clock cycles (address is always 3 bytes, even for 4-byte address mode). The device outputs the information starting from the specified address. When the 2048-byte boundary is reached, the data output wraps to address 0 of the serial Flash discovery parameter table. The operation is terminated by driving S# HIGH at any time during data output. The operation always executes in continuous mode so the read burst wrap setting in the volatile configuration register does not apply. Note: Data to be stored in the serial Flash discovery parameter area is still in the definition phase. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 39 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 23: Serial Flash Discovery Parameter Data Structure Compliant with JEDEC standard JC-42.4 1775.03 Description Serial Flash discoverable parameters signature Serial Flash discoverable parameters Address (Byte Mode) Address (Bit) Data 00h 7:00 53h 01h 15:8 46h 02h 23:16 44h 03h 31:24 50h Minor revision 04h 7:0 00h Major revision 05h 15:8 01h Number of parameter headers 06h 7:0 00h Reserved 07h 15:8 FFh Parameter ID (0) JEDEC-defined parameter table 08h 7:0 00h Parameter Minor revision 09h 15:8 00h Major revision 0Ah 23:16 01h Parameter length (DW) 0Bh 31:24 09h Parameter table pointer 0Ch 7:0 30h 0Dh 15:8 00h 0Eh 23:16 00h Reserved 0Fh 31:24 FFh Parameter ID (1) 10h 7:0 FFh Minor revision 11h 15:8 FFh Major revision Parameter 12h 23:16 FFh Parameter length (DW) 13h 31:24 FFh Parameter table pointer 14h 7:0 FFh 15h 15:8 FFh 16h 23:16 FFh Reserved 17h 31:24 FFh Parameter ID (2) 18h 7:0 FFh Minor revision 19h 15:8 FFh Major revision Parameter 1Ah 23:16 FFh Parameter length (DW) 1Bh 31:24 FFh Parameter table pointer 1Ch 7:0 FFh 1Dh 15:8 FFh 1Eh 23:16 FFh 1Fh 31:24 FFh Reserved 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 40 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 24: Parameter ID Compliant with JEDEC standard JC-42.4 1775.03 Description Minimum block/sector erase sizes Address (Byte Mode) Address (Bit) Data 30h 0 10 1 Write granularity 2 1 WRITE ENABLE command required for writing to volatile status registers 3 0 Reserved 5 1 6 1 7 1 4 4KB erase command code 31h 15:8 20h Supports DUAL OUTPUT FAST READ operation (single input address, dual output) 32h 16 1 Number of address bytes used (3-byte or 4-byte) for array READ, WRITE, and ERASE commands 17 1 Supports double transfer rate clocking 19 1 Supports DUAL INPUT/OUTPUT FAST READ operation (dual input address, dual output) 20 1 Supports QUAD INPUT/OUTPUT FAST READ operation (quad input address, quad output) 21 1 Supports QUAD OUTPUT FAST READ operation (single input address, quad output) 22 1 Reserved 23 1 33h 31:24 FFh 34h–37h 31:0 0FFFFFFFh 38h 4:00 01001b 7:5 001b Reserved Flash size (bits) Number of dummy clock cycles required before valid output from QUAD INPUT/OUTPUT FAST READ operation 18 Number of XIP confirmation bits for QUAD INPUT/OUTPUT FAST READ operation Command code for QUAD INPUT/OUTPUT FAST READ operation 39h 15:8 EBh Number of dummy clock cycles required before valid output from QUAD OUTPUT FAST READ operation 3Ah 20:16 00111b 23:21 001b Number of XIP confirmation bits for QUAD OUTPUT FAST READ operation Command code for QUAD OUTPUT FAST READ operation 3Bh 31:24 6Bh Number of dummy clock cycles required before valid output from DUAL OUTPUT FAST READ operation 3Ch 4:0 01000b 7:5 000b 15:8 3Bh Number of XIP confirmation bits for DUAL OUTPUT FAST READ operation Command code for DUAL OUTPUT FAST READ operation 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 3Dh 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ IDENTIFICATION Operations Table 24: Parameter ID (Continued) Compliant with JEDEC standard JC-42.4 1775.03 Description Number of dummy clock cycles required before valid output from DUAL INPUT/OUTPUT FAST READ operation Address (Byte Mode) Address (Bit) Data 3Eh 20:16 00111b 23:21 001b Number of XIP confirmation bits for DUAL INPUT/OUTPUT FAST READ Command code for DUAL INPUT/OUTPUT FAST READ operation 3Fh 31:24 BBh Supports FAST READ operation in dual SPI protocol 40h 0 1 3:1 111b 4 1 Reserved Supports FAST READ operation in quad SPI protocol Reserved 7:5 111b Reserved 41h–43h – FFFFFFh Reserved 44h–45h – FFFFh Number of dummy clock cycles required before valid output from FAST READ operation in dual SPI protocol 46h 4:0 00111b Number of XIP confirmation bits for FAST READ operation in dual SPI protocol 46h 7:5 001b Command code for FAST READ operation in dual SPI protocol 47h 7:0 BBh 48h–49h – FFFFh 4Ah 4:0 01001b 7:5 001b Reserved Number of dummy clock cycles required before valid output from FAST READ operation in quad SPI protocol Number of XIP confirmation bits for FAST READ operation in quad SPI protocol Command code for FAST READ operation in quad SPI protocol 4Bh 7:0 EBh Sector type 1 size (4k) 4Ch 7:0 0Ch Sector type 1 command code (4k) 4Ch 7:0 0Ch Sector type 2 size (64KB) 4Eh 7:0 10h Sector type 2 command code 64KB) 4Fh 7:0 D8h Sector type 3 size (not present) 50h 7:0 00h Sector type 3 size (not present) 51h 7:0 00h Sector type 4 size (not present) 52h 7:0 00h Sector type 4 size (not present) 53h 7:0 00h 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 42 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations READ MEMORY Operations The device supports default reading and writing to an A[MAX:MIN] of A[23:0] (3-byte address). Reading and writing to an A[MAX:MIN] of A[31:0] (4-byte address) is also supported. Selection of the 3-byte or 4-byte address range can be enabled in two ways: setting the nonvolatile configuration register or entering the ENABLE 4-BYTE ADDRESS MODE or EXIT 4-BYTE ADDRESS MODE commands. Further details for these settings and commands are in the respective register and command sections of the data sheet. Note: When the device is set to the default address range of A[23:0], another method for enabling 4-byte addressing is through the extended address register. Details can be found in Nonvolatile and Volatile Registers. 3-Byte Address To execute READ MEMORY commands, S# is driven LOW. The command code is input on DQn, followed by input on DQn of three address bytes. Each address bit is latched in during the rising edge of the clock. The addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, the entire memory can be read with a single command. The operation is terminated by driving S# HIGH at any time during data output. Table 25: Command/Address/Data Lines for READ MEMORY Commands Note 1 applies to entire table Command Name DUAL QUAD DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT FAST READ FAST READ FAST READ FAST READ READ FAST READ STR Mode 03h 0Bh 3Bh BBh 6Bh EBh DTR Mode – 0Dh 3Dh BDh 6Dh EDh Supported Yes Yes Yes Yes Yes Yes Command Input DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 Address Input DQ0 DQ0 DQ0 DQ[1:0] DQ0 DQ[3:0] Data Output DQ1 DQ1 DQ[1:0] DQ[1:0] DQ[3:0] DQ[3:0] No Yes Yes Yes No No Command Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Address Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Data Output – DQ[1:0] DQ[1:0] DQ[1:0] – – Extended SPI Protocol Dual SPI Protocol Supported Quad SPI Protocol Supported No Yes No No Yes Yes Command Input – DQ[3:0] – – DQ[3:0] DQ[3:0] Address Input – DQ[3:0] – – DQ[3:0] DQ[3:0] 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Table 25: Command/Address/Data Lines for READ MEMORY Commands (Continued) Note 1 applies to entire table Command Name DUAL QUAD DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT FAST READ FAST READ FAST READ FAST READ READ FAST READ STR Mode 03h 0Bh 3Bh BBh DTR Mode – 0Dh 3Dh BDh 6Dh EDh Data Output – DQ[3:0] – – DQ[3:0] DQ[3:0] Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 6Bh EBh 1. Yes in the "Supported" row for each protocol indicates that the command in that column is supported; when supported, a command's functionality is identical for the entire column regardless of the protocol. For example, a FAST READ functions the same for all three protocols even though its data is input/output differently depending on the protocol. 2. FAST READ is similar to READ, but requires dummy clock cycles following the address bytes and can operate at a higher frequency (fC). 44 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations 4-Byte Address To execute 4-byte READ MEMORY commands, S# is driven LOW. The command code is input on DQn, followed by input on DQn of four address bytes. Each address bit is latched in during the rising edge of the clock. The addressed byte can be at any location, and the address automatically increments to the next address after each byte of data is shifted out; therefore, the entire memory can be read with a single command. The operation is terminated by driving S# HIGH at any time during data output. Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address Notes 1 and 2 apply to entire table Command Name (4-Byte Address) DUAL OUTPUT FAST READ DUAL INPUT/OUTPUT FAST READ QUAD OUTPUT FAST READ QUAD INPUT/OUTPUT FAST READ READ FAST READ STR Mode 03h/13h 0Bh/0Ch 3Bh/3Ch BBh/BCh 6Bh/6Ch EBh/ECh DTR Mode – 0Dh 3Dh BDh 6Dh EDh Extended SPI Protocol Supported Yes Yes Yes Yes Yes Yes Command Input DQ0 DQ0 DQ0 DQ0 DQ0 DQ0 Address Input DQ0 DQ0 DQ0 DQ[1:0] DQ0 DQ[3:0] Data Output DQ1 DQ1 DQ[1:0] DQ[1:0] DQ[3:0] DQ[3:0] No Yes Yes Yes No No Command Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Address Input – DQ[1:0] DQ[1:0] DQ[1:0] – – Data Output – DQ[1:0] DQ[1:0] DQ[1:0] – – No Yes No No Yes Yes Command Input – DQ[3:0] – – DQ[3:0] DQ[3:0] Address Input – DQ[3:0] – – DQ[3:0] DQ[3:0] Data Output – DQ[3:0] – – DQ[3:0] DQ[3:0] Dual SPI Protocol Supported Quad SPI Protocol Supported Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Yes in the "Supported" row for each protocol indicates that the command in that column is supported; when supported, a command's functionality is identical for the entire column regardless of the protocol. For example, a FAST READ functions the same for all three protocols even though its data is input/output differently depending on the protocol. 2. Command codes 13h, 0Ch, 3Ch, BCh, 6Ch, and ECh do not need to be set up in the addressing mode; they will work directly in 4-byte addressing mode. 3. A 4-BYTE FAST READ command is similar to 4-BYTE READ operation, but requires dummy clock cycles following the address bytes and can operate at a higher frequency (fC). 45 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 15: READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ[0] MSB A[MAX] DOUT High-Z DQ1 DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Don’t Care Note: 1. Cx = 7 + (A[MAX] + 1). READ MEMORY Operations Timing – Single Transfer Rate Figure 16: FAST READ Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Don’t Care Dummy cycles Note: 1. For extended protocol, Cx = 7 + (A[MAX] + 1). For dual protocol, Cx = 3 + (A[MAX] + 1)/2. For quad protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 46 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 17: DUAL OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB MSB DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT A[MIN] Command DQ0 A[MAX] High-Z DQ1 DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1). 2. Shown here is the DUAL OUTPUT FAST READ timing for the extended SPI protocol. The dual timing shown for the FAST READ command is the equivalent of the DUAL OUTPUT FAST READ timing for the dual SPI protocol. Figure 18: DUAL INPUT/OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB High-Z DQ1 A[MAX] DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT MSB Dummy cycles Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Cx = 7 + (A[MAX] + 1)/2. 2. Shown here is the DUAL INPUT/OUTPUT FAST READ timing for the extended SPI protocol. The dual timing shown for the FAST READ command is the equivalent of the DUAL INPUT/OUTPUT FAST READ timing for the dual SPI protocol. 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 19: QUAD OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB ‘1’ DQ3 LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT A[MAX] High-Z DQ[2:1] DOUT MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1). 2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol. The quad timing shown for the FAST READ command is the equivalent of the QUAD OUTPUT FAST READ timing for the quad SPI protocol. Figure 20: QUAD INPUT/OUTPUT FAST READ Command – STR Extended 0 7 8 Cx C LSB DQ0 Command DOUT LSB DOUT DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT A[MIN] MSB DQ[2:1] ‘1’ DQ3 A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Dummy cycles Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Cx = 7 + (A[MAX] + 1)/4. 48 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations 2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI protocol. The quad timing shown for the FAST READ command is the equivalent of the QUAD INPUT/OUTPUT FAST READ timing for the quad SPI protocol. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 49 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations READ MEMORY Operations Timing – Double Transfer Rate Figure 21: FAST READ Command – DTR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT DOUT MSB Don’t Care Dummy cycles Note: 1. For extended protocol, Cx = 7 + (A[MAX] + 1)/2. For dual protocol, Cx = 3 + (A[MAX] + 1)/4. For quad protocol, Cx = 1 + (A[MAX] + 1)/8. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 50 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 22: DUAL OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB DQ0 A[MIN] Command MSB DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT A[MAX] High-Z DQ1 MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1)/2. 2. Shown here is the DUAL OUTPUT FAST READ timing for the extended SPI protocol. The dual timing shown for the FAST READ command is the equivalent of the DUAL OUTPUT FAST READ timing for the dual SPI protocol. Figure 23: DUAL INPUT/OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 DOUT LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB High-Z DQ1 A[MAX] MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] LSB DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB Dummy cycles Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Cx = 7 + (A[MAX] + 1)/4. 2. Shown here is the DUAL INPUT/OUTPUT FAST READ timing for the extended SPI protocol. The dual timing shown for the FAST READ command is the equivalent of the DUAL INPUT/OUTPUT FAST READ timing for the dual SPI protocol. 51 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory READ MEMORY Operations Figure 24: QUAD OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB A[MIN] DOUT LSB DOUT DOUT DOUT High-Z DOUT DOUT DOUT DOUT ‘1’ DOUT DOUT DOUT DOUT Command DQ0 MSB A[MAX] DQ[2:1] DQ3 MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT DOUT MSB Dummy cycles Notes: 1. Cx = 7 + (A[MAX] + 1)/2. 2. Shown here is the QUAD OUTPUT FAST READ timing for the extended SPI protocol. The quad timing shown for the FAST READ command is the equivalent of the QUAD OUTPUT FAST READ timing for the quad SPI protocol. Figure 25: QUAD INPUT/OUTPUT FAST READ Command – DTR Extended 0 7 8 Cx C LSB DQ0 Command A[MIN] DOUT LSB DOUT DOUT DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT MSB DQ[2:1] ‘1’ DQ3 A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT DOUT MSB Dummy cycles Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Cx = 7 + (A[MAX] + 1)/8. 2. Shown here is the QUAD INPUT/OUTPUT FAST READ timing for the extended SPI protocol. The quad timing shown for the FAST READ command is the equivalent of the QUAD INPUT/OUTPUT FAST READ timing for the quad SPI protocol. 52 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations PROGRAM Operations PROGRAM commands are initiated by first executing the WRITE ENABLE command to set the write enable latch bit to 1. S# is then driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by input on DQ[n] of address bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tPP. If the bits of the least significant address, which is the starting address, are not all zero, all data transmitted beyond the end of the current page is programmed from the starting address of the same page. If the number of bytes sent to the device exceed the maximum page size, previously latched data is discarded and only the last maximum pagesize number of data bytes are guaranteed to be programmed correctly within the same page. If the number of bytes sent to the device is less than the maximum page size, they are correctly programmed at the specified addresses without any effect on the other bytes of the same page. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. An operation can be paused or resumed by the PROGRAM/ERASE SUSPEND or PROGRAM/ERASE RESUME command, respectively. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected sector, the command is not executed, the write enable latch bit remains set to 1, and flag status register bits 1 and 4 are set. Table 27: Data/Address Lines for PROGRAM Commands Note 1 applies to entire table Command Name PAGE PROGRAM Data In Address In Extended Dual Quad DQ0 DQ0 Yes Yes Yes DUAL INPUT FAST PROGRAM DQ[1:0] DQ0 Yes Yes No EXTENDED DUAL INPUT FAST PROGRAM DQ[1:0] DQ[1:0] Yes Yes No QUAD INPUT FAST PROGRAM DQ[3:0] DQ0 Yes No Yes EXTENDED QUAD INPUT FAST PROGRAM DQ[3:0] DQ[3:0] Yes No Yes Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Yes in the protocol columns indicates that the command is supported and has the same functionality and command sequence as other commands marked Yes. 53 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 26: PAGE PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). Note: For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. Figure 27: DUAL INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN A[MAX] High-Z DQ1 LSB DIN MSB Dual 0 3 4 Cx C LSB A[MIN] LSB DIN Command DQ[1:0] MSB Note: A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 54 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 28: EXTENDED DUAL INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB High-Z DQ1 A[MAX] Dual 0 3 MSB 4 Cx C A[MIN] LSB LSB Command DQ[1:0] MSB Note: A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/2. For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. Figure 29: QUAD INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB DQ0 MSB DQ[3:1] A[MIN] LSB Command DIN DIN DIN DIN DIN DIN DIN DIN A[MAX] High-Z MSB Quad 0 1 2 Cx C LSB MSB Note: A[MIN] LSB Command DQ[3:0] A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/4. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 55 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory PROGRAM Operations Figure 30: EXTENDED QUAD INPUT FAST PROGRAM Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] LSB DIN DIN DIN High-Z DIN DIN DIN ‘1’ DIN DIN DIN DIN DIN Command MSB DQ[2:1] DQ3 A[MAX] Quad 0 1 MSB 2 Cx C LSB MSB Note: A[MIN] LSB Command DQ[3:0] A[MAX] DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1)/4. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 56 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory WRITE Operations WRITE Operations WRITE ENABLE Command The WRITE ENABLE operation sets the write enable latch bit. To execute a WRITE ENABLE command, S# is driven LOW and held LOW until the eighth bit of the command code has been latched in, after which it must be driven HIGH. The command code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on DQ[3:0] for quad SPI protocol. The write enable latch bit must be set before every PROGRAM, ERASE, WRITE, ENTER 4-BYTE ADDRESS MODE, and EXIT 4-BYTE ADDRESS MODE command. If S# is not driven HIGH after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch remains cleared to its default setting of 0. WRITE DISABLE Command The WRITE DISABLE operation clears the write enable latch bit. To execute a WRITE DISABLE command, S# is driven LOW and held LOW until the eighth bit of the command code has been latched in, after which it must be driven HIGH. The command code is input on DQ0 for extended SPI protocol, on DQ[1:0] for dual SPI protocol, and on DQ[3:0] for quad SPI protocol. If S# is not driven HIGH after the command code has been latched in, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 57 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory WRITE Operations Figure 31: WRITE ENABLE and WRITE DISABLE Command Sequence Extended 0 1 2 3 4 5 6 7 C S# Command Bits DQ0 0 0 0 0 0 LSB 1 1 0 MSB High-Z DQ1 Dual 0 1 3 2 C S# Command Bits DQ0 DQ1 LSB 0 0 1 0 0 0 0 1 MSB Quad 0 1 C S# Command Bits LSB DQ0 0 0 DQ1 0 1 DQ2 0 1 DQ3 0 0 Don’t Care MSB Note: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Shown here is the WRITE ENABLE command code, which is 06h or 0000 0110 binary. The WRITE DISABLE command sequence is identical, except the WRITE DISABLE command code is 04h or 0000 0100 binary. 58 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations ERASE Operations SUBSECTOR ERASE Command To execute the SUBSECTOR ERASE command and set the selected subsector bits set to FFh, the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by address bytes; any address within the subsector is valid. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tSSE. The operation can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respectively. If the write enable latch bit is not set, the device ignores the SUBSECTOR ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1. The write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected subsector, the command is not executed. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. SECTOR ERASE Command To execute the SECTOR ERASE command (and set selected sector bits to FFh), the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by address bytes; any address within the sector is valid. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is selftimed, is initiated; its duration is tSE. The operation can be suspended and resumed by the PROGRAM/ERASE SUSPEND and PROGRAM/ERASE RESUME commands, respectively. If the write enable latch bit is not set, the device ignores the SECTOR ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1 and the write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. When a command is applied to a protected sector, the command is not executed. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 59 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Figure 32: SUBSECTOR and SECTOR ERASE Command Extended 0 7 8 Cx C LSB DQ0 A[MIN] Command MSB Dual A[MAX] 0 3 4 Cx C LSB DQ0[1:0] A[MIN] Command MSB Quad A[MAX] 0 1 2 Cx C LSB MSB Note: A[MIN] Command DQ0[3:0] A[MAX] 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. BULK ERASE Command To initiate the BULK ERASE command, the WRITE ENABLE command must be issued to set the write enable latch bit to 1. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0. When S# is driven HIGH, the operation, which is selftimed, is initiated; its duration is tBE. If the write enable latch bit is not set, the device ignores the SECTOR ERASE command and no error bits are set to indicate operation failure. When the operation is in progress, the write in progress bit is set to 1 and the write enable latch bit is cleared to 0, whether the operation is successful or not. The status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and erase error bit is set to 1. If S# is not driven HIGH, the command is not executed, the flag status register error bits are not set, and the write enable latch remains set to 1. The command is not executed if any sector is locked. Instead, the write enable latch bit remains set to 1, and flag status register bits 1 and 5 are set. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Figure 33: BULK ERASE Command Extended 0 7 C LSB Command DQ0 MSB Dual 0 3 C LSB Command DQ[1:0] MSB Quad 0 1 C LSB Command DQ[3:0] MSB PROGRAM/ERASE SUSPEND Command To initiate the PROGRAM/ERASE SUSPEND command, S# is driven LOW. The command code is input on DQ0. The operation is terminated by the PROGRAM/ERASE RESUME command. PROGRAM/ERASE SUSPEND command enables the memory controller to interrupt and suspend an array PROGRAM or ERASE operation within the program/erase latency. If a SUSPEND command is issued during a PROGRAM operation, then the flag status register bit 2 is set to 1. After erase/program latency time, the flag status register bit 7 is also set to 1, showing the device to be in a suspended state, waiting for any operation (see the Operations Allowed/Disallowed During Device States table). If a SUSPEND command is issued during an ERASE operation, then the flag status register bit 6 is set to 1. After erase/program latency time, the flag status register bit 7 is also set to 1, showing that device to be in a suspended state, waiting for any operation (see the Operations Allowed/Disallowed During Device States table). If the time remaining to complete the operation is less than the suspend latency, the device completes the operation and clears the flag status register bits 2 or 6, as applicable. Because the suspend state is volatile, if there is a power cycle, the suspend state information is lost and the flag status register powers up as 80h. During an ERASE SUSPEND operation, a PROGRAM or READ operation is possible in any sector except the one in a suspended state. Reading from a sector that is in a suspended state will output indeterminate data. The device ignores a PROGRAM command to a sector that is in an ERASE SUSPEND state; it also sets to 1 the flag status register bit 4: program failure/protection error, and leaves the write enable latch bit unchanged. The WRITE LOCK REGISTER, WRITE VOLATILE CONFIGURATION REGISTER, and WRITE ENHANCED VOLATILE CONFIGURATION REGISTER commands are 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 61 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations allowed during an ERASE SUSPEND state. When the ERASE operation resumes, it does not check the new lock status of the WRITE LOCK REGISTER command. During a PROGRAM SUSPEND operation, a READ operation is possible in any page except the one in a suspended state. Reading from a page that is in a suspended state will output indeterminate data. The commands allowed during a program suspend state include the WRITE VOLATILE CONFIGURATION REGISTER command and the WRITE ENHANCED VOLATILE CONFIGURATION REGISTER command. It is possible to nest a PROGRAM/ERASE SUSPEND operation inside a PROGRAM/ ERASE SUSPEND operation just once. Issue an ERASE command and suspend it. Then issue a PROGRAM command and suspend it also. With the two operations suspended, the next PROGRAM/ERASE RESUME command resumes the latter operation, and a second PROGRAM/ERASE RESUME command resumes the former (or first) operation. Table 28: Suspend Parameters Parameter Condition Typ Max Units Notes Erase to suspend Sector erase or erase resume to erase suspend 700 – µs 1 Program to suspend Program resume to program suspend 5 – µs 1 Subsector erase to suspend Subsector erase or subsector erase resume to erase suspend 50 – µs 1 Suspend latency Program 7 – µs 2 Suspend latency Subsector erase 15 – µs 2 Suspend latency Erase 15 – µs 3 Notes: 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 1. Timing is not internally controlled. 2. Any READ command accepted. 3. Any command except the following are accepted: SECTOR, SUBSECTOR, or BULK ERASE; WRITE STATUS REGISTER; WRITE NONVOLATILE CONFIGURATION REGISTER; and PROGRAM OTP. 62 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ERASE Operations Table 29: Operations Allowed/Disallowed During Device States Note 1 applies to entire table Standby Operation State Program or Erase State Subsector Erase Suspend or Program Suspend State Erase Suspend State Notes READ Yes No Yes Yes 2 PROGRAM Yes No No Yes/No 3 ERASE Yes No No No 4 WRITE Yes No No No 5 WRITE Yes No Yes Yes 6 READ Yes Yes Yes Yes 7 SUSPEND No Yes No No 8 Notes: 1. The device can be in only one state at a time. Depending on the state of the device, some operations are allowed (Yes) and others are not (No). For example, when the device is in the standby state, all operations except SUSPEND are allowed in any sector. For all device states except the erase suspend state, if an operation is allowed or disallowed in one sector, it is allowed or disallowed in all other sectors. In the erase suspend state, a PROGRAM operation is allowed in any sector except the one in which an ERASE operation has been suspended. 2. All READ operations except READ STATUS REGISTER and READ FLAG REGISTER. When issued to a sector or subsector that is simultaneously in an erase suspend state, the READ operation is accepted, but the data output is not guaranteed until the erase has completed. 3. All PROGRAM operations except PROGRAM OTP. In the erase suspend state, a PROGRAM operation is allowed in any sector (Yes) except the sector (No) in which an ERASE operation has been suspended. 4. Applies to the SECTOR ERASE or SUBSECTOR ERASE operation. 5. Applies to the following operations: WRITE STATUS REGISTER, WRITE NONVOLATILE CONFIGURATION REGISTER, PROGRAM OTP, and BULK ERASE. 6. Applies to the WRITE ENABLE/DISABLE, CLEAR FLAG STATUS REGISTER, WRITE EXTENDED ADDRESS REGISTER, WRITE LOCK REGISTER, ENTER or EXIT 4-BYTE ADDRESS MODE, WRITE VOLATILE or ENHANCED VOLATILE CONFIGURATION REGISTER operation. 7. Applies to the READ STATUS REGISTER or READ FLAG STATUS REGISTER operation. 8. Applies to the PROGRAM SUSPEND or ERASE SUSPEND operation. PROGRAM/ERASE RESUME Command To initiate the PROGRAM/ERASE RESUME command, S# is driven LOW. The command code is input on DQ0. The operation is terminated by driving S# HIGH. When this command is executed, the status register write in progress bit is set to 1, and the flag status register program erase controller bit is set to 0. This command is ignored if the device is not in a suspended state. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory RESET Operations RESET Operations Table 30: Reset Command Set Command Command Code (Binary) Command Code (Hex) Address Bytes RESET ENABLE 0110 0110 66 0 RESET MEMORY 1001 1001 99 0 RESET ENABLE and RESET MEMORY Command To reset the device, the RESET ENABLE command must be followed by the RESET MEMORY command. To execute each command, S# is driven LOW. The command code is input on DQ0. A minimum de-selection time of tSHSL2 must come between the RESET ENABLE and RESET MEMORY commands or a reset is not guaranteed. When these two commands are executed and S# is driven HIGH, the device enters a power-on reset condition. A time of tSHSL3 is required before the device can be re-selected by driving S# LOW. It is recommended that the device exit XIP mode before executing these two commands to initiate a reset. If a reset is initiated while a WRITE, PROGRAM, or ERASE operation is in progress or suspended, the operation is aborted and data may be corrupted. Figure 34: RESET ENABLE and RESET MEMORY Command 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 C Reset enable Reset memory S# DQ0 Note: 1. The number of lines and rate for transmission varies with extended, dual, or quad SPI. RESET Conditions All volatile lock bits, the volatile configuration register, the enhanced volatile configuration register, and the extended address register are reset to the power-on reset default condition. The power-on reset condition depends on settings in the nonvolatile configuration register. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 64 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations ONE TIME PROGRAMMABLE Operations READ OTP ARRAY Command To initiate a READ OTP ARRAY command, S# is driven LOW. The command code is input on DQ0, followed by address bytes and dummy clock cycles. Each address bit is latched in during the rising edge of C. Data is shifted out on DQ1, beginning from the specified address and at a maximum frequency of fC (MAX) on the falling edge of the clock. The address increments automatically to the next address after each byte of data is shifted out. There is no rollover mechanism; therefore, if read continuously, after location 0x64, the device continues to output data at location 0x64. The operation is terminated by driving S# HIGH at any time during data output. Figure 35: READ OTP Command Extended 0 7 8 Cx C LSB A[MIN] Command DQ0 MSB A[MAX] DQ1 DOUT High-Z DOUT DOUT DOUT DOUT DOUT DOUT LSB DOUT DOUT DOUT DOUT LSB DOUT DOUT MSB Dummy cycles Dual 0 3 4 Cx C LSB A[MIN] DOUT Command DQ[1:0] MSB A[MAX] MSB Dummy cycles Quad 0 1 2 Cx C LSB A[MIN] DOUT Command DQ[3:0] MSB A[MAX] LSB DOUT DOUT MSB Don’t Care Dummy cycles Note: 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. PROGRAM OTP ARRAY Command To initiate the PROGRAM OTP ARRAY command, the WRITE ENABLE command must be issued to set the write enable latch bit to 1; otherwise, the PROGRAM OTP ARRAY command is ignored and flag status register bits are not set. S# is driven LOW and held LOW until the eighth bit of the last data byte has been latched in, after which it must be driven HIGH. The command code is input on DQ0, followed by address bytes and at least one data byte. Each address bit is latched in during the rising edge of the clock. When S# is driven HIGH, the operation, which is self-timed, is initiated; its duration is tPOTP. There is no rollover mechanism; therefore, after a maximum of 65 bytes are latched in and subsequent bytes are discarded. PROGRAM OTP ARRAY programs, at most, 64 bytes to the OTP memory area and one OTP control byte. When the operation is in progress, the write in progress bit is set to 1. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 65 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations The write enable latch bit is cleared to 0, whether the operation is successful or not, and the status register and flag status register can be polled for the operation status. When the operation completes, the write in progress bit is cleared to 0. If the operation times out, the write enable latch bit is reset and the program fail bit is set to 1. If S# is not driven HIGH, the command is not executed, flag status register error bits are not set, and the write enable latch remains set to 1. The OTP control byte (byte 64) is used to permanently lock the OTP memory array. Table 31: OTP Control Byte (Byte 64) Bit Name 0 OTP control byte 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN Settings Description 0 = Locked 1 = Unlocked (Default) Used to permanently lock the 64B OTP array. When bit 0 = 1, the 64B OTP array can be programmed. When bit 0 = 0, the 64B OTP array is read only. Once bit 0 has been programmed to 0, it can no longer be changed to 1. PROGRAM OTP ARRAY is ignored, write enable latch bit remains set, and flag status register bits 1 and 4 are set. 66 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ONE TIME PROGRAMMABLE Operations Figure 36: PROGRAM OTP Command Extended 0 7 8 Cx C LSB A[MIN] LSB Command DQ0 MSB Dual A[MAX] 0 3 DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN MSB 4 Cx C LSB A[MIN] LSB Command DQ[1:0] MSB Quad A[MAX] 0 1 DIN MSB 2 Cx C LSB A[MIN] LSB Command DQ[3:0] MSB A[MAX] Note: DIN MSB 1. For extended SPI protocol, Cx = 7 + (A[MAX] + 1). For dual SPI protocol, Cx = 3 + (A[MAX] + 1)/2. For quad SPI protocol, Cx = 1 + (A[MAX] + 1)/4. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 67 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ADDRESS MODE Operations – Enter and Exit 4-Byte Address Mode ENTER or EXIT 4-BYTE ADDRESS MODE Command Both ENTER 4-BYTE ADDRESS MODE and EXIT 4-BYTE ADDRESS MODE commands share the same requirements. To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. Note: The WRITE ENABLE command is not necessary for line items that enable the additional RESET# pin. S# must be driven LOW. The command must be input on DQn. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. The default address mode is three bytes, and the device returns to the default upon exiting the 4-byte address mode. ENTER or EXIT QUAD Command The ENTER or EXIT QUAD command is only available for line items that enable the additional RESET# pin. To initiate this command, S# must be driven LOW, and the command must be input on DQn. The effect of the command is immediate. Note: The WRITE ENABLE command must not be executed before this command. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 68 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory XIP Mode XIP Mode Execute-in-place (XIP) mode allows the memory to be read by sending an address to the device and then receiving the data on one, two, or four pins in parallel, depending on the customer requirements. XIP mode offers maximum flexibility to the application, saves instruction overhead, and reduces random access time. Activate or Terminate XIP Using Volatile Configuration Register Applications that boot in SPI and must switch to XIP use the volatile configuration register. XIP provides faster memory READ operations by requiring only an address to execute, rather than a command code and an address. To activate XIP requires two steps. First, enable XIP by setting volatile configuration register bit 3 to 0. Next, drive the XIP confirmation bit to 0 during the next FAST READ operation. XIP is then active. Once in XIP, any command that occurs after S# is toggled requires only address bits to execute; a command code is not necessary, and device operations use the SPI protocol that is enabled. XIP is terminated by driving the XIP confirmation bit to 1. The device automatically resets volatile configuration register bit 3 to 1. Note: For devices with basic XIP, indicated by a part number feature set digit of 2 or 4, it is not necessary to set the volatile configuration register bit 3 to 0 to enable XIP. Instead, it is enabled by setting the XIP confirmation bit to 0 during the first dummy clock cycle after any FAST READ command. Activate or Terminate XIP Using Nonvolatile Configuration Register Applications that must boot directly in XIP use the nonvolatile configuration register. To enable a device to power-up in XIP using the nonvolatile configuration register, set nonvolatile configuration register bits [11:9]. Settings vary according to protocol, as explained in the Nonvolatile Configuration Register section. Because the device boots directly in XIP, the confirmation bit is already set to 0, and after the next power cycle, XIP is active. Once in XIP, a command code is unnecessary, and device operations use the SPI protocol currently enabled. XIP is terminated by driving the XIP confirmation bit to 1. 09005aef846a804a n25q_256mb_1_8V_65nm.pdf - Rev. O 11/16 EN 69 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 1.8V, 256Mb: Multiple I/O Serial Flash Memory XIP Mode Figure 37: XIP Mode Directly After Power-On Mode 3 C 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Mode 0 tVSI VCC (