NAND04G-B2D
NAND08G-BxC
4-Gbit, 8-Gbit, 2112-byte/1056-word page
multiplane architecture, 1.8 V or 3 V, SLC NAND flash memories
Features
■
High density NAND flash memory
– Up to 8 Gbits of memory array
– Cost-effective solution for mass storage
applications
■
NAND interface
– x8 or x16 bus width
– Multiplexed address/data
■
Supply voltage: 1.8 V or 3 V device
■
Page size
– x8 device: (2048 + 64 spare) bytes
– x16 device: (1024 + 32 spare) words
■
Block size
– x8 device: (128K + 4 K spare) bytes
– x16 device: (64K + 2K spare) words
■
Multiplane architecture
– Array split into two independent planes
– Program/erase operations can be
performed on both planes at the same time
■
■
Page read/program
– Random access: 25 µs (max)
– Sequential access: 25 ns (min)
– Page program time: 200 µs (typ)
– Multiplane page program time (2 pages):
200 µs (typ)
Copy back program with automatic error
detection code (EDC)
TSOP48 12 x 20 mm (N)
LGA
ULGA52 12 x 17 x 0.65 mm (ZL)
r
■
Security features
– OTP area
– Serial number (unique ID)
– Non-volatile protection option
■
Data protection: hardware program/erase
disabled during power transitions
■
Data integrity
– 100,000 program/erase cycles (with ECC)
– 10 years data retention
■
RoHS compliant packages
Table 1.
Device summary
Reference
Part number
NAND04GR3B2D
NAND04G-B2D
NAND04GW3B2D
■
Cache read mode
NAND04GR4B2D(1)
■
Fast block erase
– Block erase time: 1.5 ms (typ)
– Multiblock erase time (2 blocks):
1.5 ms (typ)
NAND04GW4B2D(1)
NAND08GR3B2C,
NAND08GW3B2C
NAND08G-BxC
NAND08GR4B2C(1)
■
Status register
■
Electronic signature
NAND08GR3B4C
■
Chip enable ‘don’t care’
NAND08GW3B4C
■
ONFI 1.0 compliant command set
February 2010
NAND08GW4B2C(1)
1. x16 organization only available for MCP products.
Rev 9
1/72
www.numonyx.com
1
Contents
NAND04G-B2D, NAND08G-BxC
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
3.1
Inputs/outputs (I/O0-I/O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
Inputs/outputs (I/O8-I/O15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3
Address latch enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4
Command latch enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.5
Chip enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.6
Read enable (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7
Write enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8
Write protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9
Ready/Busy (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.10
VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.1
Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2
Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.3
Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.4
Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.5
Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.6
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5
Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6
Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1
6.2
2/72
Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.1
Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.2
Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
NAND04G-B2D, NAND08G-BxC
6.3
Contents
Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.1
Sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3.2
Random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4
Multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.5
Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.6
Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.7
Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.8
Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6.9
Error detection code (EDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.10
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11
Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.1
Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.11.2
P/E/R controller and cache ready/busy bit (SR6) . . . . . . . . . . . . . . . . . 37
6.11.3
P/E/R controller bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.11.4
Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.11.5
SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.12
Read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.13
Read EDC status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.14
Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.15
Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.16
Read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
7
Concurrent operations and extended read status . . . . . . . . . . . . . . . . 45
8
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9
Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10
9.1
Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.2
NAND flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.4
Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.5
Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 49
3/72
Contents
NAND04G-B2D, NAND08G-BxC
11
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
12
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
12.1
Ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 65
12.2
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
13
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
14
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4/72
NAND04G-B2D, NAND08G-BxC
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Signals names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address insertion (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Address insertion (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address definition (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Address definition (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Address definition for EDC units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Address definition for EDC units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
EDC status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Read ONFI signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Extended Read Status Register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Program erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 49
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
DC characteristics (1.8 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
DC characteristics (3 V devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 67
ULGA52 12 x 17 x 0.65 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . 68
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
5/72
List of figures
NAND04G-B2D, NAND08G-BxC
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
6/72
Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TSOP48 connections for NAND04G-B2D and NAND08G-BxC . . . . . . . . . . . . . . . . . . . . . 11
ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices . . . . . . . . . . . . . . 12
ULGA52 connections for the NAND08G-B4C devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Cache read (random) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Multiplane page program waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Copy back program (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Copy back program (with readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Page organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Equivalent testing circuit for AC characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 52
Command latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Address latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Data input latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Sequential data output after read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Sequential data output after read AC waveforms (EDO mode) . . . . . . . . . . . . . . . . . . . . . 57
Read status register or read EDC status register AC waveform. . . . . . . . . . . . . . . . . . . . . 57
Read status enhanced waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Read electronic signature AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Read ONFI signature waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Page read operation AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Page program AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Block erase AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Reset AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Read parameter page waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Ready/busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Ready/busy load circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Resistor value versus waveform timings for ready/busy signal . . . . . . . . . . . . . . . . . . . . . 66
Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 67
ULGA52 12 x 17 x 0.65 mm, 1 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . 68
NAND04G-B2D, NAND08G-BxC
1
Description
Description
The NAND04G-B2D and NAND08G-BxC are part of the NAND flash 2112-byte/1056-word
page family of non-volatile flash memories. They use NAND cell technology have a density
of 4 Gbits and 8 Gbits, respectively.
The NAND04G-B2D memory array is split into 2 planes of 2048 blocks each. This
multiplane architecture makes it possible to program 2 pages at a time (one in each plane),
or to erase 2 blocks at a time (one in each plane). This feature reduces the average program
and erase times by 50%.
The NAND08G-BxC is a stacked device that combines two NAND04G-B2D dice, both of
which feature a multiplane architecture.
In the NAND08G-B2C devices, only one of the memory components can be enabled at a
time, therefore, operations can only be performed on one of the memory components at any
one time.
The devices operate from a 1.8 V or 3 V voltage supply. Depending on whether the device
has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or 1056 words
(1024 + 32 spare), respectively.
The address lines are multiplexed with the data input/output signals on a multiplexed x8
input/output bus. This interface reduces the pin count and makes it possible to migrate to
other densities without changing the footprint.
Each block can be programmed and erased up to 100,000 cycles with ECC (error correction
code) on. To extend the lifetime of NAND flash devices, the implementation of an ECC is
mandatory.
A write protect pin is available to provide hardware protection against program and erase
operations.
The devices feature an open-drain ready/busy output that identifies if the P/E/R
(program/erase/read) controller is currently active. The use of an open-drain output allows
the ready/busy pins from several memories to connect to a single pull-up resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a page program operation fails, the data can be programmed in another page
without having to resend the data to be programmed. An embedded error detection code
(EDC) is automatically executed after each copy back operation: 1 error bit can be detected
for every 528 bytes. With this feature it is no longer necessary to use an external ECC to
detect copy back operation errors.
The devices have a cache read feature that improves the read throughput for large files.
During cache reading, the device loads the data in a cache register while the previous data
is transferred to the I/O buffers to be read.
The devices have the chip enable ‘don’t care’ feature, which allows code to be directly
downloaded by a microcontroller. This is possible because chip enable transitions during the
latency time do not stop the read operation.
Both the NAND04G-B2D and NAND08G-BxC support the ONFI 1.0 specification.
The devices are available in the following packages:
●
TSOP48 (12 x 20 mm)
●
ULGA52 (12 x 17 x 0.65 mm)
7/72
Description
NAND04G-B2D, NAND08G-BxC
and come with three security features:
●
OTP (one time programmable) area, which is a restricted access area where sensitive
data/code can be stored permanently
●
Serial number (unique identifier), which allows the device to be uniquely identified
●
Non-volatile protection to lock sensible data permanently.
These security features are subject to an NDA (non-disclosure agreement) and are,
therefore, not described in the datasheet. For more details about them, contact your nearest
Numonyx sales office.
For information on how to order these options, refer to Table 34: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
Table 2: Product description lists the part numbers and other information for all the devices
available in the family.
Table 2.
Product description
Timings
Part number
Bus
Density
width
Page
size
Block
size
2048+64
bytes
128K+
4K bytes
Memory
array
NAND04GR3B2D
x8
NAND04GW3B2D
64 pages
x 4096
blocks
4-Gbit
NAND04GR4B2D
x16
1024+ 32
words
64K +
2K words
NAND04GW4B2D
NAND08GR3B2C
x8
2048+64
bytes
128K +
4K bytes
NAND08GW3B2C
NAND08GR4B2C
8-Gbit
x16
1024+ 32
words
64K +
2K words
NAND08GW4B2C
NAND08GR3B4C
x8
2048+64
bytes
NAND08GW3B4C
64 pages
x 8192
blocks
128K +
4K bytes
x8
1. x16 organization is only available for MCP products.
2. The NAND08G-BxC is composed of two 4-Gbit dice.
8/72
Operating
voltage
Sequential
Random
access
access
time (min) time (max)
Page
Program
(typ)
Block
Erase
(typ)
Package
1.7 to
1.95 V
45 ns
ULGA52
2.7 to
3.6 V
25 ns
TSOP48
ULGA52
1.7 to
1.95 V
45 ns
2.7 to
3.6 V
25 ns
1.7 to
1.95 V
45 ns
ULGA52(2)
2.7 to
3.6 V
25 ns
TSOP48
ULGA52(2)
1.7 to
1.95 V
45 ns
2.7 to
3.6 V
25 ns
1.7 to
1.95 V
45 ns
2.7 to
3.6 V
25 ns
25 µs
200 µs
1.5 ms
(1)
25 µs
200 µs
1.5 ms
(1)(2)
ULGA52(2)
NAND04G-B2D, NAND08G-BxC
Figure 1.
Description
Logic block diagram
AL
CL
W
E
P/E/R Controller,
High Voltage
Generator
Command
Interface
Logic
X Decoder
Address
Register/Counter
NAND Flash
Memory Array
WP
Page Buffer
R
Cache Register
Command Register
Y Decoder
I/O Buffers & Latches
RB
I/O0-I/O7 (x8/x16)
I/O8-I/O15 (x16)
AI13166b
Figure 2.
Logic diagram
VDD
I/O0-I/O7 (x8/x16)
E
I/O8-I/O15 (x16)
R
W
NAND FLASH
AL
RB
CL
WP
VSS
AI13167b
9/72
Description
Table 3.
NAND04G-B2D, NAND08G-BxC
Signals names
Signal
Function
Direction
I/O0-7
Data input/outputs, address inputs, or command inputs (x8/x16 devices)
Input/output
I/O8-15
Data input/outputs (x16 devices)
Input/output
10/72
AL
Address Latch Enable
Input
CL
Command Latch Enable
Input
E
Chip Enable
Input
R
Read Enable
Input
RB
Ready/Busy (open-drain output)
W
Write Enable
Input
WP
Write Protect
Input
VDD
Supply voltage
VSS
Ground
NC
Not connected internally
–
DU
Do not use
–
Output
Power supply
Ground
NAND04G-B2D, NAND08G-BxC
Figure 3.
Description
TSOP48 connections for NAND04G-B2D and NAND08G-BxC
NC
NC
NC
NC
NC
NC
RB
R
E
1
48
NC
NC
VDD
VSS
NC
NC
CL
AL
W
WP
NC
NC
NC
NC
NC
12
37
NAND FLASH
13
36
24
25
NC
NC
NC
NC
I/O7
I/O6
I/O5
I/O4
NC
NC
NC
VDD
VSS
NC
NC
NC
I/O3
I/O2
I/O1
I/O0
NC
NC
NC
NC
AI13168b
11/72
Description
NAND04G-B2D, NAND08G-BxC
Figure 4.
ULGA52 connections for NAND04G-B2D and NAND08G-B2C devices
0
OA
1
2
5
NC
CL
E
VSS
NC
NC
NC
NC
I/O2
I/O6
NC
NC
VSS
E
G
NC
H
NC
NC
K
L
NC
VDD
NC
J
NC
I/O4
D
F
I/O5
VSS
NC
NC
I/O7
I/O3
NC
NC
VSS
I/O0
B
C
R
RB
I/O1
NC
A
NC
NC
W
NC
OF
8
NC
NC
WP
OE
7
VDD
NC
NC
OD
6
NC
AL
OC
4
NC
NC
OB
3
NC
M
N
NC
NC
AI13634b
12/72
NAND04G-B2D, NAND08G-BxC
Figure 5.
ULGA52 connections for the NAND08G-B4C devices
0
OA
Description
1
2
5
NC
CL1
E1
VSS
NC
AL2
NC
G
H
VSS
NC
I/O41
I/O42
K
L
I/O52
VDD
I/O32
J
I/O62
I/O51
VSS
NC
NC
I/O61
I/O31
I/O22
F
I/O71
I/O21
D
E
I/O72
WP2
I/O11
NC
NC
RB2
RB1
B
C
R1
VSS
I/O01
I/O12
A
NC
R2
W1
I/O02
OF
8
NC
E2
WP1
OE
7
VDD
CL2
W2
OD
6
NC
AL1
OC
4
NC
NC
OB
3
NC
M
N
NC
NC
AI13634
13/72
Memory array organization
2
NAND04G-B2D, NAND08G-BxC
Memory array organization
The memory array of the devices is made up of NAND structures where 32 cells are
connected in series. It is organized into blocks where each block contains 64 pages. The
array is split into two areas, the main area, and the spare area. The main area of the array is
used to store data, and the spare area typically stores error correction codes, software flags,
or bad block identification.
In x8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes.
In x16 devices, the pages are split into a 1024-word main area and a spare area of
32 words. Refer to Figure 6: Memory array organization.
Bad blocks
In x8 devices, the NAND flash 2112-byte/1056-word page devices may contain bad blocks,
which are blocks that contain one or more invalid bits whose reliability is not guaranteed.
Additional bad blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 9.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks. The values shown include both the bad
blocks that are present when the device is shipped and the bad blocks that could develop
later on.
These blocks need to be managed using bad blocks management, block replacement, or
error correction codes (refer to Section 9: Software algorithms).
Table 4.
Valid blocks
Density of device
Min
Max
4 Gbits
4016
4096
8032
8192
8
Gbits(1)
1. The NAND08G-BxC devices are composed of two 4-Gbit dice. The minimum number of valid blocks is
4016 for each die.
14/72
NAND04G-B2D, NAND08G-BxC
Figure 6.
Memory array organization
Memory array organization
x 8 bus width
Plane = 2048 blocks, block = 64 pages, page = 2112 bytes (2048 + 64)
First plane
Second plane
a
re
a
Sp
are
a
are
re
pa
S
Main area
Main area
2048 bytes
2048 bytes
Block
Page
8 bits
64
bytes
Page buffer, 2112 bytes
Page buffer, 2112 bytes
64
bytes
2048 bytes
64
bytes
2048 bytes
64
bytes
8 bits
2-page buffer, 2 x 2112 bytes
x 16 bus width
Plane = 2048 blocks, block = 64 pages, page = 1056 words (1024 + 32)
Second plane
First plane
a
are
are
Sp
a
re
a
Sp
Main area
Main area
1024 words
1024 words
are
Block
Page
16 bits
32
words
Page buffer, 1056 bytes
1024 words
32
words
32
words
Page buffer, 1056 bytes
1024 words
32
words
16 bits
2-page buffer, 2 x 1056 bytes
AI13170C
15/72
Signals description
3
NAND04G-B2D, NAND08G-BxC
Signals description
See Figure 2: Logic diagram and Table 3: Signals names for a brief overview of the signals
connected to this device.
3.1
Inputs/outputs (I/O0-I/O7)
Input/outputs 0 to 7 input the selected address, output the data during a read operation, or
input a command or data during a write operation. The inputs are latched on the rising edge
of Write Enable. I/O0-I/O7 are left floating when the device is deselected or the outputs are
disabled.
3.2
Inputs/outputs (I/O8-I/O15)
Input/outputs 8 to 15 are only available in x16 devices. They output the data during a read
operation or input data during a write operation. Command and address inputs only require
I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable. I/O8-I/O15 are left floating when
the device is deselected or the outputs are disabled.
3.3
Address latch enable (AL)
The address latch enable activates the latching of the address inputs in the command
interface. When AL is High, the inputs are latched on the rising edge of Write Enable.
3.4
Command latch enable (CL)
The command latch enable activates the latching of the command inputs in the command
interface. When CL is High, the inputs are latched on the rising edge of Write Enable.
3.5
Chip enable (E)
The Chip Enable input, E, activates the memory control logic, input buffers, decoders and
sense amplifiers. When Chip Enable is Low, VIL, the device is selected. If Chip Enable goes
High, VIH, while the device is busy, the device remains selected and does not go into
standby mode.
3.6
Read enable (R)
The Read Enable pin, R, controls the sequential data output during read operations. Data is
valid tRLQV after the falling edge of R. The falling edge of R also increments the internal
column address counter by one.
16/72
NAND04G-B2D, NAND08G-BxC
3.7
Signals description
Write enable (W)
The Write Enable input, W, controls writing to the command interface, input address and
data latches. Both addresses and data are latched on the rising edge of Write Enable.
During power-up and power-down a recovery time of 10 µs (min) is required before the
command interface is ready to accept a command. It is recommended to keep Write Enable
High during the recovery time.
3.8
Write protect (WP)
The Write Protect pin is an input that gives a hardware protection against unwanted program
or erase operations. When Write Protect is Low, VIL, the device does not accept any
program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL, during power-up and power-down.
3.9
Ready/Busy (RB)
The Ready/Busy output, RB, is an open-drain output that identifies if the P/E/R controller is
currently active.
When Ready/Busy is Low, VOL, a read, program or erase operation is in progress. When the
operation completes, Ready/Busy goes High, VOH.
The use of an open-drain output allows the ready/busy pins from several memories to be
connected to a single pull-up resistor. A Low then indicates that one or more of the
memories is busy.
During power-up and power-down a minimum recovery time of 10 µs is required before the
command interface is ready to accept a command. During this period the RB signal is Low,
VOL.
Refer to Section 12.1: Ready/busy signal electrical characteristics for details on how to
calculate the value of the pull-up resistor.
3.10
VDD supply voltage
VDD provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase).
An internal voltage detector disables all functions whenever VDD is below VLKO (see
Table 29) to protect the device from any involuntary program/erase during power-transitions.
Each device in a system should have VDD decoupled with a 0.1 µF capacitor. The PCB track
widths should be sufficient to carry the required program and erase currents.
3.11
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
17/72
Bus operations
4
NAND04G-B2D, NAND08G-BxC
Bus operations
There are six standard bus operations that control the memory, as described in this section.
SeeTable 5: Bus operations for a summary of these operations.
Typically, glitches of less than 5 ns on Chip Enable, Write Enable, and Read Enable are
ignored by the memory and do not affect bus operations.
4.1
Command input
Command input bus operations give commands to the memory.
Commands are accepted when Chip Enable is Low, Command Latch Enable is High,
Address Latch Enable is Low, and Read Enable is High. They are latched on the rising edge
of the Write Enable signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 24 and Table 30 for details of the timings requirements.
4.2
Address input
Address input bus operations input the memory addresses. Five bus cycles are required to
input the addresses (refer to Table 6: Address insertion (x8 devices) and Table 7: Address
insertion (x16 devices)).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low, and Read Enable is High. They are latched on the rising
edge of the Write Enable signal.
Only I/O0 to I/O7 are used to input addresses.
See Figure 25 and Table 30 for details of the timings requirements.
4.3
Data input
Data input bus operations input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low, and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 26 and Table 30 and Table 31 for details of the timings requirements.
4.4
Data output
Data output bus operations read the data in the memory array, the status register, the
electronic signature, and the unique identifier.
Data is output when Chip Enable is Low, Write Enable is High, Address Latch Enable is Low,
and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
18/72
NAND04G-B2D, NAND08G-BxC
Bus operations
If the Read Enable pulse frequency is lower then 33 MHz (tRLRL higher than 30 ns), the
output data is latched on the rising edge of Read Enable signal (see Figure 27).
For higher frequencies (tRLRL lower than 30 ns), the EDO (extended data out) mode must be
used. In this mode, data output bus operations are valid on the input/output bus for a time of
tRLQX after the falling edge of Read Enable signal (see Figure 28).
See Table 31 for details on the timings requirements.
4.5
Write protect
Write protect bus operations protect the memory against program or erase operations.
When the Write Protect signal is Low the device does not accept program or erase
operations, and, therefore, the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection, even during power-up.
4.6
Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled, and power consumption is reduced.
Table 5.
Bus operations
Bus operation
E
AL
CL
R
W
WP
I/O0 - I/O7
I/O8 - I/O15(1)
Command input
VIL
VIL
VIH
VIH
Rising
X(2)
Command
X
Address input
VIL
VIH
VIL
VIH
Rising
X
Address
X
Data input
VIL
VIL
VIL
VIH
Rising
VIH
Data input
Data input
Data output
VIL
VIL
VIL
Falling
VIH
X
Data output
Data output
Write protect
X
X
X
X
X
VIL
X
X
Standby
VIH
X
X
X
X
VIL/VDD
X
X
1. Only for x16 devices.
2. WP must be VIH when issuing a Program or Erase command.
Table 6.
Address insertion (x8 devices)
Bus
cycle(1)
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
2nd
VIL
VIL
VIL
VIL
A11
A10
A9
A8
3rd
A19
A18
A17
A16
A15
A14
A13
A12
th
4
A27
A26
A25
A24
A23
A22
A21
A20
5th
VIL
VIL
VIL
VIL
VIL
A30(2)
A29
A28
1. Any additional address input cycles are ignored.
2. A30 is only valid for the NAND08G-BxC devices.
19/72
Bus operations
NAND04G-B2D, NAND08G-BxC
Table 7.
Address insertion (x16 devices)
Bus
cycle(1)
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1st
A7
A6
A5
A4
A3
A2
A1
A0
nd
VIL
VIL
VIL
VIL
VIL
A10
A9
A8
rd
A18
A17
A16
A15
A14
A13
A12
A11
th
4
A26
A25
A24
A23
A22
A21
A20
A19
5th
VIL
VIL
VIL
VIL
VIL
A29(2)
A28
A27
2
3
1. Any additional address input cycles are ignored.
2. A29 is only valid for the NAND08G-BxC devices.
Table 8.
Table 9.
20/72
Address definition (x8 devices)
Address
Definition
A0 - A11
Column address
A12 - A17
Page address
A18 - A29
Block address(NAND04G-B2D)
A18 - A30
Block address (NAND08G-BxC)
A18 = 0
First plane
A18 = 1
Second plane
Address definition (x16 devices)
Address
Definition
A0 - A10
Column address
A11 - A16
Page address
A17 - A28
Block address (NAND04G-B2D)
A17 - A29
Block address (NAND08G-BxC)
A17 = 0
First plane
A17 = 1
Second plane
NAND04G-B2D, NAND08G-BxC
5
Command set
Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the command Latch Enable signal is High. Device operations are selected by writing specific
commands to the command register. The two-step command sequences for program and
erase operations are imposed to maximize data security.
Table 10 summarizes the commands.
Table 10.
Commands
Bus write operations
Command(1)
Commands
accepted
during busy
1st cycle
2nd cycle
3rd cycle
4th cycle
Read
00h
30h
–
–
Random Data Output
05h
E0h
–
–
Cache Read (sequential)
31h
–
–
–
Enhanced Cache Read (random)
00h
31h
–
–
Exit Cache Read
3Fh
–
–
–
Page Program
(sequential input default)
80h
10h
–
–
Random Data Input
85h
–
–
–
80h
11h
81h
10h
Multiplane Page Program
80h
11h
80h
10h
Copy Back Read
00h
35h
–
–
85h
10h
–
–
85h
11h
81h
10h
Multiplane Copy Back Program
85h
11h
85h
10h
Block Erase
60h
D0h
–
–
60h
60h
D0h
–
Multiplane Block Erase
60h
D1h
60h
D0h
Reset
FFh
–
–
–
Read Electronic Signature
90h
–
–
–
Read Status Register
70h
–
–
–
Yes
Read Status Enhanced
78h
–
–
–
Yes
Read Parameter Page
ECh
–
–
–
Read EDC Status Register
7Bh
–
–
–
Multiplane Page
Program(3)
Copy Back Program
Multiplane Copy Back
Multiplane Block
Program(3)
Erase(3)
Yes(2)
Yes
1. Commands in bold are referring to ONFI 1.0 specifications.
2. Only during cache read busy.
3. Command maintained for backward compatibility.
21/72
Device operations
6
NAND04G-B2D, NAND08G-BxC
Device operations
This section provides details of the device operations.
6.1
Read memory array
At power-up the device defaults to read mode. To enter read mode from another mode, the
Read command must be issued (see Table 10: Commands).
6.1.1
Random read
Each time the Read command is issued, the first read is random read.
6.1.2
Page read
After the first random read access, the page data (2112 bytes or 1056 words) are
transferred to the page buffer in a time of tWHBH (see Table 31). Once the transfer is
complete, the Ready/Busy signal goes High. The data can then be read sequentially (from
selected column address to last column address) by pulsing the Read Enable signal.
The device can output random data in a page, instead of consecutive sequential data, by
issuing a Random Data Output command. The Random Data Output command can be used
to skip some data during a sequential data output.
The sequential operation can be resumed by changing the column address of the next data
to be output, to the address which follows the Random Data Output command. The Random
Data Output command can be issued as many times as required within a page.
The Random Data Output command is not accepted during cache read operations.
22/72
NAND04G-B2D, NAND08G-BxC
Figure 7.
Device operations
Read operations
CL
E
W
AL
R
tBLBH1
RB
I/O
00h
Command
Code
Address Input
30h
Command
Code
Data Output (sequentially)
Busy
ai12469
23/72
Device operations
Figure 8.
NAND04G-B2D, NAND08G-BxC
Random data output during sequential data output
tBLBH1
(Read Busy time)
RB
Busy
tRHWL
W
R
I/O
00h
Address
Inputs
30h
Data Output
Cmd
Code
Cmd
Code
05h
Address
Inputs
Cmd
Code
5 Add cycles
Row Add 1,2,3 Col Add 1,2
E0h
Data Output
Cmd
Code
2 Add cycles
Col Add 1,2
Main Area
Spare
Area
Main Area
Spare
Area
ai08658b
6.2
Cache read
The cache read operation improves the read throughput by reading data using the cache
register. As soon as the user starts to read one page, the device automatically loads the
next page into the cache register.
A Read Page command, as defined in Section 6.1.1: Random read, is issued prior to the
first Read Cache command in a read cache sequence. Once the Read Page command
execution is terminated, the Cache Read command can be issued as follows:
1.
Issue a Sequential Cache Read command to copy the next page in sequential order to
the cache register
2.
Issue a Random Cache Read command to copy the page addressed in this command
to the cache register.
The two commands can be used interchangeably, in any order. When there are no more
pages are to be read, the final page is copied into the cache register by issuing the Exit
Cache Read command. A Read Cache command must not be issued after the last page of
the device is read. Data output only starts after issuing the 31h command for the first time.
See Figure 9: Cache read (sequential) operation and Figure 10: Cache read (random)
operation for examples of the two sequences.
24/72
NAND04G-B2D, NAND08G-BxC
Device operations
After the Sequential Cache Read or Random Cache Read command has been issued, the
Ready/Busy signal goes Low and the status register bits are set to SR5 =' 0' and SR6 ='0'
for a period of cache read busy time, tRCBSY, while the device copies the next page into the
cache register.
After the cache read busy time has passed, the Ready/Busy signal goes High and the status
register bits are set to SR5 = '0' and SR6 = '1', signifying that the cache register is ready to
download new data. Data of the previously read page can be output from the page buffer by
toggling the Read Enable signal. Data output always begins at column address 00h, but the
Random Data Output command is also supported.
Figure 9.
Cache read (sequential) operation
tBLBH1
tRCBSY
(Read Busy time)
RB
(Read Cache Busy time)
tRCBSY
(Read Cache Busy time)
R
Busy
I/O0-7
Address
Inputs
00h
Read
Setup
Code
Data
Outputs
31h
30h
Read
Code
Cache
Read
Sequential
Code
Data
Outputs
3Fh
Exit
Cache
Read
Code
ai13176b
Repeat as many times as ncessary.
Figure 10. Cache read (random) operation
tBLBH1
tRCBSY
(Read Busy time)
RB
tRCBSY
(Read Cache Busy time)
(Read Cache Busy time)
R
Busy
I/O0-7
00h
Read
Setup
Code
Address
Inputs
30h
00h
Read
Code
Read
Setup
Code
Address
Inputs
31h
Data
Outputs
Enhanced
Cache
Read
(random)
Code
Repeat as many times as ncessary.
3Fh
Data
Outputs
Exit
Cache
Read
Code
ai13176c
25/72
Device operations
6.3
NAND04G-B2D, NAND08G-BxC
Page program
The page program operation is the standard operation to program data to the memory array.
Generally, the page is programmed sequentially, however, the device does support random
input within a page.
It is recommended to address pages sequentially within a given block.
The memory array is programmed by page, however, partial page programming is allowed
where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed.
The maximum number of consecutive, partial-page program operations allowed in the same
page is four. After exceeding four operations a Block Erase command must be issued before
any further program operations can take place in that page.
6.3.1
Sequential input
To input data sequentially the addresses must be sequential and remain in one block.
For sequential input each page program operation consists of the following five steps:
1.
One bus cycle is required to set up the Page Program (sequential input) command (see
Table 10: Commands)
2.
Five bus cycles are then required to input the program address (refer to Table 6:
Address insertion (x8 devices) and Table 7: Address insertion (x16 devices)).
3.
The data is then loaded into the data registers
4.
One bus cycle is required to issue the Page Program Confirm command to start the
P/E/R controller. The P/E/R controller only starts if the data has been loaded in step 3.
5.
the P/E/R controller then programs the data into the array.
See Figure 11: Page program operation for more information.
6.3.2
Random data input in page
During a sequential input operation, the next sequential address to be programmed can be
replaced by a random address by issuing a Random Data Input command. The following
two steps are required to issue the command:
1.
One bus cycle is required to set up the Random Data Input command (see Table 10:
Commands)
2.
Two bus cycles are then required to input the new column address (refer to Table 6:
Address insertion (x8 devices)).
Random data input can be repeated as often as required in any given page.
Once the program operation has started, the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
26/72
NAND04G-B2D, NAND08G-BxC
Device operations
Figure 11. Page program operation
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Data Input
Address Inputs
10h
70h
Confirm
Code
Page Program
Setup Code
SR0
Read Status Register
ai08659
Figure 12. Random data input during sequential data input
tBLBH2
(Program Busy time)
RB
Busy
I/O
80h
Address
Inputs
Data Intput
85h
Cmd
Code
Cmd
Code
5 Add cycles
Row Add 1,2,3 Col Add 1,2
Main Area
Spare
Area
Address
Inputs
2 Add cycles
Col Add 1,2
Data Input
10h
Confirm
Code
Main Area
70h
SR0
Read Status Register
Spare
Area
ai08664
27/72
Device operations
6.4
NAND04G-B2D, NAND08G-BxC
Multiplane page program
The devices support multiplane page program, which enables the programming of two
pages in parallel, one in each plane.
A multiplane page program operation requires the following two steps:
1.
2.
The first step serially loads up to two pages of data (4224 bytes) into the data buffer. It
requires:
–
1 clock cycle to set up the Page Program command (see Section 6.3.1: Sequential
input)
–
5 bus write cycles to input the first page address and data. The address of the first
page must be within the first plane (A18 = 0 for x8 devices, A17 = 0 for x16
devices)
–
1 bus write cycle to issue the page program confirm code. After this, the device is
busy for a time of tIPBSY.
–
When the device returns to the ready state (Ready/Busy High), a multiplane page
program setup code must be issued, followed by the 2nd page address (5 write
cycles) and data. The address of the 2nd page must be within the second plane
(A18 = 1 for x8 devices, A17 = 1 for x16 devices)
Parallel programming of both pages starts after the issue of Page Confirm command.
Refer to Figure 13: Multiplane page program waveform for differences between ONFI
and traditional sequences.
As for standard page program operation, the device supports random data input during both
data loading phases.
Once the multiplane page program operation has started, that is during a delay of tIPBSY, the
status register can be read using the Read Status Register command.
Once the multiplane page program operation has completed, the P/E/R controller bit SR6 is
set to ‘1’ and the Ready/Busy signal goes High.
If the multiplane page program fails, an error is signaled on bit SR0 of the status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 13 provides a description of the multiplane operation while showing the restrictions
related to the multiplane page program and the differences between ONFI 1.0 and
traditional sequences.
28/72
NAND04G-B2D, NAND08G-BxC
Device operations
Figure 13. Multiplane page program waveform
tBLBH2
tIPBSY
(Program Busy time)
RB
Busy
Busy
1
I/O
80h
Page Program
setup code
Address inputs
Data input
2
11h
Confirm
code
A0-A11 = Valid
A12-A17 = set to 'Low'
A18 = set to 'Low'
A19-A28 = set to 'Low'
81h
Address inputs
Data input
A0-A11 = Valid
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
Multiplane Page
Program setup
code
10h
Confirm
code
70h
SR0
Read Status register
1) The same row address, except for A18, is applied to the two blocks.
2) Any command between 11h and 81h is prohibited except 70h and FFh.
11h
80h
10h
81h
Data
input
First plane
(1024 block)
Second plane
(1024 block)
Block 0
Block 1
Block 2
Block 3
.
.
.
.
Block 2044
Block 2045
Block 2046
Block 2047
a) Traditional protocol
CL
W
AL
R
I/O
80h C1A C2A R1A R2A R3A
D0A D1A
...
DnA
11h
80h C1B C2B R1B R2B R3B
D0B D1B
...
DnB
10h
tBLBH2
tIPBSY
(Program Busy time)
RB
Busy
Busy
b) ONFI 1.0 protocol
ai13171c
1. This address scheme refers to x8 devices, remember to use the appropriate scheme for x16 devices.
6.5
Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back program operation does not require external memory and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
29/72
Device operations
NAND04G-B2D, NAND08G-BxC
operation is particularly useful when a portion of a block is updated and the rest of the block
needs to be copied to the newly assigned block.
The NAND04G-B2D and NAND08G-BxC devices feature automatic EDC (error detection
code) during a copy back operation. Consequently, it is no longer required to use an external
ECC to detect copy back operation errors. Read error occurrences can be detected by
checking the EDC status register (see Section 6.13: Read EDC status register). See also
Section 6.9 for details of EDC operations.
The copy back program operation requires the following four steps:
1.
The first step reads the source page. The operation copies all 2112 bytes from the
page into the data buffer. It requires:
–
1 bus write cycle to set up the command
–
5 bus write cycles to input the source page address
–
1 bus write cycle to issue the confirm command code
2.
When the device returns to the ready state (ready/busy High), optional data readout is
allowed by pulsing R; the next bus write cycle of the command is given with the 5 bus
cycles to input the target page address. See Table 11 for the addresses that must be
the same for the source and target page.
3.
Issue the confirm command to start the P/E/R controller.
To see the data input cycle for modifying the source page and an example of the copy back
program operation, refer to Figure 14: Copy back program (without readout of data).
Figure 16: Page copy back program with random data input shows a data input cycle to
modify a portion or a multiple distant portion of the source page.
Table 11.
Copy back program addresses
Density
Source and target page addresses
4 Gbits
Same A18
8 Gbits
Same A18 and A30
Figure 14. Copy back program (without readout of data)
I/O
00h
Source
Add Inputs
35h
85h
Read
Code
Target
Add Inputs
10h
Copy Back
Code
tBLBH1
70h
SR0
Read Status Register
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858b
1. Copy back program is only permitted between odd address pages or even address pages.
30/72
NAND04G-B2D, NAND08G-BxC
Device operations
Figure 15. Copy back program (with readout of data)
I/O
00h
Source
Add Inputs
35h
Data Outputs
Read
Code
Target
Add Inputs
85h
10h
70h
Copy Back
Code
SR0
Read Status
Register
tBLBH1
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai09858c
Figure 16. Page copy back program with random data input
I/O
Source
Add Inputs 35h
00h
Read
Code
85h
Target
Add Inputs
Data
Copy Back
Code
tBLBH1
85h
2 Cycle
Add Inputs
Data
10h
70h
SR0
Unlimited number of repetitions
tBLBH2
(Read Busy time)
(Program Busy time)
RB
Busy
Busy
ai11001
6.6
Multiplane copy back program
In addition to multiplane page program, the NAND04G-B2D and NAND08G-BxC devices
support multiplane copy back program.
A Multiplane Copy Back Program command requires exactly the same steps as a Multiplane
Page Program command, and must satisfy the same time constraints (see Section 6.4:
Multiplane page program).
Prior to executing the multiplane copy back program operation, two single-page read
operations must be executed to copy back the first page from the first plane and the second
page from the second plane.
Two different sequences are allowed for the multiplane copy back operation:
1.
A traditional one (85h command, address insertion for the first plane, 11h command,
81h command, address insertion for the second plane, 10h command)
2.
ONFI 1.0 (85h command, address insertion for the first plane, 11h command, 85h
command, address insertion for the second plane, 10h command)
The EDC check is also performed during the multiplane copy back program. Errors during
multiplane copy back operations can be detected by performing a read EDC status register
operation (see Section 6.13: Read EDC status register).
If the multiplane copy back program fails, an error is signaled on bit SR0 of the status
register. To know which page of the two planes failed, the Read Status Enhanced command
must be executed twice, once for each plane (see Section 6.12). Figure 17: Multiplane copy
back program provides a description of multiplane copy back program waveforms.
31/72
Device operations
NAND04G-B2D, NAND08G-BxC
Figure 17. Multiplane copy back program
I/O
00h
Add. 5
cycles
35h
00h
Copy back
code
Copy back
code
Read
code
Read
code
Add. 5
cycles
35h
Col. Add. 1, 2
Col. Add. 1, 2
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Source address on 1st plane Source address on 2nd plane
tBLBH1
tBLBH1
(Read Busy time)
(Read Busy time)
Add. 5
cycles
85h
2
11h
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A17 = set to 'Low'
A18 = set to 'Low'
A19-A28 = set to 'Low'
81h
Add. 5
cycles
10h
70h
SR0
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
tIPBSY
tBLBH2
(Program Busy time)
RB
Busy
Busy
Read Status Register
Busy
Busy
Second plane
First plane
Source page
Source page
(1): Read for copy back on first plane
Target page
Target page
(2): Read for copy back on second plane
(1)
(3)
Main area
(2)
(3)
Main area
Spare area
(3): Two-plane copy back program
Spare area
a) Traditional sequence.
I/O
00h
Add. 5
cycles
35h
00h
Copy back
code
Copy back
code
Read
code
Read
code
Add. 5
cycles
35h
85h
Col. Add. 1, 2
Col. Add. 1, 2
Row Add. 1, 2, 3
Row Add. 1, 2, 3
Source address on 1st plane Source address on 2nd plane
tBLBH1
tBLBH1
(Read Busy time)
(Read Busy time)
Add. 5
cycles
2
11h
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A17 = set to 'Low'
A18 = set to 'Low'
A19-A28 = set to 'Low'
Add. 5
cycles
10h
70h
SR0
Col. Add. 1, 2
Row Add. 1, 2, 3
Destination address
A0-A11 = set to 'Low'
A12-A17 = Valid
A18 = set to 'High'
A19-A28 = Valid
tIPBSY
tBLBH2
(Program Busy time)
RB
Busy
85h
Read Status Register
Busy
Busy
Busy
b) ONFI 1.0 sequence.
ai13172f
1. This address scheme refers to x8 devices. Please, remember to use the appropriate scheme for x16 devices.
2. Any command between 11h and 81h is prohibited except 70h and FFh.
6.7
Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previous data in the block is lost.
32/72
NAND04G-B2D, NAND08G-BxC
Device operations
An erase operation consists of the following three steps (refer to Figure 18: Block erase):
1.
One bus cycle is required to set up the Block Erase command. Only addresses A18A28 are used; all other address inputs are ignored
2.
Three bus cycles are then required to load the address of the block to be erased. Refer
to Table 8: Address definition (x8 devices) for the block addresses of each device
3.
One bus cycle is required to issue the Block Erase Confirm command to start the P/E/R
controller.
The operation is initiated on the rising edge of Write Enable, W, after the Confirm command
is issued. The P/E/R controller handles block erase and implements the verify process.
During the block erase operation, only the Read Status Register and Reset commands are
accepted; all other commands are ignored.
Once the program operation has completed, the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High. If the operation completed successfully, the write status bit
SR0 is ‘0’, otherwise it is set to ‘1’.
Figure 18. Block erase
tBLBH3
(Erase Busy time)
RB
Busy
I/O
60h
Block Erase
Setup Code
Block Address
Inputs
D0h
Confirm
Code
70h
SR0
Read Status Register
ai07593
33/72
Device operations
6.8
NAND04G-B2D, NAND08G-BxC
Multiplane block erase
The multiplane block erase operation allows the erasure of two blocks in parallel, one in
each plane.
This operation consists of the following three steps (refer to Figure 19: Multiplane block
erase):
1.
10 bus cycles are required to set up the Block Erase command and load the addresses
of the blocks to be erased. The setup command followed by the address of the block to
be erased must be issued for each block. tIEBSY busy time is required between the
insertion of first and the second block addresses. As for multiplane page program
operations, the address of the first and second page must be within the first plane
(A18 = 0 for x8 devices, A17 = 0 for x16 devices) and second plane (A18 = 1 for x8
devices, A17 = 1 for x16 devices), respectively.
2.
1 bus cycle is then required to issue the Multiplane Block Erase Confirm command and
start the P/E/R controller.
If the multiplane block erase fails, an error is signaled on bit SR0 of the status register. To
know which page of the two planes failed, the Read Status Enhanced command must be
issued twice, once for each plane (see Section 6.12).
Figure 19. Multiplane block erase
tBLBH3
(Erase Busy time)
RB
Busy
I/O
60h
Block Erase
Setup code
Block address
inputs
A18=0
A12-A17=0
A17-A29=0
60h
Block address
inputs
Block Erase
Setup code
A18=1
A12-A17=0
A17-A29=valid
D0h
Confirm
code
70h
SR0
Read Status
register
a) Traditional sequence
CL
W
AL
R
I/O 0-7
60h R1A R2A R3A D1h
60h R1B R2B R3B D0h
tBLBH2
tIPBSY
(Program Busy time)
RB
Busy
Busy
b) ONFI 1.0 sequence.
ai13173c
1. This address scheme refers to x8 devices. Please remember to use the appropriate scheme for x16 devices.
34/72
NAND04G-B2D, NAND08G-BxC
6.9
Device operations
Error detection code (EDC)
The EDC (error detection code) is performed automatically during all program operations. It
starts immediately after the device becomes busy.
The EDC detects 1 single bit error per EDC unit. Each EDC unit has a density of 528 bytes
(or 264 words), split into 512 bytes of main area and 16 bytes of spare area (or
256 + 8 words). Refer to Table 12 and Figure 20 for EDC unit addresses definition. EDC
results can only be retrieved during copy back program and multiplane copy back operations
using the Read EDC Status Register command (see Section 6.13: Read EDC status
register).
To properly use the EDC, the following conditions apply:
●
Page program operations must be performed on a whole page, or on whole EDC unit(s)
●
The modification of the content of an EDC unit using a random data input before the
copy back program, must be performed on the whole EDC unit. It can only be done
once per EDC unit. Any partial modification of the EDC unit results in the corruption of
the on-chip EDCs.
Figure 20. Page organization
Page = 4 EDC units
Main area (2048 bytes/1024 words)
Spare area (64 bytes/32 words)
A area
B area
C area
D area
(512 bytes/ (512 bytes/ (512 bytes/ (512 bytes/
256 words) 256 words) 256 words) 256 words)
E area
(16 bytes/
8 words)
F area
G area
(16 bytes/ (16 bytes/
8 words) 8 words)
H area
(16 bytes/
8 words)
AI13179b
Table 12.
Address definition for EDC units (x8 devices)
Main area
Spare area
EDC unit
Area name
Column address
Area name
Column address
1st 528-byte EDC unit
A
0 to 511
E
2048 to 2063
2nd 528-byte EDC unit
B
512 to 1023
F
2064 to 2079
3rd 528-byte EDC unit
C
1024 to1535
G
2080 to 2095
4th 528-byte EDC unit
D
1536 to 2047
H
2096 to 2111
35/72
Device operations
Table 13.
NAND04G-B2D, NAND08G-BxC
Address definition for EDC units (x16 devices)
Main area
Spare area
EDC unit
Area name
Column address
Area name
Column address
1st 264-word EDC unit
A
0 to 255
E
1024 to 1031
2nd 264-word EDC unit
B
256 to 511
F
1032 to 1039
3rd 264-word EDC unit
C
512 to 767
G
1040 to 1047
4th 264-word EDC unit
D
768 to 1023
H
1048 to 1055
6.10
Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation is aborted. If the aborted
operation is a program or erase, the contents of the memory locations being modified are no
longer valid as the data is partially programmed or erased.
If the device has already been reset, then the new Reset command is not accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was performing when the command was
issued. Refer to Table 31 for the values.
6.11
Read status register
The devices contain a status register that provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status register is read by issuing the Read Status Register command. The status
register information is present on the output data bus (I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, whichever occurs last. When several memories are connected in a
system, the use of Chip Enable and Read Enable signals allows the system to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary to
toggle the Chip Enable or Read Enable signals to update the contents of the status register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore, if a Read Status Register
command is issued during a random read cycle, a new Read command must be issued to
continue with a page read operation.
The status register bits are summarized in Table 14: Status register bits. Refer to Table 14 in
conjunction with the following sections.
6.11.1
Write protection bit (SR7)
The write protection bit identifies if the device is protected or not. If the write protection bit is
set to ‘1’, the device is not protected and program or erase operations are allowed. If the
write protection bit is set to ‘0’ the device is protected and program or erase operations are
not allowed.
36/72
NAND04G-B2D, NAND08G-BxC
6.11.2
Device operations
P/E/R controller and cache ready/busy bit (SR6)
Status register bit SR6 has two different functions depending on the current operation.
During cache operations, SR6 acts as a cache ready/busy bit, which indicates whether the
cache register is ready to accept new data. When SR6 is set to '0', the cache register is
busy, and when SR6 is set to '1', the cache register is ready to accept new data.
During all other operations, SR6 acts as a P/E/R controller bit, which indicates whether the
P/E/R controller is active or inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
6.11.3
P/E/R controller bit (SR5)
The Program/Erase/Read controller bit indicates whether the P/E/R controller is active or
inactive during cache operations. When the P/E/R controller bit is set to ‘0’, the P/E/R
controller is active (device is busy); when the bit is set to ‘1’, the P/E/R controller is inactive
(device is ready).
Note:
This bit is only valid for cache operations.
6.11.4
Error bit (SR0)
The error bit identifies if any errors have been detected by the P/E/R controller. The error bit
is set to ’1’ when a program or erase operation has failed to write the correct data to the
memory. If the error bit is set to ‘0’ the operation has completed successfully.
6.11.5
SR4, SR3, SR2 and SR1 are reserved
Table 14.
Status register bits
Bit
Name
SR7
Write protection
SR6
SR5
Logic level
Definition
'1'
Not protected
'0'
Protected
'1'
P/E/R controller inactive, device ready
'0'
P/E/R controller active, device busy
'1'
P/E/R controller inactive, device ready
'0'
P/E/R controller active, device busy
Program/Erase/Read controller
Program/Erase/Read controller(1)
SR4, SR3, SR2,
SR1
Reserved
SR0
Generic error
‘don’t care’
‘1’
Error – operation failed
‘0’
No error – operation successful
1. Only valid for cache operations.
37/72
Device operations
6.12
NAND04G-B2D, NAND08G-BxC
Read status enhanced
In NAND flash devices with multiplane architecture, it is possible to independently read the
status register of a single plane using the Read Status Enhanced command. If the error bit
of the status register, SR0, reports an error during or after a multiplane operation, the Read
Status Enhanced command is used to know which of the two planes contains the page that
failed the operation. Three address cycles are required to address the selected block and
page (A12-A28 for x8 devices and A11-A27 for x16 devices).
The output of the Read Status Enhanced command has the same coding as the Read
Status command. See Table 14 for a full description and Figure 30 for the read status
enhanced waveform.
6.13
Read EDC status register
The devices contain an EDC status register, which provides information on the errors that
occurred during the read cycles of the copy back and multiplane copy back operations. In
the case of multiplane copy back program, it is not possible to distinguish which of the two
read operations caused the error.
The EDCS status register is read by issuing the Read EDC Status Register command.
After issuing the Read EDC Status Register command, a read cycle outputs the content of
the EDC status register to the I/O pins on the falling edge of Chip Enable or Read Enable
signals, whichever occurs last. The operation is similar to Read Status Register command.
Table 15: EDC status register bits summarizes the EDC status register bits. See Figure 29
for a description of Read EDC Status Register waveforms.
Table 15.
Bit
0
EDC status register bits
Name
Logic level
Definition
‘1’
Copy back or multiplane copy back
operation failed
‘0’
Copy back or multiplane copy back
operation succeeded
‘1’
Error
‘0’
No error
‘1’
Valid
‘0’
Invalid
Pass/fail
1
EDC status
2
EDC validity
3
Reserved
‘don’t care’
–
4
Reserved
‘don’t care’
–
5
Ready/busy(1)
6
Ready/busy(1)
7
Write protect
‘1’
Ready
‘0’
Busy
‘1’
Ready
‘0’
Busy
‘1’
Not protected
‘0’
Protected
1. See Table 14: Status register bits for a description of SR5 and SR6 bits.
38/72
NAND04G-B2D, NAND08G-BxC
6.14
Device operations
Read electronic signature
The devices contain a manufacturer code and device code. The following three steps are
required to read these codes:
1.
One bus write cycle to issue the Read Electronic Signature command (90h)
2.
One bus write cycle to input the address (00h)
3.
Five bus read cycles to sequentially output the data (as shown in Table 16: Electronic
signature).
The device remains in this state until a new command is issued.
Table 16.
Electronic signature
Byte 3
Byte 4
Byte 5
(see Table 17)
(see Table 18)
(see Table 19)
ACh
10h
15h
54h
20h
DCh
10h
95h
54h
NAND04GR4B2D
0020h
BCh
10h
55h
54h
NAND04GW4B2D
0020h
CCh
10h
D5h
54h
NAND08GR3B2C
20h
A3h
51h
15h
58h
NAND08GW3B2C
20h
D3h
51h
95h
58h
NAND08GR4B2C
0020h
B3h
51h
55h
58h
NAND08GW4B2C
0020h
C3h
51h
D5h
58h
Root part number
Byte 1
Byte 2
NAND04GR3B2D
NAND08GR3B4C(1)
20h
NAND04GW3B2D
NAND08GW3B4C(1)
1. For NAND08G-B4C devices, each 4-Gbit die returns its own electronic signature.
Table 17.
Electronic signature byte 3
I/O
Definition
Value
Description
Internal chip number
00
01
10
11
1
2
4
8
Cell type
00
01
10
11
2-level cell
4-level cell
8-level cell
16-level cell
I/O5-I/O4
Number of simultaneously
programmed pages
00
01
10
11
1
2
4
8
I/O6
Interleaved programming
between multiple devices
0
1
Not supported
Supported
I/O7
Cache program
0
1
Not supported
Supported
I/O1-I/O0
I/O3-I/O2
39/72
Device operations
Table 18.
Electronic signature byte 4
I/O
Definition
Value
Description
I/O1-I/O0
Page size
(without spare area)
00
01
10
11
1 Kbyte
2 Kbytes
4 Kbytes
8 Kbytes
I/O2
Spare area size
(byte/512 byte)
0
1
8
16
Minimum sequential access
time
00
10
01
11
30/50 ns
25 ns
Reserved
Reserved
I/O5-I/O4
Block size
(without spare area)
00
01
10
11
64 Kbytes
128 Kbytes
256 Kbytes
512 Kbytes
I/O6
Organization
0
1
x8
x16
I/O7, I/O3
Table 19.
Electronic signature byte 5
I/O
Definition
Value
I/O1 - I/O0
Reserved
0 0
I/O3 - I/O2
40/72
NAND04G-B2D, NAND08G-BxC
Plane number
I/O6 - I/O4
Plane size
(without spare area)
I/O7
Reserved
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
Description
1 plane
2 planes
4 planes
8 planes
64 Mbits
128 Mbits
256 Mbits
512 Mbits
1 Gbit
2 Gbits
4 Gbits
8 Gbits
NAND04G-B2D, NAND08G-BxC
6.15
Device operations
Read ONFI signature
To recognize NAND flash devices that are compatible with the ONFI 1.0 command set, the
Read Electronic Signature can be issued, followed by an address of 20h. The next four
bytes output is the ONFI signature, which is the ASCII encoding of the ‘ONFI’ word. Reading
beyond four bytes produces indeterminate values. The device remains in this state until a
new command is issued.
Figure 32 provides a description of the read ONFI signature waveform and Table 20
provides the definition of the output bytes.
Table 20.
6.16
Read ONFI signature
Byte
Value
ASCII character
1st byte
4Fh
O
2nd byte
4Eh
N
3rd byte
46h
F
4th byte
49h
I
5th byte
Undefined
Undefined
Read parameter page
The Read Parameter Page command retrieves the data structure that describes the NAND
flash organization, features, timings and other behavioral parameters. This data structure
enables the host processor to automatically recognize the NAND flash configuration of a
device. The whole data structure is repeated at least five times.
See Figure 39 for a description of the read parameter page waveform.
The Random Data Read command can be issued during execution of the read parameter
page to read specific portions of the parameter page.
The Read Status command may be used to check the status of read parameter page during
execution. After completion of the Read Status command, 00h is issued by the host on the
command line to continue with the data output flow for the Read Parameter Page command.
Read status enhanced is not be used during execution of the Read Parameter Page
command.
Table 21 defines the parameter page data structure; for parameters that span multiple bytes,
the least significant byte of the parameter corresponds to the first byte.
Values are reported in the parameter page in bytes when referring to items related to the
size of data access (as in an x8 data access device). For example, the chip returns how
many data bytes are in a page. For a device that supports x16 data access, the host is
required to convert byte values to word values for its use. Unused fields are set to 0h.
For more detailed information about parameter page data bits, refer to ONFI
specification 1.0, section 5.4.1.
41/72
Device operations
NAND04G-B2D, NAND08G-BxC
Table 21.
Parameter page data structure
Byte
0-3
O/M(1)
M
Description
Parameter page signature
– Byte 0: 4Fh, ‘O’
– Byte 1: 4Eh, ‘N’
– Byte 2: 46h, ‘F’
– Byte 3: 49h, ‘I’
Revision number
Revision information and features block
4-5
M
Bit 2 to bit 15 Reserved (0)
Bit 1
1 = supports ONFI version 1.0
Bit 0
Reserved (0)
Features supported
Bit 5 to bit 15 Reserved (0)
6-7
M
Bit 4
1 = supports odd to even page copy back
Bit 3
1 = supports interleaved operations
Bit 2
1 = supports non-sequential page programming
Bit 1
1 = supports multiple LUN operations
Bit 0
1 = supports 16-bit data bus width
Optional commands supported
Bit 6 to bit 15 Reserved (0)
8-9
M
Bit 5
1 = supports Read Unique ID
Bit 4
1 = supports Copy back
Bit 3
1 = supports Read Status Enhanced
Bit 2
1 = supports Get Features and Set Features
Bit 1
1 = supports Read Cache commands
Bit 0
1 = supports Page Cache Program command
Manufacturer
information block
10-31
42/72
Reserved (0)
32-43
M
Device manufacturer (12 ASCII characters)
44-63
M
Device model (20 ASCII characters)
64
M
JEDEC manufacturer ID
65-66
O
Date code
67-79
Reserved (0)
80-83
M
Number of data bytes per page
84-85
M
Number of spare bytes per page
86-89
M
Number of data bytes per partial page
90-91
M
Number of spare bytes per partial page
92-95
M
Number of pages per block
NAND04G-B2D, NAND08G-BxC
Table 21.
Device operations
Parameter page data structure (continued)
Byte
O/M(1)
96-99
M
Number of blocks per logical unit (LUN)
100
M
Number of logical units (LUNs)
Description
Number of address cycles
Memory organization block
101
M
Bit 4 to bit 7
Column address cycles
Bit 0 to bit 3
Row address cycles
102
M
Number of bits per cell
103-104
M
Bad blocks maximum per LUN
105-106
M
Block endurance
107
M
Guaranteed valid blocks at beginning of target
108-109
M
Block endurance for guaranteed valid blocks
110
M
Number of programs per page
Partial programming attributes
111
112
M
Bit 5 to bit 7
Reserved
4
1 = partial page layout is partial page data followed by
partial page spare
Bit 1 to bit 3
Reserved
0
1 = partial page programming has constraints
M
Number of bits ECC correctability
Number of interleaved address bits
113
M
Bit 4 to bit 7
Reserved (0)
Bit 0 to bit 3
Number of interleaved address bits
Interleaved operation attributes
114
O
115-127
128
Bit 4 to bit 7
Reserved (0)
Bit 3
Address restrictions for program cache
Bit 2
1 = program cache supported
Bit 1
1 = no block address restrictions
Bit 0
Overlapped/concurrent interleaving support
Reserved (0)
M
I/O pin capacitance
43/72
Device operations
NAND04G-B2D, NAND08G-BxC
Table 21.
Parameter page data structure (continued)
Byte
O/M(1)
Description
Timing mode support
Bit 6 to bit 15 Reserved (0)
Red. param.
pages
Vendor
block
Electrical parameters block
129-130
M
Bit 5
1 = supports timing mode 5
Bit 4
1 = supports timing mode 4
Bit 3
1 = supports timing mode 3
Bit 2
1 = supports timing mode 2
Bit 1
1 = supports timing mode 1
Bit 0
1 = supports timing mode 0, shall be 1
Program cache timing mode support
Bit 6 to bit 15 Reserved (0)
131-132
O
Bit 5
1 = supports timing mode 5
Bit 4
1 = supports timing mode 4
Bit 3
1 = supports timing mode 3
Bit 2
1 = supports timing mode 2
Bit 1
1 = supports timing mode 1
Bit 0
1 = supports timing mode 0
133-134
M
tPROG maximum page program time (µs)
135-136
M
tBERS maximum block erase time (µs)
137-138
M
tR maximum page read time (µs)
139-163
M
Reserved (0)
164-165
M
Vendor specific revision number
166-253
M
Vendor specific
254-255
M
Integrity CRC
256-511
M
Value of bytes 0-255
512-767
M
Value of bytes 0-255
768+
O
Additional redundant parameter pages
1. O = optional, M = mandatory.
44/72
NAND04G-B2D, NAND08G-BxC
7
Concurrent operations and extended read status
Concurrent operations and extended read status
The NAND08G-BxC devices are composed of two 4-Gbit dice stacked together. This
configuration allows the devices to support concurrent operations, which means that while
performing an operation in one die (erase, read, program, etc.), another operation is
possible in the other die.
The standard read status register operation returns the status of the NAND08G-BxC device.
To provide information on each 4-Gbit die, the NAND08G-BxC devices feature an Extended
Read Status Register command that independently checks the status of each NAND04GB2D.
The following steps are required to perform concurrent operations:
1.
Select one of the two dice by setting the most significant address bit A30 to ‘0’ or ‘1’
2.
Execute one operation on this die
3.
Launch a concurrent operation on the other die
4.
Check the status of these operations by performing an extended read status register
operation.
All combinations of operations are possible except read while read. This is due to the fact
that the input/output bus is common to both dice.
Refer to Table 22 for the description of the Extended Read Status Register command
sequence, and to Table 14. for the definition of the status register bits.
Table 22.
8
Extended Read Status Register commands
Command
Address range
1 bus write cycle
Read 1st die status
Address ≤ 0x3FFFFFFF
F2h
Read 2nd die status
0x3FFFFFFF < Address ≤ 0x7FFFFFF
F3h
Data protection
The devices feature a Write Protect, WP, pin, which can be used to protect the device
against program and erase operations. It is recommended to keep WP at VIL during powerup and power-down.
45/72
Software algorithms
9
NAND04G-B2D, NAND08G-BxC
Software algorithms
This section provides information on the software algorithms that Numonyx recommends
implementing to manage the bad blocks and extend the lifetime of the NAND device.
NAND flash memories are programmed and erased by Fowler-Nordheim tunnelling using
high voltage. Exposing the device to high voltage for extended periods damages the oxide
layer.
To extend the number of program and erase cycles and increase the data retention, the:
●
Number of program and erase cycles is limited (seeTable 24: Program erase times and
program erase endurance cycles for the values)
●
Implementation of a garbage collection, a wear-leveling algorithm and an error
correction code is recommended.
To help integrate a NAND memory into an application, Numonyx provides a file system OS
native reference software, which supports the basic commands of file management.
Contact the nearest Numonyx sales office for more details.
9.1
Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characteristics as devices that have all valid blocks. A bad block does not affect the
performance of valid blocks because it is isolated from the bit and common source lines by a
select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st and 6th bytes (x8
devices) /1st word (x16 devices), in the spare area of the 1st page, does not contain FFh is
a bad block.
The bad block information must be read before any erase is attempted as the bad block
information may be erased. For the system to be able to recognize the bad blocks based on
the original information, the creation of a bad block table following the flowchart shown in
Figure 21: Bad block management flowchart is recommended.
46/72
NAND04G-B2D, NAND08G-BxC
9.2
Software algorithms
NAND flash memory failure modes
Over the lifetime of the device bad blocks may develop. To implement a highly reliable
system, the possible failure modes must be considered.
●
Program/erase failure
In this case, the block has to be replaced by copying the data to a valid block. These
additional bad blocks can be identified because attempts to program or erase them
gives errors in the status register. As the failure of a page program operation does not
affect the data in other pages in the same block, the block can be replaced by
reprogramming the current data and copying the rest of the replaced block to an
available valid block. The Copy Back Program command can be used to copy the data
to a valid block. See Section 6.5: Copy back program for more details.
●
Read failure
In this case, ECC correction must be implemented. To efficiently use the memory
space, the recovery of a single-bit error in read by ECC, without replacing the whole
block, is recommended.
Refer to Table 23: Block failure for the recommended procedure to follow if an error occurs
during an operation.
Table 23.
Block failure
Operation
Procedure
Erase
Block replacement
Program
Block replacement
Read
ECC
Figure 21. Bad block management flowchart
START
Block Address =
Block 0
Data
= FFh?
Increment
Block Address
NO
Update
Bad Block table
YES
Last
block?
NO
YES
END
AI07588C
47/72
Software algorithms
9.3
NAND04G-B2D, NAND08G-BxC
Garbage collection
When a data page needs to be modified, it is faster to write to the first available page,
resulting in the previous page being marked as invalid. After several updates it is necessary
to remove invalid pages to free memory space.
To free this memory space and allow further program operations, the implementation of a
garbage collection algorithm is recommended. In garbage collection software, the valid
pages are copied into a free area and the block containing the invalid pages is erased as
show in Figure 22.
Figure 22. Garbage collection
New area (After GC)
Old area
Valid
page
Invalid
page
Free
page
(erased)
AI07599B
9.4
Wear-leveling algorithm
For write-intensive applications, the implementation of a wear-leveling algorithm is
recommended to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm, not all blocks get used at the same
rate. The wear-leveling algorithm ensures that equal use is made of all the available write
cycles for each block. There are two wear-leveling levels:
●
First level wear-leveling, where new data is programmed to the free blocks that have
had the fewest write cycles
●
Second level wear-leveling, where long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is triggered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
9.5
Error correction code
Users must implement an error correction code (ECC) to identify and correct errors in the
data stored in the NAND flash memories. The ECC implemented must be able to correct 1
bit for every 512 bytes. Sensible data stored in the spare area must be covered by ECC as
well.
48/72
NAND04G-B2D, NAND08G-BxC
10
Program and erase times and endurance cycles
Program and erase times and endurance cycles
The program and erase times and the number of program/erase cycles per block are shown
in Table 24.
Table 24.
Program erase times and program erase endurance cycles
NAND flash
Parameters
Unit
Min
Typ
Max
200
700
µs
3V
200
700
µs
1.8 V
250
800
µs
1.5
2
ms
3V
1.5
2
ms
1.8 V
2
2.5
ms
Multiplane program busy time (tIPBSY)
0.5
1
µs
Multiplane erase busy time (tIEBSY)
0.5
1
µs
3
tR
µs
Page program time
Multiplane program time
Block erase time
Multiplane block erase time
Cache read busy time (tRCBSY)
Program/erase cycles per block (with ECC)
Data retention
100,000
cycles
10
years
49/72
Maximum ratings
11
NAND04G-B2D, NAND08G-BxC
Maximum ratings
Stressing the device above the ratings listed in Table 25: Absolute maximum ratings may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 25.
Absolute maximum ratings
Value
Symbol
Parameter
Unit
Min
Max
TBIAS
Temperature under bias
– 50
125
°C
TSTG
Storage temperature
– 65
150
°C
VIO(1)
Input or output voltage
– 0.6
4.6
V
Supply voltage
– 0.6
4.6
V
VDD
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins.
Maximum voltage may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
50/72
NAND04G-B2D, NAND08G-BxC
12
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the devices. The parameters in the following DC and AC characteristics
tables are derived from tests performed under the measurement conditions summarized in
Table 26. Designers should check that the operating conditions in their circuit match the
measurement conditions when relying on the quoted parameters.
Table 26.
Operating and AC measurement conditions
NAND flash
Parameter
Supply voltage (VDD)
Ambient temperature (TA)
Load capacitance (CL) (1 TTL GATE
and CL)
Units
Min
Max
1.8 V device
1.7
1.95
3 V device
2.7
3.6
Grade 1
0
70
Grade 6
–40
85
1.8 V device
30
3 V device
50
V
°C
pF
Input pulses voltages
0
Input and output timing ref. voltages
Output circuit resistor Rref
Input rise and fall times
Table 27.
Capacitance(1)
Symbol
Parameter
Test condition
Typ
VDD
V
VDD/2
V
8.35
kΩ
5
ns
Max
Unit
CIN
Input capacitance
VIN = 0 V
10
pF
CI/O
Input/output
capacitance(2)
VIL = 0 V
10
pF
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double in stacked devices.
51/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 23. Equivalent testing circuit for AC characteristics measurement
VDD
2Rref
NAND Flash
CL
2Rref
GND
GND
Ai11085
Table 28.
Symbol
DC characteristics (1.8 V devices)(1)
Parameter
IDD1
IDD2
Operating
current
Test conditions
Min
Typ
Max
Unit
Sequential
read
tRLRL minimum
E=VIL, IOUT = 0 mA
–
10
20
mA
Program
–
–
10
20
mA
Erase
–
–
10
20
mA
IDD3
IDD5
Standby current (CMOS)
E=VDD-0.2,
WP=0/VDD
–
10
50
µA
ILI
Input leakage current
VIN= 0 to VDDmax
–
–
±10
µA
ILO
Output leakage current
VOUT= 0 to VDDmax
–
–
±10
µA
VIH
Input high voltage
–
0.8 * VDD
–
VDD + 0.3
V
VIL
Input low voltage
–
-0.3
–
0.2 * VDD
V
VOH
Output high voltage level
IOH = -100 µA
VDD - 0.1
–
–
V
VOL
Output low voltage level
IOL = 100 µA
–
–
0.1
V
IOL (RB)
Output low current (RB)
VOL = 0.1 V
3
–
4
mA
VLKO
VDD supply voltage (erase and
program lockout)
–
–
–
1.1
V
1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
52/72
NAND04G-B2D, NAND08G-BxC
Table 29.
DC and AC parameters
DC characteristics (3 V devices)(1)
Symbol
Parameter
IDD1
Operating
current
IDD2
Test conditions
Min
Typ
Max
Unit
Sequential
read
tRLRL minimum
E = VIL, IOUT = 0 mA
–
15
30
mA
Program
–
–
15
30
mA
Erase
–
–
15
30
mA
1
mA
IDD3
IDD4
Standby current (TTL)
E = VIH, WP = 0/VDD
IDD5
Standby current (CMOS)
E = VDD-0.2,
WP = 0/VDD
–
10
50
µA
ILI
Input leakage current
VIN= 0 to VDDmax
–
–
±10
µA
ILO
Output leakage current
VOUT= 0 to VDDmax
–
–
±10
µA
VIH
Input high voltage
–
0.8 VDD
–
VDD+0.3
V
VIL
Input low voltage
–
-0.3
–
0.2 VDD
V
VOH
Output high voltage level
IOH = -400 µA
2.4
–
-
V
VOL
Output low voltage level
IOL = 2.1 mA
–
–
0.4
V
IOL (RB)
Output Low current (RB)
VOL = 0.4 V
8
–
10
mA
VLKO
VDD supply voltage (erase and
program lockout)
–
–
–
1.8
V
1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
Table 30.
Symbol
tALLWH
tALHWH
tCLHWH
tCLLWH
AC characteristics for command, address, data input
Alt.
Parameter
1.8 V
3V
Unit
Address Latch Low to Write Enable High
tALS
AL setup time
Min
25
12
ns
CL setup time
Min
25
12
ns
Address Latch High to Write Enable High
Command Latch High to Write Enable High
tCLS
Command Latch Low to Write Enable High
tDVWH
tDS
Data Valid to Write Enable High
Data setup time
Min
20
12
ns
tELWH
tCS
Chip Enable Low to Write Enable High
E setup time
Min
35
20
ns
tWHALH
tALH
Write Enable High to Address Latch High
AL hold time
Min
10
5
ns
CL hold time
Min
10
5
ns
tWHCLH
tWHCLL
Write Enable High to Command Latch High
tCLH
Write Enable High to Command Latch Low
tWHDX
tDH
Write Enable High to Data Transition
Data hold time
Min
10
5
ns
tWHEH
tCH
Write Enable High to Chip Enable High
E hold time
Min
10
5
ns
tWHWL
tWH
Write Enable High to Write Enable Low
W high hold time
Min
15
10
ns
tWLWH
tWP
Write Enable Low to Write Enable High
W pulse width
Min
25
12
ns
tWLWL
tWC
Write Enable Low to Write Enable Low
Write cycle time
Min
45
25
ns
53/72
DC and AC parameters
Table 31.
Symbol
tALLRL1
tALLRL2
tBHRL
AC characteristics for operations(1)
Alt.
Parameter
Address Latch Low to Read
Enable Low
tRR
Ready/Busy High to Read Enable Low
tBLBH2
tPROG
tBLBH3
tBERS
tBLBH4
tRST
tCLLRL
tCLR
tDZRL
tIR
tEHQZ
tCHZ
tEHALX
Read electronic signature
tAR
tBLBH1
tEHCLX
NAND04G-B2D, NAND08G-BxC
tCSD
Ready/Busy Low to
Ready/Busy High
Read cycle
Min
1.8 V
3V
Unit
10
10
ns
Min
10
10
ns
Min
20
20
ns
Read Busy time
Max
25
25
µs
Program Busy time
Max
700
700
µs
Erase Busy time
Max
2
2
ms
Reset Busy time, during ready
Max
5
5
µs
Reset Busy time, during read
Max
5
5
µs
Reset Busy time, during program
Max
10
10
µs
Reset Busy time, during erase
Max
500
500
µs
Command Latch Low to Read Enable Low
Min
10
10
ns
Data Hi-Z to Read Enable Low
Min
0
0
ns
Chip Enable High to Output Hi-Z
Max
30
30
ns
Min
10
10
ns
Chip Enable High to Address Latch ‘don’t care’
Chip Enable High to Command Latch ‘don’t care’
tRHQZ
tRHZ
Read Enable High to Output Hi-Z
Max
100
100
ns
tELQV
tCEA
Chip Enable Low to Output Valid
Max
45
25
ns
tRHRL
tREH
Read Enable High to Read
Enable Low
Min
15
10
ns
tEHQX
tCOH
Chip Enable high to Output Hold
Min
15
15
ns
tRHQX
tRHOH Read Enable High to Output Hold
Min
15
15
ns
tRLQX
tRLOH Read Enable Low to Output Hold (EDO mode)
Min
5
5
ns
Read Enable High Hold time
tRLRH
tRP
Read Enable Low to Read
Enable High
tRLRL
tRC
Read Enable Low to Read
Enable Low
tRLQV
tREA
Read Enable Low to Output
Valid
tWHBH
tR
tWHBL
tWB
Write Enable High to Ready/Busy Low
Max
100
100
ns
tWHRL
tWHR
Write Enable High to Read Enable Low
Min
60
60
ns
tRHWL
tRHW Read Enable High to Write Enable Low
Min
100
100
ns
Min
100
70
ns
Min
100
100
ns
(3)
Write Enable High to
Ready/Busy High
tWHWH
tADL
tVHWH
tVLWH
tWW(4) Write protection time
Read Enable pulse width
Min
25
12
ns
Read cycle time
Min
45
25
ns
Max
30
20
ns
Max
25
25
µs
Read Enable access time
Read ES access time(2)
Read Busy time
Last address latched to data loading time during program operations
1. The time to ready depends on the value of the pull-up resistor tied to the ready/busy pin. See Figure 40, Figure 41 and
Figure 42.
2. ES = electronic signature.
3.
tADL is the time from W rising edge during the final address cycle to W rising edge during the first data cycle.
4. During a program/erase enable operation, tWW is the delay from WP high to W High.
During a program/erase disable operation, tWW is the delay from WP Low to W High.
54/72
NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 24. Command latch AC waveforms
CL
tWHCLL
tCLHWH
(CL Setup time)
(CL Hold time)
tWHEH
tELWH
(E Hold time)
H(E Setup time)
E
tWLWH
W
tALLWH
tWHALH
(ALSetup time)
(AL Hold time)
AL
tDVWH
tWHDX
(Data Setup time)
(Data Hold time)
I/O
Command
ai12470b
Figure 25. Address latch AC waveforms
tCLLWH
(CL Setup time)
CL
tWLWL
tWLWL
tELWH
tWLWL
tWLWL
(E Setup time)
E
tWLWH
tWLWH
tWLWH
tWLWH
tWLWH
W
tWHWL
tWHWL
tWHWL
tWHWL
tALHWH
(AL Setup time)
tWHALL
tWHALL
tWHALL
tWHALL
(AL Hold time)
AL
tDVWH
tDVWH
(Data Setup time)
tDVWH
tDVWH
tWHDX
tWHDX
tDVWH
tWHDX
tWHDX
tWHDX
(Data Hold time)
I/O
Adrress
cycle 1
Adrress
cycle 2
Adrress
cycle 3
Adrress
cycle 4
Adrress
cycle 5
ai12471
55/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 26. Data input latch AC waveforms
tWHCLH
(CL Hold time)
CL
tWHEH
(E Hold time)
E
tALLWH
(ALSetup time)
tWLWL
AL
tWLWH
tWLWH
tWLWH
W
tDVWH
tDVWH
tDVWH
(Data Setup time)
tWHDX
tWHDX
tWHDX
(Data Hold time)
I/O
Data In 0
Data In 1
Data In
Last
ai12472
1. The last data input is the 2112th.
Figure 27. Sequential data output after read AC waveforms
tRLRL
(Read Cycle time)
E
tEHQX
tEHQZ
tRHRL
(R High Holdtime)
R
tRHQZ
tRLQV
tRLQV
tRHQZ
tRHQX(2)
tRLQV
(R Accesstime)
I/O
Data Out
Data Out
Data Out
tBHRL
RB
ai13174
1. CL = Low, AL = Low, W = High.
2. tRHQX is applicable for frequencies lower than 33 MHz (for instance, tRLRL higher than 30 ns).
56/72
NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 28. Sequential data output after read AC waveforms (EDO mode)
tRLRL
E
tEHQX
tRLRH
tEHQZ
tRHRL
R
tELQV
tRHQZ
tRLQX
tRLQV
tRHQX(2)
tRLQV
(R Accesstime)
I/O
Data Out
Data Out
Data Out
tBHRL
RB
ai13175
1. In EDO mode, CL and AL are Low, VIL, and W is High, VIH.
2. tRLQX is applicable for frequencies high than 33 MHz (for instance, tRLRL lower than 30 ns).
Figure 29. Read status register or read EDC status register AC waveform
tCLLRL
CL
tWHCLL
tCLHWH
tWHEH
E
tELWH
tWLWH
W
tELQV
tWHRL
tEHQZ
tEHQX
R
tDZRL
tDVWH
tWHDX
tRLQV
tRHQX
(Data Hold time)
(Data Setup time)
I/O
tRHQZ
70h or 7Bh
Status Register
Output
ai13177
57/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 30. Read status enhanced waveform
CL
tWHRL
W
tALLRL2
AL
R
I/O 0-7
78h
Address 1
Address 2
Status Register
output
Address 3
ai14408b
Figure 31. Read electronic signature AC waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES Access time)
I/O
90h
Read Electronic
Signature
Command
00h
Byte1
Byte2
1st Cycle
Address
Man.
code
Device
code
Byte3
Byte4
Byte5
see Note.1
ai13178
1. Refer to Table 16 for the values of the manufacturer and device codes, and to Table 17, Table 18, and Table 19 for the
information contained in byte 3, byte 4, and byte 5.
58/72
NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 32. Read ONFI signature waveform
CL
E
W
AL
tALLRL1
R
tRLQV
(Read ES access time)
I/O
90h
Read Electronic
Signature
command
20h
4Fh
4Eh
46h
49h
XXh
1st cycle
address
ai13178b
59/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 33. Page read operation AC waveform
tEHALX
tEHCLX
CL
E
tWLWL
tEHQZ
W
tWHBL
AL
tALLRL2
tWHBH
tRLRL
tRHQZ
(Read Cycle time)
R
tRLRH
tBLBH1
RB
I/O
00h
Add.N
cycle 1
Command
Code
Add.N
cycle 2
Add.N
cycle 3
Address N Input
Add.N
cycle 4
Add.N
cycle 5
Data
N
30h
Busy
Data
N+1
Data
N+2
Data
Last
Data Output
from Address N to Last Byte or Word in Page
ai12474b
60/72
NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 34. Page program AC waveform
CL
E
tWLWL
tWLWL
tWLWL
(Write Cycle time)
W
tWHWH tWHBL
tBLBH2
tWHRL
(Program Busy time)
AL
R
I/O
80h
Add.N
cycle 1
Add.N Add.N Add.N Add.N
cycle 2 cycle 3 cycle 4 cycle 5
N
Last
10h
70h
SR0
RB
Page Program
Setup Code
Address Input
Data Input
Confirm
Code
Page
Program Read Status Register
ai12475b
61/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 35. Block erase AC waveform
CL
E
tWLWL
(Write Cycle time)
W
tBLBH3
tWHBL
(Erase Busy time)
tWHRL
AL
R
I/O
60h
Add.
Add.
Add.
cycle 1 cycle 2 cycle 3
70h
D0h
SR0
RB
Block Erase
Setup Command
Block Address Input
Confirm
Code
Block Erase
Read Status Register
ai08038c
Figure 36. Reset AC waveform
W
AL
CL
R
I/O
FFh
tBLBH4
(Reset Busy time)
RB
ai08043
62/72
NAND04G-B2D, NAND08G-BxC
DC and AC parameters
Figure 37. Program/erase enable waveform
W
W
tVHWH
tVHWH
WP
WP
RB
RB
I/O
80h
I/O
Program setup
60h
Erase setup
ai12477b
Figure 38. Program/erase disable waveform
W
W
tVLWH
tVLWH
WP
WP
High
High
RB
RB
I/O
80h
Program disable
I/O
60h
Erase disable
ai12478b
63/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 39. Read parameter page waveform
CL
W
AL
R
I/O0-7
R/B
ECh
P00
00h
P10
...
P01
P11
...
tBLBH1
ai14409
64/72
NAND04G-B2D, NAND08G-BxC
12.1
DC and AC parameters
Ready/busy signal electrical characteristics
Figure 41, Figure 40 and Figure 42 show the electrical characteristics for the ready/busy
signal. The value required for the resistor RP can be calculated using the following equation:
(V
–
)
DDmax V OLmax
R P min = ------------------------------------------------------------I OL + I L
This is an example for 3 V devices:
3.2V
R P min = -------------------------8mA + I L
where IL is the sum of the input currents of all the devices tied to the ready/busy signal. RP
max is determined by the maximum value of tr.
Figure 40. Ready/busy AC waveform
ready VDD
VOH
VOL
busy
tr
tf
NI3087B
Figure 41. Ready/busy load circuit
VDD
RP
ibusy
DEVICE
RB
Open Drain Output
VSS
AI07563B
65/72
DC and AC parameters
NAND04G-B2D, NAND08G-BxC
Figure 42. Resistor value versus waveform timings for ready/busy signal
1. T = 25 °C.
12.2
Data protection
The Numonyx NAND devices are designed to guarantee data protection during power
transitions.
A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold.
In the VDD range from VLKO to the lower limit of nominal range, the WP pin should be kept
low (VIL) to guarantee hardware protection during power transitions as shown in the below
figure.
Figure 43. Data protection
VDD
Nominal Range
VLKO
Locked
Locked
W
Ai11086
66/72
NAND04G-B2D, NAND08G-BxC
13
Package mechanical
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 44. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing is not to scale.
Table 32.
TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data
Millimeters
Inches
Symbol
Typ
Min
A
Max
Typ
Min
1.20
Max
0.047
A1
0.10
0.05
0.15
0.004
0.002
0.006
A2
1.00
0.95
1.05
0.039
0.037
0.041
B
0.22
0.17
0.27
0.009
0.007
0.011
0.10
0.21
0.004
0.008
C
CP
0.08
0.003
D1
12.00
11.90
12.10
0.472
0.468
0.476
E
20.00
19.80
20.20
0.787
0.779
0.795
E1
18.40
18.30
18.50
0.724
0.720
0.728
e
0.50
–
–
0.020
–
L
0.60
0.50
0.70
0.024
0.020
0.028
L1
0.80
a
3°
0°
5°
0.031
0°
5°
3°
67/72
Package mechanical
NAND04G-B2D, NAND08G-BxC
Figure 45. ULGA52 12 x 17 x 0.65 mm, 1 mm pitch, package outline
D
FD1
D2
D1
FD
FE1
FE
BALL "A1"
eE1
E E2
E1
e
e
ddd
b1 b2
A
A2
LGA-ME
1. Drawing is not to scale.
Table 33.
ULGA52 12 x 17 x 0.65 mm, 1 mm pitch, package mechanical data
Millimeters
Inches
Symbol
Typ
Min
Typ
Min
Max
A
0.65
0.026
A2
0.65
0.026
b1
0.70
0.65
0.75
0.028
0.026
0.029
b2
1.00
0.95
1.05
0.039
0.037
0.041
D
12.00
11.90
12.10
0.472
0.468
0.476
D1
6.00
0.236
D2
10.00
0.394
ddd
68/72
Max
0.10
16.90
17.10
0.004
E
17.00
0.669
E1
12.00
0.472
E2
13.00
0.512
0.665
0.673
e
1.00
–
–
0.039
–
–
eE1
2.00
–
–
0.079
–
–
FD
3.00
0.118
FD1
1.00
0.039
FE
2.50
0.098
FE1
2.00
0.079
NAND04G-B2D, NAND08G-BxC
14
Ordering information
Ordering information
Table 34.
Ordering information scheme
Example:
NAND04GW3B2D N
6
E
Device type
NAND flash memory
Density
04G = 4 Gbits
08G = 8 Gbits
Operating voltage
W = VDD = 2.7 to 3.6 V
R = VDD = 1.7 to 1.95 V
Bus width
3 = x8
4 = x16(1)
Family identifier
B = 2112-byte page
Device options
2 = Chip Enable ‘don't care’ enabled
4 = Chip Enable ‘don’t care’ enabled with dual interface
Product version
C= third version (NAND08G-BxC)
D = fourth version (NAND04G-B2D)
Package
N = TSOP48 12 x 20 mm
ZL = ULGA52 12 x 17 x 0.65 mm
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape and reel packing
1. x16 organization only available for MCP products
Note:
Not all combinations are necessarily available. For a list of available devices of for further
information on any aspect of these products, please contact your nearest Numonyx sales
office.
69/72
Revision history
15
NAND04G-B2D, NAND08G-BxC
Revision history
Table 35.
70/72
Document revision history
Date
Revision
Changes
22-June-2007
1
Initial release.
17-Sep-2007
2
Added the part numbers NAND08GR3B4C, NAND08GW3B4C,
therefore referring to the 8-Gbit devices as the NAND08G-BxC.
Modified all data throughout this document to reflect the addition
of these part numbers, namely:
– Table 1, Table 2, Table 6, and Table 34.
– Added Figure 5: ULGA52 connections for the NAND08G-B4C
devices.
Changed VLKO value in Table 28 from 1.1 to 1.2.
10-Dec-2007
3
Applied Numonyx branding.
23-Apr-2008
4
Modified: Figure 6: Memory array organization, Figure 13:
Multiplane page program waveform, Figure 17: Multiplane copy
back program, Figure 19: Multiplane block erase, Figure 30:
Read status enhanced waveform, Figure 37: Program/erase
enable waveform, Figure 38: Program/erase disable waveform,
and Figure 42: Resistor value versus waveform timings for
ready/busy signal, Section 6.2: Cache read, Section 6.4:
Multiplane page program, Section 6.5: Copy back program,
Section 6.8: Multiplane block erase and Section 6.15: Read
ONFI signature, Table 24: Program erase times and program
erase endurance cycles and Table 26: Operating and AC
measurement conditions.
Added ECOPACK text in Section 13: Package mechanical.
Removed ‘or ECC’ from Program failure in Table 23: Block
failure.
Minor text changes.
07-May-2008
5
Document status promoted from preliminary data to datasheet.
Modified : Bad blocks in Section 2: Memory array organization.
11-Mar-2009
6
Added security features on the cover page and in Section 1:
Description. Modified Figure 40: Ready/busy AC waveform and
Figure 42: Resistor value versus waveform timings for
ready/busy signal.
References to ECOPACK packages removed and replaced by
references to RoHS compliance throughout the document.
15-Jun-2009
7
Modified Figure 45: ULGA52 12 x 17 x 0.65 mm, 1 mm pitch,
package outline. Minor text changes.
NAND04G-B2D, NAND08G-BxC
Table 35.
Revision history
Document revision history (continued)
Date
05-Jan-2010
09-Feb-2010
Revision
Changes
8
Modified: EDC paragraph in Section 1: Description, Section 9.1:
Bad block management, Note 1 below Table 28 and Table 29,
Section 9.5: Error correction code, Figure 17: Multiplane copy
back program.
Removed Fig.23 Error detection.
9
Removed Note 1 below Figure 1: Logic block diagram, Figure 2:
Logic diagram, Table 3: Signals names, and Figure 5: ULGA52
connections for the NAND08G-B4C devices.
Modified Figure 6: Memory array organization.
71/72
NAND04G-B2D, NAND08G-BxC
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Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
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Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
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