NAND08GAH0J
NAND16GAH0H
1-Gbyte, 2-Gbyte, 1.8 V/3.3 V supply,
NAND flash memories with MultiMediaCard™ interface
Preliminary Data
Features
■
Packaged NAND flash memory with
MultiMediaCard interface
LFBGA153
■
Up to 2 Gbytes of formatted data storage
■
eMMC/MultiMediaCard system specification,
compliant with V4.3
■
Full backward compatibility with previous
MultiMediaCard system specification
■
Bus mode
– High-speed MultiMediaCard protocol
– Three different data bus widths:1 bit, 4 bits,
8 bits
– Data transfer rate: up to 52 Mbyte/s
■
Operating voltage range:
– VCCQ =1.8 V/3.3 V
– VCC = 3.3 V
■
Multiple block read (x8 at 52 MHz):
up to 15 Mbyte/s
■
Multiple block write (x8 at 52 MHz):
up to 6 Mbyte/s
■
Power dissipation
– Standby current: down to 200 µA (typ)
– Read current: down to 40 mA (typ)
– Write current: down to 100 mA (typ)
Table 1.
LFBGA153 11.5 x 13 x 1.3 mm (ZC)
LFBGA169
LFBGA169 12 x 16 x 1.4 mm (ZA)
■
Error free memory access
– Internal error correction code
– Internal enhanced data management
algorithm (wear levelling, bad block
management, garbage collection)
– Possibility for the host to make sudden
power failure safe-update operations for
data content
■
Security
– Password protection of data
– Built-in write protection
■
Boot
– Simple boot sequence method
■
Power save
– Enhanced power saving method by
introducing sleep functionality
Device summary
Root part number
Package
NAND08GAH0J
LFBGA153
NAND16GAH0H
LFBGA169
February 2009
Operating voltage
VCC = 3.3 V, VCCQ = 1.8 V/3.3 V
Rev 5
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/32
www.numonyx.com
1
Contents
NAND08GAH0J, NAND16GAH0H
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
2
Product specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
3
eMMC Standard Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
System performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Device physical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1
Package connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4
Memory array partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5
MultiMediaCard interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1
6
2/32
Signals description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.1
Clock (CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.2
Command (CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.3
Input/outputs (DAT0-DAT7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.4
VCC core supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.5
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1.6
VCCQ input/output supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.7
VSSQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.2
Bus topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.5
Bus operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.6
Bus signal levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.7
Bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
High speed MultiMediaCard operation . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1
Boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2
Identification mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.3
Data transfer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.4
Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NAND08GAH0J, NAND16GAH0H
7
Contents
6.5
Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.6
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.7
State transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.8
Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.9
Timing diagrams and values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.10
Minimum performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1
Operation conditions register (OCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3
Card specific data register (CSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.4
Extended CSD register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.5
RCA (relative card address) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.6
DSR (driver stage register) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.7
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
List of tables
NAND08GAH0J, NAND16GAH0H
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
4/32
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
System performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Communication channel performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
OCR register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Card identification (CID) register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Card specific data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Extended CSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LFBGA153 11.5 x 13 x 1.3 mm 132+21 3R14 - 0.50 mm, mechanical data . . . . . . . . . . . 27
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, mechanical data . . . . . . . . . . . 29
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
NAND08GAH0J, NAND16GAH0H
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
LFBGA153 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . 9
LFBGA169 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . 10
Form factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Memory array structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LFBGA153 11.5 x 13 x 1.3 mm 132+21 3R14 - 0.50 mm, package outline . . . . . . . . . . . . 26
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline . . . . . . . . . . . 28
5/32
Description
1
NAND08GAH0J, NAND16GAH0H
Description
The NANDxxxAH0H/J is an embedded flash memory storage solution with
MultiMediaCard™ interface (eMMC™). The eMMC™ was developed for universal low-cost
data storage and communication media. The NANDxxxAH0H/J is fully compatible with MMC
bus and hosts.
The NANDxxxAH0H/J communications are made through an advanced 13-pin bus. The bus
can be either 1-bit, 4-bit, or 8-bit in width. The device operates in high-speed mode at clock
frequencies equal to or higher than 20 MHz, which is the MMC standard. The
communication protocol is defined as a part of this MMC standard and referred to as
MultiMediaCard mode.
The device is designed to cover a wide area of applications such as smart phones,
cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They
feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications,
the NANDxxxAH0H/J supports both 3.3 V supply voltage (VCC), and 1.8 V/3.3 V
input/output voltage (VCCQ).
The address argument for the NANDxxxAH0H/J is the byte address.
The device has a built-in intelligent controller which manages interface protocols, data
storage and retrieval, wear leveling, bad block management, garbage collection, and
internal ECC.
The NANDxxxAH0H/J makes available to the host sudden power failure safe-update
operations for the data content, by supporting reliable write features.
The device supports boot operation and sleep/awake commands. In particular, during the
sleep state the host power regulator for VCC can be switched off, thus minimizing the power
consumption of the NANDxxxAH0H/J.
The system performance and characteristics are given in Table 2, Table 3, and Table 4.
1.1
eMMC Standard Specification
The NANDxxxAH0H/J device is fully compatible with the JEDEC Standard Specification No.
JESD84-A43.
This datasheet describes the key and specific features of the NANDxxxAH0H/J device. Any
additional information required to interface the device to a host system and all the practical
methods for card detection and access can be found in the proper sections of the JEDEC
Standard Specification.
6/32
NAND08GAH0J, NAND16GAH0H
2
Product specification
2.1
System performance
Table 2.
System performance
Product specification
Typical value(1)
System performance
Unit
NAND08GAH0J, NAND16GAH0H
Multiple block read sequential(2)
Multiple block read 64-Kbyte chunk
(3)
Multiple block write sequential(2)
Multiple block write 64-Kbyte chunk
(3)
15
Mbyte/s
10.5
Mbyte/s
6
Mbyte/s
2.8
Mbyte/s
1. Values given for an 8-bit bus width, a clock frequency of 52 MHz, VCC = 3.3 V and VCCQ = 1.8 V.
2. Based on a 4-Mbyte file transfer.
3. Test performed by writing/reading a 64-Kbyte chunk of data to/from random logical addresses (aligned to physical block
boundaries) of the card. The performance is calculated as an average out of several 64-Kbyte accesses.
Table 3.
Current consumption
Current consumption(1)
Operation
Test conditions
Read
Write
Standby
NAND08GAH0J
NAND16GAH0H
Typ
Max
Typ
Max
VCC= 3.3 V ± 5%
VCCQ = 1.8 V ± 5%
40
80
40
80
100
150
100
150
VCC = 3.3 V ± 5%
10
10
VCCQ = 1.8 V ± 5%
80
80
Unit
mA
µA
1. Values given for an 8-bit bus width and a clock frequency of 26 MHz.
Table 4.
Communication channel performance
MultiMediaCard communication channel performance
Three-wire serial data bus (clock, command, data)
Variable clock rate 0, 26, 52 MHz
Easy card identification
Error protected data transfer
Sequential and single/multiple block oriented data transfer
7/32
Device physical description
3
NAND08GAH0J, NAND16GAH0H
Device physical description
The NANDxxxAH0H/J contains a single chip controller and flash memory module, see
Figure 1: Device block diagram. The microcontroller interfaces with a host system allowing
data to be written to and read from the flash memory module. The controller allows the host
to be independent from details of erasing and programming the flash memory.
Figure 3 shows the package connections. See Table 5: Signal names for the description of
the signals corresponding to the balls.
Figure 1.
Device block diagram
Data
I/O
MultiMediaCard
interface
Numonyx
single chip
microcontroller
Control
Flash
module
AI13614e
8/32
NAND08GAH0J, NAND16GAH0H
Device physical description
3.1
Package connections
Figure 2.
LFBGA153 package connections (top view through package)
1
2
3
4
A
NC
NC
DAT0
DAT1
B
NC
DAT3
DAT4
C
NC
VCCI
D
NC
E
5
6
7
8
9
10
11
DAT2
NC
NC
NC
NC
NC
NC
DAT5
DAT6
DAT7
NC
NC
NC
NC
NC
VSSQ
NC
VCCQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
F
NC
NC
NC
G
NC
NC
H
NC
J
13
14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
VSS
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
NC
K
NC
NC
NC
NC
NC
NC
NC
NC
L
NC
NC
NC
NC
NC
NC
M
NC
NC
NC
VCCQ
CMD
CLK
NC
NC
NC
NC
NC
NC
NC
NC
N
NC
VSSQ
NC
VCCQ
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
P
NC
NC
VCCQ
VSSQ
VCCQ
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
VSS
NC
NC
VSS
NC
VCC
12
AI13625
1. The ball corresponding to VCCI must be decoupled with an external capacitance.
9/32
Device physical description
Figure 3.
NAND08GAH0J, NAND16GAH0H
LFBGA169 package connections (top view through package)
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
12
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCC
NC
NC
NC
8
NC
NC
NC
NC
VSS
NC
NC
NC
7
NC
NC
NC
VSS
NC
NC
NC
NC
NC
DAT7
VCCQ
VCC
NC
CLK
NC
VSSQ
DAT2
DAT6
NC
NC
NC
CMD
VSSQ
VCCQ
DAT1
DAT5
VSSQ
NC
VCCQ
VCCQ
VSSQ
DAT0
DAT4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VCCQ
NC
DAT3
VCCI
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSSQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
NC
14
NC
13
NC
10
9
6
NC
NC
5
4
NC
3
NC
2
1
NC
A
B
C
D
E
F
G
NC
VCC
NC
VSS
VSS
NC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NC
AB
AC
AD
AE
AF
AG
AH
AI13626
1. The ball corresponding to VCCI must be decoupled with an external capacitance.
3.2
Form factor
The ball diameter, d, and the ball pitch, p, for LFBGA153 and LFBGA169 packages are:
Figure 4.
●
d = 0.30 mm (solder ball diameter)
●
p = 0.5 mm (ball pitch)
Form factor
VCCQ
d
VSSQ
NC
NC
NC
p
AI13627
10/32
NAND08GAH0J, NAND16GAH0H
4
Memory array partitioning
Memory array partitioning
The basic unit of data transfer to/from the device is one byte. All data transfer
operations which require a block size always define block lengths as integer
multiples of bytes. Some special functions need other partition granularity.
For block oriented commands, the following definitions are used:
●
Block: the unit which is related to the block oriented read and write commands.
Its size is the number of bytes which are transferred when one block command
is issued by the host. The size of a block is either programmable or fixed. The
information about allowed block sizes and the programmability is stored in the
CSD register.
●
Erase group: the unit which is related to special erase and write commands
defined for R/W cards. Its size is the smallest number of consecutive write
blocks which can be addressed for erase. The size of the erase group depends
on each device and is stored in the CSD.
●
Write protect group: the smallest unit that may be individually write protected.
Its size is defined in units of erase groups. The size of a WP-group depends on
each device and is stored in the CSD.
Figure 5 shows the NANDxxxAH0H/J memory array organization.
Figure 5.
Memory array structure
Write protect group 0
Erase group 0
Block 0
Erase group 1
Erase group n
Write protect group 1
Write protect group 2
Write protect group n
MultiMediaCard
AI13615e
1. n = number of last erase group or last write protect group.
11/32
MultiMediaCard interface
5
NAND08GAH0J, NAND16GAH0H
MultiMediaCard interface
The signal/pin assignments are listed in Table 5. Refer to this table in conjunction with
Figure 3 and Figure 4: Form factor.
5.1
Signals description
5.1.1
Clock (CLK)
The Clock input, CLK, is used to synchronize the memory to the host during command and
data transfers. Each clock cycle gates one bit on the command and on all the data lines. The
Clock frequency, fPP, may vary between zero and the maximum clock frequency.
5.1.2
Command (CMD)
The CMD signal is a bidirectional command channel used for device initialization and
command transfer. The CMD signal has two operating modes: open-drain and push-pull.
The open-drain mode is used for initialization, while the push-pull mode is used for fast
command transfer. Commands are sent by the MultiMediaCard bus master (or host) to the
device who responds by sending back responses.
5.1.3
Input/outputs (DAT0-DAT7)
DAT0 to DAT7 are bidirectional data channels. The signals operate in push-pull mode. The
NANDxxxAH0H/J includes internal pull ups for all data lines. These signals cannot be driven
simultaneously by the host and the NANDxxxAH0H/J device. Right after entering the 4-bit
mode, the card disconnects the internal pull ups of lines DAT1 and DAT2 (DAT3 internal pull
up is left connected due to the SPI mode CS backward compatible usage). Correspondingly
right after entering the 8-bit mode, the card disconnects the internal pull ups of lines DAT1,
DAT2 and DAT4-DAT7.
By default, after power-up or hardware reset, only DAT0 is used for data transfers. The host
can configure the device to use a wider data bus, DAT0, DAT0-DAT3 or DAT0-DAT7, for data
transfer.
5.1.4
VCC core supply voltage
VCC provides the power supply to the internal core of the memory device. It is the main
power supply for all operations (read, program and erase). The core voltage (VCC) can be
within 2.7 V and 3.6 V.
5.1.5
VSS ground
Ground, VSS, is the reference for the power supply. It must be connected to the system
ground.
12/32
NAND08GAH0J, NAND16GAH0H
5.1.6
MultiMediaCard interface
VCCQ input/output supply voltage
VCCQ provides the power supply to the I/O pins and enables all outputs to be powered
independently from VCC.
The input/output voltage (VCCQ) can be either within 1.65/1.7 V and 1.95 V (low voltage
range) or 2.7 V and 3.6 V (high voltage range).
5.1.7
VSSQ supply voltage
VSSQ ground is the reference for the input/output circuitry driven by VCCQ.
Table 5.
Signal names
Name
Type(1)
DAT0
I/O (PP)
Data
DAT1
I/O (PP)
Data
DAT2
I/O (PP)
Data
DAT3
I/O (PP)
Data
DAT4
I/O (PP)
Data
DAT5
I/O (PP)
Data
DAT6
I/O (PP)
Data
DAT7
I/O (PP)
Data
CMD
I/O (OD or PP)
CLK
I (PP)
Description
Command
Clock
Input/output power supply
VCCQ
VCC
Core power supply
VSSQ
Input/output ground
VCCI
I
VSS
NC
Must be decoupled with an external capacitance
Ground
NC
Not connected(2)
1. I: input; O: output, OD: open drain, PP: push-pull.
2. NC pins can be connected to ground or left floating.
13/32
MultiMediaCard interface
5.2
NAND08GAH0J, NAND16GAH0H
Bus topology
The NANDxxxAH0H/J device supports the MMC protocol. For more details, refer to section
6.4 of the JEDEC Standard Specification No. JESD84-A43. The section 12 of the JEDEC
Standard Specification contains a bus circuitry diagram for reference.
5.3
Power-up
The power-up is handled locally in each device and in the bus master. Figure 6: Power-up
shows the power-up sequence. Refer to section 12.3 of the JEDEC Standard Specification
No. JESD84-A43 for specific instructions regarding the power-up sequence.
After power-up, the maximum initial load the NANDxxxAH0H/J can present on the VCC line
is C4, in parallel with a minimum of R4. During operation, device capacitance on the VCC
line must not exceed 10 µF.
5.4
Power cycling
The bus master can execute any sequences of VCC and VCCQ power-up/power down.
However, the master must not issue any commands until VCC and VCCQ are stable within
each operating voltage range. For more information about power cycling see Section 12.3.3
of the JEDEC Standard Specification No. JESD84-A43 and Figure 7: Power cycling.
14/32
NAND08GAH0J, NAND16GAH0H
Figure 6.
MultiMediaCard interface
Power-up
Supply
voltage
(3)
VCCmax
Memory
field
working
voltage
range
(3)
VCC
VCCmin(3)
VCCQmax(3)
Control logic
working
voltage range
(3)
VCCQmin
Time
Power-up
Supply
ramp-up
Initialization
sequence (1)
First CMD1 to card ready (2)
CMD1
NCC
CMD1
Initialization
delay
NCC
CMD1
CMD2
CMD1 repeated
until busy flag cleared
The longest of: 1 ms,
74 clock cycles,
supply ramp-up time,
or the boot operation period.
AI14104b
1. The initialization sequence is a contiguous stream of logic 1’s. Its length is either 1 ms, 74 clocks or the supply ramp up
time, whichever is the longest. The device shall complete its initialization within 1 second from the first CMD1 with a valid V
range.
2. NCC is the number of clock cycles.
3. Refer to Section 7.1: Operation conditions register (OCR) for details on voltage ranges.
Figure 7.
Power cycling
Supply
voltage
VCC
VCCmin
VCCQ
VCCQmin
Command input prohibited
Sleep mode
Command input prohibited
Time
AI14122b
15/32
MultiMediaCard interface
5.5
NAND08GAH0J, NAND16GAH0H
Bus operating conditions
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
5.6
Bus signal levels
Refer to section 12.6 of the JEDEC Standard Specification No. JESD84-A43.
5.7
Bus timing
Refer to section 12.7 of the JEDEC Standard Specification No. JESD84-A43.
16/32
NAND08GAH0J, NAND16GAH0H
6
High speed MultiMediaCard operation
High speed MultiMediaCard operation
All communication between the host and the device is controlled by the host (master).
The following section provides an overview of the identification and data transfer modes,
commands, dependencies, various operation modes and restrictions for controlling the clock
signal. For detailed information, refer to section 7 of the JEDEC Standard Specification No.
JESD84-A43.
6.1
Boot mode
The host can read boot data from NANDxxxAH0H/J by keeping CMD line Low after poweron or sending CMD0 with argument + 0xFFFFFFFA (optional for slave), before issuing
CMD1. The data can be read from either boot area or user area depending on the register
setting. Refer to section 7.2 of the JEDEC Standard Specification No. JESD84-A43.
6.2
Identification mode
When in card identification mode, the host resets the NANDxxxAH0H/J, validates the
operating voltage range and the access mode, identifies the device and assigns a relative
address (RCA) to it. For more information see section 7.3 of the JEDEC Standard
Specification No. JESD84-A43.
6.3
Data transfer mode
The device enters data transfer mode once an RCA is assigned to it. When the device is in
standby mode, issuing the CMD7 command along with the RCA, selects the device and puts
it into the transfer state. The host enters data transfer mode after identifying the
NANDxxxAH0H/J on the bus. When the device is in standby state, communication over the
CMD and DAT lines is in push-pull mode.
The section 7.5 of the JEDEC Standard Specification No. JESD84-A43 contains more
detailed information about data read and write, erase, write protect management,
lock/unlock operations, the switch function command, high speed mode selection, and bus
testing procedure. Moreover section 7.5.7 contains a detailed description of the reliable
write features supported by the NANDxxxAH0H/J.
6.4
Clock control
Refer to section 7.6 of the JEDEC Standard Specification No. JESD84-A43.
6.5
Error conditions
Refer to section 7.7 of the JEDEC Standard Specification No. JESD84-A43.
17/32
High speed MultiMediaCard operation
6.6
NAND08GAH0J, NAND16GAH0H
Commands
Refer to section 7.9 of the JEDEC Standard Specification No. JESD84-A43.
6.7
State transition
Refer to section 7.10 and 7.12 of the JEDEC Standard Specification No. JESD84-A43.
6.8
Response
Refer to section 7.11 of the JEDEC Standard Specification No. JESD84-A43.
6.9
Timing diagrams and values
Refer to section 7.14 of the JEDEC Standard Specification No. JESD84-A43.
6.10
Minimum performance
Refer to section 7.8 of the JEDEC Standard Specification No. JESD84-A43.
18/32
NAND08GAH0J, NAND16GAH0H
7
Device registers
Device registers
There are five different registers within the device interface:
●
Operation conditions register (OCR)
●
Card identification register (CID)
●
Card specific data register (CSD)
●
Relative card address register (RCA)
●
DSR (driver stage register)
●
Extended card specific data register (EXT_CSD).
These registers are used for the serial data communication and can be accessed only using
the corresponding commands (refer to section 7.9 of the JEDEC Standard Specification No.
JESD84-A43. The device does not implement the DSR register.
The MultiMediaCard has a status register to provide information about the device current
state and completion codes for the last host command.
7.1
Operation conditions register (OCR)
The 32-bit operation conditions register stores the VCCQ, the input/output voltage of the
flash memory component. The device is capable of communicating (identification procedure
and data transfer) with any MultiMediaCard host using any operating voltage within 1.7 V
and 1.95 V (low-voltage range) or 2.7 V and 3.6 V (high-voltage range) depending on the
voltage range supported by the host. For further details, refer to section 8.1 of the JEDEC
Standard Specification No. JESD84-A43.
If the host tries to change the OCR values during an initialization procedure the changes in
the OCR content will be ignored.
The level coding of the OCR register is as follows:
●
Restricted voltage windows = Low
●
Device busy = Low
Table 6.
OCR register definition
OCR bit
Description
MultiMediaCard
6 to 0
Reserved
000 0000b
7
Low VCCQ
1b
14 to 8
2.0 - 2.6
000 0000b
23 to 15
2.7 - 3.6 (High VCCQ range)
1 1111 1111b
28 to 24
Reserved
000 0000b
30 to 29
Access mode
00b (byte mode)
31
Power-up status bit (busy)(1)
1. This bit is set to Low if the device has not finished the power-up routine.
19/32
Device registers
7.2
NAND08GAH0J, NAND16GAH0H
Card identification (CID) register
The CID register is 16-byte long and contains a unique card identification number used
during the card identification procedure. It is a 128-bit wide register with the content as
defined in Table 7. It is programmed during device manufacturing and can not be changed
by MultiMediaCard hosts. For details, refer to section 8.2 of the JEDEC Standard
Specification No. JESD84-A43.
Table 7.
Card identification (CID) register
Name
Manufacturer ID
Field
Width
CID - slice
CID - value
MID
8
[127:120]
0xFE
6
[119:114]
Reserved
Card/BGA
CBX
2
[113:112]
0x01
OEM/application ID
OID
8
[111:104]
TBD
Product name
PNM
48
[103:56]
MMC01G, MMC02G
Product revision
PRV
8
[55:48]
Product serial number
PSN
32
[47:16]
TBD
Manufacturing date
MDT
8
[15:8]
TBD
CRC7 checksum
CRC
7
[7:1]
TBD
–
1
[0:0]
1
Not used, always ‘1’
7.3
Note
BGA
Card specific data register (CSD)
All the configuration information required to access the device data is stored in the CSD
register. The MSB bytes of the register contain the manufacturer data and the two least
significant bytes contains the host controlled data (the device copy, write protection and the
user ECC register).
The host can read the CSD register and alter the host controlled data bytes using the
SEND_CSD and PROGRAM_CSD commands.
In Table 8, the cell type column defines the CSD field as read only (R), one time
programmable (R/W) or erasable (R/W/E). The programmable part of the register (entries
marked by W or E) can be changed by command CMD27.
The copy bit in the CSD can be used to mark the device as an original or a copy. Once set it
cannot be cleared. The device can be purchased with the copy bit set (copy) or cleared,
indicating the device is a master.
The one time programmable (OTP) characteristic of the copy bit is implemented in the
MultiMediaCard controller firmware and not with a physical OTP cell.
For details, refer to section 8.3 of the JEDEC Standard Specification No. JESD84-A43.
20/32
NAND08GAH0J, NAND16GAH0H
Table 8.
Device registers
Card specific data register
Name
Field
Width
[bits]
Cell
type
CSD-slice
CSD-value
CSD structure
CSD_STRUCTURE
2
R
[127:126]
2
MultiMediaCard protocol
version
SPEC_VERS
4
R
[125:122]
4
2
R
[121:120]
TBD
Reserved
Data read access-time-1
TAAC
8
R
[119:112]
Data read access-time-2 in
CLK cycles (NSAC*100)
NSAC
8
R
[111:104]
Max. data transfer rate
TRAN_SPEED
8
R
[103:96]
50
Command classes
CCC
12
R
[95:84]
245
79
512 for
NAND08GAH0J
Max. read data block length
READ_BL_LEN
4
R
[83:80]
1024 for
NAND16GAH0H
Partial blocks for read allowed
READ_BL_PARTIAL
1
R
[79:79]
1
Write block misalignment
WRITE_BLK_MISALIGN
1
R
[78:78]
0x00
Read block misalignment
READ_BLK_MISALIGN
1
R
[77:77]
0
DSR implemented
DSR_IMP
1
R
[76:76]
0x00
2
R
[75:74]
TBD
Reserved
Device size
C_SIZE
12
R
[73:62]
According to device
density
Max. read current at VCC(min)
VDD_R_CURR_MIN
3
R
[61:59]
100 mA
Max. read current at VCC(max) VDD_R_CURR_MAX
3
R
[58:56]
200 mA
Max. write current at VCC(min)
3
R
[55:53]
100 mA
Max. write current at VCC(max) VDD_W_CURR_MAX
3
R
[52:50]
200 mA
Device size multiplier
C_SIZE_MULT
3
R
[49:47]
According to device
density
Erase group size
ERASE_GRP_SIZE
5
R
[46:42]
32
Erase group size multiplier
ERASE_GRP_MULT
5
R
[41:37]
32
Write protect group size
WP_GRP_SIZE
5
R
[36:32]
According to device
density
Write protect group enable
WP_GRP_ENABLE
1
R
[31:31]
1
Manufacturer default ECC
DEFAULT_ECC
2
R
[30:29]
TBD
Write speed factor
R2W_FACTOR
3
R
[28:26]
4
VDD_W_CURR_MIN
512 for
NAND08GAH0J
Max. write data block length
WRITE_BL_LEN
4
R
[25:22]
1024 for
NAND16GAH0H
21/32
Device registers
Table 8.
NAND08GAH0J, NAND16GAH0H
Card specific data register (continued)
Name
Field
Partial blocks for write allowed
WRITE_BL_PARTIAL
Width
[bits]
Cell
type
CSD-slice
CSD-value
1
R
[21:21]
0
[20:20]
TBD
Reserved
Content protection application
CONTENT_PROT_APP
1
R
[16:16]
0
File format group
FILE_FORMAT_GROUP
1
R/W
[15:15]
0
Copy flag (OTP)
COPY
1
R/W
[14:14]
0
Permanent write protection
PERM_WRITE_PROTECT
1
R/W
[13:13]
0
Temporary write protection
TMP_WRITE_PROTECT
1
R/W/E
[12:12]
0
File format
FILE_FORMAT
2
R/W
[11:10]
Hard disk like file
system with partition
table
ECC code 2 R/W/E none 0
ECC
2
R/W/E
[9:8]
0
CRC
CRC
7
R/W/E
[7:1]
TBD
1
–
[0:0]
TBD
Not used, always ‘1’
7.4
Extended CSD register
The extended CSD register defines the device properties and selected modes. It is 512-byte
long. The 320 most significant bytes are the properties segment that defines the device
capabilities and cannot be modified by the host. The 192 lower bytes are the modes
segment that defines the configuration the device is working in. For details, refer to section
8.4 of the JEDEC Standard Specification No. JESD84-A43.
These modes can be changed by the host by means of the Switch command.
Extended CSD(1)
Table 9.
Name
Field
Size (bytes)
Cell type
CSD-slice
CSD-slice
value
[511:505]
TBD
Properties segment
Reserved(2)
Supported command sets
7
S_CMD_SET
Reserved(2)
Boot information
BOOT_INFO
Reserved(2)
1
R
[504]
0
275
TBD
[503:229]
TBD
1
R
[228]
1
1
TBD
[227]
TBD
Boot partition size
BOOT_SIZE_MULTI
1
R
[226]
256 Kbytes
Access size
ACC_SIZE
1
R
[225]
0
High-capacity erase unit
size
HC_ERASE_GRP_SIZE
1
R
[224]
0
High-capacity erase
timeout
ERASE_TIMEOUT_MULT
1
R
[223]
0
1
R
[222]
1 sector
Reliable write sector count REL_WR_SEC_C
22/32
NAND08GAH0J, NAND16GAH0H
Device registers
Extended CSD(1) (continued)
Table 9.
Size (bytes)
Cell type
CSD-slice
CSD-slice
value
High-capacity write protect
HC_WP_GRP_SIZE
group size
1
R
[221]
0
Sleep current (VCC)
S_C_VCC
1
R
[220]
TBD
Sleep current (VCCQ)
S_C_VCCQ
1
R
[219]
TBD
1
TBD
[218]
TBD
1
R
[217]
TBD
1
TBD
[216]
TBD
4
R
[215:212]
0
[211]
TBD
Name
Field
(2)
Reserved
Sleep/awake timeout
S_A_TIMEOUT
Reserved(2)
Sector count
SEC_COUNT
Reserved(2)
1
Minimum write
performance for 8 bit at
52 MHz
MIN_PERF_W_8_52
1
R
[210]
8
Minimum read
performance for 8 bit at
52 MHz
MIN_PERF_R_8_52
1
R
[209]
8
Minimum write
performance for 8 bit at
26 MHz, for 4 bit at
52 MHz
MIN_PERF_W_8_26_4_5
2
1
R
[208]
8
Minimum read
performance for 8 bit at
26 MHz, for 4 bit at
52 MHz
MIN_PERF_R_8_26_4_5
2
1
R
[207]
8
Minimum write
performance for 4 bit at
26 MHz
MIN_PERF_W_4_26
1
R
[206]
8
Minimum read
performance for 4 bit at
26 MHz
MIN_PERF_R_4_26
1
R
[205]
8
[204]
TBD
Reserved(2)
1
Power class for 26 MHz at
3.6 V
PWR_CL_26_360
1
R
[203]
0
Power class for 52 MHz at
3.6 V
PWR_CL_52_360
1
R
[202]
0
Power class for 26 MHz at
1.95 V
PWR_CL_26_195
1
R
[201]
0
Power class for 52 MHz at
1.95 V
PWR_CL_52_195
1
R
[200]
0
[199:197]
TBD
[196]
3
[195]
TBD
[194]
2
Reserved(2)
Card type
3
CARD_TYPE
Reserved(2)
CSD structure version
1
R
1
CSD_STRUCTURE
1
R
23/32
Device registers
NAND08GAH0J, NAND16GAH0H
Extended CSD(1) (continued)
Table 9.
Name
Field
Reserved(2)
Extended CSD revision
Size (bytes)
Cell type
1
CSD-slice
CSD-slice
value
[193]
TBD
EXT_CSD_REV
1
R
[192]
2
CMD_SET
1
R/W
[191]
0
[190]
TBD
[189]
0
[188]
TBD
[187]
0
[186]
TBD
[185]
0
[184]
TBD
[183]
2
[182]
TBD
[181]
TBD
[180]
TBD
[179]
0
[178]
TBD
[177]
0
[176]
TBD
[175]
0
[174:0]
TBD
Modes segment
Command set
Reserved(2)
Command set revision
1
CMD_SET_REV
Reserved(2)
Power class
POWER_CLASS
HS_TIMING
BUS_WIDTH
ERASED_MEM_CONT
BOOT_CONFIG
BOOT_BUS_WIDTH
WO
1
RO
1
R/W
1
R/W
1
ERASE_GROUP_DEF
Reserved(2)
1. TBD stands for ‘to be defined’.
2. Reserved bits should read as ‘0’.
24/32
1
1
Reserved(2)
High-density erase group
definition
R/W
1
Reserved(2)
Boot bus width 1
1
1
Reserved(2)
Boot configuration
R/W
1
Reserved(2)
Erased memory content
1
1
Reserved(2)
Bus width mode
RO
1
Reserved(2)
High speed interface
timing
1
1
175
R/W
NAND08GAH0J, NAND16GAH0H
7.5
Device registers
RCA (relative card address) register
The writable 16-bit relative card address (RCA) register carries the device address assigned
by the host during the device identification. This address is used for the addressed host-card
communication after the device identification procedure. The default value of the RCA
register is ‘0x0001’. The value ‘0x0000’ is reserved to set all cards into the standby state
with CMD7. For details refer to section 8.5 of the JEDEC Standard Specification No.
JESD84-A43.
7.6
DSR (driver stage register) register
The 16-bit driver stage register (DSR) can be optionally used to improve the bus
performance for extended operating conditions (depending on parameters like bus length,
transfer rate or number of devices on the bus).
The CSD register contains the information concerning the DSR register usage.
The default value of the DSR register is ‘0x404’. For details refer to section 8.6 of the
JEDEC Standard Specification No. JESD84-A43.
7.7
Status register
The status register provides information about the device current state and completion
codes for the last host command. The device status can be explicitly read (polled) with the
SEND_STATUS command. The MultiMediaCard status register structure is defined in
section 7.12 of the JEDEC Standard Specification No. JESD84-A43.
25/32
Package mechanical
8
NAND08GAH0J, NAND16GAH0H
Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 8.
LFBGA153 11.5 x 13 x 1.3 mm 132+21 3R14 - 0.50 mm, package outline
D
D1
b
SE
E1
E
BALL "A1"
e
FE
A
ddd
FD
SD
e
A1
A2
NO_ME
1. Drawing is not to scale.
26/32
NAND08GAH0J, NAND16GAH0H
Table 10.
Package mechanical
LFBGA153 11.5 x 13 x 1.3 mm 132+21 3R14 - 0.50 mm, mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.30
A1
Max
0.052
0.15
0.006
A2
1.00
0.039
b
0.30
0.25
0.35
0.012
0.010
0.014
D
11.50
11.40
11.60
0.456
0.453
0.460
D1
6.50
0.256
ddd
0.08
12.90
13.10
–
–
0.010
E
13.00
0.516
0.512
0.520
E1
6.50
e
0.50
–
–
FD
2.5
0.099
FE
3.25
0.128
SD
0.25
–
–
SE
0.25
–
–
0.010
–
–
0.010
–
–
0.256
0.020
27/32
Package mechanical
Figure 9.
NAND08GAH0J, NAND16GAH0H
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, package outline
D
D1
SD
b
e
SE
E
E4
E3 E2
E1
ddd
FE
FE1
FE2
FE3
FD
e
FD1
FD2
FD3
A
A2
A1
DB_ME
1. Drawing is not to scale.
28/32
NAND08GAH0J, NAND16GAH0H
Table 11.
Package mechanical
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.40
A1
Max
0.055
0.15
0.006
A2
1.00
0.039
b
0.30
0.25
0.35
0.012
0.010
0.014
D
12.00
11.90
12.10
0.472
0.469
0.476
D1
6.50
0.256
ddd
E
0.08
16.00
15.90
16.10
0.003
0.630
E1
6.50
0.256
E2
10.50
0.413
E3
12.50
0.492
E4
13.50
0.531
e
0.50
FD
2.75
–
–
0.108
0.020
FD1
3.25
0.128
FD2
4.25
0.167
FD3
5.25
0.207
FE
4.75
0.187
FE1
2.75
0.108
FE2
1.75
0.069
0.626
0.634
–
–
FE3
1.25
SD
0.25
–
–
0.010
0.049
–
–
SE
0.25
–
–
0.010
–
–
29/32
Ordering information
9
NAND08GAH0J, NAND16GAH0H
Ordering information
Table 12.
Ordering information scheme
Example:
NAND 08GAH
0
J
ZC
5
E
Device type
NAND flash memory
Density
08G = 1 Gbyte
16G = 2 Gbytes
Operating voltage
A = VCC= 3.3 V, VCCQ = 1.8 V or 3.3 V
Memory type
H = eMMC
Device options
0 = no option
Product version
H = version H (for 2-Gbyte devices)
J = version J (for 1-Gbyte devices)
Package
ZC = LFBGA153 11.5 x 13 x 1.3 mm (only available for 1-Gbyte devices)
ZA = LFBGA169 12 x 16 x 1.4 mm (only available for 2-Gbyte devices)
Temperature range
5 = −25 to 85 °C
Packing
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape & reel packing
Note:
30/32
Other digits may be added to the ordering code for preprogrammed parts or other options.
Devices are shipped from the factory with the memory content bits erased to ’1’. For further
information on any aspect of the device, please contact your nearest Numonyx sales office.
NAND08GAH0J, NAND16GAH0H
10
Revision history
Revision history
Table 13.
Document revision history
Date
Revision
Changes
25-Sep-2008
1
Initial release.
18-Nov-2008
2
Document’s status promoted from target specification to preliminary
data. Modified Table 3: Current consumption.
03-Dec-2008
3
Modified Table 12: Ordering information scheme. Minor text
changes.
12-Jan-2009
4
Added silhouettes of packages on the cover page. Modified Figure 9:
LFBGA169 12 x 16 x 1.4 mm 132+21+16 3R14 0.50 mm, package
outline.
09-Feb-2009
5
Modified Figure 2: LFBGA153 package connections (top view
through package). Removed reference to ECOPACK packages.
31/32
NAND08GAH0J, NAND16GAH0H
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
32/32
工商网监
湘ICP备2023018690号
