128Mb: P5Q Serial PCM
Features
P5Q Serial Phase Change
Memory (PCM)
Features
• SPI bus compatible serial interface
• Maximum clock frequency
– 66 MHz (0°C to +70°C)
– 33 MHz (–30°C to +85°C)
• 2.7V to 3.6V single supply voltage
• Supports legacy SPI protocol and new quad I/O or
dual I/O SPI protocol
• Quad I/O frequency of 50 MHz, resulting in an
equivalent clock frequency up to 200 MHz
• Dual I/O frequency of 66 MHz, resulting in an
equivalent clock frequency up to 132 MHz
• Continuous READ of entire memory via single
instruction:
– Quad and dual output fast read
– Quad and dual input fast program
• Uniform 128Kb sectors (Flash emulation)
• WRITE operations
– 128Kb sectors ERASE (emulated)
– Legacy Flash PAGE PROGRAM
– Bit-alterable page WRITEs
– PAGE PROGRAM on all 1s (PRESET WRITEs)
• Write protections: protected area size defined by
four nonvolatile bits (BP0, BP1, BP2, and BP3)
• JEDEC-standard two-byte signature (DA18h)
• 128Mb density with SOIC16 package
• More than 1,000,000 WRITE cycles
• Phase change memory (PCM)
– Chalcogenide phase change storage element
– Bit-alterable WRITE operation
PDF: 09005aef8447d377/Source: 09005aef845b5cb5
pcm_spi_1.fm - Rev. E 3/11 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: P5Q Serial PCM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Serial Data Input (D/DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Serial Data Output (Q/DQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Chip Select (S#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Hold (HOLD#/DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Write Protect (W#/DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
SPI Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Operating Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
PAGE PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
DUAL INPUT FAST PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
QUAD INPUT FAST PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
SECTOR ERASE and BULK ERASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Polling During a WRITE, PROGRAM, or ERASE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Active Power and Standby Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Protocol-Related Protections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Hold Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WRITE ENABLE (WREN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE DISABLE (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
READ IDENTIFICATION (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ STATUS REGISTER (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
WRITE STATUS REGISTER (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
DUAL OUTPUT FAST READ (DOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
QUAD OUTPUT FAST READ (QOFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PAGE PROGRAM (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
DUAL INPUT FAST PROGRAM (DIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
QUAD INPUT FAST PROGRAM (QIFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
SECTOR ERASE (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BULK ERASE (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Power-Up and Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Initial Delivery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
DC and AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Endurance Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
PDF: 09005aef8447d377/Source: 09005aef845b5cb5
pcm_spiTOC.fm - Rev. E 3/11 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P5Q Serial PCM
Table of Contents
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
PDF: 09005aef8447d377/Source: 09005aef845b5cb5
pcm_spiTOC.fm - Rev. E 3/11 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P5Q Serial PCM
List of Figures
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
Figure 24:
Figure 25:
Figure 26:
Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
SO16 Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Bus Master and Memory Devices on the SPI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
SPI Modes Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Hold Condition Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
WRITE ENABLE (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
WRITE DISABLE (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . . .20
READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . .21
WRITE STATUS REGISTER (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ DATA BYTES (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . .24
FAST_READ Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . and Data-Out Sequence25
DUAL OUTPUT FAST READ Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
QUAD OUTPUT FAST READ Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PP Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
DIFP Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
QIFP Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
SE Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BE Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Serial Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Write Protect Setup and Hold Timing During WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .38
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
SO16 Wide – 16-Lead Plastic Small-Outline, 300 Mils Body Width, Package Outline . . . . . . . . . . . . .40
PDF: 09005aef8447d377/Source: 09005aef845b5cb5
pcm_spiLOF.fm - Rev. E 3/11 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P5Q Serial PCM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Sizes of Protected Areas. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Organization of Super Page Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READ IDENTIFICATION (RDID) Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Power-Up Timing and VWI Threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Endurance Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Capacitance1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SO16 wide – Wide - 16-Lead Plastic Small-Outline, 300 Mils Body Width, Mechanical Data . . . . . .40
Active Line Item Ordering Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
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128Mb: P5Q Serial PCM
Functional Description
Functional Description
P5Q serial phase change memory (PCM) is nonvolatile memory that stores information
through a reversible structural phase change in a chalcogenide material. The material
exhibits a change in material properties, both electrical and optical, when changed from
the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the case
of PCM, information is stored via the change in resistance that the chalcogenide material experiences when undergoing a phase change. The material also changes optical
properties after experiencing a phase change, a characteristic that has been successfully
mastered for use in current rewritable optical storage devices, such as rewritable CDs
and DVDs.
The P5Q serial PCM storage element consists of a thin film of chalcogenide contacted by
a resistive heating element. In PCM, the phase change is induced in the memory cell by
highly localized Joule heating caused by an induced current at the material junction.
During a WRITE operation, a small volume of the chalcogenide material is made to
change phase. The phase change is a reversible process and is modulated by the magnitude of injected current, the applied voltage, and the duration of the heating pulse.
Unlike other proposed alternative memories, P5Q serial PCM technology uses a conventional CMOS process with the addition of a few additional layers to form the memory
storage element. Overall, the basic memory manufacturing process used to make PCM is
less complex than that of NAND, NOR, or DRAM.
P5Q serial PCM combines the benefits of traditional floating gate Flash, both NOR-type
and NAND-type, with some of the key attributes of RAM and EEPROM. Like NOR Flash
and RAM technology, PCM offers fast random access times. Like NAND Flash, PCM has
the ability to write moderately fast, and like RAM and EEPROM, PCM supports bit-alterable WRITEs (overwrite). Unlike Flash, no separate erase step is required to change
information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile
with data retention compared with NOR Flash.
Product Features
P5Q serial PCM devices have 128Mb (16Mb x 8Mb) SPI phase change memory with
advanced write protection mechanisms, accessed by a high-speed, SPI-compatible bus.
The memory can be programmed from 1 to 64 bytes at a time using the PAGE
PROGRAM, DUAL INPUT FAST PROGRAM, and QUAD INPUT FAST PROGRAM instructions. It’s organized as 128 sectors that are further divided into 1024 pages each (131,072
total pages). For compatibility with Flash memory devices, P5Q serial PCM supports
SECTOR ERASE (128Kb sector) and BULK ERASE instructions.
In addition to BULK ERASE instructions, P5Q serial PCM supports four high-performance dual and quad input/output instructions that double or quadruple the transfer
bandwidth for READ and PROGRAM operations.
• DUAL OUTPUT FAST READ (DOFR) instructions read data up to 66 MHz using both
DQ0 and DQ1 pins as outputs.
• QUAD OUTPUT FAST READ (QOFR) instructions read data up to 50 MHz using DQ0,
DQ1, DQ2(W#), and DQ3(HOLD#) pins as outputs.
• DUAL INPUT FAST PROGRAM (DIFP) instructions program data up to 66 MHz using
both DQ0 and DQ1 pins as inputs.
• QUAD INPUT FAST PROGRAM (QIFP) instructions program data up to 50 MHz using
DQ0, DQ1, DQ2(W#), and DQ3(HOLD#) pins as inputs.
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128Mb: P5Q Serial PCM
Product Features
PCM P5Q serial PCM can be write protected by software using a mix of volatile and
nonvolatile protection features, depending on application needs. The protection granularity is 128Kb (sector granularity).
Figure 1:
Logic Diagram
VCC
D
Q
C
S#
W#
HOLD#
VSS
Figure 2:
SO16 Connections
HOLD#/DQ3
VCC
DU
DU
DU
DU
S#
DQ1
Notes:
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1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
C
DQ0
DU
DU
DU
DU
VSS
W#/DQ2
1. DU = Do not use. User must float these pins.
2. See “Package Dimensions” on page 40 for package dimensions and how to identify pins.
3. For SO8 package solutions, contact your Micron representative.
7
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128Mb: P5Q Serial PCM
Signal Names
Signal Names
Table 1:
Signal Names
Signal Name
C
D (DQ0)
Q (DQ1)
S#
W# (DQ2)
HOLD# (DQ3)
VCC
VSS
Standard x1 Mode
Dual Mode
Quad Mode
Function
Direction
Function
Direction
Function
Direction
Serial clock
Serial data
input
Serial data
output
Chip select
Write protect
Hold
Input
Input
Serial clock
Serial data I/O
Input
I/O1
Serial clock
Serial data I/O
Input
I/O1
Output
Serial data I/O
I/O1
Serial data I/O
I/O1
Chip select
Serial data I/O
Serial data I/O
Input
I/O1
I/O1
Notes:
Input
Input
Input
Chip select
Input
Write Protect
Input
Hold
Input
Supply voltage
Ground
1. Serves as an input during DUAL INPUT FAST PROGRAM (DIFP) and QUAD INPUT FAST PROGRAM (QIFP) instructions. Serves as an output during DUAL OUTPUT FAST READ (DOFR) and
QUAD OUTPUT FAST READ (QOFR) instructions.
Signal Descriptions
Serial Data Input (D/DQ0)
The serial data input signal (D/DQ0) transfers data serially into the device and receives
instructions, addresses, and the data to be programmed. Values are latched on the rising
edge of serial clock (C).
During the DUAL OUTPUT FAST READ (DOFR) and QUAD OUTPUT FAST READ
(QOFR) instructions, this pin is an output (DQ0). Data is shifted out on the falling edge
of the C.
Serial Data Output (Q/DQ1)
The serial data output signal (Q/DQ1) transfers data serially out of the device. Data is
shifted out on the falling edge of C.
During the DIFP and QIFP instructions, this pin is used for data input (DQ1). It is latched
on the rising edge of the C.
During the DOFR and QOFR instructions, this pin is used as data output (DQ1). Data is
shifted out on the falling edge of C.
Serial Clock (C)
The serial clock input signal (C) provides the timing of the serial interface. Instructions,
addresses, or data present at DQ0 are latched on the rising edge of C. Data on DQ1
changes after the falling edge of C.
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128Mb: P5Q Serial PCM
SPI Modes
Chip Select (S#)
When a chip select signal (S#) is HIGH, the device is deselected and DQ1 is High-Z.
Unless an internal PROGRAM, ERASE, or WRITE STATUS REGISTER cycle is in progress,
the device will be in standby power mode. Driving S# LOW enables the device, placing it
in active power mode.
After power-up, a falling edge on S# is required prior to the start of any instruction.
Hold (HOLD#/DQ3)
The hold signal (HOLD#) pauses any serial communications with the device without
deselecting the device. During the HOLD condition, DQ1 is High-Z, and DQ0 and C are
“Don’t Care.” To start the hold condition, the device must be selected with S# driven
LOW.
During QIFP instructions, this pin is used for data input (DQ3). It is latched on the rising
edge of the C. During QOFR instructions, this pin is used for data output (DQ3). Data is
shifted out on the falling edge of C.
Write Protect (W#/DQ2)
The write protect input signal (W#,DQ#2) freezes the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP3,
BP2, BP1, and BP0 bits of the status register).
During QIFP instructions, this pin is used for data input (DQ2). It is latched on the rising
edge of the C. During QOFR instructions, this pin is used for data output (DQ2). Data is
shifted out on the falling edge of C.
VCC Supply Voltage
VCC is the supply voltage.
VSS Ground
VSS is the reference for the VCC supply voltage.
SPI Modes
P5Q serial PCM devices can be driven by a microcontroller with its SPI peripheral
running in either of these two modes:
• CPOL = 0, CPHA = 0
• CPOL = 1, CPHA = 1
For these two modes, input data is latched in on the rising edge of C, and output data is
available from the falling edge of C. The difference between the two modes, as shown in
Figure 4 on page 11, is the clock polarity when the bus master is in standby mode and
not transferring data.
• C remains at 0 for (CPOL = 0, CPHA = 0)
• C remains at 1 for (CPOL = 1, CPHA = 1)
Figure 3 on page 10 is an example of three devices connected to an MCU on an SPI bus.
Only one device is selected at a time, so only one device drives the serial data output
(DQ1) line at a time; the other devices are High-Z. Resistors R (shown in Figure 3 on
page 10) ensure that the P5Q serial PCM is not selected if the bus master leaves the S#
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128Mb: P5Q Serial PCM
SPI Modes
line in the High-Z state. Because the bus master may enter a state where all inputs/
outputs are in High-Z at the same time (for example, when the bus master is reset), the
clock line (C) must be connected to an external pull-down resistor. As a result, when all
inputs/outputs become High-Z, the S# line is pulled HIGH, while the C line is pulled
LOW. This ensures that S# and C do not become HIGH at the same time and that the
t
SHCH requirement is met.
The typical value of R is 100kΩ, assuming that the time constant R × Cp (Cp = parasitic
capacitance of the bus line) is shorter than the time during which the bus master leaves
the SPI bus in High-Z.
Figure 3:
Bus Master and Memory Devices on the SPI Bus
VSS
VCC
R
SDO
SPI interface with
SDI
(CPOL, CPHA) =
SCK
(0, 0) or (1, 1)
VCC
C
SPI bus master
R
CS3
VCC
C
VCC
C
DQ1DQ0
VSS
DQ1 DQ0
VSS
DQ1DQ0
SPI memory
device
R
SPI memory
device
R
SPI memory
device
VSS
CS2 CS1
S#
Notes:
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W# HOLD#
S#
W# HOLD#
S#
W# HOLD#
1. W# and (HOLD# signals should be driven HIGH or LOW, as appropriate.
10
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128Mb: P5Q Serial PCM
SPI Modes
Figure 4:
SPI Modes Supported
CPOL CPHA
0
0
C
1
1
C
DQ0
MSB
DQ1
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MSB
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128Mb: P5Q Serial PCM
Operating Features
Operating Features
To better understand operating features of the P5Q serial PCM device, refer to the
following definitions:
• PROGRAM: P5Q serial PCM devices write only 0s of the user data to the array and
treat 1s as data masks. This is similar to programming on a floating gate Flash device.
• Bit-alterable WRITE: P5Q serial PCM devices write both 0s and 1s of the user data to
the array.
• PROGRAM on all 1s: Only 0s are written to the array, and 1s are treated as data masks.
PROGRAM on all 1s also requires that the entire page being written be previously set
to all 1s. PROGRAM on all 1s is also referred to as PRESET WRITE.
PAGE PROGRAM
To PROGRAM/WRITE one data byte, two instructions are required: WRITE ENABLE
(WREN), which is one byte; and a PAGE PROGRAM (PP) sequence, which consists of four
bytes plus data byte. This is followed by the internal PROGRAM cycle (of duration tPP).
To spread this overhead, the PP instruction allows up to 64 bytes to be programmed/
written at a time, provided that they lie in consecutive addresses on the same page of
memory.
For optimized timings, it is recommended to use the PP instruction to program all
consecutive targeted bytes in a single sequence versus using several PP sequences with
each containing only a few bytes (see “PAGE PROGRAM (PP)” on page 27 and Table 16
on page 37).
DUAL INPUT FAST PROGRAM
The DUAL INPUT FAST PROGRAM (DIFP) instruction makes it possible to PROGRAM/
WRITE up to 64 bytes using two input pins at the same time.
For optimized timings, it is recommended to use the DIFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several DIFP
sequences each containing only a few bytes.
QUAD INPUT FAST PROGRAM
The QUAD INPUT FAST PROGRAM (QIFP) instruction makes it possible to PROGRAM/
WRITE up to 64 bytes using four input pins at the same time.
For optimized timings, use the QIFP instruction to program all consecutive targeted
bytes in a single sequence rather than several QIFP sequences each containing only a
few bytes.
SECTOR ERASE and BULK ERASE
A sector can be erased to all 1s (FFh) at a time using the SECTOR ERASE (SE) instruction.
The entire memory can be erased using the BULK ERASE (BE) instruction. This starts an
internal ERASE cycle (of duration tSE or tBE).
The ERASE instruction must be preceded by a WREN instruction.
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128Mb: P5Q Serial PCM
Operating Features
Polling During a WRITE, PROGRAM, or ERASE Cycle
Additional improvements in the time to WRSR, PP, DIFP, QIFP, or ERASE (SE or BE) can
be achieved by not waiting for the worst case delay (tW, tPP, tSMEN, tSMEX, tSE, or tBE).
The write in progress (WIP) bit is provided in the status register so that the application
program can monitor its value, polling it to establish when the previous WRITE cycle,
PROGRAM cycle, or ERASE cycle is complete.
Active Power and Standby Power
When S# is LOW, the device is selected and is in the active power mode. When S# is
HIGH, the device is deselected, but could remain in the active power mode until all
internal cycles have completed (PROGRAM, ERASE, WRITE STATUS REGISTER). The
device then goes in to the standby power mode. The device consumption drops to ICC1.
Status Register
The status register contains a number of status and control bits that can be read or set
(as appropriate) by specific instructions. See “READ STATUS REGISTER (RDSR)” on
page 20 for a detailed description of the status register bits.
Protocol-Related Protections
The environments where nonvolatile memory devices are used can be very noisy, but
SPI devices cannot operate correctly in the presence of excessive noise. To help combat
this, the P5Q serial PCM features the following data protection mechanisms:
• Power on reset and an internal timer (tPUW) can provide protection against inadvertent changes while the power supply is outside the operating specification.
• PROGRAM, ERASE, and WRITE STATUS REGISTER are checked to ensure they consist
of a number of clock pulses that is a multiple of eight before they are accepted for
execution.
• All instructions that modify data must be preceded by a WREN instruction to set the
WEL bit. This bit is returned to its reset state by the following events:
– Power-up
– WRDI instruction completion
– WRSR instruction completion
– PP instruction completion
– DIFP instruction completion
– QIFP instruction completion
– SE instruction completion
– BE instruction completion
• The block protect bits and top/bottom bit enable part of the memory to be configured
as read-only. This is the software protect mode (SPM).
• The W# signal enables the block protect bits (BP3, BP2, BP1, BP0), top/bottom (TB)
bit, and status register write disable (SRWD) bit to be protected. This is the hardware
protected mode (HPM).
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128Mb: P5Q Serial PCM
Operating Features
Table 2:
Sizes of Protected Areas
Status Register Contents
Memory Content
TB Bit
BP Bit 3
BP Bit 2
BP Bit 1
BP Bit 0
Protected Area
Unprotected Area
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
All sectors1 (sectors 0 to 127)
Sectors 0 to 126
Sectors 0 to 125
Sectors 0 to 123
Sectors 0 to 119
Sectors 0 to 111
Sectors 0 to 95
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
X2
0
0
0
0
1
1
1
1
X2
1
X2
0
0
1
1
0
0
1
1
X2
1
X2
0
1
0
1
0
1
0
1
X2
None
Upper 128 (sector 127)
Upper 64 (sectors 126 to 127)
Upper 32 (sectors 124 to 127)
Upper 16 (sectors 120 to 127)
Upper 8 (sectors 112 to 127)
Upper quarter (sectors 96 to
127)
Upper half (sectors 64 to 127)
All sectors (sectors 0 to 127)
None
Lower 128 (sector 0)
Lower 64 (sectors 0 to 1)
Lower 32 (sectors 0 to 3)
Lower 16 (sectors 0 to 7)
Lower 8 (sectors 0 to 15)
Lower 4 (sectors 0 to 31)
Lower half (sectors 0 to 63)
All sectors (sectors 0 to 127)
Notes:
Sectors 0 to 63
None
All sectors1 (sectors 0 to 127)
Sectors 1 to 127
Sectors 2 to 127
Sectors 4 to 127
Sectors 8 to 127
Sectors 16 to 127
Sectors 32 to 127
Sectors 64 to 127
None
1. The device is ready to accept a BULK ERASE instruction if all block protect bits (BP3, BP2,
BP1, BP0) are 0.
2. X can be 0 or 1.
Hold Condition
The Hold (HOLD#) signal is used to pause any serial communications with the device
without resetting the clocking sequence. However, taking this signal LOW does not
terminate any WRITE STATUS REGISTER, PROGRAM, or ERASE cycle that is currently in
progress.
To enter the hold condition, the device must be selected, with S# LOW. The hold condition starts on the falling edge of the HOLD# signal, provided that this coincides with C
being LOW (as shown in Figure 5 on page 15). The hold condition ends on the rising
edge of the HOLD# signal, provided that this coincides with C being LOW.
If the falling edge does not coincide with C being LOW, the hold condition starts after the
next time C goes LOW. Similarly, if the rising edge does not coincide with C being LOW,
the hold condition ends after C next goes LOW (as shown in Figure 5 on page 15).
During the hold condition, DQ1 is High-Z, and DQ0 and C are “Don’t Care.”
Normally, the device is kept selected, with S# driven LOW, for the whole duration of the
hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the hold condition.
If S# goes HIGH while the device is in the hold condition, this has the effect of resetting
the internal logic of the device. To restart communication with the device, it is necessary
to drive HOLD# HIGH, and then to drive S# LOW. This prevents the device from going
back to the hold condition.
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128Mb: P5Q Serial PCM
Memory Organization
Figure 5:
Hold Condition Activation
C
HOLD#
Hold
condition
(standard use)
Hold
condition
(non-standard use)
Memory Organization
The memory is organized as:
• 16,772,216 bytes (8 bits each)
• 8 super page programming regions (16 sectors each)
• 128 sectors (128Kb each)
• 262,144 pages (64 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0) or written
(bit alterable: 1 can be altered to 0 and 0 can be altered to 1). The device is sector or bulk
erasable (bits are erased from 0 to 1).
Table 3:
Sector
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
Memory Organization
Address Range
FE0000
FC0000
FA0000
F80000
F60000
F40000
F20000
F00000
EE0000
EC0000
EA0000
E80000
E60000
E40000
E20000
E00000
DE0000
DC0000
DA0000
D80000
D60000
D40000
D20000
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Sector
FFFFFF
FDFFFF
FBFFFF
F9FFFF
F7FFFF
F5FFFF
F3FFFF
F1FFFF
EFFFFF
EDFFFF
EBFFFF
E9FFFF
E7FFFF
E5FFFF
E3FFFF
E1FFFF
DFFFFF
DDFFFF
DBFFFF
D9FFFF
D7FFFF
D5FFFF
D3FFFF
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
15
Address Range
CC0000
CA0000
C80000
C60000
C40000
C20000
C00000
BE0000
BC0000
BA0000
B80000
B60000
B40000
B20000
B00000
AE0000
AC0000
AA0000
A80000
A60000
A40000
A20000
A00000
CDFFFF
CBFFFF
C9FFFF
C7FFFF
C5FFFF
C3FFFF
C1FFFF
BFFFFF
BDFFFF
BBFFFF
B9FFFF
B7FFFF
B5FFFF
B3FFFF
B1FFFF
AFFFFF
ADFFFF
ABFFFF
A9FFFF
A7FFFF
A5FFFF
A3FFFF
A1FFFF
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128Mb: P5Q Serial PCM
Memory Organization
Table 3:
Sector
104
103
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
7
6
5
4
Memory Organization (continued)
Address Range
D00000
CE0000
9A0000
980000
960000
940000
920000
900000
8E0000
8C0000
8A0000
880000
860000
840000
820000
800000
7E0000
7C0000
7A0000
780000
760000
740000
720000
700000
6E0000
6C0000
6A0000
680000
660000
640000
620000
600000
5E0000
5C0000
5A0000
580000
560000
0E0000
0C0000
0A0000
080000
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Sector
D1FFFF
CFFFFF
9BFFFF
99FFFF
97FFFF
95FFFF
93FFFF
91FFFF
8FFFFF
8DFFFF
8BFFFF
89FFFF
87FFFF
85FFFF
83FFFF
81FFFF
7FFFFF
7DFFFF
7BFFFF
79FFFF
77FFFF
75FFFF
73FFFF
71FFFF
6FFFFF
6DFFFF
6BFFFF
69FFFF
67FFFF
65FFFF
63FFFF
61FFFF
5FFFFF
5DFFFF
5BFFFF
59FFFF
57FFFF
0FFFFF
0DFFFF
0BFFFF
09FFFF
79
78
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
3
2
1
0
16
Address Range
9E0000
9C0000
540000
520000
500000
4E0000
4C0000
4A0000
480000
460000
440000
420000
400000
3E0000
3C0000
3A0000
380000
360000
340000
320000
300000
2E0000
2C0000
2A0000
280000
260000
240000
220000
200000
1E0000
1C0000
1A0000
180000
160000
140000
120000
100000
060000
040000
020000
000000
9FFFFF
9DFFFF
55FFFF
53FFFF
51FFFF
4FFFFF
4DFFFF
4BFFFF
49FFFF
47FFFF
45FFFF
43FFFF
41FFFF
3FFFFF
3DFFFF
3BFFFF
39FFFF
37FFFF
35FFFF
33FFFF
31FFFF
2FFFFF
2DFFFF
2BFFFF
29FFFF
27FFFF
25FFFF
23FFFF
21FFFF
1FFFFF
1DFFFF
1BFFFF
19FFFF
17FFFF
15FFFF
13FFFF
11FFFF
07FFFF
05FFFF
03FFFF
01FFFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P5Q Serial PCM
Instructions
Table 4:
Organization of Super Page Regions
Programming Region
Sectors
Address Range
7
6
5
4
3
2
1
0
112 to 127
96 to 111
80 to 95
64 to 79
48 to 63
32 to 47
16 to 31
0 to 15
E00000 to FFFFFF
C00000 to DFFFFF
A00000 to BFFFFF
800000 to 9FFFFF
600000 to 7FFFFF
400000 to 5FFFFF
200000 to 3FFFFF
000000 to 1FFFFF
Instructions
All instructions, addresses, and data are shifted in and out of the device, most significant
bit first.
Serial data input DQ0 is sampled on the first rising edge of C after S# is driven LOW.
Then, the one-byte instruction code must be shifted in to the device, most significant bit
first, on serial data input DQ0, each bit being latched on the rising edges of C. The
instruction set is listed in Table 5 on page 17.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, data bytes, both, or none.
In the case of read data bytes (READ), read data bytes at higher speed (FAST_READ),
DOFR, QOFR, RDSR, or READ IDENTIFICATION (RDID) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. S# can be driven HIGH after
any bit of the data-out sequence is being shifted out.
In the case of a PP, DIFP, QIFP, SE, BE, WRSR, WREN, or WRDI, S# must be driven HIGH
exactly at a byte boundary; otherwise the instruction is rejected and is not executed.
That is, S# must be driven HIGH when the number of clock pulses after S# being driven
LOW is an exact multiple of eight.
All attempts to access the memory array during a WRITE STATUS REGISTER cycle,
PROGRAM cycle, or ERASE cycle are ignored and the internal WRITE STATUS REGISTER
cycle, PROGRAM cycle, ERASE cycle continues unaffected.
Note:
Table 5:
Instruction
WREN
WRDI
RDID
RDSR
WRSR
READ
FAST_READ
DOFR
Output High-Z is defined as the point where data out is no longer driven.
Instruction Set
Description
One-Byte Instruction Code
0000 0110
0000 0100
1001 1111
1001 1110
0000 0101
0000 0001
0000 0011
0000 1011
0011 1011
Write enable
Write disable
Read identification
Read status register
Write status register
Read data bytes
Read data bytes at higher speed
Dual output fast read
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06h
04h
9Fh
9Eh
05h
01h
03h
0Bh
3Bh
Address
Bytes
Dummy
Bytes
Data
Bytes
0
0
0
0
0
0
3
3
3
0
0
0
0
0
0
0
1
1
0
0
1 to 3
1 to 3
1 to ∞
1
1 to ∞
1 to ∞
1 to ∞
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128Mb: P5Q Serial PCM
Instructions
Table 5:
Instruction
QOFR
PP
DIFP
QIFP
SE
BE
Instruction Set (continued)
Description
One-Byte Instruction Code
Quad output fast read
Page program (legacy program)
Page program (bit-alterable write)
Page program (on all 1s)
Dual input fast program (legacy
program)
Dual input fast program (bit-alterable
write)
Dual input fast program (on all 1s)
Quad input fast program (legacy
program)
Quad input fast program (bit-alterable
write)
Quad input fast program (on all 1s)
Sector erase
Bulk erase
Address
Bytes
Dummy
Bytes
Data
Bytes
0110 1011
0000 0010
0010 0010
1101 0001
1010 0010
6Bh
02h
22h
D1h
A2h
3
3
3
3
3
1
0
0
0
0
1 to ∞
1 to 64
1 to 64
1 to 64
1 to 64
1101 0011
D3h
3
0
1 to 64
1101 0101
0011 0010
D5h
32h
3
3
0
0
1 to 64
1 to 64
1101 0111
D7h
3
0
1 to 64
1101 1001
1101 1000
1100 0111
D9h
D8h
C7h
3
3
0
0
0
0
1 to 64
0
0
WRITE ENABLE (WREN)
The WRITE ENABLE (WREN) instruction sets the WEL bit. The WEL bit must be set prior
to every PP, DIFP, SE, BE, or WRSR instruction.
The WREN instruction is entered by driving S# LOW, sending the instruction code, and
then driving S# HIGH.
Figure 6:
WRITE ENABLE (WREN) Instruction Sequence
S#
0
1
2
3
4
5
6
7
C
Command
DQ0
High-Z
DQ1
WRITE DISABLE (WRDI)
The WRITE DISABLE (WRDI) instruction resets the WEL bit. The WRDI instruction is
entered by driving S# LOW, sending the instruction code, and then driving S# HIGH.
The WEL bit is reset under the following conditions:
• Power-up
• WRDI instruction completion
• WRSR instruction completion
• PP instruction completion
• DIFP instruction completion
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128Mb: P5Q Serial PCM
Instructions
• QIFP instruction completion
• SE instruction completion
• BE instruction completion
Figure 7:
WRITE DISABLE (WRDI) Instruction Sequence
S#
0
1
2
3
4
5
6
7
C
Command
DQ0
DQ1
High-Z
READ IDENTIFICATION (RDID)
The READ IDENTIFICATION (RDID) instruction enables devices to read the device
identification data, including manufacturer identification (1 byte) and device identification (2 bytes).
The manufacturer identification is assigned by JEDEC and has the value 20h for Micron.
Any RDID instruction while an ERASE or PROGRAM cycle is in progress is not decoded
and has no effect on the cycle that is in progress.
The device is first selected by driving S# LOW. Then, the 8-bit instruction code for the
instruction is shifted in. After this, the 24-bit device identification stored in the memory
will be shifted out on serial data output (DQ1). Each bit is shifted out during the falling
edge of C. The instruction sequence is shown in Figure 8 on page 20.
The RDID instruction is terminated by driving S# HIGH at any time during data output.
When S# is driven HIGH, the device is put in the standby power mode. After the device is
in the standby power mode, the device waits to be selected so that it can receive, decode,
and execute instructions.
Table 6:
READ IDENTIFICATION (RDID) Data-Out Sequence
Device identification
Manufacturer Identification
Memory Type (Upper Byte)
Memory Capacity (Lower Byte)
20h
DAh
18h
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128Mb: P5Q Serial PCM
Instructions
Figure 8:
READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
C
Command
DQ0
Manufacturer identification
High-Z
DQ1
Device identification
15 14 13
MSB
3
2
1
0
MSB
READ STATUS REGISTER (RDSR)
The READ STATUS REGISTER (RDSR) instruction enables the status register to be read.
The status register may be read at any time, even while a PROGRAM, ERASE, or WRITE
STATUS REGISTER cycle is in progress. When one of these cycles is in progress, it is
recommended to check the WIP bit before sending a new instruction to the device. It is
also possible to read the status register continuously, as shown in Figure 9 on page 21.
RDSR is the only instruction accepted by the device while a PROGRAM, ERASE, WRITE
STATUS REGISTER operation is in progress.
Table 7:
Status Register Format
b7
SRWD
b0
BP3
TB
BP2
BP1
BP0
WEL
WIP
Status register write protect
Top/bottom bit
Block protect bits
Write enable latch bit
Write in progress bit
The status and control bits of the status register are described below.
WIP Bit
The write in progress (WIP) bit indicates whether the memory is busy with a WRITE
STATUS REGISTER, PROGRAM, or ERASE cycle. When set to 1, one of these cycles is in
progress; when reset to 0, none of these cycles is in progress. While WIP is 1, RDSR is the
only instruction the device will accept; all other instructions are ignored.
WEL Bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
When set to 1, the internal write enable latch is set. When it is set to 0, the internal write
enable latch is reset, and no WRITE STATUS REGISTER, PROGRAM, or ERASE instruction is accepted.
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128Mb: P5Q Serial PCM
Instructions
Block Protect Bits
The block protect bits (BP3, BP2, BP1, BP0) are nonvolatile. They define the size of the
area to be software protected against PROGRAM (or WRITE) and ERASE instructions.
These bits are written with the WRSR instruction. When one or more of the block protect
bits is set to 1, the relevant memory area (as defined in Table 2 on page 14) becomes
protected against PP, DIFP, QIFP, and SE instructions. The block protect bits can be
written, provided that the hardware protected mode has not been set. The BE instruction is executed if all block protect bits are 0.
Top/Bottom Bit
The top/bottom (TB) bit is nonvolatile. It can be set and reset with the WRSR instruction, provided that the WREN instruction has been issued. The TB bit is used in conjunction with the block protect bits to determine if the protected area defined by the block
protect bits starts from the top or the bottom of the memory array.
• When TB bit is reset to 0 (default value), the area protected by the block protect bits
starts from the top of the memory array (see Table 2 on page 14)
• When TB bit is set to 1, the area protected by the block protect bits starts from the
bottom of the memory array (see Table 2 on page 14).
The TB bit cannot be written when the SRWD bit is set to 1 and the W# pin is driven
LOW.
SRWD Bit
The status register write disable (SRWD) bit is operated in conjunction with the W#
signal. The SRWD bit and the W# signal allow the device to be put in the hardware
protected mode (when the SRWD bit is set to 1 and W# is driven LOW). In this mode, the
nonvolatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only
bits and the WRSR instruction is no longer accepted for execution.
Figure 9:
READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Command
DQ0
DQ1
Status register out
Status register out
High-Z
7
6
5
4
MSB
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
WRITE STATUS REGISTER (WRSR)
The WRITE STATUS REGISTER (WRSR) instruction enables new values to be written to
the status register. Before it can be accepted, a WREN instruction must previously have
been executed. After the WREN instruction has been decoded and executed, the device
sets the WEL.
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128Mb: P5Q Serial PCM
Instructions
The WRSR instruction is entered by driving S# LOW, followed by the instruction code
and the data byte on serial data input (DQ0). The instruction sequence is shown in
Figure 10 on page 22. The WRSR instruction has no effect on B1 and B0 of the status
register.
S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not,
the WRSR instruction is not executed. As soon as S# is driven HIGH, the self-timed
WRITE STATUS REGISTER cycle (whose duration is tW) is initiated. While the WRITE
STATUS REGISTER cycle is in progress, the status register may still be read to check the
value of the WIP bit. The WIP bit is 1 during the self-timed WRITE STATUS REGISTER
cycle, and is 0 when it is completed. When the cycle is completed, the WEL is reset.
The WRSR instruction enables the user to change the values of the block protect bits and
to define the size of the area that is to be treated as read-only, as defined in Table 2 on
page 14. The WRSR instruction also enables the user to set and reset the SRWD bit in
accordance with the W# signal. The SRWD bit and W# signal enable the device to be put
in the hardware protected mode (HPM). The WRSR instruction is not executed after the
HPM is entered.
RDSR is the only instruction that is accepted while a WRSR operation is in progress; all
other instructions are ignored.
Figure 10:
WRITE STATUS REGISTER (WRSR) Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Status
register in
Command
DQ0
7
6
5
4
3
2
1
0
MSB
High-Z
DQ1
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128Mb: P5Q Serial PCM
Instructions
Table 8:
Protection Modes
W#
SRWD
Bit
1
0
1
0
0
1
Software protected
(SPM)
0
1
Hardware protected
(HPM)
Mode
Notes:
Write Protection of
Status Register
Status register is
writable (if the WREN
instruction has set the
WEL bit); the values in
the SRWD, TB, BP3, BP2,
BP1, and BP0 bits can be
changed
Status register is
hardware write
protected; the values in
the SRWD, TB, BP3, BP2,
BP1, and BP0 bits cannot
be changed
Memory Content
Protected Area1
Unprotected Area1
Protected against PAGE
PROGRAM, SECTOR
ERASE, and BULK ERASE
Ready to accept PAGE
PROGRAM, and SECTOR
ERASE instructions
Protected against PAGE
PROGRAM, SECTOR
ERASE, and BULK ERASE
Ready to accept PAGE
PROGRAM, and SECTOR
ERASE instructions
1. As defined by the values in the block protect bits (BP3, BP2, BP1, BP0) of the status register,
as shown in Table 2 on page 14.
When the SRWD bit of the status register is 0 (its initial delivery state), it is possible to
write to the status register, provided that the WEL bit has previously been set by a WREN
instruction, regardless of whether W# is driven HIGH or LOW.
When the SRWD bit of the status register is set to 1, two cases need to be considered,
depending on the state of W#:
• If W# is driven HIGH, it is possible to write to the status register provided that the WEL
bit has previously been set by a WREN instruction.
• If W# is driven LOW, it is not possible to write to the status register even if the WEL bit
has previously been set by a WREN instruction (attempts to write to the status register
are rejected and are not accepted for execution). As a consequence, all the data bytes
in the memory area that are software protected (SPM) by the block protect bits of the
status register are also hardware protected against data modification.
Regardless of the order of the two events, the HPM can be entered in one of two ways:
• Set the SRWD bit after driving W# LOW.
• Drive W# LOW after setting the SRWD bit.
The only way to exit HPM after it has been entered is to pull write protect (W#) HIGH.
If write protect (W#) is permanently tied HIGH, HPM can never be activated, and only
the software protected mode (SPM), using the block protect bits of the status register,
can be used.
Read Data Bytes (READ)
The device is first selected by driving S# LOW. The instruction code for the read data
bytes (READ) instruction is followed by a 3-byte address A[23:0], with each bit being
latched in during the rising edge of C. Then the memory contents at that address are
shifted out on serial data output (DQ1), with each bit being shifted out at a maximum
frequency fR, during the falling edge of C. The instruction sequence is shown in
Figure 11 on page 24.
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Instructions
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole
memory can be read with a single READ instruction. When the highest address is
reached, the address counter rolls over to 000000h, enabling the read sequence to be
continued indefinitely.
The READ instruction is terminated by driving S# HIGH. S# can be driven HIGH at any
time during data output. Any READ instruction, while an ERASE, PROGRAM, or WRITE
is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 11:
READ DATA BYTES (READ) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
1
0
MSB
DQ1
Data-out 2
Data-out 1
High-Z
7
6
5
4
3
2
1
0
7
MSB
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving S# LOW. The instruction code for the read data
bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0]
and a dummy byte, with each bit being latched in during the rising edge of C. Then the
memory contents at that address are shifted out on serial data output (DQ1) at a
maximum frequency fC, during the falling edge of C. The instruction sequence is shown
in Figure 12 on page 25.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole
memory can be read with a single FAST_READ instruction. When the highest address is
reached, the address counter rolls over to 000000h, enabling the read sequence to be
continued indefinitely.
The FAST_READ instruction is terminated by driving S# HIGH. S# can be driven HIGH at
any time during data output. While an ERASE, PROGRAM, or WRITE cycle is in progress,
any FAST_READ instruction is rejected without having any effects on the cycle that is in
progress.
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128Mb: P5Q Serial PCM
Instructions
Figure 12:
FAST_READ Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
1
0
High-Z
DQ1
1
S#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
7
6
5
4
3
2
1
0
Data-out 2
Data-out 1
DQ1
7
1
6
5
4
3
2
1
0
7
MSB
MSB
6
5
4
3
2
1
0
7
MSB
DUAL OUTPUT FAST READ (DOFR)
The DUAL OUTPUT FAST READ (DOFR) instruction is very similar to the FAST_READ
instruction, except that the data are shifted out on two pins (DQ0 and DQ1) instead of
one. Outputting the data on two pins instead of one doubles the data transfer bandwidth
compared to the outputting data using the FAST_READ instruction.
The device is first selected by driving S# LOW. The instruction code for the DOFR
instruction is followed by a 3-byte address A[23:0] and a dummy byte, with each bit
being latched-in during the rising edge of serial clock (C). Then the memory contents at
that address are shifted out on DQ0 and DQ1 at a maximum frequency fC, during the
falling edge of C. The instruction sequence is shown in Figure 13 on page 26.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0 and DQ1.
The whole memory can be read with a single DOFR instruction. When the highest
address is reached, the address counter rolls over to 00 0000h so that the read sequence
can be continued indefinitely.
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Instructions
Figure 13:
DUAL OUTPUT FAST READ Instruction Sequence
S#
Mode 3
C
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 2
24-bit address
note 1
Command
DQ0
23 22 21
3
2
1
0
High-Z
DQ1
1
S#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy byte
DQ0
6
DQ1
7
4
2
0
6
1
MSB
3
1
2
0
6
Data-out 2
Data-out 1
5
4
7
MSB
5
3
1
4
2
0
6
1
7
Data-out 3
7
MSB
5
3
4
1
0
Data-out n
MSB
5
3
1
MSB
QUAD OUTPUT FAST READ (QOFR)
The QUAD OUTPUT FAST READ (QOFR) instruction is very similar to the FAST_READ
instruction, except that the data are shifted out on four pins (pins DQ0, DQ1, DQ2, and
DQ3) instead of just one. Outputting the data on four pins instead of one quadruples the
data transfer bandwidth compared to using the FAST_READ instruction.
The device is first selected by driving S# LOW. The instruction code for the QOFR
instruction is followed by a 3-byte address A[23:0] and a dummy byte, with each bit
being latched in during the rising edge of C. Then the memory contents at that address
are shifted out on DQ0, DQ1, DQ2, and DQ3 at a maximum frequency fC, during the
falling edge of C. The instruction sequence is shown in Figure 14 on page 27.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out on DQ0, DQ1,
DQ2, and DQ3. The whole memory can be read with a single QOFR instruction. When
the highest address is reached, the address counter rolls over to 00 0000h so that the read
sequence can be continued indefinitely.
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Instructions
Figure 14:
QUAD OUTPUT FAST READ Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Command 6Bh
DQ0
23 22 21
2
1
0
Don’t Care
DQ1
Don’t Care
DQ2
DQ3
3
I/O switches from input to output
8 dummy cycles
24-bit address
‘1’
4
0
4
0
4
0
4
0
4
5
1
5
1
5
1
5
1
5
6
2
6
2
6
2
6
2
6
7
3
7
3
7
3
7
3
7
Byte 1 Byte 2
Notes:
Byte 3 Byte 4
1. After 40 clock cycles (cycle labeled 39 in the figure), data inputs (DQ1) must be released
because they become outputs.
2. After command 6Bh is recognized, W# and HOLD# functionality is automatically disabled.
PAGE PROGRAM (PP)
Note:
The following description of PAGE PROGRAM (PP) applies to all instances of PAGE
PROGRAM, including legacy PROGRAM, bit-alterable WRITE, and PROGRAM on all
1s.
The PP instruction enables bytes to be programmed/written in the memory. Before it
can be accepted, a WREN instruction must previously have been executed. After the
WREN instruction has been decoded, the device sets the WEL bit.
The PP instruction is entered by driving S# LOW, followed by the instruction code, three
address bytes, and at least one data byte on serial data input (DQ0). If the six least significant address bits A[5:0] are not all zero, all transmitted data that goes beyond the end of
the current page are programmed from the start address of the same page (from the
address whose six least significant bits A[5:0] are all zero). S# must be driven LOW for the
entire duration of the sequence. The instruction sequence is shown in Figure 15 on
page 28.
If more than 64 bytes are sent to the device, previously latched data are discarded, and
the last 64 data bytes are guaranteed to be programmed/written correctly within the
same page. If fewer than 64 data bytes are sent to the device, they are correctly
programmed/written at the requested addresses without having any effects on the other
bytes of the same page. (With PROGRAM on all 1s, the entire page should already have
been set to all 1s [FFh].)
For optimized timings, it is recommended to use the PP instruction to program all
consecutive targeted bytes in a single sequence instead of using several PP sequences
with each containing only a few bytes (see Table 16 on page 37).
S# must be driven HIGH after the eighth bit of the last data byte has been latched in;
otherwise the PP instruction is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle (whose duration is
tPP) is initiated. While the PAGE PROGRAM cycle is in progress, the status register may
be read to check the value of the WIP bit. The WIP bit is 1 during the self-timed PAGE
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128Mb: P5Q Serial PCM
Instructions
PROGRAM cycle and is 0 when it is completed. At some unspecified time before the
cycle is completed, the write enable latch (WEL) bit is reset. RDSR is the only instruction
accepted while a PAGE PROGRAM operation is in progress; all other instructions are
ignored.
A PP instruction applied to a page that is protected by the block protect bits (BP3, BP2,
BP1, BP0) is not executed (see Table 2 on page 14 and Table 3 on page 15).
Figure 15:
PP Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
Data byte 1
1
0
7
6
5
4
3
2
1
0
MSB
MSB
1
2078
2079
2077
2076
2075
2074
2072
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
S#
1
0
C
DQ0
7
6
5
4
3
2
1
0
7
6
5
4
3
MSB
MSB
Data byte 64
Data byte 3
Data byte 2
2
1
0
7
6
5
4
3
2
MSB
1
DUAL INPUT FAST PROGRAM (DIFP)
Note:
The following description of DUAL INPUT FAST PROGRAM (DIFP) applies to all
instances of DUAL INPUT FAST PROGRAM, including legacy PROGRAM, bit-alterable WRITE, and PROGRAM on all 1s.
The DUAL INPUT FAST PROGRAM (DIFP) instruction is very similar to the PP instruction, except that the data are entered on two pins (pins DQ0 and DQ1) instead of just
one. Inputting the data on two pins instead of one pin doubles the data transfer bandwidth compared with using the PP instruction.
The DIFP instruction is entered by driving chip select (S#) LOW, followed by the instruction code, three address bytes, and at least one data byte on serial data input (DQ0).
If the six least significant address bits (A[5:0]) are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose six least significant bits (A[5:0]) are all zero). Chip
select (S#) must be driven LOW for the entire duration of the sequence. The instruction
sequence is shown in Figure 16 on page 29.
If more than 64 bytes are sent to the device, previously latched data are discarded and
the last 64 data bytes are guaranteed to be programmed/written correctly within the
same page. If fewer than 64 data bytes are sent to device, they are correctly
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28
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128Mb: P5Q Serial PCM
Instructions
programmed/written at the requested addresses without having any effects on the other
bytes in the same page. (With PROGRAM on all 1s, the entire page should already have
been set to all 1s [FFh].)
For optimized timings, it is recommended to use the DIFP instruction to program all
consecutive targeted bytes in a single sequence rather than using several DIFP
sequences, each containing only a few bytes (see Table 16 on page 37).
S# must be driven HIGH after the eighth bit of the last data byte has been latched in;
otherwise the DIFP instruction is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle (whose duration is
t
PP) is initiated. While the DIFP cycle is in progress, the status register may be read to
check the value of the WIP bit. The WIP bit is 1 during the self-timed PAGE PROGRAM
cycle and 0 when it is completed. At some unspecified time before the cycle is
completed, the WEL bit is reset. RDSR is the only instruction accepted while a DUAL
INPUT FAST PROGRAM operation is in progress; all other instructions are ignored.
A DIFP instruction applied to a page that is protected by the block protect bits is not
executed (see Table 2 on page 14).
Figure 16:
DIFP Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
24-bit address
Command
DQ0
23 22 21
3
2
1
0
High-Z
DQ1
1
S#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
DQ0
6
4
2
0
6
7
5
3
1 MSB
2
0
6
Data-in 2
Data-in 1
DQ1
4
1
7
MSB
5
3
4
2
0
6
7
5
MSB
3
2
0
6
Data-in 4
Data-in 3
1
4
1
7
MSB
5
3
4
2
0
6
7
MSB
5
3
1
0
Data-in 64
Data-in 5
1
4
1
7
5
3
1
MSB
QUAD INPUT FAST PROGRAM (QIFP)
Note:
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The following description of QUAD INPUT FAST PROGRAM applies to all instances of
QUAD INPUT FAST PROGRAM, including legacy PROGRAM, bit-alterable WRITE,
and PROGRAM on all 1s.
29
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128Mb: P5Q Serial PCM
Instructions
The QUAD INPUT FAST PROGRAM (QIFP) instruction is very similar to the PP instruction, except that the data are entered on four pins (DQ0, DQ1, DQ2, and DQ3) instead of
one. Inputting the data on four pins instead of one quadruples the data transfer bandwidth compared with using the PP instruction.
The QIFP instruction is entered by driving S# LOW, followed by the instruction code,
three address bytes, and at least one data byte on DQ0.
If the six least significant address bits A[5:0] are not all zero, all transmitted data that
goes beyond the end of the current page are programmed from the start address of the
same page (from the address whose six least significant bits A[5:0] are all zero). S# must
be driven LOW for the entire duration of the sequence. The instruction sequence is
shown in Figure 17 on page 30.
If more than 64 bytes are sent to the device, previously latched data are discarded and
the last 64 data bytes are guaranteed to be programmed correctly within the same page.
If fewer than 64 data bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other bytes in the same page.
(With PROGRAM on all 1s, the entire page should already have been set to all 1s [FFh].)
For optimized timings, it is recommended to use the QIFP instruction to program all
consecutive targeted bytes in a single sequence rather than o using several QIFP
sequences each containing only a few bytes (see Table 16 on page 37).
S# must be driven HIGH after the eighth bit of the last data byte has been latched in;
otherwise the QIFP instruction is not executed. As soon as S# is driven HIGH, the selftimed PAGE PROGRAM cycle (whose duration is tPP) is initiated. While the DIFP cycle is
in progress, the status register may be read to check the value of the WIP bit. The WIP bit
is 1 during the self-timed PAGE PROGRAM cycle and 0 when it is completed. At some
unspecified time before the cycle is completed, the WEL bit is reset. RDSR is the only
instruction accepted while a QUAD INPUT FAST PROGRAM operation is in progress; all
other instructions are ignored.
A QIFP instruction applied to a page that is protected by the block protect bits is not
executed (see Table 2 on page 14).
Figure 17:
QIFP Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
C
Command 32h
DQ0
23 22 21
3
Don’t Care
DQ1
Don’t Care
DQ2
Don’t Care
DQ3
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2
1
0
4
0
4
0
4
0
4
0
4
0
4
0
5
1
5
1
5
1
5
1
5
1
5
1
6
2
6
2
6
2
6
2
6
2
6
2
7 3 7 3
MSB
MSB
‘1’
Notes:
Data-in Data-in Data-in Data-in Data-in Data-in
6
4
5
3
2
1
24-bit address
7 3 7 3
MSB
MSB
7 3 7 3
MSB
MSB
1. After 32h is recognized, W# and HOLD# functionality is automatically disabled.
30
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128Mb: P5Q Serial PCM
Instructions
SECTOR ERASE (SE)
The SECTOR ERASE (SE) instruction sets all bits that are inside the chosen sector to 1
(FFh). Before it can be accepted, a WREN instruction must previously have been
executed. After the WREN instruction has been decoded, the device sets the WEL bit.
The SE instruction is entered by driving S# LOW, followed by the instruction code and
three address bytes on DQ0. Any address inside the sector is a valid address for the SE
instruction (see Table 3 on page 15). S# must be driven LOW for the entire duration of
the sequence. The instruction sequence is shown in Figure 18 on page 31.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in;
otherwise the SE instruction is not executed. As soon as S# is driven HIGH, the selftimed SECTOR ERASE cycle (whose duration is tSE) is initiated. While the SECTOR
ERASE cycle is in progress, the status register may be read to check the value of the WIP
bit. The WIP bit is 1 during the self-timed SECTOR ERASE cycle and is 0 when it is
completed. At some unspecified time before the cycle is completed, the WEL bit is reset.
RDSR is the only instruction accepted while device is busy with ERASE operation; all
other instructions are ignored.
An SE instruction applied to a page that is protected by the block protect bits is not
executed (see Table 2 on page 14 and Table 3 on page 15).
Figure 18:
SE Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
29 30 31
C
24-bit address
note 1
Command
DQ1
23 22
2
1
0
MSB
BULK ERASE (BE)
The BULK ERASE (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a
WREN instruction must previously have been executed. After the WREN instruction has
been decoded, the device sets the WEL bit.
The BE instruction is entered by driving S# LOW, followed by the instruction code on
DQ0. S# must be driven LOW for the entire duration of the sequence. The instruction
sequence is shown in Figure 19 on page 32.
S# must be driven HIGH after the eighth bit of the instruction code has been latched in;
otherwise the BE instruction is not executed. As soon as S# is driven HIGH, the selftimed BULK ERASE cycle (whose duration is tBE) is initiated. While the BULK ERASE
cycle is in progress, the status register may be read to check the value of the WIP bit. The
WIP bit is 1 during the self-timed BULK ERASE cycle and is 0 when it is completed. At
some unspecified time before the cycle is completed, the WEL bit is reset. RDSR is the
only instruction accepted while the device is busy with the ERASE operation; all other
instructions are ignored.
The BE instruction is executed only if all block protect bits are 0. The BE instruction is
ignored if one or more sectors are protected.
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Power-Up and Power-Down
Figure 19:
BE Instruction Sequence
S#
0
1
2
3
4
5
6
7
C
Command
DQ0
Power-Up and Power-Down
At power-up and power-down, the device must not be selected (that is S#) must follow
the voltage applied on VCC until VCC reaches the correct value:
• VCC,min at power-up, and then for a further delay of tVSL
• VSS at power-down
A safe configuration is provided in “SPI Modes” on page 9.
To avoid data corruption and inadvertent WRITE operations during power-up, a power
on reset (POR) circuit is included. The logic inside the device is held reset while VCC is
less than the power on reset (POR) threshold voltage, VWI. All operations are disabled,
and the device does not respond to any instruction.
The device ignores all WREN, PP, DIFP, SE, BE, and WRSR instructions until a time delay
of tPUW has elapsed after the moment that VCC rises above the VWI threshold. However,
the correct operation of the device is not guaranteed if, by this time, VCC is still below
VCC,min. No WRITE STATUS REGISTER, PROGRAM, or ERASE instructions should be
sent until the later of:
• tPUW after VCC has passed the VWI threshold
• tVSL after VCC has passed the VCC,min level
These values are specified in Table 9 on page 33.
If the time, tVSL, has elapsed after VCC rises above VCC,min, the device can be selected for
READ instructions even if the tPUW delay has not yet fully elapsed.
After power-up, the device is in the following states:
• The device is in the standby power mode.
• The WEL bit is reset.
• The WIP bit is reset.
Normal precautions must be taken for supply line decoupling to stabilize the VCC supply.
Each device in a system should have the VCC line decoupled by a suitable capacitor close
to the package pins (generally, this capacitor is about 100nF).
At power-down when VCC drops from the operating voltage to below the power on reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not
respond to any instruction (if power-down occurs while a WRITE, PROGRAM, or ERASE
cycle is in progress, some data corruption may occur).
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128Mb: P5Q Serial PCM
Initial Delivery State
Figure 20:
Power-Up Timing
VCC
VCC (MAX)
PROGRAM, ERASE, and WRITE commands are rejected by the device
Chip selection not allowed
VCC (MIN)
tVSL
Reset state
of the
device
Read access allowed
Device fully
accessible
VWI
tPUW
Time
Table 9:
Symbol
tVS 1
L
tPUW1
VWI1
Power-Up Timing and VWI Threshold
Parameter
Min
Max
Unit
VCC,min to S# LOW
Time delay to write instruction
Write inhibit voltage
100
1
1.5
–
10
2.5
µs
ms
V
Notes:
1. These parameters are characterized only.
Initial Delivery State
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The status register contains 00h (all status register bits are 0).
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128Mb: P5Q Serial PCM
Maximum Ratings
Maximum Ratings
Stresses greater than those listed in Table 10 may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any
other conditions outside those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 10:
Absolute Maximum Ratings
Note 1 applies to the entire table
Symbol
Parameter
VIO
VCC
VESD
Input and output voltage (with respect to ground)
Supply voltage
Electrostatic discharge voltage (human body model)1
Notes:
Min
Max
Unit
–0.6
–0.6
–2000
VCC + 0.6
4.0
2000
V
V
V
1. JEDEC Standard JESD22-A114A (C1 = 100pF; R1 = 1500Ω; R2 = 500Ω).
DC and AC Characteristics
The parameters in the DC and AC characteristics are derived from tests performed
under the measurement conditions summarized in the relevant tables. Operating conditions in device circuits must match the measurement conditions when relying on the
quoted parameters.
Operating Conditions
Table 11:
Symbol
VCC
TA
TA
Operating Conditions
Parameter
Min
Typ
Max
Unit
Supply voltage
Ambient operating temperature (66 MHz)
Ambient operating temperature (33 MHz)
2.7
0
–30
–
–
–
3.6
70
85
V
°C
°C
Notes:
1. Data retention for Micron PCM is 10 years at 70°C. For additional documentation about
data retention, contact your local Micron sales representative.
Endurance Specifications
Table 12:
Endurance Specifications
Parameter
Condition
WRITE cycle
Main block
Parameter block
Notes:
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Min
Units
Notes
1,000,000
1,000,000
Cycles per
32-byte page
1
1. A WRITE cycle is defined as any time a bit changes within a 32-byte page.
34
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128Mb: P5Q Serial PCM
DC and AC Characteristics
AC Measurement Conditions
Table 13:
Symbol
CL
Figure 21:
AC Measurement Conditions
Parameter
Load capacitance
Input rise and fall times
Input pulse voltages
Input timing reference voltages
Output timing reference voltages
Min
Max
Unit
30
–
30
5
pF
ns
V
V
V
0.2–0.8 VCC
0.3–0.7 VCC
VCC/2
AC Measurement I/O Waveform
Input and output
timing reference levels
Input levels
0.8VCC
0.7VCC
0.5VCC
0.2VCC
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0.3VCC
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DC and AC Characteristics
Capacitance
Table 14:
Symbol
CIN/OUT
CIN
Capacitance1
Parameter
Input/output capacitance (DQ0/DQ1)
Input capacitance (other pins)
Notes:
Test Condition
Min
Max
Unit
VOUT = 0V
VIN = 0V
–
–
8
6
pF
pF
1. Sampled only, not 100% tested, at TA = 25°C and a frequency of 33 MHz.
DC Characteristics
Table 15:
Symbol
ILI
ILO
ICC1
ICC3
DC Characteristics
Test Condition1
Parameter
Input leakage current
Output leakage current
Standby current
Operating current (READ)
Operating current (DOFR)
Operating current (QOFR)
ICC4
ICC5
ICC6
VIL
VIH
VOL
VOH
Operating current (PP)
Operating current (DIFP)
Operating current (QIFP)
Operating current (WRSR)
Operating current (SE, BE)
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Notes:
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S# = VCC, VIN = VSS or VCC
C = 0.1VCC /0.9VCC at 66 MHz,
DQ1 = open
C = 0.1VCC /0.9VCC at 33 MHz,
DQ1 = open
C = 0.1VCC /0.9VCC at 66 MHz,
DQ0 = DQ1 = open
C = 0.1VCC /0.9VCC at 50 MHz,
DQ0 = DQ1 = DQ2 = DQ3 = open
S# = VCC
S#= VCC
S# = VCC
S# = VCC
S# = VCC
IOL = 1.6mA
IOH = –100µA
Min
Max
Unit
–
–
–
–
±2
±2
200
16
µA
µA
µA
mA
–
7
mA
–
20
mA
–
24
mA
–
–
–
–
–
– 0.5
0.7 VCC
–
VCC - 0.2
50
50
50
50
50
0.3 VCC
VCC + 0.4
0.4
mA
mA
mA
mA
mA
V
V
V
V
1. For additional test conditions, refer to Table 11 on page 34.
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128Mb: P5Q Serial PCM
DC and AC Characteristics
AC Characteristics
Table 16:
AC Characteristics
AC characteristics are based on preliminary data
Test Conditions1
Symbol
Alt
f
f
C
C
f
R
fC /fR
tCH3
tCLH
tCL2
tCLL
tCLCH4
tCHCL4
tSLCH
tCSS
tCHSL
tDVCH
tDSU
tCHDX
tDH
tCHSH
tSHCH
tSHSL
tCSH
tSHQZ4
tDIS
tCLQV
tV
tCLQX
tHO
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX4
tLZ
t
t
4
HLQZ
tWHSL6
tSHWL6
tRDP4
t
t
W
PP7
t
SE
tBE
HZ
Parameter
Clock frequency for the following instructions: DOFR, DIFP,
FAST_READ, SE, BE, WREN, WRDI, RDID, RDSR, WRSR
(0°C to 70°C)
Clock frequency for the following instructions: QOFR, QIFP
(0°C to 70°C)
Clock frequency for READ instructions (0°C to 70°C)
Clock frequency for all instructions: QOFR, QIFR, DOFR,
DIFP, FAST_READ, READ SE, BE, WREN, WRDI, RDID, RDSR,
WRSR (–30°C to 85°C)
Clock HIGH time
Clock LOW time
Clock rise time5 (peak to peak)
Clock fall time5 (peak to peak)
S# active setup time (relative to C)
S# not active hold time (relative to C)
Data-in setup time
Data-in hold time
S# active hold time (relative to C)
S# not active setup time (relative to C)
S# deselect time
Output disable time
Clock LOW to output valid under 30pF
Clock LOW to output valid under 10pF
Output hold time
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# setup time (relative to C)
HOLD# hold time (relative to C)
HOLD# to output Low-Z
HOLD# to output High-Z
Write protect setup time
Write protect hold time
S# High to standby mode
WRITE STATUS REGISTER cycle time
PAGE PROGRAM cycle time (64 bytes)
(legacy PROGRAM and bit-alterable WRITE)
PAGE PROGRAM cycle time (64 bytes)
(Program on all 1s)
SECTOR ERASE cycle time
BULK ERASE cycle time
Notes:
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Min
Typ2
Max
Unit
DC
–
66
MHz
DC
–
50
MHz
DC
DC
–
–
33
33
MHz
MHz
6.5
6.5
0.1
0.1
5
5
2
5
5
5
80
–
–
–
0
5
5
5
5
–
–
20
100
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
200
120
–
–
–
–
–
–
–
–
–
–
–
8
9
8
–
–
–
–
–
10
10
–
–
30
350
360
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
–
71
280
–
–
400
50
800
100
ms
s
1. For additional test conditions, refer to Table 11 on page 34 and Table 13 on page 35.
2. Typical values given for TA = 25°C at nominal VCC.
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128Mb: P5Q Serial PCM
DC and AC Characteristics
3.
4.
5.
6.
7.
Figure 22:
CH + tCL must be ≥ 1/fC.
Value guaranteed by characterization, not 100% tested in production.
Expressed as a slew rate.
Only applicable as a constraint for a WRSR instruction when SRWD is set to 1.
When using the PP instruction to program consecutive bytes, optimized timings are
obtained with one sequence, including all the bytes versus several sequences of only a few
bytes (1 ≤ n ≤ 64).
t
Serial Input Timing
tSHSL
S#
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH tCHDX
DQ0
MSB in
DQ1
Figure 23:
tCHCL
tCLCH
LSB in
High-Z
High-Z
Write Protect Setup and Hold Timing During WRSR when SRWD = 1
W#
tWHSL
tSHWL
S#
C
DQ0
DQ1
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pcm_spi_2.fm - Rev. E 3/11 EN
High-Z
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128Mb: P5Q Serial PCM
DC and AC Characteristics
Figure 24:
Hold Timing
S#
tCHHL
tHLCH
tHHCH
C
tCHHH
tHLQZ
tHHQX
DQ0
DQ1
HOLD#
Figure 25:
Output Timing
S#
tCLQV
tCLQV
tCLQX
tCLQX
tCL
tCH
C
tSHQZ
DQ0
LSB out
DQ1 Address
LSB in
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128Mb: P5Q Serial PCM
Package Dimensions
Package Dimensions
P5Q serial PCM packages are RoHS compliant with a lead-free, second-level interconnect, which is marked on the package and on the inner box label in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
Figure 26:
SO16 Wide – 16-Lead Plastic Small-Outline, 300 Mils Body Width, Package Outline
10.30 ±0.20
(0.398 MIN/0.413 MAX)
h x 45°
16
9
0.23 MIN/0.32 MAX
(0.009 MIN/0.013 MAX)
10.00 MIN/10.65 MAX
(0.394 MIN/0.419 MAX)
7.50 ±0.10
(0.295 ±0.004)
1
8
0° MIN/8° MAX
2.5 ±0.15
(0.093 MIN/0.104 MAX)
0.20 ±0.1
(0.008 ±0.004)
0.1 Z
0.33 MIN/0.51 MAX
(0.013 MIN/0.020 MAX)
Table 17:
1.27 TYP
(0.050 TYP)
0.40 MIN/1.27 MAX
(0.016 MIN/0.050 MAX)
Z
SO16 wide – Wide - 16-Lead Plastic Small-Outline, 300 Mils Body Width, Mechanical Data
Millimeters
Inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
B
C
D
E
e
H
h
L
q
ddd
–
–
–
–
–
–
1.27
–
–
–
–
–
2.35
0.10
0.33
0.23
10.10
7.40
–
10.00
0.25
0.40
0°
–
2.65
0.30
0.51
0.32
10.50
7.60
–
10.65
0.75
1.27
8°
0.10
–
–
–
–
–
–
0.050
–
–
–
–
–
0.093
0.004
0.013
0.009
0.398
0.291
–
0.394
0.010
0.016
0°
–
0.104
0.012
0.020
0.013
0.413
0.299
–
0.419
0.030
0.050
8°
0.004
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128Mb: P5Q Serial PCM
Ordering Information
Ordering Information
Table 18:
Active Line Item Ordering Table
Part Number
NP5Q128A13ESFC0E
NP5Q128AE3ESFC0E
Notes:
Description
3V, SOIC, Pb-free,10.34 x 10.34 x 2.54, 16-lead (0oC to 70oC)
3V, SOIC, Pb-free,10.34 x 10.34 x 2.54, 16-lead (–30oC to 85 oC)
1. For SO8 packaging solutions, contact your Micron representative for details.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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