128Mb: P8P Parallel PCM
Features
P8P Parallel Phase Change
Memory (PCM)
Features
• Security
– One-time programmable registers
64 unique factory device identifier bits
2112 user-programmable OTP bits
– Selectable OTP space in main array
– Three adjacent main blocks available for boot code
or other secure information
– Absolute WRITE protection: VPP = VSS
– Power transition ERASE/PROGRAM lockout
– Individual zero-latency block locking
– Individual block lock-down
• High-performance READ
– 115ns initial READ access
– 135ns initial READ access
– 25ns, 8-word asynchronous-page READ
• Architecture
– Asymmetrically blocked architecture
– Four 32KB parameter blocks with top or bottom
configuration
– 128KB main blocks
– Serial peripheral interface (SPI) to enable lower
pin count on-board programming
• Phase change memory (PCM)
– Chalcogenide phase change storage element
– Bit-alterable WRITE operation
• Voltage and power
– VCC (core) voltage: 2.7–3.6V
– VCCQ (I/O) voltage: 1.7–3.6V
– Standby current: 80µA (TYP)
• Quality and reliability
– More than 1,000,000 WRITE cycles
– 90nm PCM technology
• Temperature
– Commercial: 0°C to +70°C (115ns initial READ
access)
– Industrial: –40°C to +85°C (135ns initial READ
access)
• Simplified software management
– No block erase or cleanup required
– Bit twiddle in either direction (1:0, 0:1)
– 35µs (TYP) PROGRAM SUSPEND
– 35µs (TYP) ERASE SUSPEND
– Flash data integrator optimized
– Scalable command set and extended command set
compatible
– Common Flash interface capable
• Density and packaging
– 128Mb density
– 56-lead TSOP package
– 64-ball easy BGA package
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcm_1.fm - Rev. K 7/12 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
128Mb: P8P Parallel PCM
Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
TSOP Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
64-Ball Easy BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Pinouts and Ballouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Signal Names and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
OUTPUT DISABLE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
STANDBY Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
RESET Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Device Command Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Device Command Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ ARRAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ IDENTIFIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
READ QUERY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
WORD PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
BIT-ALTERABLE WORD WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
BUFFERED PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
BIT-ALTERABLE BUFFER WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BIT-ALTERABLE BUFFER PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PROGRAM SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
PROGRAM RESUME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
PROGRAM PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
ERASE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
BLOCK ERASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ERASE SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ERASE RESUME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Security Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Zero Latency Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Lock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Unlock Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Lock Down Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WP# Lock Down Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Locking Operations During ERASE SUSPEND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Permanent OTP Block Locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
WP# Lock Down Control for Selectable OTP Lock Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Selectable OTP Locking Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Read Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
CLEAR STATUS REGISTER Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
System Protection Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcmTOC.fm - Rev. K 7/12 EN
0
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Table of Contents
Read Protection Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Program Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Lock Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
OTP Protection Register Addressing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SPI Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SPI Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SPI Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
SPI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
WRITE ENABLE (WREN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE DISABLE (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
READ IDENTIFICATION (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
WIP Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
WEL Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
BP3, BP2, BP1, BP0 Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Top/Bottom Bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
SRWD Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
WRITE STATUS REGISTER (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
PAGE PROGRAM (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
SECTOR ERASE (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Power and Reset Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Power-Up and Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Reset Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Maximum Ratings and Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Voltage Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Read Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Write Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SPI AC Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Program and Erase Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Supplemental Reference Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Write State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Query Structure Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Extended Query Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcmTOC.fm - Rev. K 7/12 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
List of Figures
List of Figures
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Figure 2:
Figure 3:
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Figure 6:
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Figure 11:
Figure 12:
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Figure 29:
Figure 30:
Figure 31:
Figure 32:
Figure 33:
Figure 34:
Figure 35:
Figure 36:
Figure 37:
Figure 38:
Figure 39:
Figure 40:
56-Lead TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
64-Ball Easy BGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
56-Lead TSOP Pinout (128Mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
64-Ball Easy BGA Ballout (128Mb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Example VPP Power Supply Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Block Locking State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Selectable OTP Locking Illustration (Bottom Parameter Device Example) . . . . . . . . . . . . . . . . . . . . . .33
Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
WRITE ENABLE (WREN) Instruction Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
WRITE DISABLE (WRDI) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . . .41
READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . .43
WRITE STATUS REGISTER (WRSR) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . .45
FAST_READ Instruction Sequence and Data-Out Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
PAGE PROGRAM (PP) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SECTOR ERASE (SE) Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Reset Operation Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
AC Input/Output Reference Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Transient Equivalent Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Asynchronous Single-Word Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Asynchronous Page Mode Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Write-to-Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Asynchronous Read to Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Write to Asynchronous Read Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Serial Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Write Protect Setup and Hold Timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . . . . . . . . . .58
Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Full WRITE STATUS CHECK Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WRITE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
BLOCK ERASE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
BLOCK ERASE FULL ERASE STATUS CHECK Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ERASE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
LOCKING OPERATIONS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PROGRAM PROTECTION REGISTER Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
FULL STATUS CHECK Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Write State Machine — Next State Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcmLOF.fm - Rev. K 7/12 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
List of Tables
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
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Table 41:
Table 42:
Table 43:
Table 44:
Table 45:
Table 46:
Table 47:
Table 48:
Table 49:
Table 50:
Table 51:
Top Parameter Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Bottom Parameter Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
TSOP Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Easy BGA Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Ball/Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Command Codes and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Command Sequences in x16 Bus Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Read Identifier Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Buffered Programming and Bit-Alterable Buffer Write Timing Requirements . . . . . . . . . . . . . . . . . . .25
Bit Alterability vs. Flash Bit-Masking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Block Locking Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Block Locking State Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Selectable OTP Block Locking Feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Selectable OTP Block Locking Programming of PR-LOCK0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Status Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2K OTP Space Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Status Register Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Protected Area Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Power and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Current Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
DC Voltage Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Test Configuration Component Value for Worst-Case Speed Conditions . . . . . . . . . . . . . . . . . . . . . . .53
Capacitance: TA = 25°C, f = 1 MHz1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Read Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
AC Write Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
SPI AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Program and Erase Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Active Line Item Ordering Table (0°C to 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Active Line Item Ordering Table (–40°C to 85°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Full WRITE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
WRITE SUSPEND/RESUME Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure. . . . . . . . . . . . . . . . . . . . . . . . . .66
BLOCK ERASE Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
BLOCK ERASE FULL ERASE STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
ERASE SUSPEND/RESUME Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
LOCKING OPERATIONS Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
PROGRAM PROTECTION REGISTER Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
FULL STATUS CHECK Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Summary of Query Structure Output as a Function of Device and Model . . . . . . . . . . . . . . . . . . . . . .77
Example of Query Structure Output of x16 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Query Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcmLOT.fm - Rev. K 7/12 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
List of Tables
Table 52:
Table 53:
Table 54:
Table 55:
Table 56:
Table 57:
Table 58:
Table 59:
Table 60:
Table 61:
CFI Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Bit Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Hex Code and Values for Device Geometry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
Primary Vendor-Specific Extended Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Partition and Erase Block Region Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Hex Code and Values for Partition and Erase Block Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
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6
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128Mb: P8P Parallel PCM
Functional Description
Functional Description
P8P parallel phase change memory (PCM) is nonvolatile memory that stores information through a reversible structural phase change in a chalcogenide material. The material exhibits a change in material properties, both electrical and optical, when changed
from the amorphous (disordered) to the polycrystalline (regularly ordered) state. In the
case of PCM, information is stored via the change in resistance that the chalcogenide
material experiences when undergoing a phase change. The material also changes
optical properties after experiencing a phase change, a characteristic that has been
successfully mastered for use in current rewritable optical storage devices, such as
rewritable CDs and DVDs.
The P8P parallel PCM storage element consists of a thin film of chalcogenide contacted
by a resistive heating element. In PCM, the phase change is induced in the memory cell
by highly localized Joule heating caused by an induced current at the material junction.
During a WRITE operation, a small volume of the chalcogenide material is made to
change phase. The phase change is a reversible process and is modulated by the magnitude of injected current, the applied voltage, and the duration of the heating pulse.
Unlike other proposed alternative memories, P8P parallel PCM technology uses a
conventional CMOS process with the addition of a few additional layers to form the
memory storage element. Overall, the basic memory manufacturing process used to
make PCM is less complex than that of NAND, NOR or DRAM.
P8P parallel PCM combines the benefits of traditional floating gate Flash, both NORtype and NAND-type, with some of the key attributes of RAM and EEPROM. Like NOR
Flash and RAM technology, PCM offers fast random access times. Like NAND flash, PCM
has the ability to write moderately fast, and like RAM and EEPROM, PCM supports bit
alterable WRITEs (overwrite). Unlike Flash, no separate erase step is required to change
information from 0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile
with data retention compared with NOR Flash.
Product Features
P8P parallel PCM devices provide the convenience and ease of NOR flash emulation
while providing a set of super set features that exploit the inherent capabilities of PCM
technology. The device emulates most of the features of Micron embedded memory
(P33). This is intended to ease the evaluation and design of P8P parallel PCM into
existing hardware and software development platforms. This basic features set is supplemented by the super set features, which are intended to enable the designer to exploit
the inherent capabilities of phase change memory technology and to enable the eventual simplification of hardware and software in the design.
The P8P parallel PCM product family supports 128Mb density and are available in 64ball easy BGA and 56-lead TSOP packages. These are the same pinouts and packages as
the existing P33 NOR Flash devices. Designed for low -oltage systems, P8P parallel PCM
supports READ, WRITE, and ERASE operations at a core supply of 2.7V VCC. P8P parallel
PCM offers additional power savings through standby mode, which is initiated when the
system deselects the device by driving CE inactive.
P8P parallel PCM provides a set of commands that are compatible with industry-standard command sequences used by NOR-type Flash. An internal write state machine
(WSM) automatically executes the algorithms and timings necessary for BLOCK ERASE
and WRITE. Each emulated BLOCK ERASE operation results in the contents of the
addressed block being written to all 1s. Data can be programmed in word or buffer increments. Erase suspend enables system software to pause an ERASE command so it can
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128Mb: P8P Parallel PCM
Memory Maps
read or program data in another block. PROGRAM SUSPEND enables system software to
pause programming so it can read from other locations within the device. The status
register indicates when the WSM’s BLOCK ERASE or PROGRAM operation is finished.
A 64-byte, 32 word write buffer is also included to enable optimum write performance.
Using the write buffer, data is overwritten or programmed in buffer increments. This
feature improves system program performance more than 20 times over independent
byte writes.
Similar to floating gate Flash, a command user interface (CUI) serves as the interface
between the system processor and internal operation of the device. A valid command
sequence written to the CUI initiates device automation. In addition to the CUI, a Flashcompatible common Flash interface (CFI) permits software algorithms to be used for
entire families of devices. This enables device-independent, JEDEC ID-independent,
and forward- and backward-compatible software support for the specified Flash device
families.
The serial peripheral interface (SPI) enables in-system programming through minimal
pin count interface. This interface is provided in addition to a traditional parallel system
interface. This feature has been added to facilitate the on-board, in-system programming of code into the P8P parallel PCM device after it has been soldered to a circuit
board. Preprogramming code prior to high temperature board attach is not recommended with a P8P parallel PCM device. Although device reliability across the operating
temperature range is typically superior to that of floating gate Flash, the P8P parallel
PCM device may be subject to thermally-activated disturbs at higher temperatures;
however, no permanent device damage occurs either during leaded or lead-free board
attach.
P8P parallel PCM block locking enables zero-latency block locking/unlocking and
permanent locking. Permanent block locking provides enhanced security for boot code.
The combination of these two locking features provides complete locking solution for
code and data.
PCM technology also supports the ability to change each memory bit independently
from 0 to 1 or 1 to 0 without an intervening BLOCK ERASE operation. Bit alterability
enables software to write to the nonvolatile memory in a similar manner as writing to
RAM or EEPROM without the overhead of erasing blocks prior to write. Bit Alterable
writes use similar command sequences as word programming and Buffer Programming.
Memory Maps
Table 1:
Top Parameter Memory Map
128Mb
7
16
16
16
16
64
130
129
128
127
126
7FC000-7FFFFF
7F8000-7FBFFF
7F4000-7F7FFF
7F0000-7F3FFF
7E0000-7EFFFF
64
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96
4
700000-70FFFF
6F0000-6FFFFF
…
…
112
111
…
64
64
6
…
Block
…
Size (KW)
…
Programming Region Number
600000-60FFFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Memory Maps
Table 1:
Top Parameter Memory Map (Continued)
128Mb
5
64
95
5F0000-5FFFFF
500000-50FFFF
79
4F0000-4FFFFF
400000-40FFFF
64
63
3F0000-3FFFFF
300000-30FFFF
64
47
2F0000-2FFFFF
200000-20FFFF
64
31
1F0000-1FFFFF
100000-10FFFF
15
0F0000-0FFFFF
…
16
64
…
64
…
0
…
32
…
64
…
1
…
48
…
64
…
2
…
64
…
64
…
3
…
80
64
…
64
…
4
…
Block
…
Size (KW)
…
Programming Region Number
64
0
000000-00FFFF
Programming Region Number
Size (KW)
Block
128Mb
7
64
130
7F0000-7FFFFF
64
114
6F0000-6FFFFF
600000-60FFFF
98
5F0000-5FFFFF
500000-50FFFF
64
82
4F0000-4FFFFF
400000-40FFFF
64
66
3F0000-3FFFFF
300000-30FFFF
64
50
2F0000-2FFFFF
64
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…
51
…
64
…
2
…
67
…
64
…
3
…
83
…
64
…
4
…
99
64
…
64
…
5
…
700000-70FFFF
…
115
…
64
…
6
…
Bottom Parameter Memory Map
…
Table 2:
35
5
200000-20FFFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Memory Maps
Table 2:
Bottom Parameter Memory Map (Continued)
128Mb
1
64
34
1F0000-1FFFFF
100000-10FFFF
18
0F0000-0FFFFF
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…
19
64
…
64
…
0
…
Block
…
Size (KW)
…
Programming Region Number
64
4
010000-01FFFF
16
16
16
16
3
2
1
0
00C000-00FFFF
008000-00BFFF
004000-007FFF
000000-003FFF
6
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©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Package Dimensions
Package Dimensions
TSOP Mechanical Specifications
Figure 1:
56-Lead TSOP
20 ±0.2
18.4 ±0.2
0.995 ±0.03
Pin #1 index
See notes 2
and 4
See note 3
0.5 TYP
14.00 ±0.2
0.15 ±0.05
See note 3
See note 3
0.25 ±0.1
0.15 ±0.05
0.10
3°
+2°
-3°
See Detail A
1.20 MAX
Seating
plane
0.05 MIN
0.60 ±0.10
Detail A
Notes:
Table 3:
1. One dimple on package denotes pin 1.
2. If two dimples exist, then the larger dimple denotes pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product
mark.
TSOP Package Dimensions
Millimeters
Parameter
Package height
Standoff
Package body thickness
Lead width
Lead thickness
Package body length
Package body width
Lead pitch
Terminal dimension
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Inches
Symbol
Min
Nom
Max
Min
Nom
Max
A
A1
A2
b
c
D1
E
e
D
–
0.050
0.965
0.100
0.100
18.200
13.800
–
19.800
–
–
0.995
0.150
0.150
18.400
14.000
0.500
20.00
1.200
–
1.025
0.200
0.200
18.600
14.200
–
20.200
–
0.002
0.038
0.004
0.004
0.717
0.543
–
0.780
–
–
0.039
0.006
0.006
0.724
0.551
0.0197
0.787
0.047
–
0.040
0.008
0.008
0.732
0.559
–
0.795
7
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128Mb: P8P Parallel PCM
Package Dimensions
Table 3:
TSOP Package Dimensions (Continued)
Millimeters
Parameter
Lead tip length
Lead count
Lead tip angle
Seating plane coplanarity
Lead to package offset
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Inches
Symbol
Min
Nom
Max
Min
Nom
Max
L
N
q
Y
Z
0.500
–
0°
–
0.150
0.600
56
3°
–
0.250
0.700
–
5°
0.100
0.350
0.020
–
0°
–
0.006
0.024
56
3°
–
0.010
0.028
–
5°
0.004
0.014
8
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©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Package Dimensions
64-Ball Easy BGA Package
Figure 2:
64-Ball Easy BGA Package
0.78 TYP
Seating
plane
0.1
1.00 TYP
64X Ø0.43 ±0.1
1.5 ±0.1
8
7
6
5
4
3
2
Ball A1 ID
Ball A1 ID
1
0.5 ±0.1
A
B
C
D
8 ±0.1
E
F
1.00 TYP
G
H
10 ±0.1
1.20 MAX
Table 4:
Easy BGA Package Dimensions
Millimeters
Parameter
Package height (128Mb)
Ball height
Package body thickness (128Mb)
Ball (lLead) width
Package body width
Package body length
Pitch
Ball (lead) count
Seating plane coplanarity
Corner to ball A1 distance along D
Corner to ball A1 distance along E
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9
Symbol
Min
Nom
Max
A
A1
A2
b
D
E
e
N
Y
S1
S2
–
0.25
–
0.33
9.90
7.90
–
–
–
1.40
0.49
–
–
0.78
0.43
10.00
8.00
1.00
64
–
1.50
0.50
1.20
–
–
0.53
10.10
8.10
–
–
0.10
1.60
0.51
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128Mb: P8P Parallel PCM
Pinouts and Ballouts
Pinouts and Ballouts
Figure 3:
56-Lead TSOP Pinout (128Mb)
A16
A15
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
VCC
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
NC
SERIAL
VSS
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Q
A17
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
D
C
RST#
VPP
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#/HOLD#
VSS
CE#/S#
A1
Top View
Notes:
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1. A1 is the least significant address bit to be compatible with x8 addressing systems even
though P8P parallel PCM is a 16-bit data bus.
10
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128Mb: P8P Parallel PCM
Pinouts and Ballouts
Figure 4:
1
64-Ball Easy BGA Ballout (128Mb)
4
3
2
5
6
7
8
8
7
6
5
4
3
2
1
A
A
A1
VPP
A8
A6
A13
VCC
A18
A22
A22
A18
VCC A13
VPP
A8
A6
A1
B
B
A2
A9 CE#/SE# A14
VSS
RFU
A19
RFU
RFU
A19
RFU A14 CE#/SE# A9
VSS
A2
C
C
A3
A7
A12
A10
A15 WP# A20
A21
A21
A20
WP# A15
A12
A10
A7
A3
D
D
A4
A11 RST# VCCQ VCCQ A16
A5
A17
A17
A16 VCCQ VCCQ RST# A11
A5
A4
E
E
D8
D1
D3
D9
D4
C
D15
RFU
RFU
D15
C
D4
D3
D9
D1
D8
F
F
SERIAL D0
D11
D10
D12
D
OE#/
OE#/ Q
Q
HOLD# HOLD#
D
D12
D11
D10
D0 SERIAL
G
G
A23
RFU
D2
VCCQ
D5
D6
D14
WE#
WE# D14
D6
D5
VCCQ
D2
RFU
A23
H
H
RFU
VSSQ
VCC
VSS
D13 VSSQ
D7
RFU
RFU
Easy BGA
Top view-ball side down
Notes:
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D7
VSSQ D13
VSS
VCC
VSSQ
RFU
Easy BGA
Top view-ball side up
1. A1 is the least significant address bit to be compatible with x8 addressing systems even
though P8P parallel PCM is a 16-bit data bus.
11
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128Mb: P8P Parallel PCM
Signal Names and Descriptions
Signal Names and Descriptions
Table 5:
Ball/Pin Descriptions
Symbol
Type
A[MAX:1]
Input
DQ[15:0]
CE# or S#
OE# or
HOLD#
RST#
WE#
WP#
C
D
Q
SERIAL
VPP
VCC
VCCQ
VSS
VSSQ
NC
DU
RFU
Desctiption
Address inputs: Device address inputs. 128Mb: A[23:1]. The address bus for TSOP and easy BGA
starts at A1. P8P parallel PCM uses x16 addressing. The P8P parallel PCM package is x8 addressing
and is compatible with J3 or P30 products.
Input/ Data input/outputs: Inputs data and commands during WRITEs (internally latched). Outputs data
Output during READ operations. Data signals float when CE# or OE# are VIH or RST# is VIL.
Input Chip enable: CE# LOW activates internal control logic, I/O buffers, decoders, and sense amps. CE#
HIGH deselects the device, places it in standby state, and places data outputs at High-Z.
SPI
SPI select: S# LOW activates WRITE commands to the SPI interface. Raising S# to VIH completes (or
terminates) the SPI command cycle; it also sets Q to High-Z.
Input Output enable: Active LOW OE# enables the device’s output data buffers during a READ cycle.
With OE# at VIH, device data outputs are placed in High-Z state.
SPI
SPI HOLD#: When asserted, suspends the current cycle and sets Q to High-Z until de-asserted.
Input Reset chip: When LOW, RST# resets internal automation and inhibits WRITE operations. This
provides data protection during power transitions. RST# HIGH enables normal operation. The device
is in 8-word page mode array read after reset exits.
Input Write enable: controls command user interface (CUI) and array WRITEs. Its rising edge latches
addresses and data.
Input Write protect: Disables/enables the lock-down function. When WP# is VIL, the lock-down
mechanism is enabled and software cannot unlock blocks marked lock-down. When WP# is VIH, the
lock-down mechanism is disabled and blocks previously locked-down are now locked; software can
unlock and lock them. After WP# goes LOW, blocks previously marked lock-down revert to that
state.
SPI
SPI clock: Synchronization clock for input and output data
SPI
SPI data input: Serial data input for op codes, address, and program data bytes. Input data is
clocked in on the rising edge of C, starting with the MSB.
SPI
SPI data output: Serial data output for read data. Output data is clocked out, triggered by the
falling edge of C, starting with the MSB.
SPI
SPI enable: SERIAL is a port select switching between the normal parallel or serial interface. When
VSS, the normal (non-SPI) P8P parallel PCM interface, is enabled, all other SPI inputs are “Don't
Care,” and Q is at High-Z. When VCC SPI mode is enabled, all non-SPI inputs are “Don't Care,” and all
outputs are at High-Z. This pin has an internal weak pull-down resistor to select the normal parallel
interface when users leave the pin floating. A CAM can be used to permanently disable this feature.
Pwr
Erase and write power: A valid VPP voltage enables erase or programming. Memory contents
can’t be altered when VPP VPPLK.Set VPP = VCC for in-system PROGRAM and ERASE operations. To
accommodate resistor or diode drops from the system supply, the VIH level of VPP can be as low as
VPPL,min. Program/erase voltage is normally 1.7–3.6V.
Pwr
Device power supply: WRITEs are inhibited at VCC VLKO. Device operations at invalid VCC
voltages should not be attempted.
Pwr
Output power supply: Enables all outputs to be driven at VCCQ. This input may be tied directly to
VCC if VCCQ is to function within the VCC range.
Pwr
Ground: Connects device circuitry to system ground.
Pwr
I/O ground: Tie to GND.
No connect: No internal connection; can be driven or floated.
Don’t use: Don’t connect to power supply or other signals.
Reserved for future use: Don’t connect to other signals.
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128Mb: P8P Parallel PCM
Bus Operations
Bus Operations
CE# at VIL and RST# at VIH enables device READ operations. Assume addresses are
always valid. OE# LOW activates the outputs and gates selected data onto the I/O bus.
WE# LOW enables device WRITE operations. When the VPP voltage VPPLK (lock-out
voltage), only READ operations are enabled.
Table 6:
Bus Operations
State
READ (main array)
READ (status, query, identifier)
OUTPUT DISABLE
STANDBY
RESET
WRITE
Notes:
RST#
CE#
OE#
WE#
DQ[15:0]
Notes
VIH
VIH
VIH
VIH
VIL
VIH
VIL
VIL
VIL
VIH
X
VIL
VIL
VIL
VIH
X
X
VIH
VIH
VIH
VIH
X
X
VIL
DOUT
DOUT
High-Z
High-Z
High-Z
DIN
2
2
1
1. See Table 8 on page 16 for valid DIN during a WRITE operation.
2. X = “Don’t Care) (L or H).
3. OE# and WE# should never be asserted simultaneously. If this occurs, OE# overrides WE#.
READ Operations
To perform a READ operation, RST# and WE# must be de-asserted while CE# and OE#
are asserted. CE# is the device select control. When asserted, it enables the Flash
memory device. OE# is the data output control. When asserted, the addressed Flash
memory data is driven onto the I/O bus.
WRITE Operations
To perform a WRITE operation, both CE# and WE# are asserted while RST# and OE# are
de-asserted. During a WRITE operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 7 on page 14 describes the bus cycle
sequence for each of the supported device commands, and Table 8 on page 16 describes
each command. See “AC Characteristics” on page 48 for signal timing details.
Notes:
1. WRITE operations with invalid VCC and/or VPP voltages can produce spurious results
and should not be attempted.
OUTPUT DISABLE Operations
When OE# is de-asserted, device outputs DQ[15:0] are disabled and placed in High-Z;
WAIT is also placed in High-Z.
STANDBY Operations
When CE# is de-asserted, the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5ms time interval, 5µs after CE# is de-asserted. During standby,
average current is measured over the same time interval 5µs after CE# is de-asserted.
When the device is deselected (while CE# is de-asserted) during a PROGRAM or ERASE
operation, it continues to consume active power until the PROGRAM or ERASE operation is completed.
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Command Set
RESET Operations
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
Flash memory if it is the system boot device. If a CPU reset occurs with no Flash memory
reset, improper CPU initialization may occur because the Flash memory may be
providing status information rather than array data. Micron Flash memory devices
enable proper CPU initialization following a system reset using the RST# input. RST#
should be controlled by the same low true RESET signal that resets the system CPU.
After initial power-up or reset, the device defaults to asynchronous read array mode, and
the status register is set to 0x80. Asserting RST# de-energizes all internal circuits and
places the output drivers in High-Z. When RST# is asserted, the device shuts down the
operation in progress, a process that takes a minimum amount of time to complete.
When RST# has been de-asserted, the device is reset to asynchronous read array state.
Note:
If RST# is asserted during a PROGRAM or ERASE operation, the operation is terminated, and the memory contents at the aborted location (for a PROGRAM) or block
(for an ERASE) are no longer valid because the data may have been only partially written or erased.
When returning from a reset (RST# de-asserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a WRITE cycle can be initiated. After this wake-up interval passes, normal operation is restored. See “AC Characteristics” on page 48 for details about signal timing.
Command Set
Device Command Codes
The system CPU provides control of all in-system READ, WRITE, and ERASE operations
of the device via the system bus. The on-chip write state machine (WSM) manages all
block erase and word program algorithms.
Device commands are written to the command user interface (CUI) to control all Flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the Flash device is controlled.
Table 7:
Command Codes and Descriptions
Mode
Code
Command
Read
FFh
70h
READ ARRAY
READ STATUS
REGISTER
90h
98h
50h
Description
Places device in read array mode so that data signals output array data on DQ[15:0].
Places the device in status register read mode. Status data is output on DQ[7:0]. The
device automatically enters this mode after a PROGRAM or ERASE command is
issued to it.
READ ID CODE Puts the device in read identifier mode. Device reads from the addresses output
manufacturer/device codes, block lock status, or protection register data on
DQ[15:0].
READ QUERY Puts the device in read query mode. Device reads from the address given
outputting the common Flash interface information on DQ[7:0].
CLEAR STATUS The WSM can set the status register’s block lock (SR1), VPP (SR3), program (SR4), and
REGISTER
erase (SR5) status bits to 1, but cannot clear them. Device reset or the CLEAR
STATUS REGISTER command at any device address clears those bits to 0.
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Command Set
Table 7:
Command Codes and Descriptions (Continued)
Mode
Code
Command
Program
40h
PROGRAM
SET-UP
10h
42h
E8h
EAh
DEh
D0h
Erase
20h
D0h
Suspend
B0h
D0h
Block
Locking
60h
01h
D0h
2Fh
Protection
C0h
Description
This preferred program command’s first cycle prepares the CUI for a PROGRAM
operation. The second cycle latches address and data and executes the WSM
program algorithm at this location. Status register updates occur when CE# or OE#
is toggled. A READ ARRAY command is required to read array data after
programming.
ALT SET-UP
Equivalent to a PROGRAM SET-UP command (40h).
BIT-ALTERABLE The command sequence is the same as WORD PROGRAM (40h). The difference is
WRITE
that the state of the PCM memory cell can change from a 0 to 1 or 1 to 0, unlike a
Flash memory cell, which can only change from 1 to 0 during programming.
BUFFERED
This command loads a variable number of bytes up to the buffer size 32 words onto
PROGRAM
the program buffer.
BIT-ALTERABLE This command sequence is the similar to BUFFERED PROGRAM, but the BUFFER
BUFFERED
WRITE command is bit alterable or overwrite operation. The command sequence is
WRITE
the same as E8h.
BUFFER
This command is the same as BUFFERED PROGRAM, but the user indicates that the
PROGRAM ON page is already set to all 1s. The command sequence is the same as E8h
ALL 1s
BUFFERED
The confirm command is issued after the data streaming for writing into the buffer
WRITE
is done. This initiates the WSM to carry out the buffered programing algorithm.
CONFIRM
BLOCK ERASE Prepares the CUI for block erase. The device emulates erasure of the block
SET-UP
addressed by the ERASE CONFIRM command by writing all 1s. If the next command
is not ERASE CONFIRM:
The CUI sets status register bits SR4 and SR5 to 1.
The CUI places the device in the read status register mode.
The CUI waits for another command.
ERASE
If the first command was ERASE SET-UP (20h), the CUI latches address and data, and
CONFIRM
then emulates erasure of the block indicated by the ERASE CONFIRM cycle address.
WRITE
This command issued at any device address initiates suspension of the currently
SUSPEND or
executing PROGRAM/ERASE operation. The status register, invoked by a READ
ERASE
STATUS REGISTER command, indicates successful SUSPEND operation by setting
SUSPEND
status bits SR2 (write suspend) or SR6 (erase suspend) and SR7. The WSM remains in
suspend mode regardless of the control signal states, except RST# = VIL.
SUSPEND
This command issued at any device address resumes suspended PROGRAM or ERASE
RESUME
operation.
LOCK SET-UP Prepares the CUI for lock configuration. If the next command is not BLOCK LOCK,
UNLOCK, or LOCK-DOWN the CUI sets SR4 and SR5 to indicate command sequence
error.
LOCK BLOCK If the previous command was LOCK SET-UP (60h), the CUI locks the addressed block.
UNLOCK
After a LOCK SET-UP (60h) command, the CUI latches the address and unlocks the
BLOCK
addressed block.
LOCK-DOWN After a LOCK SET-UP (60h) command, the CUI latches the address and locks down
the addressed block.
PROTECTION Prepares the CUI for a protection register program operation. The second cycle
PROGRAM
latches address and data and starts the WSM’s protection register program or lock
SET-UP
algorithm. Toggling CE# or OE# updates the PCM status register data. To read array
data after programming, issue a READ ARRAY command.
Notes:
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1. Do not use unassigned (reserved) commands.
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Device Command Bus Cycles
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the CUI. Several
commands, including WORD PROGRAM and BLOCK ERASE, are used to modify array
data commands. Writing either command to the CUI initiates a sequence of internally
timed functions that culminate in the completion of the requested task. However, the
operation can be aborted either by asserting RST# or by issuing an appropriate
SUSPEND command.
Table 8:
Mode
Read
Program
Erase
Suspend
Block
Lock
Protection
Command Sequences in x16 Bus Mode
First Bus Cycle
Bus
Cycles
Oper
READ ARRAY/RESET
READ DEVICE IDENTIFIERS
READ QUERY
READ STATUS REGISTER
CLEAR STATUS REGISTER
PROGRAM
1
2
2
2
1
2
BIT-ALTERABLE PROGRAM
BUFFERED PROGRAM3
BIT-ALTERABLE BUFFERED
PROGRAM3
BUFFERED PROGRAM ON ALL1s
BLOCK ERASE
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME
LOCK BLOCK
UNLOCK BLOCK
LOCK-DOWN BLOCK
PROTECTION PROGRAM
LOCK PROTECTION PROGRAM
Command
Notes:
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1
Second Bus Cycle
Addr
2
Data
Oper
Addr1
Data2
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
DnA
DnA
DnA
BA
X
WA
–
READ
READ
READ
–
WRITE
–
DBA+IA
DBA+QA
BA
–
WA
–
ID
QD
SRD
–
WD
2
2
>2
WRITE
WRITE
WRITE
WA
WA
WA
FFh
90h
98h
70h
50h
40h or
10h
42h
E8h
EAh
WRITE
WRITE
WRITE
PA
WA
WA
PD
N-1
N-1
>2
2
1
1
2
2
2
2
2
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WA
BA
X
X
BA
BA
BA
PA
LPA
DEh
20h
B0h
D0h
60h
60h
60h
C0h
C0h
WRITE
WRITE
–
–
WRITE
WRITE
WRITE
WRITE
WRITE
WA
BA
–
–
BA
BA
BA
PA
LPA
N-1
D0h
–
–
01h
D0h
2Fh
PD
FFFDh
1. First command cycle address should be the same as the operation’s target address.
X = Any valid address within the device
IA = Identification code address
BA = Address within the block
LPA = Lock protection address (from the CFI); P8P parallel PCM LPA is at 0080h
PA = 4-word protection address in the user-programmable area of device identification
plane
DnA = Address within the device
DBA = Device base address: (A[MAX:1] = 0h)
PRA = Program region
QA = Query code address
WA = Word address of memory location to be written
2. SRD = Data read from the status register
WD = Data to be written at location WA
ID = Identifier code data
PD = User-programmable protection data
QD = Query code data on DQ[7:0]
N = Data count to be loaded into the device to indicate how many words would be written
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READ Operations
into the buffer; because the internal registers count from 0, the user writes N - 1 to load N
words.
3. The second cycle of the BUFFERED PROGRAM command, which is the count being loaded
into the buffer, is followed by data streaming up to 32 words, and then a CONFIRM command is issued that triggers the programming operation. Refer to “Figure 33 on page 61.”
READ Operations
P8P parallel PCM has several read modes:
• Read array mode returns PCM array data from the addressed locations.
• Read identifier mode returns manufacturer device identifier data, block lock status,
and protection register data.
• Read query mode returns device CFI (or query) data.
• Read Status Register mode returns the device status register data. A system processor
can check the status register to determine the device’s state or to monitor program or
erase progress.
READ ARRAY
The READ ARRAY command places (or resets) the device to read array mode. Upon
initial device power-up or after reset (RST# transitions from VIL to VIH), the device
defaults to read array mode. If an ERASE or PROGRAM SUSPEND command suspends
the WSM, a subsequent READ ARRAY command will place the device in read array
mode. The READ ARRAY command functions independently of VPP voltage.
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READ Operations
READ IDENTIFIER
The read identifier mode is used to access the manufacturer/device identifier, block lock
status, and protection register codes. The identifier space occupies the address range
supplied by the READ IDENTIFIER command (90h) address.
Table 9:
Read Identifier Table
Address1, 2
Parameter
Manufacturer code
DBA + 000000h
Device code
Block lock configuration
Block Is unlocked
Block Is locked
Block Is not locked down
Block Is locked down
Reserved for future use
Lock protection register 0
64-bit factory-programmable
protection register
64-bit user-programmable protection
register
Lock protection register 1
16 x 128-bit user-programmable
protection registers
DBA + 000001h
BBA + 000002h
Notes:
Table 10:
Data
DBA + 000080h
DBA + 000081h–000084h
0089h
ID (see Table 10 on page 18)
Lock
DQ0 = 0
DQ0 = 1
DQ1 = 0
DQ1 = 1
DQ[7:2]
PR-LK0
Protection register data
DBA + 000085h–000088h
Protection register data
DBA + 000089h
DBA + 00008Ah–0000109h
PR-LK1
Protection register data
1. DBA = Device base address: (A[MAX:18] = DBA). Micron reserves other configuration
address locations.
2. BBA = Block base address.
Device Codes
Device Code (Byte/Word)
Binary
Device
Hex
High Byte
Low Byte
Mode
128Mb
128Mb
881E
8821
10001000
10001000
00011110
00100001
Top boot
Bottom boot
READ QUERY
The query space comes to the foreground and occupies the device address range
supplied by the READ QUERY command address. The mode outputs CFI data when the
device addresses are read. “Common Flash Interface” on page 73 describes the query
mode information and addresses. Write the READ ARRAY command to return to read
array mode. The read performance of this CFI data follows the same timings as the main
array.
In addition to other ID mode data, the protection registers (such as block locking information and the device JEDEC ID) may be accessed as long as there are no ongoing
WRITE or ERASE operations.
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PROGRAM Operations
Query (CFI) data is read by sending the READ QUERY command to the device. Reading
the query data is subject to the same restrictions as reading the protection registers.
PROGRAM Operations
Five WRITE operations are available in P8P parallel PCM.
• WORD PROGRAM (40h, or 10h)
• BIT-ALTERABLE WORD WRITE (42h)
• BUFFERED PROGRAM (E8h)
• BIT-ALTERABLE BUFFERED WRITE (EAh)
• BUFFERED PROGRAM ON ALL 1s (DEh)
Writing a PROGRAM command to the device initiates internally timed sequences that
write the requested word. The WSM executes a sequence of internally timed events to
write desired bits at the addressed location and to verify that the bits are sufficiently
written. For word programming, the memory changes specifically addressed bits to 0; 1
bits do not change the memory cell contents. This enables individual data bits to be
programmed (0) while 1 bits serve as data masks. For BIT-ALTERABLE WORD WRITE,
the memory cell can change from 0 to 1 or 1 to a 0.
The status register can be examined for write progress and errors by reading any address
within the device during a WRITE operation. Issuing a READ STATUS REGISTER
command brings the status register to the foreground enabling write progress to be
monitored or detected at other device addresses. Status register bit SR7 indicates device
write status while the write sequence executes. CE# or OE# toggle (during polling)
updates the status register. Valid commands that can be issued to the writing device
during write include READ STATUS REGISTER, WRITE SUSPEND, READ IDENTIFIER,
READ QUERY, and READ ARRAY; however, READ ARRAY will return unknown data while
the device is busy.
When writing completes, status register bit SR4 indicates write success if zero (0) or
failure if set (1). If SR3 is set (1), the WSM couldn’t execute the WRITE command because
VPP was outside acceptable limits. If SR1 is set (1), the WRITE operation targeted a
locked block and was aborted. Attempting to write in an erase suspended block will
result in failure, and SR4 will be set (1).
After examining the status register, clear it by issuing the CLEAR STATUS REGISTER
command before issuing a new command. The device remains in status register mode
until another command is written to that device. Any command can follow after writing
completes.
WORD PROGRAM
The system processor writes the WORD PROGRAM SETUP command (40h/10h) to the
device followed by a second WRITE that specifies the address and data to be
programmed. The device accessed during both of the command cycles automatically
outputs status register data when the device address is read. The device accessed during
the second cycle (the data cycle) of the program command sequence will be where the
data is programmed. See Figure 33 on page 61.
When VPP is greater than VPPLK, program and erase currents are drawn through the VCC
input. If VPP is driven by a logic signal, VPP must remain above VPP,min to perform insystem PCM modifications. Figure 5 on page 22 shows PCM power supply usage in
various configurations.
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PROGRAM Operations
BIT-ALTERABLE WORD WRITE
The BIT-ALTERABLE WORD WRITE command executes just like the WORD PROGRAM
command (40h/10h), using a two-write command sequence. The BIT-ALTERABLE
WRITE SETUP command (42h) is written to the CUI, followed by the specific address
and data to be written. The WSM will start executing the programming algorithm, but
the data written to the CUI will be directly overwritten into the PCM memory. This is
unlike Flash memory, which can only be written from 1 to 0 without a prior erase of the
entire block. See Table 12 on page 21. This overwrite function eliminates Flash bit
masking, which means that the software cannot use a 1 in a data mask to produce no
change of the memory cell, as might occur with floating gate Flash.
BUFFERED PROGRAM
A BUFFERED PROGRAM command sequence initiates the loading of a variable number
of words, up to the buffer size (32 words), into the program buffer and then into the PCM
device. First, the BUFFERED PROGRAM SETUP command is issued along with the
BLOCK ADDRESS (Figure 33 on page 61). When status register bit SR7 is set to 1, the
buffer is ready for loading. Now a word count is given to the part with the block address.
On the next write, a device starting address is given along with the program buffer data.
Subsequent writes provide additional device addresses and data, depending on the
count. All subsequent addresses must lie within the starting address plus the buffer size.
Maximum programming performance and lower power are obtained by aligning the
starting address at the beginning of a 32-word boundary. A misaligned starting address is
not allowed and results in invalid data. After the final buffer data is given, a PROGRAM
BUFFER CONFIRM command is issued. This initiates the WSM to begin copying the
buffer data to the PCM array.
If a command other than BUFFERED PROGRAM CONFIRM command (D0h) is written
to the device, an invalid command/sequence error will be generated, and status register
bits SR5 and SR4 will be set to a 1. For additional buffer writes, issue another PROGRAM
BUFFER SETUP command and check SR7. If an error occurs while writing, the device
will stop writing, and status register bit SR4 will be set to a 1 to indicate a program
failure. The internal WSM verify only detects errors for 1s that do not successfully
program to 0s.
If a program error is detected, the status register should be cleared by the user before
issuing the next PROGRAM command. Additionally, if the user attempts to program past
the block boundary with a PROGRAM BUFFER command, the device will abort the
PROGRAM BUFFER operation. This will generate an invalid command/sequence error
and status register bits SR5 and SR4 will be set to a 1. All bus cycles in the buffered
programming sequence should be addressed to the same block. If a buffered programming is attempted while the VPP VPPLK, status register bits SR4 and SR3 will be set to 1.
Buffered write attempts with invalid VCC and VPP voltages produce spurious results and
should not be attempted. Buffered program operations with VIH < RST# < VHH may
produce spurious results and should not be attempted.
Successful programming requires that the addressed block’s locking status to be cleared.
If the block is locked down, then the WP# pin must be raised HIGH, and then the block
could be unlocked to execute a PROGRAM operation. An attempt to program a locked
block results in setting of SR4 and SR1 to a 1 (for example, error in programming).
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PROGRAM Operations
BIT-ALTERABLE BUFFER WRITE
The BIT-ALTERABLE BUFFER WRITE command sequence is the same as for BUFFER
PROGRAM. For command sequence, see “BUFFERED PROGRAM” on page 20. The
primary difference between the two buffer commands is when the WSM starts
executing, the data written to the buffer will be directly overwritten into the PCM
memory, unlike Flash Memory, which can only go from 1 to 0 before an erase of the
entire block. See Table 12 on page 21. This overwrite function eliminates Flash bit
masking, which means software cannot use a 1 in a data mask for no change of the
memory cell, as might occur with floating gate Flash.
The advantage of bit alterability is that no block erase is needed prior to writing a block,
which minimizes system overhead for software management of data and ultimately
improves latency and determinism and reduces power consumption because of reduction of system overhead. Storing counter variables can easily be handled using PCM
memory because a 0 can change to a 1 or a 1 can change to a 0.
Table 11:
Buffered Programming and Bit-Alterable Buffer Write Timing Requirements
Alignment
Programming Time
Example
32-word/64-byte aligned
tPROG/PB
Start address = 1FFF10h; end address = 1FFF2Fh
Table 12:
Bit Alterability vs. Flash Bit-Masking
Programming
Function
Command
Issued
Memory Cell
Current State
Data From
User
Memory Cell
After Programming
Flash bit masking
40h or E8h
40h or E8h
40h or E8h
40h or E8h
42h or EAh
42h or EAh
42h or EAh
42h or EAh
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
1
0
1
0
1
Bit alterability
BIT-ALTERABLE BUFFER PROGRAM
This mode is sometimes referred to as PRESET BUFFERED PROGRAM.
PROGRAM ON ALL 1s is similar to program mode (1s treated as masks; 0s written to
cells) with the assumption that all the locations in the addressed page have previously
been set (1s). Performance of BUFFER PROGRAM ON ALL 1s expected to be better than
buffered program mode because the preread step before programming is eliminated.
The command sequence for BUFFERED PROGRAM ON ALL 1s is the same as BUFFERED PROGRAM command (E8h).
PROGRAM SUSPEND
Issuing the PROGRAM SUSPEND command while programming suspends the programming operation. This enables data to be accessed from the device other than the one
being programmed. The PROGRAM SUSPEND command can be issued to any device
address. A PROGRAM operation can be suspended to perform reads only. Additionally, a
PROGRAM operation that is running during an ERASE SUSPEND can be suspended to
perform a READ operation.
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ERASE
When a programming operation is executing, issuing the PROGRAM SUSPEND
command requests the WSM to suspend the programming algorithm at predetermined
points. The device continues to output status register data after the PROGRAM
SUSPEND command is issued. Programming is suspended when status register bits
SR[7,2] are set.
To read data from the device, the READ ARRAY command must be issued. READ ARRAY,
READ STATUS REGISTER, READ DEVICE IDENTIFIER, READ CFI, and PROGRAM
RESUME are valid commands during a PROGRAM SUSPEND.
During a PROGRAM SUSPEND, de-asserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in PROGRAM SUSPEND. If RST# is asserted, the device is reset.
PROGRAM RESUME
The RESUME command instructs the device to continue programming, and automatically clears Status Register bits SR[7,2]. This command can be written to any address. If
error bits are set, the Status Register should be cleared before issuing the next instruction. RST# must remain de-asserted.
PROGRAM PROTECTION
Holding the VPP input at VIL provides absolute hardware write protection for all PCM
device blocks. If VPP is below VPPLK, WRITE or ERASE operations halt and an error is
posted in status register bit SR3. The block lock registers are not affected by the VPP level;
they may be modified and read even if VPP is below VPPLK.
Figure 5:
Example VPP Power Supply Configuration
System supply
VPP
≤10kΩ
VCC
VPP
PROT# (logic signal)
VCC
• Low-Voltage programming
• Absolute write protection via logic signal
System supply
VPP
• Low-voltage and VPP factory programming
VCC
VPP
VPP
• VPP supply during factory programming
• Complete write/erase protection: VPP ≤ VPPLK
System supply
System supply
VCC
VPP
• Low-Voltage programming
ERASE
Unlike floating gate Flash, PCM does not require a high-voltage BLOCK ERASE operation
to change all the bits in a block to 1. As a bit-alterable technology, each bit is capable of
independently being changed from a 0 to a 1 and from a 1 to a 0. With floating gate Flash,
a high voltage potential must be placed in parallel upon a group of bits called an erase
block. Each bit within the block may be changed independently from 1 to a 0, but only
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ERASE
may be changed from a 1 to a 0 through a grouped ERASE operation. To maintain
compatibility with legacy Flash system software, P8P parallel PCM mimics or emulates a
Flash erase by writing each bit within a block to 1, emulating Flash-style erase.
BLOCK ERASE
The system processor writes the ERASE SETUP command (20h) to the device followed by
a second CONFIRM (D0h) command write that specifies the address of the block to be
erased. During both of the command cycles, the device automatically outputs status
register data when the device address is read. See Figure 32 on page 59.
After writing the command, the device automatically enters read status mode. The
device status register bit SR7 will be set (1) when the erase completes. If the erase fails,
status register bit SR5 will be set (1). SR3 = 1 indicates an invalid VPP voltage. SR1 = 1
indicates an ERASE operation was attempted on a locked block. CE# or OE# toggle
(during polling) updates the status register.
If an error bit is set, the status register can be cleared by issuing the CLEAR STATUS
REGISTER command before attempting the next operation. The device will remain in
status register mode until another command is written to the device. Any command can
follow after ERASE completes. Only one block can be in erase mode at a time.
ERASE SUSPEND
The WRITE/ERASE SUSPEND command halts an in-progress WRITE or ERASE operation. The command can be issued at any device address. The SUSPEND command
enables data to be accessed from memory locations other than the one block being
written or the block being erased.
A WRITE operation can be suspended to perform reads at any location except the
address being programmed. An ERASE operation can be suspended to perform either a
WRITE or a READ operation within any block except the block that is erase suspended. A
WRITE command nested within a suspended ERASE can subsequently be suspended to
read yet another location. After the WRITE/ERASE process starts, the SUSPEND
command requests that the WSM suspend the WRITE/ERASE sequence at predetermined points in the algorithm. An operation is suspended when status bits SR7 and SR6
and/or SR2 display 1. tSUSP/P/tSUSP/E specifies suspend latency.
To read data from other blocks within the device (other than an erase suspended block),
a READ ARRAY command can be written. During ERASE SUSPEND, a WRITE command
can be issued to a block other than the erase suspended block. Block erase cannot
resume until WRITE operations initiated during ERASE SUSPEND complete. READ
ARRAY, READ STATUS REGISTER, READ IDENTIFIER (ID), READ QUERY, and WRITE
RESUME are valid commands during WRITE or ERASE SUSPEND. Additionally, CLEAR
STATUS REGISTER, PROGRAM, WRITE SUSPEND, ERASE RESUME, LOCK BLOCK,
UNLOCK BLOCK, and LOCK-DOWN BLOCK are valid commands during ERASE
SUSPEND.
During a suspend, CE# = VIH places the device in standby state, which reduces supply
current. VPP must remain at its program level and WP# must remain unchanged while in
suspend mode.
The RESUME (D0h) command instructs the WSM to continue writing/erasing and automatically clears status register bits SR2 (or SR6) and SR7. If status register error bits are
set, the status register can be cleared before issuing the next instruction. RST# must
remain at VIH. See Figure 31 on page 58 and Figure 33 on page 61.
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128Mb: P8P Parallel PCM
Security Mode
If software compatibility with the P33 device is desired, a minimum tERS/SUSP time (See
“Program and Erase Characteristics” on page 55) should elapse between an ERASE
command and a subsequent ERASE SUSPEND command to ensure that the device
achieves sufficient cumulative erase time. Occasional ERASE to SUSPEND interrupts do
not cause problems, but out-of-spec ERASE to SUSPEND commands issued too
frequently to a P33 device may produce uncertain results. However, this specification is
not required for this PCM device.
ERASE RESUME
The ERASE RESUME command instructs the device to continue erasing and automatically clears status register bits SR[7,6]. This command can be written to any address. If
status register error bits are set, the status register should be cleared before issuing the
next instruction. RST# must remain de-asserted.
Security Mode
The device features security modes used to protect the information stored in the Flash
memory array.
Block Locking
Two types of block locking are available on P8P parallel PCM: zero latency block locking
and selectable OTP block locking. This type of locking enables permanent locking of the
parameter blocks and three main blocks.
Zero Latency Block Locking
Individual instant block locking protects code and data. It enables software to control
block locking or it can require hardware interaction before locking can be changed. Any
block can be locked or unlocked with no latency. Locked blocks cannot be written or
erased; they can only be read. WRITE or ERASE operations to a locked block returns a
status register bit SR1 error. State (WP#, LAT1, LAT0) specifies lock states (WP# = WP#
state, LAT1 = internal bock lock down latch status, LAT0 = internal block lock latch
status). Figure 6 on page 27 defines possible locking states. The following summarizes
the locking functionality.
• All blocks power-up in the locked state. Then UNLOCK and LOCK commands can
unlock or lock them.
• The LOCK DOWN command locks and prevents a block from being unlocked when
WP# = VIL.
• WP# = VIH overrides LOCK DOWN so commands can unlock/lock blocks.
• If a previously locked down block is given a LOCK/UNLOCK/LOCK DOWN command
and WP# returns to VIL, then those blocks will return to lock down.
• LOCK DOWN is cleared only when the device is reset or powered down.
• The block lock registers are not affected by the VPP level; they may be modified and
read even if VPP is below VPPLK.
Lock Block
All blocks default power-up or reset state is locked (states [001] or [101]) to fully protect it
from alteration. WRITE or ERASE operations to a locked block return a status register bit
SR1 error. The LOCK BLOCK command sequence can lock an unlocked block.
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128Mb: P8P Parallel PCM
Security Mode
Table 13:
Block Locking Truth Table
VPP
WP#
RST#
Block Write Protection
Block Lock Bits
X
X
VIL
Block lock bits may not be changed
VPPLK
VIL
VIH
VPPLK
VIH
VIH
VPPLK
VIL
VIH
VPPLK
VIH
VIH
All blocks write/erase
protected
All blocks write/erase
protected
All blocks write/erase
protected
All lock down and locked
blocks write/erase protected
All lock down and locked
blocks write/erase protected
Lock down block states may not be
changed
All Lock down block states may be
changed
Lock down block states may not be
changed
All Lock down block states may be
changed
Unlock Block
The UNLOCK BLOCK command unlocks locked blocks (if block isn’t locked down) so
they can be programmed or erased. Unlocked blocks return to the locked state at device
reset or power-down.
Lock Down Block
Locked down blocks (state 3 or [011]) are protected from WRITE and ERASE operations
(just like locked blocks), but software commands cannot change their protection state.
When WP# is VIH, the lock down function is disabled (state 7 or [111]), and an UNLOCK
command (60h/D0h) must be issued to unlocked locked down block (state 6 or [110]),
prior to modifying data in these blocks. To return an unlocked block to locked down
state, a LOCK command (60h/01h) must be issued prior to changing WP# to VIL (state 7
or [111] and then state 3 or [011]). A locked or unlocked block can be locked down by
writing the LOCK DOWN BLOCK command sequence. Locked down blocks revert to the
locked state at device reset or power-down.
WP# Lock Down Control
WP# = VIH overrides the block lock down. See Table 13 on page 25. The WP# signal
controls the lock down function. WP# = 0 protects lock down blocks [011] from write,
erase, and lock status changes. When WP# = 1, the lock down function is disabled [111]
and a software command can individually unlock locked down blocks [110] so they can
be erased and written. When the lock down function is disabled, locked down blocks
remain locked and must first be unlocked by writing the UNLOCK command prior to
modifying data in these blocks. These blocks can then be relocked [111] and unlocked
[110] while WP# remains HIGH.
When WP# goes LOW, blocks in relocked state [111] returns to locked down state [011].
However, WP# going LOW changes blocks at unlocked state [110] to [010] or virtual lock
down state. When the lock status of a virtual lock down blocks is read, it appears to be a
locked down state to user when WP# is VIL. Blocks in virtual lock down will be immediately unlocked when WP# is VIH. Therefore, to avoid virtual lock down, a LOCK
command must be issued to an unlocked block prior to WP# going LOW. Device reset or
power-down resets all blocks to the locked state[101] or [001], including locked down
blocks.
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Security Mode
Block Lock Status
Every block’s lock status can be read in the device’s read identifier mode. To enter this
mode, write 90h to the device. Subsequent reads at block base address + 00002h output
that block’s lock status. Data bits DQ0 and DQ1 represent the lock status. DQ0 indicates
the block lock/unlock state as set by the LOCK command and cleared by the UNLOCK
command. It is also automatically set when entering lock down. DQ1 indicates lock
down state as set by the LOCK DOWN command. It cannot be cleared by software; it can
only be cleared by device reset or power-down. See Table 14 on page 26.
Locking Operations During ERASE SUSPEND
Block lock configurations can be performed during an ERASE SUSPEND using the standard locking command sequences to unlock, lock, or lock down a block. This is useful
when another block needs to be updated while an ERASE operation is suspended.
To change block locking during an ERASE operation, first write the ERASE SUSPEND
command, and then check the status register until it indicates that the ERASE operation
has suspended. Next write the desired LOCK command sequence to a block; the lock
state will be changed. After completing LOCK, READ, or PROGRAM operations, resume
the ERASE operation with the ERASE RESUME command (D0h).
If a block is locked or locked down during a suspended ERASE of the same block, the
locking status bits will change immediately. But, when resumed, the ERASE operation
will complete. Locking operations cannot occur during WRITE SUSPEND. “Write State
Machine” on page 70 describes valid commands during ERASE SUSPEND.
Nested LOCK or WRITE commands during ERASE SUSPEND can return ambiguous
status register results. 60h followed by 01h commands lock a block. A CONFIGURATION
SETUP command (60h) followed by an invalid command produces a lock command
status register error (SR4 and SR5 = 1). If this error occurs during ERASE SUSPEND, SR4
and SR5 remain at 1 after the erase resumes. When erase completes, the previous locking
command error hides the status register’s erase errors. A similar situation occurs if a
WRITE operation error is nested within an ERASE SUSPEND.
Table 14:
Block Locking State Transitions
Name
ERASE/WRITE
Allowed?1
UnLock
Lock
LockDown
WP#
Toggle
Result
(Next
State)
Unlocked
Locked (default)1
Virtual lock down4
Locked down
Unlocked
Locked
Lock down disabled
Lock down disabled
Yes
No
No
No
Yes
No
Yes
No
000
000
011
011
100
100
110
110
001
001
011
011
101
101
111
111
011
011
011
011
111
111
111
111
100
101
110
111
000
001
010
011
Lock Command Input
Result (Next State)5
Current State
WP#
0
0
0
0
1
1
1
1
LAT1 LAT0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Notes:
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Locking
Status
Readout
D1
D0
0
0
1
1
0
0
1
1
0
1
1
1
0
1
0
1
1. Additional illegal states are shown, but are not recommended for normal, non-erroneous
operational modes.
2. This column shows whether a block’s current locking state allows ERASE or WRITE.
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Security Mode
3. At power-up or device reset, blocks default to locked state [001] if WP# = 0, the recommended default.
4. Blocks in virtual lock down appear to be in locked down state when WP# = VIL. WP# = 1
changes [010] to unlocked state [110].
5. This column shows the results of writing the four locking commands via WP# toggle from
the current locking state.
Figure 6:
Block Locking State Diagram
Locked
[X01]
Locked
down4, 5
[011]
Hardware
locked5
[011]
Unlocked
[X00]
Software
locked
[111]
Unlocked
[110]
Power-Up/Reset
Software block lock-down (0x60/0x2F)
Software block lock (0x60/0x01) or software block unlock (0x60/0xD0)
Hardware control (WP#)
Notes:
1. [a, b, c] represent [WP#, DQ1, DQ0]. X = “Don’t Care.”
2. DQ1 indicates block lock down status. DQ1 = 0; lock down has not been issued to this block.
DQ1 = 1; lock down has been issued to this block.
3. DQ0 indicates block lock status. DQ0 = 0; block is unlocked. DQ0 = 1, block is locked.
4. Lock down = hardware and software locked.
5. [011] states should be tracked by system software to determine differences between hardware locked and locked down states.
Permanent OTP Block Locking
The parameter blocks and first three main blocks for a bottom parameter device (or if
device configured as a top parameter device, this would be the last three main blocks
and the parameter blocks) can be made OTP. As a result, further WRITE and ERASE operations to these blocks are disallowed, effectively permanently programming the blocks.
This is achieved by programming bits 2, 3, 4, and 5 in the PR-LOCK0 register at offset
0x80 in ID space. The OTP locking bit mapping may be seen in Table 15 on page 28.
Bit 6 in the PR-LOCK0 register at offset 0x80 in ID space is defined as the configuration
lock bit. When bit 6 is cleared (at zero), the device shall disable further programming of
the OTP Lock bits, thereby effectively freezing their state. Putting bit 6 at zero shall not
affect the ability to write any other bits in the non-OTP regions or in the system protection registers. Reference Table 16 on page 28 for configuration lock bit (Bit 6 in PRLOCK0) control of allowed states when other bits of the register are programmed.
The READ operations of these permanently locked blocks are supported regardless of
the state of their corresponding permanent lock bits. Zero latency block locking must be
used until the block is permanently locked with the OTP block locking. PROGRAM and
ERASE operations for these blocks remain fully supported until that block’s permanent
lock bit is cleared.
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Security Mode
PROGRAM or ERASE operations to a permanently locked block returns a status register
bit SR1 error.
Programming of the permanent OTP block locking bits is not allowed during ERASE
SUSPEND of a permanent lockable block.
Note:
Table 15:
The selectable block locking will not be indicated in the zero latency block lock status.
See “Block Lock Status” on page 26 for more information. Read PR-LOCK0 register to
determine block lock status for these blocks.
Selectable OTP Block Locking Feature
Bit Number @ Offset
0x80 in CFI Space
Function When Set (‘1b)
Function When Cleared (‘0b)
2
Blocks not permanently locked
3
Block not permanently locked
4
Block not permanently locked
5
Block not permanently locked
6
Able to change PR-LOCK0[5:2] bits
WRITE/ERASE disabled for all parameter blocks
Bottom boot - Blocks 0–3
Top boot 128M - Blocks 127–130
WRITE/ERASE disabled for first Main Block
Bottom Boot - Block 4
Top Boot 128M - Block 126
WRITE/ERASE disabled for second Main Block
Bottom Boot - Block 5
Top Boot 128M - Block 125
WRITE/ERASE disabled for third Main Block
Bottom Boot - Block 6
Top Boot 128M - Block 124
Program disabled for PR-LOCK0[5:2]
Table 16:
Selectable OTP Block Locking Programming of PR-LOCK0
Bit 6
Program to
[5:2]
Program to
[1:0]
Status Register
Abort
Program
Status of Data in 80H OTP
Space
Unlocked
Locked
Locked
Locked
Don’t Care
Yes
Yes
No
Don’t Care
Yes
No
Yes
No fail bits set
Program fail/lock fail
Program fail/lock fail
No fail bits set
No
Yes
Yes
No
Changed
No change
No change
Changed
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Registers
Figure 7:
Selectable OTP Locking Illustration (Bottom Parameter Device Example)
Main Array Block 6
0x030000 (Main array)
Main Array Block 5
0x020000 (Main array)
Main Array Block 4
0x010000 (Main array)
Parameter Blocks: Blocks 0–3
0x000000 (Parameter array)
0x80 (OTP array)
6
5
4
3
2
PR-LOCK0
WP# Lock Down Control for Selectable OTP Lock Blocks
Once the block has been permanently locked with OTP bit, WP# at VIH does not override
the lock down of the blocks those bits control.
Selectable OTP Locking Implementation Details
Clearing (write to 0) any of the four permanent lock bits shall effectively cause the
following commands to fail with a block locking error when issued to their corresponding blocks: BUFFER PROGRAM, BIT-ALTERABLE BUFFER WRITE, WORD
PROGRAM, BIT-ALTERABLE WORD WRITE, and ERASE. No other commands shall be
affected.
Programming the permanent lock bits or the configuration lock bit shall be done using
the protection register programming command. As with all bits in the CFI/OTP space,
after the permanent lock or the configuration bits are programmed, they may not be
erased (set) again.
Registers
Read Status Register
The device’s status register displays PROGRAM and ERASE operation status. A device’s
status can be read after writing the READ STATUS REGISTER command. The status
register can also be read following a PROGRAM, ERASE, or LOCK BLOCK command
sequence. Subsequent single reads from the device outputs its status until another valid
command is written.
The last of OE# or CE# falling edge latches and updates the status register content.
DQ[7:0] output is the satus register bits; DQ[15:8] output 00h. See Table 17 on page 30.
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System Protection Registers
Issuing a READ STATUS, BLOCK LOCK, PROGRAM, or ERASE command to the device
places it in the read status mode. Status register bit SR7 (DWS — device write status)
provides program/erase status of the device. Status register bits SR1–SR6 present information about the WSM’s program, erase, suspend, VPP, and block lock status mode.
Table 17:
Status Register Definitions
DRS
ESS
ES
PS
VPPS
PSS
DPS
PRW
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Status Register Bits
Notes
SR7 = Device write/erase status (DWS)
0 = Device WSM is busy
1 = Device WSM is ready
SR6 = Erase suspend status (ESS)
0 = Erase in progress/completed
1 = Erase suspended
SR5 = Erase status (ES)
0 = Successful erase
1 = Erase error
SR4 = Program status (PS)
0 = Successful write
1 = Write error
SR3 = VPP status (VPPS)
0 = VPP OK
1 = VPP low detect, operation aborted
SR2 = Program suspend status (PSS)
0 = Write in progress/completed
1 = Write suspended
SR1 = Device protect status (DPS)
0 = Unlocked
1 = Aborted erase/program attempt on
locked block
SR0 Super Page write status (PRW)
0 = Reserved
1 = Reserved
SR7 indicates erase or program completion in the device. SR1–6 are invalid
while SR7 = 0
After issuing an ERASE SUSPEND command, the WSM halts and sets (1) SR7
and SR6. SR6 remains set until the device receives an ERASE RESUME
command.
SR5 is set (1) if an attempted erase failed.
A command sequence error is indicated when SR4, SR5, and SR7 are set.
SR4 is set (1) if the WSM failed to program.
A command sequence error is indicated when SR4, SR5, and SR7 are set.
The WSM indicates the VPP level after program or erase starts. SR3 does not
provide continuous VPP feedback and isn’t guaranteed when VPP VPPLK
After receiving a WRITE SUSPEND command, the WSM halts execution and
sets (1) SR7 and SR2, which remains set until a RESUME command is
received.
If an ERASE or PROGRAM operation is attempted to a locked block (if WP#
= VIL), the WSM sets (1) SR1 and aborts the operation.
Reserved
CLEAR STATUS REGISTER Command
The CLEAR STATUS REGISTER command clears the status register. The command functions independently of the applied VPP voltage. The WSM can set (1) status register bits
SR[7:0] and clear (0) bits 2, 6, and 7. Because bits 1, 3, 4, and 5 indicate various error
conditions, they can only be cleared by the Cclear status register command. By allowing
system software to reset these bits, several operations (such as cumulatively programming several addresses or erasing multiple blocks in sequence) may be performed
before reading the status register to determine error occurrence. The status register
should be cleared before beginning another command or sequence. Device reset (RST#
= VIL) also clears the status register.
System Protection Registers
The device contains two 64-bit, and sixteen 128-bit individually lockable protection
registers that can increase system security or hinder device substitution by containing
values that mate the PCM component to the system’s CPU or ASIC.
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128Mb: P8P Parallel PCM
System Protection Registers
One 64-bit protection register is programmed at the Micron factory with an nonchangeable unique 64-bit number. The other 64-bit and sixteen 128-bit protection registers are blank so customers can program them as desired. Once programmed, each
customer segment can be locked to prevent further reprogramming.
Read Protection Register
The READ IDENTIFIER command allows protection register data to be read 16 bits at a
time from addresses shown in Table 9 on page 18. To read the protection register, first
issue the READ DEVICE IDENTIFIER command at device base address to place the
device in the read device identifier mode. Next, perform a READ operation at the device’s
base address plus the address offset corresponding to the register to be read. Table 9 on
page 18 shows the address offsets of the protection registers and lock registers. Register
data is read 16 bits at a time. Refer Table 18 on page 32.
Program Protection Register
The PROTECTION PROGRAM command should be issued followed by the data to be
programed at the specified location. It programs the 64 user protection register 16 bits at
a time. Table 9 on page 18 and in Table 18 on page 32 show allowable addresses. See also
Figure 38 on page 68. Addresses A[MAX:11] are ignored when programming the OTP, and
OTP program will succeed if A[10:1] are within the prescribed protection addressing
range; otherwise an error is indicated by SR4 = 1.
Lock Protection Register
Each of the protection registers are lockable by programming their respective lock bits in
the PR-LOCK0 or PR-LOCK1 registers. Bit 0 of the lock register -0 is programmed by
Micron to lock-in the unique device number. The physical address of the PR-LOCK0
register is 80h as seen in Figure 8 on page 32. Bit 1 of the lock register -0 can be
programmed by the user to lock the upper 64-bit portion. (Refer Table 18 on page 32.).
The bits in both PR-LOCK registers are made of PCM cells that may only be programmed
to 0 and may not be altered.
Note:
Bit0 of the lock register, PR-LOCK0, is a “Don’t Care,” so users must mask out this bit
when reading PR LOCK0 register. This number is guaranteed to persist through board
attach.
For the 2K OTP space, there exists an additional 16-bit lock register called PR_LOCK1.
Each bit in the PR_LOCK1 register locks a 128-bit segment of the 2K OTP space. Therefore, the 16 128-bit segments of the 2K OTP space can be locked individually. Hence, any
128-bit segment can be first programmed and then locked using the PROTECTION
PROGRAM command followed by protection register data. The PR-LOCK1 register is
physically located at the address 89h as shown in the Figure 8 on page 32.
After PR-LOCK register bits have been programmed, no further changes can be made to
the protection registers' stored values. PROTECTION PROGRAM commands written to a
locked section result in a status register error (program error bit SR4 and lock error bit
SR1 are set to 1). Once locked, protection register states are not reversible.
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128Mb: P8P Parallel PCM
System Protection Registers
Figure 8:
Protection Register Memory Map
109h
8 words
user programmed
..
.
102h
91h
8 words
user programmed
8Ah
89h
Lock register 1
88h
4 words (64 bits)
user programmed
85h
84h
4 words (64 bits)
Intel factory programmed
81h
80h
Lock register 0
OTP Protection Register Addressing Details
Table 18:
Protection Register Addressing
Word
Use
ID Offset
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
0
1
2
3
4
5
6
7
Both
Micron
Micron
Micron
Micron
Customer
Customer
Customer
Customer
DBA + 000080h
DBA + 000081h
DBA + 000082h
DBA + 000083h
DBA + 000084h
DBA + 000085h
DBA + 000086h
DBA + 000087h
DBA + 000088h
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Notes:
Table 19:
1. Addresses A[23:9] should be set to zero.
2K OTP Space Addressing
Word
Use
ID Offset
Lock
0
:
:
127
Customer
Customer
:
:
Customer
DBA+000089h
DBA+00008Ah
:
:
DBA+000109h
Notes:
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A13 A12 A11 A10 A9
0
0
:
:
0
0
0
:
:
0
0
0
:
:
0
0
0
:
:
0
0
0
:
:
1
A8
A7
A6
A5
A4
A3
A2
A1
1
1
:
:
0
0
0
:
:
0
0
0
:
:
0
0
0
:
:
0
1
1
:
:
1
0
0
:
:
0
0
1
:
:
0
1
0
:
:
1
1. DBA - Device base address. Typically this would start from address 0.
32
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
SPI Overview
A serial peripheral interface has been added as a secondary interface on P8P parallel
PCM to enable low cost, low pin count on-board programming. This interface gives
access to the P8P parallel PCM memory by using only seven signals, instead of a conventional parallel interface that may take 45 signals or more. The seven signals consist of six
SPI-only signals plus one signal that is shared with the conventional interface.
When the SPI mode is enabled, all non-SPI P8P parallel PCM output signals are tristated, and all non-SPI P8P parallel PCM inputs signals are ignored (made “Don't Care”).
When the conventional interface is enabled, the SPI-only output is tri-stated, and the
SPI-only inputs are ignored (made “Don't Care”).
Note:
The SPI interface can only be enable upon power-up and to enable this interface, the
SERIAL pin must be tied to VCC for the interface to be factional. Once the SPI interface
is enabled, it is the only interface that can be accessed until the part is powered down.
The SPI mode may be disabled. Please contact Micron for more information.
SPI Signal Names
For P8P parallel PCM, the six additional SPI-only signals are implemented in addition to
the power pins. VCC, VCCQ, and VPP are valid power pins during serial mode and must be
connected during SPI mode operation. Four of the six additional SPI signals do not share
functions with the regular interface. For pin and signal descriptions of all P8P parallel
PCM pins see Table 5 on page 12. Two pins are shared between the interface modes: S# is
the same pin as CE#, and HOLD# is the same pin as OE#. The signals that are unique to
the SPI mode and require a separate connection are C, D, Q, and SERIAL.
SPI Memory Organization
The memory is organized as:
• 16,772,216 bytes (8 bits each)
• 128 sectors (128 Kbytes each)
• 131,072 pages (64 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0) or written
(bit alterable: 1 can be altered to 0 and 0 can be altered to 1). The device is sector or bulk
erasable (bits are erased from 0 to 1).
Table 20:
Sector
127
126
125
124
123
122
121
120
119
118
Memory Organization
Address Range
FE0000
FC0000
FA0000
F80000
F60000
F40000
F20000
F00000
EE0000
EC0000
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Sector
FFFFFF
FDFFFF
FBFFFF
F9FFFF
F7FFFF
F5FFFF
F3FFFF
F1FFFF
EFFFFF
EDFFFF
63
62
61
60
59
58
57
56
55
54
33
Address Range
7E0000
7C0000
7A0000
780000
760000
740000
720000
700000
6E0000
6C0000
7FFFFF
7DFFFF
7BFFFF
79FFFF
77FFFF
75FFFF
73FFFF
71FFFF
6FFFFF
6DFFFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Table 20:
Memory Organization (Continued)
Sector
Address Range
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
EA0000
E80000
E60000
E40000
E20000
E00000
DE0000
DC0000
DA0000
D80000
D60000
D40000
D20000
D00000
CE0000
CC0000
CA0000
C80000
C60000
C40000
C20000
C00000
BE0000
BC0000
BA0000
B80000
B60000
B40000
B20000
B00000
AE0000
AC0000
AA0000
A80000
A60000
A40000
A20000
A00000
9E0000
9C0000
9A0000
980000
960000
940000
920000
900000
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Sector
EBFFFF
E9FFFF
E7FFFF
E5FFFF
E3FFFF
E1FFFF
DFFFFF
DDFFFF
DBFFFF
D9FFFF
D7FFFF
D5FFFF
D3FFFF
D1FFFF
CFFFFF
CDFFFF
CBFFFF
C9FFFF
C7FFFF
C5FFFF
C3FFFF
C1FFFF
BFFFFF
BDFFFF
BBFFFF
B9FFFF
B7FFFF
B5FFFF
B3FFFF
B1FFFF
AFFFFF
ADFFFF
ABFFFF
A9FFFF
A7FFFF
A5FFFF
A3FFFF
A1FFFF
9FFFFF
9DFFFF
9BFFFF
99FFFF
97FFFF
95FFFF
93FFFF
91FFFF
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
34
Address Range
6A0000
680000
660000
640000
620000
600000
5E0000
5C0000
5A0000
580000
560000
540000
520000
500000
4E0000
4C0000
4A0000
480000
460000
440000
420000
400000
3E0000
3C0000
3A0000
380000
360000
340000
320000
300000
2E0000
2C0000
2A0000
280000
260000
240000
220000
200000
1E0000
1C0000
1A0000
180000
160000
140000
120000
100000
6BFFFF
69FFFF
67FFFF
65FFFF
63FFFF
61FFFF
5FFFFF
5DFFFF
5BFFFF
59FFFF
57FFFF
55FFFF
53FFFF
51FFFF
4FFFFF
4DFFFF
4BFFFF
49FFFF
47FFFF
45FFFF
43FFFF
41FFFF
3FFFFF
3DFFFF
3BFFFF
39FFFF
37FFFF
35FFFF
33FFFF
31FFFF
2FFFFF
2DFFFF
2BFFFF
29FFFF
27FFFF
25FFFF
23FFFF
21FFFF
1FFFFF
1DFFFF
1BFFFF
19FFFF
17FFFF
15FFFF
13FFFF
11FFFF
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Table 20:
Memory Organization (Continued)
Sector
Address Range
71
70
69
68
67
66
65
64
8E0000
8C0000
8A0000
880000
860000
840000
820000
800000
Sector
8FFFFF
8DFFFF
8BFFFF
89FFFF
87FFFF
85FFFF
83FFFF
81FFFF
7
6
5
4
3
2
1
0
Address Range
0E0000
0C0000
0A0000
080000
060000
040000
020000
000000
0FFFFF
0DFFFF
0BFFFF
09FFFF
07FFFF
05FFFF
03FFFF
01FFFF
SPI Instruction
Serial data input D is sampled on the first rising edge of serial clock (C) after chip select
(S#) is driven LOW. Then, the one-byte instruction code must be shifted in to the device,
most significant bit first, on serial data input DQ0, each bit being latched on the rising
edges of C. The instruction set is listed in Table 21 on page 35.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
In the case of a read data bytes (READ), read data bytes at higher speed (FAST_READ),
read status register (RDSR), or read identification (RDID) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. S# can be driven HIGH after
any bit of the data-out sequence is being shifted out.
In the case of a page program (PP), sector erase (SE), write status register (WRSR), write
enable (WREN), or write disable (WRDI), S# must be driven HIGH exactly at a byte
boundary, otherwise the instruction is rejected and is not executed. That is, S# must
driven HIGH when the number of clock pulses after S# being driven LOW is an exact
multiple of eight.
All attempts to access the memory array during a WRITE STATUS REGISTER cycle,
PROGRAM cycle, adn ERASE cycle are ignored, and the internal WRITE STATUS
REGISTER cycle, PROGRAM cycle, and ERASE cycle continues unaffected.
Note:
Table 21:
Output High-Z is defined as the point where data out is no longer driven.
Instruction Set
Instruction
Description
WREN
WRDI
RDID
RDSR
WRSR
READ
FAST_READ
PP
Write enable
Write disable
Read identification
Read status register
Write status register
Read data bytes
Read data bytes at higher speed
Page program (legacy program)
Page program (bit-alterable write)
Page program (On all 1s)
Sector erase
SE
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One-byte Instruction Code
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
0010 0010
1101 0001
1101 1000
35
06h
04h
9Fh
05h
01h
03h
0Bh
02h
22h
D1h
D8h
Address
Bytes
Dummy
Bytes
Data
Bytes
0
0
0
0
0
3
3
3
3
3
3
0
0
0
0
0
0
1
0
0
0
0
0
0
1 to 3
1 to
1
1 to
1 to
1 to 64
1 to 64
1 to 64
0
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
WRITE ENABLE (WREN)
The WRITE ENABLE (WREN) instruction sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every PAGE PROGRAM (PP),
SECTOR ERASE (SE), or WRITE STATUS REGISTER (WRSR) instruction.
The WREN instruction is entered by driving S# LOW, sending the instruction code and
then driving S# HIGH.
Figure 9:
WRITE ENABLE (WREN) Instruction Sequence
S#
0
1
2
3
4
5
6
7
C
Command
DQ0
High-Z
DQ1
WRITE DISABLE (WRDI)
The WRITE DISABLE (WRDI) instruction resets the write enable latch (WEL) bit.
The WRDI instruction is entered by driving S# LOW, sending the instruction code and
then driving S# HIGH.
The write enable latch (WEL) bit is reset under the following conditions:
• Power-up
• WRDI instruction completion
• WRSR instruction completion
• PP instruction completion
• SE instruction completion
Figure 10:
WRITE DISABLE (WRDI) Instruction Sequence
S#
0
1
2
3
4
5
6
7
C
Command
DQ0
DQ1
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High-Z
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
READ IDENTIFICATION (RDID)
The READ IDENTIFICATION (RDID) instruction allows to read the device identification
data:
• Manufacturer identification (1 byte)
• Device identification (2 bytes)
The manufacturer identification is assigned by JEDEC and has the value 20h for Micron.
Any RDID instruction while an ERASE or PROGRAM cycle is in progress, is not decoded,
and has no effect on the cycle that is in progress.
The device is first selected by driving S# LOW. Then, the 8-bit instruction code for the
instruction is shifted in. After this, the 24-bit device identification stored in the memory
will be shifted out on serial data output (DQ1). Each bit is shifted out during the falling
edge of C.
The RDID instruction is terminated by driving S# HIGH at any time during data output.
When S# is driven HIGH, the device is put in the standby power mode. Once in the
standby power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Figure 11:
READ IDENTIFICATION (RDID) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
C
Command
DQ0
High-Z
Manufacturer identification
DQ1
Device identification
15 14 13
MSB
3
2
1
0
MSB
Read Status Register (RDSR)
The READ STATUS REGISTER (RDSR) instruction allows the status register to be read.
The status register may be read at any time, even while a PROGRAM, ERASE, WRITE
STATUS REGISTER is in progress. When one of these cycles is in progress, it is recommended to check the write in progress (WIP) bit before sending a new instruction to the
device. It is also possible to read the status register continuously, as shown in Figure 8 on
page 32
RDSR is the only instruction accepted by the device while a PROGRAM, ERASE, WRITE
STATUS REGISTER operation is in progress.
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Table 22:
Status Register Format
b7
b0
SRWD
BP3
TB
BP2
BP1
BP0
WEL
WIP
Status register write protect
RFU
RFU
Write enable latch bit
Write in progress bit
The status and control bits of the status register are as follows:
WIP Bit
The write in progress (WIP) bit indicates whether the memory is busy with a WRITE
STATUS REGISTER, PROGRAM, ERASE cycle. When set to 1, such a cycle is in progress,
when reset to 0 no such cycle is in progress.
While WIP is 1, RDSR is the only instruction the device will accept; all other instructions
are ignored.
WEL Bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
When set to 1, the internal write enable latch is set; when set to 0, the internal write
enable latch is reset, and no WRITE STATUS REGISTER, PROGRAM, ERASE instruction
is accepted.
BP3, BP2, BP1, BP0 Bits
The block protect bits (BP3, BP2, BP1, BP0) are nonvolatile. They define the size of the
area to be software protected against PROGRAM (or WRITE) and ERASE instructions.
These bits are written with the WRSR instruction. When one or more of the block protect
bits is set to 1, the relevant memory area (as defined in Table 1) becomes protected
against PP, DIFP, QIFP, and SE instructions. The block protect bits can be written
provided that the hardware protected mode has not been set.The bulk erase (BE)
instruction is executed if, and only if, all block protect bits are 0.
Table 23:
Protected Area Sizes
Status Register Contents
Memory Content
TB
Bit
BP
Bit 3
BP
Bit 2
BP
Bit 1
BP
Bit 0
Protected Area
Unprotected Area
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X2
0
0
1
1
0
0
1
1
X2
0
1
0
1
0
1
0
1
X2
None
Upper 128th (sector 127)
Upper 64th (sectors 126 to 127)
Upper 32nd (sectors 124 to 127)
Upper 16th (sectors 120 to 127)
Upper 8th (sectors 112 to 127)
Upper quarter (sectors 96 to 127)
Upper half (sectors 64 to 127)
All sectors (sectors 0 to 127)
All sectors1 (sectors 0 to 127)
Sectors 0 to 126
Sectors 0 to 125
Sectors 0 to 123
Sectors 0 to 119
Sectors 0 to 111
Sectors 0 to 95
Sectors 0 to 63
None
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Table 23:
Protected Area Sizes (Continued)
Status Register Contents
Memory Content
TB
Bit
BP
Bit 3
BP
Bit 2
BP
Bit 1
BP
Bit 0
Protected Area
Unprotected Area
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
X2
0
0
1
1
0
0
1
1
X2
0
1
0
1
0
1
0
1
X2
None
Lower 128th (sector 0)
Lower 64th (sectors 0 to 1)
Lower 32nd (sectors 0 to 3)
Lower 16th (sectors 0 to 7)
Lower 8th (sectors 0 to15)
Lower 4th (sectors 0 to 31)
Lower half (sectors 0 to 63)
All sectors (sectors 0 to 127)
All sectors1 (sectors 0 to 127)
Sectors 1 to 127
Sectors 2 to 127
Sectors 4 to 127
Sectors 8 to 127
Sectors 16 to 127
Sectors 32 to 127
Sectors 64 to 127
None
Notes:
1. The device is ready to accept a bulk erase instruction if all block protect bits (BP3, BP2, BP1,
BP0) are 0.
2. X can be 0 or 1.
Top/Bottom Bit
The top/bottom bit reads as 0.
SRWD Bit
The status register write disable (SRWD) bit is operated in conjunction with the write
protect (W) signal. The status register write disable (SRWD) bit and the W signal allow
the device to be put in the hardware protected mode (when the status register write
disable (SRWD) bit is set to 1, and W is driven LOW). In this mode, the nonvolatile bits of
the status register (SRWD, TB, BP3, BP2, BP1, BP0) become read-only bits and the write
status register (WRSR) instruction is no longer accepted for execution.
Figure 12:
READ STATUS REGISTER (RDSR) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Command
DQ0
DQ1
Status register out
Status register out
High-Z
7
6
5
4
MSB
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
WRITE STATUS REGISTER (WRSR)
The WRITE STATUS REGISTER (WRSR) instruction allows new values to be written to
the status register. Before it can be accepted, a WREN instruction must previously have
been executed. After the WREN instruction has been decoded and executed, the device
sets the write enable latch (WEL).
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
The WRSR instruction is entered by driving S# LOW, followed by the instruction code
and the data byte on serial data input (DQ0).
The WRSR instruction has no effect on b1 and b0 of the status register.
S# must be driven HIGH after the eighth bit of the data byte has been latched in. If not,
the WRSR instruction is not executed. As soon as S# is driven HIGH, the self-timed
WRITE STATUS REGISTER cycle (whose duration is tW) is initiated. While the WRITE
STATUS REGISTER cycle is in progress, the status register may still be read to check the
value of the write in progress (WIP) bit. The WIP bit is 1 during the self-timed WRITE
STATUS REGISTER cycle, and is 0 when it is completed. When the cycle is completed,
the WEL is reset.
The WRSR instruction allows the user to change the values of the block protect bits to
define the size of the area that is to be treated as read-only. The WRSR instruction also
allows the user to set and reset the SRWD bit in accordance with the W signal. The SRWD
bit and W signal allow the device to be put in the hardware protected mode (HPM). The
WRSR instruction is not executed once the hardware protected mode (HPM) is entered.
RDSR is the only instruction accepted while WRSR operation is in progress; all other
instructions are ignored.
Figure 13:
WRITE STATUS REGISTER (WRSR) Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Status
register in
Command
DQ0
7
6
5
4
3
2
1
0
MSB
High-Z
DQ1
Read Data Bytes (READ)
The device is first selected by driving S# LOW. The instruction code for the READ
instruction is followed by a 3-byte address A[23:0], each bit being latched-in during the
rising edge of C. Then the memory contents, at that address, is shifted out on serial data
output (Q), each bit being shifted out, at a maximum frequency fR, during the falling
edge of C.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole
memory can, therefore, be read with a single READ instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The READ instruction is terminated by driving S# HIGH. S# can be driven HIGH at any
time during data output. Any READ instruction, while an ERASE, PROGRAM, WRITE
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Figure 14:
Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
1
0
MSB
DQ1
Data-out 2
Data-out 1
High-Z
7
6
5
4
3
2
1
0
7
MSB
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving S# LOW. The instruction code for the read data
bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0]
and a dummy byte, each bit being latched-in during the rising edge of C. Then the
memory contents, at that address, are shifted out on Q at a maximum frequency fC,
during the falling edge of C.
The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole
memory can, therefore, be read with a single FAST_READ instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The FAST_READ instruction is terminated by driving S# HIGH. S# can be driven HIGH at
any time during data output. Any FAST_READ instruction, while an ERASE, PROGRAM,
or WRITE cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
Figure 15:
FAST_READ Instruction Sequence and Data-Out Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
1
0
High-Z
DQ1
1
S#
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
C
Dummy cycles
DQ0
7
6
5
4
3
2
1
0
Data-out 2
Data-out 1
DQ1
7
1
6
5
4
3
2
1
0
7
MSB
MSB
6
5
4
3
2
1
0
7
MSB
PAGE PROGRAM (PP)
Note:
The following description of PAGE PROGRAM applies to all instances of PP, including
legacy program and bit alterable.
The PP instruction allows bytes to be programmed/written in the memory. Before it can
be accepted, a WREN instruction must previously have been executed. After the WREN
instruction has been decoded, the device sets the WEL.
The PP instruction is entered by driving S# LOW, followed by the instruction code, three
address bytes, and at least one data byte on serial data input (DQ0). If the six least significant address bits (A[5:0]) are not all zero, all transmitted data that goes beyond the end
of the current page are programmed from the start address of the same page (from the
address whose six least significant bits (A[5:0]) are all zero). S# must be driven LOW for
the entire duration of the sequence.
If more than 64 bytes are sent to the device, previously latched data are discarded and
the last 64 data bytes are guaranteed to be programmed/written correctly within the
same page. If fewer than 64 data bytes are sent to device, they are correctly
programmed/written at the requested addresses without having any effects on the other
bytes of the same page. (With PROGRAM ON ALL 1s, the entire page should already have
been set to all 1s (FFh).)
For optimized timings, it is recommended to use the PP instruction to program all
consecutive targeted bytes in a single sequence versus using several PP sequences with
each containing only a few bytes.
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128Mb: P8P Parallel PCM
Serial Peripheral Interface (SPI)
S# must be driven HIGH after the eighth bit of the last data byte has been latched in,
otherwise the PP instruction is not executed.
As soon as S# is driven HIGH, the self-timed PAGE PROGRAM cycle (whose duration is
t
PP) is initiated. While the PAGE PROGRAM cycle is in progress, the status register may
be read to check the value of the WIP bit. The WIP bit is 1 during the self-timed PAGE
PROGRAM cycle, and is 0 when it is completed. At some unspecified time before the
cycle is completed, the WEL bit is reset. RDSR is the only instruction accepted while a
PAGE PROGRAM operation is in progress; all other instructions are ignored.
Figure 16:
PAGE PROGRAM (PP) Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
24-bit address
note 1
Command
DQ0
23 22 21
3
2
Data byte 1
1
0
7
6
5
4
3
2
1
0
MSB
MSB
1
2078
2079
2077
2076
2075
2074
2072
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
2072
S#
1
0
C
DQ0
7
6
5
4
MSB
3
2
Data byte 64
Data byte 3
Data byte 2
1
0
7
6
5
4
3
MSB
2
1
0
7
6
5
4
3
2
MSB
1
SECTOR ERASE (SE)
The SECTOR ERASE (SE) instruction sets to 1 (FFh) all bits inside the chosen sector.
Before it can be accepted, a WREN instruction must previously have been executed.
After the WREN instruction has been decoded, the device sets the WEL.
The SE instruction is entered by driving S# LOW, followed by the instruction code, and
three address bytes on DQ0. Any address inside the sector is a valid address for the SE
instruction. S# must be driven LOW for the entire duration of the sequence.
S# must be driven HIGH after the eighth bit of the last address byte has been latched in,
otherwise the SE instruction is not executed. As soon as S# is driven HIGH, the selftimed SE cycle (whose duration is tSE) is initiated. While the SE cycle is in progress, the
status register may be read to check the value of the WIP bit. The WIP bit is 1 during the
self-timed SE cycle and is 0 when it is completed. At some unspecified time before the
cycle is completed, the WEL bit is reset. RDSR is the only instruction accepted while
device is busy with ERASE operation; all other instructions are ignored.
An SE instruction applied to a page which is protected by the block protect bits is not
executed.
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128Mb: P8P Parallel PCM
Power and Reset Specification
Figure 17:
SECTOR ERASE (SE) Instruction Sequence
S#
0
1
2
3
4
5
6
7
8
9
29 30 31
C
24-bit address
note 1
Command
DQ1
23 22
2
1
0
MSB
Power and Reset Specification
Power-Up and Power-Down
Upon power-up the Flash memory interface is defined by the SERIAL pin being at VSS
(parallel) or VCC (serial).
• During power-up if the SERIAL pin is at VSS the Flash memory will be a x16 parallel
interface.
• During power-up if the SERIAL pin is at VCC the Flash memory will be a SPI interface.
After the interface is defined it can not be changed until a full power-down is completed
and a power-up sequence is reinitiated.
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is LOW. This protects the device
from accidental programming or erasure during power transitions.
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from Flash memory when coming out
of RESET. If a CPU reset occurs without a Flash memory reset, proper CPU initialization
may not occur. This is because the Flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active LOW RESET signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 24:
Power and Reset
Num
Symbol
Parameter1
Min
Max
Unit
Notes
P1
P2
tPLPH
tPLRH
tVCCPH
100
100
40
40
-
ns
us
P3
RST# pulse width LOW
RST# LOW to device reset during erase
RST# LOW to device reset during program
VCC power valid to RST# de-assertion (HIGH)
1, 2, 3, 4
1, 3, 4, 7
1, 3, 4,7
1, 4, 5, 6
Notes:
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1. These specifications are valid for all device versions (packages and speeds).
2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
3. Not applicable if RST# is tied to VCC.
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Power and Reset Specification
4. Sampled, but not 100% tested.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC VCCMIN.
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC VCCMIN.
7. Reset completes within tPLPH if RST# is asserted while no ERASE or PROGRAM operation is
executing.
Figure 18:
Reset Operation Waveforms
tPLPH
(A) Reset during
read mode
RST# [P]
tPHQV
VIH
VIL
tPLRH
(B) Reset during
program or block erase RST# [P]
P1 ≤ P2
tPHQV
VIH
VIL
tPLRH
(C) Reset during
program or block erase RST# [P]
P1 ≥ P2
Abort
complete
Abort
complete
tPHQV
VIH
VIL
tVCCPH
(D) VCC power-up to
RST# HIGH
VCC
VCC
0V
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are standby current levels, active current levels, and transient peaks produced when CE# and OE# are asserted and de-asserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of these
internal activities produce transient signals. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading. Two-line control and correct decoupling capacitor selection suppress transient voltage peaks.
Flash memory devices draw their power from VCC and VCCQ; each power connection
should have a 0.1µF ceramic capacitor to ground. High-frequency, inherently low-inductance capacitors should be placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
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128Mb: P8P Parallel PCM
Maximum Ratings and Operating Conditions
Maximum Ratings and Operating Conditions
Absolute Maximum Ratings
Stresses greater than those listed in Table 25 may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at these or any
other conditions outside those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may adversely affect reliability.
Table 25:
Absolute Maximum Ratings
Parameter
Maximum Rating
Voltage on any signal (except
VPP voltage2, 4
VCC voltage2, 4
VCCQ voltage2, 4, 5
Output short circuit current3
Notes:
VCC, VCCQ, VPP)1
–2.0V to +5.6V, < 20ns
–2.0V to +5.6V, < 20ns
–2.0V to +5.6V, < 20ns
–2.0V to +5.6V, < 20ns
100mA
1. All specified voltages are with respect to VSS. During infrequent non-periodic transitions,
the voltage potential between VSS and input/output pins may undershoot to –2.0V for periods < 20ns or overshoot to VCCQ + 2.0Vfor periods < 20ns.
2. During infrequent non-periodic transitions, the voltage potential between VSS and the supplies may undershoot to –2.0V for periods < 20ns or overshoot to supply voltage (max) +
2.0V for periods < 20ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. For functional operating voltages, please refer to “DC Voltage Characteristics” on page 48.
5. Make sure that VCCQ is less or equal to VCC in value, otherwise the device fails to operate
correctly in the next revision of the data sheet.
Operating Conditions
Operation beyond the operating conditions is not recommended, and extended exposure may affect device reliability.
Table 26:
Operating Conditions
Symbol
TC
TC
VCC
VCCQ
Parameter
Operating temperature (115ns)
Operating temperature (135 ns)
VCC supply voltage
I/O supply voltage
CMOS inputs
TTL inputs
VPP voltage supply (logic level)
VPP
Notes:
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Min
Max
Units
Notes
0
–40
2.7
1.7
2.4
0.9
70
85
3.6
3.6
3.6
3.6
°C
°C
V
1
2
3
1. TC = case temperature.
2. VCCQ = 1.7–3.6V range is intended for CMOS inputs and the 2.4–3.6V is intended for TTL
inputs.
3. In typical operation VPP program voltage is VPPL.
4. Data retention for Micron PCM is 10 years at 70°C. For additional documentation about
data retention, contact your local Micron sales representative.
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128Mb: P8P Parallel PCM
Electrical Specifications
Endurance
P8P parallel PCM endurance is different than traditional nonvolatile memory. For PCM a
WRITE cycle is defined as any time a bit changes within a 32-byte page.
Table 27:
Endurance
Parameter
Condition
Min
Units
Notes
Write cycle
Main block (VPP = VPPH)
Parameter block (VPP = VPPH)
1,000,000
1,000,000
Cycles per
32-byte page
1
Notes:
1. In typical operation VPP program voltage is VPPL.
Electrical Specifications
DC Current Characteristics
Table 28:
DC Current Characteristics
CMOS
Inputs
VCCQ
1.7–3.6V
TTL Inputs
VCCQ
2.4–3.6V
Sym
Parameter1
Note
Typ
Max
Typ
Max
Unit
Test Condition
ILI
Input load
9
–
±1
–
±2
µA
VCC = VCCMAX
VCCQ = VCCQMAX
VIN = VCCQ or GND
VCC = VCCMAX
VCCQ = VCCQMAX
VIN = VCCQ or GND
VCC = VCCMAX, VCCQ = VCCQMAX
CE# = VCCQ, RST# = VCCQ
WP# = VIH
Must reach stated ICCS µs
after CE# = VIH
Internal 8-word VCC = VCCMAX
READ
CE# = VIL
OE# = VIH
Inputs: VIH or
8-word READ
VIL
ILO
Output
leakage
DQ[15:0]
–
–
±1
–
±10
µA
ICCS
ICCD
VCC
standby,
powerdown
128Mb
11
80
160
80
160
µA
ICCR
Average
VCC
READ
Asynchronous single
word
f = 5 MHz (1 CLK)
Page mode
f = 13 MHz (9 CLK)
–
30
42
30
42
mA
–
15
20
15
20
mA
3,4,5,
12
6
35
50
36
51
mA
PROGRAM/ERASE in progress
µA
µA
CE# = VCCQ, SUSPEND in
progress
VPP = VPPL, SUSPEND in progress
µA
mA
mA
VPP VCC
WRITE in progress
ERASE in progress
ICCW,
ICCE
ICCWS
ICCES
IPPS
IPPWS
IPPES
IPPR
IPPW
IPPE
VCC WRITE,
VCC ERASE
VCC WRITE SUSPEND
VCC ERASE SUSPEND
VPP STANDBY
VPP WRITE SUSPEND
VPP ERASE SUSPEND
VPP READ
VPP WRITE
VPP ERASE
Notes:
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3
–
3
3
Refer to ICCS for each density
above.
0.2
5
0.2
5
2
0.05
0.05
15
0.10
0.10
2
0.05
0.05
15
0.10
0.10
1. Refer Table 29 on page 48 for the notes relevant to this table.
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AC Characteristics
DC Voltage Characteristics
Table 29:
DC Voltage Characteristics
CMOS Inputs
VCCQ
1.7–3.6V
TTL Inputs
VCCQ
2.4–3.6V
Sym
Parameter
Notes
Min
Max
Min
Max
Unit
VIL
VIH
VOL
Input LOW
Input HIGH
Output LOW
2
2
0
VCCQ – 0.4
–
0.4
VCCQ
0.1
0
2.0
0.6
VCCQ
0.1
V
V
V
VOH
Output HIGH
VCCQ – 0.1
–
VCCQ – 0.1
–
V
VPPLK
VLKO
VLKOQ
VPP lock out
VCC lock
VCCQ lock
–
1.5
0.9
0.4
–
–
–
1.5
0.9
0.4
–
–
V
V
V
Notes:
1
Test Condition
VCC = VCC,min
VCCQ = VCCQ,min
IOL = 100µA
VCC = VCC,min
VCCQ = VCCQ,min
IOH = –100µA
1. VPP; VPPLK inhibits ERASE and WRITE operations. Don’t use VPP outside the valid range.
2. VIL can undershoot to –1.0V for durations of 2ns or less and VIH can overshoot to
VCCQ(MAX)+1.0V for durations of 2 ns or less.
AC Characteristics
AC Test Conditions
Figure 19:
AC Input/Output Reference Waveform
VCC
Input VCC/2
0V
Notes:
Figure 20:
VIH
Test Points
VIL
VCC/2 Output
1. AC test inputs are driven at VCCQ for logic 1 and 0.0V for logic 0. Input/output timing
begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5ns. Worst-case speed occurs
at VCC = VCC,min.
Transient Equivalent Testing Load Circuit
Device under
test
Out
CL
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AC Characteristics
Table 30:
Test Configuration Component Value for Worst-Case Speed Conditions
Test Configuration
CL (pF) (includes jig capacitance)
VCCQ,min
30
Capacitance
Table 31:
Capacitance: TA = 25°C, f = 1 MHz1
Symbol
Parameter1
Min
Typ
Max
Unit
Condition
CIN
COUT
Input capacitance
Output capacitance
2
2
6
4
8
7
pF
pF
VIN = 0.0V
VOUT = 0.0V
Notes:
1. Sampled, not 100% tested.
AC Read Specifications
Table 32:
AC Read Specifications
0°C to 70°C
Number
Symbol
R1
R2
R3
R4
R5
R6
R7
tAVAV
R8
R9
R10
R11
R108
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
tEHEL
tAPA
Notes:
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parallel_pcm_2.fm - Rev. K 7/12 EN
–40°C to 85°C
Parameter1
Min
Max
Min
Max
Units
Notes
Read cycle time
Address to output valid
CE# LOW to output valid
OE# LOW to output valid
RST# HIGH to output valid
CE# LOW to output in Low-Z
OE# LOW to output in Low-Z
115
–
–
–
–
0
0
–
115
115
25
150
–
–
135
–
–
–
–
0
0
–
135
135
25
150
–
–
ns
ns
ns
ns
ns
ns
ns
–
–
0
24
24
–
–
–
0
24
24
–
ns
ns
ns
1, 4
1, 4
1, 4
1, 2, 4
1, 4
3, 4
1, 2, 3,
4
1, 3, 4
1, 3, 4
1, 3, 4
20
–
–
25
20
–
–
25
ns
ns
CE# HIGH to output in High-Z
tOE# HIGH to output in High-Z
Output hold from first occurring address,
CE#, or OE# change
CE# pulse width high
Page address access
1, 4
1. See Figure 19 on page 48 for timing measurements and maximum allowable input slew
rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to
t
ELQV.
3. Sampled, not 100% tested.
4. All specs apply to all densities.
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AC Characteristics
Figure 21:
Asynchronous Single-Word Read
tAVAV
tAVQV
Address
tELQV
tEHQZ
CE#
tGHQZ
tGLQV
OE#
tGLQX
tOH
tELQX
DQ
tPHQV
RST#
Figure 22:
Asynchronous Page Mode Read Timing
tAVAV
tAVQV
Address
tOH
tOH
tOH
tOH
A[3:1]
tELQV
tEHQZ
CE#
tGHQZ
tGLQV
OE#
tELQX
DQ
Q1
tAPA
tAPA
tAPA
Q2
Q3
Q7
AC Write Specifications
Table 33:
AC Write Characteristics
All Speeds
Num
Sym
W1
W2
W3
W4
W5
W6
W7
W8
W9
tPHWL
tELWL
t
WLWH
tDVWH
tAVWH
tWHEH
tWHDX
t
WHAX
tWHWL
Parameter1, 2
Min
Max
Units
Notes
RST# high recovery to WE# LOW
CE# setup to WE# LOW
WE# write pulse width LOW
Data setup to WE# HIGH
Address valid setup to WE# HIGH
CE# hold from WE# HIGH
Data hold from WE# HIGH
Address hold from WE# HIGH
WE# pulse width HIGH
150
0
50
50
50
0
0
0
20
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
10
4
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50
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AC Characteristics
Table 33:
AC Write Characteristics (Continued)
All Speeds
Num
W10
W11
W12
W13
W14
W16
Parameter1, 2
Sym
t
VPWH
QVVL
t
QVBL
t
BHWH
t
WHGL
t
WHQV
VPP setup to WE# HIGH
VPP hold from valid status read
WP# hold from valid status read
WP# setup to WE# HIGH
WE# HIGH to OE# LOW
WE# HIGH to read valid
t
Min
Max
Units
Notes
200
0
0
200
0
t
AVQV+35
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
3,6
3,6
3,6
3,6
8
3, 5, 9
0
–
ns
3, 5, 7
Write to Asynchronous Read Specifications
W18
t
WHAV
WE# HIGH to address valid
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
Figure 23:
Write timing characteristics during ERASE SUSPEND are the same as write-only operations.
CE#- or WE#-high terminates a WRITE operation.
Sampled, not 100% tested.
Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# LOW (whichever
occurs last) to CE# or WE# HIGH (whichever occurs first). Hence, tWLWH = tELEH = tWLEH =
tELWH.
Write pulse width HIGH (tWHWL or tEHEL) is defined from CE# or WE# HIGH (whichever is
first) to CE# or WE# LOW (whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
VPP and WP# should be at a valid level without changing state until erase or program success is determined.
This spec is only applicable when transitioning from a WRITE cycle to an asynchronous read.
When doing a READ STATUS operation following any command that alters the status register contents, W14 is 20ns.
Add 10ns if the WRITE operation results in a block lock status change, for subsequent READ
operations to reflect this change.
Guaranteed by design.
Write-to-Write Timing
tAVWH
tWHAV
tAVWH
tWHAV
Address
tELWL
tWHEH
tELWL
tWHEH
WE#
tWLWH
tWHWL
tWLWH
CE#
OE#
tDVWH
tWHDX
tDVWH
tWHDX
DQ
tPHWL
RST#
tBHWH
WP#
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AC Characteristics
Figure 24:
Asynchronous Read to Write Timing
tAVAV
tAVQV
tWHAX
tAVWH
Address
tELQV
tEHQZ
CE#
tGLQV
tGHQZ
OE#
tELWL
tWLWH
tWHEH
WE#
tGLQX
tWHDX
tELQX
tDVWH
tOH
Q
DQ
D
tPHQV
RST#
Notes:
Figure 25:
1. See AC Read Characteristics and AC Write Characteristics sections for the values of Rs and
Ws.
Write to Asynchronous Read Timing
tAVWH
tWHAX
tAVAV
Address
tELWL
tWHEH
tOH
CE#
tWLWH
tWHAV
WE#
tWHGL
OE#
tGLQV
tGHQZ
tAVQV
tDVWH
D
DQ
tWHDX
tELQV
tEHQZ
Q
tPHWL
RST#
Notes:
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1. See AC Read Characteristics and AC Write Characteristics sections for the values of Rs and
Ws.
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AC Characteristics
SPI AC Specifications
Table 34:
SPI AC Specifications
Speed
Sym
f
C
C
f
R
t
CH
tCL
t
CLCH
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tSHQZ
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHHQX
tHLQZ
tWHSL
tSHWL
f
Parameter
Note
Clock frequency for all instructions except READ (0°C to 70°C)
Clock frequency for all instructions except READ (–40°C to 85°C)
Clock frequency for READ
Clock high time
Clock low time
Clock rise time (peak to peak)
Clock fall time (peak to peak)
S# active setup time (relative to C)
S# active hold time (relative to C)
Data input setup time
Data input hold time
S# active hold time (relative to C)
S# inactive hold time (relative to C)
S# deselect time
Output disable time
Clock low to output valid
Output hold time
HOLD# assertion setup time (relative to C)
HOLD# assertion hold time (relative to C)
HOLD# de-assertion setup time (relative to C)
HOLD# de-assertion hold time (relative to C)
HOLD# de-assertion to output Low-Z
HOLD# de-assertion to output High-Z
W# setup time
W# hold time
Notes:
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1.
2.
3.
4.
1
1
2, 3
2, 3
2
2
2
4
4
All Speeds
Min
Max
Units
DC
DC
DC
9
9
0.1
0.1
5
5
2
5
5
5
100
–
–
0
5
5
5
5
50
33
25
–
–
–
–
–
–
–
–
–
–
–
8
9
–
–
–
–
–
10
10
–
–
MHz
MHz
MHz
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
100
TCH + TCL must be greater than or equal to 1/fC(max).
Sampled, not 100% tested.
Expressed as a slew rate.
Only applicable as a constraint for a WRSR instruction when SRWD is set to 1.
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AC Characteristics
Figure 26:
Serial Input Timing
tCHSL
tSLCH
tCHSH
tSHCH
C
tSHSL
S#
tDVCH
DQ0
tCHDX
MSB
LSB
Q
Figure 27:
Write Protect Setup and Hold Timing during WRSR when SRWD = 1
W#
tWHSL
tSHWL
S#
C
DQ0
DQ1
Figure 28:
High-Z
Hold Timing
S#
tCHHL
tHLCH
tHHCH
C
tCHHH
tHLQZ
tHHQX
DQ0
DQ1
HOLD#
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Program and Erase Characteristics
Figure 29:
Output Timing
S#
tCLQV
tCLQV
tCLQX
tCLQX
tCL
tCH
C
tSHQZ
DQ0
LSB out
DQ1 Address
LSB in
Program and Erase Characteristics
Table 35:
Program and Erase Specifications
VPPL4, 5
Operation1
Symbol
Parameter
Description
Min
Typ
Max
Unit
–
500
–
µs
–
–
–
–
100
400
35
35
200
800
60
60
ms
tSUSP P
/
tSUSP/E
ERASE or ERASE RESUME
command to ERASE
SUSPEND command
16KW parameter
64KW main
Write suspend
Erase suspend
W200
tPROG/W
Single word
–
60
120
µs
W200
tPROG/W
5
120
240
µs
W250
t
Single word
(legacy program and bitalterable write)
One buffer (64 bytes/32
words)
(legacy program and bitalterable write)
One buffer (64 bytes/32
words)
(program on all 1s)
4,5
120
360
µs
71
280
Erasing and Suspending
Erase to suspend
W602 3
tERS/SUSP
Erase time
W500
W501
W600
W601
tERS/PB
Suspend latency
tERS/MB
µs
Conventional Word Programming
Program time6
Buffered Programming
Program time
Notes:
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PROG/PB
1. Typical values measured at TA = 25°C, typical voltages and 50% data pattern per word.
Excludes system overhead. Performance numbers are valid for all speed versions. Sampled,
but not 100% tested.
2. Averaged over entire device.
3. W602 is the minimum time between an initial BLOCK ERASE or ERASE RESUME command
and the a subsequent ERASE SUSPEND command. Violating the specification repeatedly
during any particular BLOCK ERASE may cause erase failures in Flash devices. This specification is required if the designer wishes to maintain compatibility with the P33 NOR Flash
device. However, it is not required with PCM.
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Ordering Information
4. These performance numbers are valid for all speed versions.
5. Sampled, not 100% tested.
Ordering Information
Table 36:
Active Line Item Ordering Table (0°C to 70°C)
Part Number
NP8P128A13BSM60E
NP8P128A13TSM60E
NP8P128A13B1760E
NP8P128A13T1760E
Table 37:
Description
P8P 128Mb TSOP 14 x 20 Bottom Boot
P8P 128Mb TSOP 14 x 20 Top Boot
P8P 128M lead-free 10 x 8 x 1.2 easy BGA Bottom Boot
P8P 128M lead-free 10 x 8 x 1.2 easy BGA Top Boot
Active Line Item Ordering Table (–40°C to 85°C)
Part Number
NP8P128AE3BSM60E
NP8P128AE3TSM60E
NP8P128AE3B1760E
NP8P128AE3T1760E
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Description
P8P 128Mb TSOP 14 x 20 Bottom Boot
P8P 128Mb TSOP 14 x 20 Top Boot
P8P 128M lead-free 10 x 8 x 1.2 easy BGA Bottom Boot
P8P 128M lead-free 10 x 8 x 1.2 easy BGA Top Boot
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Supplemental Reference Information
Supplemental Reference Information
Flowcharts
Figure 30:
WORD PROGRAM or BIT-ALTERABLE WORD WRITE Flowchart
Start
Write 40h or 42h
word address
Program
setup
Write data
word address
Confirm
data
Read status
register
Suspend write
loop
No
0
SR7 =
Suspend
write
Yes
1
Full status check
(if desired)
Write
complete
Table 38:
WORD PROGRAM or BIT-ALTERABLE WORD WRITE Procedure
Bus Operation
Command
WRITE
PROGRAM/WRITE
SETUP
DATA
WRITE
READ
Standby
Notes:
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Notes
Data = 40h or 42h (bit alterable
Addr = Location to WRITE (WA)
Data = Data to be written (WD)
Addr = Location to be written (WA)
Status register data; initiate a READ cycle to update status register
Check SR7
1 = WSM ready
0 = WSM busy
1. Repeat for subsequent WRITE operations
2. Full status register check can be done after each WRITE or after a sequence of WRITE operations.
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Supplemental Reference Information
3. WRITE FFh after the last operation to end read array mode.
Figure 31:
Full WRITE STATUS CHECK Flowchart
Read status
register
SR3 =
1
VPP range
error
1
Write
error
1
Device protect
error
0
SR4 =
0
SR1 =
0
Write
successful
Table 39:
Full WRITE STATUS CHECK Procedure
Bus Operation
Command
STANDBY
Notes
Check SR3
1 = VPP error
Check SR4
1 = Data WRITE error
Check SR1
1 = Attempted to WRITE to locked block; WRITE aborted
STANDBY
STANDBY
Notes:
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1. SR3 must be cleared before the device will allow further WRITE attempts.
2. Only the CLEAR STATUS REGISTER command clears SR1, SR3, and SR4.
3. If an error is detected, clear the status register before attempting a WRITE RETRY or other
error recovery.
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Supplemental Reference Information
Figure 32:
WRITE SUSPEND/RESUME Flowchart
Start
Write 70hs
Read
status
Write B0h
any address
Program
suspend
Read status
register
SR7 =
0
1
SR2 =
0
Write
completed
1
Write FFh
Read array
Read array
data
Done
reading?
No
Yes
Write D0h
any address
Write
resume
Write FFh
Write
resumed
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Read array
Read array
data
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Table 40:
WRITE SUSPEND/RESUME Procedure
Bus Operation
Command
WRITE
READ STATUS
WRITE
WRITE SUSPEND
READ
STANDBY
STANDBY
WRITE
READ ARRAY
READ
WRITE
WRITE RESUME
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Notes
Data = 70h
Addr = Block to suspend (BA)
Data = B0h
Addr = X
Status register data; initiate a READ cycle to update status register
Addr = Suspended block (BA)
Check SR7
1 = WSM ready
0 = WSM busy
Check SR2
1 = Program suspended
0 = Program completed
Data = FFh
Addr = Block address to be read (BA)
Read array data from block other than the one being written
Data = D0h
Addr = Suspended block (BA)
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Supplemental Reference Information
Figure 33:
BUFFER PROGRAM or Bit-Alterable BUFFER WRITE Flowchart
Start
Device
supports buffer
writes?
No
Use single
word writes
Yes
Set timeout or
loop counter
Get next
target address
Issue WRITE-to-BUFFER
command E8h or EAh
and block address
Read status register
(at block address )
No
Is WSM
ready? SR[7] =
0 = No
Timeout
or count expired?
Yes
1 = Yes
Write word count,
block address
Write buffer data,
start address
X=X+1
X=0
Write buffer data,
block address
No
X = N?
No
Yes
Abort
bufferred
write?
Yes
Write confirm D0h
and block address
Write to another
block address
Buffered write
aborted
Read status
register
No
SR[7]?
0
Suspend
write?
Yes
Suspend
write loop
1
Full status
check (if desired)
Yes
Another
buffered
write?
No
Write
complete
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Table 41:
BUFFER PROGRAM OR BIT-ALTERABLE BUFFER WRITE Procedure
Bus Operation
Command
WRITE
WRITE TO BUFFER
READ
STANDBY
WRITE1, 2
WRITE3, 4
WRITE5, 6
WRITE
WRITE CONFIRM
READ
STANDBY
Notes:
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Notes
Data = E8H or EAH (bit alterable)
Addr = Block address
SR7 = Valid
Addr = Block address
Check SR7
1 = WSM busy
0 = WSM ready
Data = N - 1 = Word count
N = 0 corresponds to count = 1
Addr = Block address
Data = Write buffer data
Addr = Start address
Data = Write buffer data
Addr = Block address
Data = D0H
Addr = Block address
Status register data
CE# and CE# LOW updates SR
Addr = Block address
Check SR7
1 = WSM ready
0 = WSM busy
1. Word count values on DQ[7:0] are loaded into the count register. Count ranges for this
device are N = 0000h to 0001Fh.
2. The device outputs the status register when read.
3. Write buffer contents will be written at the device start address or destination Flash
address.
4. Align the start address on a write buffer boundary for maximum write performance (for
example, A[5:1] of the start address = 0).
5. The device aborts the BUFFERED PROGRAM command if the current address is outside the
original block address.
6. The status register indicates an improper command sequence if the BUFFERED PROGRAM
command is aborted. Follow this with a CLEAR STATUS REGISTER command.
7. Full status check can be done after all erase and write sequences are complete. Write FFh
after the last operation to reset the device to read array mode.
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Supplemental Reference Information
Figure 34:
BLOCK ERASE Flowchart
Start
Write 20h
block address
Block erase
Write data
word address
Erase confirm
Read status
register
Suspend erase
loop
No
0
SR7 =
Suspend
erase
Yes
1
Full status check
(if desired)
Block erase
complete
Table 42:
BLOCK ERASE Procedure
Bus Operation
Command
WRITE
BLOCK ERASE
SETUP
ERASE CONFIRM
WRITE
READ
STANDBY
Notes:
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Notes
Data = 20h
Addr = Block to be erased (BA)
Data = D0h
Addr = Block to be erased (BA)
Status register data; toddle CE# or OE# to update status register data
Check SR7
1 = WSM ready
0 = WSM busy
1. Repeat for subsequent block erasures
2. Full status register check can be done after each block erase or after a sequence of block
erasures.
3. Write FFh after the last operation to enter read array mode.
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Supplemental Reference Information
Figure 35:
BLOCK ERASE FULL ERASE STATUS CHECK Flowchart
Read status
register
SR3 =
1
VPP range
error
1
Command
sequence error
1
Block erase
error
1
Erase of locked
block aborted
0
SR4, 5 =
0
SR5 =
0
SR1 =
0
Block erase
successful
Table 43:
BLOCK ERASE FULL ERASE STATUS CHECK Procedure
Bus Operation
Command
STANDBY
Notes
Check SR3
1 = VPP error
Check SR4, SR5
1 = Command sequence error
Check SR5
1 = Block erase error
Check SR1
1 = Attempted erase of locked block erase aborted
STANDBY
STANDBY
STANDBY
Notes:
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1. Only the CLEAR STATUS REGISTER command clears SR1, SR3, SR4, and SR5.
2. If an error is detected, clear the status register before attempting an erase retry or other
error recovery.
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Supplemental Reference Information
Figure 36:
ERASE SUSPEND/RESUME Flowchart
Start
Write 70h
any address
Read status
Write B0h
any address
Erase
suspend
Read status
register
0
SR7 =
1
0
SR6 =
Erase
completed
1
Read
Read array
data
Read or
program?
No
Program
Program
loop
Done?
Yes
(Erase resume)
Read status
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Write D0h
any address
Erase
resumed
Write FFh
any address
Write 70h
any address
Read array
data
65
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Supplemental Reference Information
Table 44:
ERASE SUSPEND/RESUME Procedure
Bus Operation
Command
WRITE
READ STATUS
WRITE
READ
STANDBY
STANDBY
WRITE
READ or WRITE
WRITE
Notes
Data = 70h
Addr = Any device address
ERASE SUSPEND
Data = B0h
Addr = Same partition address as above
Status register data; toggle CE# or OE# to update status register
Addr = X
Check SR7
1 = WSM ready
0 = WSM busy
Check SR
1 = Erase suspended
0 = Erase completed
READ ARRAY OR Data = FFh or 40h
PROGRAM
Addr = Block to program or read
Read array or program data from/to block other than the one being erased
PROGRAM RESUME Data = D0h
Addr = Any address
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Supplemental Reference Information
Figure 37:
LOCKING OPERATIONS Flowchart
Optional
Start
Write 60h
block address
Lock setup
Write
01h/D0h/2Fh
block address
Lock confirm
Write 0x90
Read ID plane
Read block
lock status
Locking
change?
No
Yes
Write FFh
any address
Read array
Lock change
complete
Table 45:
LOCKING OPERATIONS Procedure
Bus Operation
Command
WRITE
LOCK SETUP
WRITE
WRITE (optional)
READ (optional)
Notes
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
LOCK, UNLOCK, OR Data = 01h (Lock block)
LOCKDOWN
D0h (Unlock block)
CONFIRM
2Fh (Lock-down block)
Addr = Block to lock/unlock/lock-down (BA)
READ ID PLANE
Data = 90h
Addr = Block address offset + 2 (BA + 2)
BLOCK LOCK
Block lock status data
STATUS
Addr = Block address offset + 2 (BA + 2)
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Supplemental Reference Information
Table 45:
LOCKING OPERATIONS Procedure (Continued)
Bus Operation
STANDBY
(optional)
WRITE
Figure 38:
Command
Notes
Confirm locking change on DQ1, DQ0 (see Table 14 on page 26 for valid
combinations)
Data = FFh
Addr = Block address (BA)
READ ARRAY
PROGRAM PROTECTION REGISTER Flowchart
Start
Write 0xC0,
PR address
Program
setup
Write PR
address and data
Confirm
data
Read status
register
0
SR7 =
1
Full status check
(if desired)
Program
complete
Table 46:
PROGRAM PROTECTION REGISTER Procedure
Bus Operation
Command
WRITE
PROGRAM PR
SETUP
PROTECTION
PROGRAM
None
None
WRITE
READ
IDLE
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Notes
Data = 0xC0
Addr = First location to program
Data = Data to program
Addr = Location to program
Status register data
Check SR7
1 = WSM ready
0 = WSM busy
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Supplemental Reference Information
Notes:
Figure 39:
1. PROGRAM PROTECTION REGISTER operation addresses must be within the protection register address space. Addresses outside this space will return an error.
2. Repeat for subsequent programming operations.
3. Full status register check can be done after each program or after a sequence of PROGRAM
operations.
4. Write 0xFF after the last operation to set read array state.
FULL STATUS CHECK Flowchart
Read status
register
SR3 =
1
VPP range
error
1
Program
error
1
Register locked;
program aborted
0
SR4 =
0
SR1 =
0
Program
successful
Table 47:
FULL STATUS CHECK Procedure
Bus Operation
Command
IDLE
None
IDLE
None
IDLE
None
Notes:
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Notes
Check SR3
1 = VPP range error
Check SR4
1 = Programming error
Check SR1
1 = Block locked; operation aborted
1. Only the CLEAR STATUS REGISTER command clears SR1, SR3, and SR4.
2. If an error is detected, clear the status register before attempting a program retry or other
error recovery.
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Supplemental Reference Information
Write State Machine
Figure 40:
Write State Machine — Next State Table
Command Input to Chip and resulting Chip Next State
Current Chip State (6)
Ready
Read
Array (2)
Word
Program
(3,4)
(FFH)
(10H/40H)
Ready
SM Ready
SM Ready
Bit Alterable
Word Write
Write to
Buffered
Program
(BP)
Bit Alterable
Write to
Buffer
(42H)
(E8H)
(EAH)
Program Setup
BP Setup
Program Setup
BP Setup
Lock/CR Setup
OTP
Word Program
Streaming
Mode Entry
(SM Entry)
Streaming
Mode Exit
(SM Exit)
BE Confirm,
Erase Setup P/E Resume, BP / Prg / Erase
(3,4)
Suspend
ULB,
Confirm (7)
(20H)
(D0H)
(B0H)
Read
Status
Clear
Status
Register (5)
Read
ID/Query
(70H)
(50H)
(90H, 98H)
Lock,
Unlock,
Lock-down,
CR setup (4)
(4AH)
(4FH)
SM Entry
Setup
SM Exit
Setup
Erase Setup
Ready
Lock/CR
Setup
SM Ready
SM Exit
Setup
Erase Setup
SM Ready
Lock/CR
Setup
Ready
(Unlock Block)
Ready (Lock Error [Botch])
Setup
Busy
Setup
(60H)
Ready (Lock Error [Botch])
OTP Busy
Word Program Busy
Word Pgm
Suspend
Word Program Busy
Busy
Word Program Busy
Word Pgm
Busy
Word Program Suspend
Suspend
Setup
BP Load 1
BP Load 1 (8)
BP Confirm if Data load complete; ELSE BP Load 2
BP Load 2 (8)
BP Confirm if Data load complete; ELSE BP Load 2
Word Program Suspend
BP
BP Confirm
Ready (Error [Botch])
BP Busy
BP Suspend
Setup
BP Busy
BP Suspend
Ready (Error [Botch])
BP Suspend
BP Busy
Erase Busy
Erase Busy
Busy
Ready (Error [Botch])
BP Busy
BP Busy
BP Suspend
Ready (Error [Botch])
Erase Busy
Erase Suspend
Erase
Suspend
Erase
Suspend
Word Program Setup in
Erase Suspend
BP Setup in Erase
Suspend
Erase
Suspend
Word Program Busy in Erase Suspend
Setup
Word Program
in Erase
Suspend
Busy
Suspend
Lock/CR
Setup in
Erase
Suspend
Erase Suspend
Erase Busy
Word Program
Suspend in
Erase Suspend
Word Program Busy in Erase Suspend
Word Program Suspend in Erase Suspend
Word Pgm
Busy in Erase
Suspend
Word Program Busy in Erase Suspend Busy
Word Program Suspend in Erase Suspend
Setup
BP Load 1 in Erase Suspend
BP Load 1 (8)
BP Confirm in Erase Suspend if Data load complete; ELSE BP Load 2
BP Load 2 (8)
BP Confirm in Erase Suspend if Data load complete; ELSE BP Load 2
BP in Erase
Suspend
BP Confirm
BP Busy
BP Suspend
Lock/CR Setup in Erase Suspend
SM Entry
Setup
Busy
SM Exit
Setup
Busy
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Erase Suspend (Error [Botch BP])
BP Busy in
Erase
Suspend
Ready (Error [Botch BP] in Erase Suspend)
BP Suspend in
Erase Suspend
BP Busy in Erase Suspend
BP Busy in Erase Suspend
BP Suspend in Erase Suspend
BP Busy in
Erase
Suspend
BP Suspend in Erase Suspend
Erase Suspend (Lock Error [Botch])
Erase
Suspend
(Unlock Blk)
Erase Suspend (Lock Error [Botch])
Ready (Error [Botch])
SM Entry Busy
SM Entry Busy
Ready (Error [Botch])
SM Ready
Ready (Error [Botch])
SM Exit Busy
Ready
70
SM Entry Busy
Ready (Error [Botch])
SM Exit Busy
SM Exit Busy
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Supplemental Reference Information
Command Input to Chip and resulting Chip Next State
OTP Setup
(4)
Lock
Block
Confirm (7)
(C0H)
(01H)
Lock-Down
Write
Block
Illegal Cmds+U48
Block
RCR/ECR
Address
(1)
Confirm (7) Confirm (7) (¹WA0) (9)
(2FH)
(03H,04H)
(XXXXH)
WSM
Operation
Completes
(all other codes)
Ready
OTP Setup
SM Ready
Ready
Ready
Ready (Lock
(Lock Down
Error [Botch]) (Lock Block)
Blk)
N/A
Ready
(Set CR)
Ready (Lock Error [Botch])
OTP Busy
Word Program Busy
Ready
N/A
Word Program Busy
Ready
Word Program Suspend
BP Load 1
BP Confirm if Data load complete; ELSE BP Load 2
BP Confirm if Data load complete; ELSE BP Load 2
Ready
BP Confirm if Data
load complete;
ELSE BP Load 2
Ready (Error [Botch])
Ready
(Error
[Botch])
(Proceed if
unlocked or
Lock error)
Ready (Error
[Botch])
N/A
BP Busy
BP suspend
Ready (Error [Botch])
Ready
Erase Busy
Ready
N/A
Erase Suspend
N/A
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Erase Suspend
Word Program Suspend in Erase Suspend
BP Load 1 in Erase Suspend
BP Confirm in Erase Suspend if Data load complete;
ELSE BP Load 2
Ready
BP Confirm in
Erase Suspend if
Data load
complete; ELSE
BP Load 2
BP Confirm in Erase Suspend if Data load complete;
ELSE BP Load 2
Ready
BP Confirm in
Erase Suspend if
Data load
complete; ELSE
BP Load 2
Ready (Error [Botch BP] in Erase Suspend)
Ready
(Error
[Botch])
(Proceed if
unlocked or
Lock error)
Ready (Error
[Botch BP] in
Erase Suspend)
Erase
Suspend
(Error
[Botch])
Erase
Suspend
(Lock Blk)
N/A
BP Busy in Erase Suspend
Erase Suspend
BP Suspend in Erase Suspend
N/A
Erase
Suspend
(Lock Down
Blk)
Erase
Suspend
(Set CR)
Erase Suspend (Lock Error
[Botch])
N/A
Ready (Error [Botch])
SM Entry Busy
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Ready
Ready (Error [Botch])
N/A
SM Exit Busy
Ready
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Supplemental Reference Information
Command Input to Chip and resulting Output Mux Next State
Current chip state
Read
Array (2)
Word
Program
Setup (3,4)
Bit Alterable
Word Write
Write to
Buffered
Program
(BP)
Bit Alterable
Write to
Buffer
Streaming
Mode Entry
(SM Entry)
Streaming
Mode Exit
(SM Exit)
(FFH)
(10H/40H)
(42H)
(E8H)
(EAH)
(4AH)
(4FH)
Erase Setup,
OTP Setup,
BP: Setup, Load 1, Load 2, Confirm,
Word Pgm Setup,
SM Entry Setup, SM Exit Setup
BE Confirm,
Erase Setup P/E Resume,
(3,4)
ULB Confirm
(7)
(20H)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock,
Unlock,
Lock-down,
CR setup (4)
(B0H)
(70H)
(50H)
(90H, 98H)
(60H)
(D0H)
Status Read
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status
Read
OTP Busy
Ready, SM Ready
Erase Suspend,
BP Suspend
BP Busy,
Word Program Busy,
Erase Busy,
BP Busy
BP Busy in Erase Suspend
Word Pgm Suspend,
Word Pgm Busy in Erase Suspend,
Pgm Suspend In Erase Suspend
BP Suspend in Erase Suspend
SM Entry Busy
SM Exit Busy
Read Array
Status Read
Output mux does not change.
Status Read Ready Array
Status Read
ID Read
Command Input to Chip and resulting Output Mux Next State
Current chip state
OTP Setup
(4)
Lock
Block
Confirm (7)
(C0H)
(01H)
Erase Setup,
OTP Setup,
BP: Setup, Load 1, Load 2, Confirm,
Word Pgm Setup,
SM Entry Setup, SM Exit Setup
Lock-Down
Write
Block
RCR/ECR
Confirm (7) Confirm (7)
(2FH)
(03H,04H)
Block
Address
(WA0)
Illegal Cmds (1)
(FFFFH)
(all other codes)
WSM
Operation
Completes
Status Read
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Status Read
Ready
Array
Status Read
OTP Busy
Ready, SM Ready
Erase Suspend,
BP Suspend
BP Busy,
Word Program Busy,
Erase Busy,
BP Busy
BP Busy in Erase Suspend
Word Pgm Suspend,
Word Pgm Busy in Erase Suspend,
Pgm Suspend In Erase Suspend
BP Suspend in Erase Suspend
SM Entry Busy
SM Exit Busy
Notes:
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Status Read
Output mux does not change.
Ready Array
Read Array
1. Illegal commands include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [erase]).
2. If a READ ARRAY is attempted while the device is busy writing or erasing, the result will be
invalid data. The ID and query data are located at different locations in the address map.
3. First and second cycles of two cycles WRITE commands must be given to the same device
address, or unexpected results will occur.
4. The second cycle of the following two cycle commands will be ignored by the user interface:
word program setup, erase setup, OTP setup, and lock/unlock/lock down/CR setup when
issued in an illegal condition. Illegal conditions are such as "pgm setup while busy", “erase
setup while busy", “Word program suspend”, etc. For example, the second cycle of an
ERASE command issued in PROGRAM SUSPEND will NOT resume the program operation.
5. The CLEAR STATUS COMMAND only clears the error bits in the status register if the device is
not in the following modes: 1. WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, modes); 2. Suspend states (Pgm Suspend, Pgm Suspend In Erase Suspend)
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Supplemental Reference Information
6. The current state is that of the device.
7. Confirm commands (LOCK BLOCK, UNLOCK BLOCK, LOCK DOWN BLOCK) perform the operation and then move to the ready state.
8. Buffered programming will botch when a different block address (as compared to address
given with E8 command) is written during the BP load1 and BP load2 states.
9. WA0 refers to the block address latched during the first WRITE cycle of the current operation.
Common Flash Interface
The P8P parallel PCM device borrows from the existing standards established for Flash
memory and supports the use of the CFI. The query is part of an overall specification for
multiple command set and control interface descriptions called CFI. This appendix
defines the data structure or database returned by the CFI QUERY command. System
software should parse this structure to gain critical information, such as block size,
density, x16, and electrical specifications. After this information has been obtained, the
software will know which command sets to use to enable PCM writes, block erases, and
otherwise control the PCM component.
Query Structure Output
The query database allows system software to obtain information for controlling the
PCM device. This section describes the device’s CFI-compliant interface that allows
access to query data.
Query data are presented on the lowest-order data outputs (DQ[7:0]) only. The numerical offset value is the address relative to the maximum bus width supported by the
device. On this family of devices, the query table device starting address is a 10h, which
is a word address for x16 devices.
For a word-wide (x16) device, the first two query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ[7:0])
and 00h in the high byte (DQ[15:8]).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal notation, so the “h” suffix has been dropped. In addition, because the upper byte of wordwide devices is always 00h, the leading 00 has been dropped from the table notation and
only the lower byte value is shown. Any x16 device outputs can be assumed to have 00h
on the upper byte in this mode.
Table 48:
Summary of Query Structure Output as a Function of Device and Model
Device
Hex Offset
Hex Code
ASCII Value
Device address
00010:
00011:
00012:
51
52
59
“Q”
“R”
“Y”
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Supplemental Reference Information
Table 49:
Example of Query Structure Output of x16 Devices
Word Addressing
Offset
Hex Code
AX–A0
Byte Addressing
Value
Offset
D15–D0
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
0051
0052
0059
P_IDLO
P_IDIH
PLO
PIH
A_IDLO
A_IDIH
Hex Code
AX–A0
Q
R
Y
PrVendor
ID#
PrVendor
TblAdr
AltVendor
ID#
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
Value
D15–D0
51
52
59
P_IDLO
P_IDLO
P_IDIH
–
–
–
Q
R
Y
PrVendor
ID#
ID#
–
–
–
Query Structure Overview
The QUERY command causes the PCM component to display the CFI query structure or
database. The structure subsections and address locations are summarized below.
Table 50:
Query Structure
Offset
00000h
00001h
(BA + 2)h2
00004–Fh
00010h
0001Bh
00027h
P3
Description1
Subsection Name
Block status register
Reserved
CFI query identification setting
System interface information
Device geometry definition
Primary Intel-specific extended query table
Notes:
Manufacturer code
Device code
Block-specific information
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing and voltage information
Flash device layout
Vendor-defined additional information specific to
the primary vendor algorithm
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of
offset address as a function of device bus width and mode.
2. BA = Block address beginning location (for example, 08000h is block 1s beginning location
when the block size is 32K-word).
3. Offset 15 defines “P,” which points to the primary Micron-specific extended query table.
CFI Query Identification String
The identification string provides verification that the component supports the CFI
specification. It also indicates the specification version and supported vendor-specified
command set(s).
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Supplemental Reference Information
Table 51:
Block Status Register
Offset
Length
(BA + 2)h
1
Table 52:
Description
Block lock status register
BSR 0: Block lock status
0 = Unlocked
1 = Locked
BSR 1: Block lock-down status
0 = Not locked down
1 = Locked down
BSR 4 EFA: Block lock status
0 = Unlocked
1 = Locked
BSR 5EFA: Block lock-down status
0 = Not locked down
1 = Locked down
BSR 2–3, 6–7: Reserved for future use
Value
BA + 2
BA + 2
–00 or –01
(bit 0): 0 or 1
BA + 2
(bit 1): 0 or 1
BA + 2
(bit 4): 0 or 1
BA + 2
(bit 5): 0 or 1
BA + 2
(bit 2–3, 6–7): 0
CFI Identification
Offset
Length
10h
3
Query-unique ASCII string QRY
13h
2
15h
2
17h
2
19h
2
Primary vendor command set and control
interface ID code; 16-bit ID code for vendorspecific algorithms
Extended query table primary algorithm
address
Alternate vendor command set and control
interface ID code; 0000h means no second
vendor-specified algorithm exists
Secondary algorithm extended query table
address; 0000h means none exists
Table 53:
Address
Description
Address
Hex Code
Value
10
11
12
13
14
–51
–52
–59
–01
–00
Q
R
Y
15
16
17
18
–0A
01
–00
–00
19
1A
–00
–00
Address
Hex Code
Value
1B
–27
2.7V
1C
–36
3.6V
1D
–09
0.9V
System Interface Information
Offset
Length
1Bh
1
1Ch
1
1Dh
1
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Description
VCC logic supply minimum PROGRAM/ERASE
voltage
bits 0–3 BCD 100mV
bits 4–7 BCD volts
VCC logic supply maximum PROGRAM/ERASE
voltage
bits 0–3 BCD 100mV
bits 4–7 BCD volts
VPP (programming) supply minimum
PROGRAM/ERASE voltage
bits 0–3 BCD 100mV
bits 4–7 HEX volts
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Supplemental Reference Information
Table 53:
System Interface Information (Continued)
Offset
Length
1Eh
1
1Fh
1
20h
1
21h
1
22h
1
23h
1
24h
1
25h
1
26h
1
Table 54:
Offset
Description
VPP (programming) supply maximum
PROGRAM/ERASE voltage
bits 0–3 BCD 100mV
bits 4–7 HEX volts
n such that typical single word program timeout = 2n µ-sec
n such that typical full buffer write time-out =
2n µ-sec
n such that typical block erase time-out = 2n msec
n such that typical full chip erase time-out = 2n
m-sec
n such that maximum word program time-out
= 2n times typical
n such that maximum buffer write time-out =
2n times typical
n such that maximum block erase time-out = 2n
times typical
n such that maximum chip erase time-out = 2n
times typical
Address
Hex Code
Value
1E
–36
3.6V
1F
–08
256µs
20
–09
512µs
21
–0A
1s
22
–00
NA
23
–01
512µs
24
–01
1024µs
25
–02
4s
26
–00
NA
Address
Hex Code
Value
Device Geometry Definition
Length
Description
n
27h
1
n such that device size = 2 in number of bytes
27
28h
2
28
29
2Ah
2
2Ch
1
2Dh
4
31h
4
Flash device interface code assignment: n such
that n + 1 specifies the bit field that represents
the Flash device width capabilities as described
in Table 55 on page 77
n such that maximum number of bytes in write
buffer = 2n
Number of erase block regions (x) within
device:
x = 0 means no erase blocking; the device
erases in bulk
x specifies the number of device regions with
one or more contiguous same-size erase blocks
Symmetrically blocked partitions have one
blocking region
Erase block region 1 information
bits 0-15 = y, y + 1 = number of identical-size
erase blocks
bits 16-31 = z, region erase block(s) size are z x
256 bytes
Erase block region 2 information
bits 0-15 = y, y + 1 = number of identical-size
erase blocks
bits 16-31 = z, region erase block(s) size are z x
256 bytes
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76
See Table 56 on
page 77
-01
x16
-00
2A
2B
2C
-06
64
-00
See Table 56 on
page 77
2D
2E
2F
30
See Table 56 on
page 77
31
32
33
34
See Table 56 on
page 77
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Supplemental Reference Information
Table 54:
Device Geometry Definition (Continued)
Offset
Length
35h
4
Table 55:
Description
Address
Hex Code
35
36
37
38
Reserved for future block erase block region
information
Value
See Table 56 on
page 77
Bit Field Definitions
Bit
7
-
6
-
5
-
4
-
3
x64
2
x32
1
x16
0
x8
11
-
10
-
9
-
8
-
Bit
15
-
Table 56:
14
-
13
-
12
-
Hex Code and Values for Device Geometry
128Mb
Address
-B
-T
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
-18
01
00
06
00
-02
-03
-00
-80
-00
-7E
-00
-00
-02
-00
-00
-00
-00
-18
01
00
06
00
-02
-7E
-00
-00
-02
-03
-00
-80
-00
-00
-00
-00
-00
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Extended Query Tables
Extended Query Tables
Table 57:
Offset
P = 10Ah
(P + 0)h
(P + 1)h
(P + 2)h
(P + 3)h
(P + 4)h
(P + 5)h
(P + 6)h
(P + 7)h
(P + 8)h
(P + 9)h
(P + A)h
(P + B)h
Primary Vendor-Specific Extended Query
Length Description (Optional Flash Features and Commands
3
Primary extended query table; unique ASCII string PRI
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1 = yes, 0 = no)
bits 10-31 are reserved; undefined bit are 0. If bit 31 is 1, then
another bit31 field of optional features follows at the end of the bit30 field
bit 0: Chip erase supported
bit 1: Suspend erase supported
bit 2: Suspend program supported
bit 3: Legacy lock/unlock supported
bit 4: Queued erase supported
bit 5: Instant individual block locking supported
bit 6: Protection bits supported
bit 7: Page mode read supported
bit 8: Synchronous read supported
bit 9: Simultaneous operations supported
bit 10: Extended Flash array blocks supported
bit 30: DFI link(s) to follow
bit 31: Another optional features field to follow
1
2
(P + C)h
1
(P + D)h
1
Table 58:
Offset
P = 10Ah
(P + E)h
Supported functions after suspend: read array, status, query
Other supported features include:
bits 1-7: Reserved; undefined bits are 0
bit 0: Program supported after erase suspend
Block status register mask
bits 2-15: Reserved; undefined bits are 0
bit 0: Block lock bit status register active
bit 1: Block lock-down bit status active
bit 4: EFA block lock bit status register active
bit 5: EFA block lock-down bit status active
VCC logic supply highest performance program/erase voltage
bits 0-3: BCD value in 100mV
bit 4-7: BCD value in volts
VPP optimum program/erase supply voltage
bits 0-3: BCD value in 100mV
bit 4-7: Hex value in volts
Hex
Address Code
10A
-50
10B
-52
10C
-49
10D
-31
10E
-34
10F
-E6
110
-00
111
-00
112
-00
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 0
bit 9 = 0
bit 10 = 0
bit 30 = 0
bit 31 = 0
113
-01
bit 0 = 1
Value
P
R
T
1
4
No
Yes
Yes
no
No
Yes
Yes
Yes
No
No
No
No
No
Yes
114
-03
115
-00
bit 0 = 1
bit 1 = 1
bit 4 = 0
bit 5 = 0
116
-33
Yes
Yes
No
No
3.3V
117
-33
3.3V
Hex
Address Code
Value
Protection Register Information
Length Description (Optional Flash Features and Commands
1
Number of protection register fields in JEDEC ID space
000h indicates that 256 protection fields are available
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118
-02
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Extended Query Tables
Table 58:
Offset
P = 10Ah
Protection Register Information (Continued)
Length Description (Optional Flash Features and Commands
(P + F)h
(P + 10)h
(P + 11)h
(P + 12)h
4
(P + 13)h
(P + 14)h
(P + 15)h
(P + 16)h
(P + 17)h
(P + 18)h
(P + 19)h
(P + 1A)h
(P + 1B)h
(P + 1C)h
10
Table 59:
Offset
P = 10Ah
Value
119
11A
11B
11C
-80
-00
-03
-03
80h
00h
8 byte
8 byte
11D
11E
11F
120
121
122
123
124
125
126
-89
-00
-00
-00
-00
-00
-00
-10
-00
-04
89h
00h
00h
00h
0
0
0
16
0
16
Read Information
Length Description (Optional Flash Features and Commands
(P + 1D)h
1
(P + 1E)h
1
Table 60:
Protection field 1: Protection Description
This field describes user-available one-time programmable (OTP)
protection register bytes. Some are preprogrammed with deviceunique serial numbers. Others are user-programmable. Bits 0-15
point to the protection register lock byte, the section’s first byte. The
following bytes are factory preprogrammed and userprogrammable.
bits 0–7: Lock/bytes JEDEC-plane physical low address
bits 8–15: Lock/bytes JEDEC-plane physical high address
bits 16–23: n such that 2n = factory preprogrammed bytes
bits 24–31 = n such that 2n = user-programmable bytes
Protection field 2: Protection Description
Bits 0-31 point to the protection register physical lock-word address
in the JEDEC-plane. The following bytes are factory- or userprogrammable
bits 32-39: = n ¬ n = factory programmed groups (low byte)
bits 44739: = n n = factory programmed groups (high byte)
bits 48-55: = n \ 2n = factory programmable bytes/group
bits 56-63: = n ¬ n = user-programmed groups (low byte)
bits 64-71: = n ¬ n = user-programmed groups (high byte)
bits 72-79: = n ¬ 2n = user-programmable bytes/group
Hex
Address Code
Page mode read capability
bits 0-7 = n such that 2n hex value represents the number of readpage bytes. See offset 28h for device word width to determine page
mode data output width. 00h indicates no read page buffer.
Number of synchronous mode read configuration fields that follow.
00h indicates no burst capability.
Hex
Address Code
Value
127
-04
16
byte
128
-00
0
Partition and Erase Block Region Information
Offset
P = 10Ah
Address
Bottom
Top
Description (Optional Flash Features and Commands
(P + 1F)h
(P + 1F)h
Number of device hardware-partition regions within the device.
x = 0: a single hardware partition device (no fields follow)
x specifies the number of device partition regions containing one
or more contiguous erase block regions.
(P + 20)h
(P + 21)h
(P + 22)h
(P + 23)h
(P + 20)h
(P + 21)h
(P + 22)h
(P + 23)h
Length
Bottom Top
1
129
129
Data size of this partition region information field (number of
addressable locations, including this field)
2
12A
12B
12A
12B
Number of identical partitions within the partition region
2
12C
12D
12C
12D
Partition Region 1 Information
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Extended Query Tables
Table 60:
Partition and Erase Block Region Information (Continued)
Offset
P = 10Ah
Address
Bottom
Top
(P + 24)h
(P + 24)h
(P + 25)h
(P + 25)h
(P + 26)h
(P + 26)h
(P + 27)h
(P + 27)h
(P + 28)h
(P + 28)h
(P + 2A)h
(P + 2B)h
(P + 2C)h
(P + 2D)h
(P + 2E)h
(P + 28)h
(P + 28)h
(P + 2A)h
(P + 2B)h
(P + 2C)h
(P + 2D)h
(P + 2E)h
(P + 2F)h
(P + 2F)h
(P + 30)h
(P + 31)h
(P + 32)h
(P + 33)h
(P + 34)h
(P + 35)h
(P + 30)h
(P + 31)h
(P + 32)h
(P + 33)h
(P + 34)h
(P + 35)h
(P + 36)h
(P + 37)h
(P + 38)h
(P + 39)h
(P + 3A)h
(P + 3B)h
(P + 36)h
(P + 37)h
(P + 38)h
(P + 39)h
(P + 3A)h
(P + 3B)h
PDF: 09005aef8447d46d/Source: 09005aef845b5c96
parallel_pcm_2.fm - Rev. K 7/12 EN
Description (Optional Flash Features and Commands
Number of program or erase operations allowed in a partition
bits 0–3: number of simultaneous PROGRAM operations
bits 4–7: number of simultaneous ERASE operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in program mode
bits 0–3: number of simultaneous PROGRAM operations
bits 4–7: number of simultaneous ERASE operations
Simultaneous program or erase operations allowed in other
partitions while a partition in this region is in erase mode
bits 0–3: number of simultaneous PROGRAM operations
bits 4–7: number of simultaneous ERASE operations
Types of erase block regions in the partition region
x = 0: no erase blocking; the partition region erases in bulk
x = 0: number of erase block regions with contiguous same-size
erase blocks
Symmetrically blocked partitions have one blocking region
Partition size = (type 1 blocks) × (type 1 block sizes) + (type 2
blocks) × (type 2 block sizes) + ... + (type n blocks) × (type n block
sizes)
Partition region 1, erase block type 1 information
bits 0–15 = y, y + 1 = number of identical-size erase blocks in a
partition
bits 16–31 = z, region erase block(s) size are z × 256 bytes
Partition 1 (erase block, type 1)
Block erase cycles × 1000
Partition 1 (erase block, type 1) bits per cell; internal EDAC
bits 0–3: bits per cell in erase region
bit 4: internal EDAC used (1 = yes, 0 = no)
bits 5–7: reserved for future use
Partition 1 (erase block, type 1) page mode and synchronous
mode capabilities defined in Table 10 on page 18
bit 0: page mode host reads permitted (1 = yes, 0 = no)
bit 1: synchronous host reads permitted (1 = yes, 0 = no)
bit 2: synchronous host writes permitted (1 = yes, 0 = no)
bits 3–7: reserved for future use
Partition 1 (erase block, type 1) programmed region information
bits 0–7 = x, 2^x = programming region aligned size (bytes)
bits 8–14: reserved; bit 15: legacy Flash operation (ignore 0:7)
bits 16–23 = y = control mode valid size in bytes
bits 24–31: reserved
bits 32–39 = z = control mode invalid size in bytes
bits 40–46: reserved; bit 47: legacy Flash operation (ignore 23:16
and 39:32)
Partition 1 (erase block, type 2) information
bits 0–15 = y, y + 1 = number of identical-sized blocks in a
partition
bits 16–31 = z, region erase block(s) size are z × 256 bytes
Partition 1 (erase block type 2)
Block erase cycles × 1000
80
Length
Bottom Top
1
12E
12E
1
12F
12F
1
130
130
1
131
131
4
1
132
133
134
135
136
137
138
132
133
134
135
136
137
138
1
139
139
6
13A
13B
13C
13D
13E
13F
13A
13B
13C
13D
13E
13F
4
140
141
142
143
144
145
140
141
142
143
144
145
2
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Extended Query Tables
Table 60:
Partition and Erase Block Region Information (Continued)
Offset
P = 10Ah
Address
Bottom
Top
(P + 3C)h
(P + 3C)h
(P + 3D)h
(P + 3D)h
(P + 3E)h
(P + 3F)h
(P + 40)h
(P + 41)h
(P + 42)h
(P + 43)h
(P + 3E)h
(P + 3F)h
(P + 40)h
(P + 41)h
(P + 42)h
(P + 43)h
Table 61:
Description (Optional Flash Features and Commands
Partition 1 (erase block type 2) bits per cell; internal EDAC
bits 0–3: bits per cell in erase region
bit 4: internal EDAC used (1 = yes, 0 = no)
bits 5–7: reserved for future use
Partition 1 (erase block, type 2) page mode and synchronous
mode capabilities defined in Table 10 on page 18
bit 0: page mode host reads permitted (1 = yes, 0 = no)
bit 1: synchronous host reads permitted (1 = yes, 0 = no)
bit 2: synchronous host writes permitted (1 = yes, 0 = no)
bits 3–7: reserved for future use
Partition 1 (erase block, type 2) programming region information
bits 0–7 = x, 2^x = programming region aligned size (bytes)
bits 8–14: reserved; bit 15: legacy Flash operation (ignore 0:7)
bits 16–23 = y = control mode valid size in bytes
bits 24–31: reserved
bits 32–39 = z = control mode invalid size in bytes
bits 40–46: reserved; bit 47: legacy Flash operation (ignore 23:16
and 39:32)
Length
Bottom Top
1
146
146
1
147
147
Hex Code and Values for Partition and Erase Block Regions
128Mb
Address
-B
-T
129
12A
12B
12C
12D
12E
12F
130
131
132
133
134
135
136
137
138
139
13A
13B
13C
13D
13E
13F
–01
–24
–00
–01
–00
–11
–00
–00
–02
–03
–00
–80
–00
–64
–00
–01
–01
–00
–80
–00
–00
–00
–80
–01
–24
–00
–01
–00
–11
–00
–00
–02
–7E
–00
–00
–02
–64
–00
–01
–01
–00
–80
–00
–00
–00
–80
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parallel_pcm_2.fm - Rev. K 7/12 EN
81
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
128Mb: P8P Parallel PCM
Extended Query Tables
Table 61:
Hex Code and Values for Partition and Erase Block Regions (Continued)
128Mb
Address
-B
-T
140
141
142
143
144
145
146
147
148
149
14A
14B
14C
14D
–7E
–00
–00
–02
–64
–00
–01
–01
–00
–80
–00
–00
–00
–80
–03
–00
–80
–00
–64
–00
–01
–01
–00
–80
–00
–00
–00
–80
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although
considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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parallel_pcm_2.fm - Rev. K 7/12 EN
82
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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