Numonyx™ StrataFlash® Embedded Memory
(J3-65nm)
256-Mbit
Datasheet
Product Features
Architecture
— Multi-Level Cell Technology: Highest
Density at Lowest Cost
— 256 symmetrically-sized blocks of 128
Kbytes
Performance
— 95 ns initial access time for Easy BGA
— 105 ns initial accsss time for TSOP
— 25 ns 16-word Asynchronous page-mode
reads
— 512-Word Buffer Programming at
1.46MByte/s (Typ)
Voltage and Power
— VCC (Core) = 2.7 V to 3.6 V
— VCCQ (I/O) = 2.7 V to 3.6 V
— Standby Current: 65 µA (Typ)
— Erase & Program Current: 35 mA (Typ)
— Page Read: 12 mA (Typ)
Quality and Reliability
— Operating temperature:
-40 °C to +85 °C
— 100K Minimum erase cycles per block
— 65 nm NumonyxTM ETOX™ X Process
technology
Security
— Enhanced security options for code
protection
— Absolute protection with VPEN = GND
— Individual block locking
— Block erase/program lockout during power
transition
— Password Access feature
— One-Time Programmable Register:
64 OTP bits, programmed with unique
information by Numonyx
64 OTP bits, available for customer
programming
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator (FDI)
— Common Flash Interface (CFI) Compatible
Packaging
— 56-Lead TSOP
— 64-Ball Easy BGA package
319942-02
December 2008
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Legal Lines and Disclaimers
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2008, Numonyx B.V., All Rights Reserved.
Datasheet
2
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
Contents
1.0
Functional Overview .................................................................................................. 5
1.1
Document purpose .............................................................................................. 5
1.2
Product overview................................................................................................. 5
1.3
Configuration & Memory Map ................................................................................ 7
1.4
Device ID ........................................................................................................... 8
2.0
Package Information ................................................................................................. 9
2.1
56-Lead TSOP Package, 256-Mbit .......................................................................... 9
2.2
Easy BGA Package, 256-Mbit .............................................................................. 11
3.0
Ballout..................................................................................................................... 12
3.1
Easy BGA Ballout, 256-Mbit ................................................................................ 12
3.2
56-Lead TSOP Package Pinout, 256-Mbit .............................................................. 13
4.0
Signal Descriptions .................................................................................................. 14
5.0
Bus Interface........................................................................................................... 15
5.1
Reads .............................................................................................................. 16
5.2
Writes.............................................................................................................. 16
5.3
Output Disable .................................................................................................. 16
5.4
Standby ........................................................................................................... 16
5.5
Reset............................................................................................................... 17
6.0
Command Set .......................................................................................................... 18
6.1
Device Command Codes ..................................................................................... 18
6.2
Device Command Bus Cycle................................................................................ 19
7.0
Read
7.1
7.2
7.3
7.4
7.5
8.0
Program operation .................................................................................................. 24
8.1
Single-Word/Byte Programming .......................................................................... 24
8.2
Buffered Programming ....................................................................................... 24
8.3
Suspend/Resume .............................................................................................. 25
9.0
Erase Operation....................................................................................................... 26
9.1
Block Erase ...................................................................................................... 26
9.2
Suspend/Resume .............................................................................................. 26
operation ........................................................................................................ 21
Read Array ....................................................................................................... 21
Asynchronous Page Mode Read ........................................................................... 21
Read Status Register ......................................................................................... 22
Read Device Information .................................................................................... 22
CFI Query ........................................................................................................ 22
10.0 Security ................................................................................................................... 28
10.1 Normal Block Locking......................................................................................... 28
10.2 Configurable Block Locking ................................................................................. 28
10.3 VPEN Protection ................................................................................................ 29
10.4 Password Access ............................................................................................... 29
11.0 Registers ................................................................................................................. 30
11.1 Status Register ................................................................................................. 30
11.2 Status Signal .................................................................................................... 31
11.3 OTP Protection Register...................................................................................... 32
12.0 Power and Reset Specifications ............................................................................... 35
12.1 Power-Up and Power-Down................................................................................. 35
December 2008
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Datasheet
3
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
12.2
12.3
Reset Specifications ...........................................................................................36
Power Supply Decoupling....................................................................................37
13.0 Maximum Ratings and Operating Conditions ............................................................38
13.1 Absolute Maximum Ratings .................................................................................38
13.2 Operating Conditions..........................................................................................38
14.0 Electrical characteristics ..........................................................................................39
14.1 DC Current Specifications ...................................................................................39
14.2 DC Voltage Specifications....................................................................................40
14.3 Capacitance .....................................................................................................40
15.0 AC characteristics ....................................................................................................41
15.1 AC Test Conditions.............................................................................................41
15.2 AC Read Specifications .......................................................................................43
15.3 AC Write Specification ........................................................................................46
16.0 Program and erase characteristics ...........................................................................48
16.1 Program & Erase Specifications............................................................................48
17.0 Ordering Information...............................................................................................49
A
Reference Information .............................................................................................50
A.1
Common Flash Interface .....................................................................................50
A.2
Query Structure Output ......................................................................................50
A.3
Flow Charts.......................................................................................................57
B
Terms, definitions, and acronyms ............................................................................62
B.1
Nomenclature....................................................................................................62
B.2
Acronyms .........................................................................................................62
B.3
Conventions......................................................................................................63
C
Revision History.......................................................................................................64
Datasheet
4
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
1.0
Functional Overview
The Numonyx™ StrataFlash® Embedded Memory (J3-65nm) provides improved
mainstream performance with enhanced security features, taking advantage of the
high quality and reliability of the NOR-based Numonyx 65 nm ETOX™ X process technology.
Offered in 32-Mbit up through 256-Mbit densities, the Numonyx™ Embedded Memory
(J3-65nm) device brings reliable, low-voltage capability (3 V read, program, and
erase) with high speed, low-power operation. The Numonyx™ StrataFlash® Embedded
Memory (J3-65nm) device is ideal for code and data applications where high density
and low cost are required, such as in networking, telecommunications, digital set top
boxes, audio recording, and digital imaging. Numonyx Flash Memory components also
deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Numonyx
Flash Memory devices.
1.1
Document purpose
This document contains information pertaining to the Numonyx™ StrataFlash®
Embedded Memory (J3-65nm) device features, operation, and specifications.
The Numonyx™ Embedded Memory (J3-65nm) device is offered in Single Bit Cell
technology for 32-, 64-, 128-Mbit densities. The Numonyx™ StrataFlash® Embedded
Memory (J3-65nm) device is offered in Multi-Level Cell technology for 256-Mbit density.
This document just covers 256-Mbit die information.
Unless otherwise indicated throughout the rest of this document, Numonyx™
StrataFlash® Embedded Memory (J3-65nm) is referred to as J3-65nm.
1.2
Product overview
The 256-Mbit J3-65nm is organized as 256 individual 128Kbyte symmetrical blocks.
A 128-bit Protection Register has multiple uses, including unique flash device
identification.
The J3-65nm device includes new security features that were not available on the
(previous) 0.25µm, 0.18µm, and 0.13µm versions of the J3 family. The new security
features can be implemented to protect critical code and data from unwanted
modification (program or erase). Usage can be defined to fit the specific needs of each
customer.
The J3-65nm optimized architecture and interface dramatically increases read
performance by supporting page-mode reads. This read mode is ideal for non-clock
memory systems.
The J3-65nm Common Flash Interface (CFI) permits software algorithms to be used for
entire families of devices. This allows device-independent, JEDEC ID-independent, and
forward- and backward-compatible software support for the specified flash device
families. Flash vendors can standardize their existing interfaces for long-term
compatibility.
The Scalable Command Set (SCS) allows a single, simple software driver in all host
systems to work with all SCS-compliant flash memory devices, independent of systemlevel packaging (e.g., memory card, SIMM, or direct-to-board placement). Additionally,
SCS provides the highest system/device data transfer rates and minimizes device and
system-level implementation costs.
December 2008
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Datasheet
5
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
A Command User Interface (CUI) serves as the interface between the system processor
and internal operation of the device. A valid command sequence written to the CUI
initiates device automation. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase, program, and lock-bit
configuration operations.
A block erase operation erases one of the device’s 128-Kbyte blocks typically within one
second, independent of other blocks. Each block can be independently erased 100,000
times. Block erase suspend mode allows system software to suspend block erase to
read or program data from any other block. Similarly, program suspend allows system
software to suspend programming (byte/word program and write-to-buffer operations)
to read data or execute code from any other block that is not being suspended.
Each device incorporates a Write Buffer of 512 words to allow optimum programming
performance. By using the Write Buffer data is programmed more efficiently in buffer
increments.
Memory Blocks are selectively and individually lockable in-system. Individual block
locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block erase
and program operations. Lock-bit configuration operations set and clear lock-bits (using
the Set Block Lock-Bit and Clear Block Lock-Bits commands).
The Status Register indicates when the WSM’s block erase, program, or lock-bit
configuration operation completes.
The STS (status) output gives an additional indicator of WSM activity by providing both
a hardware signal of status (versus software polling) and status masking (interrupt
masking for background block erase, for example). Status indication using STS
minimizes both CPU overhead and system power consumption. When configured in
level mode (default mode), it acts as a RY/BY# signal. When low, STS indicates that the
WSM is performing a block erase, program, or lock-bit configuration. STS-high indicates
that the WSM is ready for a new command, block erase is suspended (and
programming is inactive), program is suspended, or the device is in reset/power-down
mode. Additionally, the configuration command allows the STS signal to be configured
to pulse on completion of programming and/or block erases.
Three CE signals are used to enable and disable the device. A unique CE logic design (
see Table 6, “Chip Enable Truth Table for 256-Mb” on page 15) reduces decoder logic
typically required for multi-chip designs. External logic is not required when designing a
single chip, a dual chip, or a 4-chip miniature card or SIMM module.
The BYTE# signal allows either x8 or x16 read/writes to the device:
• BYTE#-low enables 8-bit mode; address A0 selects between the low byte and high
byte.
• BYTE#-high enables 16-bit operation; address A1 becomes the lowest order
address and address A0 is not used (don’t care).
When the device is disabled (see Table 6, “Chip Enable Truth Table for 256-Mb” on
page 15), with CEx at VIH and RP# at VIH, the standby mode is enabled. When RP# is
at VIL, a further power-down mode is enabled which minimizes power consumption and
provides write protection during reset. A reset time (tPHQV) is required from RP# going
high until data outputs are valid. Likewise, the device has a wake time (tPHWL) from
RP#-high until writes to the CUI are recognized. With RP# at VIL, the WSM is reset and
the Status Register is cleared.
Datasheet
6
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
1.3
Configuration & Memory Map
The J3-65nm device features a symmetrically-blocked architecture. The flash device
main array is divided as follows:
• 256-Mbit, organized into two-hundred-fifty-six 128-Kbyte blocks.
J3-65nm Memory Map
A 256 Mbit
A 256 Mbit
1FFFFFF
1FE0000
0FFFFFF
0FE0000
07FFFFF
07E0000
003 FFFF
0020000
001 FFFF
0000000
128-Kbyte Block
FFFFFF
255
7FFFFF
128-Kbyte Block
127
128-Kbyte Block
63
128-Kbyte Block
1
128-Kbyte Block
0
7F0000
3FFFFF
3F0000
01FFFF
Byte-Wide (x8) Mode
December 2008
319942-02
FF0000
010000
00FFFF
000000
64-Kword Block
255
64-Kword Block
127
64-Kword Block
63
64-Kword Block
1
64-Kword Block
0
256-Mbit
Figure 1:
Word Wide (x16) Mode
Datasheet
7
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
1.4
Table 1:
Device ID
Device Identifier Codes
Code
Device Code
Datasheet
8
256-Mbit
Address
Data
00001h
001Dh
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
2.0
Package Information
2.1
56-Lead TSOP Package, 256-Mbit
Figure 2:
56-Lead TSOP Package Mechanical
Z
See Notes 1 and 3
A2
See Note 2
Pin 1
e
See Detail B
E
Y
D1
A1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Notes:
1.
One dimple on package denotes Pin 1.
2.
If two dimples, then the larger dimple denotes Pin 1.
3.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Table 2:
56-Lead TSOP Dimension Table
Millimeters
Parameter
Inches
Symbol
Min
Nom
Max
Min
Nom
Package Height
A
Standoff
A1
0.050
Package Body Thickness
A2
0.965
0.995
1.025
0.038
0.039
0.040
Lead Width
b
0.100
0.150
0.200
0.004
0.006
0.008
Lead Thickness
1.200
Max
0.047
0.002
c
0.100
0.150
0.200
0.004
0.006
0.008
Package Body Length
D1
18.200
18.400
18.600
0.717
0.724
0.732
Package Body Width
E
13.800
14.000
14.200
0.543
0.551
0.559
Lead Pitch
e
December 2008
319942-02
0.500
0.0197
Datasheet
9
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
Table 2:
56-Lead TSOP Dimension Table
Millimeters
Parameter
Inches
Symbol
Min
Nom
Max
Min
Nom
Max
D
19.800
20.00
20.200
0.780
0.787
0.795
Lead Tip Length
L
0.500
0.600
0.700
0.020
0.024
0.028
Lead Count
N
Terminal Dimension
Lead Tip Angle
θ
Seating Plane Coplanarity
Y
Lead to Package Offset
Z
Datasheet
10
56
0°
3°
56
5°
0°
3°
0.100
0.150
0.250
0.350
5°
0.004
0.006
0.010
0.014
December 2008
319942-02
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
2.2
Figure 3:
Easy BGA Package, 256-Mbit
Easy BGA Mechanical Specifications
Ball A1
Corner
Ball A1
Corner
D
1
2
3
4
S1
5
6
7
8
8
A
A
B
B
C
C
D
7
6
5
4
3
2
1
S2
D
E
E
E
F
F
G
G
H
H
e
b
Bottom View - Ball Side Up
Top View - Plastic Backside
Complete Ink Mark Not Shown
A1
A2
A
Seating
Y
Plane
Table 3:
Easy BGA Package Dimensions Table
Millimeters
Parameter
Min
Package Height (256 Mbit)
Inches
Symbol
Nom
A
Ball Height
A1
Package Body Thickness (256 Mbit)
A2
Max
Min
Nom
1.200
0.250
Max
0.0472
0.0098
0.780
0.0307
Ball (Lead) Width
b
0.330
0.430
0.530
0.0130
0.0169
0.0209
Package Body Width
D
9.900
10.000
10.100
0.3898
0.3937
0.3976
Package Body Length
E
12.900
13.000
13.100
0.5079
0.5118
0.5157
Pitch
e
1.000
Ball (Lead) Count
N
64
Seating Plane Coplanarity
Y
0.0394
64
0.100
0.0039
Corner to Ball A1 Distance Along D (256 Mb)
S1
1.400
1.500
1.600
0.0551
0.0591
0.0630
Corner to Ball A1 Distance Along E (256 Mb)
S2
2.900
3.000
3.100
0.1142
0.1181
0.1220
December 2008
319942-02
Datasheet
11
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
3.0
Ballout
J3-65nm is available in two package types. All densities of the J3-65nm devices are
supported on both 64-ball Easy BGA and 56-lead Thin Small Outline Package (TSOP)
packages. The figures below show the ballouts.
3.1
Easy BGA Ballout
Figure 4:
Easy BGA Ballout
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
A1
A6
A8
VPEN
A13
VCC
A18
A22
A22
A18
VCC
A13
VPEN
A8
A6
A1
A2
VSS
A9
CE0
A14
RFU
A19
CE1
CE1
A19
RFU
A14
CE0
A9
VSS
A2
A3
A7
A10
A12
A15
RFU
A20
A21
A21
A20
RFU
A15
A12
A10
A7
A3
A4
A5
A11
RP#
RFU
RFU
A16
A17
A17
A16
RFU
RFU
RP#
A11
A5
A4
DQ8
DQ1
DQ9
DQ3
DQ4
RFU
DQ15
STS
STS
DQ15
RFU
DQ4
DQ3
DQ9
DQ1
DQ8
BYTE# DQ0
DQ10
DQ11
DQ12
RFU
RFU
OE#
OE#
RFU
RFU
DQ12
DQ11
DQ10
DQ0
BYTE#
A
A
B
B
C
C
D
D
E
E
F
F
G
G
A23
A0
DQ2
VCCQ
DQ5
DQ6
DQ14
WE#
WE#
DQ14
DQ6
DQ5
VCCQ
DQ2
A0
A23
CE2
RFU
VCC
VSS
DQ13
VSS
DQ7
A24
A24
DQ7
VSS
DQ13
VSS
VCC
RFU
CE2
H
H
Easy BGA
Top View – Ball Side Down
Datasheet
12
Easy BGA
Bottom View – Ball Side Up
December 2008
319942-02
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
3.2
Figure 5:
56-Lead TSOP Package Pinout, 256-Mbit
56-Lead TSOP Package Pinout (256 Mbit)
A22
CE1
A21
A20
A19
A18
A17
A16
VCC(1)
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
GND
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56-Lead TSOP
Standard Pinout
14 mm x 20 mm
Top View
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
A24
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
GND
DQ13
DQ5
DQ12
DQ4
VCCQ
GND
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE
A23
CE2
Notes:
1.
No internal connection on Pin 9; it may be driven or floated. For legacy designs, pin can be tied to Vcc.
December 2008
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Datasheet
13
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
4.0
Signal Descriptions
Table 4 lists the active signals used on J3-65nm and provides a description of each.
Table 4:
TSOP & Easy BGA Signal Descriptions
Symbol
Type
Name and Function
A0
Input
BYTE-SELECT ADDRESS: Selects between high and low byte when the device is in x8 mode. This
address is latched during a x8 program cycle. Not used in x16 mode (i.e., the A0 input buffer is
turned off when BYTE# is high).
A[MAX:1]
Input
ADDRESS INPUTS: Inputs for addresses during read and program operations. Addresses are
internally latched during a program cycle:
256-Mbit — A[24:1]
DQ[7:0]
Input/
Output
LOW-BYTE DATA BUS: Inputs data during buffer writes and programming, and inputs commands
during CUI writes. Outputs array, CFI, identifier, or status data in the appropriate read mode. Data
is internally latched during write operations.
DQ[15:8]
Input/
Output
HIGH-BYTE DATA BUS: Inputs data during x16 buffer writes and programming operations.
Outputs array, CFI, or identifier data in the appropriate read mode; not used for Status Register
reads. Data is internally latched during write operations in x16 mode. DQ[15:8] float in x8 mode
CE[2:0]
Input
CHIP ENABLE: Activate the 256-Mbit devices’ control logic, input buffers, decoders, and sense
amplifiers. When the device is de-selected (see Table 6, “Chip Enable Truth Table for
256-Mb” on page 15), power reduces to standby levels.
All timing specifications are the same for these three signals. Device selection occurs with the
falling edge of CE0, CE1, or CE2 that enables the device. Device deselection occurs with the rising
edge of CE0, CE1, or CE2 that disables the device (see Table 6, “Chip Enable Truth Table
for 256-Mb” on page 15).
RP#
Input
RESET: RP#-low resets internal automation and puts the device in power-down mode. RP#-high
enables normal operation. Exit from reset sets the device to read array mode. When driven low,
RP# inhibits write operations which provides data protection during power transitions.
OE#
Input
OUTPUT ENABLE: Activates the device’s outputs through the data buffers during a read cycle.
OE# is active low.
WE#
Input
WRITE ENABLE: Controls writes to the CUI, the Write Buffer, and array blocks. WE# is active low.
Addresses and data are latched on the rising edge of WE#.
STS
Open Drain
Output
STATUS: Indicates the status of the internal state machine. When configured in level mode
(default), it acts as a RY/BY# signal. When configured in one of its pulse modes, it can pulse to
indicate program and/or erase completion. For alternate configurations of the Status signal, see the
Configurations command and Section 11.2, “Status Signal” on page 31. STS is to be
tied to VCCQ with a pull-up resistor.
BYTE#
Input
BYTE ENABLE: BYTE#-low places the device in x8 mode; data is input or output on DQ[7:0], while
DQ[15:8] is placed in High-Z. Address A0 selects between the high and low byte. BYTE#-high
places the device in x16 mode, and turns off the A0 input buffer. Address A1 becomes the lowestorder address bit.
VPEN
Input
ERASE / PROGRAM / BLOCK LOCK ENABLE: For erasing array blocks, programming data, or
configuring lock-bits.
With VPEN ≤ VPENLK, memory contents cannot be altered.
VCC
Power
CORE Power Supply: Core (logic) source voltage. Writes to the flash array are inhibited when VCC
≤ VLKO.
Caution: Device operation at invalid Vcc voltages should not be attempted.
VCCQ
Power
I/O Power Supply: Power supply for Input/Output buffers.This ball can be tied directly to VCC.
GND/VSS
Supply
NC
—
No Connect: Lead is not internally connected; it may be driven or floated.
RFU
—
Reserved for Future Use: Balls designated as RFU are reserved by Numonyx for future device
functionality and enhancement.
Datasheet
14
GROUND: Ground reference for device logic voltages. Connect to system ground.
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
5.0
Bus Interface
This section provides an overview of Bus operations. There are three operations flash
memory: Read, Program (Write), and Erase.
CE[2:0]-enable, OE#-low, WE#-high and RP#-high enable device read operations.
Addresses are always assumed to be valid. OE#-low activates the outputs and gates
selected data onto the I/O bus. WE#-low enables device write operations. Table 5
summarizes the necessary states of each control signal for different modes of
operations.
Table 5:
Bus Operations
Mode
RP#
CEx(1)
OE#(2)
WE#(2)
DQ15:0(3)
STS
(Default
Mode)
VPEN
Notes
Reads: Async., Status, Query and
Identifier
VIH
Enabled
VIL
VIH
DOUT
High-Z
X
4,6
Output Disable
VIH
VIH
Enabled
VIH
High-Z
High-Z
X
Command Writes
VIH
Enabled
VIH
VIL
DIN
High Z
X
6,7
8,5
(8)
Array Writes
VIH
Enabled
VIH
VIL
DIN
VIL
VPENH
Standby
VIH
Disabled
X
X
High Z
High Z
X
Reset/Power-down
VIL
X
X
X
High Z
High Z
X
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
See Table 6 for valid CEx Configurations.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.
Refer to DC characteristics. When VPEN ≤ VPENLK, memory contents can be read but not altered.
X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH.
In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is VOH (pulled up by an external pull up resistance ≈10k) when the WSM is not busy, in block erase suspend
mode (with programming inactive), program suspend mode, or reset power-down mode.
See Table 7 for valid DIN (user commands) during a Write operation
Array writes are either program or erase operations.
CE0, CE1 and CE2 control device activation. With the proper input (see Figure 6, “Chip
Enable Truth Table for 256-Mb) the device gets selected, which in turn activates its
internal circuits. WE# and OE# determine the direction of the data buffers (input or
output).
Table 6:
Chip Enable Truth Table for 256-Mb
Note:
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319942-02
CE2
CE1
CE0
DEVICE
VIL
VIL
VIL
Enabled
VIL
VIL
VIH
Disabled
VIL
VIH
VIL
Disabled
VIL
VIH
VIH
Disabled
VIH
VIL
VIL
Enabled
VIH
VIL
VIH
Enabled
VIH
VIH
VIL
Enabled
VIH
VIH
VIH
Disabled
For single-chip applications, CE2 and CE1 can be connected to GND.
Datasheet
15
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
5.1
Reads
Reading from flash memory outputs stored information to the processor or chipset, and
does not change any contents. Reading can be performed an unlimited number of
times. Besides array data, other types of data such as device information or device
status are available from the flash.
To perform a bus read operation, CEx (refer to Table 6 on page 15) and OE# must be
asserted. CEx is the device-select control; when active, it enables the flash memory
device. OE# is the data-output control; when active, the addressed flash memory data
is driven onto the I/O bus. For all read states, WE# and RP# must be de-asserted. See
Section 7.0, “Read operation” on page 21.
5.2
Writes
Writing or Programming to the device is where the host writes information or data into
the flash device for non-volatile storage. When the flash device is programmed, ‘ones’
are changed to ‘zeros’. ‘Zeros’ cannot be programmed back to ‘ones’. To do so, an erase
operation must be performed. Writing commands to the Command User Interface (CUI)
enables various modes of operation, including the following:
• Reading of array data
• Common Flash Interface (CFI) data
• Identifier codes, inspection, and clearing of the Status Register
• Block Erasure, Program, and Lock-bit Configuration (when VPEN = VPENH)
Erasing is performed on a block basis – all flash cells within a block are erased together.
Any information or data previously stored in the block will be lost. Erasing is typically
done prior to programming. The Block Erase command requires appropriate command
data and an address within the block to be erased. The Byte/Word Program command
requires the command and address of the location to be written. Set Block Lock-Bit
commands require the command and block within the device to be locked. The Clear
Block Lock-Bits command requires the command and address within the device to be
cleared.
The CUI does not occupy an addressable memory location. It is written when the device
is enabled and WE# is active. The address and data needed to execute a command are
latched on the rising edge of WE# or the first edge of CE0, CE1, or CE2 that disables
the device (see Table 6 on page 15). Standard microprocessor write timings are used.
5.3
Output Disable
With CEx asserted, and OE# at a logic-high level (VIH), the device outputs are disabled.
Output signals D[15:0] are placed in a high-impedance state.
5.4
Standby
CE0, CE1, and CE2 can disable the device (see Table 6 on page 15) and place it in
standby mode. This manipulation of CEx substantially reduces device power
consumption. D[15:0] outputs are placed in a high-impedance state independent of
OE#. If deselected during block erase, program, or lock-bit configuration, the WSM
continues functioning, and consuming active power until the operation completes.
Datasheet
16
December 2008
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Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
5.5
Reset
RP# at VIL initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a highimpedance state, and turns off numerous internal circuits. RP# must be held low for a
minimum of tPLPH. Time tPHQV is required after return from reset mode until initial
memory access outputs are valid. After this wake-up interval, normal operation is
restored. The CUI is reset to read array mode and Status Register is set to 0080h.
During Block Erase, Program, or Lock-Bit Configuration modes, RP#-low will abort the
operation. In default mode, STS transitions low and remains low for a maximum time
of tPLPH + tPHRH until the reset operation is complete. Memory contents being altered
are no longer valid; the data may be partially corrupted after a program or partially
altered after an erase or lock-bit configuration. Time tPHWL is required after RP# goes to
logic-high (VIH) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When
the system comes out of reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed during Block Erase, Program,
or Lock-Bit Configuration modes. If a CPU reset occurs with no flash memory reset,
proper initialization may not occur because the flash memory may be providing status
information instead of array data. Numonyx Flash memories allow proper initialization
following a system reset through the use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that resets the system CPU.
December 2008
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Datasheet
17
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
6.0
Command Set
6.1
Device Command Codes
The system Central Processing Unit provides control of all in-system read, write, and
erase operations of the device via the system bus. The on-chip WSM manages all blockerase and program algorithms.
Device commands are written to the CUI to control all flash memory device operations.
The CUI does not occupy an addressable memory location; it is the mechanism through
which the flash device is controlled. Table 7 shows valid device command codes and
descriptions.
Table 7:
Program
Read
Mode
Command Codes and Definitions (Sheet 1 of 2)
Code
Device Mode
0xFF
Read Array
Places the device in Read Array mode. Array data is output on DQ[15:0].
0x70
Read Status Register
Places the device in Read Status Register mode. The device enters this mode after a
program or erase command is issued. SR data is output on DQ[7:0].
0x90
Read Device ID
or Configuration
Register
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status, or OTP
register data on DQ[15:0].
0x98
Read Query
Places the device in Read Query mode. Subsequent reads output Common Flash
Interface information on DQ[7:0].
0x50
Clear Status Register
The WSM can only set SR error bits. The Clear Status Register command is used to
clear the SR error bits.
0x40
Word/Byte Program
Setup
First cycle of a 2-cycle programming command, prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the WSM
executes the programming algorithm at the addressed location. During program
operations, the device responds only to Read Status Register and Program Suspend
commands. CEX or OE# must be toggled to update the Status Register in
asynchronous read. CEX must be toggled to update the SR Data for synchronous
Non-array reads. The Read Array command must be issued to read array data after
programming has finished.
0xE8
Buffered Program
This command loads a variable number of words up to the buffer size of 512 words
onto the program buffer in x16 mode. (1)
0xD0
Program Confirm
The confirm command is Issued after the data streaming for writing into the buffer
is done. This instructs the WSM to perform the Buffered Program algorithm, writing
the data from the buffer to the flash memory array.
Block Erase Setup
First cycle of a 2-cycle command; prepares the CUI for a block-erase operation. The
WSM performs the erase algorithm on the block addressed by the Erase Confirm
command. If the next command is not the Erase Confirm (0xD0) command, the CUI
sets Status Register bits SR [5,4], and places the device in Read Status Register
mode.
0xD0
Block Erase Confirm
If the first command was Block Erase Setup (0x20), the CUI latches the address and
data, and the WSM erases the addressed block. During block-erase operations, the
device responds only to Read Status Register and Erase Suspend commands. CEX or
OE# must be toggled to update the Status Register in asynchronous read. CEX must
be toggled to update the SR Data for synchronous Non-array reads.
0xB0
Program or Erase
Suspend
This command issued to any device address initiates a suspend of the currentlyexecuting program or block erase operation. The Status Register indicates
successful suspend operation by setting either SR.2 (program suspended) or SR 6
(erase suspended), along with SR.7 (ready). The WSM remains in the suspend mode
regardless of control signal states (except for RPRP# asserted).
0xD0
Suspend Resume
This command issued to any device address resumes the suspended program or
block-erase operation.
Suspend
Erase
0x20
Datasheet
18
Description
December 2008
319942-02
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
Table 7:
Protection
Mode
Command Codes and Definitions (Sheet 2 of 2)
Code
Device Mode
Description
0x60
Block lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock configuration
changes. If the next command is not Block Lock (0x01), Block Unlock (0xD0), the
CUI sets SR.5 and SR.4, indicating a command sequence error.
0x01
Block lock
If the previous command was Block Lock Setup (0x60), the addressed block is
locked.
0xD0
Unlock Block
If the previous command was Block Lock Setup (0x60), on issuing this command, all
of the Block lock bits that are set are cleared in parallel.
0xC0
Protection program
setup
First cycle of a 2-cycle command; prepares the device for a OTP register or Lock
Register program operation. The second cycle latches the register address and data,
and starts the programming algorithm to program data the OTP array.
Extended Function
Interface (EFI)
0xEB
This command is used in security features. first cycle of a multiple-cycle command
second cycle is a Sub-Op-Code, the data written on third cycle is one less than the
word count; the allowable value on this cycle are 0 through 511. The subsequent
cycles load data words into the program buffer at a specified address until word
count is achieved.
For additional information and collateral request, please contact your filed.
STS Configuration
B8h
Configuration Set-Up
Configures the STS pin to different states. The default operation of the STS pin is
the level mode, just like RY/BY# which indicates if the Write State Machine is Busy
or Available. Using this command the STS pin can be configured to generate an
Erase/Program interrupt pulse once the operation is done.
Configures the STS pin in level mode. Makes the STS pin function like a RY/BY#
pin.
00h
01h
Configuration Code
02h
Configures the STS pin to generate a pulse once an erase operation is completed.
The STS pin is configured to generate a pulse once a program operation completes.
The STS pin is configured to generate a pulse when either a program or erase
operation completes.
03h
6.2
Device Command Bus Cycle
Device operations are initiated by writing specific device commands to the CUI. See
Table 8, “Command Bus Cycles” on page 19. Several commands are used to modify
array data including Word Program and Block Erase commands. Writing either
command to the CUI initiates a sequence of internally-timed functions that culminate in
the completion of the requested task. However, the operation can be aborted by either
asserting RP# or by issuing an appropriate suspend command.
Table 8:
Command Bus Cycles (Sheet 1 of 2)
Program
Read
Mode
Command
Bus
Cycles
First Bus Cycle
Addr(1)
Data(2)
Second Bus Cycle
Addr(1)
Data(2)
Last Bus Cycle
Addr(1)
Data(2)
Read Array
1
DnA
0xFF
---
---
---
---
Read Status Register
2
DnA
0x70
DnA
SRD
---
---
Read Device Identifier
≥2
DnA
0x90
DBA + IA
ID
---
---
Read CFI
≥2
DnA
0x98
DBA + CFI-A
CFI-D
---
---
Clear Status Register
1
DnA
0x50
---
---
---
---
Word Program
2
WA
0x40
WA
WD
---
---
>2
WA
0xE8
WA
N-1
WA
0xD0
Buffered Program(3)
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Datasheet
19
Numonyx™ StrataFlash® Embedded Memory (J3-65nm)
Table 8:
Command Bus Cycles (Sheet 2 of 2)
Protection
Suspend Erase
Mode
Bus
Cycles
Command
First Bus Cycle
Second Bus Cycle
Last Bus Cycle
Addr(1)
Data(2)
Addr(1)
Data(2)
Addr(1)
Data(2)
Block Erase
2
BA
0x20
BA
0xD0
---
---
Program/Erase Suspend
1
DnA
0xB0
---
---
---
---
Program/Erase Resume
1
DnA
0xD0
---
---
---
---
Lock Block
2
BA
0x60
BA
0x01
---
---
Unlock Block
2
BA
0x60
BA
0xD0
---
---
Program OTP register
2
OTP-RA
0xC0
OTP-RA
OTP-D
---
---
Program Lock Register
2
LRA
0xC0
LRA
LRD
---
---
STS Configuration
2
BA
0xB8
BA
Register Data
---
---
>2
WA
0xEB
WA
Sub-Op code
WA
0xD0
Extended Flash Interface
(4)
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = OTP register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[15:0].
2.
ID = Identifier data.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = OTP register data.
LRD = Lock Register data.
3.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into
the write buffer. This is followed by up to 512 words of data.Then the confirm command (0xD0) is
issued, triggering the array programming operation.
4.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1=
