3-Volt Advanced Boot Block Flash
Memory
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Datasheet
Product Features
• Flexible SmartVoltage Technology
— 2.7 V–3.6 V Read/Program/Erase
— 12 V VPP Fast Production Programming
• 1.65 V–2.5 V or 2.7 V–3.6 V I/O Option
— Reduces Overall System Power
• High Performance
— 2.7 V–3.6 V: 70 ns Max Access Time
• Optimized Block Sizes
— Eight 8-KB Blocks for Data,Top or
Bottom Locations
— Up to One Hundred Twenty-Seven 64KB Blocks for Code
• Block Locking
— VCC-Level Control through WP#
• Low Power Consumption
— 9 mA Typical Read Current
• Absolute Hardware-Protection
— VPP = GND Option
— VCC Lockout Voltage
• Extended Temperature Operation
— –40 °C to +85 °C
• Automated Program and Block Erase
— Status Registers
• Intel® Flash Data Integrator Software
— Flash Memory Manager
— System Interrupt Manager
— Supports Parameter Storage, Streaming
Data (e.g., Voice)
• Extended Cycling Capability
— Minimum 100,000 Block Erase Cycles
Guaranteed
• Automatic Power Savings Feature
— Typical ICCS after Bus Inactivity
• Standard Surface Mount Packaging
— 48-Ball CSP Packages
— 40- and 48-Lead TSOP Packages
• Density and Footprint Upgradeable for
common package
— 8-, 16-, 32- and 64-Mbit Densities
• ETOX™ VIII (0.13 µm) Flash
Technology
— 16 and 32-Mbit Densities
• ETOX™ VII (0.18 µm) Flash Technology
— 16-, 32- and 64-Mbit Densities
• ETOX ™ VI (0.25µm) Flash Technology
— 8-, 16-, and 32-Mbit Densities
• The x8 option not recommended for new
designs
The Intel® 3-Volt Advanced Boot Block flash memory, manufactured on Intel’s latest 0.13 µm
and 0.18 µm technologies, represent a feature-rich solution at overall lower system cost. The 3Volt Advanced Boot Block Flash Memory products in x16 will be available in 48-lead TSOP and
48-ball CSP packages. The x8 option of this product family will be available only in 40-lead
TSOP and 48-ball µBGA* packages. Additional information on this product family can be
obtained by accessing Intel’s website at: http://www.intel.com/design/flash.
Notice: This specification is subject to change without notice. Verify with your local Intel sales
office that you have the latest data sheet before finalizing a design.
Order Number: 290580-016
April 2002
Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800548-4725 or by visiting Intel's website at http://developer.intel.com/design/flash.
Copyright © Intel Corporation 1999– 2002.
*Other names and brands may be claimed as the property of others.
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Contents
1.0
Introduction ..................................................................................................................1
1.1
2.0
Product Description ..................................................................................................3
2.1
2.2
3.0
Package Pinouts ...................................................................................................3
Block Organization ..............................................................................................10
2.2.1 Parameter Blocks ...................................................................................10
2.2.2 Main Blocks ............................................................................................10
Principles of Operation ..........................................................................................10
3.1
3.2
3.3
3.4
3.5
3.6
3.7
4.0
Product Overview ..................................................................................................2
Bus Operation .....................................................................................................10
3.1.1 Read .......................................................................................................11
3.1.2 Output Disable........................................................................................11
3.1.3 Standby ..................................................................................................11
3.1.4 Deep Power-Down / Reset.....................................................................11
3.1.5 Write .......................................................................................................12
Modes of Operation.............................................................................................12
3.2.1 Read Array .............................................................................................12
3.2.2 Read Identifier ........................................................................................14
3.2.3 Read Status Register .............................................................................14
3.2.3.1 Clearing the Status Register .....................................................14
3.2.4 Program Mode........................................................................................15
3.2.4.1 Suspending and Resuming Program ........................................15
3.2.5 Erase Mode ............................................................................................15
3.2.5.1 Suspending and Resuming Erase .............................................16
Block Locking ......................................................................................................17
3.3.1 WP# = VIL for Block Locking ..................................................................17
3.3.2 WP# = VIH for Block Unlocking ..............................................................18
VPP Program and Erase Voltages .......................................................................18
3.4.1 VPP = VIL for Complete Protection .........................................................18
Power Consumption ............................................................................................18
3.5.1 Active Power ..........................................................................................19
3.5.2 Automatic Power Savings (APS) ............................................................19
3.5.3 Standby Power .......................................................................................19
3.5.4 Deep Power-Down Mode .......................................................................19
Power and Reset Considerations........................................................................19
3.6.1 Power-Up/Down Characteristics ............................................................19
3.6.2 RP# Connected to System Reset...........................................................20
3.6.3 VCC, VPP and RP# Transitions ...............................................................20
Power Supply Decoupling ...................................................................................20
Electrical Specifications........................................................................................21
4.1
4.2
4.3
4.4
4.5
Absolute Maximum Ratings.................................................................................21
Operating Conditions...........................................................................................22
Capacitance ........................................................................................................22
DC Characteristics ..............................................................................................23
AC Characteristics —Read Operations...............................................................27
iii
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.6
4.7
AC Characteristics —Write Operations ............................................................... 32
Program and Erase Timings ............................................................................... 36
5.0
Reset Operations ..................................................................................................... 38
6.0
Ordering Information .............................................................................................. 39
7.0
Additional Information ........................................................................................... 41
Appendix A
Write State Machine Current/Next States ................................................. 42
Appendix B
Architecture Block Diagram ........................................................................... 43
Appendix C
Word-Wide Memory Map Diagrams............................................................. 44
Appendix D
Byte-Wide Memory Map Diagrams .............................................................. 50
Appendix E
Program and Erase Flowcharts .................................................................... 53
iv
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Revision History
Number
Description
-001
Original version
-002
Section 3.4, VPP Program and Erase Voltages, added
Updated Figure 9: Automated Block Erase Flowchart
Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table)
Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes)
IPPR maximum specification change from ±25 µA to ±50 µA
Program and Erase Suspend Latency specification change
Updated Appendix A: Ordering Information (included 8 M and 4 M information)
Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes)
Minor wording changes
-003
Combined byte-wide specification (previously 290605) with this document
Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V)
Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4)
Improved several DC characteristics (Section 4.4)
Improved several AC characteristics (Sections 4.5 and 4.6)
Combined 2.7 V and 1.8 V DC characteristics (Section 4.4)
Added 5 V VPP read specification (Section 3.4)
Removed 120 ns and 150 ns speed offerings
Moved Ordering Information from Appendix to Section 6.0; updated information
Moved Additional Information from Appendix to Section 7.0
Updated figure Appendix B, Access Time vs. Capacitive Load
Updated figure Appendix C, Architecture Block Diagram
Moved Program and Erase Flowcharts to Appendix E
Updated Program Flowchart
Updated Program Suspend/Resume Flowchart
Minor text edits throughout
-004
Added 32-Mbit density
Added 98H as a reserved command (Table 4)
A1–A20 = 0 when in read identifier mode (Section 3.2.2)
Status register clarification for SR3 (Table 7)
VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1)
Combined IPPW and ICCW into one specification (Section 4.4)
Combined IPPE and ICCE into one specification (Section 4.4)
Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7)
Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7)
Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 µs typical and 20 µs maximum
(Section 4.7)
Ordering Information updated (Section 6.0)
Write State Machine Current/Next States Table updated (Appendix A)
Program Suspend/Resume Flowchart updated (Appendix F)
Erase Suspend/Resume Flowchart updated (Appendix F)
Text clarifications throughout
-005
µBGA package diagrams corrected (Figures 3 and 4)
IPPD test conditions corrected (Section 4.4)
32-Mbit ordering information corrected (Section 6)
µBGA package top side mark information added (Section 6)
-006
VIH and VILSpecification change (Section 4.4)
ICCS test conditions clarification (Section 4.4)
Added Command Sequence Error Note (Table 7)
Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash
Memory Family.
Added device ID information for 4-Mbit x8 device
Removed 32-Mbit x8 to reflect product offerings
Minor text changes
-007
Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions
Corrected typographical error fixed in Ordering Information
v
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Number
Description
-008
4-Mbit packaging and addressing information corrected throughout document
-009
Corrected 4-Mbit memory addressing tables in Appendices D and E
-010
Max ICCD changed to 25 µA
VCCMax on 32 M (28F320B3) changed to 3.3 V
-011
Added 64-Mbit density and faster speed offerings
Removed access time vs. capacitance load curve
-012
Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product
offering.
Changed VccMax=3.3V reference to indicate the affected product is the 0.25µm 32Mbit
device.
Minor text edits throughout document.
-013
Added New Pin-1 indicator information on 40 and 48Lead TSOP packages.
Minor text edits throughout document.
-014
Added specifications for 0.13 micron product offerings throughout document
-015
Minor text edits throughout document.
Adjusted ordering information.
Adjusted specifications for 0.13 micron product offerings.
-016
Revised and corrected DC Characteristics Table.
Adjusted package diagram information.
Minor text edits throughout document.
vi
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.0
Introduction
This datasheet contains the specifications for the 3-Volt Advanced Boot Block Flash Memory
family, which is optimized for portable, low-power, systems. This family of products features
1.65 V–2.5 V or 2.7 V–3.6 V I/Os, and a low VCC/VPP operating range of 2.7 V–3.6 V for Read,
Program, and Erase operations. In addition, this family is capable of fast programming at 12 V.
Throughout this document, the term “2.7 V” refers to the full voltage range 2.7 V–3.6 V (except
where noted otherwise) and “VPP = 12 V” refers to 12 V ±5%. Section 1.0 and 2.0 provide an
overview of the Flash Memory family including applications, pinouts, and pin descriptions.
Section 3.0 describes the memory organization and operation for these products. Sections 4.0 and
5.0 contain the operating specifications. Finally, Sections 6.0 and 7.0 provide ordering and other
reference information.
The 3-Volt Advanced Boot Block Flash Memory features the following:
• Enhanced blocking for easy segmentation of code and data or additional design flexibility
• Program Suspend to Read command
• VCCQ input of 1.65 V–2.5 V or 2.7 V–3.6 V on all I/Os. See Figures 1 through 4 for pinout
diagrams and VCCQ location
• Maximum program and erase time specification for improved data storage.
Table 1.
3-Volt Advanced Boot Block Feature Summary
Feature
VCC Read Voltage
VCCQ I/O Voltage
1.65 V–2.5 V or 2.7 V– 3.6 V
Section 4.2, 4.4
2.7 V– 3.6 V or 11.4 V– 12.6 V
Section 4.2, 4.4
8 bit
Speed
Reference
Section 4.2,
Section 4.4
2.7 V– 3.6 V
VPP Program/Erase Voltage
Bus Width
28F800B3, 28F160B3,
28F320B3(3), 28F640B3
28F008B3, 28F016B3
16 bit
70 ns, 80 ns, 90 ns, 100 ns, 110 ns
512 Kbit x 16 (8 Mbit),
1024 Kbit x 16 (16 Mbit),
2048 Kbit x 16 (32 Mbit),
4096 Kbit x 16 (64 Mbit)
Table 3
Section 4.5
Memory Arrangement
1024 Kbit x 8 (8 Mbit),
2048 Kbit x 8 (16 Mbit)
Blocking (top or bottom)
Eight 8-Kbyte parameter blocks and
Fifteen 64-Kbyte blocks (8 Mbit) or
Thirty-one 64-Kbyte main blocks (16 Mbit)
Sixty-three 64-Kbyte main blocks (32 Mbit)
One hundred twenty-seven 64-Kbyte main blocks (64 Mbit)
Section 2.2
Appendix C
WP# locks/unlocks parameter blocks
All other blocks protected using VPP
Section 3.3
Table 8
Locking
Section 2.2
Operating Temperature
Extended: –40 °C to +85 °C
Section 4.2, 4.4
Program/Erase Cycling
100,000 cycles
Section 4.2, 4.4
(1)
Packages
40-lead TSOP ,
48-Ball µBGA* CSP(2)
48-Lead TSOP,
48-Ball µBGA CSP(2),
48-Ball VF BGA(4)
Figure 4, Figure 5
NOTES:
1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP.
2. 8-Mbit densities not available in µBGA* CSP.
3. VCCMax is 3.3 V on 0.25µm 32-Mbit devices.
1
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
1.1
Product Overview
Intel provides the most flexible voltage solution in the flash industry, providing three discrete
voltage supply pins: VCC for Read operation, VCCQ for output swing, and VPP for Program and
Erase operation. All 3-Volt Advanced Boot Block Flash Memory products provide program/erase
capability at 2.7 V or 12 V (for fast production programming), and read with VCC at 2.7 V. Since
many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can
provide substantial power savings.
The 3-Volt Advanced Boot Block Flash Memory products are available in either x8 or x16
packages in the following densities: (see Section 6.0, “Ordering Information” on page 39 for
availability.)
• 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024
Kbytes of 8-bits each
• 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or
2048 Kbytes of 8-bits each
• 32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each
• 64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each
The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix)
of the address map in order to accommodate different microprocessor protocols for kernel code
location. The upper two (or lower two) parameter blocks can be locked to provide complete code
security for system initialization code. Locking and unlocking is controlled by WP# (see Section
3.3, “Block Locking” on page 17 for details).
The Command User Interface (CUI) serves as the interface between the microprocessor or
microcontroller and the internal operation of the flash memory. The internal Write State Machine
(WSM) automatically executes the algorithms and timings necessary for Program and Erase
operations, including verification, thereby unburdening the microprocessor or microcontroller. The
status register indicates the status of the WSM by signifying block erase or word program
completion and status.
The 3-Volt Advanced Boot Block flash memory is also designed with an Automatic Power Savings
(APS) feature, which minimizes system current drain and allows for very low power designs. This
mode is entered following the completion of a read cycle (approximately 300 ns later).
The RP# pin provides additional protection against unwanted command writes that may occur
during system reset and power-up/down sequences due to invalid system bus conditions (see
Section 3.6, “Power-Up/Down Operation” on page 19).
Section 3.0, “Principles of Operation” on page 10 gives detailed explanation of the different modes
of operation. Section 4.4, “DC Characteristics” on page 23 provides complete current and voltage
specifications. Refer to Section 4.5, “AC Characteristics —Read Operations” on page 27 for read,
program, and erase performance specifications.
2
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2.0
Product Description
This section explains device pin description and package pinouts.
2.1
Package Pinouts
The 3-Volt Advanced Boot Block flash memory is available in 40-lead TSOP (x8, Figure 1),
48-lead TSOP (x16, Figure 2), 48-ball µBGA(x8 and x16, Figure 4 and Figure 5, respectively), and
48-ball VF BGA (x16, Figure 5) packages. In all figures, pin changes necessary for density
upgrades have been circled.
Figure 1. 40-Lead TSOP Package for x8 Configurations
4M
A16
A15
A14
A13
A12
A11
A9
A8
WE#
RP#
VPP
WP#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Advanced Boot Block
40-Lead TSOP
10 mm x 20 mm
TOP VIEW
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
GND
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
VCCQ
VCC
NC
DQ3
DQ2
DQ1
DQ0
OE#
GND
CE#
A0
16 M
8M
0580_01
NOTES:
1. 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only.
2. Lower densities will have NC on the upper address pins. For example, an 8-Mbit device will have NC on
Pin 38.
3
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 2. 48-Lead TSOP Package for x16 Configurations
64 M
32 M
16 M
A15
A14
A13
A12
A11
A10
A9
A8
A21
A20
WE#
RP#
VPP
WP#
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Advanced Boot Block
48-Lead TSOP
12 mm x 20 mm
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A 16
V CCQ
GND
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
GND
CE#
A0
0580_02
4
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 3. New Mark for Pin-1 indicator for 40-Lead 8 Mb, 16 Mb TSOP and 48-Lead 8 Mb, 16
Mb and 32 Mb TSOP
Current Mark:
New Mark:
Note:
The topside marking on 8 Mb, 16 Mb, and 32 Mb Advanced & Advanced + Boot Block 40L and
48L TSOP products will convert to a white ink triangle as a Pin-1 indicator. Products without the
white triangle will continue to use a dimple as a Pin-1 indicator. There are no other changes in
package size, materials, functionality, customer handling, or manufacturability. Product will
continue to meet stringent Intel quality requirements.
Products Affected are Intel Ordering Codes:
5
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Ordering Information Valid Combinations
40-Lead TSOP
48-Lead TSOP
TE28F320B3TC70
TE28F320B3BC70
TE28F320B3TC90
TE28F320B3BC90
Ext. Temp. 32
Mbit
TE28F320B3TA100
TE28F320B3BA100
TE28F320B3TA110
TE28F320B3BA110
TE28F160B3TC70
TE28F160B3BC70
TE28F160B3TC80
Ext. Temp. 16
Mbit
TE28F160B3BC80
TE28F016B3TA90(3)
TE28F160B3TA90(3)
TE28F016B3BA90(3)
TE28F160B3BA90(3)
(3)
TE28F160B3TA110(3)
(3)
TE28F016B3TA110
Ext. Temp. 8
Mbit
TE28F016B3BA110
TE28F160B3BA110(3)
TE28F008B3TA90(3)
TE28F800B3TA90(3)
TE28F008B3BA90(3)
TE28F800B3BA90(3)
(3)
TE28F800B3TA110(3)
(3)
TE28F800B3BA110(3)
TE28F008B3TA110
TE28F008B3BA110
6
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 4. x8 48-Ball µBGA* Chip Size Package (Top View, Ball Down)
1
2
3
4
5
6
7
8
16M
A
A14
A12
A8
V PP
B
A15
A10
W E#
RP#
C
A16
A13
A9
D
A17
NC
D5
NC
E
VCCQ
A11
D6
D7
NC
W P#
A20
A7
A4
A19
A18
A5
A2
A6
A3
A1
D2
NC
CE#
A0
NC
D3
NC
D0
GND
D4
VCC
NC
D1
OE#
8M
F
GND
0580_04
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A20 is the upgrade address for the
16-Mbit device.
7
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Figure 5. x16 48-Ball Very Fine Pitch BGA and µBGA* Chip Size Package (Top View, Ball
Down)
1
2
3
4
5
6
7
8
16M
A
A13
A11
A8
VPP
WP#
A19
A7
A4
B
A14
A10
WE#
RP#
A18
A17
A5
A2
64M
32M
C
A15
A12
A9
A21
A20
A6
A3
A1
D
A16
D14
D5
D11
D2
D8
CE#
A0
E
VCCQ
D15
D6
D12
D3
D9
D0
Vss
F
Vss
D7
D13
D4
VCC
D10
D1
OE#
0580_03
NOTES:
1. Shaded connections indicate the upgrade address connections. Lower density devices will not have the
upper address solder balls. Routing is not recommended in this area. A19 is the upgrade address for the
16-Mbit device. A20 is the upgrade address for the 32-Mbit device. A21 is the upgrade address for the 64-Mbit
device.
2. Table 2, “3-Volt Advanced Boot Block Pin Descriptions” on page 9 details the usage of each device pin.
8
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 2.
Symbol
A0–A21
3-Volt Advanced Boot Block Pin Descriptions
Type
INPUT
Name and Function
ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or
erase cycle.
28F008B3: A[0-19], 28F016B3: A[0-20],
28F800B3: A[0-18], 28F160B3: A[0-19],
28F320B3: A[0-20], 28F640B3: A[0-21]
DQ0–DQ7
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Inputs commands to the Command User Interface when CE# and WE# are active. Data is
internally latched. Outputs array, identifier and status register data. The data pins float to tri-state when
the chip is de-selected or the outputs are disabled.
DQ8–
DQ15
INPUT/
OUTPUT
DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program
command. Data is internally latched. Outputs array and identifier data. The data pins float to tri-state
when the chip is de-selected. Not included on x8 products.
CE#
INPUT
CHIP ENABLE: Activates the internal control logic, input buffers, decoders and sense amplifiers. CE#
is active low. CE# high de-selects the memory device and reduces power consumption to standby
levels.
OE#
INPUT
OUTPUT ENABLE: Enables the device’s outputs through the data buffers during a Read operation.
OE# is active low.
WE#
INPUT
WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low.
Addresses and data are latched on the rising edge of the second WE# pulse.
RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep power-down
mode.
RP#
INPUT
When RP# is at logic low, the device is in reset/deep power-down mode, which drives the outputs
to High-Z, resets the Write State Machine, and minimizes current levels (ICCD).
When RP# is at logic high, the device is in standard operation. When RP# transitions from logiclow to logic-high, the device defaults to the read array mode.
WRITE PROTECT: Provides a method for locking and unlocking the two lockable parameter blocks.
WP#
INPUT
When WP# is at logic low, the lockable blocks are locked, preventing Program and Erase
operations to those blocks. If a Program or Erase operation is attempted on a locked block, SR.1 and
either SR.4 [program] or SR.5 [erase] will be set to indicate the operation failed.
When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased.
See Section 3.3 for details on write protection.
VCCQ
INPUT
OUTPUT VCC: Enables all outputs to be driven to 1.8 V – 2.5 V while the VCC is at 2.7 V–3.3 V. If the
VCC is regulated to 2.7 V–2.85 V, VCCQ can be driven at 1.65 V–2.5 V to achieve lowest power
operation (see Section 4.4).
This input may be tied directly to VCC (2.7 V–3.6 V).
VCC
VPP
DEVICE POWER SUPPLY: 2.7 V–3.6 V
PROGRAM/ERASE POWER SUPPLY: Supplies power for Program and Erase operations. VPP may
be the same as VCC (2.7 V–3.6 V) for single supply voltage operation. For fast programming at
manufacturing, 11.4 V–12.6 V may be supplied to VPP. This pin cannot be left floating. Applying
11.4 V–12.6 V to VPP can only be done for a maximum of 1000 cycles on the main blocks and 2500
cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80 hours maximum (see
Section 3.4 for details).
VPP < VPPLK protects memory contents against inadvertent or unintended program and erase
commands.
GND
GROUND: For all internal circuitry. All ground inputs must be connected.
NC
NO CONNECT: Pin may be driven or left floating.
9
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
2.2
Block Organization
The 3-Volt Advanced Boot Block is an asymmetrically blocked architecture that enables system
integration of code and data within a single flash device. Each block can be erased independently
of the others up to 100,000 times. For the address locations of each block, see the memory maps in
Appendix C.
2.2.1
Parameter Blocks
The 3-Volt Advanced Boot Block flash memory architecture includes parameter blocks to facilitate
storage of frequently updated small parameters (i.e., data that would normally be stored in an
EEPROM). The word-rewrite functionality of EEPROMs can be emulated using software
techniques. Each device contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096
words) each.
2.2.2
Main Blocks
After the parameter blocks, the remainder of the array is divided into equal-size main blocks
(65,536 bytes/32,768 words) for data or code storage. The 8-Mbit device contains 15 main blocks;
16-Mbit flash has 31 main blocks; 32-Mbit has 63 main blocks; 64-Mbit has 127 main blocks.
3.0
Principles of Operation
Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase
capability. The 3-Volt Advanced Boot Block Flash Memory family utilizes a Command User
Interface (CUI) and automated algorithms to simplify Program and Erase operations. The CUI
allows for 100% CMOS-level control inputs and fixed power supplies during erasure and
programming.
When VPP < VPPLK, the device will execute only the following commands successfully: Read
Array, Read Status Register, Clear Status Register, and Read Identifier. The device provides
standard EEPROM read, standby, and Output-Disable operations. Manufacturer identification and
device identification data can be accessed through the CUI. All functions associated with altering
memory contents, namely program and erase, are accessible via the CUI. The internal Write State
Machine (WSM) completely automates Program and Erase operations, while the CUI signals the
start of an operation and the status register reports status. The CUI handles the WE# interface to the
data and address latches, as well as system status requests during WSM operation.
3.1
Bus Operation
3-Volt Advanced Boot Block flash memory devices read, program, and erase in-system via the
local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard
microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash
component: CE#, OE#, WE#, and RP#. Table 3 summarizes these bus operations.
10
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 3.
Bus Operations(1)
Mode
Note
Read (Array, Status, or Identifier)
RP#
CE#
OE#
WE#
DQ0–7
DQ8–15
2–4
VIH
VIL
VIL
VIH
DOUT
DOUT
Output Disable
2
VIH
VIL
VIH
VIH
High Z
High Z
Standby
2
VIH
VIH
X
X
High Z
High Z
Reset
2, 7
VIL
X
X
X
High Z
High Z
Write
2, 5–7
VIH
VIL
VIH
VIL
DIN
DIN
NOTES:
1. 8-bit devices use only DQ[0:7], 16-bit devices use DQ[0:15].
2. X must be VIL, VIH for control pins and addresses.
3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages.
4. Manufacturer and device codes may also be accessed in read identifier mode (A1–A21 = 0). See Table 5.
5. Refer to Table 6 for valid DIN during a Write operation.
6. To program or erase the lockable blocks, hold WP# at VIH.
7. RP# must be at GND ± 0.2 V to meet the maximum deep power-down current specified.
3.1.1
Read
The flash memory has four read modes available: read array, read identifier, read status, and read
query. These modes are accessible independent of the VPP voltage. The appropriate Read Mode
command must be issued to the CUI to enter the corresponding mode. Upon initial device powerup or after exit from reset, the device automatically defaults to read-array mode.
CE# and OE# must be driven active to obtain data at the outputs. CE# is the device selection
control; when active, it enables the flash memory device. OE# is the data output control, and it
drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at
VIH. Figure 8 illustrates a read cycle.
3.1.2
Output Disable
With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins are placed in a
high-impedance state.
3.1.3
Standby
Deselecting the device by bringing CE# to a logic-high level (VIH) places the device in standby
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during Program or Erase operation, the device continues to consume active power until
the Program or Erase operation is complete.
3.1.4
Deep Power-Down / Reset
From read mode, RP# at VIL for time tPLPH deselects the memory, places output drivers in a highimpedance state, and turns off all internal circuits. After return from reset, a time tPHQV is required
until the initial read-access outputs are valid. A delay (tPHWL or tPHEL) is required after return from
reset before a write can be initiated. After this wake-up interval, normal operation is restored. The
CUI resets to read-array mode, and the status register is set to 80H. Figure 10A illustrates this case.
11
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
If RP# is taken low for time tPLPH during a Program or Erase operation, the operation will be
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process that takes time
tPLRH to complete.
2. After this time tPLRH, the part will either reset to read-array mode (if RP# has gone high during
tPLRH, Figure 10B), or enter reset mode (if RP# is still logic low after tPLRH, Figure 10C).
3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/
tPHEL must be waited before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than
when RP# goes high.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel® Flash memories
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
3.1.5
Write
A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the
Command User Interface (CUI) using standard microprocessor write timings to control Flash
operations. The CUI does not occupy an addressable memory location. The address and data buses
are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Figure 9
illustrates a Program and Erase operation. Table 6 shows the available commands, and Appendix A
provides detailed information on moving between the different modes of operation using CUI
commands.
Two commands modify array data: Program (40H), and Erase (20H). Writing either of these
commands to the internal Command User Interface (CUI) initiates a sequence of internally timed
functions that culminate in the completion of the requested task (unless that operation is aborted by
either RP# being driven to VIL for tPLRH or an appropriate Suspend command).
3.2
Modes of Operation
The flash memory has four read modes (read array, read identifier, read status, and read query; see
Appendix B), and two write modes (program and block erase). Three additional modes (erase
suspend to program, erase suspend to read, and program suspend to read) are available only during
suspended operations. Table 4 summarizes the commands used to reach these modes. Appendix A
is a comprehensive chart showing the state transitions.
3.2.1
Read Array
When RP# transitions from VIL (reset) to VIH, the device defaults to read-array mode and will
respond to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI
commands.
12
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
When the device is in read-array mode, four control signals control data output.
•
•
•
•
WE# must be logic high (VIH)
CE# must be logic low (VIL)
OE# must be logic low (VIL)
RP# must be logic high (VIH)
In addition, the address of the preferred location must be applied to the address pins. If the device is
not in read-array mode, as would be the case after a Program or Erase operation, the Read Array
command (FFH) must be written to the CUI before array reads can occur.
Table 4.
Command Codes and Descriptions
Code
Device Mode
00, 01,
60, 2F,
C0, 98
Invalid/
Reserved
Unassigned commands that should not be used. Intel reserves the right to redefine these
codes for future functions.
FF
Read Array
Places the device in read-array mode, such that array data will be output on the data pins.
40
Program Set-Up
This is a two-cycle command. The first cycle prepares the CUI for a program operation. The
second cycle latches addresses and data information and initiates the WSM to execute the
program algorithm. The flash outputs status register data when CE# or OE# is toggled. A Read
Array command is required after programming to read array data. See Section 3.2.4.
10
Alternate
Program Set-Up
(See 40H/Program Set-Up)
20
Erase Set-Up
Erase Confirm
D0
Description
Prepares the CUI for the Erase Confirm command. If the next command is not an Erase
Confirm command, then the CUI will (a) set both SR.4 and SR.5 of the status register to a “1,”
(b) place the device into the read-status-register mode, and (c) wait for another command. See
Section 3.2.5.
If the previous command was an Erase Set-Up command, then the CUI will close the address
and data latches, and begin erasing the block indicated on the address pins. During erase, the
device will only respond to the Read Status Register and Erase Suspend commands. The
device will output status-register data when CE# or OE# is toggled.
Program / Erase
Resume
If a Program or Erase operation was previously suspended, this command will resume that
operation.
B0
Program / Erase
Suspend
Issuing this command will begin to suspend the currently executing Program/Erase operation.
The status register will indicate when the operation has been successfully suspended by
setting either the program suspend (SR.2) or erase suspend (SR.6), and the WSM status bit
(SR.7) to a “1” (ready). The WSM will continue to idle in the SUSPEND state, regardless of the
state of all input-control pins except RP#, which will immediately shut down the WSM and the
remainder of the chip, if it is driven to VIL. See Section 3.2.4.1 and Section 3.2.4.1.
70
Read Status
Register
This command places the device into read-status-register mode. Reading the device will output
the contents of the status register, regardless of the address presented to the device. The
device automatically enters this mode after a Program or Erase operation has been initiated.
See Section 3.2.3.
50
Clear Status
Register
The WSM can set the block-lock status (SR.1), VPP status (SR.3), program status (SR.4), and
erase status (SR.5) bits in the status register to “1,” but it cannot clear them to “0.” Issuing this
command clears those bits to “0.”
90
Read Identifier
Puts the device into the intelligent-identifier-read mode, so that reading the device will output
the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for device, all other
address inputs must be 0). See Section Section 3.2.2.
NOTE: See Appendix A for mode transition information.
13
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.2.2
Read Identifier
To read the manufacturer and device codes, the device must be in read-identifier mode, which can
be reached by writing the Read Identifier command (90H). Once in read-identifier mode, A0 = 0
outputs the manufacturer’s identification code, and A0 = 1 outputs the device identifier (see
Table 5) Note: A1–A21 = 0. To return to read-array mode, write the Read-Array command (FFH).
Table 5.
Read Identifier Table
Device Identifier
Size
Mfr. ID
-T
(Top Boot)
-B
(Bottom Boot)
D4H
D5H
28F400B3
8894H
8895H
28F008B3
D2H
D3H
28F004B3
0089H
28F800B3
8892H
8893H
28F016B3
D0H
D1H
28F160B3
8890H
8891H
8896H
8897H
8898H
8899H
28F320B3
28F640B3
3.2.3
0089H
0089H
Read Status Register
The device status register indicates when a Program or Erase operation is complete, and the success
or failure of that operation. To read the status register, issue the Read Status Register (70H)
command to the CUI. This causes all subsequent Read operations to output data from the status
register until another command is written to the CUI. To return to reading from the array, issue the
Read Array (FFH) command.
The status-register bits are output on DQ0–DQ7. The upper byte, DQ8–DQ15, outputs 00H during a
Read Status Register command.
The contents of the status register are latched on the falling edge of OE# or CE#, which prevents
possible Bus errors that might occur if status-register contents change while being read. CE# or
OE# must be toggled with each subsequent status read, or the status register will not indicate
completion of a Program or Erase operation.
When the WSM is active, SR.7 will indicate the status of the WSM; the remaining bits in the status
register indicate whether or not the WSM was successful in performing the preferred operation (see
Table 7 on page 17).
3.2.3.1
Clearing the Status Register
The WSM sets status bits 1 through 7 to “1,” and clears bits 2, 6, and 7 to “0,” but cannot clear
status bits 1 or 3 through 5 to “0.” Because bits 1, 3, 4, and 5 indicate various error conditions,
these bits can be cleared only through the Clear Status Register (50H) command. By allowing the
system software to control the resetting of these bits, several operations may be performed (such as
cumulatively programming several addresses or erasing multiple blocks in sequence) before
14
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
reading the status register to determine if an error occurred during that series. Clear the status
register before beginning another command or sequence. Note, again, that the Read Array
command must be issued before data can be read from the memory array.
3.2.4
Program Mode
Programming is executed using a two-write sequence. The Program Setup command (40H) is
written to the CUI followed by a second write that specifies the address and data to be
programmed. The WSM will execute a sequence of internally timed events to program preferred
bits of the addressed location, then verify the bits are sufficiently programmed. Programming the
memory results in specific bits within an address location being changed to a “0.” If users attempt
to program “1”s, the memory cell contents do not change and no error occurs.
The status register indicates programming status: while the program sequence executes, status bit 7
is “0.” The status register can be polled by toggling either CE# or OE#. While programming, the
only valid commands are Read Status Register, Program Suspend, and Program Resume.
When programming is complete, the program-status bits should be checked. If the programming
operation was unsuccessful, bit SR.4 of the status register is set to indicate a program failure. If
SR.3 is set, then VPP was not within acceptable limits, and the WSM did not execute the program
command. If SR.1 is set, a program operation was attempted on a locked block and the operation
was aborted.
The status register should be cleared before attempting the next operation. Any CUI instruction can
follow after programming is completed; however, to prevent inadvertent status-register reads, be
sure to reset the CUI to read-array mode.
3.2.4.1
Suspending and Resuming Program
The Program Suspend halts the in-progress program operation to read data from another location of
memory. Once the programming process starts, writing the Program Suspend command to the CUI
requests that the WSM suspend the program sequence (at predetermined points in the program
algorithm). The device continues to output status-register data after the Program Suspend
command is written. Polling status-register bits SR.7 and SR.2 will determine when the program
operation has been suspended (both will be set to “1”). tWHRH1/tEHRH1 specify the programsuspend latency.
A Read Array command can now be written to the CUI to read data from blocks other than that
which is suspended. The only other valid commands while program is suspended are Read Status
Register, Read Identifier, and Program Resume. After the Program Resume command is written to
the flash memory, the WSM will continue with the program process and status-register bits SR.2
and SR.7 will automatically be cleared. After the Program Resume command is written, the device
automatically outputs status-register data when read (see Appendix E for Program Suspend and
Resume Flowchart). VPP must remain at the same VPP level used for program while in programsuspend mode. RP# must also remain at VIH.
3.2.5
Erase Mode
To erase a block, write the Erase Set-up and Erase Confirm commands to the CUI, along with an
address identifying the block to be erased. This address is latched internally when the Erase
Confirm command is issued. Block erasure results in all bits within the block being set to “1.” Only
one block can be erased at a time. The WSM will execute a sequence of internally timed events to
program all bits within the block to “0,” erase all bits within the block to “1,” then verify that all
bits within the block are sufficiently erased. While the erase executes, status bit 7 is a “0.”
15
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
When the status register indicates that erasure is complete, check the erase-status bit to verify that
the Erase operation was successful. If the Erase operation was unsuccessful, SR.5 of the status
register will be set to a “1,” indicating an erase failure. If VPP was not within acceptable limits after
the Erase Confirm command was issued, the WSM will not execute the erase sequence; instead,
SR.5 of the status register is set to indicate an Erase error, and SR.3 is set to a “1” to identify that
VPP supply voltage was not within acceptable limits.
After an Erase operation, clear the status register (50H) before attempting the next operation. Any
CUI instruction can follow after erasure is completed; however, to prevent inadvertent statusregister reads, it is advisable to place the flash in read-array mode after the erase is complete.
3.2.5.1
Suspending and Resuming Erase
Since an Erase operation requires on the order of seconds to complete, an Erase Suspend command
is provided to allow erase-sequence interruption in order to read data from—or program data to—
another block in memory. Once the erase sequence is started, writing the Erase Suspend command
to the CUI requests that the WSM pause the erase sequence at a predetermined point in the erase
algorithm. The status register will indicate if/when the Erase operation has been suspended.
A Read Array/Program command can now be written to the CUI in order to read data from/
program data to blocks other than the one currently suspended. The Program command can
subsequently be suspended to read yet another array location. The only valid commands while
Erase is suspended are Erase Resume, Program, Read Array, Read Status Register, or Read
Identifier. During erase-suspend mode, the chip can be placed in a pseudo-standby mode by taking
CE# to VIH, which reduces active current consumption.
Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard Erase
operation, the status register must be read and cleared before the next instruction is issued.
Table 6.
(1,4)
Command Bus Definitions
First Bus Cycle
Command
Notes
Read Array
Read Identifier
Oper
Addr
Data
Write
X
FFH
Oper
Addr
Data
Write
X
90H
Read
IA
ID
Read Status Register
Write
X
70H
Read
X
SRD
Clear Status Register
Write
X
50H
Write
X
40H /
10H
Write
PA
PD
Block Erase/Confirm
Write
X
20H
Write
BA
D0H
Program/Erase Suspend
Write
X
B0H
Program/Erase Resume
Write
X
D0H
Program
2
Second Bus Cycle
3
NOTES:
PA: Program Address
PD: Program Data
BA: Block Address
IA: Identifier Address
ID: Identifier Data
SRD: Status Register Data
1. Bus operations are defined in Table 3.
2. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes.
A 0 = 0 for manufacturer code, A0 = 1 for device code. A1–A21 = 0.
3. Either 40H or 10H command is valid although the standard is 40H.
4. When writing commands to the device, the upper data bus [DQ 8–DQ15] should be either VIL or VIH, to
minimize current draw.
16
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
Table 7.
Status Register Bit Definition
WSMS
ESS
ES
PS
VPPS
PSS
BLS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
Check Write State Machine bit first to determine word program
or block-erase completion, before checking program or erasestatus bits.
SR.6 = ERASE-SUSPEND STATUS (ESS)
1 = Erase Suspended
0 = Erase In Progress/Completed
When erase suspend is issued, WSM halts execution and sets
both WSMS and ESS bits to “1.” ESS bit remains set at “1” until
an Erase Resume command is issued.
SR.5 = ERASE STATUS (ES)
1 = Error In Block Erasure
0 = Successful Block Erase
When this bit is set to “1,” WSM has applied the max. number
of erase pulses to the block and is still unable to verify
successful block erasure.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Word Program
0 = Successful Word Program
When this bit is set to “1,” WSM has attempted but failed to
program a word.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
The VPP status bit does not provide continuous indication of
VPP level. The WSM interrogates VPP level only after the
Program or Erase command sequences have been entered,
and informs the system if VPP has not been switched on. The
VPP is also checked before the operation is verified by the
WSM. The VPP status bit is not guaranteed to report accurate
feedback between VPPLK max and VPP1 min or between VPP1
max and VPP4 min.
SR.2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
When program suspend is issued, WSM halts execution and
sets both WSMS and PSS bits to “1.” PSS bit remains set to “1”
until a Program Resume command is issued.
SR.1 = BLOCK LOCK STATUS
1 = Program/Erase attempted on locked block;
Operation aborted
0 = No operation to locked blocks
If a Program or Erase operation is attempted to one of the
locked blocks, this bit is set by the WSM. The operation
specified is aborted and the device is returned to read status
mode.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)
This bit is reserved for future use and should be masked out
when polling the status register.
NOTE: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set.
3.3
Block Locking
The 3-Volt Advanced Boot Block flash memory architecture features two hardware-lockable
parameter blocks.
3.3.1
WP# = VIL for Block Locking
The lockable blocks are locked when WP# = VIL; any program or Erase operation to a locked
block will result in an error, which will be reflected in the status register. For top configuration, the
top two parameter blocks (blocks #133 and #134 for the 64 Mbit, #69 and #70 for the 32 Mbit,
blocks #37 and #38 for the 16 Mbit, blocks #21 and #22 for the 8 Mbit, blocks #13 and #14 for the
4 Mbit) are lockable. For the bottom configuration, the bottom two parameter blocks (blocks #0
and #1 for 4 /8 /16 /32/64 Mbit) are lockable. Unlocked blocks can be programmed or erased
normally (unless VPP is below VPPLK).
17
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.3.2
WP# = VIH for Block Unlocking
WP# = VIH unlocks all lockable blocks.
These blocks can now be programmed or erased.
Note that RP# does not override WP# locking as in previous Boot Block devices. WP# controls all
block locking and VPP provides protection against spurious writes. Table 8 defines the writeprotection methods.
Table 8.
3.4
Write-Protection Truth Table for the Advanced Boot Block Flash Memory Family
VPP
WP#
RP#
Write Protection Provided
X
X
VIL
All Blocks Locked
VIL
X
VIH
All Blocks Locked
≥ VPPLK
VIL
VIH
Lockable Blocks Locked
≥ VPPLK
VIH
VIH
All Blocks Unlocked
VPP Program and Erase Voltages
Intel® 3-Volt Advanced Boot Block products provide in-system programming and erase at 2.7 V.
For customers requiring fast programming in their manufacturing environment, 3-Volt Advanced
Boot Block includes an additional low-cost 12-V programming feature.
The 12-V VPP mode enhances programming performance during the short period of time typically
found in manufacturing processes; however, it is not intended for extended use. 12 V may be
applied to VPP during program and Erase operations for a maximum of 1000 cycles on the main
blocks, and 2500 cycles on the parameter blocks. VPP may be connected to 12 V for a total of 80
hours maximum.
Warning:
Stressing the device beyond these limits may cause permanent damage.
During Read operations or idle times, VPP may be tied to a 5-V supply. For Program and Erase
operations, a 5-V supply is not permitted. The VPP must be supplied with either 2.7 V–3.6 V or
11.4 V–12.6 V during Program and Erase operations.
3.4.1
VPP = VIL for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the
flash device. When VPP is below VPPLK, any Program or Erase operation will result in a error,
prompting the corresponding status-register bit (SR.3) to be set.
3.5
Power Consumption
Intel flash devices have a tiered approach to power savings that can significantly reduce overall
system power consumption. The Automatic Power Savings (APS) feature reduces power
consumption when the device is selected but idle. If the CE# is deasserted, the flash enters its
standby mode, where current consumption is even lower. The combination of these features can
minimize memory power consumption, and therefore, overall system power consumption.
18
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.5.1
Active Power
With CE# at a logic-low level and RP# at a logic-high level, the device is in the active mode. Refer
to the DC Characteristic tables for ICC current values. Active power is the largest contributor to
overall system power consumption. Minimizing the active current could have a profound effect on
system power consumption, especially for battery-operated devices.
3.5.2
Automatic Power Savings (APS)
Automatic Power Savings provides low-power operation during read mode. After data is read from
the memory array and the address lines are quiescent, APS circuitry places the device in a mode
where typical current is comparable to ICCS. The flash stays in this static state with outputs valid
until a new location is read.
3.5.3
Standby Power
With CE# at a logic-high level (VIH) and the device in read mode, the flash memory is in standby
mode, which disables much of the device circuitry, and substantially reduces power consumption.
Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE#
transitions to a logic-high level during Erase or Program operations, the device will continue to
perform the operation and consume corresponding active power until the operation is completed.
System engineers should analyze the breakdown of standby time versus active time, and quantify
the respective power consumption in each mode for their specific application. This approach will
provide a more accurate measure of application-specific power and energy requirements.
3.5.4
Deep Power-Down Mode
The deep power-down mode is activated when RP# = VIL (GND ± 0.2 V). During read modes,
RP# going low de-selects the memory and places the outputs in a high-impedance state. Recovery
from deep power-down requires a minimum time of tPHQV (see AC Characteristics—Read
Operations, Section 4.5).
During program or erase modes, RP# transitioning low will abort the in-progress operation. The
memory contents of the address being programmed or the block being erased are no longer valid as
the data integrity has been compromised by the abort. During deep power-down, all internal
circuits are switched to a low-power savings mode (RP# transitioning to VIL or turning off power
to the device clears the status register).
3.6
Power and Reset Considerations
3.6.1
Power-Up/Down Characteristics
In order to prevent any condition that may result in a spurious write or erase operation, it is
recommended to power-up VCC and VCCQ together. Conversely, VCC and VCCQ must power-down
together. It is also recommended to power-up VPP with or slightly after VCC. Conversely, VPP must
powerdown with or slightly before VCC.
If VCCQ and/or VPP are not connected to the VCC supply, then VCC should attain VCCMin before
applying VCCQ and VPP. Device inputs should not be driven before supply voltage = VCCMin.
Power supply transitions should only occur when RP# is low.
19
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
3.6.2
RP# Connected to System Reset
The use of RP# during system reset is important with automated program/erase devices because the
system expects to read from the flash memory when it exits reset. If a CPU reset occurs without a
flash memory reset, proper CPU initialization will not occur because the flash memory may be
providing status information instead of array data. Intel recommends connecting RP# to the system
CPU RESET# signal to allow proper CPU/flash initialization following system reset.
System designers must guard against spurious writes when VCC voltages are above VLKO. Because
both WE# and CE# must be low for a command write, driving either signal to VIH will inhibit
writes to the device. The CUI architecture provides additional protection since alteration of
memory contents can occur only after successful completion of the two-step command sequences.
The device is also disabled until RP# is brought to VIH, regardless of the state of its control inputs.
By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down,
invalid bus conditions during power-up can be masked, providing yet another level of memory
protection.
3.6.3
VCC, VPP and RP# Transitions
The CUI latches commands as issued by system software and is not altered by VPP or CE#
transitions or WSM actions. Its default state upon power-up, after exit from reset mode or after
VCC transitions above VLKO (Lockout voltage), is read-array mode.
After any program or Block-Erase operation is complete (even after VPP transitions down to
VPPLK), the CUI must be reset to read-array mode via the Read Array command if access to the
flash-memory array is required.
3.7
Power Supply Decoupling
Flash memory power-switching characteristics require careful device decoupling. System
designers should consider the following three supply current issues:
1. Standby current levels (ICCS)
2. Read current levels (ICCR)
3. Transient peaks produced by falling and rising edges of CE#.
Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Twoline control and proper decoupling capacitor selection will suppress these transient voltage peaks.
Each flash device should have a 0.1 µF ceramic capacitor connected between each VCC and GND,
and between its VPP and GND. These high-frequency, inherently low-inductance capacitors should
be placed as close as possible to the package leads.
20
28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3
4.0
Electrical Specifications
4.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Extended Operating Temperature
During Read
–40 °C to +85 °C
During Block Erase and Program
–40 °C to +85 °C
Temperature under Bias
–40 °C to +85 °C
Storage Temperature
–65 °C to +125 °C
Voltage On Any Pin (except VCC, VCCQ and VPP) with Respect to GND
–0.5 V to +3.7 V(1)
VPP Voltage (for Block Erase and Program) with Respect to GND
–0.5 V to +13.5 V(1,2,3)
VCC and VCCQ Supply Voltage with Respect to GND
–0.2 V to +3.7 V(4)
Output Short Circuit Current
100 mA(5)
NOTES:
1. Minimum DC voltage is -0.5 V on input/output pins, with allowable undershoot to -2.0 V for periods
工商网监
湘ICP备2023018690号
