MAS3549F

DATA SHEET MICRONAS MAS 35x9F MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec June 30, 2004 6251-505-1DS MICRONAS MAS 35x9F Contents Page 5 6 6 7 8 8 8 8 9 9 9 9 10 10 10 10 10 10 10 11 11 11 11 11 12 12 12 13 15 15 15 15 15 15 15 15 16 17 17 18 18 18 18 18 18 19 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.3.1. 2.3.2. 2.3.2.1. 2.3.2.2. 2.4. 2.4.1. 2.4.2. 2.4.2.1. 2.4.2.2. 2.4.2.3. 2.4.2.4. 2.4.3. 2.4.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.6.1. 2.6.2. 2.6.3. 2.7. 2.8. 2.8.1. 2.8.2. 2.8.3. 2.8.4. 2.8.5. 2.8.6. 2.9. 2.10. 2.10.1. 2.10.2. 2.10.2.1. 2.10.2.2. 2.11. 2.11.1. 2.11.2. 2.11.2.1. Title Introduction Features Features of the MAS 35x9F Family Application Overview Functional Description Overview Architecture of the MAS 35x9F DSP Core RAM and Registers Firmware and Software Internal Program ROM and Firmware, MPEG-Decoding Program Download Feature Audio Codec A/D Converter and Microphone Amplifier Baseband Processing Bass, Treble, and Loudness Micronas Bass (MB) Automatic Volume Control (AVC) Balance and Volume D/A Converters Output Amplifiers Clock Management DSP Clock Clock Output At CLKO Power Supply Concept Power Supply Regions DC/DC Converters Power Supply Configurations Battery Voltage Supervision Interfaces I2C Control Interface S/PDIF Input Interface S/PDIF Output Multiline Serial Audio Input (SDI, SDIB) Multiline Serial Output (SDO) Parallel Input/Output Interface (PIO) MPEG Synchronization Output MP3 Block Input Mode Functional Description of the MP3 Block Input Mode Setup Resync Timeout Detailed Setup Default Operation Stand-by Functions Power-Up of the DC/DC Converters and Reset Important Advice for Turn-on and Operating Voltage DATA SHEET 2 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Contents, continued Page 20 21 21 21 22 22 22 22 22 22 23 23 27 27 28 28 28 28 29 29 29 29 29 30 30 30 31 31 31 32 32 43 43 44 44 45 45 45 46 52 Section 2.11.3. 2.11.4. 2.11.5. 2.11.6. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.2. 3.2.1. 3.2.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.3.2.8. 3.3.2.9. 3.3.2.10. 3.3.2.11. 3.3.2.12. 3.3.3. 3.3.4. 3.3.4.1. 3.3.4.2. 3.3.5. 3.3.6. 3.3.7. 3.3.8. 3.4. 3.4.1. 3.4.2. 3.4.3. 3.4.4. Title Reset Signal Specification Control of the Signal Processing Start-up of the Audio Codec Power-Down Controlling I2C Interface Device Address I2C Registers and Subaddresses Naming Convention Direct Configuration Registers Write Direct Configuration Registers Read Direct Configuration Register DSP Core Access Protocol Data Formats Run and Freeze (Codes 0hex to 3hex) Read Register (Code Ahex) Write Register (Code Bhex) Read Memory (Codes Chex and Dhex) Short Read Memory (Codes C4hex and D4hex) Write Memory (Codes Ehex and Fhex) Short Write Memory (Codes E4hex and F4hex) Clear SYNC Signal (Code 5hex) Default Read Fast Program Download (Code 6hex) Serial Program Download Read IC Version (Code 7hex) List of DSP Registers List of DSP Memory Cells Application Selection and Application Running Application Specific Control Ancillary Data Reading of the Memory Cells “Number of Bits in Ancillary Data” and “Ancillary Data” DSP Volume Control Explanation of the G.729A Data Format Audio Codec Access Protocol Write Codec Register Read Codec Register Codec Registers Basic MB Configuration Micronas June 30, 2004; 6251-505-1DS 3 MAS 35x9F Contents, continued Page 54 54 57 60 60 60 60 60 60 60 61 61 61 61 61 61 61 61 62 62 63 64 65 65 67 71 72 73 74 76 77 77 79 80 81 84 86 89 89 90 92 Section 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.6.1. 4.3.7. 4.3.8. 4.3.9. 4.3.10. 4.3.11. 4.3.12. 4.3.13. 4.3.14. 4.4. 4.5. 4.5.1. 4.6. 4.6.1. 4.6.1.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.2.5. 4.6.2.6. 4.6.2.7. 4.6.2.8. 4.6.3. 4.6.4. 4.6.5. 5. 5.1. 5.2. 6. Title Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Analog Reference Pins DC/DC Converters and Battery Voltage Supervision Oscillator Pins and Clocking Control Lines Parallel Interface Lines PIO Handshake Lines Serial Input Interface (SDI) Serial Input Interface B (SDIB) Serial Output Interface (SDO) S/PDIF Input Interface S/PDIF Output Interface Analog Input Interfaces Analog Output Interfaces Miscellaneous Pin Configuration Internal Pin Circuits Reset Pin Configuration for MAS 3529F and MAS 3539F Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions Digital Characteristics I2C Characteristics Serial (I2S) Input Interface Characteristics (SDI, SDIB) Serial Output Interface Characteristics (SDO) S/PDIF Input Characteristics S/PDIF Output Characteristics PIO as Parallel Input Interface: DMA Mode PIO as Parallel Input Interface: Program Download Mode PIO as Parallel Output Interface Analog Characteristics DC/DC Converter Characteristics Typical Performance Characteristics Application Typical Application in a Portable Player Recommended DC/DC Converter Application Circuit Data Sheet History DATA SHEET 4 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F In MPEG 1 (ISO 11172-3), three hierarchical layers of compression have been standardized. The most sophisticated and complex, layer 3, allows compression rates of approximately 12:1 for mono and stereo signals while still maintaining CD audio quality. Layer 2 (widely used, e.g., in DVD) achieves a compression of 8:1 without significant losses in audio quality. The MAS 35x9F supports the “Advanced Audio Coding” (AAC) that is defined as a part of MPEG 2. AAC provides compression rates up to 16:1. It defines several profiles for different applications. This IC decodes the “low complexity profile” that is especially optimized for portable applications. The MAS 35x9F also implements a voice encoder and decoder that is compliant to the ITU Standard G.729 Annex A. SC4 is a proprietary Micronas speech codec technology that can be downloaded to the MAS 35x9F, to allow recording and playing back speech at various sampling rates. MPEG Layer 2/3, AAC Audio Decoder, G.729 Annex A Codec Release Note: Revision bars indicate significant changes to the previous edition. This data sheet applies to the MAS 35x9F version B4. 1. Introduction The MAS 35x9F is a single-chip, low-power MPEG layer 2/3 and MPEG2-AAC audio stereo decoder. It also contains the G.729 Annex A speech compression and decompression technology for use in memorybased or broadcast applications. Additional functionality is achievable via download software (e.g., CELP voice decoder, Micronas SC4 (ADPCM) encoder/ decoder). The MAS 35x9F decoding block accepts compressed digital data streams as serial bit streams or in parallel format, and provides serial PCM and S/PDIF output of decompressed audio. In addition to the signal processing function, the IC incorporates a high-performance stereo D/A converter, headphone amplifiers, a stereo A/D converter, a microphone amplifier, and two DC/DC converters. Thus, the MAS 35x9F provides a true “all-in-one” solution that is ideally suited for highly optimized memory-based portable music players with integrated speech recording and playback function. Micronas June 30, 2004; 6251-505-1DS 5 MAS 35x9F 1.1. Features Firmware – MPEG 1/2 layer 2 and layer 3 decoder – Extension to MPEG 2 layer 3 for low sampling rates (“MPEG 2.5”) – Extraction of MPEG Ancillary Data – MPEG 2 AAC decoder (low-complexity profile) – Micronas G.729 Annex A speech compression and decompression – Master or slave clock operation – Adaptive bit rates (bit rate switching) – Intelligent power management (processor clock is dependent on sampling frequencies) – SDMI-compliant security technology – Stereo channel mixer – Bass, treble, and loudness function – Micronas Bass (MB) – Automatic Volume Control (AVC) Interfaces – Two serial asynchronous interfaces for bit streams and uncompressed digital audio – Parallel handshake bit stream input – Serial audio output via I2S and related formats – S/PDIF data input and output – Controlling via I2C interface Hardware Features DATA SHEET – Two independent embedded DC/DC converters, (e.g., for DSP and flash RAM supply) – Low DC/DC converter start-up voltage (0.9 V) – DC converter efficiency up to 95% – Battery voltage monitor – Low supply voltage down to 2.2 V – Low power dissipation, e.g., 87 mW (128kBit/s, 44.1 kHz, Headphone playback) – High-performance RISC DSP core – On-chip crystal oscillator – Hardware power management and power-off functions – Microphone amplifier – Stereo A/D converter for FM/AM-radio and speech input – CD quality stereo D/A converter – Headphone amplifier – Noise and power-optimized volume – External clock or crystal frequency of 13...28 MHz – Standby current < 10 µA 1.2. Features of the MAS 35x9F Family Feature Layer 3 Decoder G.729 Encoder/Decoder AAC Decoder 3509 X X X 3519 X X X 3529 X 3539 X X X 3549 3559 6 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 1.3. Application Overview The following block diagram shows an example application for the MAS 35x9F in a portable audio player device. Besides a simple controller and the external flash memories, all required components are integrated in the MAS 35x9F. The MAS 35x9F supports both speech and radio quality audio encoding, as well as compressed-audio decoding tasks. Fig. 1–1 depicts a portable power-optimized audio application. The two embedded DC/DC converters of the MAS 35x9F generate optimum power supply voltages for the DSP core and also for state-of-the art flash memories that typically require 2.7 to 3.3 V supply. The performance of the DC/DC converters reaches efficiencies of up to 95%. Portable Digital Music Player MAS 35x9F optional line in A/D Audio baseband features DSP Core D/A Microphone amplifier MP3 AAC G.729 Optional SC4 Downloads Headphone amplifier Volume Headphone optional digital in S/PDIF or serial digital out S/PDIF and serial Crystal Osc./PLL I2C Battery Voltage Monitor DC/DC1 DC/DC2 Parallel I/O Bus System clock I2C Control e.g. 1.0 V e.g. 2.2 V e.g. 3.0 V I 2C Display Keyboard µC PC Connector Fig. 1–1: Example of an application for the MAS 35x9F in a portable audio player device Micronas Flash RAM June 30, 2004; 6251-505-1DS 7 MAS 35x9F 2. Functional Description 2.1. Overview The MAS 35x9F is intended for use in portable consumer audio applications. It receives parallel or serial data streams and decodes MPEG Layer 2 and 3 (including the low sampling frequency extensions) and MPEG 2 AAC. A low bit-rate speech codec, compliant to the ITU Standard G.729 Annex A, is integrated. Additional downloadable software modules (SDMI, other audio/speech encoders/decoders) are available on request. 2.2. Architecture of the MAS 35x9F DATA SHEET The hardware of the MAS 35x9F consists of a highperformance RISC Digital Signal Processor (DSP), and appropriate interfaces. A hardware overview of the IC is shown in Fig. 2–1. 2.3. DSP Core The internal processor is a dedicated DSP for advanced audio applications. Mic. Input (incl. Bias) 1 Line Input 2 Audio Codec 2 A/D MIX Audio Proc. D/A 2 Audio Output DSP Core S/PDIF Input 1 S/PDIF Input 2 Serial Audio (I S, SDI) 2 ALU MAC Serial Audio (I2S, SDO) Accumulators ROM Output Select Input Select S/PDIF Output Control DCCF DCFR DSP Codec Serial Audio (stream, SDIB) VBAT Volt. Mon. D0 D1 IC Interface 2 I 2C control V1 DC/DC 2 DC/DC 1 Registers Div. Div. V2 Parallel I/O Bus (PIO) Xtal 18.432 MHz Osc. PLL Synth. Synthesizer Clock Scaler ÷2 CLKO Fig. 2–1: The MAS 35x9F architecture 8 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F selected, the Layer 2, Layer 3 or AAC bit stream is recognized and decoded automatically. To add/remove MPEG layers while running in MPEG decoding mode (e.g. Layer 2, Layer 3 (0x0c) to Layer 2, Layer 3, AAC (0x1c)), the application selection has to be reset before writing the new value. For general control purposes, the operation system provides a set of I2C instructions that give access to internal DSP registers and memory areas. An auxiliary digital volume control and mixer matrix is applied to the digital stereo audio data. This matrix is capable of performing the balance control and a simple kind of stereo basewidth enhancement. All four factors LL, LR, RL, and RR are adjustable, please refer to Fig. 3–3 on page 44. 2.3.2.2. Program Download Feature The standard functions of the MAS 35x9F can be extended or substituted by downloading up to 4 kWords (1 Word = 20 bits) of program code and additionally up to 4 kWords of coefficients into the internal RAM. 2.3.1. RAM and Registers The DSP core has access to two RAM banks denoted D0 and D1. All RAM addresses can be accessed in a 20-bit or a 16-bit mode via I2C bus. For fast access of internal DSP states the processor core has an address space of 256 data registers which also can be accessed via I2C bus. For more details, please refer to Section 3.3. on page 27. 2.3.2. Firmware and Software 2.3.2.1. Internal Program ROM and Firmware, MPEG-Decoding The firmware implemented in the program ROM of the MAS 35x9F provides MPEG 1/2 Layer 2, MPEG 1/2/ 2.5 Layer 3 and MPEG 2 AAC-decoding as well as a G.729 encoder and decoder. The DSP operating system starts the firmware in the “Application Selection Mode”. By setting the appropriate bit in the Application Select memory cell (see Table 3–8 on page 32), the MPEG audio decoder or the G.729 Codec can be activated. The MPEG decoder provides an automatic standard detection mode. If all MPEG audio decoders are SDI Encoder PIO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2–2: Encoder signal flow PIO Decoder SDIB DSP Volume Matrix S/PDIF SDO LINE IN MIC IN A/D MIX Audio Proc. D/A OUT Fig. 2–3: Decoder signal flow Micronas June 30, 2004; 6251-505-1DS 9 MAS 35x9F 2.4. Audio Codec A sophisticated set of audio converters and sound features has been implemented to comply with various kinds of operating environments that range up to highend equipment (see Fig. 2–4). 2.4.2.2. Micronas Bass (MB) DATA SHEET Mic-In Mic-Amplifier incl. Bias Deemphasis 50µs / 75µs Line-In A D D Q-peak Mixer Mono/Stereo Q-peak AVC Bass/Treble Headphone Amplifier DSP A Mono The Micronas Bass system (MB) was developed to extend the frequency range of loudspeakers or headphones below the cutoff frequency of the speakers. Apart from dynamically amplifying the low-frequency bass signals, the MB exploits the psycho-acoustic phenomenon of the ‘missing fundamental’. Adding harmonics of the frequency components below the cutoff frequency gives the impression of actually hearing the low frequency fundamental, while at the same time retaining the loudness of the original signal. Due to the parametric implementation of the MB, it can be customized to create different bass effects and adapted to various loudspeaker characteristics (see Section 3.4.4. and Table 3–16). 2.4.2.3. Automatic Volume Control (AVC) In a collection of tracks from different sources fairly often the average volume level varies. Especially in a noisy listening environment the user must adjust the volume to comfortably enjoy listening. The Automatic Volume Correction (AVC) solves this problem by equalizing the volume level. To prevent clipping, the AVC's gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see Table 3–16 on page 46). For input levels of -18 dBr to 0 dBr, the AVC maintains a fixed output level of -9 dBr. Fig. 2–5 shows the AVC output level versus its input level. For volume and baseband registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. Audio Codec D A D A Volume Balance Loudness MB Right invert Output Fig. 2–4: Signal flow block diagram of Audio Codec 2.4.1. A/D Converter and Microphone Amplifier A pair of A/D converters is provided for recording or loop-through purposes. In addition, a microphone amplifier including voltage supply function for an electret type microphone has been integrated. 2.4.2. Baseband Processing The several baseband functions are applied to the digital audio signal immediately before D/A conversion. 2.4.2.1. Bass, Treble, and Loudness Standard baseband functions such as bass, treble, and loudness are provided (refer to Table 3–16 for details). output level dBr −9 −15 −21 AVCoff AVCon −30 −24 −18 −12 −6 0 +6 input level dBr Fig. 2–5: Simplified AVC characteristics 2.4.2.4. Balance and Volume To minimize quantization noise, the main volume control is automatically split into a digital and an analog part. The volume range is −114...+12 dB with an additional mute position. A balance function is provided. 10 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.5.1. DSP Clock The DSP clock has a separate divider. In order to reduce the power consumption, it is set to the lowest acceptable rate of the synthesizer clock which is capable to allow the processor core to perform all tasks. 2.5.2. Clock Output At CLKO If the DSP or audio codec functions are enabled (bits[11] or [10] in the Control Register at I2C subaddress 6Ahex), the reference clock at pin CLKO is derived from the synthesizer clock. Dependent on the sample rate of the decoded signal a scaler is applied which automatically divides the clockout by 1, 2, or 4, as shown in Table 2–1. An additional division by 2 may be selected by setting bit[17] of the OutClkConfig memory cell (see Table 3–8 on page 32). The scaler can be disabled by setting bit[8] of this cell. The controlling at OutClkConfig is only possible as long as the DSP is operational (bit[10] of the Control Register). Settings remain valid if the DSP is disabled by clearing bit[10]. R ≥ 32 Ω Table 2–1: Settings of bits[8] and [17] in OutClkConfig and resulting CLKO output frequencies Output Frequency at CLKO/MHz Synth. Scaler On Scaler Plus Clock bit[8]=0, bit[17]=0 Extra Division bit[8]=1 bit[8]=0, bit[17]=1 24.576 22.5792 24.576 24 22.05 16 24.576 12 11.025 8 22.5792 24.576 768⋅fs 22.5792 768⋅fs 512⋅fs 768⋅fs 512⋅fs 512⋅fs 24.576 22.5792 24.576 12.288 11.2896 12.288 6.144 5.6448 6.144 384⋅fs 384⋅fs 256⋅fs 384⋅fs 256⋅fs 256⋅fs 12.288 11.2896 12.288 6.144 5.6448 6.144 3.072 2.8224 3.072 2.4.3. D/A Converters One pair of Micronas’ unique multibit sigma-delta D/A converters is used to convert the audio data with high linearity and a superior S/N. In order to attenuate highfrequency noise caused by noise-shaping, internal low-pass filters are included. They require additional external capacitors between pins FILTx and OUTx (see Section 5.1. on page 89). 2.4.4. Output Amplifiers The integrated output amplifiers are capable of directly driving stereo headphones or loudspeakers of 16 to 32 Ω impedance via 22 Ω series resistors. If more output power is required, the right output signal can be inverted and a single loudspeaker can be connected as a bridge between pins OUTL and OUTR. In this case, the source should be set to mono for optimized power. MASF DAC DAC OUTL OUTR Fig. 2–6: Bridge operation mode 2.5. Clock Management The MAS 35x9F is driven by a single crystal-controlled clock with a frequency of 18.432 MHz. It is possible to drive the MAS 35x9F with other reference clocks. In this case, the nominal crystal frequency must be written into memory location D0:348. The crystal clock acts as a reference for the embedded synthesizer that generates the internal clock. For compressed audio data reception, the MAS 35x9F may act either as the clock master (Demand Mode) or as a slave (Broadcast Mode) as defined by bit[1] in IOControlMain memory cell (see Table 3–8 on page 32). In both modes, the output of the clock synthesizer depends on the sample rate of the decoded data stream as shown in Table 2–1. In the BROADCAST MODE (PLL on), the incoming audio data controls the clock synthesizer via a PLL. In the DEMAND MODE (PLL off) the MAS 35x9F acts as the system master clock. The data transfer is triggered by a demand signal at pin EOD. fs/kHz 48 44.1 32 Micronas June 30, 2004; 6251-505-1DS 11 MAS 35x9F 2.6. Power Supply Concept The MAS 35x9F was designed for minimal power dissipation. In order to optimize the battery management in portable players, two DC/DC converters were implemented to supply the complete portable audio player with regulated voltages. 2.6.1. Power Supply Regions The MAS 35x9F has five power supply regions. The VDD/VSS pin pair supplies all digital parts including the DSP core, the XVDD/XVSS pin pair is connected to the digital signal pin output buffers, the AVDD0/AVSS0 supply is for the analog output amplifiers, AVDD1/AVSS1 for all other analog circuits like clock oscillator, PLL circuits, system clock synthesizer and A/D and D/A converters. The I2C interface has an own supply region via pin I2CVDD. Connecting this to the microcontroller supply assures that the I2C bus always works as long as the microcontroller is alive so that the operating modes can be selected. Beside these regions, the DC/DC converters have start-up circuits of their own which get their power via pin VSENSx. 2.6.2. DC/DC Converters The MAS 35x9F has two embedded high-performance step-up DC/DC converters with synchronous rectifiers to supply both the DSP core itself and external circuitry such as a controller or flash memory at two different voltage levels. An overview is given in Fig. 2–7 on page 13. The DC/DC converters are designed to generate an output voltage between 2.0 V and 3.5 V which can be programmed separately for each converter via the I2C interface (see table 3.3). Both converters are of bootstrapped type allowing to start up from a voltage down to 0.9 V for use with a single battery or NiCd/NiMH cell. The default output voltages are 3.0 V. Both converters are enabled with a high level at pin DCEN and enabled/disabled by the I2C interface. The MAS 35x9F DC/DC converters feature a constantfrequency, low noise pulse width modulation (PWM) mode and a low quiescent current, pulse frequency modulation (PFM) mode for improved efficiencies at low current loads. Both modes – PWM or PFM – can be selected independently for each converter via I2C interface. The default mode is PWM. In PWM mode the switching frequency of the powerMOSFET-switches is derived from the crystal oscillator. Switching harmonics generated by constant frequency operation are consistent and predictable. DATA SHEET When the audio codec is enabled, the switching frequency of the converters is synchronised to the audio codec clock to avoid interferences into the audio band. The actual switching frequency can be selected via the I2C-interface between 300 kHz and 580 kHz (for details see DCFR Register in Table 3–3 on page 24). In the PFM operation mode, the switching frequency is controlled by the converters themselves. It will be just high enough to service the output load, thus resulting in the best possible efficiency at low current loads. The PFM mode does not need a clock signal from the crystal oscillator. If both converters do not use the PWMmode, the crystal clock will be shut down as long it is not needed by other internal blocks. The synchronous rectifier bypasses the external Schottky diode to reduce losses caused by the diode forward voltage providing up to 5% efficiency improvement. By default, the P-channel synchronous rectifier switch is turned on when the voltage at pin(s) DCSOn exceeds the converter’s output voltage at pin(s) VSENSn, and is turned off when the inductor current drops below a threshold. If one or both converters are disabled, the corresponding P-channel switch will be turned on, connecting the battery voltage to the DC/ DC converters output voltage at pin VSENSn. However, it is possible to individually disable both synchronous rectifier switches by setting the corresponding bits (bit[8] and [0] in DCCF-register). If both DC/DC-converters are off, a high signal may be applied at pin DCEN. This will start the converters in their default mode (PWM with 3.0 V output voltage). The PUP signal will change from low to high when both converters have reached their nominal output voltage and will return to low when both converters output voltages have dropped 200 mV below their programmed output voltage. The signal at pin PUP can be used to control the reset of an external microcontroller (see Section 2.11.2. on page 18 for details on the startup procedure). If only DC/DC-converter 1 is used, the output of the unused converter 2 (VSENS2) must be connected to the output of converter 1 (VSENS1) to make the PUP signal work properly. Also, if a DC/DC-converter is not used (no inductor connected), the pin DCSO must be left vacant. 12 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F If DC/DC converter 1 is used, it must supply the analog circuits (pins AVDD0, AVDD1) of the MAS 35x9F. If only one DC/DC converter is required, DC/DC1 must be used. Pin DCSO2 must be left vacant, pin VSENS2 should be connected to pin VSENS1. If the DC/DC converters are not used, pin DCEN must be connected to VSS, DCSOx must be left vacant. 2.6.3. Power Supply Configurations One of the following supply configurations may be used: – Power-optimized solution (recommended operation). DC/DC 1 (e.g. 2.2 V) drives the MAS 35x9F DSP and the audio circuitry, DC/DC 2 (e.g. 2.7 V) supplies controller and flash (see Fig. 2–8 on page 14) – Volume-optimized solution. DC/DC 1 (e.g. 2.7 V) supplies controller, flash and MAS 35x9F audio parts, DC/DC 2 generates e.g. 2.2 V for the MAS 35x9F DSP (see Fig. 2–9 on page 14). – Minimized external components. DC/DC 1 operates on, e.g., 2.7 V and feeds all components, DC/DC 2 remains off (see Fig. 2–10 on page 14). – External power supply. All components are powered by an external source, no DC/DC converter is used (see Fig. 2–11 on page 14). battery voltage monitor to I2C interface DCCF (76hex) 15 8 VBAT supply output 1 DCSO2 L1 22 µH I2CVDD DC/DC converter 2 DCSG2 D1 VSENS2 + − C1 330 µF set voltage PUP2 voltage monitor DCEN S PUP Start + − + − Vin system or crystal clock frequency divider factor 0 R 3 voltage monitor DCFR (77hex) DCCF (76hex) 7 0 DC/DC converter 1 VSS Fig. 2–7: DC/DC converter overview. The DCEN input must be connected to pin I2CVDD via start-up push button. Micronas June 30, 2004; 6251-505-1DS 13 MAS 35x9F DATA SHEET Flash VSENS1 DC/DC 1 on Flash e.g. 2.7 V VSENS1 DC/DC1 on µC I2CVDD I 2C DSP µC I2CVDD I 2C DSP XVDD VDD VSENS2 XVDD VDD VSENS2 DC/DC 2 on DC/DC2 off AVDD0/1 e.g. 2.7 V e.g. 2.2 V Analog Parts AVDD0/1 Analog Parts Fig. 2–8: Solution 1: Power-optimized Fig. 2–10: Solution 3: Minimized components Flash VSENS1 DC/DC1 on Flash VSENS1 DC/DC1 off µC I2CVDD I2C DSP µC I2CVDD I2C DSP XVDD VDD VSENS2 XVDD VDD DC/DC2 on VSENS2 DC/DC2 off External Supply AVDD0/1 e.g. 2.7 V e.g. 2.2 V Analog Parts AVDD0/1 e.g. 2.7 V Analog Parts Fig. 2–9: Solution 2: Volume-optimized Fig. 2–11: Solution 4: External power supply 14 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.8.4. Multiline Serial Audio Input (SDI, SDIB) There are two multiline serial audio input interfaces (SDI, SDIB) each consisting of the three pins SI(B)C, SI(B)I, and SI(B)D. The standard firmware only supports SDIB for bit-stream signals, while PCM-inputs should be routed to SDI. The interfaces can be configured as continuous bitstream or word-oriented inputs. For the MPEG bit streams, the word strobe pin SIBI must always be connected to VSS; bits must be sent MSB first as created by the encoder. If the download software (refer to Download Software Supplement I2SPDIF (6251-505-1PDS)) is used, the interface acts as an I2S-type with SI(B)I as a wordstrobe for PCM data. For the Demand Mode (see Section 2.5.), the signal clock coming from the data source must be higher than the nominal data transmission rate (e.g. 128 kbit/s). Pin EOD is used to interrupt the data flow whenever the input buffer of the MAS 35x9F is filled. For controlling details, please refer to Table 3–8 on page 32. 2.8.5. Multiline Serial Output (SDO) The serial audio output interface of the MAS 35x9F is a standard I2S-like interface consisting of the data lines SOD, the word strobe SOI and the clock signal SOC. It is possible to choose between two standard interface configurations (16-bit data words with word strobe time offset or 32-bit data words with inverted SOI signal). If the serial output generates 32 bits per audio sample, only the first 20 bits will carry valid audio data. The 12 trailing bits are set to zero by default. 2.8.6. Parallel Input/Output Interface (PIO) The parallel interface of the MAS 35x9F consists of the 8 data lines PI12...PI19 (MSB) and the control lines PCS, PR, PRTR, PRTW, and EOD. It can be used for data exchange with an external memory, for fast program download and for other special purposes as defined by the DSP software. For MPEG data input, the PIO interface is activated by setting bits[9] and [8] in D0:346 to 01. For the handshake protocol, please refer to Section 4.6.2.8. on page 80. 2.7. Battery Voltage Supervision Independent of the DC/DC converters, a battery voltage supervision circuit (at pin VBAT) is provided. It can be programmed to supervise one or two battery cells. The voltage is measured by subsequently setting a series of voltage thresholds and checking the respective comparison result in register 77hex. 2.8. Interfaces The MAS 35x9F uses an I2C control interface, a serial input interface for MPEG bit streams, and digital audio output interfaces for the decoded audio data (I2S and S/PDIF). S/PDIF input is available after Software download. A parallel I/O interface (PIO) may be used for fast data exchange. 2.8.1. I2C Control Interface For controlling and program download purposes, a standard I2C slave interface is implemented. A detailed description of all functions can be found in Section 3. 2.8.2. S/PDIF Input Interface The S/PDIF interface receives a one-wire serial bus signal. In addition to the signal input pin SPDI1/SPDI2, a reference pin SPDIR is provided to support balanced signal sources or twisted pair transmission lines. The synchronization time on the input signal is < 50 ms. S/PDIF input is not supported for MPEG 1/2 Layer 2/3 and MPEG 2 AAC. Micronas has developed a download software for flexible usage of the S/PDIF I/O and SDI/SDO interfaces. It is described in Download Software Supplement I2SPDIF (6251-505-1PDS). 2.8.3. S/PDIF Output The S/PDIF output of the baseband audio signals is implemented at pin SPDO since version B4. The channel status bits can be set as described in Table 3–8. Micronas June 30, 2004; 6251-505-1DS 15 MAS 35x9F 2.9. MPEG Synchronization Output The signal at pin SYNC is set to ‘1’ after the internal decoding for the MPEG header has been finished for one frame. The rising edge of this signal can be used as an interrupt input for the controller that triggers the read out of the control information and ancillary data. As soon as the MAS 35x9F has received the SYNC reset command (see Section 4.6.2.6. on page 77), the SYNC signal is cleared. If the controller does not issue a reset command, the SYNC signal returns to ‘0’ as soon as the decoding of the next MPEG frame is started. MPEG status and ancillary data become invalid until the frame is completely decoded and the signal at pin SYNC rises again. The controller must have finished reading all MPEG information before it becomes invalid. The MPEG Layer 2/3 frame lengths are given in Table 2–2. AAC has no fixed frame length. DATA SHEET tframe = 24...72 ms Vh Vl tread Fig. 2–12: Schematic timing of the signal at pin SYNC. The signal is cleared at tread when the controller has issued a Clear SYNC Signal command (see Section 4.6.2.6. on page 77). If no command is issued, the signal returns to ‘0’ just before the decoding of the next MPEG frame. Table 2–2: Frame length in MPEG Layer 2/3 fs/kHz 48 44.1 32 24 22.05 16 12 11.025 8 Frame Length Layer 2 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms not available not available not available Frame Length Layer 3 24 ms 26.12 ms 36 ms 24 ms 26.12 ms 36 ms 48 ms 52.24 ms 72 ms 16 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.10.MP3 Block Input Mode A new so-called MP3 block input mode is now available which improves the input timing behavior of the MAS 35x9F MPEG 1/2/2.5 Layer 3 decoder. The following sections provide a detailed description of this new mode. 2.10.1.Functional Description of the MP3 Block Input Mode In MP3 block input, the MAS 35x9F generates a demand for new input data each time one of its two input buffers becomes available. The controller then has to send one block of input data via the serial interface SDIB. The block size is 2048 byte. The demand is signalized via a pulse on the EOD pin. Fig. 2–13 shows that the number of interrupts per second does not depend on the data rate at the serial interface. The maximum input data bit clock rate supported by the MAS 35x9F for all MPEG audio sampling rates is 1.4 MHz. Table 2–3 shows the average number of interrupts per second for several typical MP3 bit rates. The time period between two interrupts may vary slightly even for fixed bit rate input streams due to the MP3 specific bit reservoir. Table 2–3: MP3 bit rate vs. number of interrupts Bit Rate [kbit/s] 320 256 224 192 160 128 112 96 80 64 Number of Interrupts [1/s] 20 16 14 12 10 8 7 6 5 4 Interrupt a) SIC Interrupt b) SIC Data blocks in a) and b) contain the same number of bytes. Data block a) is sent with a lower data rate than data block b). t Fig. 2–13: Data Block Timing Diagram Micronas June 30, 2004; 6251-505-1DS 17 MAS 35x9F 2.10.2.Setup Table 3–10 on page 39 lists the new bits, UIC cells, and registers to setup the MP3 block input mode. 2.10.2.1.Resync Timeout In case the MP3 decoder loses the synchronization (e.g. due to corrupted input data), the output is softly muted and a resync loop is entered where the MAS 35x9F can be accessed via I2C. The loop is left and the re-synchronization procedure continues in any of the following cases: – the last input data block is fully sent, – the Validate bit of IOControlMain is set (D0:346, bit[0]), – the timeout is reached (ResyncTimeout in Table 3–10), the end bit is set (this bit will be reset by the MAS 35x9F). 2.10.2.2.Detailed Setup After the MPEG audio decoder application has been selected, the following settings enable the MP3 block decoding process. Play MP3 1. Write 0x318 into SerialInConfig. 2. Write IOControlMain with bit[2] and bit[0] equal one. 3. Write IOControlMain with bit[2] equals zero and bit[0] equals one. 4. Write 0x0 into ResyncTimeout. 5. Write 0x0 into SoftMute. 6. Enable EODQ interrupt for sending data in controller. 7. Set StartBit in MP3BlockConfig. 8. Send data block of 2048 byte when EODQ goes high. Stop/Pause MP3 1. Write 0x1 into SoftMute. 2. Clear start bit in MP3BlockConfig. 2.11.Default Operation DATA SHEET This sections refers to the standard operation mode “power-optimized solution” (see Section 2.6.3.). 2.11.1. Stand-by Functions After applying the battery voltage, the system will remain stand-by, as long as the DCEN pin level is kept low. Due to the low stand-by current of CMOS circuits, the battery may remain connected to DCSOn/VSENSn at all times. 2.11.2.Power-Up of the DC/DC Converters and Reset The battery voltage must be applied to pin DCSOn via the 22 µH inductor and, furthermore, to the sense pin VSENSn via a Schottky diode (see Fig. 2–7 on page 13). For start-up, the pin DCEN must be connected via an external “start” push button to the I2CVDD supply, which is equivalent to the battery supply voltage (> 0.9 V) at start-up. The supply at DCEN must be applied until the DC/DC converters have started up (signal at pin PUP) and then removed for normal operation. As soon as the output voltage at VSENSn reaches the default voltage monitor reset level of 3.0 V, the respective internal PUPn bit will be set. When both PUPn bits are set, the signal at pin PUP will go high and can be used to start and reset the microcontroller. Before transmitting any I2C commands, the controller must issue a power-on reset to pin POR. The separate supply pin I2CVDD ensures that the I2C interface works independently from the DSP or the audio codec. Now the desired supply voltage can be programmed at I2C subaddress 76hex. 18 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.11.2.1.Important Advice for Turn-on and Operating Voltage Before the 2.2 V are programmed at the DCDC converter, DSP+Codec must be enabled. Operating and Turn-Off is possible down to 2.2 V. The sequence should be similar to the following: 1. Start DCDC 2. Set DCDC to 2.5 V Turn on DSP+Codec Write App-Select memory cell Read App-Running Mem cell If okay: Set DCDC to 2.2 V Set other mem cells Set other codec registers ..... 3. Demute...send data 4. Mute...stop data.....loop "3)" "4)"... 5. Turn off DSP+Codec goto "2)" etc..... The signal at pin PUP will return to low only when both PUPn flags (I2C subaddress 76hex) have returned to zero. Care must be taken when changing both DC/DC output voltages to higher values. In this case, both output voltages are momentarily insufficient to keep the PUPn flags up; the resulting dip in the signal at the PUP pin may, in turn, reset the microcontroller. To avoid this condition, only one DC/DC output voltage should be changed at a time. Before modifying the second voltage, the microcontroller must wait for the PUPn flag of the first voltage to be set again. If only DC/DC converter 1 is used, the reference voltage of the second, unused converter should be set to a lower value than that of converter 1, and its pin VSENS2 should be connected to VDD. The operating mode pulse width modulation, or pulse frequency modulation, are controlled at I2C subaddress 76hex, the operating frequency at I2C subaddress 77hex. Micronas June 30, 2004; 6251-505-1DS 19 MAS 35x9F 2.11.3. Reset Signal Specification After power-up, a reset signal should be applied to the pin POR by the microcontroller as follows: DATA SHEET VDD 2.2 V min. VDD POR 2.2 V min. POR see Note 1 0.5 µs min. delay I2C access works without additional delay from this point time Fig. 2–14: Reset signal at pin POR Note: The slew rate of POR should be as high as possible, but must be glitch-free in any case. Slew rate typ.: 1 µs for 10% to 90% level transition, Slew rate max.: 20 µs for 10% to 90% level transition. 20 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F 2.11.5.Start-up of the Audio Codec Before enabling the audio codec, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The audio codec is enabled by setting the appropriate bit at the Control register (I2C subaddress 6Ahex). After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. The A/D and the D/A converters must be switched on explicitly (register 00 00hex at I2C subaddress 6Chex). The D/A converters may either accept data from the A/D converters or the output of the DSP, or a mix of both1) (register 00 06hex and 00 07hex at I2C subaddress 6Chex). Finally, an appropriate output volume (register 00 10hex at I2C subaddress 6Chex) must be selected. 2.11.6.Power-Down All analog outputs should be muted and the A/D and the D/A converters must be switched off (register 00 10hex and 00 00hex at I2C subaddress 6Chex). The DSP and the audio codec must be disabled (clear DSP_EN and CODEC_EN bits in the Control register, I2C subaddress 6Ahex). By clearing both DC/DC enable flags in the Control register (I2C subaddress 6Ahex), the microcontroller can power down the complete system. 2.11.4.Control of the Signal Processing Before starting the DSP, the controller should check for a sufficient voltage supply (respective flag PUPn at I2C subaddress 76hex). The DSP is enabled by setting the appropriate bit in the Control register (I2C subaddress 6Ahex). The nominal frequency of the crystal oscillator must be written into D0:348. After an initialization phase of 5 ms, the DSP data registers can be accessed via I2C. Input and output control is performed via memory location D0:346 and D0:347. The serial input interface SDIB is the default. The decoded audio can be routed to either the S/PDIF, the SDO and the analog outputs. The output clock signal at pin CLKO is defined in D0:349. All changes in the D0 memory cells become effective synchronously upon setting the LSB of Main I/O Control (see Table 3–8 on page 32). Therefore, this cell should always be written last. The digital volume control (see Table 3–8 on page 32) is applied to the output signal of the DSP. The decoded audio data will be available at the SPDO output interface in the next version. The DSP does not have to be started if its functions are not required, e.g., for routing audio through the codec part of the IC via the A/D and the D/A converters. 1) mixer available in version A2 and later; in version A1, please use selector 00 0Fhex. Micronas 21 June 30, 2004; 6251-505-1DS MAS 35x9F 3. Controlling 3.1. I2C Interface Controlling between the MAS 35x9F and the external controller is done via an I2C slave interface. 3.1.1. Device Address The device addresses are 3C/3Ehex (device write “DW”) and 3D/3Fhex (device read, “DR”) as shown in Table 3–1. The device address pair 3C/3Dhex applies if the DVS pin is connected to VSS, the device address pair 3E/3Fhex applies if the DVS pin is connected to I2CVDD. Table 3–1: I2C device address A7 0 A6 0 A5 1 A4 1 A3 1 A2 1 A1 DVS W/R 0/1 nibble. DATA SHEET – Data values in nibbles are always shown in hexadecimal notation. – A hexadecimal 20-bit number d is written, e.g. as d = 17C63hex, its five nibbles are d0 = 3hex, d1 = 6hex, d2 = Chex, d3 = 7hex, and d4 = 1hex. – Variables used in the following descriptions: I²C address: DW3C/3EhexI2C device write DR3D/3FhexI2C device read DSP core: data_write68hexDSP data write data_read69hexDSP data read Codec: codec_write6Chexcodec write codec_read6Dhexcodec read – Bus signals S Start P Stop A ACK = N NAK = W Wait = I2C clock synchronization is used to slow down the interface if required. 3.1.2. I2C Registers and Subaddresses The interface uses one level of subaddresses. The MAS 35x9F interface has 7 subaddresses allocated for the corresponding I2C registers. The registers can be divided into three categories as shown in Table 3– 2. The address 6Ahex is used for basic control, i.e. reset and task select. The other addresses are used for data transfer from/to the MAS 35x9F. The I2C registers of the MAS 35x9F are 16 bits wide, the MSB is denoted as bit[15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, MSB sent first); thus, for each register access, two 8-bit data words must be sent/received via I2C bus. 3.1.3. Naming Convention The description of the various controller commands uses the following formalism: – Abbreviations used in the following descriptions: a address d data value n count value o offset value r register number x don’t care – Memory addresses, like D1:89f, are always in hexadecimal notation. – A data value is split into 4-bit nibbles which are numbered beginning with 0 for the least significant Acknowledge Not acknowledge I2C clock line is held low while the MAS 35x9F is processing the current I2C command – Symbols in the telegram examples < Start Condition > Stop dd data bytes xx ignore All telegram numbers are hexadecimal, data originating from the MAS 35x9F are represented as gray letters. Example: write data to DSP 2.4 V >3.0 V VSUPA >2.0 V >2.4 V >3.0 V bits[15], [14] in register 6Ahex 00 01 10 bits[15], [14] in register 6Ahex 00 01 10 at minimum analog input gain, i.e. −3 dB at maximum analog input gain, i.e. +19.5 dB not selected at minimum analog input gain, i.e. −21 dB at maximum analog input gain, i.e. +43.5 dB not selected BW = 20 Hz...20 kHz, analog gain = 0 dB, input 1 kHz at VAI−20 dB BW = 20 Hz...20 kHz, analog gain = +21 dB, input 1 kHz at VMI−20 dB BW = 20 Hz...20 kHz, analog gain = 0 dB, resp. 24 dB, input 1 kHz at −3 dBFS = VAI−6 dB resp. VMI−6 dB f = 1 kHz, sine wave, analog gain = 0 dB, input = −3 dBFS 1 kHz sine at 100 mVrms ≤100 kHz sine at 100 mVrms SNRMI MICIN 73 dB(A) THDAI INL/R MICIN 0.01 0.02 % XTALKAI Crosstalk attenuation left/right channel (analog inputs) Power supply rejection ratio for analog audio inputs INL/R MICIN AVDD0/1, INL/R MICIN 80 dB PSRRAI 45 20 dB dB 82 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Symbol Parameter Pin Name Min. Limit Values Typ. Max. Unit Test Conditions Audio Output VAO1 Analog output voltage AC OUTL/R RL ≥1 kΩ input = 0 dBFS digital VSUPA at 0 dB output gain 1.56 1.84 2.27 at +3 dB output gain 2.20 2.60 3.20 dVAO1 Deviation of DC-level at analog output for AGNDCVoltage Analog output voltage AC OUTL/R −20 20 mV Vpp Vpp >2.2 V >2.4 V >3.0 V >2.2 V >2.6 V >3.2 V bits[15], [14] in register 6Ahex 00 01 10 00 01 10 VAO2 OUTL/R RLis 16 Ω headphone and 22 Ω series resistor Input = 0 dBFS digital (see Fig. 5–1 on page 89) VSUPA bits[15], [14] in register 6Ahex 00 01 10 00 01 10 at 0 dB output gain 1.56 1.84 2.27 Vpp >2.2 V >2.4 V >3.0 V at +3 dB output gain 2.00 2.40 3.00 Vpp >2.2 V >2.6 V >3.2 V RoutAO SNRAO Analog output resistance Signal-to-noise ratio of analog output OUTL/R OUTL/R 94 6 Ω dB(A) analog gain = +3 dB, input = 0 dBFS digital RL≥16 Ω BW = 20 Hz...20 kHz, analog gain = 0 dB input = −20 dBFS for RL≥16 Ω plus 22 Ω series resistor (see Fig. 5–1 on page 89) for RL≥1 kΩ THDAO Total harmonic distortion (headphone) OUTL/R 0.03 0.05 % 0.003 LevMuteAO Mute level OUTL/R −113 0.01 dBV A-weighted BW = 20 Hz...22 kHz, no digital input signal, analog gain = mute Micronas June 30, 2004; 6251-505-1DS 83 MAS 35x9F DATA SHEET Symbol Parameter Pin Name Min. Limit Values Typ. 80 Max. Unit Test Conditions XTALKAO Crosstalk attenuation left/right channel (headphone) OUTLR dB f = 1 kHz, sine wave, OUTL/R: RL≥16 Ω (see Fig. 5–1 on page 89) analog gain = 0 dB input = −3 dBFS PSRRAO Power supply rejection ratio for analog audio outputs AVDD0/1 OUTL/R 70 35 dB dB 1 kHz sine at 100 mVrms ≤100 kHz sine at 100 mVrms 4.6.4. DC/DC Converter Characteristics at T = TA, Vin = 1.2 V, Voutn = 3.0 V, fclk = 18.432 MHz, fsw = 384 kHz, PWM mode, L = 22 µH, in P(L/M)QFP package (unless otherwise noted) Typ. values for TA = 25 °C Symbol Parameter Pin Name Min. VIN VIN Minimum start-up input voltage Minimum operating input voltage DC1 DC2 DC1 DC2 VOUT Programmable output voltage range Output voltage tolerance Output current 1 battery cell Output current 2 battery cells Line regulation Load regulation Maximum efficiency Switching frequency Switching frequency during start-up DCSOn DCSOn 297 384 250 VSENSn VSENSn 0.7 −1.8 95 576 VSENSn 2.0 0.7 0.8 1.1 1.2 3.5 V V V Limit Values Typ. 0.9 Max. V ILOAD ≤ 1 mA, DCCF = 5050hex (reset) 1) Unit Test Conditions ILOAD = 50 mA, DCCF = 5050hex (reset) ILOAD = 200 mA, DCCF = 5050hex (reset) Voltage settings in DCCF register (I2C subaddress 76hex) ILOAD = 20 mA TA = 25 °C2) VIN = 0.9...1.5 V, 330 µF VIN = 1.8...3.0 V, 330 µF ILOAD = 20 mA ILOAD = 20...200 mA, VIN = 2.4 V, VOUT = 3.5 V (see Section 2.6.2. on page 12), (see Table 3–3) VSENSn < 1.9 V VOTOL ILOAD1 ILOAD2 dVOUT/ dVIN/VOUT dVOUT/ VOUT hmax fswitch fstartup VSENSn VSENSn −4 4 200 600 % mA mA %/V % % kHz kHz 1) Since the regulators are bootstrapped, once 2) PFM mode regulates approx. 1% higher started they will operate down to 0.7 V input voltage 84 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Symbol Parameter Pin Name Min. Limit Values Typ. 75 135 265 325 1 0.4 Max. Unit Test Conditions IsupPFM1 IsupPFM2 IsupPWM1 IsupPWM2 Ilnmax Supply current in PFM mode VSENS1 VSENS2 µA 3) Supply current in PWM mode VSENS1 VSENS2 µA 3) 4) VSENSn NMOS switch current limit (low side switch) PMOS switch turnoff current (rectifier switch) NMOS switch on Resistance (low side switch) DCSOn, DCSGn DCSOn VSENSn DCSO1, DCSG1 DCSO2, DCSG2 A A mA mΩ mΩ µA PWM-Mode PFM-Mode IIptoff Ron 70 170 280 0.1 ILEAK 3) 4) Leakage current DCSOn, DCSGn Converter off, no load Current into VSENSn Pin. VIN > VOUT + 0.4V; no DC/DC-Converter switching action present Add. current of oscillator at PIN AVDD0/1, (see Section 4.6.3. on page 81) Micronas June 30, 2004; 6251-505-1DS 85 MAS 35x9F 4.6.5. Typical Performance Characteristics DATA SHEET Efficiency vs. Load Current DCDC1 (VOUT = 3.5 V) 100 3.0 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.5 V) 3.0 V 80 Efficiency (%) 1.8 V Efficiency (%) 80 1.8 V 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 60 VIN: 3.0 V 2.4 V 1.8 V PFM PWM 40 40 20 20 0 10−4 10 −3 10 −2 10 −1 1 0 10−4 10−3 10−2 10−1 1 Load Current (A) Load Current (A) Efficiency vs. Load Current DCDC1 (VOUT = 3.0 V) 100 2.4 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 3.0 V) 2.4 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 2.4 V 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 10−3 10−2 10−1 0 10−4 10 −3 10 −2 10 −1 1 0 10−4 1 Load Current (A) Fig. 4–31: Efficiency vs. Load Current Load Current (A) 86 June 30, 2004; 6251-505-1DS Micronas DATA SHEET MAS 35x9F Efficiency vs. Load Current DCDC1 (VOUT = 2.2 V) 100 1.5 V 100 Efficiency vs. Load Current DCDC2 (VOUT = 2.2 V) 1.5 V 80 Efficiency (%) Efficiency (%) 80 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 60 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 40 40 20 PFM PWM 20 PFM PWM 0 10−4 10 −3 10 −2 10 −1 1 0 10−4 10−3 10−2 10−1 1 Load Current (A) Load Current (A) Maximum Load Current vs. Input Voltage 0.8 DCDC1 Vout: 2.2 V 3.0 V 3.5 V PFM PWM 0.8 Maximum Load Current vs. Input Voltage DCDC2 Maximum Load Current (A) Vout: 2.2 V 3.0 V 3.5 V PFM 0.4 PWM Maximum Load Current (A) 0.6 0.6 0.4 0.2 0.2 0 0.0 1.0 2.0 3.0 Input Voltage (V) Fig. 4–32: Maximum Load Current vs. Input Voltag Note: Efficiency is measured as VSENSn × ILOAD / (Vin × Iin). IAVDD is not included (Oscillator current) 0 0.0 1.0 2.0 3.0 Input Voltage (V) Micronas June 30, 2004; 6251-505-1DS 87 MAS 35x9F DATA SHEET Loadregulation at VOUT = 2.7 V, 2.5 V 2.75 2.7 Output Voltage (V) 2.65 2.6 2.55 2.5 2.45 DCDC1 2.4 0 50 100 150 200 Load Current (mA) 2.9 0 VIN: 1.5 V 1.2 V 0.9 V 0.9 V 3.55 3.5 Output Voltage (V) 3.45 3.4 3.05 3.0 2.95 Loadregulation at VOUT = 3.0 V, 3.5 V 1.5 V 1.5 V VIN: 1.5 V 1.2 V 0.9 V 0.9 V DCDC1 50 100 150 200 Load Current (mA) No-Load Battery Current VOUT = 3.0 V 10 Both DCDC running in PWM One DCDC running in PFM Battery Current (mA) 8 6 4 2 0 0.5 1.0 1.5 2.0 2.5 3.0 Input Voltage (V) 88 June 30, 2004; 6251-505-1DS Micronas VDC2 VDC2 Micronas Serial memory device Parallel memory device e.g. SmartMediaCard 3 MPEG, CELP, SC4 8 Reference clock VDC2 D e.g. SDI-Card Portable radio telephone MPEG, SC4 2 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 D SII SOD SIC SID SOI PI12 PI13 PI14 PI15 PI16 PI17 PI18 PI19 SOC SPDO PCSQ 10k SIBC PIO-control 100n SPDI2 100n SPDIR FILTL AVDD0 OUTL OUTR AVSS0 470p FILTR AVSS1 VREF 3n XTI VSS POR TE DVS XTO INL VDD XVDD XVSS INR MICBI AVDD1 1 3u3 220p 1n 18p 18p 390 n A 18.432 MHz 3.6...5.6 k 3.3 n 390p MIC 390p separate trace Tape recorder FM radio D A 1u Place VDD / XVDD -filter capacitors above ground plane 390n VDC1 VDC2 390n D 4u7 D 1.5u 1.5u Option for I2C-address connect to VSS or I2CVDD A D Star point ground connection very close to pins DCSG1 and DCSG2 1n A 10n 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 See figure caption 64 17 PVDD 63 18 DCSG1 DCSO1 62 19 DCSG2 61 20 DCSO2 60 21 VSENS2 59 22 DCEN 58 23 CLKO 4k7 VDC2 4k7 57 56 25 I2CD I2CC 55 26 SYNC 54 27 VBAT 100n 470p SPDI1 53 28 PUP 52 29 EODQ SIBI 51 30 PRTRQ 50 31 PRTWQ SIBD 5 49 32 PR D DATA SHEET 5. Application DigiAmp MD-recorder IEC 60958 100 k 3 DAB-receiver DVD-player 75 MPEG (IEC 61937) ADR-receiver 75 220u 22 MAS 35x9F 24 5.1. Typical Application in a Portable Player 220u L R 22 100 Headphone > 16 Ω 1.5k 100 1.5k µC − MMC/SDI-Card or SMC/CF2+ used as storage media − Dashed lines show optional (external) devices 6.8n 6.8n 22u I2CVDD VSENS1 MICIN AGNDC A 10n Fig. 5–1: Application circuit of the MAS 35x9F. For connections of the DC/DC converters, please refer to Fig. 5–2. June 30, 2004; 6251-505-1DS Place all ceramic capacitors as close as possible to IC pins VDC1 470p capacitorss should be high-Q (NP0 or C0G)