MAS9090BJ

DA9090B.001 January 14, 1998 MAS9090B LOW VOLTAGE 14-BIT LINEAR CODEC • 14-bit linear analog to digital and digital to analog converters • 8-bit A-law or µ-law companded analog to digital and digital to analog converters DESCRIPTION The MAS9090 is a high performance low power PCM CODEC and filter device tailored to implement the audio front-end functions required by the low voltage/low power consumption digital terminals. FEATURES • • • • • • • • • • Single 2.7-3.6 V or 4.5-5.5 V supply selectable -30°C to 85°C temperature operation range 11 mW operating power (typ. at 2.7V) 15 mW operating power (typ. at 3.0V) 27 mW operating power (typ. at 3.6V) 38 mW operating power (typ. at 5.0V) Digital bandpass filters ±0.5 dB absolute gain accuracy (untrimmed) 28-pin SO and 44-pin TQFP packages Pin compatible with ST5090 and ST5092 APPLICATIONS • • • • GSM digital cellular telephones Battery operated audio front-ends for DSPs ISDN Terminals CT2 and DECT digital cordless telephones BLOCK DIAGRAM MIC3MIC2MIC1- MUX PreAmp TX Gain EN PCM A to D Converter DE VS MIC3+ MIC2+ MIC1+ TE 1 1 0...22.5 dB 1.5 dB step Tone Gain Bandpass Filter Compressor TX Register TX MUX Clock Generator Sidetone Gain MCLK FS Ring/Tone/DTMF Generator BE BZ 4 0...-27 dB 3 dB step Buzzer Control OE1 2 -12.5...-27.5 dB 1 dB step Serial Control Interface EN CO CI CS CCLK LO SP1SP1+ RTE RX Gain (SP1/SP2) Buffer Amplifiers PCM D to A Converter SI SE 3 3 + + Bandpass Filter Expander RX Register RX SP2SP2+ 0...-30 dB 2 dB step OE2 1 DA9090B.001 January 14, 1998 PIN CONFIGURATION SO28 TQFP44 NC VCCA VCCP NC SP1SP1+ SP2SP2+ GNDP RX 1 2 3 4 5 6 7 8 9 10 28 MIC3+ 27 MIC326 GNDA 25 MIC1+ 24 MIC123 MIC2+ 22 MIC221 LO 20 MCLK 19 FS 18 GND 17 TX 16 CO 15 VCC 12 13 14 15 16 17 18 19 20 21 22 NNCCCBVCTGN CCCS I ZCOXNC D L C K 1 NC SP1- 2 3 SP1 NC 4 SP2- 5 SP2 6 NC 7 GNDP 8 9 NC 10 RX 11 NC 33 32 31 30 29 28 27 26 25 24 23 MIC1NC MIC2+ MIC2NC NC NC LO MCLK FS NC V C NNC CCP V C CNN ACC M I C 3 + M I C 3 M G I N C DN1 AC+ 44 43 42 41 40 39 38 37 36 35 34 CCLK 11 CS CI BZ 12 13 14 PIN DESCRIPTION Pin Name Pin Number SO28 TQFP44 1,4 1,4,7,9 11,12,13 22,23,27 28,29,32 35,39,40, 43,44 41 42 2 3 5 6 8 10 14 15 16 17 18 19 20 Type Function No connection. VCCA VCCP SP1SP1+ SP2SP2+ GNDP RX CCLK CS CI BZ VCC CO TX 2 3 5 6 7 8 9 10 11 12 13 14 15 16 17 P P AO AO AO AO G DI DI DI DI AO P DO DO GND FS 18 19 21 24 G DI Positive power supply input for analog section. Positive power supply input for speaker amplifiers. Speaker 1 amplifier negative output. Speaker 1 amplifier positive output. Speaker 2 amplifier negative output. Speaker 2 amplifier positive output. Speaker amplifier. Receive data input. Control clock input. Shifts serially into CI and CO when CS is low. CCLK is asynchronous with other system clocks. Chip select input. Control data input. Buzzer driver output. Positive power supply input for the digital section. VCCA, VCCP AND VCC must be connected together. Control data output. Transmit data output. Data is shifted out on this during the assigned transmit slots. Otherwise, TX is on high impedance state. Ground for the digital section. Frame sync input. This 8kHz signal defines the start of the TX and RX frames. 2 DA9090B.001 January 14, 1998 PIN DESCRIPTION Pin Name MCLK LO MIC2MIC2+ MIC1MIC1+ GNDA MIC3MIC3+ Pin Number 20 25 21 26 22 30 23 31 24 33 25 34 26 36 27 37 28 38 Type DI DO AI AI AI AI G AI AI Function Master clock input. Must be 512, 1536, 2048 or 2560 kHz Value of bit DO of CR1. Negative differential input for MIC2. Positive differential input for MIC2. Negative differential input for MIC1. Positive differential input for MIC1. GNDA analog ground. Negative differential input for MIC3. Positive differential input for MIC3. ABSOLUTE MAXIMUM RATINGS Parameter Supply Voltage Voltage at MIC Current at any digital output Voltage at any digital input Storage Temperature Symbol VCC Conditions VCC < 5.5V VCC < 5.5V Min -1 -1 -55 Max 7.0 VCC+1 50 VCC+1 +125 Unit V V mA V °C TS RECOMMENDED OPERATION CONDITIONS Parameter Supply Voltage Operating Temperature Symbol VCC TA Conditions 3.0V mode (SV=0) 5.0V mode (SV=1) Min 2.7 4.5 -30 Typ 3.0 5.0 Max 3.6 5.5 +85 Unit V v °C AC, TESTING INPUT, OUTPUT WAVEFORM IN PU T /O U T P UT 0.8 V cc 0.7 V cc test po ints AC testing: inputs are driven at 0.8Vcc for a logic ’1’ and 0.2Vcc for a logic ’0’. Timing measurements are made at 0.7Vcc for a ’1’ and 0.3 Vcc for a ’0’. 0.2 Vcc 0.3 Vcc 3 DA9090B.001 January 14, 1998 ELECTRICAL CHARACTERISTICS x Digital Inputs/Outputs (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Input low voltage Input high voltage Output low voltage Output high voltage Input low current Input high current Output current impedance in high Symbol VIL VIH VOL VOH IIL IIH IOZ Conditions All digital inputs DC All digital inputs AC All digital inputs DC All digital inputs AC All digital outputs, IL = 10µA All digital outputs, IL = 2mA All digital outputs, IL = 10µA All digital outputs, IL = 2mA Any digital input, GND < VIN < VIL Any digital input, VIH < VIN < VCC TX and CO Min Typ Max 0.3VCC 0.2VCC Unit V V 0.7VCC 0.8VCC 0.1 0.4 VCC-0.1 VCC-0.4 -10 -10 -10 V V 10 10 10 µA µA µA x Analog Inputs/Outputs (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Input leakage Input resistance Load resistance Load capacitance Output resistance Differential offset voltage from SP1+ to SP1Load resistance Load capacitance Input resistance Output resistance Differential offset voltage from SP2+ to SP2x Power Dissipation Symbol IMIC RMIC RLSP1 CLSP1 ROSP1 VOSP1 RLSP2 CLSP2 RMIC ROSP2 VOSP2 Conditions GND < VMIC < VCC (active mic) GND < VMIC < VCC SP1+ to SP1SP1+ to SP1Steady zero PCM code applied to RX, I = 1mA Alternating zero PCM code applied to RX, RL = 30 ohms SP2+ to SP2SP2+ to SP2GND < VMIC < VCC Steady zero PCM code applied to RX, I = 1mA Alternating zero PCM code applied to RX, RL = 30 ohms Min -100 50 30 Typ ±20 Max +100 Unit µA kΩ Ω 50 1.0 -100 30 50 50 1.0 -100 0 +100 0 +100 nF Ω mV Ω nF kΩ Ω mV (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Power down current at 3.0V Power down current at 5V Power up current at 2.7V Power up current at 3.0V Power up current at 3.6V Power up current at 5V SP1 short circuit current Symbol ICC0 ICC0 ICC1 ICC1 ICC1 ICC1 ISHORT Conditions CCLK, CI = 0.1V CS = VCC - 0.1V CCLK, CI = 0.1V CS = VCC - 0.1V SP1 and SP2 not loaded SP1 and SP2 not loaded SP1 and SP2 not loaded SP1 and SP2 not loaded Min Typ 0.08 0.08 4 5 7.5 7.5 130 Max 10 10 6 8 12 20 Unit µA µA mA mA mA mA mA 4 DA9090B.001 January 14, 1998 TIMING SPECIFICATIONS x Master Clock Timing Parameter Frequency of MCLK Symbol fMCLK tWHM tWLM tWHM tWLM tRM tFM Conditions programmable Min Typ 512 1536 2048 878 80 80 30 30 1074 Max Unit kHz Period of MCLK high/low fMCK = 512 Period of MCLK high fMCK = 1536, 2048 Period of MCLK low fMCK = 1536, 2048 Rise time of MCLK Fall time of MCLK x PCM Interface Timing Parameter Hold time, MCLK low to FS low Setup time, FS high to MCLK low Delay time, MCLK high to valid TX data Delay time, MCLK low to TX disabled Delay time, FS high to valid TX data Setup time, RX data valid to MCLK low Hold time, MCLK low to invalid RX data Hold time, MCLK high to FS low Setup time, FS high to MCLK high Delay time, MCLK low to valid TX data Delay time, MCLK high to TX disabled Hold time, MCLK high to invalid RX data x Non-Delayed Data Timing Diagram tHMLF MCLK 1 2 3 Measured from VIH to VIH Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL ns ns ns ns ns Symbol tHMLF tSFML tDMHT tDMLZ tDFT tSRML tHMLR tHMHF tSFMH tDMLT tDMHZ tHMHR Conditions Min 17 30 Typ Max Unit ns ns Load = 100pF 10 Load = 100pF non-delayed mode only 20 10 30 30 Load = 100pF 10 20 100 100 100 ns ns ns ns ns ns ns 100 100 ns ns ns tRM 4 tFM 5 tWHM 6 7 8/16 tSFML FS tWLM tDFT tDMHT TX 1 2 3 4 5 6 7 tDMLZ 8/16 tSRML tHMLR RX 1 2 3 4 5 6 7 8/16 In companded mode the timing is applied to 8 bits instead of 16 bits. 5 DA9090B.001 January 14, 1998 TIMING SPECIFICATIONS x Delayed Data Timing Diagram tHMLF MCLK 1 2 3 tRM 4 tFM 5 tWHM 6 7 8/16 tSFML FS tWLM tDMLZ tDMHT TX 1 2 3 4 5 6 7 8/16 tSRML tHMLR RX 1 2 3 4 5 6 7 8/16 In companded mode the timing is applied to 8 bits instead of 16 bits. x Non-Delayed Reverse Data Timing Diagram tHMHF MCLK 1 2 3 tFM 4 tRM 5 6 tWHM 7 8/16 tSFMH FS tWLM tDFT tDMLT TX 1 2 3 4 5 6 7 tDMHZ 8/16 tSRML RX 1 2 3 tHMLR 4 5 6 7 8/16 In companded mode the timing is applied to 8 bits instead of 16 bits. 6 DA9090B.001 January 14, 1998 TIMING SPECIFICATIONS x Serial Control Port Timing Parameter Frequency of CCLK Period of CCLK high Period of CCLK low Rise time of CCLK Fall time of CCLK Hold time, CCLK high to CS low Setup time, CS low to CCLK high Setup time, valid CI data to CCLK high Hold time, CCLK high to invalid CI data Delay time, CCLK low to valid CO data Delay time, CS low to valid CO data Delay time, CS high or 8 CCLK low to CO high impedance th Hold time, 8 CCLK high to CS high Setup time, CS high to CCLK high th Symbol fCCLK tWHC tWLC tRC tFC tHCHS tSSLCH tSDCH tHCHD tDCLD tDSD tDSZ tH8CHS tSSHCH Conditions Min Typ Max 2.048 Unit MHz ns ns Measured from VIH to VIH Measured from VIL to VIL Measured from VIL to VIH Measured from VIH to VIL 160 160 50 50 10 50 50 50 ns ns ns ns ns ns Load = 100 pF 10 100 100 80 50 80 ns ns ns ns ns x Serial Control Port Timing Diagram (MICROWIRE mode) tWHC CCLK 1 2 3 4 5 tWLC 6 7 8 tHCHS 1 2 3 tRC 4 tFC 5 6 7 8 tSSLCH tHCHS CS BYTE 1 tSSHCH BYTE 2 tHCHSH tSDCH tHCHD CI 7 6 5 4 3 2 1 0 tHCHSH tSSLCH 7 6 5 4 3 2 1 0 tDSD CO 7 tDCLD 6 5 4 3 2 1 tDSZ 0 7 DA9090B.001 January 14, 1998 TRANSMISSION CHARACTERISTICS x Absolute levels at MIC1/MIC2/MIC3 (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter 0 dBm0 level Overload level 0 dBm0 level Overload level Conditions Transmit amps connected for 20 dB gain Transmit amps connected for 42.5 dB gain Min Typ 49.26 70.71 3.694 5.302 Max Unit mVRMS mVRMS mVRMS mVRMS x Absolute levels at SP1 / SP2 (differentially measured) (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter 0 dBm0 level 0 dBm0 level Conditions Receive gains = 0 dB Receive gains = -30 dB Min Typ 1.965 61.85 Max Unit VRMS mVRMS x Transmit path amplitude response (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Transmit gain absolute accuracy, HPT = 0 HPT = 1 Transmit gain variation with programmed gain Symbol GXA Conditions TX gain set to maximum, measure deviation of digital PCM code from ideal 0 dBm0 PCM code at TX Measure TX gain over the range (from max to min). Calculate the deviation from the programmed gain relative to GXA, i.e. GXAG = Gactual - Gprog - GXA Measured relative to GXA min. gain < GX < max. gain Measured relative to GXA GX = maximum gain Relative to 1.015625 kHz, multitone test technique used min. gain < GX < max. gain f = 60 Hz f = 100 Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz f = 4600 Hz f = 8000 Hz f = 60 Hz to 3000 Hz f = 3000 to 8000 Hz, see HPT=0 Sinusoidal test method reference level = -10 dBm0 VMIC = -40 dBm0 to +3.0 dBm0 VMIC = -50 dBm0 to -40 dBm0 VMIC = -55 dBm0 to -50 dBm0 Measure deviation of digital PCM code from ideal 0dBm0 PCM code at TX Min -0.5 -0.4 -0.5 Typ 0 0.1 Max 0.5 0.6 0.5 Unit dB GXAG dB Transmit gain variation with temperature Transmit gain variation with supply Transmit gain variation with frequency HPT=0 GXAT GXAV GXAF -0.1 -0.1 0.1 0.1 dB dB -1.5 -0.5 -1.5 -34 -36 -11 -0.7 -1.3 -17 -62 -68 HPT=1 Transmit gain variation with signal level GXAL -0.5 -33 -35 -10 0.5 0.5 0.0 -16 -61 -67 0.5 dB dB Tone Generator gain absolute accuracy GXTONE -0.5 -0.5 -1.2 -0.3 0.5 0.5 1.2 0.6 dB dB 8 DA9090B.001 January 14, 1998 TRANSMISSION CHARACTERISTICS x Receive path amplitude response (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Receive gain absolute accuracy, HPX = 0 HPX = 1 Receive gain absolute accuracy, HPX = 0 HPX = 0 Receive gain variation with programmed gain Symbol GRA1 GRA2 GRAG1 Conditions RX gain programmed to maximum, apply -6dBm0 PCM code to RX, measure SP1+ to SP1RX gain programmed to maximum, apply -6dBm0 PCM code to RX, measure SP2+ to SP2Measure SP1 gain over the range from maximum to minimum setting, calculate the deviation from the programmed gain relative to GRA1, i.e. GRAG1 = Gactual-GprogGRA1 Measure SP2 gain over the range from maximum to minimum setting, calculate the deviation from the programmed gain relative to GRA2, i.e. GRAG2 = Gactual-GprogGRA2 Measured relative to GRA1 or GRA2 min. gain < GR < max. gain Measured relative to GRA1 or GRA2 GR = maximum gain Relative to 1.015625 kHz, multitone test technique used. min. gain < GR < max. gain. f = 60 Hz f = 100 Hz f = 200 Hz f = 300 Hz f = 400 Hz to 3000 Hz f = 3400 Hz f = 4000 Hz Min -0.5 -0.4 -0.5 -0.4 -0.5 Typ 0 0.1 0 0.1 Max 0.5 0.6 0.5 0.6 0.5 Unit dB dB dB Receive gain variation with programmed gain GRAG2 -0.5 0.5 dB Receive gain variation with temperature Receive gain variation with supply Receive gain variation with frequency (SP1 and SP2) HPR = 0 GRAT GRAV GRAF -0.1 -0.1 0.1 0.1 dB dB -34 -38 -12 -1.5 -0.5 -1.5 -1.3 -15 -0.5 -0.5 -33 -35 -10 0.5 0.5 0.0 -14 0.5 dB HPR = 1 Receive gain variation with signal level (SP1) GRAL1 f = 60 Hz to 3000 Hz f = 3000 to 4000 Hz, see HPR=0 Sinusoidal test method, reference level = -10 dBm0 RX = -40 dBm0 to -3 dBm0 RX = -50 dBm0 to -40 dBm0 RX = -55 dBm0 to -50 dBm0 -0.5 -0.5 -1.2 0.5 0.5 1.2 dB Receive gain variation with signal level (SP2) GRAL2 Sinusoidal test method, reference level = -10 dBm0 RX = -40 dBm0 to -3 dBm0 RX = -50 dBm0 to -40 dBm0 RX = -55 dBm0 to -50 dBm0 -0.5 -0.5 -1.2 -1 0.5 0.5 1.2 1 dB Tone Generator absolute accuracy gain GRTONE Measure signal level at SP1 dB 9 DA9090B.001 January 14, 1998 TRANSMISSION CHARACTERISTICS x Envelope delay distortion with frequency (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter TX delay, absolute TX delay, relative Symbol DTXA DTXR Conditions f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz Min Typ 800 15 20 5 -15 -40 -50 -50 800 15 20 5 -15 -40 -50 -50 Max Unit µs µs RX delay, absolute RX delay, relative DRXA DRXR f = 1600 Hz f = 500 - 600 Hz f = 600 - 800 Hz f = 800 - 1000 Hz f = 1000 - 1600 Hz f = 1600 - 2600 Hz f = 2600 - 2800 Hz f = 2800 - 3000 Hz µs µs x Noise (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter TX noise, P weighted RX noise, A weighted (max. gain) Noise, single frequency Symbol NTXP NRXA NS PPSRTX PPSRRX Conditions VMIC = 0V, DE = 0, TX gain set to 15 dB Receive PCM code = positive zero SI = 0, RTE = 0 MIC = 0V, loop around measurement from f = 0 Hz to 100 kHz MIC = 0V VCC = 3.3VDC + 50 mVRMS f = 0 Hz to 50 kHz PCM code equals positive zero VCC = 3.3 VDC + 50 mVRMS f = 0 Hz to 4 kHz f = 4 kHz to 50 kHz RX input set to -6 dBm0 PCM code, 300 Hz 3400 Hz input PCM code applied at RX 4600 Hz - 5600 Hz 5600 Hz - 7600 Hz 7600 Hz - 8400 Hz 8400 Hz - 20000 Hz Min Typ -72* Max -68* Unit dBm0 µVRMS dBm0 140* -76 190* -50 PSRR, TX 30 44 dB PSRR, RX 30 30 54 dB Spurious out-band signal at the output (relative to signal) SOS -45 -45 -50 -50 -74 -36 -45 -28 dB Common mode rejection ratio Tone generator noise CMRRX NTONE MIC = -6dBm0, max. gain DTMF frequencies, TX/SP output dB dBm0 *Limit is used to speed up automatic testing. True value is less. 10 DA9090B.001 January 14, 1998 TRANSMISSION CHARACTERISTICS x Distortion (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Signal to total distortion TX (up to 35 dB gain) Typical values measured with 35 dB gain Symbol STDTX Conditions Sinusoidal test method (Linear 300 Hz to 3400 Hz weighting). Level = 0 dBm0 Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -45 dBm0 Level = -55 dBm0 0 dBm0 input signal Sinusoidal test method (Linear 300 Hz to 3400 Hz weighting). Load is 1000 or 30 Ω. Level = -6 dBm0 Level = -10 dBm0 Level = -20 dBm0 Level = -30 dBm0 Level = -45 dBm0 Level = -55 dBm0 -6 dBm0 input signal DTMF frequencies Linear 300 Hz to 3400 Hz weighting. Loop around measurement voltage at MIC = -10 dBm0 to 27 dBm0, 2 frequencies in the range 300 Hz to 3400 Hz Min Typ Max Unit 56 50 48 43 38 24 15 Single frequency distortion transmit Signal to total distortion SP1/SP2 (up to 20 dB attenuation) SDTX STDSP1 STDSP2 64 60 57 53 44 29 19 -70 dB -56 dB 45* 45* 43* 38* 24* 15* 50 48 43 38 24 15 Single frequency distortion receive SP1/SP2 Signal to distortion of tone generator signals Intermodulation SDSP1 SDSP2 STONE IMD 60 60 55 50 40 28 -62 42 dB -45 dB dB 28 -61 -46 dB *max. load (30Ω) and min. Vcc (2.7V) x Crosstalk (VCC = 2.7-3.6V or 4.5-5.5V, TA = -30°C to +85°C, unless otherwise specified) Parameter Transmit to receive Symbol CTX-RX CRX-TX Conditions Transmit level = 0 dBm0 f = 300 Hz to 3400 Hz RX = quiet PCM code Receive level = -6 dBm0 f = 300 Hz to 3400 Hz MIC = 0V Min Typ -82 Max -65 Unit dB Receive to transmit -75 -60 dB 11 DA9090B.001 January 14, 1998 RESPONSES x RX frequency response 10 0 −10 Amplitude dB −20 −30 −40 −50 −60 1 10 10 2 10 Frequency Hz 3 x RX frequency response (passband) 1 0.5 Amplitude dB 0 −0.5 −1 −1.5 10 Frequency Hz 3 12 DA9090B.001 January 14, 1998 RESPONSES x RX frequency response (stopband low) 0 −10 Amplitude dB −20 −30 −40 −50 1 10 Frequency Hz 10 2 x RX frequency response (stopband high) 0 −10 Amplitude dB −20 −30 −40 −50 −60 4000 Frequency Hz 5000 6000 13 DA9090B.001 January 14, 1998 RESPONSES xTX frequency response 10 0 −10 Amplitude dB −20 −30 −40 −50 −60 1 10 10 2 10 Frequency Hz 3 10 4 xTX frequency response (passband) 1 0.5 Amplitude dB 0 −0.5 −1 −1.5 10 Frequency Hz 3 14 DA9090B.001 January 14, 1998 RESPONSES xTX frequency response (stopband low) 0 −10 Amplitude dB −20 −30 −40 −50 1 10 Frequency Hz 10 2 xTX frequency response (stopband high) 0 −10 Amplitude dB −20 −30 −40 −50 −60 4000 Frequency Hz 5000 15 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION x Operating Modes When power is first applied, power-on reset circuit initializes control and data registers of MAS9090 and puts it into a power-down state. During powerdown state, control registers retain their initial state until they are written via the serial interface. Master clock (MCLK) can be inactive. The power up/down control is accomplished by changing the P-bit of the address byte of the serial interface ("0" means active and "1" power-down) or by stopping the master clock. P=0, active MCLK and FS powerdown P=1 powerup normal data timing, non-delayed reverse data timing and delayed data timing. These modes are set with bits DM0 and DM1 of control register CR1. In non-delayed timing modes the first time slot begins coincident with the rising edge of the FS. In delayed timing mode the FS must be active at least one half cycle of MCLK before the beginning of the first time slot. Bit EN of control register CR1 enables the voice data transfer on TX and RX pins. Data is shifted out from TX output on the rising edge of MCLK and shifted into RX on falling edge of MCLK on assigned time slot. In non-delayed reverse mode the data is shifted with different edge of MCLK (on falling edge from TX and on rising edge into RX). TX output is in tristate condition during non selected time slots. The TX output transmits 8 bits of encoded data (A-law or µ-law) or 16 bits (14 effective bits, 2 LSB bits zero) of linear data when compressor is bypassed. Two time slots (B1 and B2) can be used in two formats: in Format 1, time slot B1 corresponds to eight MCLK cycles starting immediately after the rising edge of FS and time slot B2 starts immediately after the B1 is ended. A two-bit space is left after B2 for insertion of possible D channel data. The position of this two-bit data is changed in Format 2 to the center of time slots B1 and B2. The data format is selected by bit FF in control register CR0 and time slots B1 and B2 are selected by bit TS in control register CR1. x Control Channel Access to PCM Interface When companded code is selected it is possible to access the selected time slot (B1 or B2) by writing data bytes to internal registers CR2 and CR3. The byte written to CR3 is transmitted from TX with the following frame in place of PCM data if bit MX (3) of CR1 is selected. To implement a continuous data flow from interface to B channel a control byte has to be sent on each PCM frame. The byte written into CR2 is sent through the receive audio path (RX) if bit MR (4) of CR1 is selected. CR2 can also be used to read the RX input. In order to implement a continuous data flow from B channel to the interface, register CR2 has to be read at each PCM frame. power-on reset no MCLK x Control Interface Control information or data is written into or readback from the internal registers of MAS9090 via the serial control port. Serial control port consists of control output CO, control input CI, chip select CSand control clock CCLK and supports the MICROWIRE™*) communication protocol. All control instructions, except the single byte power up/down command require two bytes of data. To shift the data into MAS9090, CCLK must be pulsed eight times (CS is low). Data on the CI input is shifted into the serial input register on the rising edges of CCLK pulses. After 8 bit address data is shifted in, the content of the shift register is decoded and may indicate that 8 bit control word will follow. Control word may start immediately after the address byte or after a single CS pulse. It is not mandatory for the CS signal to return high in between the address and the data. After the second byte is shifted in, the CS signal must return to a high state. The same process takes place for reading-back status information during the next CS low state. CS will remain low for eight CCLK pulses. The data is shifted out on the CO output from the serial output register on the falling edges of CCLK. When CS is high, the CO pin is in a high impedance state, which enables CO pins of other devices to be multiplexed together. x Digital Data Interface Digital data is shifted in/out from RX/TX using master clock (MCLK) and Frame Sync (FS) signals. FS determines the beginning of frame and its duration can vary from single cycle of MCLK to squarewave. Three different modes between FS and the first time slot of a data frame can be used: non-delayed *) Trade Mark of National Semiconductor 16 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION x TX Audio Path Analog front end provides three identical differential inputs (MIC1, MIC2, MIC3) for capacitive connection of microphones or auxiliary audio circuits. Desired input signal is selected with bits VS and TE (6 and 7) of register CR4 and forwarded to a low noise preamplifier. Preamplifier has 15.7 dB gain and its output is fed to the programmable gain amplifier which provides an additional gain from 0 to 22.5 dB in 1.5 dB steps. Gain is controlled with bits 4-7 of register CR5. An active RC anti alias filter is used to prevent signal folding during the sampling. Accurate analog to digital conversion is done by using a sigma-delta modulator followed by a decimation filter. Digital multiplexer (bit DE (0) in CR 7) is used to select the input of a digital bandpass filter (3003400 Hz). The input can be taken from the output of the decimator or from an internal ring/tone generator. The bandpass filter output contains hard clipping saturation logic for signals exceeding overload level (+3.14 dB). Highpass part of the bandpass filter can be bypassed with bit HPT of register CR10. Output data can be compressed by using CCITT Alaw or µ255-law coding. The compression code is selected with bits CM (5), MA (4) and IA (3) of register CR0. x RX Audio Path Received signal is transferred into RX register in 8 bit encoded format or in 16 bit linear format. The data is expanded by using A-law or µ-law signal encoding according to CCITT A and µ255 laws. The expansion code is selected with bits CM (5), MA (4) and IA (3) of register CR0. Signal is then passed through a bandpass filter (bandpass 300-3400 Hz). The high pass section of the filter can be bypassed with bit HPR of register CR4. The input signal of RX gain3 is controlled with bits SI (5), RTE (2) and SE (0) of register CR4. Bit SI activates the transmit side tone signal, bit RTE activates the ring/tone generator and bit SE activates the received signal to be summed to the gain input. RX gain3 can be programmed with bits 4-7 of register CR6 from 0 dB to -30 dB with -2dB steps. It contains also hard-clipping saturation logic. After gain adjustment the signal is fed to a digital sigma-delta modulator followed by a switched capacitor (SC) reconstruction filter and a continuous time smoothing filter. Filtered analog signal can be directed to a speaker amplifier (SP1) or to an extra analog output amplifier (SP2) with bits OE1 (4) and OE2 (3) of register CR4. Gains can be set with register CR6 in the range of 0 to -30 dB in -2 dB steps. 17 Differential analog outputs (SP1, SP2) are capable of directly driving output load of 30 Ω with power level up to 66mW. Also ceramic receivers up to 50nF can be used. Power up transient noise suppression is used in both outputs. x Ring and tone generator Ring/tone generator is able to generate one or two sinewave or squarewave frequencies (including DTMF tones) to the transmit (TX) receive (RX) or buzzer paths. Generated frequencies can be programmed with registers CR8 and CR9. One of the three frequency ranges can be selected with bits DFT and HFT of register CR10. Output signal level of the tone generator can be selected from 0 to -27 dB with -3dB steps with bits 4-7 of register CR7. Single ended BZ output is used to drive a buzzer by using an external bipolar transistor with pulse width modulated (PWM) squarewave signal f1 (CR8). This PWM signal can also be amplitude modulated with signal f2 (CR9). Maximum load for BZ is 5 kΩ and 50pF. Implementation of tone generator is fully digital. Therefore no amplitude or frequency response variations (at TX output) over temperature, power supply or from unit to unit exist. DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION x Digital Interface Format Format 1 FS delayed timing FS 1 2 34 5 6 78 non-delayed timing MCLK RX B1 B2 X X X TX B1 B2 Format 2 FS delayed timing FS 1 2 34 5 6 78 non-delayed timing MCLK RX B1 X B2 X X TX B1 B2 18 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION x Registers Register Map Register 7 Power P CR0 P P CR1 P P CR2 P P CR3 P P CR4 P P CR5 P P CR6 P P CR7 P P CR8 P P CR9 P P CR10 P P CR11 P P CR14 X 6 X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X Address Byte 5432 XXXX 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111 XXXX I/O 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X 0 X X X X X X X X X X X X X X X X X X X X X X X X X X 7 6 F0 DM0 5 CM DO Data Byte 4 MA MR 3 IA MX 2 FF EN 1 B7 TS 0 DL SV Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read F1 DM1 Input data [0:7] Output data [0:7] VS TE SI OE1 OE2 RTE HPR SE TX gain [4:7] SP1 gain [4:7] Tone gain [4:7] F1 Side tone gain [0:3] SP2 gain [0:3] F2 SN DE Binary word used for calculating f1 Binary word used for calculating f2 POR BE SCA BI HPT EXT LI LO DFT HFT Duty cycle for BZ (0:5) For testing purposes only Address byte bits: • • • • • • • Bit 0 reserved for future extensions Bit 1 indicates the presence of a second byte. If cleared indicates single byte power up/down command Bit 2 is write/read select bit Bits 6 to 3 contain the address of register Registers CR12, CR13, CR15 are not accessible MSB bit (bit 7) of the address and data byte is always clocked first into or out from CI and CO pins Bit 7 ‘P’ controls the power up/down state of the chip. P = 1 means power down Data bits: • • All registers are cleared during power on reset or by writing to bit POR of CR10 Default value for all bits is zero. Notice the difference between power down and POR. Registers can be written in both power down/up states and they retain their values in power down. Both data and control registers are cleared when POR bit (in CR10) is written high or during power on reset (i.e. Vcc transition from 0 volts to 3-5 volts). 19 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION Control register CR0 7 6 5 F1 F0 CM 0 0 0 1 1 0 1 1 0 4 MA 3 IA 2 FF 1 B7 0 DL Function MCLK = 512 kHz MCLK = 1536 kHz MCLK = 2048 kHz Not implemented Linear code 2’s complement sign and magnitude 2’s complement 1’s complement Companded code µ-Law: CCITT D3-D4 µ-Law: bare coding A-Law: including even bit inversions A-Law: bare coding B1 and B2 consecutive B1 and B2 separated 8-bit time slot 7-bit time slot Normal operation (default) Digital loop back (TX and RX muted) * 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * * (1)* (1) (1)* (1) * Control register CR1 7 6 5 TM1 TM0 DO 0 X 1 0 1 1 0 1 4 MR 3 MX 2 EN 1 TS 0 SV Function Delayed data timing Non-delayed normal data timing Non-delayed reverse data timing LO latch set to 1 LO latch set to 0 RX connected to RX path CR2 connected to RX path TX path connected to TX CR3 connected to TX Voice data transfer disable Voice data transfer enable B1 channel selected B2 channel selected 2.7-3.6V power supply * 5.0V power supply * * * (1) * (1) * (1)* (1) 0 1 0 1 0 1 0 1 0 1 (1) * significant in companded mode only state at power on initialization 20 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION Control register CR2 7 6 5 d7 d6 d5 msb 4 d4 3 d3 2 d2 1 d1 0 d0 Function Data sent to RX path or data received from RX input Control register CR3 7 6 5 d7 d6 d5 msb 4 d4 3 d3 2 d2 1 d1 0 d0 TX data transmitted Function Control register CR4 7 6 5 VS TE SI 0 0 0 1 1 0 1 1 0 1 4 OE1 3 OE2 2 RTE 1 HPR 0 SE Function TX input muted MIC1 selected MIC2 selected MIC3 selected Internal side tone disabled Internal side tone enabled RX output muted SP1 output selected SP2 output selected NOT ALLOWED Ring/Tone to SP1 or SP2 disabled Ring/Tone to SP1 or SP2 enabled Receive HP filter enabled Receive HP filter disabled RX signal to SP1 or SP2 disabled RX signal to SP1 or SP2 enabled * * * 0 0 1 1 0 1 0 1 0 1 0 1 0 1 * * * Control register CR5 7 6 5 TX Gain 0 0 0 0 0 0 1 1 1 4 0 1 1 3 2 1 Sidetone Gain 0 0 dB gain 1.5 dB gain in 1.5 dB steps 22.5 dB gain -12.5 dB gain -13.5 dB gain in 1 dB steps -27.5 dB gain Function * 0 0 1 * state at power on initialization 0 0 1 0 0 1 0 1 1 * 21 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION Control register CR6 7 6 5 Earpiece Gain (SP1) 0 0 0 0 0 0 1 1 1 4 3 2 1 Extra Gain (SP2) 0 Function 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 dB gain -2 dB gain in -2 dB steps -30 dB gain 0 dB gain -2 dB gain in -2 dB steps -30 dB gain * * Control register CR7 7 6 5 4 Tone gain 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 X X 0 1 X X 1 3 f1 2 f2 1 SN 0 DE 0 0 1 1 0 1 0 1 0 1 0 1 Function Attenuation f1 dBm0 f2 dBm0 f1+f2 dBm0 0 dB gain * 1.20 (2) -0.87 (2) -1.81 (2) -3 dB -6 dB -9 dB -12 dB -15 dB -18 dB -21 dB -24 dB -27 dB -25.80 -27.87 -28.81 f1 and f2 muted * f2 selected f1 selected f1 and f2 in summed mode Squarewave signal selected * Sinewave signal selected Normal operation * Tone/Ring generator connected to TX path Control register CR8 7 6 5 d7 d6 D5 msb 4 d4 3 d3 2 d2 1 d1 0 d0 f1 control word Function Control register CR9 7 6 5 d7 d6 d5 msb 4 d4 3 d3 2 d2 1 d1 0 d0 f2 control word Function (2) X * values are calculated from TX output, levels on RX are 6 dB smaller don’t care state at power on initialization 22 DA9090B.001 January 14, 1998 FUNCTIONAL DESCRIPTION Control register CR10 7 6 5 4 POR SCA HPT EXT 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 Control register CR11 7 6 5 4 BE BI BZ5 BZ4 0 1 0 1 msb 0 1 0 1 3 L1 2 L0 1 DFT 0 HFT Function Normal operation Set power-on-reset initialization Normal operation Scan. CI is input, DX is output. testing. Normal operation Bypass TX highpass filter Normal operation Read 2-bit input to the decimator. testing (CI and DR) Normal operation Loop from expander to compressor Normal operation Loop from TX to Rx Standard frequency tone range Halved frequency tone range Double frequency tone range Forbidden * * For device * * For device * * * 3 BZ3 2 BZ2 1 BZ1 0 BZ0 Function Buzzer Output disabled (set to 0) * Buzzer output enabled Duty cycle is relative to width of logic 1 * Duty cycle is relative to width of logic 0 Duty cycle control word Control register CR14 ( for testing purposes only) 7 6 5 4 3 2 1 AM2 AM1 AM0 DM2 DM1 DM0 MUX 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 1 X X 0 1 0 1 0 1 0 1 0 EDX Function rxtest pin Txtest pin VSA VSA Anti-image filter Gain amplifier DAC output VSA RX pos. reference Anti-image filter RX neg. reference VSA RX agnd VSA NC VSA NC NC TX (configured for test by MUX) Power-on reset Input of TX bandpass filter Sign bit of DIGSDM 512 kHz clock (phi1) internal frame sync Output of RX gain3 Normal operation Connect selected test outputs to TX output Normal operation Enable TX output continuously 0 1 * state at power on initialization 23 DA9090B.001 January 14, 1998 REGISTER DESCRIPTION Control register CR0 Master Clock Frequency Selection: External MCLK frequency can be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz. During initialization Bits F1 (7) and F0 (6) must be set to select correct value for internal clock divider. Default value for external MCLK is 512 kHz. Any other value must be selected before Power up command. Coding Selection Bit CM (5) permits selection of 14-bit linear coding or companded coding. Default is linear mode. In case of companded mode (CM=1) bits MA (4) and IA (3) select either µ-255 or A law coding mode and the format for both. In case of linear mode (CM=0) bits MA (4) and IA (3) select the linear data to be in 2’s complement, 1’s complement or sign and magnitude format. Digital Interface Format (1) Bit FF (2) selects the format for TX and Rx data transfer. If FF=0 Format 1 is selected and channels B1 and B2 are consecutive. FF = 1 selects Format 2 where channels B1 and B2 are separated by two bits. 56+8 Selection (1) If bit B7 (1) is selected MAS9090 takes only seven most significant bits of the companded PCM data byte. LSB bit on RX is ignored and LSB bit on TX is in high impedance state. This allows direct connection of an external “in band” data generator to the digital interface. Digital Loopback Bit DL (0) selects the digital loopback mode, where data written into RX data register (CR2) from received time slot is read-back from that register in the selected time-slot on TX. No PCM decoding or encoding takes place in this mode. Control Register CR1 Digital Interface Timing Bit TM1 (7) selects the timing mode for digital interface. As a default (TM1=0) delayed timing mode is selected. In delayed mode (TM1=1) bit TM0 (6) selects the normal (TM0=0) or reversed timing mode (TM0=1). Latch output control Bit DO (5) controls directly the LO output pin. Bit written to DO is seen inverted from the output LO. (1) Significant in companded mode only Microwire access on RX path (1) When bit MR (4) is set high the data written into register CR2 is decoded each frame and sent to receive path. Data input RX is ignored when MR is high. In other direction, current PCM data input received at RX can be read from register CR2 each frame. Microwire access on TX path (1) Bit MX (3) enables the access of write only register CR3 to TX output. When MX is set active data written to CR3 is send to TX output every frame. PCM encoder is ignored. Transmit/Receive enable/disable Bit EN (2) enables or disables voice data transfer on TX and RX pins. When disabled PCM data from RX input is not decoded and TX output is on high impedance state. Default value is disabled. B-channel selection (1) Bit TS (1) selects the active channel B1 or B2. Default (TS=0) is B1 channel. (See Fig on page 14) Power supply selection Bit SV (0) selects the main supply voltage used. When SV is low a 2.7-3.6 V supply is assumed. When SV is high 4.5-5.5 V is expected. Control Register CR2 (1) Data sent to receive path or data received from RX input is seen in register CR2. See register CR1 bit MR (4). Control Register CR3 (1) TX data transmitted. Refer to bit MX (3) in CR1. 24 DA9090B.001 January 14, 1998 REGISTER DESCRIPTION Control Register CR4 Transmit Input Selection Bits VS (7) and TE (6) select active input (MIC1, MIC2 or MIC3). Default is that all inputs are muted. Transmit (TX) gain can be adjusted from 0 to 22.5 dB in 1.5 dB steps with register CR5 bits (7:4). Sidetone Selection Transmit signal after bandpass filter can be fed back to the receive amplifiers when bit SI (5) is set high. Output Driver Selection Bits OE1 (4) and OE2 (3) select the active output of the RX gain to be SP1 or SP2. Both outputs can be muted. Ring/Tone Signal Selection Bit RTE (2) connects the on-chip Ring/Tone generator to the RX gain input. Receive High Pass Filter Selection Bit HPR (1) provides possibility to bypass high pass section of the receive bandpass filter. PCM receive data selection Bit SE (0) enables the connection of the received signal to the RX gain input. Control Register CR5 Transmit Gain Selection TX gain can be programmed from 0 to 22.5 dB in 1.5 dB steps with bits (7:4). Sidetone Attenuation Selection Transmit signal picked after digital bandpass filters can be fed back to RX gain. Attenuation of the sidetone signal can be programmed from –12.5 dB to –27.5 dB in 1 dB steps with bits (7:4). Attenuation is relative to the input signal level of bandpass filter. Control Register CR6 Speaker 1 and 2 Gain Selection The attenuation of both speaker gains can be programmed separately from 0 to –30 dB in 2 dB steps with bits (7:4) and (3:0). 0 dBm0 voltage at the output of the RX gain on pins SP1/2+ and SP1/2- is 1.965 Vrms when 0 dB gain is selected. When –30 dB gain is selected the 0 dBm0 level is 61.85 mVrms. Control Register CR7 Tone/Ring Gain Selection Output of Tone/Ring generator can be attenuated from 0 to –27 dB in 3 dB steps with bits (7:4). Frequency Mode Selection Bits f1 (3) and f2 (2) permit selection of f1 and/or f2 frequency generators. When f1 (f2) is selected the output of the tone generator is signal at the frequency programmed by the register CR8 (CR9). If both f1 and f2 are selected the output is a sum of both signals. In case of squarewave the f1 is amplitude modulated by f2. In order to meet DTMF specifications the level of f2 is attenuated by 2 dB relative to f1. Waveform Selection Bit SN (1) selects the output waveform of the tone generator to be square (SN=0) or sinewave (SN=1). DTMF Selection Bit DE (0) permits the connection of the tone generator to the transmit path. Speaker output can also be provided by using sidetone circuit (bit SI of CR4) or directly connecting the tone generator to RX gain with bit RTE of CR4. 25 DA9090B.001 January 14, 1998 REGISTER DESCRIPTION Control Registers CR8 and CR9 The frequency of both frequency generators is programmed by CR8 and CR9. When standard frequency range is selected (CR10: DFT=0, HFT=0) the frequency is defined by formulas: f1 = CR8 / 0.128 Hz and f2 = CR9 / 0.128 Hz, where CR8 and CR9 are decimal equivalents of the register content. Thus any frequency between 7.8 Hz and 1992 Hz in 7.8 Hz step can be selected. When halved frequency range is selected (CR10:DFT=0, HFT=1) the frequency is defined by formulas: f1 = CR8 / 0.256 Hz and f2 = CR9 / 0.256 Hz. Thus any frequency between 3.9 Hz and 996 Hz in 3.9 Hz step can be selected. When doubled frequency range is selected (CR10:DFT=1, HFT=0) the frequency is defined by formulas: f1 = CR8 / 0.064 Hz and f2 = CR9 / 0.064 Hz. Thus any frequency between 15.6 Hz and 3984 Hz in 15.6 Hz step can be selected. Control Register CR10 Writing bit POR (7) high puts the MAS9090 in power-on-reset state and all data and control registers are cleared (including the POR bit). Logic low written to bit SCA (6) sets the chip to scan mode. During scan CI is the input and TX is the output. Used only for device testing. High written to bit HPT (5) bypasses the highpass part of the TX bandpass filter. When Bit EXT (4) is set active the two bit output of the ADC is disabled and data is fed from pins CR and DR. Used only for device testing. With bit L0 (3) it is possible to loop internally from TX to RX. Bit L1 (2) permits looping from the expander output to the compressor input. Frequency Range Selection Bits DFT (1) and HFT (0) define the frequency range of the tone generator output. Three modes are possible: halved, standard and doubled with output frequencies from 3.9…996 Hz and 7.8…1992 Hz, 15.6…3984 Hz respectively. Control Register CR11 When bit BE (7) is high it permits the connection of f1 squarewave pulse width modulated (PWM) ring signal to buzzer driver output pin BZ. Signal can be amplitude modulated (AM) with squarewave signal f2. When bit BE is low (buzzer disabled) the state of the output pin BZ is logical inversion of bit BI (6). This works also in power-down state. 26 When buzzer output is enabled (BE = 1) bit BI (6) controls the polarity of the duty cycle selection. BI = 1 means the duty cycle is calculated from the relative width of the logic one. When BI = 0 the duty cycle is calculated from the relative width of the logic zero. Bits BZ5:BZ0 (5:0) define the duty cycle of the PWM squarewave, according to the following formula: duty cycle = CR11(5:0) x 0.78125 %, where CR11 (5:0) is the decimal equivalent of binary value BZ5:BZ0. Control Register CR14 (for testing) Bits AM2:AM0 (7:5) control the analog multiplexer. Different analog test signals can be fed to test pads. Test pads are not wire bonded in production packages. Bits DM2:DM0 (4:2) control the digital multiplexer. Different test signals can be fed to the TX output pin. Bit MUX (1) connects the test outputs to the TX output pin. It is for device testing. Bit EDX (0) enables the TX output continuously. No pull-up resistor is needed when TX pin is the only output for the reading device and EDX is written High. DA9090B.001 January 14, 1998 APPLICATION INFORMATION Typical application of MAS9090 for digital cellular systems DIGITAL BASEBAND RF A/D D/A Modem Equalizer Channel Codec Speech Codec MAS9090 A/D D/A Control Function Memory Display Keyboard Power Typical application circuit of MAS9090 2.7-3.6V (3V mode) or 4.5-5.5V (5V mode) MIC3MIC2MIC1MIC3+ MIC2+ MIC1+ VCC VCCP VCCA GND GNDP GNDA 0V MCLK FS BZ CO SP1SP1+ CI CS CCLK LO SP2SP1+ 30 ohm/50 pF TX RX SPEECH CODEC PROCESSOR MICRO CONTROLLER 512 kHz 8 kHz + - 27 DA9090B.001 January 14, 1998 PACKAGE OUTLINES AND RECOMMENDED LAND PATTERNS 28 LEAD S O TLIN (300 M BO Y) OU E IL D 1.27 TY . P 0.25 0.75 x 45 0.33 0.51 2.35 2.65 17.70 18.10 10.00 10.65 0 - 8 TY . P 0.40 1.27 11.68 7.11 0.10 0.30 0.23 0.32 S ATIN E G PN LA E PCB LAYOUT P1 IN 0.69 1.27 A M A U E E TS IN m LL E S R M N m 44 LEAD TQ O TLIN FP U E 0.80 TYP AL IC 1.60 M AX 0.09 0.20 SEA G PLAN TIN E 0°-7° 1.35 1.45 0.05 0.15 0.30 0.45 0.45 0.75 10.00 TY AL PIC 14.47 10.53 12.00 TYPIC AL PCB LAYOUT 0.55 0.80 ALL M EASU EM TS IN m R EN m 10.00 TYPIC AL 12.00 TY AL PIC 14.47 10.53 7.40 7.60 28 DA9090B.001 January 14, 1998 ORDERING INFORMATION Product Code MAS9090BS MAS9090BS-T MAS9090BJ MAS9090BJ-T Product Low Voltage 14-bit Linear Codec Low Voltage 14-bit Linear Codec Low Voltage 14-bit Linear Codec Low Voltage 14-bit Linear Codec Package SO28 SO28 TQFP44 TQFP44 Tape and Reel Comments Tape and Reel LOCAL DISTRIBUTOR MICRONAS CONTACTS Micronas Semiconductor GmbH Lohweg 29 D-85375 NEUFAHRN, GERMANY Micronas Semiconductor SA Ch. Chapons-des-Prés CH-2022 BEVAIX, SWITZERLAND Micronas Oy Kamreerintie 2, P.O.Box 51 FIN-02771 ESPOO, FINLAND Tel. (08165) 9521 0 Tel. Int. + 49 8165 9521 0 Telefax + 49 8165 9521 99 Tel. (032) 847 0111 Tel. Int. +41 32 847 0111 Telefax +41 32 846 1930 Tel. (09) 80521 Tel. Int. +358 9 80521 Telefax +358 9 8053213 NOTICE Micronas reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micronas assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micronas makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. 29 End of Data Sheet Multimedia ICs MICRONAS Back to Data Sheets