MSP3467G

PRELIMINARY DATA SHEET MICRONAS MSP 34x7G Multistandard Sound Processor Family Edition March 5, 2001 6251-535-2PD MICRONAS MSP 34x7G Contents Page 5 6 6 7 8 9 9 9 9 10 10 10 12 12 12 12 12 13 13 13 13 13 14 14 14 15 15 16 16 16 16 16 16 16 16 18 19 19 19 21 22 23 29 30 30 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.2.1. 2.2.2. 2.2.3. 2.2.4. 2.2.5. 2.3. 2.4. 2.5. 2.5.1. 2.5.2. 2.6. 2.6.1. 2.6.2. 2.7. 2.8. 3. 3.1. 3.1.1. 3.1.2. 3.1.3. 3.1.4. 3.1.4.1. 3.1.4.2. 3.1.4.3. 3.1.4.4. 3.2. 3.3. 3.3.1. 3.3.2. 3.3.2.1. 3.3.2.2. 3.3.2.3. 3.3.2.4. 3.3.2.5. 3.3.2.6. 3.3.2.7. 3.4. 3.5. Title PRELIMINARY DATA SHEET Introduction Features of the MSP 34x7G Family and Differences to MSPD MSP 34x7G Version List MSP 34x7G Versions and their Application Fields Functional Description Architecture of the MSP 34x7G Family Sound IF Processing Analog Sound IF Input Demodulator: Standards and Features Preprocessing of Demodulator Signals Automatic Sound Select Manual Mode Preprocessing for SCART Source Selection and Output Channel Matrix Audio Baseband Processing Automatic Volume Correction (AVC) Quasi-Peak Detector SCART Signal Routing SCART DSP In and SCART Out Select Stand-by Mode Digital Control I/O Pins and Status Change Indication Clock PLL Oscillator and Crystal Specifications Control Interface I2C Bus Interface Internal Hardware Error Handling Description of CONTROL Register Protocol Description Proposals for General MSP 34x7G I2C Telegrams Symbols Write Telegrams Read Telegrams Examples Start-Up Sequence: Power-Up and I2C-Controlling MSP 34x7G Programming Interface User Registers Overview Description of User Registers STANDARD SELECT Register Refresh of STANDARD SELECT Register STANDARD RESULT Register Write Registers on I2C Subaddress 10hex Read Registers on I2C Subaddress 11hex Write Registers on I2C Subaddress 12hex Read Registers on I2C Subaddress 13hex Programming Tips Examples of Minimum Initialization Codes 2 Micronas PRELIMINARY DATA SHEET MSP 34x7G Contents, continued Page 30 30 30 31 31 31 33 33 34 36 38 39 41 41 42 42 42 43 44 46 46 47 48 49 50 51 51 52 53 57 57 58 59 59 60 60 61 61 62 63 63 63 63 65 65 Section 3.5.1. 3.5.2. 3.5.3. 3.5.4. 3.5.5. 3.5.6. 4. 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.2.2. 4.6.2.3. 4.6.2.4. 4.6.3. 4.6.3.1. 4.6.3.2. 4.6.3.3. 4.6.3.4. 4.6.3.5. 4.6.3.6. 4.6.3.7. 4.6.3.8. 4.6.3.9. 5. 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 6. 6.1. 6.2. 6.3. 6.3.1. 6.3.1.1. 6.3.1.2. 6.3.2. 6.3.3. Title B/G-FM (A2 or NICAM) BTSC-Stereo BTSC-SAP with SAP at Loudspeaker Channel FM-Stereo Radio Automatic Standard Detection Software Flow for Interrupt driven STATUS Check Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Analog Input and Output Recommendations Recommendations for Analog Sound IF Input Signal Crystal Recommendations Characteristics General Characteristics Digital Inputs, Digital Outputs Reset Input and Power-Up I2C Bus Characteristics Analog Baseband Inputs and Outputs, AGNDC Sound IF Input Power Supply Rejection Analog Performance Sound Standard Dependent Characteristics Appendix A: Overview of TV Sound Standards NICAM 728 A2 Systems BTSC-Sound System Japanese FM Stereo System (EIA-J) FM Satellite Sound FM-Stereo Radio Appendix B: Manual/Compatibility Mode Demodulator Write and Read Registers for Manual/Compatibility Mode DSP Write and Read Registers for Manual/Compatibility Mode Manual/Compatibility Mode: Description of Demodulator Write Registers Automatic Switching between NICAM and Analog Sound Function in Automatic Sound Select Mode Function in Manual Mode A2 Threshold Carrier-Mute Threshold Micronas 3 MSP 34x7G Contents, continued Page 66 68 69 69 71 71 71 71 72 72 72 72 73 73 73 73 73 73 74 74 74 74 74 75 75 75 75 75 77 77 78 80 80 Section 6.3.4. 6.3.5. 6.3.6. 6.3.7. 6.4. 6.4.1. 6.4.2. 6.4.3. 6.4.4. 6.4.5. 6.4.6. 6.4.7. 6.5. 6.5.1. 6.5.2. 6.5.3. 6.5.4. 6.5.5. 6.5.6. 6.5.7. 6.6. 6.6.1. 6.6.2. 6.7. 6.7.1. 6.7.2. 6.8. 6.9. 7. 7.1. 7.2. 8. 9. Title PRELIMINARY DATA SHEET Register AD_CV Register MODE_REG FIR-Parameter, Registers FIR1 and FIR2 DCO-Registers Manual/Compatibility Mode: Description of Demodulator Read Registers NICAM Mode Control/Additional Data Bits Register Additional Data Bits Register CIB Bits Register NICAM Error Rate Register PLL_CAPS Readback Register AGC_GAIN Readback Register Automatic Search Function for FM-Carrier Detection in Satellite Mode Manual/Compatibility Mode: Description of DSP Write Registers Additional Channel Matrix Modes Volume Modes of SCART1 Output FM Fixed Deemphasis FM Adaptive Deemphasis NICAM Deemphasis Identification Mode for A2 Stereo Systems FM DC Notch Manual/Compatibility Mode: Description of DSP Read Registers Stereo Detection Register for A2 Stereo Systems DC Level Register Demodulator Source Channels in Manual Mode Terrestric Sound Standards SAT Sound Standards Exclusions of Audio Baseband Features Compatibility Restrictions to MSP 34x7D Appendix D: Application Information Phase Relationship of Analog Outputs Application Circuit Appendix E: MSP 34x7G Version History Data Sheet History License Notice: “Dolby Pro Logic” is a trademark of Dolby Laboratories. Supply of this implementation of Dolby Technology does not convey a license nor imply a right under any patent, or any other industrial or intellectual property right of Dolby Laboratories, to use this implementation in any finished end-user or ready-to-use final product. Companies planning to use this implementation in products must obtain a license from Dolby Laboratories Licensing Corporation before designing such products. 4 Micronas PRELIMINARY DATA SHEET MSP 34x7G EIA-J. The MSP 34x7G has optimum stereo performance without any adjustments. All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x7G further simplifies controlling software. Standard selection requires a single I2C transmission only. Note: The MSP 34x7G version has reduced control registers and less functional pins. The remaining registers are software-compatible to the MSP 34x0G. The pinning is compatible to the MSP 34x0G. The MSP 34x7G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The MSP 34x7G can handle very high FM deviations even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China. The ICs are produced in submicron CMOS technology. The MSP 34x7G is available in the following packages: PSDIP52 and PMQFP44. Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the MSP 34x7G version B8 and following versions. 1. Introduction The MSP 34x7G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed in a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x7G. These TV sound processing ICs include versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM-Stereo-Radio standard. Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and Sound IF1 ADC Demodulator Preprocessing Loudspeaker Sound Processing DAC Loudspeaker SCART1 DAC SCART DSP Input Select MONO ADC Prescale Source Select SCART Output Select SCART1 Fig. 1–1: Simplified functional block diagram of MSP 34x7G Micronas 5 MSP 34x7G 1.1. Features of the MSP 34x7G Family and Differences to MSPD Feature (Features not available for MSPD are shaded gray.) 3407 X X X X X X X X X X X 3417 X X X X X X X X X X X X X X X PRELIMINARY DATA SHEET 3427 X X X X X X X X X X 3447 X X X X X X X X X X 3457 X X X X X X X X X X X X X X 3467 X X X X X X X X X X Standard Selection with single I2C transmission Automatic Standard Detection of terrestrial TV standards Automatic Sound Selection (mono/stereo/bilingual), new registers MODUS, STATUS Automatic Carrier Mute function Interrupt output programmable (indicating status change) Loudspeaker channel with volume AVC: Automatic Volume Correction One Stereo SCART (line) input, one Mono input; one Stereo SCART output Complete SCART in/out switching matrix All analog Mono sound carriers including AM-SECAM L All analog FM-Stereo A2 and satellite standards All NICAM standards Simultaneous demodulation of (very) high-deviation FM-Mono and NICAM Adaptive deemphasis for satellite (Wegener-Panda, acc. to ASTRA specification) Demodulation of the BTSC multiplex signal and the SAP channel Alignment free digital DBX noise reduction for BTSC Stereo and SAP Alignment free digital Micronas Noise Reduction (MNR) for BTSC Stereo and SAP BTSC stereo separation (MSP 3427/47G also EIA-J) significantly better than spec. SAP and stereo detection for BTSC system Korean FM-Stereo A2 standard Alignment-free Japanese standard EIA-J Demodulation of the FM-Radio multiplex signal X X X X X X X X X X X X X X X X X X X X X X X X 1.2. MSP 34x7G Version List Version MSP 3407G MSP 3417G MSP 3427G MSP 3447G MSP 3457G MSP 3467G Status available available not confirmed not confirmed not confirmed not confirmed Description FM Stereo (A2) Version NICAM and FM Stereo (A2) Version NTSC Version (A2 Korea, BTSC with Micronas Noise Reduction (MNR), Japanese EIA-J system) NTSC Version (A2 Korea, BTSC with DBX noise reduction, Japanese EIA-J system) Global Stereo Version (all sound standards) Global Mono Version (all sound standards) 6 Micronas PRELIMINARY DATA SHEET MSP 34x7G 1.3. MSP 34x7G Versions and their Application Fields Table 1–1 provides an overview of TV sound standards that can be processed by the MSP 34x7G family. In addition, the MSP 34x7G is able to handle the FMRadio standard. With the MSP 34x7G, a complete multimedia receiver covering all TV sound standards together with terrestrial/cable and satellite radio sound can be built. Table 1–1: TV Stereo Sound Standards covered by the MSP 34x7G IC Family (details see Appendix A) MSP Version 3407 TVSystem B/G 5.5/5.85 L I 6.5/5.85 6.0/6.552 6.5/6.2578125 3407 3417 6.5/6.7421875 D/K 3457 6.5/5.7421875 6.5/5.85 6.5 7.02/7.2 7.38/7.56 etc. 4.5/4.724212 3427, 3447 M/N 4.5 4.5 FM-Radio 3467 10.7 FM-Stereo (A2, D/K3) FM-Mono/NICAM (D/K, NICAM) FM-Mono FM-Stereo SECAM-East PAL Poland China, Hungary Europe Sat. ASTRA Korea Japan USA, Argentina USA, Europe FM-Mono/NICAM AM-Mono/NICAM FM-Mono/NICAM FM-Stereo (A2, D/K1) FM-Stereo (A2, D/K2) PAL SECAM-L PAL SECAM-East PAL Scandinavia, Spain France UK, Hong Kong Slovak. Rep. currently no broadcast Position of Sound Carrier /MHz 5.5/5.7421875 Sound Modulation FM-Stereo (A2) Color System PAL Broadcast e.g. in: Germany 3407 Satellite PAL FM-Stereo (A2) FM-FM (EIA-J) BTSC-Stereo + SAP FM-Stereo Radio NTSC NTSC NTSC, PAL All standards as above, but Mono demodulation only. 33 34 39 MHz 4.5 9 MHz SAW Filter Tuner Sound IF Mixer 1 Loudspeaker Mono Vision Demodulator MSP 34x7G SCART Input 2 SCART1 2 SCART1 SCART Output Composite Video Fig. 1–2: Typical MSP 34x7G application Micronas 7 Source Select SCART DSP Input Select SC1_IN_L SC1_IN_R SCART Output Select 8 Standard Selection AGC ANA_IN1+ D A DEMODULATOR (incl. Carrier Mute) Deemphasis: 50/75 µs, J17 DBX/MNR Panda1 FM/AM Prescale (0Ehex) 2. Functional Description MSP 34x7G Automatic Sound Select FM/AM 0 1 3 Stereo or A/B Loudspeaker Channel Matrix (08hex) AVC Σ Volume D A DACM_L DACM_R (29hex) (00hex) Decoded Standards: − NICAM − A2 − AM − BTSC − EIA-J − SAT − FM-Radio NICAM Deemphasis J17 Prescale (10hex) Stereo or A Beeper Stereo or B 4 (14hex) Standard and Sound Detection I2 C Read Register Quasi-Peak Channel Matrix (0Chex) Quasi-Peak Detector I2C Read Register (19hex) (1Ahex) A D SCART 2 Prescale (0Dhex) SCART1 Channel Matrix (0Ahex) Volume D SCART1_L/R A (07hex) SC1_OUT_L SC1_OUT_R (13hex) PRELIMINARY DATA SHEET MONO_IN (13hex) Fig. 2–1: Signal flow block diagram of the MSP 34x7G (input and output names correspond to pin names). Micronas PRELIMINARY DATA SHEET MSP 34x7G BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP-subcarrier. Processing of the DBX noise reduction or Micronas Noise Reduction (MNR). Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L-R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodulation of the (L-R)-carrier. The demodulator blocks of all MSP 34x7G versions have identical user interfaces. Even completely different systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x7G demodulator blocks are Standard Selection: The controlling of the demodulator is minimized: All parameters, such as tuning frequencies or filter bandwidth, are adjusted automatically by transmitting one single value to the STANDARD SELECT register. For all standards, specific MSP standard codes are defined. Automatic Standard Detection: If the TV sound standard is unknown, the MSP 34x7G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x7G offers a configurable carrier mute feature, which is activated automatically if the TV sound standard is selected by means of the STANDARD SELECT register. If no FM carrier is detected at one of the two MSP demodulator channels, the corresponding demodulator output is muted. This is indicated in the STATUS register. 2.1. Architecture of the MSP 34x7G Family Fig. 2–1 on page 8 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3457G. Other members of the MSP 34x7G family do not have the complete set of features: The demodulator handles only a subset of the standards presented in the demodulator block; NICAM processing is only possible in the MSP 3417G and MSP 3457G (see dashed block in Fig. 2–1). 2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+ and ANA_IN− offer the possibility to connect sound IF (SIF) sources to the MSP 34x7G. The analog-to-digital conversion of the sound IF signal is done by an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The high-pass filter formed by the coupling capacitor at pin ANA_IN1+ (see Section 7. “Appendix D: Application Information” on page 77) is sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filtering is recommended. 2.2.2. Demodulator: Standards and Features The MSP 34x7G is able to demodulate all TV sound standards worldwide including the digital NICAM system. Depending on the MSP 34x7G version, the following demodulation modes can be performed: A2-Systems: Detection and demodulation of two separate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM-Systems: Demodulation and decoding of the NICAM carrier, detection and demodulation of the analog (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum deviation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, AM demodulation of the (L-R)-carrier and detection of the SAP subcarrier. Processing of the DBX noise reduction or Micronas Noise Reduction (MNR). Micronas 9 MSP 34x7G 2.2.3. Preprocessing of Demodulator Signals The NICAM signals must be processed by a deemphasis filter and adjusted in level. The analog demodulated signals must be processed by a deemphasis filter, adjusted in level, and dematrixed. The correct deemphasis filters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/ AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically by the Automatic Sound Selection. PRELIMINARY DATA SHEET – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language A (on left and right). – “Stereo or B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains language B (on left and right). Fig. 2–2 and Table 2–2 show the source channel assignment of the demodulated signals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the 2nd FM carrier, the L-R signal of the MPX carrier, or the SAP signal. 2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identification information in the STATUS register. No I2C interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono-compatible standards (standards that have the same FM-Mono carrier) automatically and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these standards. The same action is performed for the standards: D/K1-FM, D/K2-FM, D/K3-FM and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x7G automatically falls back from digital NICAM sound to analog FM or AM mono. Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on. primary channel primary channel secondary channel FM/AM Prescale FM/AM 0 LS Ch. Matrix Source Select NICAM A NICAM Automatic Sound Select Stereo or A/B 1 Stereo or A 3 Output-Ch. matrices must be set once to stereo. NICAM B Prescale Stereo or B 4 Fig. 2–2: Source channel assignment of demodulated signals in Automatic Sound Select Mode 2.2.5. Manual Mode Fig. 2–3 shows the source channel assignment of demodulated signals in case of manual mode. If manual mode is required, more information can be found in Section 6.7. “Demodulator Source Channels in Manual Mode” on page 75. FM/AM FM-Matrix FM/AM 0 LS Ch. Matrix Source Select To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig. 2–2). By choosing one of the four demodulator channels, the preferred sound mode can be selected for each of the output channels (loudspeaker, headphone, etc.). This is done by means of the Source Select registers. The following source channels of demodulated sound are defined: – “FM/AM” channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). – “Stereo or A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broadcast, it contains both languages A (left) and B (right). secondary channel Prescale NICAM A NICAM NICAM (Stereo or A/B) 1 Output-Ch. matrices must be set according to the standard. NICAM B Prescale Fig. 2–3: Source channel assignment of demodulated signals in Manual Mode 10 Micronas PRELIMINARY DATA SHEET MSP 34x7G Table 2–1: Performed actions of the Automatic Sound Selection Selected TV Sound Standard B/G-FM, D/K-FM, M-Korea, and M-Japan B/G-NICAM, L-NICAM, I-NICAM, D/K-NICAM Performed Actions Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K3-FM, and D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and nonaudible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2–2. Detection of the SAP carrier. In the absence of SAP, the MSP switches to BTSC-stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2–2). BTSC-STEREO, FM Radio M-BTSC-SAP Table 2–2: Sound modes for the demodulator source channels with Automatic Sound Select Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard M-Korea B/G-FM D/K-FM M-Japan Selected MSP Standard Code3) 02 03, 081) 04, 05, 07, 0B1) 30 Broadcasted Sound Mode MONO STEREO BILINGUAL: Languages A and B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) Mono Stereo Right = B analog Mono analog Mono analog Mono analog Mono Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo Mono Stereo Left = A Right = B analog Mono NICAM Mono NICAM Stereo Left = NICAM A Right = NICAM B Mono Stereo Mono Stereo Left = Mono Right = SAP Left = Mono Right = SAP Mono Stereo Mono Stereo A analog Mono NICAM Mono NICAM Stereo NICAM A Mono Stereo Mono Stereo Mono Mono Mono Stereo Mono Stereo B analog Mono NICAM Mono NICAM Stereo NICAM B Mono Stereo Mono Stereo SAP SAP Mono Stereo 08, 032) 09 0A 0B, 042), 052) 0C, 0D NICAM not available or error rate too high MONO STEREO BILINGUAL: Languages A and B 20, 21 MONO STEREO 20 BTSC 21 MONO + SAP STEREO + SAP MONO + SAP STEREO + SAP FM Radio 40 MONO STEREO 1) 2) 3) The Automatic Sound Select process will automatically switch to the mono compatible analog standard. The Automatic Sound Select process will automatically switch to the mono compatible digital standard. The MSP Standard Codes are defined in Table 3–7 on page 18. Micronas 11 MSP 34x7G 2.3. Preprocessing for SCART The SCART input need only be adjusted in level by means of the SCART prescale register. PRELIMINARY DATA SHEET 2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low level inputs. The decay time is programmable by means of the AVC register (see page 27). For input signals ranging from −24 dBr to 0 dBr, the AVC maintains a fixed output level of −18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input/output. This is – SCART input/output 0 dBr = 2.0 Vrms – Loudspeaker output 0 dBr = 1.4 Vrms output level [dBr] −18 −24 −30 −24 −18 −12 −6 2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source channels or SCART) to the desired output channels (loudspeaker, etc.). All input and output signals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the sound mode can be set to sound A, sound B, stereo, or mono by means of the output channel matrix. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. 0 input level [dBr] Fig. 2–4: Simplified AVC characteristics 2.5.2. Quasi-Peak Detector The quasi-peak readout register can be used to read out the quasi-peak level of any input source. The feature is based on following filter time constants: attack time: 1.3 ms decay time: 37 ms 12 Micronas PRELIMINARY DATA SHEET MSP 34x7G 2.7. Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I2C-bus by means of the ACB register (see page 28). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high impedance by means of the MODUS register (see page 21). In this mode, the pins can be used as input. The current state can be read out of the STATUS register (see page 22). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes polling unnecessary; I2C-bus interactions are reduced to a minimum (see STATUS register on page 22 and MODUS register on page 21). 2.6. SCART Signal Routing 2.6.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include switching facilities. The switches are controlled by the ACB user register (see page 28). 2.6.2. Stand-by Mode If the MSP 34x7G is switched off by first pulling STANDBYQ low and then (after >1 µs delay) switching off DVSUP and AVSUP, but keeping AHVSUP (‘Stand-by’-mode), the SCART switches maintain their position and function. This allows the copying from SCART-input to SCART-output in the TV set’s stand-by mode. In case of power on or starting from stand-by (switching on the DVSUP and AVSUP, RESETQ going high 2 ms later), all internal registers except the ACB register (page 28) are reset to the default configuration (see Table 3–5 on page 17). The reset position of the ACB register becomes active after the first I2C transmission into the Baseband Processing part. By transmitting the ACB register first, the reset state can be redefined. 2.8. Clock PLL Oscillator and Crystal Specifications The MSP 34x7G derives all internal system clocks from the 18.432-MHz oscillator. In NICAM mode, the clock is phase-locked to the corresponding source. For proper performance, the MSP clock oscillator requires a 18.432-MHz crystal. Note, that for the phase-locked mode (NICAM), crystals with tighter tolerance are required. Micronas 13 MSP 34x7G 3. Control Interface 3.1. I2C Bus Interface The MSP 34x7G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 34x7G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x7G responds to different device addresses. A device address pair is defined as a write address and a read address (see Table 3–1). Writing is done by sending the write device address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address and reading two bytes of data. Refer to Section 3.1.3. for the I2C bus protocol and to Section 3.4. “Programming Tips” on page 30 for proposals of MSP 34x7G I2C telegrams. See Table 3–2 for a list of available subaddresses. Besides the possibility of hardware reset, the MSP can also be reset by means of the RESET bit in the CONTROL register by the controller via I2C bus. Due to the architecture of the MSP 34x7G, the IC cannot react immediately to an I2C request. The typical Table 3–1: I2C Bus Device Addresses ADR_SEL Mode MSP device address Low (connected to DVSS) Write 80hex Read 81hex High (connected to DVSUP) Write 84hex Read 85hex PRELIMINARY DATA SHEET response time is about 0.3 ms. If the MSP cannot accept another byte of data (e.g. while servicing an internal interrupt), it holds the clock line I2C_CL low to force the transmitter into a wait state. The I2C Bus Master must read back the clock line to detect when the MSP is ready to receive the next I2C transmission. The positions within a transmission where this may happen are indicated by ’Wait’ in Section 3.1.3. The maximum wait period of the MSP during normal operation mode is less than 1 ms. 3.1.1. Internal Hardware Error Handling In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time period elapses, the MSP releases data and clock lines. Indication and solving the error status: To indicate the error status, the remaining acknowledge bits of the actual I2C-protocol will be left high. Additionally, bit[14] of CONTROL is set to one. The MSP can then be reset via the I2C bus by transmitting the RESET condition to CONTROL. Indication of reset: Any reset, even caused by an unstable reset line etc., is indicated in bit[15] of CONTROL. A general timing diagram of the I2C bus is shown in Fig. 4–21 on page 49. Left Open Write 88hex Read 89hex Table 3–2: I2C Bus Subaddresses Name CONTROL WR_DEM RD_DEM WR_DSP RD_DSP Binary Value 0000 0000 0001 0000 0001 0001 0001 0010 0001 0011 Hex Value 00 10 11 12 13 Mode Read/Write Write Write Write Write Function Write: Software reset of MSP (see Table 3–3) Read: Hardware error status of MSP write address demodulator read address demodulator write address DSP read address DSP 14 Micronas PRELIMINARY DATA SHEET MSP 34x7G 3.1.2. Description of CONTROL Register Table 3–3: CONTROL as a Write Register Name CONTROL Subaddress 00hex Bit[15] (MSB) 1 : RESET 0 : normal Bits[14:0] 0 Table 3–4: CONTROL as a Read Register Name CONTROL Subaddress 00hex %LW>@ 06% RESET status after last reading of CONTROL: 0 : no reset occured 1 : reset occured Bit>@ Internal hardware status: 0 : no error occured 1 : internal error occured BitV>@ not of interest Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be read once to be reset. 3.1.3. Protocol Description Write to DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte ACK data-byte ACK P high low high low Read from DSP or Demodulator S Wait write device address ACK sub-addr ACK addr-byte ACK addr-byte ACK S high low read device address Wait ACK data-byte- ACK data-byte NAK P high low Write to Control Register S Wait write device address ACK sub-addr ACK data-byte ACK data-byte ACK P high low Read from Control Register S Wait write device address ACK 00hex ACK S read device address Wait ACK data-byte- ACK data-byte NAK P high low Note: S = P= ACK = NAK = I2C-Bus Start Condition from master I2C-Bus Stop Condition from master Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller, dark gray) Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MSP indicating internal error state Wait = I2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms Micronas 15 MSP 34x7G PRELIMINARY DATA SHEET I2C_DA S I2C_CL 1 0 P Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high) 3.1.4. Proposals for General MSP 34x7G I2C Telegrams 3.1.4.1. Symbols daw dar < > aa dd write device address (80hex, 84hex or 88hex) read device address (81hex, 85hex or 89hex) Start Condition Stop Condition Address Byte Data Byte 3.2. Start-Up Sequence: Power-Up and I2C-Controlling After POWER-ON or RESET (see Fig. 4–20), the IC is in an inactive state. All registers are in the Reset position (see Table 3–5 and Table 3–6), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary. 3.3. MSP 34x7G Programming Interface 3.3.1. User Registers Overview 3.1.4.2. Write Telegrams write to CONTROL register write data into demodulator write data into DSP 3.1.4.3. Read Telegrams read data from CONTROL register