v3.0
HiRel FPGAs
Fe a t ur es
• Low-Power 0.8µ CMOS Technology
• Highly Predictable Performance with 100% Automatic
Placement and Routing
• Device Sizes from 1,200 to 20,000 Gates
• Up to 6 Fast, Low-Skew Clock Networks
• Up to 202 User-Programmable I/O Pins
•
•
•
•
•
•
•
•
•
32 0 0D X Fe a t ur es
• 100 MHz System Logic Integration
• Highest Speed FPGA SRAM, up to 2.5 kbits Configurable
Dual-Port SRAM
• Fast Wide-Decode Circuitry
• Low-Power 0.6µ CMOS Technology
More Than 500 Macro Functions
Up to 1,276 Dedicated Flip-Flops
I/O Drive to 10 mA
Devices Available to DSCC SMD
CQFP and CPGA Packaging
Nonvolatile, User Programmable
Logic Fully Tested Prior to Shipment
100% Military Temperature Tested (–55°C to +125°C)
QML Certified Devices
12 0 0X L Fe at ure s
• Pin for Pin Compatible with ACT 2
• System Performance to 50 MHz over Military Temperature
• Low-Power 0.6µ CMOS Technology
A CT 2 Fe at ure s
• Best-Value, High-Capacity FPGA Family
• System Performance to 40 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
• Proven Reliability Data Available
• Successful Military/Avionics Supplier for Over 10 Years
A CT 1 Fe at ure s
A CT 3 Fe at ure s
• Highest-Performance, Highest-Capacity FPGA Family
• System Performance to 60 MHz over Military Temperature
• Lowest-Cost FPGA Family
• System Performance to 20 MHz over Military Temperature
• Low-Power 1.0µ CMOS Technology
Pr od uc t F am i l y P r o f i l e (more devices on page 2)
Family
Device
3200DX
ACT 3
1200XL
A32100DX
A32200DX
A1425A
A1460A
A14100A
A1280XL
Capacity
System Gates
Logic Gates
SRAM Bits
15,000
10,000
2,048
30,000
20,000
2,560
3,750
2,500
NA
9,000
6,000
NA
15,000
10,000
NA
12,000
8,000
Logic Modules
S-Modules
C-Modules
Decode
1,362
700
662
20
2,414
1,230
1,184
24
310
160
150
NA
848
432
416
NA
1,377
697
680
NA
1,232
624
608
NA
Flip-Flops (Maximum)
738
1,276
435
976
1,493
998
User I/Os (Maximum)
152
202
100
168
228
140
55 MHz
55 MHz
60 MHz
60 MHz
60 MHz
50 MHz
84
208, 256
133
132
207
196
257
256
176
172
Performance
System Speed (maximum)
Packages (by Pin Count)
CPGA
CQFP
J an u a r y 2 0 0 0
© 2000 Actel Corporation
1
Pr od uc t F am i l y P r o f i l e
Family
Device
ACT 2
ACT 1
A1240A
A1280A
A1010B
A1020B
Capacity
System Gates
Logic Gates
SRAM Bits
6,000
4,000
NA
12,000
8,000
NA
1,800
1,200
NA
3,000
2,000
NA
Logic Modules
S-Modules
C-Modules
Decode
684
348
336
NA
1,232
624
608
NA
295
—
295
NA
547
—
547
NA
Flip-Flops (maximum)
568
998
147
273
User I/Os (maximum)
104
140
57
69
Packages (by pin count)
CPGA
CQFP
132
—
176
172
84
—
84
84
40 MHz
40 MHz
20 MHz
20 MHz
Performance
System Speed (maximum)
H i gh - R el i a bi l i t y , L o w - Ri s k So l ut i on
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 Failures-In-Time (FITs),
corresponding to a useful life of more than 40 years. Actel
FPGAs have been production proven, with more than five
million devices shipped and more than one trillion antifuses
manufactured. Actel devices are fully tested prior to
shipment, with an outgoing defect level of less than 100 ppm.
(Further reliability data is available in the Actel Device
Reliability Report, at http://www.actel.com/hirel).
junction temperatures. Actel’s non-PLD architecture delivers
lower dynamic operating current. Our reliability tests show a
very low failure rate of 6.6 FITs at 90°C junction temperature
with no degradation in AC performance. Special stress testing
at wafer test eliminates infant mortalities prior to packaging.
M ini m ized S ecu ri ty R is k
B en ef i t s
Reverse engineering of programmed Actel devices from
optical or electrical data is extremely difficult. Programmed
antifuses cannot be identified from a photograph or by using
an SEM. The antifuse map cannot be deciphered either
electrically or by microprobing. Each device has a silicon
signature that identifies its origins, down to the wafer lot and
fabrication facility.
Mi nim i zed C os t Ri sk
M ini m ized T es ti ng Ri sk
With Actel’s line of development tools, designers can produce
as many chips as they choose for just the cost of the device
itself. There will be no NRE charges to cut into the
development budget each time a new design is tried.
Unprogrammed Actel parts are extensively tested at the
factory. Routing tracks, logic modules, and programming,
debug and test circuits are 100 percent tested before
shipment. AC performance is ensured by special speed path
tests, and programming circuitry is verified on test antifuses.
During the programming process, an algorithm is run to
ensure that all antifuses are correctly programmed. In
addition, Actel’s Silicon Explorer diagnostic tool uses
ActionProbe circuitry, allowing 100 percent observability of
all internal nodes to check and debug the design.
M i n im i z e d T i m e R is k
After the design is entered, placement and routing is
automatic, and programming the device takes only about 5 to
15 minutes for an average design. Designers save time in the
design entry process by using tools with which they are
familiar.
Mi nim i zed R el iabi li ty R is k
A c t e l FP G A De sc r i p t i o n
The PLICE antifuse is a one-time programmable, nonvolatile
connection. Since Actel devices are permanently
programmed, no downloading from EPROM or SRAM storage
is required. Inadvertent erasure is impossible, and there is no
need to reload the program after power disruptions.
Fabrication using a low-power CMOS process means cooler
The Actel families of FPGAs offer a variety of packages,
speed/performance characteristics, and processing levels for
use in all high reliability and military applications. Devices
are implemented in a silicon gate, two-level metal CMOS
process, utilizing Actel’s PLICE antifuse technology. This
2
H iR e l F PG A s
unique architecture offers gate array flexibility, high
performance, and quick turnaround through user
programming. Device utilization is typically 95 percent of
available logic modules. All Actel devices include on-chip
clock drivers and a hard-wired distribution network.
A CT 3 De sc r i p t i o n
User-definable I/Os are capable of driving at both TTL and
CMOS drive levels. Available packages for the military are the
Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid
Array (CPGA). See the “Product Plan” section on page 6 for
details.
The ACT 3 family is the third-generation Actel FPGA
family. This family offers the highest-performance and
highest-capacity devices, ranging from 2,500 to 10,000 gates,
with system performance up to 60 MHz over the military
temperature range. The devices have four clock distribution
networks, including dedicated array and I/O clocks. In
addition, the ACT 3 family offers the highest I/O-to-gate ratio
available. ACT 3 devices are manufactured using 0.8µ CMOS
technology.
Q M L C e r t i f i c at i on
12 0 0X L / 32 00 D X D e sc r i p t i o n
Actel has achieved full QML certification, demonstrating
that quality management, procedures, processes, and
controls are in place and comply with MIL-PRF-38535, the
performance specification used by the Department of
Defense for monolithic integrated circuits. QML
certification is a good example of Actel's commitment to
supplying the highest quality products for all types of
high-reliability, military and space applications.
3200DX and 1200XL FPGAs were designed to integrate
system logic which is typically implemented in multiple
CPLDs, PALs, and FPGAs. These devices provide the features
and performance required for today’s complex, high-speed
digital logic systems. The 3200DX family offers the industry’s
fastest dual-port SRAM for implementing fast FIFOs, LIFOs,
and temporary data storage.
Many suppliers of microelectronics components have
implemented QML as their primary worldwide business
system. Appropriate use of this system not only helps in the
implementation of advanced technologies, but also allows
for a quality, reliable and cost-effective logistics support
throughout QML products’ life cycles.
A CT 2 De sc r i p t i o n
The ACT 2 family is the second-generation Actel FPGA family.
This family offers the best-value, high-capacity devices,
ranging from 4,000 to 8,000 gates, with system performance
up to 40 MHz over the military temperature range. The
devices have two routed array clock distribution networks.
ACT 2 devices are manufactured using 1.0µ CMOS technology.
D ev el o pm en t T oo l S up po r t
The HiRel devices are fully supported by Actel’s line of FPGA
development tools, including the Actel DeskTOP series and
Designer Advantage tools. The Actel DeskTOP Series is an
integrated design environment for PCs that includes design
entry, simulation, synthesis, and place and route tools.
Designer Advantage is Actel’s suite of FPGA development
point tools for PCs and Workstations that includes the
ACTgen Macro Builder, Designer with DirectTime timing
driven place and route and analysis tools, and device
programming software.
A CT 1 De sc r i p t i o n
The ACT 1 family is the first Actel FPGA family and the first
antifuse-based FPGA. This family offers the lowest-cost logic
integration, with devices ranging from 1,200 to 2,000 gates,
with system performance up to 20 MHz over the military
temperature range. The devices have one routed array clock
distribution network. ACT 1 devices are manufactured using
1.0µ CMOS technology.
In addition, the HiRel devices contain ActionProbe circuitry
that provides built-in access to every node in a design,
enabling 100 percent real-time observation and analysis of a
device’s internal logic nodes without design iteration. The
probe circuitry is accessed by Silicon Explorer, an easy to use
integrated verification and logic analysis tool that can sample
data at 100 MHz (asynchronous) or 66 MHz (synchronous).
Silicon Explorer attaches to a PC’s standard COM port,
turning the PC into a fully functional 18 channel logic
analyzer. Silicon Explorer allows designers to complete the
design verification process at their desks and reduces
verification time from several hours per cycle to a few
seconds.
3
M i l i t a r y D e v i c e Or de r i n g I n f o r m a t i on
A14100
A
–
1
CQ
256
B
Application (Temperature Range)
C = Commercial (0 to +70°C)
M = Military (–55 to +125°C)
B = MIL-STD-883 Class B
E = Extended Flow (Space Level)
Package Lead Count
Package Type
CQ = Ceramic Quad Flat Pack (CQFP)
PG = Ceramic Pin Grid Array (CPGA)
Speed Grade
Std = Standard Speed
–1 = Approximately 15% faster than Standard
Device Revision
Part Number
A1010 =
A1020 =
A1240 =
A1280 =
A1425 =
A1460 =
A14100 =
A32100 =
A32200 =
4
1,200 Gates—ACT 1
2,000 Gates—ACT 1
4,000 Gates—ACT 2
8,000 Gates—ACT 2/1200XL
2,500 Gates—ACT 3
6,000 Gates—ACT 3
10,000 Gates—ACT 3
10,000 Gates—3200DX
20,000 Gates—3200DX
H iR e l F PG A s
D ES C SM D / A ct el P ar t N um b e r C r os s R e f e r en ce
Actel Part Number
DSCC SMD
DSCC SMD
(Gold Leads)
(Gold Leads)
(Solder Dipped)
A1010B-PG84B
5962-9096403MXC
5962-9096403MXA
A1010B-1PG84B
5962-9096404MXC
5962-9096404MXA
A1020B-PG84B
5962-9096503MUC
5962-9096503MUA
A1020B-1PG84B
5962-9096504MUC
5962-9096504MUA
A1020B-CQ84B
5962-9096503MTC
5962-9096503MTA
A1020B-1CQ84B
5962-9096504MTC
5962-9096504MTA
A1240A-PG132B
5962-9322101MXC
5962-9322101MXA
A1240A-1PG132B
5962-9322102MXC
5962-9322102MXA
A1280A-PG176B
5962-9215601MXC
5962-9215601MXA
A1280A-1PG176B
5962-9215602MXC
5962-9215602MXA
A1280A-CQ172B
5962-9215601MYC
5962-9215601MYA
A1280A-1CQ172B
5962-9215602MYC
5962-9215602MYA
A1425A-PG133B
5962-9552001MXC
N/A
A1425A-1PG133B
5962-9552002MXC
N/A
A1425A-CQ132B
5962-9552001MYC
N/A
A1425A-1CQ132B
5962-9552002MYC
N/A
A1460A-PG207B
5962-9550801MXC
N/A
A1460A-1PG207B
5962-9550802MXC
N/A
A1460A-CQ196B
5962-9550801MYC
N/A
A1460A-1CQ196B
5962-9550802MYC
N/A
A14100A-PG257B
5962-9552101MXC
N/A
A14100A-1PG257B
5962-9552102MXC
N/A
A14100A-CQ256B
5962-9552101MYC
N/A
A14100A-1CQ256B
5962-9552102MYC
N/A
A32100DX-CQ84B
5962-9875901QXC
N/A
A32100DX-1CQ84B
5962-9857902QXC
N/A
A32200DX-CQ256B
5962-9952701QXC
N/A
A32200DX-1CQ256B
5962-9952702QXC
N/A
A32200DX-CQ208B
5962-9952701QYC
N/A
A32200DX-1CQ208B
5962-9952702QYC
N/A
5
Pr od uc t P l a n
Speed Grade
Application
Std
–1*
C
M
B
E
✔
✔
✔
✔
✔
—
208-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
—
256-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
—
132-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
133-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
196-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
207-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
256-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
257-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
172-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
—
176-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
—
✔
✔
✔
✔
✔
—
172-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
176-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
84-pin Ceramic Quad Flat Pack (CQFP)
✔
✔
✔
✔
✔
✔
84-pin Ceramic Pin Grid Array (CPGA)
✔
✔
✔
✔
✔
✔
3 2 00 D X F a m i l y
A32100DX Device
84-pin Ceramic Quad Flat Pack (CQFP)
A32200DX Device
A C T 3 F am i l y
A1425A Device
A1460A Device
A14100A Device
1 2 00 X L F am i l y
A1280XL Device
A C T 2 F am i l y
A1240A Device
132-pin Ceramic Pin Grid Array (CPGA)
A1280A Device
A C T 1 F am i l y
A1010B Device
84-pin Ceramic Pin Grid Array (CPGA)
A1020B Device
Applications:
6
C
M
B
E
=
=
=
=
Commercial
Military
MIL-STD-883
Extended Flow
Availability: ✔ = Available
— = Not Planned
*Speed Grade: –1 = Approx. 15% faster than Standard
H iR e l F PG A s
32 0 0D X De v i ce R es ou r c es
User I/Os
FPGA
Device Type
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
84-pin
208-pin
256-pin
A32100DX
1,362
10,000
60
—
—
A32200DX
2,414
20,000
—
176
202
A CT 3 De vi c e Re s ou r c es
User I/Os
FPGA
Device Type
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
CPGA
132-pin
196-pin
256-pin
133-pin
207-pin
257-pin
A1425A
310
2,500
100
—
—
100
—
—
A1460A
848
6,000
—
168
—
—
168
—
A14100A
1,377
10,000
—
—
228
—
—
228
12 0 0X L De vi c e Re so u r ce s
User I/Os
CPGA
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
FPGA
Device Type
172-pin
176-pin
A1280XL
1,232
8,000
140
140
A CT 2 De vi c e Re s ou r c es
User I/Os
FPGA
Device Type
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
CPGA
172-pin
132-pin
176-pin
A1240A
684
4,000
—
104
—
A1280A
1,232
8,000
140
—
140
A CT 1 De vi c e Re s ou r c es
User I/Os
CPGA
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
FPGA
Device Type
84-pin
84-pin
A1010B
295
1,200
—
57
A1020B
547
2,000
69
69
7
A ct e l M I L - ST D - 88 3 Pr od uc t F l ow
883—Class B
Requirement
Step
Screen
883 Method
1.
Internal Visual
2010, Test Condition B
100%
2.
Temperature Cycling
1010, Test Condition C
100%
3.
Constant Acceleration
2001, Test Condition D or E,
Y1, Orientation Only
100%
4.
Seal
a. Fine
b. Gross
1014
5.
Visual Inspection
2009
100%
6.
Pre-Burn-In
Electrical Parameters
In accordance with applicable Actel
device specification
100%
7.
Burn-in Test
1015, Condition D,
160 hours @ 125°C or 80 hours @ 150°C
100%
8.
Interim (Post-Burn-In)
Electrical Parameters
In accordance with applicable Actel
device specification
100%
9.
Percent Defective Allowable
5%
10.
Final Electrical Test
In accordance with applicable Actel
device specification, which includes a, b, and c:
a. Static Tests
(1) 25°C
(Subgroup 1, Table I)
(2) –55°C and +125°C
(Subgroups 2, 3, Table I)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table I)
(2) –55°C and +125°C
(Subgroups 8A and 8B, Table I)
11.
Note:
8
100%
100%
All Lots
100%
5005
5005
100%
5005
5005
c. Switching Tests at 25°C
(Subgroup 9, Table I)
5005
100%
External Visual
2009
100%
When Destructive Physical Analysis (DPA) is performed on Class B devices, the step coverage requirement as specified in Method 2018
must be waived.
H iR e l F PG A s
A ct e l E xt e n de d F l o w 1
Step
Screen
1.
Wafer Lot Acceptance2
Method
3
Requirement
5007 with Step Coverage Waiver
All Lots
2011, Condition D
Sample
2010, Condition A
100%
2.
Destructive In-Line Bond Pull
3.
Internal Visual
4.
Serialization
5.
Temperature Cycling
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
100%
7.
Particle Impact Noise Detection
2020, Condition A
100%
8.
Radiographic
2012 (one view only)
100%
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
100%
10.
Burn-in Test
1015, Condition D, 240 hours @ 125°C minimum
100%
11.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
12.
Reverse Bias Burn-In
1015, Condition C, 72 hours @ 150°C minimum
100%
13.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
14.
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25°C
15.
Final Electrical Test
In accordance with Actel applicable device specification
which includes a, b, and c:
a. Static Tests
(1) 25°C
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
16.
100%
All Lots
100%
100%
5005
5005
100%
5005
5005
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
5005
100%
Seal
1014
100%
2009
100%
a. Fine
b. Gross
17.
External Visual
Notes:
1. Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is
compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow
incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004
are shown in notes 2 and 3 below.
2. Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.
3. MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing,
and this requirement must be waived in its entirety.
9
A bs ol u t e M ax i m u m Ra t i n gs 1
R ec o m m en d ed O pe r a t i ng C on d i t i o ns
Free air temperature range
Symbol
Parameter
Parameter
Limits
Units
VCC
DC Supply Voltage2, 3, 4
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCC +0.5
V
VO
Output Voltage
–0.5 to VCC +0.5
V
IIO
I/O Source Sink
Current5
±20
mA
TSTG
Storage Temperature
–65 to +150
°C
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings”
may cause permanent damage to the device. Exposure to
absolute maximum rated conditions for extended periods may
affect device reliability. Devices should not be operated outside
the recommended operating conditions.
2. VPP = VCC , except during device programming.
3. VSV = VCC , except during device programming.
4. VKS = GND , except during device programming.
5. Device inputs are normally high impedance and draw extremely
low current. However, when input voltage is greater than VCC +
0.5V or less than GND – 0.5V, the internal protection diode will be
forward biased and can draw excessive current.
Commercial
Military
Units
Temperature
Range1
0 to +70
–55 to +125
°C
Power Supply
Tolerance2
±5
±10
%VCC
Notes:
1. Ambient temperature (TA) is used for commercial and
industrial; case temperature (TC) is used for military.
2. All power supplies must be in the recommended operating range.
For more information, refer to the Power-Up Design Considerations
application note at http://www.actel.com/appnotes.
El e c t r i c al S p ec i f i c at i o n s
Commercial
Symbol
Parameter
Test Condition
Min.
VOH1, 2
HIGH Level Output
IOH = –4 mA (CMOS)
IOH = –6 mA (CMOS)
Max.
Max.
V
IOL = +6 mA (CMOS)
VIH
HIGH Level Input
TTL Inputs
2.0
VCC + 0.3
VIL
LOW Level Input
TTL Inputs
–0.3
IIN
Input Leakage
VI = VCC or GND
IOZ
3-state Output Leakage
VO = VCC or GND
CIO
I/O Capacitance3, 4
ICC(S)
Standby VCC Supply Current VI = VCC or GND, IO = 0 mA
0.33
0.4
V
2.0
VCC + 0.3
V
0.8
–0.3
0.8
V
–10
+10
–10
+10
µA
–10
+10
–10
+10
µA
10
10
pF
ACT 1
3
20
mA
ACT 2/3/1200XL/3200DX
2
20
mA
See the “Power Dissipation” section on page 11.
Notes:
1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required.
2. Tested one output at a time, VCC = min.
3. Not tested; for information only.
4. VOUT = 0V, f = 1 MHz
10
Units
V
3.84
LOW Level Output
Dynamic VCC Supply Current
Min.
3.7
VOL1, 2
ICC(D)
Military
H iR e l F PG A s
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
The device junction to case thermal characteristic is θjc, and
the junction to ambient air characteristic is θja. The thermal
characteristics for θja are shown with two different air flow
rates.
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a CPGA 176-pin package at military
temperature is as follows:
– 125°C = 1.1 W
Max.
junction temp. (°C) – Max. military temp.- = 150°C
---------------------------------------------------------------------------------------------------------------------------------------------------23°C/W
θ ja (°C/W)
Pin Count
θjc
θja
Still Air
θja
300 ft/min
Units
Ceramic Pin Grid Array
84
132
133
176
207
257
6.0
4.8
4.8
4.6
3.5
2.8
33
25
25
23
21
15
20
16
15
12
10
8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Ceramic Quad Flat Pack
84
132
172
196
256
7.8
7.2
6.8
6.4
6.2
40
35
25
23
20
30
25
20
15
10
°C/W
°C/W
°C/W
°C/W
°C/W
Package Type
Po w e r D i s s i pa t i o n
Gener al P ow er E quat i on
P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N +
IOH * (VCC – VOH) * M
The power due to standby current is typically a small
component of the overall power. Standby power is calculated
below for commercial, worst-case conditions.
where:
Family
ICC
VCC
Power
ICCstandby is the current flowing when no inputs or outputs
are changing.
ACT 3
2 mA
5.25V
10.5 mW
1200XL/3200DX
2 mA
5.25V
10.5 mW
ICCactive is the current flowing due to CMOS switching.
ACT 2
2 mA
5.25V
10.5 mW
IOL, IOH are TTL sink/source currents.
ACT 1
3 mA
5.25V
15.8 mW
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
Accurate values for N and M are difficult to determine
because they depend on the family type, on the design, and on
the system I/O. The power can be divided into two
components—static and active.
S tat i c P ow er Co m ponen t
Actel FPGAs have small static power components that result
in power dissipation lower than that of PALs or PLDs. By
integrating multiple PALs or PLDs into one FPGA, an even
greater reduction in board-level power dissipation can be
achieved.
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33V will generate 42 mW with all
outputs driving low, and 140 mW with all outputs driving high.
Ac ti ve P ower Com po nent
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totempole current in CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
11
can be combined with frequency and voltage to represent
active power dissipation.
E quiv al ent C apac it ance
The power dissipated by a CMOS circuit can be expressed by
Equation 1:
Power (uW) = CEQ * VCC2 * F
(1)
where:
CEQ
= Equivalent capacitance in pF
VCC
= Power supply in volts (V)
F
= Switching frequency in MHz
Equivalent capacitance is calculated by measuring ICCactive
at a specified frequency and voltage for each circuit
component of interest. Measurements are made over a range
of frequencies at a fixed value of VCC. Equivalent capacitance
is frequency independent so that the results can be used over
a wide range of operating conditions. Equivalent capacitance
values are shown below.
CE Q Val ues f or Act el FP G A s
1200XL
ACT 3 3200DX ACT 2 ACT 1
Modules (CEQM)
6.7
5.2
5.8
3.7
Input Buffers (CEQI)
7.2
11.6
12.9
22.1
10.4
23.8
23.8
31.2
Output Buffers (CEQO)
Routed Array Clock
Buffer Loads (CEQCR)
1.6
3.5
3.9
m
= Number of logic modules switching at fm
n
= Number of input buffers switching at fn
p
= Number of output buffers switching at fp
q1
= Number of clock loads on the first routed
array clock (all families)
q2
= Number of clock loads on the second routed
array clock (ACT 2, 1200XL, 3200DX, ACT 3
only)
r1
= Fixed capacitance due to first routed array
clock (all families)
r2
= Fixed capacitance due to second routed array
clock (ACT 2, 1200XL, 3200DX, ACT 3 only)
s1
= Fixed number of clock loads on the dedicated
array clock (ACT 3 only)
s2
= Fixed number of clock loads on the dedicated
I/O clock (ACT 3 only)
CEQM
= Equivalent capacitance of logic modules in pF
CEQI
= Equivalent capacitance of input buffers in pF
CEQO
= Equivalent capacitance of output buffers
in pF
CEQCR
= Equivalent capacitance of routed array clock
in pF
CEQCD
= Equivalent capacitance of dedicated array
clock in pF
CEQCI
= Equivalent capacitance of dedicated I/O clock
in pF
CL
= Output lead capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
(all families)
fq2
= Average second routed array clock rate in
MHz (ACT 2, 1200XL, 3200DX, ACT 3 only)
fs1
= Average dedicated array clock rate in MHz
(ACT 3 only)
fs2
= Average dedicated I/O clock rate in MHz
(ACT 3 only)
4.6
Dedicated Clock Buffer
Loads (CEQCD)
0.7
N/A
N/A
N/A
I/O Clock Buffer Loads
(CEQCI)
0.9
N/A
N/A
N/A
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piecewise linear summation
over all components that applies to all ACT 1, 1200XL,
3200DX, ACT 2, and ACT 3 devices. Since the ACT 1 family has
only one routed array clock, the terms labeled routed_Clk2,
dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2
family has two routed array clocks, and the dedicated_Clk
and IO_Clk terms do not apply. For ACT 3 devices, all terms
will apply.
Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs +
(p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1
+ (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * fq2)routed_Clk2 +
(r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk +
(s2 * CEQCI * fs2)IO_Clk]
(2)
12
where:
H iR e l F PG A s
Fix ed Capa cit anc e V alu es for
Act el FP GA s (pF)
Fix ed Clo ck Loads ( s 1 / s 2 — A CT 3 O nl y )
s1
Clock Loads on
Dedicated
Array Clock
s2
Clock Loads on
Dedicated
I/O Clock
A1425A
160
100
134
A1460A
432
168
168
168
A14100A
697
228
168
168
De ter m in ing Av er age S wi tc hing Fr equ ency
To determine the switching frequency for a design, you must
have a detailed understanding of the data values input to the
circuit. The guidelines in the table below are meant to
represent worst-case scenarios so that they can be generally
used to predict the upper limits of power dissipation.
r1
routed_Clk1
r2
routed_Clk2
A1010B
41
n/a
Device Type
A1020B
69
n/a
A1240A
134
A1280A
A1280XL
Device Type
A1425A
75
75
A1460A
165
165
A14100A
195
195
A32100DX
178
178
A32200DX
230
230
Type
ACT 3
3200DX/ACT 2/1200XL
ACT 1
Logic modules (m)
80% of modules
80% of modules
90% of modules
Input switching (n)
# inputs/4
# inputs/4
# inputs/4
Outputs switching (p)
#outputs/4
#outputs/4
#outputs/4
First routed array clock loads (q1)
40% of sequential
modules
40% of sequential
modules
40% of modules
Second routed array clock loads (q2)
40% of sequential
modules
40% of sequential
modules
n/a
Load capacitance (CL)
35 pF
35 pF
35 pF
Average logic module switching rate (fm)
F/10
F/10
F/10
Average input switching rate (fn)
F/5
F/5
F/5
Average output switching rate (fp)
F/10
F/10
F/10
Average first routed array clock rate (fq1)
F/2
F
F
Average second routed array clock rate (fq2)
F/2
F/2
n/a
Average dedicated array clock rate (f s1)
F
n/a
n/a
Average dedicated I/O clock rate (fs2)
F
n/a
n/a
13
32 0 0D X Ti m i ng M od el ( Lo g i c F un c t i on s us i ng A r r a y C l o ck s) *
Input Delays
Internal Delays
Predicted
Routing
Delays
I/O Module
tINPY = 1.9 ns t
IRD1 = 2.2 ns
Output Delays
I/O Module
Combinatorial
Module
D
Q
tDLH = 6.3 ns
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
tPD = 3.1 ns
G
tINH = 0.0 ns
tINSU = 0.7 ns
tINGO = 4.0 ns
Decode
Module
tRDD = 0.5 ns
tPDD = 3.3 ns
I/O Module
tDLH = 6.3 ns
Sequential
Logic Module
Combinatorial
Logic
included
in tSUD
tSU = 0.5 ns
tHD = 0.0 ns
ARRAY
CLOCKS
tCKH = 6.5 ns
FMAX = 140 MHz
*Values shown for A32100DX–1 at worst-case military conditions.
14
D
Q
tRD1 = 1.3 ns
D
Q
tENHZ = 11.5 ns
G
tCO = 3.1 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
H iR e l F PG A s
32 0 0D X Ti m i ng M od el ( Lo g i c F un c t i on s us i ng Q ua dr an t C l o ck s) *
Input Delays
Internal Delays
Predicted
Routing
Delays
I/O Module
tINPY = 1.9 ns t
IRD1 = 2.2 ns
Output Delays
I/O Module
Combinatorial
Module
D
Q
tDLH = 6.3 ns
tRD1 = 1.3 ns
tRD2 = 1.9 ns
tRD4 = 3.3 ns
tPD = 3.1 ns
G
tINH = 0.0 ns
tINSU = 0.7 ns
tINGO = 4.0 ns
Decode
Module
tRDD = 0.5 ns
tPDD = 3.3 ns
I/O Module
tDLH = 6.3 ns
Sequential
Logic Module
Combinatorial
Logic
included
in tSUD
tSU = 0.5 ns
tHD = 0.0 ns
QUADRANT
CLOCKS
D
Q
tRD1 = 1.3 ns
D
Q
tENHZ = 11.5 ns
G
tCO = 3.1 ns
tLH = 0.0 ns
tLSU = 0.4 ns
tGHL= 12.4 ns
tCKH = 12 ns**
FMAX = 100 MHz
* Values shown for A32100DX–1 at worst-case military conditions.
** Load dependent.
15
32 0 0D X Ti m i ng M od el ( SR A M Fu n ct i on s) *
Input Delays
I/O Module
tINPY = 1.9 ns t
IRD1 = 2.2 ns
D
Q
G
tINSU = 0.7 ns
tINH = 0.0 ns
tINGO = 4.0 ns
Predicted
Routing
Delays
WD [7:0]
WRAD [5:0]
ARRAY
CLOCKS
tDLH = 6.3 ns
RD [7:0]
RDAD [5:0]
tRD1 = 1.3 ns
BLKEN
REN
D
WEN
WCLK
RCLK
G
tADSU = 2.1 ns
tADH = 0.0 ns
tWENSU = 3.5 ns
tBENS = 3.6 ns
tADSU = 2.1 ns
tADH = 0.0 ns
tRENSU = 0.8 ns
tRCO = 4.4 ns
FMAX = 140 MHz
*Values shown for A32100DX–1 at worst-case military conditions.
16
I/O Module
Q
tGHL = 12.4 ns
tLSU = 0.4 ns
tLH = 0.0 ns
H iR e l F PG A s
12 0 0X L Ti m i n g M od el *
Input Delays
Internal Delays
Combinatorial
I/O Module
Logic Module
tINYL = 1.7 ns t
IRD2 = 5.2 ns†
Predicted
Routing
Delays
Output Delays
I/O Module
tDLH = 6.6 ns
D
Q
tRD1 = 1.7 ns
tRD2 = 2.5 ns
tRD4 = 3.7 ns
tRD8 = 7.0 ns
tPD = 3.7 ns
G
Sequential
Logic Module
tINH = 0.0 ns
tINSU = 0.4 ns
tINGL = 3.7 ns
Combinatorial
Logic
included
in tSUD
ARRAY
CLOCKS
tCKH = 7.1 ns
FMAX = 110 MHz
FO = 256
tSU = 0.4 ns
tHD = 0.0 ns
D
I/O Module
tDLH = 6.6 ns
D
Q
Q
tRD1 = 1.7 ns
tENHZ = 7.5 ns
G
tCO = 3.7 ns
tOUTH = 0.0 ns
tOUTSU = 0.4 ns
tGLH = 5.9 ns
tLCO = 10.7 ns (64 loads, pad-pad)
*Values shown for A1280XL–1 at worst-case military conditions.
† Input module predicted routing delay.
17
Pa r a m et er M ea su r e m en t
O ut put B uf f er D el ays
E
D
VCC
In
50%
PAD
VOL
PAD
TRIBUFF
To AC test loads (shown below)
VCC
GND
50%
VOH
E
1.5V
1.5V
50%
VCC
VCC
50%
GND
1.5V
PAD
E
PAD
GND
10%
VOL
tDLH
tENZL
tDHL
90%
1.5V
tENZH
tENLZ
GND
50%
VOH
50%
tENHZ
AC Test Load
Load 1
(Used to measure propagation delay)
Load 2
(Used to measure rising/falling edges)
VCC
GND
To the output under test
50 pF
R to VCC for tPLZ/tPZL
R to GND for tPHZ/tPZH
R = 1 kΩ
To the output under test
50 pF
Inpu t Buffe r De lay s
PAD
Com b ina tor i al Macr o Del ay s
S
A
B
Y
INBUF
Y
VCC
S, A, or B
50% 50%
VCC
Y
GND
50%
3V
PAD
1.5V 1.5V
VCC
Y
GND
50%
50%
tINYH
18
0V
tINYL
tPLH
GND
50%
tPHL
VCC
Y
50%
tPHL
GND
tPLH
50%
H iR e l F PG A s
Se q ue nt i al T i m i n g C h ar ac t er i st i c s
Fl ip- Fl ops and La tch es (AC T 3)
D
E
CLK
Y
CLR
(Positive edge triggered)
tHD
1
D
tSUD
tA
tWCLKA
G, CLK
tSUENA
tHENA
E
tCO
Q
tCLR
CLR
tWASYN
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
19
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Fl ip- Fl ops and La tch es (120 0XL /3 200D X, AC T 2, a nd A CT 1)
D
E
CLK
Y
PRE
CLR
(Positive edge triggered)
tHD
1
D
tSUD
tA
tWCLKA
G, CLK
tSUENA
tHENA
E
tCO
Q
tRS
PRE, CLR
tWASYN
Note:
1. D represents all data functions involving A, B, and S for multiplexed flip-flops.
20
H iR e l F PG A s
Se q ue nt i al T i m i n g C h ar ac t er i st i c s (continued)
Inp ut Bu ffer La tc hes (A CT 2 and 120 0XL /3 200D X)
PAD
IBDL
G
PAD
CLK
CLKBUF
PAD
tINH
G
tINSU
tHEXT
CLK
tSUEXT
Out put Buffe r Lat che s (AC T 2 and 1200 XL/ 320 0DX )
D
PAD
OBDLHS
G
D
tOUTSU
G
tOUTH
21
D ec od e Mo d ul e T i m i ng
A
B
C
D
E
F
G
Y
H
VCC
A–G, H
50%
VCC
Y
tPHL
tPLH
SR A M T i m i ng C ha r a ct er i s t i c s
Read Port
Write Port
WRAD [5:0]
BLKEN
WEN
WCLK
WD [7:0]
22
RDAD [5:0]
RAM Array
LEW
32x8 or 64x4
(256 bits)
REN
RCLK
RD [7:0]
H iR e l F PG A s
D ua l - Po r t SR A M Ti m i n g W av ef or m s
3200 DX S RA M W ri te Ope rat i on
tRCKHL
tRCKHL
WCLK
tADSU
WD[7:0]
WRAD[5:0]
tADH
Valid
tWENSU
tWENH
tBENSU
tBENH
WEN
BLKEN
Note:
Valid
Identical timing for falling-edge clock.
3200 DX S RA M S y nch ro nous R ead Oper at io n
tCKHL
tRCKHL
RCLK
tRENSU
tRENH
tADSU
tADH
REN
RDAD[5:0]
Valid
tRCO
tDOH
RD[7:0]
Note:
Old Data
New Data
Identical timing for falling-edge clock.
23
3200 DX S RA M A sy nc hronous R ead Oper at i on— Ty pe 1
(Read Address Controlled)
tRDADV
RDAD[5:0]
ADDR1
ADDR2
tRPD
tDOH
Data 1
RD[7:0]
Data 2
3200 DX S RA M A sy nc hronous R ead Oper at i on— Ty pe 2
(Write Address Controlled)
WEN
WD[7:0]
WRAD[5:0]
BLKEN
tWENSU
tWENH
Valid
tADSU
WCLK
tADH
tRPD
tDOH
RD[7:0]
24
Old Data
New Data
H iR e l F PG A s
A CT 1 Ti m i n g Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Logic Module Propagation Delays
tPD1
Single Module
4.7
5.5
ns
tPD2
Dual Module Macros
10.8
12.7
ns
tCO
Sequential Clk to Q
4.7
5.5
ns
tGO
Latch G to Q
4.7
5.5
ns
tRS
Flip-Flop (Latch) Reset to Q
4.7
5.5
ns
Logic Module Predicted Routing Delays1
tRD1
FO=1 Routing Delay
1.5
1.7
ns
tRD2
FO=2 Routing Delay
2.3
2.7
ns
tRD3
FO=3 Routing Delay
3.4
4.0
ns
tRD4
FO=4 Routing Delay
5.0
5.9
ns
tRD8
FO=8 Routing Delay
10.6
12.5
ns
Logic Module Sequential Timing
2
tSUD
Flip-Flop (Latch) Data Input Setup
8.8
10.4
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
8.8
10.4
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
10.9
12.9
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
10.9
12.9
ns
tA
Flip-Flop Clock Input Period
23.2
27.3
ns
fMAX
Flip-Flop (Latch) Clock
Frequency
tWASYN
44
37
MHz
4.9
5.8
ns
4.9
5.8
ns
Input Module Propagation Delays
tINYH
Pad to Y High
tINYL
Pad to Y Low
1, 3
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
1.5
1.7
ns
tIRD2
FO=2 Routing Delay
2.3
2.7
ns
tIRD3
FO=3 Routing Delay
3.4
4.0
ns
tIRD4
FO=4 Routing Delay
5.0
5.9
ns
tIRD8
FO=8 Routing Delay
10.6
12.5
ns
Notes:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
2. Setup times assume fanout of 3. Further derating information can be obtained from the DirectTime Analyzer utility.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
25
A CT 1 Ti m i n g Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Global Clock Network
tCKH
Input Low to High
FO = 16
FO = 128
7.8
8.9
9.2
10.5
ns
tCKL
Input High to Low
FO = 16
FO = 128
10.3
11.2
12.1
13.2
ns
tPWH
Minimum Pulse Width High
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tPWL
Minimum Pulse Width Low
FO = 16
FO = 128
10.4
10.9
12.2
12.9
ns
tCKSW
Maximum Skew
FO = 16
FO = 128
tP
Minimum Period
FO = 16
FO = 128
fMAX
Maximum Frequency
FO = 16
FO = 128
1.9
2.9
21.7
23.2
2.2
3.4
25.6
27.3
ns
ns
46
44
40
37
MHz
TTL Output Module Timing1
tDLH
Data to Pad High
12.1
14.2
ns
tDHL
Data to Pad Low
13.8
16.3
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
15.1
17.7
ns
tDHL
Data to Pad Low
11.5
13.6
ns
tENZH
Enable Pad Z to High
12.0
14.1
ns
tENZL
Enable Pad Z to Low
14.6
17.1
ns
tENHZ
Enable Pad High to Z
16.0
18.8
ns
tENLZ
Enable Pad Low to Z
14.5
17.0
ns
dTLH
Delta Low to High
0.16
0.18
ns/pF
dTHL
Delta High to Low
0.09
0.11
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
26
H iR e l F PG A s
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
5.2
6.1
ns
tCO
Sequential Clk to Q
5.2
6.1
ns
tGO
Latch G to Q
5.2
6.1
ns
tRS
Flip-Flop (Latch) Reset to Q
5.2
6.1
ns
Logic Module Predicted Routing Delays
2
tRD1
FO=1 Routing Delay
1.9
2.2
ns
tRD2
FO=2 Routing Delay
2.4
2.8
ns
tRD3
FO=3 Routing Delay
3.1
3.7
ns
tRD4
FO=4 Routing Delay
4.3
5.0
ns
tRD8
FO=8 Routing Delay
6.6
7.7
ns
3, 4
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.3
1.3
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
8.1
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
8.1
ns
tA
Flip-Flop Clock Input Period
14.8
18.6
ns
tINH
Input Buffer Latch Hold
2.5
2.5
ns
tINSU
Input Buffer Latch Setup
–3.5
–3.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.5
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
tWASYN
63
54
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
27
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
4.0
4.7
ns
tINYL
Pad to Y Low
3.6
4.3
ns
tINGH
G to Y High
6.9
8.1
ns
tINGL
G to Y Low
6.6
7.7
ns
1
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
5.8
6.9
ns
tIRD2
FO=2 Routing Delay
6.7
7.8
ns
tIRD3
FO=3 Routing Delay
7.5
8.8
ns
tIRD4
FO=4 Routing Delay
8.2
9.7
ns
tIRD8
FO=8 Routing Delay
10.9
12.9
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 256
13.3
16.3
15.7
19.2
ns
tCKL
Input High to Low
FO = 32
FO = 256
13.3
16.5
15.7
19.5
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 256
5.7
6.0
6.7
7.1
ns
tCKSW
Maximum Skew
FO = 32
FO = 256
tSUEXT
Input Latch External Setup
FO = 32
FO = 256
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 256
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 256
11.5
12.2
13.5
14.3
ns
fMAX
Maximum Frequency
FO = 32
FO = 256
0.6
3.1
87
82
0.6
3.1
74
70
ns
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
28
H iR e l F PG A s
A 12 40 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
TTL Output Module Timing1
tDLH
Data to Pad High
11.0
13.0
ns
tDHL
Data to Pad Low
13.9
16.4
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.17
0.20
ns/pF
CMOS Output Module Timing1
tDLH
Data to Pad High
14.0
16.5
ns
tDHL
Data to Pad Low
11.7
13.7
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.17
0.20
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
29
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
5.2
6.1
ns
tCO
Sequential Clk to Q
5.2
6.1
ns
tGO
Latch G to Q
5.2
6.1
ns
tRS
Flip-Flop (Latch) Reset to Q
5.2
6.1
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
2.4
2.8
ns
tRD2
FO=2 Routing Delay
3.4
4.0
ns
tRD3
FO=3 Routing Delay
4.2
4.9
ns
tRD4
FO=4 Routing Delay
5.1
6.0
ns
tRD8
FO=8 Routing Delay
9.2
10.8
ns
Logic Module Sequential Timing
3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.3
1.3
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
7.4
8.6
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
7.4
8.6
tA
Flip-Flop Clock Input Period
16.4
22.1
ns
tINH
Input Buffer Latch Hold
2.5
2.5
ns
tINSU
Input Buffer Latch Setup
–3.5
–3.5
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.5
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
tWASYN
60
ns
41
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
30
H iR e l F PG A s
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
4.0
4.7
ns
tINYL
Pad to Y Low
3.6
4.3
ns
tINGH
G to Y High
6.9
8.1
ns
tINGL
G to Y Low
6.6
7.7
ns
1
Input Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
6.2
7.3
ns
tRD2
FO=2 Routing Delay
7.2
8.4
ns
tRD3
FO=3 Routing Delay
7.7
9.1
ns
tRD4
FO=4 Routing Delay
8.9
10.5
ns
tRD8
FO=8 Routing Delay
12.9
15.2
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
13.3
17.9
15.7
21.1
ns
tCKL
Input High to Low
FO = 32
FO = 384
13.3
18.2
15.7
21.4
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
6.9
7.9
8.1
9.3
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
8.6
13.8
8.6
13.8
ns
tP
Minimum Period
FO = 32
FO = 384
13.7
16.0
16.2
18.9
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
0.6
3.1
73
63
0.6
3.1
62
53
ns
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
31
A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
TTL Output Module Timing
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tDLH
Data to Pad High
11.0
13.0
ns
tDHL
Data to Pad Low
13.9
16.4
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.09
0.11
ns/pF
dTHL
Delta High to Low
0.17
0.20
ns/pF
CMOS Output Module Timing
1
tDLH
Data to Pad High
14.0
16.5
ns
tDHL
Data to Pad Low
11.7
13.7
ns
tENZH
Enable Pad Z to High
12.3
14.4
ns
tENZL
Enable Pad Z to Low
16.1
19.0
ns
tENHZ
Enable Pad High to Z
9.8
11.5
ns
tENLZ
Enable Pad Low to Z
11.5
13.6
ns
tGLH
G to Pad High
12.4
14.6
ns
tGHL
G to Pad Low
15.5
18.2
ns
dTLH
Delta Low to High
0.17
0.20
ns/pF
dTHL
Delta High to Low
0.12
0.15
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
32
H iR e l F PG A s
A 12 80 X L T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD1
Single Module
3.7
4.3
ns
tCO
Sequential Clk to Q
3.7
4.3
ns
tGO
Latch G to Q
3.7
4.3
ns
tRS
Flip-Flop (Latch) Reset to Q
3.7
4.3
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.7
2.1
ns
tRD2
FO=2 Routing Delay
2.5
3.0
ns
tRD3
FO=3 Routing Delay
3.1
3.6
ns
tRD4
FO=4 Routing Delay
3.7
4.3
ns
tRD8
FO=8 Routing Delay
7.0
8.3
ns
Logic Module Sequential Timing
3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.4
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.1
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
5.3
6.1
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
5.3
6.1
tA
Flip-Flop Clock Input Period
10.7
12.3
ns
tINH
Input Buffer Latch Hold
0.0
0.0
ns
tINSU
Input Buffer Latch Setup
0.4
0.4
ns
tOUTH
Output Buffer Latch Hold
0.0
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.4
0.4
ns
fMAX
Flip-Flop (Latch) Clock Frequency
tWASYN
90
ns
75
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
33
A 12 80 X L T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINYH
Pad to Y High
1.5
1.7
ns
tINYL
Pad to Y Low
1.7
2.1
ns
tINGH
G to Y High
2.8
3.3
ns
tINGL
G to Y Low
3.7
4.3
ns
1
Input Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
4.6
5.3
ns
tRD2
FO=2 Routing Delay
5.2
6.1
ns
tRD3
FO=3 Routing Delay
5.5
6.5
ns
tRD4
FO=4 Routing Delay
6.4
7.5
ns
tRD8
FO=8 Routing Delay
9.2
10.8
ns
Global Clock Network
tCKH
Input Low to High
FO = 32
FO = 384
7.1
8.0
8.4
9.5
ns
tCKL
Input High to Low
FO = 32
FO = 384
7.0
8.0
8.3
9.5
ns
tPWH
Minimum Pulse Width High
FO = 32
FO = 384
4.3
4.8
5.3
5.7
ns
tPWL
Minimum Pulse Width Low
FO = 32
FO = 384
4.3
4.8
5.3
5.7
ns
tCKSW
Maximum Skew
FO = 32
FO = 384
tSUEXT
Input Latch External Setup
FO = 32
FO = 384
0.0
0.0
0.0
0.0
ns
tHEXT
Input Latch External Hold
FO = 32
FO = 384
3.6
4.6
4.2
5.3
ns
tP
Minimum Period
FO = 32
FO = 384
9.1
9.8
10.7
11.8
ns
fMAX
Maximum Frequency
FO = 32
FO = 384
1.1
1.1
110
100
1.2
1.2
90
85
ns
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based
on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce delays by 0
to 4 ns.
34
H iR e l F PG A s
A 12 80 X L T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
TTL Output Module Timing
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tDLH
Data to Pad High
5.3
6.2
ns
tDHL
Data to Pad Low
5.7
6.6
ns
tENZH
Enable Pad Z to High
5.3
6.2
ns
tENZL
Enable Pad Z to Low
5.8
6.8
ns
tENHZ
Enable Pad High to Z
7.5
8.9
ns
tENLZ
Enable Pad Low to Z
7.5
8.9
ns
tGLH
G to Pad High
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
Delta Low to High
0.05
0.06
ns/pF
dTHL
Delta High to Low
0.05
0.09
ns/pF
CMOS Output Module Timing
1
tDLH
Data to Pad High
6.6
7.9
ns
tDHL
Data to Pad Low
4.7
5.5
ns
tENZH
Enable Pad Z to High
5.3
6.2
ns
tENZL
Enable Pad Z to Low
5.8
6.8
ns
tENHZ
Enable Pad High to Z
7.5
8.9
ns
tENLZ
Enable Pad Low to Z
7.5
8.9
ns
tGLH
G to Pad High
5.9
6.9
ns
tGHL
G to Pad Low
6.6
7.8
ns
dTLH
Delta Low to High
0.07
0.09
ns/pF
dTHL
Delta High to Low
0.06
0.09
ns/pF
Notes:
1. Delays based on 50 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
35
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
Logic Module Propagation Delays
tPD
Internal Array Module
3.0
3.5
ns
tCO
Sequential Clock to Q
3.0
3.5
ns
tCLR
Asynchronous Clear to Q
3.0
3.5
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
1.9
2.1
ns
tRD3
FO=3 Routing Delay
2.1
2.5
ns
tRD4
FO=4 Routing Delay
2.6
2.9
ns
tRD8
FO=8 Routing Delay
4.2
4.9
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
1.0
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
3.8
4.4
ns
tWCLKA
Flip-Flop Clock Pulse Width
3.8
4.4
ns
tA
Flip-Flop Clock Input Period
7.9
9.3
ns
fMAX
Flip-Flop Clock Frequency
125
100
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
4.9
ns
tICKY
Input Reg IOCLK Pad to Y
7.0
8.2
ns
tOCKY
Output Reg IOCLK Pad to Y
7.0
8.2
ns
tICLRY
Input Asynchronous Clear to Y
7.0
8.2
ns
tOCLRY
Output Asynchronous Clear to Y
7.0
8.2
ns
1, 3
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
36
H iR e l F PG A s
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
‘Std’ Speed
Max.
Min.
Max.
Units
I/O Module Sequential Timing
tINH
tINSU
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input F-F Data Setup
(w.r.t. IOCLK Pad)
2.1
2.4
ns
Input Data Enable Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input Data Enable Setup
(w.r.t. IOCLK Pad)
8.7
10.0
ns
Output F-F Data Hold
(w.r.t. IOCLK Pad)
1.1
1.2
ns
Output F-F Data Setup
(w.r.t. IOCLK Pad)
1.1
1.2
ns
Output Data Enable Hold
(w.r.t. IOCLK Pad)
0.5
0.6
ns
Output Data Enable Setup
(w.r.t. IOCLK Pad)
2.0
2.4
ns
TTL Output Module Timing
1
tDHS
Data to Pad, High Slew
7.5
8.9
ns
tDLS
Data to Pad, Low Slew
11.9
14.0
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
6.0
7.0
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
10.9
12.8
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
9.9
11.6
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
9.9
11.6
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
10.5
11.6
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
15.7
17.4
ns
dTLHHS
Delta Low to High, High Slew
0.04
0.04
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.07
0.08
ns/pF
dTHLHS
Delta High to Low, High Slew
0.05
0.06
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.07
0.08
ns/pF
Note:
1. Delays based on 35 pF loading.
37
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
CMOS Output Module Timing
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
9.9
11.6
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.5
11.6
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
12.5
13.7
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
18.1
20.1
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
3.0
3.5
ns
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
tIOPWH
Minimum Pulse Width High
3.9
4.4
ns
tIOPWL
Minimum Pulse Width Low
3.9
4.4
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
tIOP
Minimum Period
fIOMAX
Maximum Frequency
0.5
7.9
0.5
9.3
ns
ns
125
100
MHz
Input Low to High
(Pad to S-Module Input)
4.6
5.3
ns
Input High to Low
(Pad to S-Module Input)
4.6
5.3
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width High
3.9
4.4
ns
tHPWL
Minimum Pulse Width Low
3.9
4.4
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.4
7.9
0.4
9.3
125
ns
ns
100
MHz
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
38
H iR e l F PG A s
A 14 25 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
Input Low to High (FO=64)
5.5
6.4
ns
tRCKL
Input High to Low (FO=64)
6.0
7.0
ns
tRPWH
Min. Pulse Width High (FO=64)
4.9
5.7
ns
tRPWL
Min. Pulse Width Low (FO=64)
4.9
5.7
ns
tRCKSW
Maximum Skew (FO=128)
tRP
Minimum Period (FO=64)
fRMAX
Maximum Frequency (FO=64)
1.1
10.1
1.2
11.6
100
ns
ns
85
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
3.0
0.0
3.0
ns
tIORCKSW
I/O Clock to R-Clock Skew
0.0
3.0
0.0
3.0
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
39
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
3.0
3.5
ns
tCO
Sequential Clock to Q
3.0
3.5
ns
tCLR
Asynchronous Clear to Q
3.0
3.5
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
1.9
2.1
ns
tRD3
FO=3 Routing Delay
2.1
2.5
ns
tRD4
FO=4 Routing Delay
2.6
2.9
ns
tRD8
FO=8 Routing Delay
4.2
4.9
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
0.9
1.0
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
0.9
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWASYN
Asynchronous Pulse Width
4.8
5.6
ns
tWCLKA
Flip-Flop Clock Pulse Width
4.8
5.6
ns
tA
Flip-Flop Clock Input Period
9.9
11.6
ns
fMAX
Flip-Flop Clock Frequency
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
4.9
ns
tICKY
Input Reg IOCLK Pad to Y
7.0
8.2
ns
tOCKY
Output Reg IOCLK Pad to Y
7.0
8.2
ns
tICLRY
Input Asynchronous Clear to Y
7.0
8.2
ns
tOCLRY
Output Asynchronous Clear to Y
7.0
8.2
ns
Input Module Predicted Routing Delays2, 3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
40
H iR e l F PG A s
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
I/O Module Sequential Timing
tINH
tINSU
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input F-F Data Setup
(w.r.t. IOCLK Pad)
2.1
2.4
ns
Input Data Enable Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input Data Enable Setup
(w.r.t. IOCLK Pad)
8.7
10.0
ns
Output F-F Data Hold
(w.r.t. IOCLK Pad)
1.1
1.2
ns
Output F-F Data Setup
(w.r.t. IOCLK Pad)
1.1
1.2
ns
Output Data Enable Hold
(w.r.t. IOCLK Pad)
0.5
0.6
ns
Output Data Enable Setup
(w.r.t. IOCLK Pad)
2.0
2.4
ns
TTL Output Module Timing
1
tDHS
Data to Pad, High Slew
7.5
8.9
ns
tDLS
Data to Pad, Low Slew
11.9
14.0
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
6.0
7.0
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
10.9
12.8
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
11.5
13.5
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
11.6
13.4
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
17.8
19.8
ns
dTLHHS
Delta Low to High, High Slew
0.04
0.04
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.07
0.08
ns/pF
dTHLHS
Delta High to Low, High Slew
0.05
0.06
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.07
0.08
ns/pF
Note:
1. Delays based on 35 pF loading.
41
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
10.9
12.8
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
14.1
16.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
20.2
22.4
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
3.5
4.1
ns
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
tIOPWH
Minimum Pulse Width High
4.8
5.7
ns
tIOPWL
Minimum Pulse Width Low
4.8
5.7
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
tIOP
Minimum Period
fIOMAX
Maximum Frequency
0.9
9.9
1.0
11.6
ns
ns
100
85
MHz
Input Low to High
(Pad to S-Module Input)
5.5
6.4
ns
Input High to Low
(Pad to S-Module Input)
5.5
6.4
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width High
4.8
5.7
ns
tHPWL
Minimum Pulse Width Low
4.8
5.7
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.9
9.9
1.0
11.6
100
ns
ns
85
MHz
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
42
H iR e l F PG A s
A 14 60 A Ti m i ng Ch a r ac t e r i s t i cs (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
Input Low to High (FO=256)
9.0
10.5
ns
tRCKL
Input High to Low (FO=256)
9.0
10.5
ns
tRPWH
Min. Pulse Width High (FO=256)
6.3
7.1
ns
tRPWL
Min. Pulse Width Low (FO=256)
6.3
7.1
ns
tRCKSW
Maximum Skew (FO=128)
tRP
Minimum Period (FO=256)
fRMAX
Maximum Frequency (FO=256)
1.9
12.9
2.1
14.5
75
ns
ns
65
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
3.0
0.0
3.0
ns
tIORCKSW
I/O Clock to R-Clock Skew
0.0
5.0
0.0
5.0
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
ns
43
A 14 10 0A T i m i n g C h ar a c t er i st i c s
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Logic Module Propagation Delays1
tPD
Internal Array Module
3.0
3.5
ns
tCO
Sequential Clock to Q
3.0
3.5
ns
tCLR
Asynchronous Clear to Q
3.0
3.5
ns
2
Logic Module Predicted Routing Delays
tRD1
FO=1 Routing Delay
1.3
1.5
ns
tRD2
FO=2 Routing Delay
1.9
2.1
ns
tRD3
FO=3 Routing Delay
2.1
2.5
ns
tRD4
FO=4 Routing Delay
2.6
2.9
ns
tRD8
FO=8 Routing Delay
4.2
4.9
ns
Logic Module Sequential Timing
tSUD
Flip-Flop (Latch) Data Input Setup
1.0
1.0
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.6
0.6
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.0
1.0
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.6
0.6
ns
tWASYN
Asynchronous Pulse Width
4.8
5.6
ns
tWCLKA
Flip-Flop Clock Pulse Width
4.8
5.6
ns
tA
Flip-Flop Clock Input Period
9.9
11.6
ns
fMAX
Flip-Flop Clock Frequency
100
85
MHz
Input Module Propagation Delays
tINY
Input Data Pad to Y
4.2
4.9
ns
tICKY
Input Reg IOCLK Pad to Y
7.0
8.2
ns
tOCKY
Output Reg IOCLK Pad to Y
7.0
8.2
ns
tICLRY
Input Asynchronous Clear to Y
7.0
8.2
ns
tOCLRY
Output Asynchronous Clear to Y
7.0
8.2
ns
Input Module Predicted Routing Delays2, 3
tIRD1
FO=1 Routing Delay
1.3
1.5
ns
tIRD2
FO=2 Routing Delay
1.9
2.1
ns
tIRD3
FO=3 Routing Delay
2.1
2.5
ns
tIRD4
FO=4 Routing Delay
2.6
2.9
ns
tIRD8
FO=8 Routing Delay
4.2
4.9
ns
Notes:
1. For dual-module macros, use tPD + tRD1 + tPDn , tCO + tRD1 + tPDn , or tPD1 + tRD1 + tSUD , whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
3. Optimization techniques may further reduce delays by 0 to 4 ns.
44
H iR e l F PG A s
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
I/O Module Sequential Timing
tINH
tINSU
tIDEH
tIDESU
tOUTH
tOUTSU
tODEH
tODESU
Input F-F Data Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input F-F Data Setup
(w.r.t. IOCLK Pad)
2.1
2.4
ns
Input Data Enable Hold
(w.r.t. IOCLK Pad)
0.0
0.0
ns
Input Data Enable Setup
(w.r.t. IOCLK Pad)
8.7
10.0
ns
Output F-F Data Hold
(w.r.t. IOCLK Pad)
1.2
1.2
ns
Output F-F Data Setup
(w.r.t. IOCLK Pad)
1.2
1.2
ns
Output Data Enable Hold
(w.r.t. IOCLK Pad)
0.6
0.6
ns
Output Data Enable Setup
(w.r.t. IOCLK Pad)
2.4
2.4
ns
TTL Output Module Timing
1
tDHS
Data to Pad, High Slew
7.5
8.9
ns
tDLS
Data to Pad, Low Slew
11.9
14.0
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
6.0
7.0
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
10.9
12.8
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
11.9
14.0
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
12.2
14.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
17.8
17.8
ns
dTLHHS
Delta Low to High, High Slew
0.04
0.04
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.07
0.08
ns/pF
dTHLHS
Delta High to Low, High Slew
0.05
0.06
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.07
0.08
ns/pF
Note:
1. Delays based on 35 pF loading.
45
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
CMOS Output Module Timing1
tDHS
Data to Pad, High Slew
9.2
10.8
ns
tDLS
Data to Pad, Low Slew
17.3
20.3
ns
tENZHS
Enable to Pad, Z to H/L, High Slew
7.7
9.1
ns
tENZLS
Enable to Pad, Z to H/L, Low Slew
13.1
15.5
ns
tENHSZ
Enable to Pad, H/L to Z, High Slew
11.6
14.0
ns
tENLSZ
Enable to Pad, H/L to Z, Low Slew
10.9
12.8
ns
tCKHS
IOCLK Pad to Pad H/L, High Slew
14.4
16.0
ns
tCKLS
IOCLK Pad to Pad H/L, Low Slew
20.2
22.4
ns
dTLHHS
Delta Low to High, High Slew
0.06
0.07
ns/pF
dTLHLS
Delta Low to High, Low Slew
0.11
0.13
ns/pF
dTHLHS
Delta High to Low, High Slew
0.04
0.05
ns/pF
dTHLLS
Delta High to Low, Low Slew
0.05
0.06
ns/pF
3.5
4.1
ns
Dedicated (Hard-Wired) I/O Clock Network
tIOCKH
Input Low to High
(Pad to I/O Module Input)
tIOPWH
Minimum Pulse Width High
4.8
5.7
ns
tIOPWL
Minimum Pulse Width Low
4.8
5.7
ns
tIOSAPW
Minimum Asynchronous Pulse Width
3.9
4.4
ns
tIOCKSW
Maximum Skew
tIOP
Minimum Period
fIOMAX
Maximum Frequency
0.9
9.9
1.0
11.6
ns
ns
100
85
MHz
Input Low to High
(Pad to S-Module Input)
5.5
6.4
ns
Input High to Low
(Pad to S-Module Input)
5.5
6.4
ns
Dedicated (Hard-Wired) Array Clock Network
tHCKH
tHCKL
tHPWH
Minimum Pulse Width High
4.8
5.7
ns
tHPWL
Minimum Pulse Width Low
4.8
5.7
ns
tHCKSW
Maximum Skew
tHP
Minimum Period
fHMAX
Maximum Frequency
0.9
9.9
1.0
11.6
100
ns
ns
85
MHz
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
46
H iR e l F PG A s
A 14 10 0A T i m i n g C h ar a c t er i st i c s (continued)
(W or st -C as e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
Input Low to High (FO=256)
9.0
10.5
ns
tRCKL
Input High to Low (FO=256)
9.0
10.5
ns
tRPWH
Min. Pulse Width High (FO=256)
6.3
7.1
ns
tRPWL
Min. Pulse Width Low (FO=256)
6.3
7.1
ns
tRCKSW
Maximum Skew (FO=128)
tRP
Minimum Period (FO=256)
fRMAX
Maximum Frequency (FO=256)
1.9
12.9
2.1
14.5
75
ns
ns
65
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
3.5
0.0
3.5
ns
tIORCKSW
I/O Clock to R-Clock Skew
0.0
5.0
0.0
5.0
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
0.0
1.0
3.0
0.0
0.0
1.0
3.0
ns
47
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
3.1
4.1
ns
tPDD
Internal Decode Module Delay
3.3
4.3
ns
Logic Module Predicted Routing Delays
1
tRD1
FO=1 Routing Delay
1.3
1.8
ns
tRD2
FO=2 Routing Delay
1.9
2.6
ns
tRD3
FO=3 Routing Delay
2.6
3.4
ns
tRD4
FO=4 Routing Delay
3.3
4.3
ns
tRD5
FO=8 Routing Delay
0.6
0.8
ns
tRDD
Decode-to-Output Routing Delay
0.5
0.6
ns
Logic Module Sequential Timing
tCO
Flip-Flop Clock-to-Output
3.1
4.1
ns
tGO
Latch Gate-to-Output
3.1
4.1
ns
tSU
Flip-Flop (Latch) Setup Time
0.5
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
tSUENA
Flip-Flop (Latch) Enable Setup
0.9
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse
Width
4.3
5.8
ns
Flip-Flop (Latch) Asynchronous Pulse
Width
5.6
7.5
ns
tWASYN
3.1
4.1
ns
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
48
H iR e l F PG A s
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
’–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
11.8
ns
tWC
Write Cycle Time
8.8
11.8
ns
tRCKHL
Clock High/Low Time
4.4
5.9
ns
tRCO
Data Valid After Clock High/Low
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSU
Read Enable Setup
0.8
1.1
ns
tRENH
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tBENS
Block Enable Setup
3.6
4.8
ns
tBENH
Block Enable Hold
0.0
0.0
ns
4.4
5.9
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
11.5
15.3
ns
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSUA
Read Enable Setup to Address Valid
0.8
1.1
ns
tRENHA
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tDOH
Data Out Hold Time
10.6
1.6
14.1
2.1
ns
ns
49
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad to Y
1.9
2.6
ns
tINGO
Input Latch Gate-to-Output
4.0
5.3
ns
tINH
Input Latch Hold
0.0
0.0
ns
tINSU
Input Latch Setup
0.7
0.9
ns
tILA
Latch Active Pulse Width
6.1
8.1
ns
1
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
2.2
2.9
ns
tIRD2
FO=2 Routing Delay
2.8
3.8
ns
tIRD3
FO=3 Routing Delay
3.5
4.7
ns
tIRD4
FO=4 Routing Delay
3.5
4.7
ns
tIRD8
FO=8 Routing Delay
5.6
7.5
ns
Global Clock Network
tCKH
Input Low to High
FO=32
FO=635
6.5
7.9
8.7
10.6
ns
ns
tCKL
Input High to Low
FO=32
FO=635
6.6
8.8
8.8
11.8
ns
ns
tPWH
Minimum Pulse Width High
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
tPWL
Minimum Pulse Width Low
FO=32
FO=635
4.1
4.6
5.5
6.1
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch External Setup
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
tP
Minimum Period (1/fmax)
FO=32
FO=635
7.1
7.9
9.5
10.5
ns
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
1.8
1.8
140
126
2.4
2.4
105
95
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
50
H iR e l F PG A s
A 32 10 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C)
‘–1’ Speed
Parameter
Description
TTL Output Module Timing
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tDLH
Data to Pad High
5.1
6.8
ns
tDHL
Data to Pad Low
6.3
8.3
ns
tENZH
Enable Pad Z to High
6.6
8.8
ns
tENZL
Enable Pad Z to Low
7.1
9.4
ns
tENHZ
Enable Pad High to Z
11.5
15.3
ns
tENLZ
Enable Pad Low to Z
11.5
15.3
ns
tGLH
G to Pad High
11.5
15.3
ns
tGHL
G to Pad Low
12.4
16.6
ns
tLSU
I/O Latch Output Setup
0.4
0.5
ns
tLH
I/O Latch Output Hold
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
11.5
15.4
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
16.3
21.7
ns
dTLH
Capacitive Loading, Low to High
0.04
0.06
ns/pF
dTHL
Capacitive Loading, High to Low
0.06
0.08
ns/pF
tWDO
Hard-Wired Wide Decode Output
0.05
0.07
ns
CMOS Output Module Timing1
tDLH
Data to Pad High
6.3
8.3
ns
tDHL
Data to Pad Low
5.1
6.8
ns
tENZH
Enable Pad Z to High
6.6
8.8
ns
tENZL
Enable Pad Z to Low
7.1
9.4
ns
tENHZ
Enable Pad High to Z
11.5
15.3
ns
tENLZ
Enable Pad Low to Z
11.5
15.3
ns
tGLH
G to Pad High
11.5
15.3
ns
tGHL
G to Pad Low
12.4
16.6
ns
tLSU
I/O Latch Setup
0.4
0.5
ns
tLH
I/O Latch Hold
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
13.7
18.2
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
19.2
25.6
ns
dTLH
Capacitive Loading, Low to High
0.06
0.08
ns/pF
dTHL
Capacitive Loading, High to Low
0.05
0.07
ns/pF
tWDO
Hard-Wired Wide Decode Output
0.05
0.07
ns
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
51
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Logic Module Combinatorial Functions
tPD
Internal Array Module Delay
2.8
3.8
ns
tPDD
Internal Decode Module Delay
3.4
4.6
ns
Logic Module Predicted Routing Delays
1
tRD1
FO=1 Routing Delay
1.6
2.1
ns
tRD2
FO=2 Routing Delay
2.3
3.1
ns
tRD3
FO=3 Routing Delay
2.9
3.9
ns
tRD4
FO=4 Routing Delay
3.5
4.7
ns
tRD5
FO=8 Routing Delay
6.2
8.2
ns
tRDD
Decode-to-Output Routing Delay
0.8
1.1
ns
Logic Module Sequential Timing Characteristics
tCO
Flip-Flop Clock-to-Output
3.2
4.2
ns
tGO
Latch Gate-to-Output
2.8
3.8
ns
tSU
Flip-Flop (Latch) Setup Time
0.5
0.6
ns
tH
Flip-Flop (Latch) Hold Time
0.0
0.0
ns
tRO
Flip-Flop (Latch) Reset to Output
tSUENA
Flip-Flop (Latch) Enable Setup
0.9
1.2
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
4.3
5.8
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
5.7
7.6
ns
3.2
4.2
ns
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
52
H iR e l F PG A s
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Synchronous SRAM Operations
tRC
Read Cycle Time
8.8
11.8
ns
tWC
Write Cycle Time
8.8
11.8
ns
tRCKHL
Clock High/Low Time
4.4
5.9
ns
tRCO
Data Valid After Clock High/Low
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSU
Read Enable Setup
0.8
1.1
ns
tRENH
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tBENS
Block Enable Setup
3.6
4.8
ns
tBENH
Block Enable Hold
0.0
0.0
ns
4.4
5.9
ns
Asynchronous SRAM Operations
tRPD
Asynchronous Access Time
tRDADV
Read Address Valid
11.5
15.3
ns
tADSU
Address/Data Setup Time
2.1
2.8
ns
tADH
Address/Data Hold Time
0.0
0.0
ns
tRENSUA
Read Enable Setup to Address Valid
0.8
1.1
ns
tRENHA
Read Enable Hold
4.4
5.9
ns
tWENSU
Write Enable Setup
3.5
4.7
ns
tWENH
Write Enable Hold
0.0
0.0
ns
tDOH
Data Out Hold Time
10.6
1.6
14.1
2.1
ns
ns
53
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Wor st - Cas e M il it ar y Cond it ion s, V C C = 4.5 V, T J = 1 25° C)
‘–1’ Speed
Parameter
Description
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
Input Module Propagation Delays
tINPY
Input Data Pad to Y
1.9
2.6
ns
tINGO
Input Latch Gate-to-Output
4.6
6.0
ns
tINH
Input Latch Hold
0.0
0.0
ns
tINSU
Input Latch Setup
0.7
0.9
ns
tILA
Latch Active Pulse Width
6.1
8.1
ns
1
Input Module Predicted Routing Delays
tIRD1
FO=1 Routing Delay
2.6
3.5
ns
tIRD2
FO=2 Routing Delay
3.4
4.6
ns
tIRD3
FO=3 Routing Delay
4.6
6.1
ns
tIRD4
FO=4 Routing Delay
5.4
7.2
ns
tIRD5
FO=8 Routing Delay
7.0
9.3
ns
Global Clock Network
tCKH
Input Low to High
FO=32
FO=635
7.3
8.5
9.8
11.3
ns
ns
tCKL
Input High to Low
FO=32
FO=635
7.2
9.3
9.6
12.5
ns
ns
tPWH
Minimum Pulse Width High
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
tPWL
Minimum Pulse Width Low
FO=32
FO=635
3.2
3.9
4.3
5.2
ns
ns
tCKSW
Maximum Skew
FO=32
FO=635
tSUEXT
Input Latch External Setup
FO=32
FO=635
0.0
0.0
0.0
0.0
ns
ns
tHEXT
Input Latch External Hold
FO=32
FO=635
3.0
3.8
4.0
5.1
ns
ns
tP
Minimum Period (1/fmax)
FO=32
FO=635
5.8
6.8
7.7
9.1
ns
ns
fHMAX
Maximum Datapath Frequency
FO=32
FO=635
1.8
1.8
172
147
2.4
2.4
130
110
ns
ns
MHz
MHz
Note:
1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment. Optimization techniques may further reduce
delays by 0 to 4 ns.
54
H iR e l F PG A s
A 32 20 0D X T i m i ng C ha r a ct er i s t i c s (continued)
(Worst-Case Military Conditions, V C C = 4.5V, T J = 125°C)
‘–1’ Speed
Parameter
Description
TTL Output Module Timing
Min.
Max.
‘Std’ Speed
Min.
Max.
Units
1
tDLH
Data to Pad High
5.1
6.8
ns
tDHL
Data to Pad Low
6.3
8.3
ns
tENZH
Enable Pad Z to High
6.6
8.8
ns
tENZL
Enable Pad Z to Low
7.1
9.5
ns
tENHZ
Enable Pad High to Z
11.5
15.3
ns
tENLZ
Enable Pad Low to Z
11.5
15.3
ns
tGLH
G to Pad High
11.5
15.3
ns
tGHL
G to Pad Low
12.3
16.5
ns
tLSU
I/O Latch Output Setup
0.4
0.5
ns
tLH
I/O Latch Output Hold
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
11.5
15.4
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
16.3
21.7
ns
dTLH
Capacitive Loading, Low to High
0.04
0.06
ns/pF
dTHL
Capacitive Loading, High to Low
0.06
0.08
ns/pF
tWDO
Hard-Wired Wide Decode Output
0.05
0.07
ns
CMOS Output Module Timing1
tDLH
Data to Pad High
5.1
6.8
ns
tDHL
Data to Pad Low
6.3
8.3
ns
tENZH
Enable Pad Z to High
6.6
8.8
ns
tENZL
Enable Pad Z to Low
7.1
9.5
ns
tENHZ
Enable Pad High to Z
11.5
15.3
ns
tENLZ
Enable Pad Low to Z
11.5
15.3
ns
tGLH
G to Pad High
11.5
15.3
ns
tGHL
G to Pad Low
12.3
16.5
ns
tLSU
I/O Latch Setup
0.4
0.5
ns
tLH
I/O Latch Hold
0.0
0.0
ns
tLCO
I/O Latch Clock-Out (Pad-to-Pad) 32 I/O
13.7
18.2
ns
tACO
Array Latch Clock-Out (Pad-to-Pad) 32 I/O
19.2
25.6
ns
dTLH
Capacitive Loading, Low to High
0.06
0.08
ns/pF
dTHL
Capacitive Loading, High to Low
0.05
0.07
ns/pF
tWDO
Hard-Wired Wide Decode Output
0.05
0.07
ns
Notes:
1. Delays based on 35 pF loading.
2. SSO information can be found in the Simultaneously Switching Output Limits for Actel FPGAs application note at
http://www.actel.com/appnotes.
55
Pi n D es c ri pt i on
CLK
Clock (Input)
ACT 1 only. TTL Clock input for global clock distribution
network. The Clock input is buffered prior to clocking the
logic modules. This pin can also be used as an I/O.
CLKA
Clock A (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
CLKB
Clock B (Input)
ACT 2, 1200XL, 3200DX, and ACT 3 only. TTL Clock input for
global clock distribution networks. The Clock input is
buffered prior to clocking the logic modules. This pin can also
be used as an I/O.
DCLK
Diagnostic Clock (Input)
TTL Clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
GND
Ground
LOW supply voltage.
HCLK
Dedicated (Hard-wired) Array
Clock (Input)
ACT 3 only. TTL Clock input for sequential modules. This
input is directly wired to each S-module and offers clock
speeds independent of the number of S-modules being driven.
This pin can also be used as an I/O.
I/O
Input/Output (Input, Output)
I/O pin functions as an input, output, tristate, or
bi-directional buffer. Input and output levels are compatible
with standard TTL and CMOS specifications. In the ACT 3 and
3200DX families, unused I/Os are automatically tri-stated.
With this configuration, the input buffer internal to the I/O
module is disabled. In the ACT 1, ACT 2 and 1200XL families,
unused I/Os are automatically configured as bi-directional
buffers where each buffer is configured as a LOW driver.
IOCLK
Dedicated (Hard-wired) I/O
Clock (Input)
ACT 3 only. TTL Clock input for I/O modules. This input is
directly wired to each I/O module and offers clock speeds
independent of the number of I/O modules being driven. This
pin can also be used as an I/O.
IOPCL
Dedicated (Hard-wired) I/O
Preset/Clear (Input)
ACT 3 only. TTL input for I/O preset or clear. This global input
is directly wired to the preset and clear inputs of all I/O
registers. This pin functions as an I/O when no I/O preset or
clear macros are used.
56
MODE
Mode (Input)
The MODE pin controls the use of diagnostic pins (DCLK,
PRA, PRB, SDI). When the MODE pin is HIGH, the special
functions are active. When the MODE pin is LOW, the pins
function as I/Os. To provide debugging capability, the MODE
pin should be terminated to GND through a 10 kΩ resistor so
that the MODE pin can be pulled high when required.
NC
No Connection
This pin is not connected to circuitry within the device.
PRA, I/O
Probe A (Output)
The Probe A pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe B pin to allow
real-time diagnostic output of any signal path within the
device. The Probe A pin can be used as a user-defined I/O
when debugging has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRA is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
PRB, I/O
Probe B (Output)
The Probe B pin is used to output data from any user-defined
design node within the device. This independent diagnostic
pin can be used in conjunction with the Probe A pin to allow
real-time diagnostic output of any signal path within the
device. The Probe B pin can be used as a user-defined I/O
when verification has been completed. The pin’s probe
capabilities can be permanently disabled to protect
programmed design confidentiality. PRB is accessible when
the MODE pin is HIGH. This pin functions as an I/O when the
MODE pin is LOW.
SDI
Serial Data Input (Input)
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH. This
pin functions as an I/O when the MODE pin is LOW.
VCC
5.0V Supply Voltage
HIGH supply voltage.
QCLKA/B,C,D Quadrant Clock (Input/Output)
3200DX only. These four pins are the quadrant clock inputs.
When not used as a register control signal, these pins can
function as general purpose I/O.
TCK
Test Clock
Clock signal to shift the JTAG data into the device. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
H iR e l F PG A s
TDI
Test Data In
Serial data input for JTAG instructions and data. Data is
shifted in on the rising edge of TCLK. This pin functions as an
I/O when the JTAG fuse is not programmed. JTAG pins are
only available in the 3200DX device.
TDO
Test Data Out
Serial data output for JTAG instructions and test data. This pin
functions as an I/O when the JTAG fuse is not programmed.
JTAG pins are only available in the 3200DX device.
TMS
Test Mode Select
Serial data input for JTAG test mode. Data is shifted in on the
rising edge of TCLK. This pin functions as an I/O when the
JTAG fuse is not programmed. JTAG pins are only available in
the 3200DX device.
57
Pa c ka ge P i n A s si g nm e n t s
84- Pi n CP GA (T op Vie w)
1
2
3
4
5
6
7
8
9
10 11
A
A
B
B
C
C
D
D
E
E
84-Pin
CPGA
F
F
G
G
H
H
J
J
K
K
L
L
1
2
3
4
5
6
7
8
9
10 11
Orientation Pin (C3)
58
H iR e l F PG A s
84- Pi n CP GA
Pin Number
A1010B
Function
A1020B
Function
Pin Number
A1010B
Function
A1020B
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
NC
NC
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PRA, I/O
I/O
NC
I/O
I/O
F9
F10
F11
G1
G2
G3
G9
G10
G11
H1
H2
H10
H11
J1
J2
CLK, I/O
GND
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
NC
CLK, I/O
GND
I/O
I/O
VCC
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
B6
B7
B8
B9
B10
B11
C1
C2
C5
C6
C7
C10
C11
D1
D2
D10
D11
E1
E2
E3
E9
E10
E11
F1
F2
F3
I/O
GND
I/O
I/O
PRB, I/O
SDI, I/O
NC
NC
I/O
I/O
I/O
DCLK, I/O
NC
I/O
I/O
NC
NC
I/O
GND
GND
VCC
VCC
MODE
VCC
I/O
I/O
VCC
I/O
GND
I/O
I/O
PRB, I/O
SDI, I/O
I/O
I/O
I/O
I/O
I/O
DCLK, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
VCC
VCC
MODE
VCC
I/O
I/O
J5
J6
J7
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
I/O
I/O
I/O
NC
I/O
NC
VCC
I/O
I/O
GND
I/O
VCC
I/O
I/O
NC
NC
NC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
59
Pa c ka ge P i n A s si g nm e n t s (continued)
132- P in CP GA (T op Vi ew)
1
2
3
4
5
6
7
8
9
10 11 12 13
A
A
B
B
C
C
D
D
E
E
F
F
132-Pin
CPGA
G
G
H
H
J
J
K
K
L
L
M
M
N
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
60
H iR e l F PG A s
132- P in CP GA
Pin Number
A1240A
Function
Pin Number
A1240A
Function
Pin Number
A1240A
Function
A1
A2
MODE
D8
I/O
K7
VCC
I/O
D11
I/O
K8
I/O
A3
I/O
D12
I/O
K11
I/O
A4
I/O
D13
I/O
K12
GND
A5
I/O
E1
I/O
K13
I/O
A6
I/O
E2
I/O
L1
I/O
A7
I/O
E3
GND
L2
I/O
A8
I/O
E11
GND
L3
I/O
A9
I/O
E12
GND
L4
I/O
A10
I/O
E13
I/O
L5
GND
A11
I/O
F1
I/O
L6
I/O
A12
I/O
F2
I/O
L7
VCC
A13
I/O
F3
I/O
L8
I/O
B1
I/O
F4
GND
L9
GND
B2
I/O
F10
I/O
L10
I/O
B3
I/O
F11
I/O
L11
I/O
B4
I/O
F12
I/O
L12
I/O
B5
GND
F13
I/O
L13
I/O
B6
CLKB, I/O
G1
I/O
M1
I/O
B7
CLKA, I/O
G2
VCC
M2
I/O
B8
PRA, I/O
G3
VCC
M3
I/O
B9
GND
G4
VCC
M4
I/O
B10
I/O
G10
VCC
M5
I/O
B11
I/O
G11
VCC
M6
I/O
B12
SDI, I/O
G12
VCC
M7
I/O
B13
I/O
G13
VCC
M8
I/O
C1
I/O
H1
I/O
M9
GND
C2
I/O
H2
I/O
M10
I/O
C3
DCLK, I/O
H3
I/O
M11
I/O
C4
I/O
H4
I/O
M12
I/O
C5
GND
H10
I/O
M13
I/O
C6
PRB, I/O
H11
I/O
N1
I/O
C7
VCC
H12
I/O
N2
I/O
C8
I/O
H13
GND
N3
I/O
C9
GND
J1
I/O
N4
I/O
C10
I/O
J2
GND
N5
I/O
C11
I/O
J3
GND
N6
I/O
C12
I/O
J11
GND
N7
I/O
C13
I/O
J12
I/O
N8
I/O
D1
I/O
J13
I/O
N9
I/O
D2
I/O
K1
I/O
N10
I/O
D3
I/O
K2
I/O
N11
I/O
D6
I/O
K3
I/O
N12
I/O
D7
VCC
K6
I/O
N13
I/O
61
Pa c ka ge P i n A s si g nm e n t s (continued)
133- P in CP GA (T op Vi ew)
1
2
3
4
5
6
7
8
9
10 11 12 13
A
A
B
B
C
C
D
D
E
E
F
F
133-Pin
CPGA
G
G
H
H
J
J
K
K
L
L
M
M
N
N
1
2
3
4
5
6
7
8
9
10 11 12 13
Orientation Pin
62
H iR e l F PG A s
133- P in CP GA
Pin Number
A1425A
Function
Pin Number
A1425A
Function
Pin Number
A1425A
Function
A1
NC
D8
I/O
K8
I/O
A2
A3
GND
I/O
D11
D12
I/O
I/O
K11
K12
I/O
I/O
A4
A5
I/O
I/O
D13
E1
I/O
I/O
K13
L1
I/O
I/O
A6
A7
PRA, I/O
NC
E2
E3
I/O
MODE
L2
L3
I/O
GND
A8
I/O
E11
VCC
L4
I/O
A9
A10
I/O
I/O
E12
E13
I/O
I/O
L5
L6
I/O
PRB, I/O
A11
A12
I/O
I/O
F1
F2
I/O
I/O
L7
L8
GND
I/O
A13
B1
NC
I/O
F3
F4
I/O
I/O
L9
L10
I/O
IOPCL, I/O
B2
B3
VCC
I/O
F10
F11
GND
I/O
L11
L12
GND
I/O
B4
I/O
F12
I/O
L13
I/O
B5
B6
I/O
CLKB, I/O
F13
G1
I/O
NC
M1
M2
I/O
VCC
B7
B8
VCC
I/O
G2
G3
VCC
GND
M3
M4
GND
I/O
B9
B10
I/O
I/O
G4
G10
I/O
I/O
M5
M6
I/O
I/O
B11
B12
I/O
VCC
G11
G12
GND
VCC
M7
M8
VCC
I/O
B13
I/O
G13
NC
M9
I/O
C1
C2
I/O
SDI, I/O
H1
H2
I/O
I/O
M10
M11
I/O
I/O
C3
C4
GND
I/O
H3
H4
I/O
I/O
M12
M13
VCC
I/O
C5
C6
I/O
I/O
H10
H11
I/O
I/O
N1
N2
NC
I/O
C7
C8
GND
I/O
H12
H13
I/O
I/O
N3
N4
I/O
I/O
C9
I/O
J1
I/O
N5
I/O
C10
C11
IOCLK, I/O
GND
J2
J3
VCC
I/O
N6
N7
I/O
NC
C12
C13
GND
I/O
J11
J12
I/O
VCC
N8
N9
I/O
I/O
D1
D2
I/O
I/O
J13
K1
I/O
I/O
N10
N11
I/O
I/O
D3
I/O
K2
I/O
N12
GND
D4
D6
DCLK, I/O
CLKA, I/O
K3
K6
I/O
I/O
N13
NC
D7
I/O
K7
HCLKA, I/O
63
Pa c ka ge P i n A s si g nm e n t s (continued)
176- P in CP GA (T op Vi ew)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
A
A
B
B
C
C
D
D
E
E
F
F
G
G
176-Pin
CPGA
H
H
J
J
K
K
L
L
M
M
N
N
P
P
R
R
1
.
64
2
3
4
5
6
7
8
9
10 11 12 13 14 15
H iR e l F PG A s
176- P in CP GA
Pin Number
A1280A
Function
A1280XL
Function
Pin Number
A1280A
Function
A1280XL
Function
A1
I/O
I/O
C15
I/O
I/O
A2
I/O
I/O
D1
I/O
I/O
A3
I/O
I/O
D2
I/O
I/O
A4
I/O
I/O
D3
I/O
I/O
A5
I/O
I/O
D4
GND
GND
A6
I/O
I/O
D5
VCC
VCC
A7
I/O
I/O
D6
GND
GND
A8
I/O
I/O
D7
PRB, I/O
PRB, I/O
A9
CLKA, I/O
CLKA, I/O
D8
VCC
VCC
A10
I/O
I/O
D9
I/O
I/O
A11
I/O
I/O
D10
GND
GND
A12
I/O
I/O
D11
VCC
VCC
A13
I/O
I/O
D12
GND
GND
A14
I/O
I/O
D13
I/O
I/O
A15
I/O
I/O
D14
I/O
I/O
B1
I/O
I/O
D15
I/O
I/O
B2
I/O
I/O
E1
I/O
I/O
B3
DCLK, I/O
DCLK, I/O
E2
I/O
I/O
B4
I/O
I/O
E3
I/O
I/O
B5
I/O
I/O
E4
GND
GND
B6
I/O
I/O
E12
GND
GND
B7
I/O
I/O
E13
I/O
I/O
B8
CLKB, I/O
CLKB, I/O
E14
I/O
I/O
B9
I/O
I/O
E15
I/O
I/O
B10
I/O
I/O
F1
I/O
I/O
B11
I/O
I/O
F2
I/O
I/O
B12
I/O
I/O
F3
I/O
I/O
B13
I/O
I/O
F4
VCC
VCC
B14
SDI, I/O
SDI, I/O
F12
GND
GND
B15
I/O
I/O
F13
I/O
I/O
C1
I/O
I/O
F14
I/O
I/O
C2
I/O
I/O
F15
I/O
I/O
C3
MODE
MODE
G1
I/O
I/O
C4
I/O
I/O
G2
I/O
I/O
C5
I/O
I/O
G3
I/O
I/O
C6
I/O
I/O
G4
GND
GND
C7
I/O
I/O
G12
VCC
VCC
C8
GND
GND
G13
I/O
I/O
C9
PRA, I/O
PRA, I/O
G14
I/O
I/O
C10
I/O
I/O
G15
I/O
I/O
C11
I/O
I/O
H1
I/O
I/O
C12
I/O
I/O
H2
VCC
VCC
C13
I/O
I/O
H3
VCC
VCC
C14
I/O
I/O
H4
GND
GND
65
176- P in CP GA (C ont inu ed)
66
Pin Number
A1280A
Function
A1280XL
Function
Pin Number
A1280A
Function
A1280XL
Function
H12
GND
GND
N2
I/O
I/O
H13
VCC
VCC
N3
I/O
I/O
H14
VCC
VCC
N4
I/O
I/O
H15
I/O
I/O
N5
I/O
I/O
J1
I/O
I/O
N6
I/O
I/O
J2
I/O
I/O
N7
I/O
I/O
J3
I/O
I/O
N8
VCC
VCC
J4
VCC
VCC
N9
I/O
I/O
J12
GND
GND
N10
I/O
I/O
J13
GND
GND
N11
I/O
I/O
J14
VCC
VCC
N12
I/O
I/O
J15
I/O
I/O
N13
I/O
I/O
K1
I/O
I/O
N14
I/O
I/O
K2
I/O
I/O
N15
I/O
I/O
K3
I/O
I/O
P1
I/O
I/O
K4
GND
GND
P2
I/O
I/O
K12
GND
GND
P3
I/O
I/O
K13
I/O
I/O
P4
I/O
I/O
K14
I/O
I/O
P5
I/O
I/O
K15
I/O
I/O
P6
I/O
I/O
L1
I/O
I/O
P7
I/O
I/O
L2
I/O
I/O
P8
I/O
I/O
L3
I/O
I/O
P9
I/O
I/O
L4
GND
GND
P10
I/O
I/O
L12
I/O
I/O
P11
I/O
I/O
L13
I/O
I/O
P12
I/O
I/O
L14
I/O
I/O
P13
I/O
I/O
L15
I/O
I/O
P14
I/O
I/O
M1
I/O
I/O
P15
I/O
I/O
M2
I/O
I/O
R1
I/O
I/O
M3
I/O
I/O
R2
I/O
I/O
M4
GND
GND
R3
I/O
I/O
M5
VCC
VCC
R4
I/O
I/O
M6
GND
GND
R5
I/O
I/O
M7
I/O
I/O
R6
I/O
I/O
M8
GND
GND
R7
I/O
I/O
M9
I/O
I/O
R8
I/O
I/O
M10
GND
GND
R9
I/O
I/O
M11
VCC
VCC
R10
I/O
I/O
M12
GND
GND
R11
I/O
I/O
M13
I/O
I/O
R12
I/O
I/O
M14
I/O
I/O
R13
I/O
I/O
M15
I/O
I/O
R14
I/O
I/O
N1
I/O
I/O
R15
I/O
I/O
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
207- P in CP GA (T op Vi ew)
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
207-Pin
CPGA
J
H
J
K
K
L
L
M
M
N
N
P
P
R
R
S
S
T
T
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17
67
207- P in CP GA
68
Pin Number
A1460A
Function
Pin Number
A1460A
Function
Pin Number
A1460A
Function
A1
NC
C10
I/O
G3
I/O
A2
NC
C11
I/O
G4
I/O
A3
I/O
C12
I/O
G14
I/O
A4
I/O
C13
I/O
G15
I/O
A5
I/O
C14
I/O
G16
I/O
A6
I/O
C15
GND
G17
I/O
A7
I/O
C16
I/O
H1
PRA, I/O
A8
I/O
C17
I/O
H2
I/O
A9
I/O
D1
I/O
H3
I/O
A10
I/O
D2
I/O
H4
I/O
A11
I/O
D3
I/O
H14
I/O
A12
I/O
D4
GND
H15
I/O
A13
I/O
D5
GND
H16
I/O
A14
I/O
D6
I/O
H17
I/O
A15
I/O
D7
MODE
J1
I/O
A16
NC
D8
I/O
J2
VCC
A17
NC
D9
GND
J3
CLKB, I/O
B1
NC
D10
I/O
J4
GND
B2
VCC
D11
VCC
J14
GND
B3
I/O
D12
I/O
J15
HCLK, I/O
B4
I/O
D13
I/O
J16
VCC
B5
I/O
D14
GND
J17
I/O
B6
I/O
D15
I/O
K1
CLKA, I/O
B7
I/O
D16
I/O
K2
I/O
B8
I/O
D17
I/O
K3
I/O
B9
VCC
E1
I/O
K4
I/O
B10
I/O
E2
I/O
K14
I/O
B11
I/O
E3
I/O
K15
I/O
B12
I/O
E4
DCLK, I/O
K16
PRB, I/O
B13
I/O
E14
I/O
K17
I/O
B14
I/O
E15
I/O
L1
I/O
B15
I/O
E16
I/O
L2
I/O
B16
VCC
E17
I/O
L3
I/O
.
B17
NC
F1
I/O
L4
I/O
C1
NC
F2
I/O
L14
I/O
C2
NC
F3
I/O
L15
I/O
C3
SDI, I/O
F4
I/O
L16
I/O
C4
I/O
F14
I/O
L17
I/O
C5
I/O
F15
I/O
M1
I/O
C6
I/O
F16
I/O
M2
I/O
C7
I/O
F17
I/O
M3
I/O
C8
I/O
G1
I/O
M4
I/O
C9
I/O
G2
I/O
M14
I/O
H iR e l F PG A s
207- P in CP GA (C ont inu ed)
Pin Number
A1460A
Function
Pin Number
A1460A
Function
Pin Number
A1460A
Function
M15
I/O
P17
I/O
S10
I/O
M16
I/O
R1
I/O
S11
I/O
M17
I/O
R2
I/O
S12
I/O
N1
I/O
R3
I/O
S13
I/O
N2
I/O
R4
I/O
S14
I/O
N3
I/O
R5
I/O
S15
I/O
VCC
N4
I/O
R6
I/O
S16
N14
IOPCL, I/O
R7
I/O
S17
NC
N15
I/O
R8
I/O
T1
NC
N16
I/O
R9
I/O
T2
NC
N17
I/O
R10
I/O
T3
I/O
P1
I/O
R11
I/O
T4
I/O
P2
I/O
R12
I/O
T5
VCC
P3
GND
R13
I/O
T6
I/O
P4
GND
R14
I/O
T7
I/O
P5
IOCLK, I/O
R15
GND
T8
I/O
P6
I/O
R16
I/O
T9
I/O
P7
GND
R17
I/O
T10
I/O
P8
I/O
S1
NC
T11
I/O
P9
GND
S2
VCC
T12
I/O
P10
I/O
S3
NC
T13
I/O
P11
I/O
S4
I/O
T14
I/O
P12
VCC
S5
I/O
T15
I/O
P13
I/O
S6
I/O
T16
NC
P14
GND
S7
I/O
T17
NC
P15
I/O
S8
I/O
P16
I/O
S9
VCC
69
Pa c ka ge P i n A s si g nm e n t s (continued)
257- P in CP GA (T op Vi ew)
1
2
3
4
5
6
7
8
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
257-Pin
CPGA
K
J
K
L
L
M
M
N
N
P
P
R
R
T
T
V
V
X
X
Y
Y
1
70
9 10 11 12 13 14 15 16 17 18 19
A
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19
H iR e l F PG A s
257- P in CP GA
Pin Number
A14100A
Function
Pin Number
A14100A
Function
Pin Number
A14100A
Function
A1
I/O
C7
I/O
E19
I/O
A2
I/O
C8
I/O
F1
I/O
A3
I/O
C9
I/O
F2
I/O
A4
I/O
C10
VCC
F3
I/O
A5
MODE
C11
I/O
F4
I/O
A6
I/O
C12
I/O
F16
I/O
A7
I/O
C13
VCC
F17
I/O
A8
I/O
C14
I/O
F18
I/O
A9
I/O
C15
I/O
F19
I/O
A10
I/O
C16
I/O
G1
I/O
A11
I/O
C17
VCC
G2
I/O
A12
I/O
C18
I/O
G3
I/O
A13
I/O
C19
I/O
G4
I/O
A14
I/O
D1
I/O
G5
I/O
A15
I/O
D2
I/O
G15
I/O
A16
I/O
D3
I/O
G16
I/O
A17
I/O
D4
GND
G17
I/O
A18
I/O
D5
I/O
G18
I/O
A19
I/O
D6
I/O
G19
I/O
B1
I/O
D7
I/O
H1
I/O
B2
I/O
D8
I/O
H2
I/O
B3
I/O
D9
I/O
H3
I/O
B4
SDI, I/O
D10
GND
H4
I/O
B5
I/O
D11
I/O
H16
I/O
B6
I/O
D12
I/O
H17
I/O
B7
I/O
D13
I/O
H18
I/O
B8
I/O
D14
I/O
H19
I/O
B9
I/O
D15
I/O
J1
PRA, I/O
B10
I/O
D16
GND
J2
I/O
B11
I/O
D17
I/O
J3
I/O
B12
I/O
D18
I/O
J4
I/O
B13
I/O
D19
I/O
J5
GND
B14
I/O
E1
I/O
J15
I/O
B15
I/O
E2
I/O
J16
HCLK, I/O
B16
GND
E3
I/O
J17
PRB, I/O
B17
I/O
E4
DCLK, I/O
J18
I/O
B18
I/O
E5
NC
J19
I/O
B19
I/O
E7
I/O
K1
I/O
C1
I/O
E9
I/O
K2
I/O
C2
I/O
E11
GND
K3
VCC
C3
VCC
E13
I/O
K4
GND
C4
GND
E16
I/O
K16
GND
C5
I/O
E17
I/O
K17
VCC
C6
I/O
E18
I/O
K18
I/O
71
257- P in CP GA (C ont inu ed)
72
Pin Number
A14100A
Function
Pin Number
A14100A
Function
Pin Number
A14100A
Function
K19
L1
I/O
R9
I/O
V17
VCC
I/O
R11
I/O
V18
I/O
L2
I/O
R13
I/O
V19
I/O
L3
I/O
R16
IOPCL, I/O
X1
I/O
L4
CLKA, I/O
R17
I/O
X2
I/O
L5
CLKB, I/O
R18
I/O
X3
I/O
L15
GND
R19
I/O
X4
I/O
L16
I/O
T1
I/O
X5
I/O
L17
I/O
T2
I/O
X6
I/O
L18
I/O
T3
I/O
X7
GND
L19
I/O
T4
GND
X8
I/O
M1
I/O
T5
IOCLK, I/O
X9
I/O
M2
I/O
T6
I/O
X10
I/O
M3
I/O
T7
I/O
X11
I/O
M4
I/O
T8
I/O
X12
I/O
M16
I/O
T9
I/O
X13
I/O
M17
I/O
T10
GND
X14
VCC
M18
I/O
T11
I/O
X15
I/O
M19
I/O
T12
I/O
X16
I/O
N1
I/O
T13
I/O
X17
I/O
N2
I/O
T14
I/O
X18
I/O
N3
I/O
T15
I/O
X19
I/O
N4
I/O
T16
GND
Y1
I/O
N5
I/O
T17
GND
Y2
I/O
N15
I/O
T18
I/O
Y3
I/O
N16
I/O
T19
I/O
Y4
I/O
N17
I/O
V1
I/O
Y5
I/O
N18
I/O
V2
I/O
Y6
I/O
N19
I/O
V3
VCC
Y7
I/O
P1
I/O
V4
I/O
Y8
I/O
P2
I/O
V5
I/O
Y9
I/O
P3
I/O
V6
I/O
Y10
I/O
P4
I/O
V7
VCC
Y11
I/O
P16
I/O
V8
I/O
Y12
I/O
P17
I/O
V9
I/O
Y13
I/O
P18
I/O
V10
VCC
Y14
I/O
P19
I/O
V11
I/O
Y15
I/O
R1
I/O
V12
I/O
Y16
I/O
R2
I/O
V13
I/O
Y17
I/O
R3
I/O
V14
I/O
Y18
I/O
R4
GND
V15
I/O
Y19
I/O
R7
I/O
V16
I/O
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
84- Pi n CQFP (To p V iew )
Pin #1
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64
84-Pin
CQFP
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
73
84- Pi n CQFP
74
Pin Number
A1020B
Function
A32100DX
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
NC
I/O
I/O
I/O
I/O
I/O
GND
GND
I/O
I/O
I/O
I/O
I/O
VCC
VCC
I/O
I/O
I/O
I/O
GND
MODE
I/O
I/O
I/O
I/O
VCC
I/O
I/O
GND
VCC
VCC
I/O
I/O
I/O
I/O
GND
I/O
I/O
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O (WD)
I/O (WD)
I/O
QCLKA, I/O
GND
I/O (WD)
I/O
GND
VCC
I/O (WD)
I/O (WD)
QCLKB, I/O
I/O (WD)
GND
I/O (WD)
I/O (WD)
I/O (WD)
SDO, I/O
Pin Number
A1020B
Function
A32100DX
Function
43
44
45
46
47
48
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
49
50
51
52
53
54
55
56
57
58
59
60
61
GND
GND
I/O
I/O
CLKA, I/O
I/O
MODE
VCC
VCC
I/O
I/O
I/O
SDI, I/O
I/O
GND
TCK, I/O
GND
VCC
VCC
VCC
VCC
I/O
I/O
GND
I/O
I/O
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
DCLK, I/O
PRA, I/O
PRB, I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
SDI, I/O
I/O (WD)
I/O (WD)
I/O (WD)
I/O (WD)
QCLKD, I/O
I/O (WD)
I/O (WD)
PRA, I/O
CLKA, I/O
VCC
GND
CLKB, I/O
PRB, I/O
I/O (WD)
I/O (WD)
QCLKC, I/O
GND
I/O (WD)
I/O (WD)
DCLK, I/O
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
132- P in CQF P (T op Vie w)
132 131 130 129 128 127 126 125 124
107 106 105 104 103 102 101 100
Pin #1
Index
1
99
2
98
3
97
4
96
5
95
6
94
7
93
8
92
132-Pin
CQFP
25
75
26
74
27
73
28
72
29
71
30
70
31
69
32
68
33
67
34 35 36 37 38 39 40 41 42
59 60 61 62 63 64 65 66
75
132- P in CQF P
Pin Number
76
A1425A
Function
Pin Number
A1425A
Function
Pin Number
A1425A
Function
1
NC
45
I/O
89
VCC
2
GND
46
I/O
90
GND
3
SDI, I/O
47
I/O
91
VCC
4
I/O
48
PRB, I/O
92
GND
5
I/O
49
I/O
93
I/O
6
I/O
50
HCLK, I/O
94
I/O
7
I/O
51
I/O
95
I/O
8
I/O
52
I/O
96
I/O
9
MODE
53
I/O
97
I/O
10
GND
54
I/O
98
IOCLK, I/O
11
VCC
55
I/O
99
NC
12
I/O
56
I/O
100
NC
13
I/O
57
I/O
101
GND
14
I/O
58
GND
102
I/O
15
I/O
59
VCC
103
I/O
16
I/O
60
I/O
104
I/O
17
I/O
61
I/O
105
I/O
18
I/O
62
I/O
106
GND
19
I/O
63
I/O
107
VCC
20
I/O
64
IOPCL, I/O
108
I/O
21
I/O
65
GND
109
I/O
22
VCC
66
NC
110
I/O
23
I/O
67
NC
111
I/O
24
I/O
68
I/O
112
I/O
25
I/O
69
I/O
113
I/O
26
GND
70
I/O
114
I/O
27
VCC
71
I/O
115
I/O
28
I/O
72
I/O
116
CLKA, I/O
29
I/O
73
I/O
117
CLKB, I/O
30
I/O
74
GND
118
PRA, I/O
31
I/O
75
VCC
119
I/O
32
I/O
76
I/O
120
I/O
33
I/O
77
I/O
121
I/O
34
NC
78
VCC
122
GND
35
I/O
79
I/O
123
VCC
36
GND
80
I/O
124
I/O
37
I/O
81
I/O
125
I/O
38
I/O
82
I/O
126
I/O
39
I/O
83
I/O
127
I/O
40
I/O
84
I/O
128
I/O
41
I/O
85
I/O
129
I/O
42
GND
86
I/O
130
I/O
43
VCC
87
I/O
131
DCLK, I/O
44
I/O
88
I/O
132
NC
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
172- P in CQF P (T op Vie w)
172 171 170 169 168 167 166 165 164
137 136 135 134 133 132 131 130
Pin #1
Index
1
129
2
128
3
127
4
126
5
125
6
124
7
123
8
122
172-Pin
CQFP
35
95
36
94
37
93
38
92
39
91
40
90
41
89
42
88
43
87
44 45 46 47 48 49 50 51 52
79 80 81 82 83 84 85 86
77
172- P in CQF P
78
Pin Number
A1280A
Function
A1280XL
Function
Pin Number
A1280A
Function
A1280XL
Function
1
MODE
MODE
45
I/O
I/O
2
I/O
I/O
46
I/O
I/O
3
I/O
I/O
47
I/O
I/O
4
I/O
I/O
48
I/O
I/O
5
I/O
I/O
49
I/O
I/O
6
I/O
I/O
50
VCC
VCC
7
GND
GND
51
I/O
I/O
8
I/O
I/O
52
I/O
I/O
9
I/O
I/O
53
I/O
I/O
10
I/O
I/O
54
I/O
I/O
11
I/O
I/O
55
GND
GND
12
VCC
VCC
56
I/O
I/O
13
I/O
I/O
57
I/O
I/O
14
I/O
I/O
58
I/O
I/O
15
I/O
I/O
59
I/O
I/O
16
I/O
I/O
60
I/O
I/O
17
GND
GND
61
I/O
I/O
18
I/O
I/O
62
I/O
I/O
19
I/O
I/O
63
I/O
I/O
20
I/O
I/O
64
I/O
I/O
21
I/O
I/O
65
GND
GND
22
GND
GND
66
VCC
VCC
23
VCC
VCC
67
I/O
I/O
24
VCC
VCC
68
I/O
I/O
25
I/O
I/O
69
I/O
I/O
26
I/O
I/O
70
I/O
I/O
27
VCC
VCC
71
I/O
I/O
28
I/O
I/O
72
I/O
I/O
29
I/O
I/O
73
I/O
I/O
30
I/O
I/O
74
I/O
I/O
31
I/O
I/O
75
GND
GND
32
GND
GND
76
I/O
I/O
33
I/O
I/O
77
I/O
I/O
34
I/O
I/O
78
I/O
I/O
35
I/O
I/O
79
I/O
I/O
36
I/O
I/O
80
VCC
VCC
37
GND
GND
81
I/O
I/O
38
I/O
I/O
82
I/O
I/O
39
I/O
I/O
83
I/O
I/O
40
I/O
I/O
84
I/O
I/O
41
I/O
I/O
85
I/O
I/O
42
I/O
I/O
86
I/O
I/O
43
I/O
I/O
87
I/O
I/O
44
I/O
I/O
88
I/O
I/O
H iR e l F PG A s
172- P in CQF P (Co nti nue d)
Pin Number
A1280A
Function
A1280XL
Function
Pin Number
A1280A
Function
A1280XL
Function
89
I/O
I/O
131
SDI, I/O
SDI, I/O
90
I/O
I/O
132
I/O
I/O
91
I/O
I/O
133
I/O
I/O
92
I/O
I/O
134
I/O
I/O
93
I/O
I/O
135
I/O
I/O
94
I/O
I/O
136
VCC
VCC
95
I/O
I/O
137
I/O
I/O
96
I/O
I/O
138
I/O
I/O
97
I/O
I/O
139
I/O
I/O
98
GND
GND
140
I/O
I/O
99
I/O
I/O
141
GND
GND
100
I/O
I/O
142
I/O
I/O
101
I/O
I/O
143
I/O
I/O
102
I/O
I/O
144
I/O
I/O
103
GND
GND
145
I/O
I/O
104
I/O
I/O
146
I/O
I/O
105
I/O
I/O
147
I/O
I/O
106
GND
GND
148
PRA, I/O
PRA, I/O
107
VCC
VCC
149
I/O
I/O
108
GND
GND
150
CLKA, I/O
CLKA, I/O
109
VCC
VCC
151
VCC
VCC
110
VCC
VCC
152
GND
GND
111
I/O
I/O
153
I/O
I/O
112
I/O
I/O
154
CLKB, I/O
CLKB, I/O
113
VCC
VCC
155
I/O
I/O
114
I/O
I/O
156
PRB, I/O
PRB, I/O
115
I/O
I/O
157
I/O
I/O
116
I/O
I/O
158
I/O
I/O
117
I/O
I/O
159
I/O
I/O
118
GND
GND
160
I/O
I/O
119
I/O
I/O
161
GND
GND
120
I/O
I/O
162
I/O
I/O
121
I/O
I/O
163
I/O
I/O
122
I/O
I/O
164
I/O
I/O
123
GND
GND
165
I/O
I/O
124
I/O
I/O
166
VCC
VCC
125
I/O
I/O
167
I/O
I/O
126
I/O
I/O
168
I/O
I/O
127
I/O
I/O
169
I/O
I/O
128
I/O
I/O
170
I/O
I/O
129
I/O
I/O
171
DCLK, I/O
DCLK, I/O
130
I/O
I/O
172
I/O
I/O
79
Pa c ka ge P i n A s si g nm e n t s (continued)
196- P in CQF P (T op Vie w)
196 195 194 193 192 191 190 189 188
155 154 153 152 151 150 149 148
Pin #1
Index
1
147
2
146
3
145
4
144
5
143
6
142
7
141
8
140
196-Pin
CQFP
41
107
42
106
43
105
44
104
45
103
46
102
47
101
48
100
49
99
50 51 52 53 54 55 56 57 58
80
91 92 93 94 95 96 97 98
H iR e l F PG A s
196- P in CQF P
A1460A
Function
Pin Number
A1460A
Function
Pin Number
A1460A
Function
1
GND
44
I/O
87
I/O
2
SDI, I/O
45
I/O
88
I/O
3
I/O
46
I/O
89
I/O
4
I/O
47
I/O
90
I/O
5
I/O
48
I/O
91
I/O
6
I/O
49
I/O
92
I/O
7
I/O
50
I/O
93
I/O
8
I/O
51
GND
94
VCC
9
I/O
52
GND
95
I/O
Pin Number
10
I/O
53
I/O
96
I/O
11
MODE
54
I/O
97
I/O
12
VCC
55
I/O
98
GND
13
GND
56
I/O
99
I/O
14
I/O
57
I/O
100
IOPCL, I/O
15
I/O
58
I/O
101
GND
16
I/O
59
VCC
102
I/O
17
I/O
60
I/O
103
I/O
18
I/O
61
I/O
104
I/O
19
I/O
62
I/O
105
I/O
20
I/O
63
I/O
106
I/O
21
I/O
64
GND
107
I/O
22
I/O
65
I/O
108
I/O
23
I/O
66
I/O
109
I/O
24
I/O
67
I/O
110
VCC
25
I/O
68
I/O
111
VCC
26
I/O
69
I/O
112
GND
27
I/O
70
I/O
113
I/O
28
I/O
71
I/O
114
I/O
29
I/O
72
I/O
115
I/O
30
I/O
73
I/O
116
I/O
31
I/O
74
I/O
117
I/O
32
I/O
75
PRB, I/O
118
I/O
33
I/O
76
I/O
119
I/O
34
I/O
77
HCLK, I/O
120
I/O
35
I/O
78
I/O
121
I/O
36
I/O
79
I/O
122
I/O
37
GND
80
I/O
123
I/O
38
VCC
81
I/O
124
I/O
39
VCC
82
I/O
125
I/O
40
I/O
83
I/O
126
I/O
41
I/O
84
I/O
127
I/O
42
I/O
85
I/O
128
I/O
43
I/O
86
GND
129
I/O
81
196- P in CQF P (Co nti nue d)
82
Pin Number
A1460A
Function
Pin Number
A1460A
Function
Pin Number
A1460A
Function
130
I/O
153
I/O
176
I/O
131
I/O
154
I/O
177
I/O
132
I/O
155
VCC
178
I/O
133
I/O
156
I/O
179
I/O
134
I/O
157
I/O
180
I/O
135
I/O
158
I/O
181
I/O
136
I/O
159
I/O
182
I/O
137
VCC
160
I/O
183
GND
138
GND
161
I/O
184
I/O
139
GND
162
GND
185
I/O
140
VCC
163
I/O
186
I/O
141
I/O
164
I/O
187
I/O
142
I/O
165
I/O
188
I/O
143
I/O
166
I/O
189
VCC
144
I/O
167
I/O
190
I/O
145
I/O
168
I/O
191
I/O
146
I/O
169
I/O
192
I/O
147
I/O
170
I/O
193
GND
148
IOCLK, I/O
171
I/O
194
I/O
149
GND
172
CLKA, I/O
195
I/O
150
I/O
173
CLKB, I/O
196
DCLK, I/O
151
I/O
174
PRA, I/O
152
I/O
175
I/O
H iR e l F PG A s
Pa c ka ge P i n A s si g nm e n t s (continued)
208- P in CQF P (T op Vie w)
208 207 206 205 204 203 202 201 200
164 163 162 161 160 159 158 157
Pin #1
Index
1
156
2
155
3
154
4
153
5
152
6
151
7
150
8
149
208-Pin
CQFP
44
113
45
112
46
111
47
110
48
109
49
108
50
107
51
106
52
105
53 54 55 56 57 58 59 60 61
97 98 99 100 101 102 103 104
83
208- P in CQF P
84
Pin Number
A32100DX
Function
Pin Number
A32100DX
Function
Pin Number
A32100DX
Function
1
GND
44
I/O
87
I/O
2
VCC
45
I/O
88
I/O
3
MODE
46
I/O
89
I/O
4
I/O
47
I/O
90
I/O
5
I/O
48
I/O
91
QCLKB, I/O
6
I/O
49
I/O
92
I/O
7
I/O
50
I/O
93
I/O (WD)
8
I/O
51
I/O
94
I/O (WD)
9
I/O
52
GND
95
I/O
10
I/O
53
GND
96
I/O
11
I/O
54
TMS, I/O
97
I/O
12
I/O
55
TDI, I/O
98
VCC
13
I/O
56
I/O
99
I/O
14
I/O
57
I/O (WD)
100
I/O (WD)
15
I/O
58
I/O (WD)
101
I/O (WD)
16
I/O
59
I/O
102
I/O
17
VCC
60
VCC
103
SDO, I/O
18
I/O
61
I/O
104
I/O
19
I/O
62
I/O
105
GND
20
I/O
63
I/O
106
VCC
21
I/O
64
I/O
107
I/O
22
GND
65
QCLKA, I/O
108
I/O
23
I/O
66
I/O (WD)
109
I/O
24
I/O
67
I/O (WD)
110
I/O
25
I/O
68
I/O
111
I/O
26
I/O
69
I/O
112
I/O
27
GND
70
I/O (WD)
113
I/O
28
VCC
71
I/O (WD)
114
I/O
29
VCC
72
I/O
115
I/O
30
I/O
73
I/O
116
I/O
31
I/O
74
I/O
117
I/O
32
VCC
75
I/O
118
I/O
33
I/O
76
I/O
119
I/O
34
I/O
77
I/O
120
I/O
35
I/O
78
GND
121
I/O
36
I/O
79
VCC
122
I/O
37
I/O
80
VCC
123
I/O
38
I/O
81
I/O
124
I/O
39
I/O
82
I/O
125
I/O
40
I/O
83
I/O
126
GND
41
I/O
84
I/O
127
I/O
42
I/O
85
I/O (WD)
128
TCK, I/O
43
I/O
86
I/O (WD)
129
GND
H iR e l F PG A s
208- P in CQF P (Co nti nue d)
Pin Number
A32100DX
Function
Pin Number
A32100DX
Function
Pin Number
A32100DX
Function
GND
130
VCC
157
GND
184
131
GND
158
I/O
185
I/O
132
VCC
159
SDI, I/O
186
CLKB, I/O
133
VCC
160
I/O
187
I/O
134
I/O
161
I/O (WD)
188
PRB, I/O
135
I/O
162
I/O (WD)
189
I/O
136
VCC
163
I/O
190
I/O (WD)
137
I/O
164
VCC
191
I/O (WD)
138
I/O
165
I/O
192
I/O
139
I/O
166
I/O
193
I/O
140
I/O
167
I/O
194
I/O (WD)
141
I/O
168
I/O (WD)
195
I/O (WD)
142
I/O
169
I/O (WD)
196
QCLKC, I/O
143
I/O
170
I/O
197
I/O
144
I/O
171
QCLKD, I/O
198
I/O
145
I/O
172
I/O
199
I/O
146
I/O
173
I/O
200
I/O
147
I/O
174
I/O
201
I/O
148
I/O
175
I/O
202
VCC
149
I/O
176
I/O (WD)
203
I/O (WD)
150
GND
177
I/O (WD)
204
I/O (WD)
151
I/O
178
PRA, I/O
205
I/O
152
I/O
179
I/O
206
I/O
153
I/O
180
CLKA, I/O
207
DCLK, I/O
154
I/O
181
I/O
208
I/O
155
I/O
182
VCC
156
I/O
183
VCC
85
Pa c ka ge P i n A s si g nm e n t s (continued)
256- P in CQF P (T op Vie w)
256 255 254 253 252 251 250 249 248
200 199 198 197 196 195 194 193
Pin #1
Index
1
192
2
191
3
190
4
189
5
188
6
187
7
186
8
185
256-Pin
CQFP
56
137
57
136
58
135
59
134
60
133
61
132
62
131
63
130
64
129
65 66 67 68 69 70 71 72 73
86
121 122 123 124 125 126 127 128
H iR e l F PG A s
256- P in CQF P
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
1
GND
NC
45
I/O
I/O
89
I/O
I/O
2
SDI, I/O
GND
46
VCC
I/O
90
PRB, I/O
I/O
3
I/O
I/O
47
I/O
I/O
91
GND
I/O
4
I/O
I/O
48
I/O
GND
92
VCC
I/O
5
I/O
I/O
49
I/O
I/O
93
GND
I/O
6
I/O
I/O
50
I/O
I/O
94
VCC
I/O
7
I/O
I/O
51
I/O
I/O
95
I/O
VCC
8
I/O
I/O
52
I/O
I/O
96
HCLK, I/O
VCC
9
I/O
I/O
53
I/O
I/O
97
I/O
GND
10
I/O
GND
54
I/O
I/O
98
I/O
GND
11
MODE
I/O
55
I/O
I/O
99
I/O
I/O
12
I/O
I/O
56
I/O
I/O
100
I/O
I/O
13
I/O
I/O
57
I/O
I/O
101
I/O
I/O
14
I/O
I/O
58
I/O
I/O
102
I/O
I/O
15
I/O
I/O
59
GND
I/O
103
I/O
I/O
16
I/O
I/O
60
I/O
VCC
104
I/O
I/O
17
I/O
I/O
61
I/O
GND
105
I/O
I/O (WD)
18
I/O
I/O
62
I/O
GND
106
I/O
I/O (WD)
19
I/O
I/O
63
I/O
NC
107
I/O
I/O
20
I/O
I/O
64
I/O
NC
108
I/O
I/O
21
I/O
I/O
65
I/O
NC
109
I/O
I/O (WD)
22
I/O
I/O
66
I/O
I/O
110
GND
I/O (WD)
23
I/O
I/O
67
I/O
SDO, I/O
111
I/O
I/O
24
I/O
I/O
68
I/O
I/O
112
I/O
QCLKA, I/O
25
I/O
I/O
69
I/O
I/O (WD)
113
I/O
I/O
26
I/O
VCC
70
I/O
I/O (WD)
114
I/O
GND
27
I/O
I/O
71
I/O
I/O
115
I/O
I/O
28
VCC
I/O
72
I/O
VCC
116
I/O
I/O
29
GND
VCC
73
I/O
I/O
117
I/O
I/O
30
VCC
VCC
74
I/O
I/O
118
I/O
I/O
31
GND
GND
75
I/O
I/O
119
I/O
VCC
32
I/O
VCC
76
I/O
I/O (WD)
120
I/O
I/O
33
I/O
GND
77
I/O
GND
121
I/O
I/O (WD)
34
I/O
TCK, I/O
78
I/O
I/O (WD)
122
I/O
I/O (WD)
35
I/O
I/O
79
I/O
I/O
123
I/O
I/O
36
I/O
GND
80
I/O
QCLKB, I/O
124
I/O
I/O
37
I/O
I/O
81
I/O
I/O
125
I/O
TDI, I/O
38
I/O
I/O
82
I/O
I/O
126
I/O
TMS, I/O
39
I/O
I/O
83
I/O
I/O
127
IOPCL, I/O
GND
40
I/O
I/O
84
I/O
I/O
128
GND
NC
41
I/O
I/O
85
I/O
I/O
129
I/O
NC
42
I/O
I/O
86
I/O
I/O
130
I/O
NC
43
I/O
I/O
87
I/O
I/O (WD)
131
I/O
GND
44
I/O
I/O
88
I/O
I/O (WD)
132
I/O
I/O
87
256- P in CQF P (Co nti nue d)
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
A32200DX
Function
Pin
Number
A14100A
Function
133
I/O
I/O
175
GND
I/O
217
I/O
I/O
134
I/O
I/O
176
GND
I/O
218
I/O
PRB, I/O
135
I/O
I/O
177
I/O
I/O
219
CLKA, I/O
I/O
136
I/O
I/O
178
I/O
I/O
220
CLKB, I/O
CLKB, I/O
137
I/O
I/O
179
I/O
I/O
221
VCC
I/O
88
A32200DX
Function
138
I/O
I/O
180
I/O
GND
222
GND
GND
139
I/O
GND
181
I/O
I/O
223
VCC
GND
140
I/O
I/O
182
I/O
I/O
224
GND
VCC
141
VCC
I/O
183
I/O
I/O
225
PRA, I/O
VCC
142
I/O
I/O
184
I/O
I/O
226
I/O
I/O
143
I/O
I/O
185
I/O
I/O
227
I/O
CLKA, I/O
144
I/O
I/O
186
I/O
I/O
228
I/O
I/O
145
I/O
I/O
187
I/O
I/O
229
I/O
PRA, I/O
146
I/O
I/O
188
IOCLK, I/O
MODE
230
I/O
I/O
147
I/O
I/O
189
GND
VCC
231
I/O
I/O
148
I/O
I/O
190
I/O
GND
232
I/O
I/O (WD)
149
I/O
I/O
191
I/O
NC
233
I/O
I/O (WD)
150
I/O
I/O
192
I/O
NC
234
I/O
I/O
151
I/O
I/O
193
I/O
NC
235
I/O
I/O
152
I/O
I/O
194
I/O
I/O
236
I/O
I/O
153
I/O
I/O
195
I/O
DCLK, I/O
237
I/O
I/O
154
I/O
I/O
196
I/O
I/O
238
I/O
I/O
155
I/O
VCC
197
I/O
I/O
239
I/O
I/O
156
I/O
I/O
198
I/O
I/O
240
GND
QCLKD, I/O
157
I/O
I/O
199
I/O
I/O (WD)
241
I/O
I/O
158
GND
VCC
200
I/O
I/O (WD)
242
I/O
I/O (WD)
159
VCC
VCC
201
I/O
VCC
243
I/O
GND
160
GND
GND
202
I/O
I/O
244
I/O
I/O (WD)
161
VCC
I/O
203
I/O
I/O
245
I/O
I/O
162
I/O
I/O
204
I/O
I/O
246
I/O
I/O
163
I/O
I/O
205
I/O
I/O
247
I/O
I/O
VCC
164
I/O
I/O
206
I/O
GND
248
I/O
165
I/O
GND
207
I/O
I/O
249
I/O
I/O
166
I/O
I/O
208
I/O
I/O
250
I/O
I/O (WD)
167
I/O
I/O
209
I/O
QCLKC, I/O
251
I/O
I/O (WD)
168
I/O
I/O
210
I/O
I/O
252
I/O
I/O
SDI, I/O
169
I/O
I/O
211
I/O
I/O (WD)
253
I/O
170
I/O
VCC
212
I/O
I/O (WD)
254
I/O
I/O
171
I/O
I/O
213
I/O
I/O
255
I/O
GND
172
I/O
I/O
214
I/O
I/O
256
DCLK, I/O
NC
173
I/O
I/O
215
I/O
I/O (WD)
174
VCC
I/O
216
I/O
I/O (WD)
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s
84- Pi n CP GA
.050" ± .010"
Pin #1 ID
.045
.055
0.18" ± .002"
.100" BSC
1.100" ± .020" square
.080"
.110"
.120"
.140"
L
K
J
H
G
1.000 BSC
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
Orientation Pin
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
89
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
132-Pin CPGA
.085"
.110"
Pin #1 ID
.045
.055
0.18" ± .002"
.100" BSC
.050" ± .010"
1.360" ± .015" square
.120"
.140"
N
M
L
K
J
H
1.200 BSC
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
Orientation Pin
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
90
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
133- P in CP GA
Top View
0.100"
0.130"
Pin #1
0.045"
0.055"
0.018" ± 0.002"
0.100" BSC
0.050" ± 0.010"
1.360" ± 0.015" square
0.120"
0.140"
N
Side View
M
L
K
J
H
1.200" BSC
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
13
Orientation Pin
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
91
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
176- P in CP GA
INDEX MARK
0.102"
0.132"
0.100" BSC
0.018" ± .002"
0.050" ± .005"
0.120"
0.140"
1.570" ± .015" square
R
P
N
M
L
K
J
1.400 BSC
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
92
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
207- P in CP GA
Top View
INDEX MARK
0.120" ± 0.015"
0.100" BSC
0.018" ± 0.002"
0.05" ± 0.005"
0.180" ± 0.010"
1.77" ± 0.010" square
0.05" ± 0.005"
Side View
U
T
R
P
N
M
L
K
1.600" BSC
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13
14
15
16
17
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
93
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
257- P in CP GA
Top View
0.105" ± 0.012"
0.100" BSC
0.018" ± 0.002"
0.05" ± 0.005"
0.180" ± 0.010"
1.970" ± 0.015" square
0.05" ± 0.01"
Y
Side View
X
V
T
R
P
N
M
L
1.800" BSC
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
Bottom View
Notes:
1. All dimensions are in inches unless otherwise stated.
2. BSC—Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
94
H iR e l F PG A s
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
84- Pi n CQFP
Top View
D1
D2
H
E2
E1
F
e
b
L1
Side View
A
Lid
c
A1
Notes:
1. Seal ring and lid are connected to Ground.
2. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
3. Packages are shipped unformed with the ceramic tie bar in a test carrier.
95
Pa c ka ge M e ch an i c al D r a w i ng s (continued)
132-Pin, 172-Pin, 196-Pin, 208-Pin, and 256-Pin CQFP (Cavity Up)
Top View
H
D1
D2
No. 1
Ceramic
Tie Bar
L1
E2
F
e
b
Side View
Lid
A
A1
Notes:
1. Outside leadframe holes (from dimension H) are circular for the CQ208 and CQ256.
2. Seal ring and lid are connected to Ground.
3. Lead material is Kovar with minimum 50 microinches gold plate over nickel.
4. Packages are shipped unformed with the ceramic tie bar.
5. 32200DX – CQ208 has a heat sink on the back.
96
C
Lead Kovar
E1
K
H iR e l F PG A s
CQFP (Ce ram i c Q uad Fla t Pa ck)
CQFP 84
CQFP 132
CQFP 172
CQFP 196
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
Min.
Nom.
Max.
Min.
Nom.
Max.
A
0.070
0.090
0.100
0.094
0.105
0.116
0.094
0.105
0.116
0.094
0.105
0.116
A1
0.060
0.075
0.080
0.080
0.090
0.100
0.080
0.090
0.100
0.080
0.090
0.100
b
0.008
0.010
0.012
0.007
0.008
0.010
0.007
0.008
0.010
0.007
0.008
0.010
c
0.004
0.006
0.008
0.004
0.006
0.008
0.004
0.006
0.008
0.004
0.006
0.008
D1/E1
0.640
0.650
0.660
0.940
0.950
0.960
1.168
1.180
1.192
1.336
1.350
1.364
D2/E2
0.500 BSC
0.800 BSC
1.050 BSC
1.200 BSC
e
0.025 BSC
0.025 BSC
0.025 BSC
0.025 BSC
F
0.130
0.140
0.150
0.325
0.350
0.375
0.175
0.200
0.225
0.175
0.200
H
1.460 BSC
2.320 BSC
2.320 BSC
2.320 BSC
K
—
2.140 BSC
2.140 BSC
2.140 BSC
L1
1.595
1.600
1.615
2.485
2.500
2.505
2.485
2.495
2.505
2.485
2.495
0.225
2.505
Note:
1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
CQFP (Ce ram i c Q uad Fla t Pa ck)
CQFP 208
CQFP 256
Symbol
Min.
Nom.
Max.
Min.
Nom.
Max.
A
2.78
3.17
3.56
2.28
2.67
3.06
A1
2.43
2.79
3.15
1.93
2.29
2.65
b
0.18
0.20
0.22
0.18
0.20
0.22
c
0.11
0.15
0.17
0.11
0.15
0.18
D1/E1
28.96
29.21
29.46
35.64
36.00
36.36
D2/E2
25.5 BSC
31.5 BSC
e
0.50 BSC
0.50 BSC
F
7.05
7.75
8.45
7.05
7.75
H
70.00 BSC
70.00 BSC
K
65.90 BSC
65.90 BSC
L1
74.60
75.00
75.40
74.60
75.00
8.45
75.40
Note:
1. All dimensions are in inches except CQ208 and CQ256, which are in millimeters.
2. BSC equals Basic Spacing between Centers. This is a theoretical true position dimension and so has no tolerance.
97
Actel and the Actel logo are registered trademarks of Actel Corporation.
All other trademarks are the property of their owners.
http://www.actel.com
Actel Europe Ltd.
Daneshill House, Lutyens Close
Basingstoke, Hampshire RG24 8AG
United Kingdom
Tel: +44-(0)125-630-5600
Fax: +44-(0)125-635-5420
Actel Corporation
955 East Arques Avenue
Sunnyvale, California 94086
USA
Tel: (408) 739-1010
Fax: (408) 739-1540
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Fax: +81-(0)3-3445-7668
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