DS2316
Datasheet
40MX and 42MX FPGA
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Fax: +1 (949) 215-4996
Email: sales.support@microsemi.com
www.microsemi.com
© 2016 Microsemi Corporation. All
rights reserved. Microsemi and the
Microsemi logo are trademarks of
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of
its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the
application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have
been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any
performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all
performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer's responsibility to
independently determine suitability of any products and to test and verify the same. The information provided by Microsemi
hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely
with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP
rights, whether with regard to such information itself or anything described by such information. Information provided in this
document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
document or to any products and services at any time without notice.
About Microsemi
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor and system solutions for
aerospace & defense, communications, data center and industrial markets. Products include high-performance and
radiation-hardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products;
timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing
devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and
scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design
capabilities and services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800 employees
globally. Learn more at www.microsemi.com.
5172136. 15.0 12/16
Contents
1 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Revision 15.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 14.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 13.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 12.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 11.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 10.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 9.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 6.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
1
1
1
2
2
2 40MX and 42MX FPGA Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1
High Capacity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2
High Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3
HiRel Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.4
Ease of Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Product Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
1
1
1
1
1
3
4
4
5
5
3 40MX and 42MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
3.2
3.3
3.4
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.1
Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2.2
Dual-Port SRAM Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.2.3
Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2.4
Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.5
MultiPlex I/O Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.2
User Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.3
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3.4
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.5
Power-Up/Down in Mixed-Voltage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.6
Transient Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.7
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.1
General Power Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.2
Static Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.3
Active Power Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4.4
Equivalent Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.5
CEQ Values for Microsemi MX FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.4.6
Test Circuitry and Silicon Explorer II Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4.7
Design Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.8
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.9
JTAG Mode Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4.10 TRST Pin and TAP Controller Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
DS2316 Datasheet Revision 15.0
iii
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.4.11 Boundary Scan Description Language (BSDL) File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.1
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.2
User Guides and Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6.3
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.0 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7.1
5 V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8.1
3.3 V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.9.1
Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.2
Output Drive Characteristics for 5.0 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9.3
Output Drive Characteristics for 3.3 V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.9.4
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9.5
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.10.1 Parameter Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.10.2 Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.10.3 Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.10.4 Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10.5 SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10.6 Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.10.7 Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.11.1 Critical Nets and Typical Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.11.2 Long Tracks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.11.3 Timing Derating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11.4 Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.11.5 PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.11.6 PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
4 Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
DS2316 Datasheet Revision 15.0
iv
Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
42MX C-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
42MX C-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
42MX S-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
A42MX24 and A42MX36 D-Module Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
A42MX36 Dual-Port SRAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MX Routing Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Networks of 42MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Quadrant Clock Network of A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
42MX I/O Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
PCI Output Structure of A42MX24 and A42MX36 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Silicon Explorer II Setup with 40MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Silicon Explorer II Setup with 42MX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
42MX IEEE 1149.1 Boundary Scan Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Device Selection Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Typical Output Drive Characteristics (Based Upon Measured Data) . . . . . . . . . . . . . . . . . . . . . . . 28
40MX Timing Model* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
42MX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
42MX Timing Model (Logic Functions Using Quadrant Clocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
42MX Timing Model (SRAM Functions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Module Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flip-Flops and Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Input Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Output Buffer Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
42MX SRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
42MX SRAM Synchronous Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
42MX SRAM Asynchronous Read Operation—Type 1 (Read Address Controlled) . . . . . . . . . . . . 36
42MX SRAM Asynchronous Read Operation—Type 2 (Write Address Controlled) . . . . . . . . . . . . 37
42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
42MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
40MX Junction Temperature and Voltage Derating Curves
(Normalized to TJ = 25°C, VCC = 3.3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
DS2316 Datasheet Revision 15.0
v
Figure 51
Figure 52
Figure 53
BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS2316 Datasheet Revision 15.0
vi
Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Plastic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ceramic Device Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Temperature Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Speed Grade Offerings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage Support of MX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Fixed Capacitance Values for MX FPGAs (pF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Device Configuration Options for Probe Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Test Access Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Supported BST Public Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Boundary Scan Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute Maximum Ratings for 40MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Absolute Maximum Ratings for 42MX Devices* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC Specification (5.0 V PCI Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AC Specifications (5.0V PCI Signaling)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Specification (3.3 V PCI Signaling) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
AC Specifications for (3.3 V PCI Signaling)* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
42MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCCA = 5.0 V) . . . 38
40MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCC = 5.0 V) . . . . . 38
42MX Temperature and Voltage Derating Factors(Normalized to TJ = 25°C, VCCA = 3.3 V) . . . . 39
40MX Temperature and Voltage Derating Factors (Normalized to TJ = 25°C, VCC = 3.3 V) . . . . 39
Clock Specification for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Timing Parameters for 33 MHz PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
A40MX02 Timing Characteristics (Nominal 5.0 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
A40MX02 Timing Characteristics (Nominal 3.3 V Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
A40MX04 Timing Characteristics (Nominal 5.0 V Operation) (Worst-Case Commercial Conditions,
VCC = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
A40MX04 Timing Characteristics (Nominal 3.3 V Operation) (Worst-Case Commercial Conditions,
VCC = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
A42MX09 Timing Characteristics (Nominal 5.0 V Operation) (Worst-Case Commercial Conditions,
VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
A42MX09 Timing Characteristics (Nominal 3.3 V Operation) (Worst-Case Commercial Conditions,
VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
A42MX16 Timing Characteristics (Nominal 5.0 V Operation) (Worst-Case Commercial Conditions,
VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
A42MX16 Timing Characteristics (Nominal 3.3 V Operation) (Worst-Case Commercial Conditions,
VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
A42MX24 Timing Characteristics (Nominal 5.0 V Operation) (Worst-Case Commercial Conditions,
VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
A42MX24 Timing Characteristics (Nominal 3.3 V Operation) (Worst-Case Commercial Conditions,
VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
A42MX36 Timing Characteristics (Nominal 5.0 V Operation)(Worst-Case Commercial Conditions,
VCCA = 4.75 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
A42MX36 Timing Characteristics (Nominal 3.3 V Operation) (Worst-Case Commercial Conditions,
DS2316 Datasheet Revision 15.0
vii
Table 46
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
VCCA = 3.0 V, TJ = 70°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Configuration of Unused I/Os . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
PL44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PL68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
PL84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
PQ 100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
PQ144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
PQ160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
PQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
PQ240 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
VQ80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
TQ176 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
CQ208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
CQ256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
BG272 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
PG132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
CQ172 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
DS2316 Datasheet Revision 15.0
viii
Revision History
1
Revision History
The revision history describes the changes that were implemented in the document. The changes are
listed by revision, starting with the most current publication.
1.1
Revision 15.0
The following is a summary of the changes in revision 15.0 of this document.
•
•
•
1.2
Table 15, page 21 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
Table 22, page 25 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
Table 23, page 25 is edited to add the footnote, VIH(Min) is 2.4V for A42MX36 family. This applies
only to VCCI of 5V and is not applicable to VCCI of 3.3V
Revision 14.0
The following is a summary of the changes in revision 14.0 of this document.
•
•
•
•
1.3
Added CQFP package information for A42MX16 device in Product Profile, page 1 and Ceramic
Device Resources, page 4 (SAR 79522).
Added Military (M) and MIL-STD-883 Class B (B) grades for CPGA 132 Package and added
Commercial (C), Military (M), and MIL-STD-883 Class B (B) grades for CQFP 172 Package in
Temperature Grade Offerings, page 5 (SAR 79519)
Changed Silicon Sculptor II to Silicon Sculptor in Programming, page 12 (SAR 38754)
Added Figure 53, page 158 CQ172 package (SAR 79522).
Revision 13.0
The following is a summary of the changes in revision 13.0 of this document.
•
•
1.4
Added Figure 42, page 97 PQ144 Package for A42MX09 device (SAR 69776)
Added Figure 52, page 153 PQ132 Package for A42MX09 device (SAR 69776)
Revision 12.0
The following is a summary of the changes in revision 12.0 of this document.
•
•
1.5
Added information on power-up behavior for A42MX24 and A42MX36 devices to the Power Supply,
page 13 (SAR 42096
Corrected the inadvertent mistake in the naming of the PL68 pin assignment table (SARs 48999,
49793)
Revision 11.0
The following is a summary of the changes in revision 11.0 of this document.
•
•
1.6
The FuseLock logo and accompanying text was removed from the User Security, page 12. This
marking is no longer used on Microsemi devices (PCN 0915)
The Development Tool Support, page 19 was updated (SAR 38512)
Revision 10.0
The following is a summary of the changes in revision 10.0 of this document.
•
•
Ordering Information, page 3 was updated to include lead-free package ordering codes (SAR
21968)
The User Security, page 12 was revised to clarify that although no existing security measures can
give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry
(SAR 34673)
DS2316 Datasheet Revision 15.0
1
Revision History
•
•
1.7
The Transient Current, page 13 is new (SAR 36930).
Package names were revised according to standards established in Package Mechanical Drawings
(SAR 34774)
Revision 9.0
The following is a summary of the changes in revision 9.0 of this document
•
In Table 20, page 23, the limits in VI were changed from -0.5 to VCCI + 0.5 to -0.5 to VCCA + 0.5
In Table 22, page 25, VOH was changed from 3.7 to 2.4 for the min in industrial and military. VIH had VCCI
and that was changed to VCCA
1.8
Revision 6.0
The following is a summary of the changes in revision 6.0 of this document.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The Ease of Integration, page 1 was updated
The Temperature Grade Offerings, page 5 is new
The Speed Grade Offerings, page 5 is new
The General Description, page 6 was updated
The MultiPlex I/O Modules, page 11 was updated
The User Security, page 12 was updated
Table 6, page 13 was updated
The Power Dissipation, page 14 was updated.
The Static Power Component, page 14 was updated
The Equivalent Capacitance, page 15 was updated
Figure 13, page 17 was updated
Table 10, page 18 was updated.
Figure 14, page 18 was updated.
Table 11, page 19 was updated.
DS2316 Datasheet Revision 15.0
2
40MX and 42MX FPGA Families
2
40MX and 42MX FPGA Families
2.1
Features
The following sections list out various features of the 40MX and 42MX FPGA family devices.
2.1.1
High Capacity
•
•
•
•
•
2.1.2
High Performance
•
•
•
•
•
2.1.3
Commercial, Industrial, Automotive, and Military Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883 Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
•
•
•
•
•
•
2.2
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
HiRel Features
•
•
•
•
2.1.4
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
Mixed-Voltage Operation (5.0 V or 3.3 V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
The following table gives the features of the products.
Table 1 •
Product profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Capacity
System Gates
SRAM Bits
3,000
–
6,000
–
14,000
–
24,000
–
36,000
–
54,000
2,560
Logic Modules
Sequential
Combinatorial
Decode
–
295
–
–
547
–
348
336
–
624
608
–
954
912
24
1,230
1,184
24
Clock-to-Out
9.5 ns
9.5 ns
5.6 ns
6.1 ns
6.1 ns
6.3 ns
SRAM Modules
(64x4 or 32x8)
–
–
–
–
–
10
Dedicated Flip-Flops
–
–
348
624
954
1,230
DS2316 Datasheet Revision 15.0
1
40MX and 42MX FPGA Families
Table 1 •
Product profile
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
Maximum Flip-Flops
147
273
516
928
1,410
1,822
Clocks
1
1
2
2
2
6
User I/O (maximum)
57
69
104
140
176
202
PCI
–
–
–
–
Yes
Yes
Boundary Scan Test
(BST)
–
–
–
–
Yes
Yes
44, 68
100
80
–
–
–
–
44, 68, 84
100
80
–
–
–
–
84
100, 144, 160
100
176
–
–
132
84
100, 160, 208
100
176
172
–
–
84
160, 208
–
176
–
–
–
–
208, 240
–
–
208, 256
272
–
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
CPGA
DS2316 Datasheet Revision 15.0
2
40MX and 42MX FPGA Families
2.3
Ordering Information
The following figure shows ordering information.All the following tables show plastic and ceramic device
resources, temperature and speed grade offerings.
Figure 1 •
Ordering Information
A42MX16 _
1
PQ
100
G
ES
Application (Temperature Range)
Blank = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
A = Automotive (–40 to +125°C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
BG = Plastic Ball Grid Array
CQ =Ceramic Quad Flat Pack
PG =Ceramic Pin Grid Array
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A40MX02 = 3,000 System Gates
A40MX04 = 6,000 System Gates
A42MX09 = 14,000 System Gates
A42MX16 = 24,000 System Gates
A42MX24 = 36,000 System Gates
A42MX36 = 54,000 System Gates
DS2316 Datasheet Revision 15.0
3
40MX and 42MX FPGA Families
2.4
Plastic Device Resources
Table 2 •
Plastic Device Resources
User I/Os
Device
PQFP
PLCC PLCC PLCC PQFP 14444-Pin 68-Pin 84-Pin 100-Pin Pin
PQFP
PQFP 208160-Pin Pin
VQFP
PQFP VQFP 100240-Pin 80-Pin Pin
TQFP
176Pin
PBGA
272Pin
A40MX02 34
57
–
57
–
–
–
–
57
–
–
–
A40MX04 34
57
69
69
–
–
–
–
69
–
–
–
A42MX09 –
–
72
83
95
101
–
–
–
83
104
–
A42MX16 –
–
72
83
–
125
140
–
–
83
140
–
A42MX24 –
–
72
–
–
125
176
–
–
–
150
–
A42MX36 –
–
–
–
–
–
176
202
–
–
–
202
Note: Package Definitions: PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack,
TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array
2.5
Ceramic Device Resources
Table 3 •
Ceramic Device Resources
User I/Os
Device
CPGA 132-Pin
A42MX09
95
A42MX16
CQFP 172-Pin
CQFP 208-Pin
CQFP 256-Pin
176
202
131
A42MX36
Note: Package Definitions: CQFP = Ceramic Quad Flat Pack
DS2316 Datasheet Revision 15.0
4
40MX and 42MX FPGA Families
2.6
Temperature Grade Offerings
Table 4 •
Temperature Grade Offerings
Package
A40MX02
A40MX04
PLCC 44
C, I, M
C, I, M
PLCC 68
C, I, A, M
C, I, M
PLCC 84
PQFP 100
C, I, A, M
A42MX09
A42MX16
A42MX24
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, M
PQFP 144
C
PQFP 160
C, I, A, M
PQFP 208
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
A42MX36
C, I, A, M
PQFP 240
VQFP 80
C, I, A, M
C, I, A, M
C, I, A, M
VQFP 100
C, I, A, M
C, I, A, M
TQFP 176
C, I, A, M
C, I, A, M
C, I, A, M
PBGA 272
C, I, M
CQFP 172
C, M, B
CQFP 208
C, M, B
CQFP 256
C, M, B
CPGA 132
C, M, B
Note: C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
2.7
Speed Grade Offerings
Table 5 •
Speed Grade Offerings
–F
Std
–1
–2
–3
P
P
P
P
P
I
P
P
P
P
A
P
M
P
P
B
P
P
C
Note: See the 40MX and 42MX Automotive Family FPGAs datasheet for details on automotive-grade MX
offerings.
Contact your local Microsemi Sales representative for device availability.
DS2316 Datasheet Revision 15.0
5
40MX and 42MX FPGAs
3
40MX and 42MX FPGAs
3.1
General Description
Microsemi's 40MX and 42MX families offer a cost-effective design solution at 5V. The MX devices are
single-chip solutions and provide high performance while shortening the system design and development
cycle. MX devices can integrate and consolidate logic implemented in multiple PALs, CPLDs, and
FPGAs. Example applications include high-speed controllers and address decoding, peripheral bus
interfaces, DSP, and co-processor functions.
The MX device architecture is based on Microsemi’s patented antifuse technology implemented in a
0.45µm triple-metal CMOS process. With capacities ranging from 3,000 to 54,000 system gates,
the MX devices provide performance up to 250 MHz, are live on power-up and have one-fifth the standby
power consumption of comparable FPGAs. MX FPGAs provide up to 202 user I/Os and are available in a
wide variety of packages and speed grades.
A42MX24 and A42MX36 devices also feature multiPlex I/Os, which support mixed-voltage systems,
enable programmable PCI, deliver high-performance operation at both 5.0V and 3.3V, and provide a
low-power mode. The devices are fully compliant with the PCI local bus specification
(version 2.1). They deliver 200 MHz on-chip operation and 6.1 ns clock-to-output performance.
The 42MX24 and 42MX36 devices include system-level features such as
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing and fast wide-decode modules. In addition, the
A42MX36 device offers dual-port SRAM for implementing fast FIFOs, LIFOs, and temporary data
storage. The storage elements can efficiently address applications requiring wide data path manipulation
and can perform transformation functions such as those required for telecommunications, networking,
and DSP.
All MX devices are fully tested over automotive and military temperature ranges. In addition, the largest
member of the family, the A42MX36, is available in both CQ208 and CQ256 ceramic packages screened
to MIL-STD-883 levels. For easy prototyping and conversion from plastic to ceramic, the CQ208 and
PQ208 devices are pin-compatible.
3.2
MX Architectural Overview
The MX devices are composed of fine-grained building blocks that enable fast, efficient logic designs. All
devices within these families are composed of logic modules, I/O modules, routing resources and clock
networks, which are the building blocks for fast logic designs. In addition, the A42MX36 device contains
embedded dual-port SRAM modules, which are optimized for high-speed data path functions such as
FIFOs, LIFOs and scratch pad memory. A42MX24 and A42MX36 also contain wide-decode modules.
3.2.1
Logic Modules
The 40MX logic module is an eight-input, one-output logic circuit designed to implement a wide range of
logic functions with efficient use of interconnect routing resources.(see the following figure).
The logic module can implement the four basic logic functions (NAND, AND, OR and NOR) in gates of
two, three, or four inputs. The logic module can also implement a variety of D-latches, exclusivity
functions, AND-ORs and OR-ANDs. No dedicated hard-wired latches or flip-flops are required in the
array; latches and flip-flops can be constructed from logic modules whenever required in the application.
DS2316 Datasheet Revision 15.0
6
40MX and 42MX FPGAs
Figure 2 •
42MX C-Module Implementation
The 42MX devices contain three types of logic modules: combinatorial (C-modules), sequential (Smodules) and decode (D-modules). The following figure illustrates the combinatorial logic module. The
S-module, shown in Figure 4, page 8, implements the same combinatorial logic function as the C-module
while adding a sequential element. The sequential element can be configured as either a D-flip-flop or a
transparent latch. The S-module register can be bypassed so that it implements purely combinatorial
logic.
Figure 3 •
42MX C-Module Implementation
A0
B0
S0
D00
D01
Y
D10
D11
S1
A1
B1
DS2316 Datasheet Revision 15.0
7
40MX and 42MX FPGAs
Figure 4 •
42MX S-Module Implementation
D00
D01
D00
D01
Y
D10
D
S0
D11
S1
Q
OUT
CLR
Up to 7-Input Function Plus D-Type Flip-Flop with Clear
D10
D11
S1
Y
S0
D
Q
OUT
GATE
Up to 7-Input Function Plus Latch
D00
D0
Y
D1
S
Q
D
D01
D10
OUT
D11
S1
GATE
CLR
Up to 4-Input Function Plus Latch with Clear
Y
OUT
S0
Up to 8-Input Function (Same as C-Module)
A42MX24 and A42MX36 devices contain D-modules, which are arranged around the periphery of the
device. D-modules contain wide-decode circuitry, providing a fast, wide-input AND function similar to that
found in CPLD architectures (Figure 5, page 9). The D-module allows A42MX24 and A42MX36 devices
to perform wide-decode functions at speeds comparable to CPLDs and PALs. The output of the
D-module has a programmable inverter for active HIGH or LOW assertion. The D-module output is
hardwired to an output pin, and can also be fed back into the array to be incorporated into other logic.
3.2.2
Dual-Port SRAM Modules
The A42MX36 device contains dual-port SRAM modules that have been optimized for synchronous or
asynchronous applications. The SRAM modules are arranged in 256-bit blocks that can be configured as
32x8 or 64x4. SRAM modules can be cascaded together to form memory spaces of user-definable width
and depth. A block diagram of the A42MX36 dual-port SRAM block is shown in Figure 6, page 9.
The A42MX36 SRAM modules are true dual-port structures containing independent read and write ports.
Each SRAM module contains six bits of read and write addressing (RDAD[5:0] and WRAD[5:0],
respectively) for 64x4-bit blocks. When configured in byte mode, the highest order address bits (RDAD5
and WRAD5) are not used. The read and write ports of the SRAM block contain independent clocks
(RCLK and WCLK) with programmable polarities offering active HIGH or LOW implementation. The
SRAM block contains eight data inputs (WD[7:0]), and eight outputs (RD[7:0]), which are connected to
segmented vertical routing tracks.
The A42MX36 dual-port SRAM blocks provide an optimal solution for high-speed buffered applications
requiring FIFO and LIFO queues. The ACTgen Macro Builder within Microsemi's designer software
provides capability to quickly design memory functions with the SRAM blocks. Unused SRAM blocks can
be used to implement registers for other user logic within the design.
DS2316 Datasheet Revision 15.0
8
40MX and 42MX FPGAs
Figure 5 •
A42MX24 and A42MX36 D-Module Implementation
7 Inputs
Hard-Wire to I/O
Programmable
Inverter
Feedback to Array
Figure 6 •
A42MX36 Dual-Port SRAM Block
Latches
WD[7:0]
[7:0]
WRAD[5:0]
MODE
BLKEN
WEN
Write
Port
Logic
[5:0]
[5:0]
Read
Port
Logic
Latches
Read
Logic
Latches
RD[7:0]
Write
Logic
RDAD[5:0]
REN
RCLK
Routing Tracks
WCLK
3.2.3
SRAM Module
32 x 8 or 64 x 4
(256 Bits)
Routing Structure
The MX architecture uses vertical and horizontal routing tracks to interconnect the various logic and I/O
modules. These routing tracks are metal interconnects that may be continuous or split into segments.
Varying segment lengths allow the interconnect of over 90% of design tracks to occur with only two
antifuse connections. Segments can be joined together at the ends using antifuses to increase their
lengths up to the full length of the track. All interconnects can be accomplished with a maximum of four
antifuses.
3.2.3.1
Horizontal Routing
Horizontal routing tracks span the whole row length or are divided into multiple segments and are located
in between the rows of modules. Any segment that spans more than one-third of the row length is
considered a long horizontal segment. A typical channel is shown in Figure 7, page 10. Within horizontal
routing, dedicated routing tracks are used for global clock networks and for power and ground tie-off
tracks. Non-dedicated tracks are used for signal nets.
3.2.3.2
Vertical Routing
Another set of routing tracks run vertically through the module. There are three types of vertical tracks:
input, output, and long. Long tracks span the column length of the module, and can be divided into
multiple segments. Each segment in an input track is dedicated to the input of a particular module; each
segment in an output track is dedicated to the output of a particular module. Long segments are
uncommitted and can be assigned during routing.
Each output segment spans four channels (two above and two below), except near the top and bottom of
the array, where edge effects occur. Long vertical tracks contain either one or two segments. An example
of vertical routing tracks and segments is shown in Figure 7, page 10.
DS2316 Datasheet Revision 15.0
9
40MX and 42MX FPGAs
3.2.3.3
Antifuse Structures
An antifuse is a “normally open” structure. The use of antifuses to implement a programmable logic
device results in highly testable structures as well as efficient programming algorithms. There are no
pre-existing connections; temporary connections can be made using pass transistors. These temporary
connections can isolate individual antifuses to be programmed and individual circuit structures to be
tested, which can be done before and after programming. For instance, all metal tracks can be tested for
continuity and shorts between adjacent tracks, and the functionality of all logic modules can be verified.
Figure 7 •
MX Routing Structure
Segmented
Horizontal
Routing
Logic
Modules
Antifuses
Vertical Routing Tracks
3.2.4
Clock Networks
The 40MX devices have one global clock distribution network (CLK). A signal can be put on the CLK
network by being routed through the CLKBUF buffer.
In 42MX devices, there are two low-skew, high-fanout clock distribution networks, referred to as CLKA
and CLKB. Each network has a clock module (CLKMOD) that can select the source of the clock signal
from any of the following (Figure 8, page 11):
•
•
•
•
Externally from the CLKA pad, using CLKBUF buffer
Externally from the CLKB pad, using CLKBUF buffer
Internally from the CLKINTA input, using CLKINT buffer
Internally from the CLKINTB input, using CLKINT buffer
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel.
Clock input pads in both 40MX and 42MX devices can also be used as normal I/Os, bypassing the clock
networks.
The A42MX36 device has four additional register control resources, called quadrant clock networks
(Figure 9, page 11). Each quadrant clock provides a local, high-fanout resource to the contiguous logic
modules within its quadrant of the device. Quadrant clock signals can originate from specific I/O pins or
from the internal array and can be used as a secondary register clock, register clear, or output enable.
DS2316 Datasheet Revision 15.0
10
40MX and 42MX FPGAs
Figure 8 •
Clock Networks of 42MX Devices
CLKB
CLKINB
CLKA
From
Pads
CLKINA
CLKMOD
S0
S1
Internal
Signal
CLKO(17)
Clock
Drivers
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
Clock Tracks
Figure 9 •
Quadrant Clock Network of A42MX36 Devices
QCLKA
QCLKB
QCLKC
Quad
Clock
Modul
QCLK1
QCLK3
Quad
Clock
Modul
QCLKD
*QCLK3IN
*QCLK1IN
S1 S0
S0 S1
Quad
Clock
Modul
QCLK2
QCLK4
Quad
Clock
Modul
*QCLK4IN
*QCLK2IN
S1 S0
S0 S1
Note: *QCLK1IN, QCLK2IN, QCLK3IN, and QCLK4IN are internally-generated signals.
3.2.5
MultiPlex I/O Modules
42MX devices feature Multiplex I/Os and support 5.0 V, 3.3 V, and mixed 3.3 V/5.0 V operations.
The MultiPlex I/O modules provide the interface between the device pins and the logic array. Figure 10,
page 12 is a block diagram of the 42MX I/O module. A variety of user functions, determined by a library
macro selection, can be implemented in the module. (See the Antifuse Macro Library Guide for more
information.) All 42MX I/O modules contain tristate buffers, with input and output latches that can be
configured for input, output, or bidirectional operation.
All 42MX devices contain flexible I/O structures, where each output pin has a dedicated output-enable
control (Figure 10, page 12). The I/O module can be used to latch input or output data, or both, providing
fast set-up time. In addition, the Designer software tools can build a D-type flip-flop using a C-module
combined with an I/O module to register input and output signals. See the Antifuse Macro Library Guide
for more details.
A42MX24 and A42MX36 devices also offer selectable PCI output drives, enabling 100% compliance with
version 2.1 of the PCI specification. For low-power systems, all inputs and outputs are turned off to
reduce current consumption to below 500 A.
To achieve 5.0 V or 3.3 V PCI-compliant output drives on A42MX24 and A42MX36 devices, a chip-wide
PCI fuse is programmed via the Device Selection Wizard in the Designer software (Figure 11, page 12).
When the PCI fuse is not programmed, the output drive is standard.
DS2316 Datasheet Revision 15.0
11
40MX and 42MX FPGAs
Designer software development tools provide a design library of I/O macro functions that can implement
all I/O configurations supported by the MX FPGAs.
Figure 10 • 42MX I/O Module
EN
Q
D
PAD
From Array
G/CLK*
To Array
Q
D
G/CLK*
Note: *Can be configured as a Latch or D Flip-Flop (Using C-Module)
Figure 11 • PCI Output Structure of A42MX24 and A42MX36 Devices
STD
Signal
Output
PCI
Drive
PCI Enable
Fuse
3.3
Other Architectural Features
The following sections cover other architectural features of 40MX and 42MX FPGAs.
3.3.1
Performance
MX devices can operate with internal clock frequencies of 250 MHz, enabling fast execution of complex
logic functions. MX devices are live on power-up and do not require auxiliary configuration devices and
thus are an optimal platform to integrate the functionality contained in multiple programmable logic
devices. In addition, designs that previously would have required a gate array to meet performance can
be integrated into an MX device with improvements in cost and time-to-market. Using
timing-driven place-and-route (TDPR) tools, designers can achieve highly deterministic device
performance.
3.3.2
User Security
Microsemi FuseLock provides robust security against design theft. Special security fuses are hidden in
the fabric of the device and protect against unauthorized users attempting to access the programming
and/or probe interfaces. It is virtually impossible to identify or bypass these fuses without damaging the
device, making Microsemi antifuse FPGAs protected with the highest level of security available from both
invasive and noninvasive attacks.
Special security fuses in 40MX devices include the Probe Fuse and Program Fuse. The former disables
the probing circuitry while the latter prohibits further programming of all fuses, including the Probe Fuse.
In 42MX devices, there is the Security Fuse which, when programmed, both disables the probing circuitry
and prohibits further programming of the device.
3.3.3
Programming
Device programming is supported through the Silicon Sculptor series of programmers. Silicon Sculptor is
a compact, robust, single-site and multi-site device programmer for the PC. With standalone software,
Silicon Sculptor is designed to allow concurrent programming of multiple units from the same PC.
DS2316 Datasheet Revision 15.0
12
40MX and 42MX FPGAs
Silicon Sculptor programs devices independently to achieve the fastest programming times possible.
After being programmed, each fuse is verified to insure that it has been programmed correctly.
Furthermore, at the end of programming, there are integrity tests that are run to ensure no extra fuses
have been programmed. Not only does it test fuses (both programmed and non-programmed), Silicon
Sculptor also allows self-test to verify its own hardware extensively.
The procedure for programming an MX device using Silicon Sculptor is as follows:
1.
2.
3.
Load the *.AFM file
Select the device to be programmed
Begin programming
When the design is ready to go to production, Microsemi offers device volume-programming services
either through distribution partners or via In-House Programming from the factory.
For more details on programming MX devices, see the AC225: Programming Antifuse Devices
application note and the Silicon Sculptor 3 Programmers User Guide.
3.3.4
Power Supply
MX devices are designed to operate in both 5.0V and 3.3V environments. In particular, 42MX devices
can operate in mixed 5.0 V/3.3 V systems. The following table describes the voltage support of MX
devices.
Table 6 •
Voltage Support of MX Devices
Device
VCC
VCCA
VCCI
Maximum Input Tolerance
Nominal Output Voltage
40MX
5.0 V
–
–
5.5 V
5.0 V
3.3 V
–
–
3.6 V
3.3 V
–
5.0 V
5.0 V
5.5 V
5.0 V
–
3.3 V
3.3 V
3.6 V
3.3 V
–
5.0 V
3.3 V
5.5 V
3.3 V
42MX
For A42MX24 and A42MX36 devices the VCCA supply has to be monotonic during power up in order for
the POR to issue reset to the JTAG state machine correctly. For more information, see the AC291: 42MX
Family Devices Power-Up Behavior.
3.3.5
Power-Up/Down in Mixed-Voltage Mode
When powering up 42MX in mixed voltage mode (VCCA = 5.0 V and VCCI = 3.3 V), VCCA must be
greater than or equal to VCCI throughout the power-up sequence. If VCCI exceeds VCCA during
power-up, one of two things will happen:
•
•
The input protection diode on the I/Os will be forward biased
The I/Os will be at logical High
In either case, ICC rises to high levels. For power-down, any sequence with VCCA and VCCI can be
implemented.
3.3.6
Transient Current
Due to the simultaneous random logic switching activity during power-up, a transient current may appear
on the core supply (VCC). Customers must use a regulator for the VCC supply that can source a
minimum of 100 mA for transient current during power-up. Failure to provide enough power can prevent
the system from powering up properly and result in functional failure. However, there are no reliability
concerns, since transient current is distributed across the die instead of confined to a localized spot.
Since the transient current is not due to I/O switching, its value and duration are independent of the
VCCI.
DS2316 Datasheet Revision 15.0
13
40MX and 42MX FPGAs
3.3.7
Low Power Mode
42MX devices have been designed with a Low Power Mode. This feature, activated with setting the
special LP pin to HIGH for a period longer than 800 ns, is particularly useful for battery-operated systems
where battery life is a primary concern. In this mode, the core of the device is turned off and the device
consumes minimal power with low standby current. In addition, all input buffers are turned off, and all
outputs and bidirectional buffers are tristated. Since the core of the device is turned off, the states of the
registers are lost. The device must be re-initialized when exiting Low Power Mode. I/Os can be driven
during LP mode, and clock pins should be driven HIGH or LOW and should not float to avoid drawing
current. To exit LP mode, the LP pin must be pulled LOW for over 200 µs to allow for charge pumps to
power up, and device initialization will begin.
3.4
Power Dissipation
The general power consumption of MX devices is made up of static and dynamic power and can be
expressed with the following equation.
3.4.1
General Power Equation
P = ICCs tan dby + ICCactive VCCI + IOL VOL N + IOH VCCI – VOH M
EQ 1
where:
•
•
•
•
•
•
ICCstandby is the current flowing when no inputs or outputs are changing.
ICCactive is the current flowing due to CMOS switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to VOL.
M equals the number of outputs driving TTL loads to VOH.
Accurate values for N and M are difficult to determine because they depend on the family type, on design
details, and on the system I/O. The power can be divided into two components: static and active.
3.4.2
Static Power Component
The static power due to standby current is typically a small component of the overall power consumption.
Standby power is calculated for commercial, worst-case conditions. The static power dissipation by TTL
loads depends on the number of outputs driving, and on the DC load current. For instance, a 32-bit bus
sinking 4mA at 0.33V will generate 42mW with all outputs driving LOW, and 140mW with all outputs
driving HIGH. The actual dissipation will average somewhere in between, as I/Os switch states with time.
3.4.3
Active Power Component
Power dissipation in CMOS devices is usually dominated by the dynamic power dissipation. Dynamic
power consumption is frequency-dependent and is a function of the logic and the external I/O. Active
power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external capacitances due to PC board traces and
load device inputs. An additional component of the active power dissipation is the totem pole current in
the CMOS transistor pairs. The net effect can be associated with an equivalent capacitance that can be
combined with frequency and voltage to represent active power dissipation.
The power dissipated by a CMOS circuit can be expressed by the equation:
Power W = C EQ VCCA2 F 1
EQ 2
where:
•
CEQ = Equivalent capacitance expressed in picofarads (pF)
DS2316 Datasheet Revision 15.0
14
40MX and 42MX FPGAs
•
•
3.4.4
VCCA = Power supply in volts (V)
F = Switching frequency in megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for
each circuit component of interest. Measurements have been made over a range of frequencies at a
fixed value of VCC. Equivalent capacitance is frequency-independent, so the results can be used over a
wide range of operating conditions. Equivalent capacitance values are shown below.
3.4.5
CEQ Values for Microsemi MX FPGAs
Modules (CEQM)3.5
Input Buffers (CEQI)6.9
Output Buffers (CEQO)18.2
Routed Array Clock Buffer Loads (CEQCR)1.4
To calculate the active power dissipated from the complete design, the switching frequency of each part
of the logic must be known. The equation below shows a piece-wise linear summation over all
components.
Power = VCCA
2
m C EQM f m
modules
+ n C EQI f n inputs + p C EQO + C L f p outputs +
0.5 q 1 C EQCR f q1 routed
Clk1
+ r 1 f q1 routed
Clk1
0.5 q 2 C EQCR f q2 routed
Clk2
+ r 2 f q2 routed
Clk2
+
2
EQ 3
where:
m = Number of logic modules switching at frequency fm
n = Number of input buffers switching at frequency fn
p = Number of output buffers switching at frequency fp
q1 = Number of clock loads on the first routed array clock
q2 = Number of clock loads on the second routed array clock
r1 = Fixed capacitance due to first routed array clock
r2 = Fixed capacitance due to second routed array clock
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in pF
CL = Output load capacitance in pF
fm = Average logic module switching rate in MHz
fn = Average input buffer switching rate in MHz
fp = Average output buffer switching rate in MHz
fq1 = Average first routed array clock rate in MHz
DS2316 Datasheet Revision 15.0
15
40MX and 42MX FPGAs
fq2 = Average second routed array clock rate in MHz)
Table 7 •
3.4.6
Fixed Capacitance Values for MX FPGAs (pF)
Device Type
r1 routed_Clk1
r2 routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
118
A42MX16
165
165
A42MX24
185
185
A42MX36
220
220
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-in access to every node in a design, via the use of
Silicon Explorer II. Silicon Explorer II is an integrated hardware and software solution that, in conjunction
with the Designer software, allow users to examine any of the internal nets of the device while it is
operating in a prototyping or a production system. The user can probe into an MX device without
changing the placement and routing of the design and without using any additional resources. Silicon
Explorer II's noninvasive method does not alter timing or loading effects, thus shortening the debug cycle
and providing a true representation of the device under actual functional situations.
Silicon Explorer II samples data at 100 MHz (asynchronous) or 66 MHz (synchronous). Silicon Explorer II
attaches to a PC's standard COM port, turning the PC into a fully functional 18-channel logic analyzer.
Silicon Explorer II allows designers to complete the design verification process at their desks and
reduces verification time from several hours per cycle to a few seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI and SDO pins in MX devices to select the
desired nets for debugging. The user simply assigns the selected internal nets in the Silicon Explorer II
software to the PRA/PRB output pins for observation. Probing functionality is activated when the MODE
pin is held HIGH.
Figure 12, page 16 illustrates the interconnection between Silicon Explorer II and 40MX devices, while
Figure 13, page 17 illustrates the interconnection between Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must not be programmed. (See User Security,
page 12 for the security fuses of 40MX and 42MX devices). Table 8, page 17 summarizes the possible
device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the “Reserve Probe Pin” is checked in the Designer
software, PRA and PRB pins are reserved as dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and “Reserve Probe Pin” is checked, the layout tool
will override the option and place user I/Os on PRA and PRB pins.
Figure 12 • Silicon Explorer II Setup with 40MX
16 Logic Analyzer Channels
Serial Connection
to Windows PC
40MX
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
PRA
DS2316 Datasheet Revision 15.0
16
40MX and 42MX FPGAs
Figure 13 • Silicon Explorer II Setup with 42MX
16 Logic Analyzer Channels
Serial Connection
to Windows PC
42MX
MODE
SDI
DCLK
Silicon
Explorer II
SDO
PRB
Table 8 •
PRA
Device Configuration Options for Probe Capability
Security Fuse(s) Programmed
Mode
PRA, PRB1
SDI, SDO, DCLK1
No
LOW
User I/Os2
User I/Os2
No
HIGH
Probe Circuit Outputs
Probe Circuit Inputs
Yes
–
Probe Circuit Secured
Probe Circuit Secured
1. Avoid using SDI, SDO, DCLK, PRA and PRB pins as input or bidirectional ports. Since these pins are active during
probing, input signals will not pass through these pins and may cause contention.
2. If no user signal is assigned to these pins, they will behave as unused I/Os in this mode. See the Pin Descriptions, page 83
for information on unused I/O pins
3.4.7
Design Consideration
It is recommended to use a series 70 termination resistor on every probe connector (SDI, SDO, MODE,
DCLK, PRA and PRB). The 70 series termination is used to prevent data transmission corruption
during probing and reading back the checksum.
3.4.8
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
42MX24 and 42MX36 devices are compatible with IEEE Standard 1149.1 (informally known as Joint
Testing Action Group Standard or JTAG), which defines a set of hardware architecture and mechanisms
for cost-effective board-level testing. The basic MX boundary-scan logic circuit is composed of the TAP
(test access port), TAP controller, test data registers and instruction register (Figure 14, page 18). This
circuit supports all mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/PRELOAD and BYPASS)
and some optional instructions. Table 9, page 18 describes the ports that control JTAG testing, while
Table 10, page 18 describes the test instructions supported by these MX devices.
Each test section is accessed through the TAP, which has four associated pins: TCK (test clock input),
TDI and TDO (test data input and output), and TMS (test mode selector).
The TAP controller is a four-bit state machine. The '1's and '0's represent the values that must be present
at TMS at a rising edge of TCK for the given state transition to occur. IR and DR indicate that the
instruction register or the data register is operating in that state.
The TAP controller receives two control inputs (TMS and TCK) and generates control and clock signals
for the rest of the test logic architecture. On power-up, the TAP controller enters the Test-Logic-Reset
state. To guarantee a reset of the controller from any of the possible states, TMS must remain high for
five TCK cycles.
42MX24 and 42MX36 devices support three types of test data registers: bypass, device identification,
and boundary scan. The bypass register is selected when no other register needs to be accessed in a
device. This speeds up test data transfer to other devices in a test data path. The 32-bit device
identification register is a shift register with four fields (lowest significant byte (LSB), ID number, part
number and version). The boundary-scan register observes and controls the state of each I/O pin.
DS2316 Datasheet Revision 15.0
17
40MX and 42MX FPGAs
Each I/O cell has three boundary-scan register cells, each with a serial-in, serial-out, parallel-in, and
parallel-out pin. The serial pins are used to serially connect all the boundary-scan register cells in a
device into a boundary-scan register chain, which starts at the TDI pin and ends at the TDO pin. The
parallel ports are connected to the internal core logic tile and the input, output and control ports of an I/O
buffer to capture and load data into the register to control or observe the logic state of each I/O.
Figure 14 • 42MX IEEE 1149.1 Boundary Scan Circuitry
Boundary Scan Register
Output
MUX
TDO
Bypass
Register
Control Logic
JTAG
TMS
TAP Controller
TCK
Instruction
Decode
JTAG
Instruction
Register
TDI
Table 9 •
Test Access Port Descriptions
Port
Description
TMS
(Test Mode Select)
Serial input for the test logic control bits. Data is captured on the rising edge of the test logic
clock (TCK).
TCK
(Test Clock Input)
Dedicated test logic clock used serially to shift test instruction, test data, and control inputs on
the rising edge of the clock, and serially to shift the output data on the falling edge of the clock.
The maximum clock frequency for TCK is 20 MHz.
TDI
(Test Data Input)
Serial input for instruction and test data. Data is captured on the rising edge of the test logic
clock.
TDO
(Test Data Output)
Serial output for test instruction and data from the test logic. TDO is set to an Inactive Drive
state (high impedance) when data scanning is not in progress.
Table 10 •
Supported BST Public Instructions
Instruction
IR Code Instruction
(IR2.IR0) Type
Description
EXTEST
000
Mandatory
Allows the external circuitry and board-level interconnections to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
SAMPLE/PRELOAD 001
Mandatory
Allows a snapshot of the signals at the device pins to be captured and
examined during operation
HIGH Z
101
Optional
Tristates all I/Os to allow external signals to drive pins. See the IEEE
Standard 1149.1 specification.
CLAMP
110
Optional
Allows state of signals driven from component pins to be determined
from the Boundary-Scan Register. See the IEEE Standard 1149.1
specification for details.
BYPASS
111
Mandatory
Enables the bypass register between the TDI and TDO pins. The test
data passes through the selected device to adjacent devices in the
test chain.
DS2316 Datasheet Revision 15.0
18
40MX and 42MX FPGAs
3.4.9
JTAG Mode Activation
The JTAG test logic circuit is activated in the Designer software by selecting Tools > Device Selection.
This brings up the Device Selection dialog box as shown in the following figure. The JTAG test logic
circuit can be enabled by clicking the “Reserve JTAG Pins” check box. The following table explains the
pins' behavior in either mode.
Figure 15 • Device Selection Wizard
Table 11 •
Boundary Scan Pin Configuration and Functionality
Reserve JTAG
Checked
Unchecked
TCK
BST input; must be terminated to logical HIGH or LOW to avoid floating
User I/O
TDI, TMS
BST input; may float or be tied to HIGH
User I/O
TDO
BST output; may float or be connected to TDI of another device
User I/O
3.4.10
TRST Pin and TAP Controller Reset
An active reset (TRST) pin is not supported; however, MX devices contain power-on circuitry that resets
the boundary scan circuitry upon power-up. Also, the TMS pin is equipped with an internal pull-up
resistor. This allows the TAP controller to remain in or return to the Test-Logic-Reset state when there is
no input or when a logical 1 is on the TMS pin. To reset the controller, TMS must be HIGH for at least five
TCK cycles.
3.4.11
Boundary Scan Description Language (BSDL) File
Conforming to the IEEE Standard 1149.1 requires that the operation of the various JTAG components be
documented. The BSDL file provides the standard format to describe the JTAG components that can be
used by automatic test equipment software. The file includes the instructions that are supported,
instruction bit pattern, and the boundary-scan chain order. For an in-depth discussion on BSDL files, see
the BSDL Files Format Description application note.
BSDL files are grouped into two categories - generic and device-specific. The generic files assign all user
I/Os as inouts. Device-specific files assign user I/Os as inputs, outputs or inouts.
Generic files for MX devices are available on the Microsemi SoC Product Group's website:
http://www.microsemi.com/soc/techdocs/models/bsdl.html.
3.5
Development Tool Support
The MX family of FPGAs is fully supported by Libero® Integrated Design Environment (IDE). Libero IDE
is a design management environment, seamlessly integrating design tools while guiding the user through
the design flow, managing all design and log files, and passing necessary design data among tools.
Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the
entire design in a single environment. Libero IDE includes SynplifyPro from Synopsys, ModelSim® HDL
Simulator from Mentor Graphics® and Viewdraw.
Libero IDE includes place-and-route and provides a comprehensive suite of backend support tools for
FPGA development, including timing-driven place-and-route, and a world-class integrated static timing
analyzer and constraints editor.
DS2316 Datasheet Revision 15.0
19
40MX and 42MX FPGAs
Additionally, the back-annotation flow is compatible with all the major simulators and the simulation
results can be cross-probed with Silicon Explorer II, Microsemi’s integrated verification and logic analysis
tool. Another tool included in the Libero software is the SmartGen macro builder, which easily creates
popular and commonly used logic functions for implementation into your schematic or HDL design.
Microsemi’s Libero software is compatible with the most popular FPGA design entry and verification tools
from companies such as Mentor Graphics, Synopsys, and Cadence design systems.
See the Libero IDE web content at www.microsemi.com/soc/products/software/libero/default.aspx for
further information on licensing and current operating system support.
3.6
Related Documents
The following sections give the list of related documents which can be refered for this datasheet.
3.6.1
Application Notes
•
•
•
3.6.2
User Guides and Manuals
•
•
3.6.3
AC278: BSDL Files Format Description
AC225: Programming Antifuse Devices
AC168: Implementation of Security in Microsemi Antifuse FPGAs
Antifuse Macro Library Guide
Silicon Sculptor Programmers User Guide
Miscellaneous
Libero IDE Flow Diagram
3.7
5.0 V Operating Conditions
The following tables show 5.0 V operating conditions.
Table 12 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
VCC
DC Supply Voltage
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCC+0.5
V
VO
Output Voltage
–0.5 to VCC+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Table 13 •
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
DS2316 Datasheet Revision 15.0
20
40MX and 42MX FPGAs
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Table 14 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
–40 to +85
–55 to +125
°C
VCC (40MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCA (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI (42MX)
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
Note: * Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
3.7.1
5 V TTL Electrical Specifications
The following tables show 5 V TTL electrical specifications.
Table 15 •
5V TTL Electrical Specifications
Commercial
Commercial -F
Industrial
Military
Min.
Min.
Min. Max.
Min.
Symbol
Parameter
VOH1
IOH = –10 mA 2.4
Max.
Max.
2.4
3.7
IOL = 10 mA
0.5
VIH (40MX)
VIH
(42MX)2
3.7
V
0.5
V
IOL = 6 mA
VIL
0.4
–0.3
Units
V
IOH = –4 mA
VOL1
Max.
–0.3 0.8
0.8
V
0.8
2.0
VCC + 0.3 2.0
VCC + 0.3 2.0
VCC + 0.3 2.0
VCC + 0.3 V
2.0
VCCI +
0.3
VCCI +
0.3
VCCI +
0.3
VCCI + 0.3 V
2.0
–0.3
V
–0.3
2.0
0.8
0.4
2.0
IIL
VIN = 0.5 V
–10
–10
–10
–10
µA
IIH
VIN = 2.7 V
–10
–10
–10
–10
µA
Input Transition
Time, TR and TF
500
500
500
500
ns
CIO I/O
Capacitance
10
10
10
10
pF
Standby Current, A40MX02,
ICC3
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
Low power mode 42MX devices
Standby Current only
IIO, I/O source
sink current
1.
2.
Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Only one output tested at a time. VCC/VCCI = min
VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
DS2316 Datasheet Revision 15.0
21
40MX and 42MX FPGAs
3.
All outputs unloaded. All inputs = VCC/VCCI or GND
3.8
3.3 V Operating Conditions
The following table shows 3.3 V operating conditions.
Table 16 •
Absolute Maximum Ratings for 40MX Devices*
Symbol
Parameter
Limits
Units
VCC
DC Supply Voltage
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCC + 0.5
V
VO
Output Voltage
–0.5 to VCC + 0.5
V
tSTG
Storage Temperature
–65 to + 150
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Table 17 •
Absolute Maximum Ratings for 42MX Devices*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCI+0.5
V
VO
Output Voltage
–0.5 to VCCI+0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability. Devices should not be operated outside the recommended operating conditions.
Table 18 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
–40 to +85
–55 to +125
°C
VCC (40MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCA (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
VCCI (42MX)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
All the following tables show various specifications and operating conditions of 40MX and 42MX FPGAs.
DS2316 Datasheet Revision 15.0
22
40MX and 42MX FPGAs
3.8.1
3.3 V LVTTL Electrical Specifications
Table 19 •
3.3V LVTTL Electrical Specifications
Symbol
Parameter
Commercial
Commercial -F
Industrial
Military
Min.
Min.
Min.
Min.
1
IOH = –4 mA 2.15
1
IOL = 6 mA
VOH
VOL
Max.
Max.
2.15
0.4
2.4
0.4
2.4
0.48
–0.3
0.8
–0.3
Units
V
0.48
V
0.8
V
–0.3
0.8
VIH (40MX)
2.0
VCC + 0.3 2.0
VCC + 0.3 2.0
VCC + 0.3 2.0
VCC + 0.3 V
VIH (42MX)
2.0
VCCI + 0.3 2.0
VCCI + 0.3 2.0
VCCI + 0.3 2.0
VCCI + 0.3 V
IIL
–10
–10
–10
–10
µA
IIH
–10
–10
–10
–10
µA
Input Transition
Time, TR and TF
500
500
500
500
ns
CIO I/O
Capacitance
10
10
10
10
pF
A40MX02,
A40MX04
3
25
10
25
mA
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
15
25
25
25
mA
Low-Power
Mode Standby
Current
42MX
devices only
0.5
ICC - 5.0
ICC - 5.0
ICC - 5.0
mA
IIO, I/O source
sink current
Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
1.
2.
0.8
Max.
VIL
Standby
Current, ICC2
–0.3
Max.
Only one output tested at a time. VCC/VCCI = min.
All outputs unloaded. All inputs = VCC/VCCI or GND.
3.9
Mixed 5.0 V / 3.3 V Operating Conditions (for 42MX
Devices Only)
Table 20 •
Absolute Maximum Ratings*
Symbol
Parameter
Limits
Units
VCCI
DC Supply Voltage for I/Os
–0.5 to +7.0
V
VCCA
DC Supply Voltage for Array
–0.5 to +7.0
V
VI
Input Voltage
–0.5 to VCCA +0.5
V
VO
Output Voltage
–0.5 to VCCI + 0.5
V
tSTG
Storage Temperature
–65 to +150
°C
Note: *Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. Exposure to absolute maximum rated conditions for extended periods may affect device
DS2316 Datasheet Revision 15.0
23
40MX and 42MX FPGAs
reliability. Devices should not be operated outside the recommended operating conditions.
Table 21 •
Recommended Operating Conditions
Parameter
Commercial
Industrial
Military
Units
Temperature Range*
0 to +70
–40 to +85
–55 to +125
°C
VCCA
4.75 to 5.25
4.5 to 5.5
4.5 to 5.5
V
VCCI
3.14 to 3.47
3.0 to 3.6
3.0 to 3.6
V
Note: *Ambient temperature (TA) is used for commercial and industrial grades; case temperature (TC) is used
for military grades.
DS2316 Datasheet Revision 15.0
24
40MX and 42MX FPGAs
3.9.1
Mixed 5.0V/3.3V Electrical Specifications
Table 22 •
Mixed 5.0V/3.3V Electrical Specifications
Symbol
Parameter
1
VOH
Commercial
Commercial –F
Industrial
Military
Min. Max.
Min. Max.
Min. Max.
Min. Max.
IOH = –10 mA 2.4
2.4
V
IOH = –4 mA
1
VOL
2.4
IOL = 10 mA
Units
0.5
–0.3 0.8
VIH2
2.0
V
0.5
V
IOL = 6 mA
VIL
2.4
–0.3 0.8
0.4
0.4
V
–0.3 0.8
–0.3 0.8
V
VCCA + 0.3 2.0
VCCA + 0.3 2.0
VCCA + 0.3 2.0
VCCA + 0.3 V
IL
VIN = 0.5 V
–10
–10
–10
–10
µA
IH
VIN = 2.7 V
–10
–10
–10
–10
µA
Input Transition
Time, TR and TF
500
500
500
500
ns
C
10
10
10
10
pF
A42MX09
5
25
25
25
mA
A42MX16
6
25
25
25
mA
A42MX24,
A42MX36
20
25
25
25
mA
0.5
ICC – 5.0
ICC – 5.0
ICC – 5.0
mA
IO I/O
Capacitance
Standby Current,
ICC3
Low Power Mode
Standby Current
IIO I/O source sink
current
1.
2.
3.
Can be derived from the IBIS model (http://www.microsemi.com/soc/techdocs/models/ibis.html)
Only one output tested at a time. VCCI = min.
VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V
All outputs unloaded. All inputs = VCCI or GND
3.9.2
Output Drive Characteristics for 5.0 V PCI Signaling
MX PCI device I/O drivers were designed specifically for high-performance PCI systems. Figure 16,
page 28 shows the typical output drive characteristics of the MX devices. MX output drivers are
compliant with the PCI Local Bus Specification.
Table 23 •
DC Specification (5.0 V PCI Signaling)1
PCI
Symbol Parameter
Condition
Min.
MX
Max.
Min.
Max.
Units
V
VCCI
Supply Voltage for I/Os
4.75
5.25
4.75
5.252
VIH3
Input High Voltage
2.0
VCC + 0.5
2.0
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current VIN = 2.7 V
70
—
10
µA
IIL
Input Low Leakage Current
VIN=0.5 V
–70
—
–10
µA
VOH
Output High Voltage
IOUT = –2 mA
IOUT = –6 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
2.4
V
3.84
0.55
DS2316 Datasheet Revision 15.0
—
0.33
V
25
40MX and 42MX FPGAs
Table 23 •
DC Specification (5.0 V PCI Signaling)1
PCI
Symbol Parameter
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
Pin Inductance
1.
2.
3.
4.
Condition
MX
Min.
Max.
Min.
Max.
Units
10
—
10
pF
5
12
—
10
pF
20
—
< 8 nH4
nH
PCI Local Bus Specification, Version 2.1, Section 4.2.1.1.
Maximum rating for VCCI –0.5 V to 7.0 V
VIH(Min) is 2.4V for A42MX36 family. This applies only to VCCI of 5V and is not applicable to VCCI of 3.3V.
Dependent upon the chosen package. PCI recommends QFP and BGA packaging to reduce pin inductance and capacitance.
Table 24 •
AC Specifications (5.0V PCI Signaling)*
PCI
Symbol
Parameter
Condition
Min.
ICL
Low Clamp Current
–5 < VIN –1
–25 + (VIN +1) /0.015
Slew (r)
Output Rise Slew Rate 0.4 V to 2.4 V load
1
Slew (f)
Output Fall Slew Rate
1
2.4 V to 0.4 V load
MX
Max.
Min.
Max.
Units
–60
–10
mA
5
1.8
2.8
V/ns
5
2.8
4.3
V/ns
Note: *PCI Local Bus Specification, Version 2.1, Section 4.2.1.2.
DS2316 Datasheet Revision 15.0
26
40MX and 42MX FPGAs
3.9.3
Output Drive Characteristics for 3.3 V PCI Signaling
Table 25 •
DC Specification (3.3 V PCI Signaling)1
PCI
Symbol Parameter
Condition
MX
Min.
Max.
Min.
Max.
Units
2
VCCI
Supply Voltage for I/Os
3.0
3.6
3.0
3.6
V
VIH
Input High Voltage
0.5
VCC + 0.5
0.5
VCCI + 0.3
V
VIL
Input Low Voltage
–0.5
0.8
–0.3
0.8
V
IIH
Input High Leakage Current VIN = 2.7 V
70
10
µA
IIL
Input Leakage Current
–70
–10
µA
VOH
Output High Voltage
IOUT = –2 mA
VOL
Output Low Voltage
IOUT = 3 mA, 6 mA
CIN
Input Pin Capacitance
CCLK
CLK Pin Capacitance
LPIN
1.
2.
3.
0.9
3.3
5
Pin Inductance
0.1
0.1 VCCI
V
10
10
pF
12
10
20
pF
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