A54SX32-PQG208

v3.2 SX Family FPGAs ™ u e Leading Edge Performance • • • • Features 320 MHz Internal Performance 3.7 ns Clock-to-Out (Pin-to-Pin) 0.1 ns Input Setup 0.25 ns Clock Skew • • • • • • • • Specifications • • • • 12,000 to 48,000 System Gates Up to 249 User-Programmable I/O Pins Up to 1,080 Flip-Flops 0.35 µ CMOS • • 66 MHz PCI CPLD and FPGA Integration Single-Chip Solution 100% Resource Utilization with 100% Pin Locking 3.3 V and 5.0 V Operation with 5.0 V Input Tolerance Very Low Power Consumption Deterministic, User-Controllable Timing Unique In-System Diagnostic and Debug Capability with Silicon Explorer II Boundary Scan Testing in Compliance with IEEE Standard 1149.1 (JTAG) Secure Programming Technology Prevents Reverse Engineering and Design Theft SX Product Profile Device A54SX08 A54SX16 A54SX16P A54SX32 8,000 12,000 16,000 24,000 16,000 24,000 32,000 48,000 Logic Modules Combinatorial Cells 768 512 1,452 924 1,452 924 2,880 1,800 Register Cells (Dedicated Flip-Flops) 256 528 528 1,080 Maximum User I/Os 130 175 175 249 Capacity Typical Gates System Gates Clocks JTAG PCI Clock-to-Out Input Setup (external) Speed Grades Temperature Grades Packages (by pin count) PLCC PQFP VQFP TQFP PBGA FBGA June 2006 © 2006 Actel Corporation 3 3 3 3 Yes Yes Yes Yes – – Yes – 3.7 ns 3.9 ns 4.4 ns 4.6 ns 0.8 ns 0.5 ns 0.5 ns 0.1 ns Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 Std, –1, –2, –3 C, I, M C, I, M C, I, M C, I, M 84 208 100 144, 176 – 144 – 208 100 176 – – – 208 100 144, 176 – – – 208 – 144, 176 313, 329 – i See the Actel website for the latest version of the datasheet. SX Family FPGAs Ordering Information A54SX16 – P PQ 2 G 208 Application (Temperature Range) Blank = Commercial (0 to +70˚C) I = Industrial (–40 to +85˚C) M = Military (–55 to +125˚C) PP = Pre-production Package Lead Count Lead-Free Packaging Blank = Standard Packaging G = RoHS Compliant Packaging Package Type BG = Ball Grid Array PL = Plastic Leaded Chip Carrier PQ = Plastic Quad Flat Pack TQ = Thin (1.4 mm) Quad Flat Pack VQ = Very Thin (1.0 mm) Quad Flat Pack FG = Fine Pitch Ball Grid Array (1.0 mm) Speed Grade Blank = Standard Speed –1 = Approximately 15% Faster than Standard –2 = Approximately 25% Faster than Standard –3 = Approximately 35% Faster than Standard Blank = Not PCI Compliant P = PCI Compliant Part Number A54SX08 = 12,000 System Gates A54SX16 = 24,000 System Gates A54SX16P = 24,000 System Gates A54SX32 = 48,000 System Gates Plastic Device Resources User I/Os (including clock buffers) PLCC 84-Pin VQFP 100-Pin PQFP 208-Pin TQFP 144-Pin TQFP 176-Pin PBGA 313-Pin PBGA 329-Pin FBGA 144-Pin A54SX08 69 81 130 113 128 – – 111 A54SX16 – 81 175 – 147 – – – A54SX16P – 81 175 113 147 – – – A54SX32 – – 174 113 147 249 249 – Device Note: Package Definitions (Consult your local Actel sales representative for product availability): PLCC = Plastic Leaded Chip Carrier PQFP = Plastic Quad Flat Pack TQFP = Thin Quad Flat Pack VQFP = Very Thin Quad Flat Pack PBGA = Plastic Ball Grid Array FBGA = Fine Pitch (1.0 mm) Ball Grid Array ii v3.2 SX Family FPGAs Table of Contents SX Family FPGAs General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 3.3 V / 5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 PCI Compliance for the SX Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 A54SX16P AC Specifications for (PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 A54SX16P DC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-12 A54SX16P AC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-13 Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Power-Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15 Evaluating Power in SX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 SX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23 Package Pin Assignments 84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 313-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16 329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 v3.2 iii SX Family FPGAs SX Family FPGAs General Description SX Family Architecture The Actel SX family of FPGAs features a sea-of-modules architecture that delivers device performance and integration levels not currently achieved by any other FPGA architecture. SX devices greatly simplify design time, enable dramatic reductions in design costs and power consumption, and further decrease time to market for performance-intensive applications. The SX family architecture was designed to satisfy nextgeneration performance and integration requirements for production-volume designs in a broad range of applications. The Actel SX architecture features two types of logic modules, the combinatorial cell (C-cell) and the register cell (R-cell), each optimized for fast and efficient mapping of synthesized logic functions. The routing and interconnect resources are in the metal layers above the logic modules, providing optimal use of silicon. This enables the entire floor of the device to be spanned with an uninterrupted grid of fine-grained, synthesis-friendly logic modules (or “sea-of-modules”), which reduces the distance signals have to travel between logic modules. To minimize signal propagation delay, SX devices employ both local and general routing resources. The high-speed local routing resources (DirectConnect and FastConnect) enable very fast local signal propagation that is optimal for fast counters, state machines, and datapath logic. The general system of segmented routing tracks allows any logic module in the array to be connected to any other logic or I/O module. Within this system, propagation delay is minimized by limiting the number of antifuse interconnect elements to five (90 percent of connections typically use only three antifuses). The unique local and general routing structure featured in SX devices gives fast and predictable performance, allows 100 percent pin-locking with full logic utilization, enables concurrent PCB development, reduces design time, and allows designers to achieve performance goals with minimum effort. The SX family provides efficient use of silicon by locating the routing interconnect resources between the Metal 2 (M2) and Metal 3 (M3) layers (Figure 1-1 on page 1-2). This completely eliminates the channels of routing and interconnect resources between logic modules (as implemented on SRAM FPGAs and previous generations of antifuse FPGAs), and enables the entire floor of the device to be spanned with an uninterrupted grid of logic modules. Programmable Interconnect Element Interconnection between these logic modules is achieved using The Actel patented metal-to-metal programmable antifuse interconnect elements, which are embedded between the M2 and M3 layers. The antifuses are normally open circuit and, when programmed, form a permanent low-impedance connection. The extremely small size of these interconnect elements gives the SX family abundant routing resources and provides excellent protection against design pirating. Reverse engineering is virtually impossible because it is extremely difficult to distinguish between programmed and unprogrammed antifuses, and there is no configuration bitstream to intercept. Additionally, the interconnect elements (i.e., the antifuses and metal tracks) have lower capacitance and lower resistance than any other device of similar capacity, leading to the fastest signal propagation in the industry. Further complementing SX’s flexible routing structure is a hardwired, constantly loaded clock network that has been tuned to provide fast clock propagation with minimal clock skew. Additionally, the high performance of the internal logic has eliminated the need to embed latches or flip-flops in the I/O cells to achieve fast clockto-out or fast input setup times. SX devices have easy to use I/O cells that do not require HDL instantiation, facilitating design reuse and reducing design and verification time. Logic Module Design The SX family architecture is described as a “sea-ofmodules” architecture because the entire floor of the device is covered with a grid of logic modules with virtually no chip area lost to interconnect elements or routing. The Actel SX family provides two types of logic modules, the register cell (R-cell) and the combinatorial cell (C-cell). v3.2 1-1 SX Family FPGAs The R-cell contains a flip-flop featuring asynchronous clear, asynchronous preset, and clock enable (using the S0 and S1 lines) control signals (Figure 1-2). The R-cell registers feature programmable clock polarity selectable on a register-by-register basis. This provides additional flexibility while allowing mapping of synthesized functions into the SX FPGA. The clock source for the R-cell can be chosen from either the hardwired clock or the routed clock. Routing Tracks Metal 3 Amorphous Silicon/ Dielectric Antifuse Tungsten Plug Via Tungsten Plug Via Metal 2 Metal 1 Tungsten Plug Contact Silicon Substrate Figure 1-1 • SX Family Interconnect Elements Routed Data Input S1 S0 PSETB Direct Connect Input D Q Y HCLK CLKA, CLKB, Internal Logic CLRB CKS Figure 1-2 • CKP R-Cell The C-cell implements a range of combinatorial functions up to 5-inputs (Figure 1-3 on page 1-3). Inclusion of the DB input and its associated inverter function dramatically increases the number of combinatorial functions that can be implemented in a single module from 800 options in previous architectures to more than 4,000 in the SX architecture. An example of the improved flexibility 1 -2 v3.2 enabled by the inversion capability is the ability to integrate a 3-input exclusive-OR function into a single C-cell. This facilitates construction of 9-bit parity-tree functions with 2 ns propagation delays. At the same time, the C-cell structure is extremely synthesis friendly, simplifying the overall design and reducing synthesis time. SX Family FPGAs Chip Architecture To increase design efficiency and device performance, Actel has further organized these modules into SuperClusters (Figure 1-4). SuperCluster 1 is a two-wide grouping of Type 1 clusters. SuperCluster 2 is a two-wide group containing one Type 1 cluster and one Type 2 cluster. SX devices feature more SuperCluster 1 modules than SuperCluster 2 modules because designers typically require significantly more combinatorial logic than flipflops. The SX family chip architecture provides a unique approach to module organization and chip routing that delivers the best register/logic mix for a wide variety of new and emerging applications. Module Organization Actel has arranged all C-cell and R-cell logic modules into horizontal banks called clusters. There are two types of clusters: Type 1 contains two C-cells and one R-cell, while Type 2 contains one C-cell and two R-cells. D0 D1 Y D2 D3 Sb Sa DB A0 Figure 1-3 • B0 A1 B1 C-Cell C-Cell R-Cell D0 Routed Data Input S0 D1 S1 Y PSETB D2 Direct Connect Input D Q D3 Y Sa Sb HCLK CLRB CLKA, CLKB, Internal Logic DB CKS CKP Cluster 1 A0 Cluster 2 Cluster 2 Type 1 SuperCluster Figure 1-4 • B0 A1 B1 Cluster 1 Type 2 SuperCluster Cluster Organization v3.2 1-3 SX Family FPGAs Routing Resources Clusters and SuperClusters can be connected through the use of two innovative local routing resources called FastConnect and DirectConnect, which enable extremely fast and predictable interconnection of modules within clusters and SuperClusters (Figure 1-5 and Figure 1-6). This routing architecture also dramatically reduces the number of antifuses required to complete a circuit, ensuring the highest possible performance. DirectConnect • No antifuses • 0.1 ns routing delay FastConnect • One antifuse • 0.4 ns routing delay Routing Segments • Typically 2 antifuses • Max. 5 antifuses Figure 1-5 • DirectConnect and FastConnect for Type 1 SuperClusters DirectConnect • No antifuses • 0.1 ns routing delay FastConnect • One antifuse • 0.4 ns routing delay Routing Segments • Typically 2 antifuses • Max. 5 antifuses Figure 1-6 • 1 -4 DirectConnect and FastConnect for Type 2 SuperClusters v3.2 SX Family FPGAs Performance DirectConnect is a horizontal routing resource that provides connections from a C-cell to its neighboring Rcell in a given SuperCluster. DirectConnect uses a hardwired signal path requiring no programmable interconnection to achieve its fast signal propagation time of less than 0.1 ns. The combination of architectural features described above enables SX devices to operate with internal clock frequencies exceeding 300 MHz, enabling very fast execution of even complex logic functions. Thus, the SX family is an optimal platform upon which to integrate the functionality previously contained in multiple CPLDs. In addition, designs that previously would have required a gate array to meet performance goals can now be integrated into an SX device with dramatic improvements in cost and time to market. Using timingdriven place-and-route tools, designers can achieve highly deterministic device performance. With SX devices, designers do not need to use complicated performance-enhancing design techniques such as the use of redundant logic to reduce fanout on critical nets or the instantiation of macros in HDL code to achieve high performance. FastConnect enables horizontal routing between any two logic modules within a given SuperCluster and vertical routing with the SuperCluster immediately below it. Only one programmable connection is used in a FastConnect path, delivering maximum pin-to-pin propagation of 0.4 ns. In addition to DirectConnect and FastConnect, the architecture makes use of two globally oriented routing resources known as segmented routing and high-drive routing. The Actel segmented routing structure provides a variety of track lengths for extremely fast routing between SuperClusters. The exact combination of track lengths and antifuses within each path is chosen by the 100 percent automatic place-and-route software to minimize signal propagation delays. I/O Modules Each I/O on an SX device can be configured as an input, an output, a tristate output, or a bidirectional pin. The Actel high-drive routing structure provides three clock networks. The first clock, called HCLK, is hardwired from the HCLK buffer to the clock select multiplexer (MUX) in each R-cell. This provides a fast propagation path for the clock signal, enabling the 3.7 ns clock-to-out (pin-to-pin) performance of the SX devices. The hardwired clock is tuned to provide clock skew as low as 0.25 ns. The remaining two clocks (CLKA, CLKB) are global clocks that can be sourced from external pins or from internal logic signals within the SX device. Even without the inclusion of dedicated I/O registers, these I/Os, in combination with array registers, can achieve clock-to-out (pad-to-pad) timing as fast as 3.7 ns. I/O cells that have embedded latches and flip-flops require instantiation in HDL code; this is a design complication not encountered in SX FPGAs. Fast pin-topin timing ensures that the device will have little trouble interfacing with any other device in the system, which in turn enables parallel design of system components and reduces overall design time. Other Architectural Features Power Requirements The SX family supports 3.3 V operation and is designed to tolerate 5.0 V inputs. (Table 1-1). Power consumption is extremely low due to the very short distances signals are required to travel to complete a circuit. Power requirements are further reduced because of the small number of low-resistance antifuses in the path. The antifuse architecture does not require active circuitry to hold a charge (as do SRAM or EPROM), making it the lowest power architecture on the market. Technology The Actel SX family is implemented on a high-voltage twin-well CMOS process using 0.35 µ design rules. The metal-to-metal antifuse is made up of a combination of amorphous silicon and dielectric material with barrier metals and has a programmed ("on" state) resistance of 25 Ω with a capacitance of 1.0 fF for low signal impedance. Table 1-1 • Supply Voltages Device VCCA VCCI VCCR Maximum Input Tolerance Maximum Output Drive A54SX08 A54SX16 A54SX32 3.3 V 3.3 V 5.0 V 5.0 V 3.3 V A54SX16-P* 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 5.0 V 5.0 V 3.3 V 3.3 V 5.0 V 5.0 V 5.0 V 5.0 V Note: *A54SX16-P has three different entries because it is capable of both a 3.3 V and a 5.0 V drive. v3.2 1-5 SX Family FPGAs Boundary Scan Testing (BST) Development Tool Support All SX devices are IEEE 1149.1 compliant. SX devices offer superior diagnostic and testing capabilities by providing Boundary Scan Testing (BST) and probing capabilities. These functions are controlled through the special test pins in conjunction with the program fuse. The functionality of each pin is described in Table 1-2. In the dedicated test mode, TCK, TDI, and TDO are dedicated pins and cannot be used as regular I/Os. In flexible mode, TMS should be set HIGH through a pull-up resistor of 10 kΩ. TMS can be pulled LOW to initiate the test sequence. The SX family of FPGAs is fully supported by both the Actel Libero® Integrated Design Environment (IDE) and Designer FPGA Development software. Actel Libero IDE is a design management environment, seamlessly integrating design tools while guiding the user through the design flow, managing all design and log files, and passing necessary design data among tools. Libero IDE allows users to integrate both schematic and HDL synthesis into a single flow and verify the entire design in a single environment. Libero IDE includes Synplify® for Actel from Synplicity®, ViewDraw® for Actel from Mentor Graphics®, ModelSim® HDL Simulator from Mentor Graphics, WaveFormer Lite™ from SynaptiCAD™, and Designer software from Actel. Refer to the Libero IDE flow diagram (located on the Actel website) for more information. The program fuse determines whether the device is in dedicated or flexible mode. The default (fuse not blown) is flexible mode. Table 1-2 • Boundary Scan Pin Functionality Program Fuse Blown (Dedicated Test Mode) Program Fuse Not Blown (Flexible Mode) TCK, TDI, TDO are dedicated TCK, TDI, TDO are flexible and BST pins. may be used as I/Os. No need for pull-up resistor for Use a pull-up resistor of 10 kΩ TMS on TMS. Dedicated Test Mode In Dedicated mode, all JTAG pins are reserved for BST; designers cannot use them as regular I/Os. An internal pull-up resistor is automatically enabled on both TMS and TDI pins, and the TMS pin will function as defined in the IEEE 1149.1 (JTAG) specification. To select Dedicated mode, users need to reserve the JTAG pins in Actel's Designer software by checking the "Reserve JTAG" box in "Device Selection Wizard" (Figure 1-7). JTAG pins comply with LVTTL/TTL I/O specification regardless of whether they are used as a user I/O or a JTAG I/O. Refer to the Table 1-5 on page 1-8 for detailed specifications. Actel Designer software is a place-and-route tool and provides a comprehensive suite of backend support tools for FPGA development. The Designer software includes timing-driven place-and-route, and a world-class integrated static timing analyzer and constraints editor. With the Designer software, a user can select and lock package pins while only minimally impacting the results of place-and-route. Additionally, the back-annotation flow is compatible with all the major simulators, and the simulation results can be cross-probed with Silicon Explorer II, Actel integrated verification and logic analysis tool. Another tool included in the Designer software is the SmartGen core generator, which easily creates popular and commonly used logic functions for implementation into your schematic or HDL design. Actel Designer software is compatible with the most popular FPGA design entry and verification tools from companies such as Mentor Graphics, Synplicity, Synopsys®, and Cadence® Design Systems. The Designer software is available for both the Windows® and UNIX® operating systems. Probe Circuit Control Pins The Silicon Explorer II tool uses the boundary scan ports (TDI, TCK, TMS, and TDO) to select the desired nets for verification. The selected internal nets are assigned to the PRA/PRB pins for observation. Figure 1-8 on page 1-7 illustrates the interconnection between Silicon Explorer II and the FPGA to perform in-circuit verification. Design Considerations The TDI, TCK, TDO, PRA, and PRB pins should not be used as input or bidirectional ports. Because these pins are active during probing, critical signals input through these pins are not available while probing. In addition, the Security Fuse should not be programmed because doing so disables the Probe Circuitry. Figure 1-7 • Device Selection Wizard 1 -6 v3.2 SX Family FPGAs 16 Channels TDI TCK TMS Silicon Explorer II Serial Connection SX FPGA TDO PRA PRB Figure 1-8 • Probe Setup Programming The procedure for programming an SX device using Silicon Sculptor II are as follows: Device programming is supported through Silicon Sculptor series of programmers. In particular, Silicon Sculptor II are compact, robust, single-site and multi-site device programmer for the PC. 1. Load the .AFM file 2. Select the device to be programmed 3. Begin programming When the design is ready to go to production, Actel offers device volume-programming services either through distribution partners or via in-house programming from the factory. With standalone software, Silicon Sculptor II allows concurrent programming of multiple units from the same PC, ensuring the fastest programming times possible. Each fuse is subsequently verified by Silicon Sculptor II to insure correct programming. In addition, integrity tests ensure that no extra fuses are programmed. Silicon Sculptor II also provides extensive hardware self-testing capability. For more details on programming SX devices, refer to the Programming Antifuse Devices application note and the Silicon Sculptor II User's Guide. 3.3 V / 5 V Operating Conditions Table 1-3 • Absolute Maximum Ratings1 Symbol VCCR 2 Parameter DC Supply Voltage3 Limits Units –0.3 to + 6.0 V VCCA2 DC Supply Voltage –0.3 to + 4.0 V VCCI2 DC Supply Voltage (A54SX08, A54SX16, A54SX32) –0.3 to + 4.0 V DC Supply Voltage (A54SX16P) –0.3 to + 6.0 V VI Input Voltage –0.5 to + 5.5 V VO Output Voltage –0.5 to + 3.6 V IIO I/O Source Sink Current3 –30 to + 5.0 mA TSTG Storage Temperature –65 to +150 °C VCCI 2 Notes: 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the Recommended Operating Conditions. 2. VCCR in the A54SX16P must be greater than or equal to VCCI during power-up and power-down sequences and during normal operation. 3. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND – 0.5 V, the internal protection diodes will forward-bias and can draw excessive current. v3.2 1-7 SX Family FPGAs Table 1-4 • Recommended Operating Conditions Parameter Commercial Industrial Military Units 0 to + 70 –40 to + 85 –55 to +125 °C 3.3 V Power Supply Tolerance ±10 ±10 ±10 %VCC 5.0 V Power Supply Tolerance ±5 ±10 ±10 %VCC Temperature Range* Note: *Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Table 1-5 • Electrical Specifications Commercial Symbol Parameter VOH (IOH = –20 µA) (CMOS) (IOH = –8 mA) (TTL) Min. Max. Min. Max. Units (VCCI – 0.1) VCCI (VCCI – 0.1) VCCI V 2.4 VCCI 2.4 VCCI (IOH = –6 mA) (TTL) VOL Industrial (IOL= 20 µA) (CMOS) 0.10 (IOL = 12 mA) (TTL) 0.50 V (IOL = 8 mA) (TTL) 0.50 0.8 VIL VIH 2.0 0.8 2.0 V V tR , tF Input Transition Time tR, tF 50 50 ns CIO CIO I/O Capacitance 10 10 pF ICC Standby Current, ICC 4.0 4.0 mA ICC(D) ICC(D) IDynamic VCC Supply Current 1 -8 See "Evaluating Power in SX Devices" on page 1-16. v3.2 SX Family FPGAs PCI Compliance for the SX Family The SX family supports 3.3 V and 5.0 V PCI and is compliant with the PCI Local Bus Specification Rev. 2.1. Table 1-6 • A54SX16P DC Specifications (5.0 V PCI Operation) Symbol Parameter VCCA Condition Min. Max. Units Supply Voltage for Array 3.0 3.6 V VCCR Supply Voltage required for Internal Biasing 4.75 5.25 V VCCI Supply Voltage for I/Os 4.75 5.25 V 2.0 VCC + 0.5 V –0.5 0.8 V 1 VIH Input High Voltage VIL Input Low Voltage1 IIH Input High Leakage Current VIN = 2.7 70 µA IIL Input Low Leakage Current VIN = 0.5 –70 µA VOH Output High Voltage IOUT = –2 mA VOL Output Low Voltage2 IOUT = 3 mA, 6 mA Capacitance3 CIN Input Pin CCLK CLK Pin Capacitance CIDSEL IDSEL Pin 2.4 5 Capacitance4 V 0.55 V 10 pF 12 pF 8 pF Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 2. Signals without pull-up resistors must have 3 mA low output current. Signals requiring pull-up must have 6 mA; the latter include, FRAME#, IRDY#, TRDY#, DEVSEL#, STOP#, SERR#, PERR#, LOCK#, and, when used, AD[63::32], C/BE[7::4]#, PAR64, REQ64#, and ACK64#. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. v3.2 1-9 SX Family FPGAs A54SX16P AC Specifications for (PCI Operation) Table 1-7 • A54SX16P AC Specifications for (PCI Operation) Symbol Parameter Condition Min. IOH(AC) Switching Current High 0 < VOUT ≤ 1.41 1.4 ≤ VOUT < 2.4 1, 2 3.1 < VOUT < IOL(AC) Max. –44 mA –44 + (VOUT – 1.4)/0.024 mA VCC1, 3 EQ 1-1 on page 1-11 3 (Test Point) VOUT = 3.1 Switching Current High VOUT ≥ 2.21 –142 95 2.2 > VOUT > 0.55 1 VOUT /0.023 0.71 > VOUT > 0 ICL slewR slewF 3 VOUT = 0.71 Low Clamp Current –5 < VIN ≤ –1 Output Rise Slew Rate Output Fall Slew Rate mA mA 1, 3 (Test Point) Units EQ 1-2 on page 1-11 mA 206 mA –25 + (VIN + 1) /0.015 mA 0.4 V to 2.4 V load4 1 5 V/ns 2.4 V to 0.4 V load4 1 5 V/ns Notes: 1. Refer to the V/I curves in Figure 1-9 on page 1-11. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half-size output drivers may be used on these signals. This specification does not apply to CLK and RST#, which are system outputs. “Switching Current High” specifications are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD#, which are open drain outputs. 2. Note that this segment of the minimum current curve is drawn from the AC drive point directly to the DC drive point rather than toward the voltage rail (as is done in the pull-down curve). This difference is intended to allow for an optional N-channel pull-up. 3. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (A and B) are provided with the respective diagrams in Figure 1-9 on page 1-11. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 4. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per revision 2.0 of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is now required (the maximum is no longer simply a guideline). Since adherence to the maximum slew rate was not required prior to revision 2.1 of the specification, there may be components in the market for some time that have faster edge rates; therefore, motherboard designers must bear in mind that rise and fall times faster than this specification could occur, and should ensure that signal integrity modeling accounts for this. Rise slew rate does not apply to open drain outputs. Pin 1/2 in. max. Output Buffer 1 kΩ 1 kΩ 1 -1 0 VCC 10 pF v3.2 SX Family FPGAs Figure 1-9 shows the 5.0 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 PCI IOL Maximum 0.35 Current (A) 0.30 0.25 SX PCI IOL 0.20 0.15 0.10 PCI IOL Mininum 0.05 0 1 –0.05 –0.10 2 3 4 5 6 PCI IOH Mininum SX PCI IOH –0.15 PCI IOH Maximum –0.20 Voltage Out Figure 1-9 • 5.0 V PCI Curve for A54SX16P Device IOH = 11.9 × (VOUT – 5.25) × (VOUT + 2.45) IOL = 78.5 × VOUT × (4.4 – VOUT) for VCC > VOUT > 3.1 V for 0 V < VOUT < 0.71 V EQ 1-1 EQ 1-2 v3.2 1-11 SX Family FPGAs A54SX16P DC Specifications (3.3 V PCI Operation) Table 1-8 • A54SX16P DC Specifications (3.3 V PCI Operation) Symbol Parameter VCCA Min. Max. Units Supply Voltage for Array 3.0 3.6 V VCCR Supply Voltage required for Internal Biasing 3.0 3.6 V VCCI Supply Voltage for I/Os 3.0 3.6 V VIH Input High Voltage 0.5VCC VCC + 0.5 V VIL Input Low Voltage –0.5 0.3VCC V IIPU Input Pull-up Voltage Condition 1 0.7VCC 2 IIL Input Leakage Current VOH Output High Voltage IOUT = –500 µA VOL Output Low Voltage IOUT = 1500 µA Input Pin CCLK CLK Pin Capacitance IDSEL Pin ±10 0.9VCC Capacitance3 CIN CIDSEL 0 < VIN < VCC 5 Capacitance4 V µA V 0.1VCC V 10 pF 12 pF 8 pF Notes: 1. This specification should be guaranteed by design. It is the minimum voltage to which pull-up resistors are calculated to pull a floated network. Applications sensitive to static power utilization should assure that the input buffer is conducting minimum current at this input voltage. 2. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tristate outputs. 3. Absolute maximum pin capacitance for a PCI input is 10 pF (except for CLK). 4. Lower capacitance on this input-only pin allows for non-resistive coupling to AD[xx]. 1 -1 2 v3.2 SX Family FPGAs A54SX16P AC Specifications (3.3 V PCI Operation) Table 1-9 • A54SX16P AC Specifications (3.3 V PCI Operation) Symbol Parameter Condition Switching Current High IOH(AC) Min. 0 < VOUT ≤ 0.3VCC1 0.3VCC ≤ VOUT < –12VCC 0.7VCC < VOUT < VCC1, 2 –17.1 + (VCC – VOUT) mA 0.7VCC2 VOUT = Switching Current High VCC > VOUT ≥ 0.6VCC1 0.6VCC > VOUT > EQ 1-3 on page 1-14 –32VCC mA mA 0.1VCC1 0.18VCC > VOUT > 0 Units mA 0.9VCC1 (Test Point) IOL(AC) Max. 16VCC 1, 2 mA 26.7VOUT EQ 1-4 on page 1-14 0.18VCC2 mA (Test Point) VOUT = ICL Low Clamp Current –3 < VIN ≤ –1 –25 + (VIN + 1)/0.015 mA ICH High Clamp Current –3 < VIN ≤ –1 25 + (VIN – VOUT – 1)/0.015 mA slewR slewF Rate3 0.2VCC to 0.6VCC load 1 4 V/ns Rate3 0.6VCC to 0.2VCC load 1 4 V/ns Output Rise Slew Output Fall Slew 38VCC Notes: 1. Refer to the V/I curves in Figure 1-10 on page 1-14. Switching current characteristics for REQ# and GNT# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. This specification does not apply to CLK and RST# which are system outputs. “Switching Current High” specification are not relevant to SERR#, INTA#, INTB#, INTC#, and INTD# which are open drain outputs. 2. Maximum current requirements must be met as drivers pull beyond the last step voltage. Equations defining these maximums (C and D) are provided with the respective diagrams in Figure 1-10 on page 1-14. The equation defined maxima should be met by design. In order to facilitate component testing, a maximum current test point is defined for each side of the output driver. 3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the instantaneous rate at any point within the transition range. The specified load (diagram below) is optional; i.e., the designer may elect to meet this parameter with an unloaded output per the latest revision of the PCI Local Bus Specification. However, adherence to both maximum and minimum parameters is required (the maximum is no longer simply a guideline). Rise slew rate does not apply to open drain outputs. Pin 1/2 in. max. Output Buffer VCC 10 pF 1 kΩ 1 kΩ v3.2 1-13 SX Family FPGAs Figure 1-10 shows the 3.3 V PCI V/I curve and the minimum and maximum PCI drive characteristics of the A54SX16P device. 0.50 0.45 0.40 PCI IOL Maximum 0.35 Current (A) 0.30 0.25 0.20 SX PCI IOL 0.15 0.10 PCI IOL Minimum 0.05 SX PCI IOH 0 –0.05 1 2 3 PCI IOH Minimum 4 5 6 PCI IOH Maximum –0.10 –0.15 –0.20 Voltage Out Figure 1-10 • 3.3 V PCI Curve for A54SX16P Device IOH = (98.0/VCC) × (VOUT – VCC) × (VOUT + 0.4VCC) IOL = (256/VCC) × VOUT × (VCC – VOUT) for VCC > VOUT > 0.7 VCC for 0 V < VOUT < 0.18 VCC EQ 1-3 1 -1 4 v3.2 EQ 1-4 SX Family FPGAs Power-Up Sequencing Table 1-10 • Power-Up Sequencing VCCA VCCR VCCI Power-Up Sequence Comments 3.3 V 5.0 V First 3.3 V Second No possible damage to device 3.3 V First 5.0 V Second Possible damage to device A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 3.3 V Only No possible damage to device 3.3 V 5.0 V 3.3 V 5.0 V First 3.3 V Second No possible damage to device 3.3 V First 5.0 V Second Possible damage to device 5.0 V First 3.3 V Second No possible damage to device 3.3 V First 5.0 V Second No possible damage to device 3.3 V 5.0 V 5.0 V Note: No inputs should be driven (high or low) before completion of power-up. Power-Down Sequencing Table 1-11 • Power-Down Sequencing VCCA VCCR VCCI Power-Down Sequence Comments 3.3 V 5.0 V First 3.3 V Second Possible damage to device 3.3 V First 5.0 V Second No possible damage to device A54SX08, A54SX16, A54SX32 3.3 V 5.0 V A54SX16P 3.3 V 3.3 V 3.3 V 3.3 V Only No possible damage to device 3.3 V 5.0 V 3.3 V 5.0 V First 3.3 V Second Possible damage to device 3.3 V First 5.0 V Second No possible damage to device 5.0 V First 3.3 V Second No possible damage to device 3.3 V First 5.0 V Second No possible damage to device 3.3 V 5.0 V 5.0 V Note: No inputs should be driven (high or low) after the beginning of the power-down sequence. v3.2 1-15 SX Family FPGAs Evaluating Power in SX Devices AC Power Dissipation A critical element of system reliability is the ability of electronic devices to safely dissipate the heat generated during operation. The thermal characteristics of a circuit depend on the device and package used, the operating temperature, the operating current, and the system's ability to dissipate heat. The power dissipation of the SX Family is usually dominated by the dynamic power dissipation. Dynamic power dissipation is a function of frequency, equivalent capacitance, and power supply voltage. The AC power dissipation is defined in EQ 1-7 and EQ 1-8. PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net + POutput Buffer + PInput Buffer You should complete a power evaluation early in the design process to help identify potential heat-related problems in the system and to prevent the system from exceeding the device’s maximum allowed junction temperature. The actual power dissipated by most applications is significantly lower than the power the package can dissipate. However, a thermal analysis should be performed for all projects. To perform a power evaluation, follow these steps: 1. Estimate the application. power consumption of the EQ 1-7 PAC = VCCA2 × [(m × CEQM × fm)Module + (n × CEQI × fn)Input Buffer+ (p × (CEQO + CL) × fp)Output Buffer + (0.5 × (q1 × CEQCR × fq1) + (r1 × fq1))RCLKA + (0.5 × (q2 × CEQCR × fq2)+ (r2 × fq2))RCLKB + (0.5 × (s1 × CEQHV × fs1) + (CEQHF × fs1))HCLK] EQ 1-8 Definition of Terms Used in Formula 2. Calculate the maximum power allowed for the device and package. m n p q1 = = = = 3. Compare the estimated power and maximum power values. q2 = x y r1 r2 = = = = s1 = CEQM CEQI CEQO CEQCR CEQHV CEQHF CL fm fn fp fq1 fq2 fs1 = = = = = = = = = = = = = Estimating Power Consumption The total power dissipation for the SX family is the sum of the DC power dissipation and the AC power dissipation. Use EQ 1-5 to calculate the estimated power consumption of your application. PTotal = PDC + PAC EQ 1-5 DC Power Dissipation The power due to standby current is typically a small component of the overall power. The Standby power is shown in Table 1-12 for commercial, worst-case conditions (70°C). Table 1-12 • Standby Power ICC VCC Power 4 mA 3.6 V 14.4 mW The DC power dissipation is defined in EQ 1-6. PDC = (Istandby) × VCCA + (Istandby) × VCCR + (Istandby) × VCCI + xVOL × IOL + y(VCCI – VOH) × VOH EQ 1-6 1 -1 6 v3.2 Number of logic modules switching at fm Number of input buffers switching at fn Number of output buffers switching at fp Number of clock loads on the first routed array clock Number of clock loads on the second routed array clock Number of I/Os at logic low Number of I/Os at logic high Fixed capacitance due to first routed array clock Fixed capacitance due to second routed array clock Number of clock loads on the dedicated array clock Equivalent capacitance of logic modules in pF Equivalent capacitance of input buffers in pF Equivalent capacitance of output buffers in pF Equivalent capacitance of routed array clock in pF Variable capacitance of dedicated array clock Fixed capacitance of dedicated array clock Output lead capacitance in pF Average logic module switching rate in MHz Average input buffer switching rate in MHz Average output buffer switching rate in MHz Average first routed array clock rate in MHz Average second routed array clock rate in MHz Average dedicated array clock rate in MHz SX Family FPGAs Table 1-13 devices. shows capacitance values for Guidelines for Calculating Power Consumption various Table 1-13 • Capacitance Values for Devices The power consumption guidelines are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. These guidelines are shown in Table 1-14. A54SX08 A54SX16 A54SX16P A54SX32 CEQM (pF) 4.0 4.0 4.0 4.0 CEQI (pF) 3.4 3.4 3.4 3.4 CEQO (pF) 4.7 4.7 4.7 4.7 Sample Power Calculation CEQCR (pF) One of the designs used to characterize the SX family was a 528 bit serial-in, serial-out shift register. The design utilized 100 percent of the dedicated flip-flops of an A54SX16P device. A pattern of 0101… was clocked into the device at frequencies ranging from 1 MHz to 200 MHz. Shifting in a series of 0101… caused 50 percent of the flip-flops to toggle from low to high at every clock cycle. 1.6 1.6 1.6 1.6 CEQHV 0.615 0.615 0.615 0.615 CEQHF 60 96 96 140 r1 (pF) 87 138 138 171 r2 (pF) 87 138 138 171 Table 1-14 • Power Consumption Guidelines Description Power Consumption Guideline Logic Modules (m) 20% of modules Inputs Switching (n) # inputs/4 Outputs Switching (p) # outputs/4 First Routed Array Clock Loads (q1) 20% of register cells Second Routed Array Clock Loads (q2) 20% of register cells Load Capacitance (CL) 35 pF Average Logic Module Switching Rate (fm) f/10 Average Input Switching Rate (fn) f/5 Average Output Switching Rate (fp) f/10 Average First Routed Array Clock Rate (fq1) f/2 Average Second Routed Array Clock Rate (fq2) f/2 Average Dedicated Array Clock Rate (fs1) f Dedicated Clock Array Clock Loads (s1) 20% of regular modules AC Power Dissipation Follow the steps below to estimate power consumption. The values provided for the sample calculation below are for the shift register design above. This method for estimating power consumption is conservative and the actual power consumption of your design may be less than the estimated power consumption. PAC = PModule + PRCLKA Net + PRCLKB Net + PHCLK Net + POutput Buffer + PInput Buffer EQ 1-10 2 PAC = VCCA × [(m × CEQM × fm)Module + (n × CEQI × fn)Input Buffer+ (p × (CEQO + CL) × fp)Output Buffer + (0.5 (q1 × CEQCR × fq1) + (r1 × fq1))RCLKA + (0.5 (q2 × CEQCR × fq2)+ (r2 × fq2))RCLKB + (0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1))HCLK] The total power dissipation for the SX family is the sum of the AC power dissipation and the DC power dissipation. PTotal = PAC (dynamic power) + PDC (static power) EQ 1-9 EQ 1-11 v3.2 1-17 SX Family FPGAs Step 1: Define Terms Used in Formula VCCA 3.3 Number of logic modules switching at fm (Used 50%) m 264 Average logic modules switching rate fm (MHz) (Guidelines: f/10) fm 20 Module capacitance CEQM (pF) CEQM 4.0 Number of input buffers switching at fn n 1 Average input switching rate fn (MHz) (Guidelines: f/5) fn 40 Input buffer capacitance CEQI (pF) CEQI 3.4 Step 2: Calculate Dynamic Power Consumption VCCA × VCCA 10.89 0.02112 m × fm × CEQM n × fn × CEQI 0.000136 p × fp × (CEQO+CL) 0.000794 0.11208 0.5 (q1 × CEQCR × fq1) + (r1 × fq1) 0.5(q2 × CEQCR × fq2) + (r2 × fq2) 0 0.5 (s1 × CEQHV × fs1) + (CEQHF × fs1) 0 PAC = 1.461 W Module Input Buffer Step 3: Calculate DC Power Dissipation DC Power Dissipation PDC = (Istandby) × VCCA + (Istandby) × VCCR + (Istandby) × VCCI + X × VOL × IOL + Y(VCCI – VOH) × VOH Output Buffer Number of output buffers switching at fp p 1 Average output buffers switching rate fp(MHz) (Guidelines: f/10) fp 20 Output buffers buffer capacitance CEQO (pF) CEQO 4.7 Output Load capacitance CL (pF) CL 35 Number of Clock loads q1 q1 528 Capacitance of routed array clock (pF) CEQCR 1.6 Average clock rate (MHz) fq1 200 Fixed capacitance (pF) r1 138 Number of Clock loads q2 q2 0 Capacitance of routed array clock (pF) CEQCR 1.6 Average clock rate (MHz) fq2 0 Fixed capacitance (pF) r2 138 Number of Clock loads s1 0 Variable capacitance of dedicated array clock (pF) CEQHV 0.61 5 Fixed capacitance of dedicated array clock (pF) CEQHF 96 Average clock rate (MHz) fs1 0 EQ 1-12 For a rough estimate of DC Power Dissipation, only use PDC = (Istandby) × VCCA. The rest of the formula provides a very small number that can be considered negligible. PDC = (Istandby) × VCCA PDC = .55 mA × 3.3 V RCLKA PDC = 0.001815 W Step 4: Calculate Total Power Consumption PTotal = PAC + PDC PTotal = 1.461 + 0.001815 PTotal = 1.4628 W RCLKB Step 5: Compare Estimated Power Consumption against Characterized Power Consumption The estimated total power consumption for this design is 1.46 W. The characterized power consumption for this design at 200 MHz is 1.0164 W. HCLK 1 -1 8 v3.2 SX Family FPGAs Figure 1-11 shows the characterized power dissipation numbers for the shift register design using frequencies ranging from 1 MHz to 200 MHz. 1200 Power Dissipation mW 1000 800 600 400 200 0 0 20 40 60 80 100 120 140 160 180 200 Frequency MHz Figure 1-11 • Power Dissipation Junction Temperature (TJ) P The temperature that you select in Designer Series software is the junction temperature, not ambient temperature. This is an important distinction because the heat generated from dynamic power consumption is usually hotter than the ambient temperature. Use the equation below to calculate junction temperature. = Power calculated from Consumption section Estimating Power θja = Junction to ambient of package. θja numbers are located in the "Package Thermal Characteristics" section. Package Thermal Characteristics The device junction to case thermal characteristic is θjc, and the junction to ambient air characteristic is θja. The thermal characteristics for θja are shown with two different air flow rates. Junction Temperature = ΔT + Ta EQ 1-13 Where: The maximum junction temperature is 150 °C. Ta = Ambient Temperature A sample calculation of the absolute maximum power dissipation allowed for a TQFP 176-pin package at commercial temperature and still air is as follows: ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja × P 150°C – 70°C Max. junction temp. (°C) – Max. ambient temp. (°C) Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------ = ----------------------------------- = 2.86 W 28°C/W θ ja (°C/W) EQ 1-14 v3.2 1-19 SX Family FPGAs Table 1-15 • Package Thermal Characteristics Pin Count θjc θja Still Air θja 300 ft/min. Units Plastic Leaded Chip Carrier (PLCC) 84 12 32 22 °C/W Thin Quad Flat Pack (TQFP) 144 11 32 24 °C/W Thin Quad Flat Pack (TQFP) 176 11 28 21 °C/W Very Thin Quad Flatpack (VQFP) 100 10 38 32 °C/W Plastic Quad Flat Pack (PQFP) without Heat Spreader 208 8 30 23 °C/W Plastic Quad Flat Pack (PQFP) with Heat Spreader 208 3.8 20 17 °C/W Plastic Ball Grid Array (PBGA) 272 3 20 14.5 °C/W Plastic Ball Grid Array (PBGA) 313 3 23 17 °C/W Plastic Ball Grid Array (PBGA) 329 3 18 13.5 °C/W Fine Pitch Ball Grid Array (FBGA) 144 3.8 38.8 26.7 °C/W Package Type Note: SX08 does not have a heat spreader. Table 1-16 • Temperature and Voltage Derating Factors* Junction Temperature VCCA –55 –40 0 25 70 85 125 3.0 0.75 0.78 0.87 0.89 1.00 1.04 1.16 3.3 0.70 0.73 0.82 0.83 0.93 0.97 1.08 3.6 0.66 0.69 0.77 0.78 0.87 0.92 1.02 Note: *Normalized to worst-case commercial, TJ = 70°C, VCCA = 3.0 V 1 -2 0 v3.2 SX Family FPGAs SX Timing Model Input Delays I/O Module tINY = 1.5 ns Predicted Routing Delays Internal Delays Combinatorial Cell Output Delays I/O Module tIRD2 = 0.6 ns tDHL = 1.6 ns tRD1 = 0.3 ns tRD4 = 1.0 ns tRD8 = 1.9 ns tPD = 0.6 ns I/O Module tDLH = 1.6 ns Register Cell D Register Cell D Q Q tRD1 = 0.3 ns tRD1 = 0.3 ns tENZH = 2.3 ns tSUD = 0.5 ns tHD = 0.0 ns Routed Clock tRCO = 0.8 ns tRCO = 0.8 ns tRCKH = 1.5 ns (100% Load) FMAX = 250 MHz Hardwired Clock tHCKH = 1.0 ns FHMAX = 320 MHz Note: Values shown for A54SX08-3, worst-case commercial conditions. Figure 1-12 • SX Timing Model Hardwired Clock External Setup = tINY + tIRD1 + tSUD – tHCKH = 1.5 + 0.3 + 0.5 – 1.0 = 1.3 ns Routed Clock External Setup = tINY + tIRD1 + tSUD – tRCKH = 1.5 + 0.3 + 0.5 – 1.5 = 0.8 ns EQ 1-15 EQ 1-17 Clock-to-Out (Pin-to-Pin) Clock-to-Out (Pin-to-Pin) = tHCKH + tRCO + tRD1 + tDHL = tRCKH + tRCO + tRD1 + tDHL = 1.0 + 0.8 + 0.3 + 1.6 = 3.7 ns = 1.52+ 0.8 + 0.3 + 1.6 = 4.2 ns EQ 1-16 EQ 1-18 v3.2 1-21 SX Family FPGAs E D VCC VCC In VOL 1.5 V 1.5 V tDLH En GND 50% 50% VOH Out PAD To AC Test Loads (shown below) TRIBUFF Out GND 50% 50% VCC 1.5 V 10% VOL tDHL GND VOH Out GND tENLZ tENZL VCC 50% 50% En 90% 1.5 V tENZH tENHZ Figure 1-13 • Output Buffer Delays Load 2 (used to measure disable delays) VCC GND Load 2 (used to measure enable delays) VCC GND Load 1 (used to measure propagation delay) To Output Under Test 35 pF To Output Under Test R to VCC for tPLZ R to GND for tPHZ R = 1 kΩ R to VCC for tPLZ R to GND for tPHZ R = 1 kΩ To Output Under Test 35 pF 35 pF Figure 1-14 • AC Test Loads PAD INBUF S A B Y Y VCC S, A ,or B In 3V 1.5 V 1.5 V VCC Out GND VCC Out GND 0V 50% tPD tINY Figure 1-15 • Input Buffer Delays 1 -2 2 50% 50% tPD tPD Out 50% 50% tINY GND 50% 50% Figure 1-16 • C-Cell Delays v3.2 GND tPD VCC 50% SX Family FPGAs Register Cell Timing Characteristics Q PRESET D CLR CLK (positive edge triggered) tHD D tSUD CLK tHP tHPWH' RPWH tRCO tHPWL' RPWL Q tCLR tPRESET CLR tWASYN PRESET Figure 1-17 • Flip-Flops Timing Characteristics Long Tracks Timing characteristics for SX devices fall into three categories: family-dependent, device-dependent, and design-dependent. The input and output buffer characteristics are common to all SX family members. Internal routing delays are device-dependent. Design dependency means actual delays are not determined until after placement and routing of the user’s design is complete. Delay values may then be determined by using the DirectTime Analyzer utility or performing simulation with post-layout delays. Some nets in the design use long tracks. Long tracks are special routing resources that span multiple rows, columns, or modules. Long tracks employ three and sometimes five antifuse connections. This increases capacitance and resistance, resulting in longer net delays for macros connected to long tracks. Typically up to 6 percent of nets in a fully utilized device require long tracks. Long tracks contribute approximately 4 ns to 8.4 ns delay. This additional delay is represented statistically in higher fanout (FO = 24) routing delays in the datasheet specifications section. Critical Nets and Typical Nets Timing Derating Propagation delays are expressed only for typical nets, which are used for initial design performance evaluation. Critical net delays can then be applied to the most timecritical paths. Critical nets are determined by net property assignment prior to placement and routing. Up to 6% of the nets in a design may be designated as critical, while 90% of the nets in a design are typical. SX devices are manufactured in a CMOS process. Therefore, device performance varies according to temperature, voltage, and process variations. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature, and best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature, and worst-case processing. v3.2 1-23 SX Family FPGAs A54SX08 Timing Characteristics Table 1-17 • A54SX08 Timing Characteristics (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing 0.6 0.7 0.8 0.9 ns Delays2 tDC FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns tFC FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns tRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns Input Module Predicted Routing Delays2 tIRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tIRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tIRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tIRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tIRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tIRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 1 -2 4 v3.2 SX Family FPGAs Table 1-17 • A54SX08 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH Input LOW to HIGH (pad to R-Cell input) 1.0 1.1 1.3 1.5 ns tHCKL Input HIGH to LOW (pad to R-Cell input) 1.0 1.2 1.4 1.6 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.1 2.7 0.2 3.1 0.2 3.6 0.2 4.2 ns ns 350 320 280 240 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (light load) (pad to R-Cell input) 1.3 1.5 1.7 2.0 ns tRCKL Input HIGH to LOW (light load) (pad to R-Cell Input) 1.4 1.6 1.8 2.1 ns tRCKH Input LOW to HIGH (50% load) (pad to R-Cell input) 1.4 1.7 1.9 2.2 ns tRCKL Input HIGH to LOW (50% load) (pad to R-Cell input) 1.5 1.7 2.0 2.3 ns tRCKH Input LOW to HIGH (100% load) (pad to R-Cell input) 1.5 1.7 1.9 2.2 ns tRCKL Input HIGH to LOW (100% load) (pad to R-Cell input) 1.5 1.8 2.0 2.3 ns tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns tRCKSW Maximum Skew (light load) 0.1 0.2 0.2 0.2 ns tRCKSW Maximum Skew (50% load) 0.3 0.3 0.4 0.4 ns tRCKSW Maximum Skew (100% load) 0.3 0.3 0.4 0.4 ns TTL Output Module Timing1 tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.8 3.2 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. v3.2 1-25 SX Family FPGAs A54SX16 Timing Characteristics Table 1-18 • A54SX16 Timing Characteristics (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA ,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing 0.6 0.7 0.8 0.9 ns Delays2 tDC FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns tFC FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns tRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.8 1.1 1.2 1.4 ns tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns Predicted Input Routing Delays2 tIRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tIRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tIRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tIRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tIRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tIRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH, the loading is 5 pF. 1 -2 6 v3.2 SX Family FPGAs Table 1-18 • A54SX16 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA ,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH Input LOW to HIGH (pad to R-Cell input) 1.2 1.4 1.5 1.8 ns tHCKL Input HIGH to LOW (pad to R-Cell input) 1.2 1.4 1.6 1.9 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 2.7 0.2 3.1 0.3 3.6 0.3 4.2 ns ns 350 320 280 240 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (light load) (pad to R-Cell input) 1.6 1.8 2.1 2.5 ns tRCKL Input HIGH to LOW (light load) (pad to R-Cell input) 1.8 2.0 2.3 2.7 ns tRCKH Input LOW to HIGH (50% load) (pad to R-Cell input) 1.8 2.1 2.5 2.8 ns tRCKL Input HIGH to LOW (50% load) (pad to R-Cell input) 2.0 2.2 2.5 3.0 ns tRCKH Input LOW to HIGH (100% load) (pad to R-Cell input) 1.8 2.1 2.4 2.8 ns tRCKL Input HIGH to LOW (100% load) (pad to R-Cell input) 2.0 2.2 2.5 3.0 ns tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns tRCKSW Maximum Skew (light load) 0.5 0.5 0.5 0.7 ns tRCKSW Maximum Skew (50% load) 0.5 0.6 0.7 0.8 ns tRCKSW Maximum Skew (100% load) 0.5 0.6 0.7 0.8 ns TTL Output Module Timing3 tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.8 3.2 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns tENHZ Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns Notes: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH, the loading is 5 pF. v3.2 1-27 SX Family FPGAs A54SX16P Timing Characteristics Table 1-19 • A54SX16P Timing Characteristics (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA ,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing Delays 0.6 0.7 0.8 0.9 ns 2 tDC FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns tFC FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns tRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.9 1.1 1.3 1.4 ns tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.5 0.5 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns Predicted Input Routing Delays 2 tIRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tIRD2 FO = 2 Routing Delay 0.6 0.7 0.8 0.9 ns tIRD3 FO = 3 Routing Delay 0.8 0.9 1.0 1.2 ns tIRD4 FO = 4 Routing Delay 1.0 1.2 1.4 1.6 ns tIRD8 FO = 8 Routing Delay 1.9 2.2 2.5 2.9 ns tIRD12 FO = 12 Routing Delay 2.8 3.2 3.7 4.3 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 10 pF loading. 1 -2 8 v3.2 SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA ,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH Input LOW to HIGH (pad to R-Cell input) 1.2 1.4 1.5 1.8 ns tHCKL Input HIGH to LOW (pad to R-Cell input) 1.2 1.4 1.6 1.9 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.2 2.7 0.2 3.1 0.3 3.6 0.3 4.2 ns ns 350 320 280 240 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (light load) (pad to R-Cell input) 1.6 1.8 2.1 2.5 ns tRCKL Input HIGH to LOW (Light Load) (pad to R-Cell input) 1.8 2.0 2.3 2.7 ns tRCKH Input LOW to HIGH (50% load) (pad to R-Cell input) 1.8 2.1 2.5 2.8 ns tRCKL Input HIGH to LOW (50% load) (pad to R-Cell input) 2.0 2.2 2.5 3.0 ns tRCKH Input LOW to HIGH (100% load) (pad to R-Cell input) 1.8 2.1 2.4 2.8 ns tRCKL Input HIGH to LOW (100% load) (pad to R-Cell input) 2.0 2.2 2.5 3.0 ns tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns tRCKSW Maximum Skew (light load) 0.5 0.5 0.5 0.7 ns tRCKSW Maximum Skew (50% load) 0.5 0.6 0.7 0.8 ns tRCKSW Maximum Skew (100% load) 0.5 0.6 0.7 0.8 ns TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 2.4 2.8 3.1 3.7 ns tDHL Data-to-Pad HIGH to LOW 2.3 2.9 3.2 3.8 ns tENZL Enable-to-Pad, Z to L 3.0 3.4 3.9 4.6 ns tENZH Enable-to-Pad, Z to H 3.3 3.8 4.3 5.0 ns tENLZ Enable-to-Pad, L to Z 2.3 2.7 3.0 3.5 ns tENHZ Enable-to-Pad, H to Z 2.8 3.2 3.7 4.3 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 10 pF loading. v3.2 1-29 SX Family FPGAs Table 1-19 • A54SX16P Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCR = 4.75 V, VCCA ,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units TTL/PCI Output Module Timing tDLH Data-to-Pad LOW to HIGH 1.5 1.7 2.0 2.3 ns tDHL Data-to-Pad HIGH to LOW 1.9 2.2 2.4 2.9 ns tENZL Enable-to-Pad, Z to L 2.3 2.6 3.0 3.5 ns tENZH Enable-to-Pad, Z to H 1.5 1.7 1.9 2.3 ns tENLZ Enable-to-Pad, L to Z 2.7 3.1 3.5 4.1 ns tENHZ Enable-to-Pad, H to Z 2.9 3.3 3.7 4.4 ns 3 PCI Output Module Timing tDLH Data-to-Pad LOW to HIGH 1.8 2.0 2.3 2.7 ns tDHL Data-to-Pad HIGH to LOW 1.7 2.0 2.2 2.6 ns tENZL Enable-to-Pad, Z to L 0.8 1.0 1.1 1.3 ns tENZH Enable-to-Pad, Z to H 1.2 1.2 1.5 1.8 ns tENLZ Enable-to-Pad, L to Z 1.0 1.1 1.3 1.5 ns tENHZ Enable-to-Pad, H to Z 1.1 1.3 1.5 1.7 ns TTL Output Module Timing tDLH Data-to-Pad LOW to HIGH 2.1 2.5 2.8 3.3 ns tDHL Data-to-Pad HIGH to LOW 2.0 2.3 2.6 3.1 ns tENZL Enable-to-Pad, Z to L 2.5 2.9 3.2 3.8 ns tENZH Enable-to-Pad, Z to H 3.0 3.5 3.9 4.6 ns tENLZ Enable-to-Pad, L to Z 2.3 2.7 3.1 3.6 ns tENHZ Enable-to-Pad, H to Z 2.9 3.3 3.7 4.4 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 10 pF loading. 1 -3 0 v3.2 SX Family FPGAs A54SX32 Timing Characteristics Table 1-20 • A54SX32 Timing Characteristics (Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units C-Cell Propagation Delays1 tPD Internal Array Module Predicted Routing 0.6 0.7 0.8 0.9 ns Delays2 tDC FO = 1 Routing Delay, Direct Connect 0.1 0.1 0.1 0.1 ns tFC FO = 1 Routing Delay, Fast Connect 0.3 0.4 0.4 0.5 ns tRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tRD2 FO = 2 Routing Delay 0.7 0.8 0.9 1.0 ns tRD3 FO = 3 Routing Delay 1.0 1.2 1.4 1.6 ns tRD4 FO = 4 Routing Delay 1.4 1.6 1.8 2.1 ns tRD8 FO = 8 Routing Delay 2.7 3.1 3.5 4.1 ns tRD12 FO = 12 Routing Delay 4.0 4.7 5.3 6.2 ns R-Cell Timing tRCO Sequential Clock-to-Q 0.8 1.1 1.3 1.4 ns tCLR Asynchronous Clear-to-Q 0.5 0.6 0.7 0.8 ns tPRESET Asynchronous Preset-to-Q 0.7 0.8 0.9 1.0 ns tSUD Flip-Flop Data Input Set-Up 0.5 0.6 0.7 0.8 ns tHD Flip-Flop Data Input Hold 0.0 0.0 0.0 0.0 ns tWASYN Asynchronous Pulse Width 1.4 1.6 1.8 2.1 ns Input Module Propagation Delays tINYH Input Data Pad-to-Y HIGH 1.5 1.7 1.9 2.2 ns tINYL Input Data Pad-to-Y LOW 1.5 1.7 1.9 2.2 ns Predicted Input Routing Delays2 tIRD1 FO = 1 Routing Delay 0.3 0.4 0.4 0.5 ns tIRD2 FO = 2 Routing Delay 0.7 0.8 0.9 1.0 ns tIRD3 FO = 3 Routing Delay 1.0 1.2 1.4 1.6 ns tIRD4 FO = 4 Routing Delay 1.4 1.6 1.8 2.1 ns tIRD8 FO = 8 Routing Delay 2.7 3.1 3.5 4.1 ns tIRD12 FO = 12 Routing Delay 4.0 4.7 5.3 6.2 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF. v3.2 1-31 SX Family FPGAs Table 1-20 • A54SX32 Timing Characteristics (Continued) (Worst-Case Commercial Conditions, VCCR= 4.75 V, VCCA,VCCI = 3.0 V, TJ = 70°C) '–3' Speed Parameter Description Min. Max. '–2' Speed Min. Max. '–1' Speed Min. Max. 'Std' Speed Min. Max. Units Dedicated (Hardwired) Array Clock Network tHCKH Input LOW to HIGH (pad to R-Cell input) 1.9 2.1 2.4 2.8 ns tHCKL Input HIGH to LOW (pad to R-Cell input) 1.9 2.1 2.4 2.8 ns tHPWH Minimum Pulse Width HIGH 1.4 1.6 1.8 2.1 ns tHPWL Minimum Pulse Width LOW 1.4 1.6 1.8 2.1 ns tHCKSW Maximum Skew tHP Minimum Period fHMAX Maximum Frequency 0.3 2.7 0.4 3.1 0.4 3.6 0.5 4.2 ns ns 350 320 280 240 MHz Routed Array Clock Networks tRCKH Input LOW to HIGH (light load) (pad to R-Cell input) 2.4 2.7 3.0 3.5 ns tRCKL Input HIGH to LOW (light load) (pad to R-Cell input) 2.4 2.7 3.1 3.6 ns tRCKH Input LOW to HIGH (50% load) (pad to R-Cell input) 2.7 3.0 3.5 4.1 ns tRCKL Input HIGH to LOW (50% load) (pad to R-Cell input) 2.7 3.1 3.6 4.2 ns tRCKH Input LOW to HIGH (100% load) (pad to R-Cell input) 2.7 3.1 3.5 4.1 ns tRCKL Input HIGH to LOW (100% load) (pad to R-Cell input) 2.8 3.2 3.6 4.3 ns tRPWH Min. Pulse Width HIGH 2.1 2.4 2.7 3.2 ns tRPWL Min. Pulse Width LOW 2.1 2.4 2.7 3.2 ns tRCKSW Maximum Skew (light load) 0.85 0.98 1.1 1.3 ns tRCKSW Maximum Skew (50% load) 1.23 1.4 1.6 1.9 ns tRCKSW Maximum Skew (100% load) 1.30 1.5 1.7 2.0 ns TTL Output Module Timing3 tDLH Data-to-Pad LOW to HIGH 1.6 1.9 2.1 2.5 ns tDHL Data-to-Pad HIGH to LOW 1.6 1.9 2.1 2.5 ns tENZL Enable-to-Pad, Z to L 2.1 2.4 2.8 3.2 ns tENZH Enable-to-Pad, Z to H 2.3 2.7 3.1 3.6 ns tENLZ Enable-to-Pad, L to Z 1.4 1.7 1.9 2.2 ns tENHZ Enable-to-Pad, H to Z 1.3 1.5 1.7 2.0 ns Note: 1. For dual-module macros, use tPD + tRD1 + tPDn, tRCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate. 2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is based on actual routing delay measurements performed on the device prior to shipment. 3. Delays based on 35 pF loading, except tENZL and tENZH. For tENZL and tENZH the loading is 5 pF. 1 -3 2 v3.2 SX Family FPGAs Pin Description CLKA/B Clock A and B TCK Test Clock These pins are 3.3 V / 5.0 V PCI/TTL clock inputs for clock distribution networks. The clock input is buffered prior to clocking the R-cells. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. (For A54SX72A, these clocks can be configured as bidirectional.) Test clock input for diagnostic probe and device programming. In flexible mode, TCK becomes active when the TMS pin is set LOW (refer to Table 1-2 on page 1-6). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. GND TDI Ground LOW supply voltage. HCLK Serial input for boundary scan testing and diagnostic probe. In flexible mode, TDI is active when the TMS pin is set LOW (refer to Table 1-2 on page 1-6). This pin functions as an I/O when the boundary scan state machine reaches the "logic reset" state. Dedicated (hardwired) Array Clock This pin is the 3.3 V / 5.0 V PCI/TTL clock input for sequential modules. This input is directly wired to each R-cell and offers clock speeds independent of the number of R-cells being driven. If not used, this pin must be set LOW or HIGH on the board. It must not be left floating. I/O TDO Input/Output TMS No Connection Probe A The Probe A pin is used to output data from any userdefined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB, I/O Test Mode Select The TMS pin controls the use of the IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). In flexible mode when the TMS pin is set LOW, the TCK, TDI, and TDO pins are boundary scan pins (refer to Table 1-2 on page 1-6). Once the boundary scan pins are in test mode, they will remain in that mode until the internal boundary scan state machine reaches the "logic reset" state. At this point, the boundary scan pins will be released and will function as regular I/O pins. The "logic reset" state is reached 5 TCK cycles after the TMS pin is set HIGH. In dedicated test mode, TMS functions as specified in the IEEE 1149.1 specifications. This pin is not connected to circuitry within the device. PRA, I/O Test Data Output Serial output for boundary scan testing. In flexible mode, TDO is active when the TMS pin is set LOW (refer to Table 1-2 on page 1-6). This pin functions as an I/O when the boundary scan state machine reaches the “logic reset” state. The I/O pin functions as an input, output, tristate, or bidirectional buffer. Based on certain configurations, input and output levels are compatible with standard TTL, LVTTL, 3.3 V PCI or 5.0 V PCI specifications. Unused I/O pins are automatically tristated by the Designer Series software. NC Test Data Input VCCI Supply Voltage Supply voltage for I/Os. See Table 1-1 on page 1-5. Probe B VCCA The Probe B pin is used to output data from any node within the device. This diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when verification has been completed. The pin’s probe capabilities can be permanently disabled to protect programmed design confidentiality. Supply Voltage Supply voltage for Array. See Table 1-1 on page 1-5. VCCR Supply Voltage Supply voltage for input tolerance (required for internal biasing). See Table 1-1 on page 1-5. v3.2 1-33 54SX Family FPGAs Package Pin Assignments 84-Pin PLCC 1 84 84-Pin PLCC Figure 2-1 • 84-Pin PLCC (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v3.2 2-1 54SX Family FPGAs 84-Pin PLCC 84-Pin PLCC 2 -2 84-Pin PLCC Pin Number A54SX08 Function Pin Number A54SX08 Function Pin Number A54SX08 Function 1 VCCR 36 I/O 71 I/O 2 GND 37 I/O 72 I/O 3 VCCA 38 I/O 73 I/O 4 PRA, I/O 39 I/O 74 I/O 5 I/O 40 PRB, I/O 75 I/O 6 I/O 41 VCCA 76 I/O 7 VCCI 42 GND 77 I/O 8 I/O 43 VCCR 78 I/O 9 I/O 44 I/O 79 I/O 10 I/O 45 HCLK 80 I/O 11 TCK, I/O 46 I/O 81 I/O 12 TDI, I/O 47 I/O 82 I/O 13 I/O 48 I/O 83 CLKA 14 I/O 49 I/O 84 CLKB 15 I/O 50 I/O 16 TMS 51 I/O 17 I/O 52 TDO, I/O 18 I/O 53 I/O 19 I/O 54 I/O 20 I/O 55 I/O 21 I/O 56 I/O 22 I/O 57 I/O 23 I/O 58 I/O 24 I/O 59 VCCA 25 I/O 60 VCCI 26 I/O 61 GND 27 GND 62 I/O 28 VCCI 63 I/O 29 I/O 64 I/O 30 I/O 65 I/O 31 I/O 66 I/O 32 I/O 67 I/O 33 I/O 68 VCCA 34 I/O 69 GND 35 I/O 70 I/O v3.2 54SX Family FPGAs 208-Pin PQFP 208 1 208-Pin PQFP Figure 2-2 • 208-Pin PQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v3.2 2-3 54SX Family FPGAs 208-Pin PQFP 208-Pin PQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function GND 37 I/O I/O I/O TDI, I/O TDI, I/O 38 I/O I/O I/O I/O I/O I/O 39 NC I/O I/O 4 NC I/O I/O 40 VCCI VCCI VCCI 5 I/O I/O I/O 41 VCCA VCCA VCCA 6 NC I/O I/O 42 I/O I/O I/O 7 I/O I/O I/O 43 I/O I/O I/O 8 I/O I/O I/O 44 I/O I/O I/O 9 I/O I/O I/O 45 I/O I/O I/O 10 I/O I/O I/O 46 I/O I/O I/O 11 TMS TMS TMS 47 I/O I/O I/O 12 VCCI VCCI VCCI 48 NC I/O I/O 13 I/O I/O I/O 49 I/O I/O I/O 14 NC I/O I/O 50 NC I/O I/O 15 I/O I/O I/O 51 I/O I/O I/O 16 I/O I/O I/O 52 GND GND GND 17 NC I/O I/O 53 I/O I/O I/O 18 I/O I/O I/O 54 I/O I/O I/O 19 I/O I/O I/O 55 I/O I/O I/O 20 NC I/O I/O 56 I/O I/O I/O 21 I/O I/O I/O 57 I/O I/O I/O 22 I/O I/O I/O 58 I/O I/O I/O 23 NC I/O I/O 59 I/O I/O I/O 24 I/O I/O I/O 60 VCCI VCCI VCCI 25 VCCR VCCR VCCR 61 NC I/O I/O 26 GND GND GND 62 I/O I/O I/O 27 VCCA VCCA VCCA 63 I/O I/O I/O 28 GND GND GND 64 NC I/O I/O 29 I/O I/O I/O 65* I/O I/O NC* 30 I/O I/O I/O 66 I/O I/O I/O 31 NC I/O I/O 67 NC I/O I/O 32 I/O I/O I/O 68 I/O I/O I/O 33 I/O I/O I/O 69 I/O I/O I/O 34 I/O I/O I/O 70 NC I/O I/O 35 NC I/O I/O 71 I/O I/O I/O 36 I/O I/O I/O 72 I/O I/O I/O Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 1 GND GND 2 TDI, I/O 3 Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC). 2 -4 v3.2 54SX Family FPGAs 208-Pin PQFP 208-Pin PQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function I/O 109 I/O I/O I/O I/O I/O 110 I/O I/O I/O NC I/O I/O 111 I/O I/O I/O 76 PRB, I/O PRB, I/O PRB, I/O 112 I/O I/O I/O 77 GND GND GND 113 I/O I/O I/O 78 VCCA VCCA VCCA 114 VCCA VCCA VCCA 79 GND GND GND 115 VCCI VCCI VCCI 80 VCCR VCCR VCCR 116 NC I/O I/O 81 I/O I/O I/O 117 I/O I/O I/O 82 HCLK HCLK HCLK 118 I/O I/O I/O 83 I/O I/O I/O 119 NC I/O I/O 84 I/O I/O I/O 120 I/O I/O I/O 85 NC I/O I/O 121 I/O I/O I/O 86 I/O I/O I/O 122 NC I/O I/O 87 I/O I/O I/O 123 I/O I/O I/O 88 NC I/O I/O 124 I/O I/O I/O 89 I/O I/O I/O 125 NC I/O I/O 90 I/O I/O I/O 126 I/O I/O I/O 91 NC I/O I/O 127 I/O I/O I/O 92 I/O I/O I/O 128 I/O I/O I/O 93 I/O I/O I/O 129 GND GND GND 94 NC I/O I/O 130 VCCA VCCA VCCA 95 I/O I/O I/O 131 GND GND GND 96 I/O I/O I/O 132 VCCR VCCR VCCR 97 NC I/O I/O 133 I/O I/O I/O 98 VCCI VCCI VCCI 134 I/O I/O I/O 99 I/O I/O I/O 135 NC I/O I/O 100 I/O I/O I/O 136 I/O I/O I/O 101 I/O I/O I/O 137 I/O I/O I/O 102 I/O I/O I/O 138 NC I/O I/O 103 TDO, I/O TDO, I/O TDO, I/O 139 I/O I/O I/O 104 I/O I/O I/O 140 I/O I/O I/O 105 GND GND GND 141 NC I/O I/O 106 NC I/O I/O 142 I/O I/O I/O 107 I/O I/O I/O 143 NC I/O I/O 108 NC I/O I/O 144 I/O I/O I/O Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 73 NC I/O 74 I/O 75 Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC). v3.2 2-5 54SX Family FPGAs 208-Pin PQFP 208-Pin PQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 145 VCCA VCCA VCCA 181 CLKB CLKB CLKB 146 GND GND GND 182 VCCR VCCR VCCR 147 I/O I/O I/O 183 GND GND GND 148 VCCI VCCI VCCI 184 VCCA VCCA VCCA 149 I/O I/O I/O 185 GND GND GND 150 I/O I/O I/O 186 PRA, I/O PRA, I/O PRA, I/O 151 I/O I/O I/O 187 I/O I/O I/O 152 I/O I/O I/O 188 I/O I/O I/O 153 I/O I/O I/O 189 NC I/O I/O 154 I/O I/O I/O 190 I/O I/O I/O 155 NC I/O I/O 191 I/O I/O I/O 156 NC I/O I/O 192 NC I/O I/O 157 GND GND GND 193 I/O I/O I/O 158 I/O I/O I/O 194 I/O I/O I/O 159 I/O I/O I/O 195 NC I/O I/O 160 I/O I/O I/O 196 I/O I/O I/O 161 I/O I/O I/O 197 I/O I/O I/O 162 I/O I/O I/O 198 NC I/O I/O 163 I/O I/O I/O 199 I/O I/O I/O 164 VCCI VCCI VCCI 200 I/O I/O I/O 165 I/O I/O I/O 201 VCCI VCCI VCCI 166 I/O I/O I/O 202 NC I/O I/O 167 NC I/O I/O 203 NC I/O I/O 168 I/O I/O I/O 204 I/O I/O I/O 169 I/O I/O I/O 205 NC I/O I/O 170 NC I/O I/O 206 I/O I/O I/O 171 I/O I/O I/O 207 I/O I/O I/O 172 I/O I/O I/O 208 TCK, I/O TCK, I/O TCK, I/O 173 NC I/O I/O 174 I/O I/O I/O 175 I/O I/O I/O 176 NC I/O I/O 177 I/O I/O I/O 178 I/O I/O I/O 179 I/O I/O I/O 180 CLKA CLKA CLKA Note: * Note that Pin 65 in the A54SX32—PQ208 is a no connect (NC). 2 -6 v3.2 54SX Family FPGAs 144-Pin TQFP 144 1 144-Pin TQFP Figure 2-3 • 144-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v3.2 2-7 54SX Family FPGAs 144-Pin TQFP 144-Pin TQFP Pin Number A54SX08 Function A54SX16P Function A54SX32 Function Pin Number A54SX08 Function A54SX16P Function A54SX32 Function 1 GND GND GND 37 I/O I/O I/O 2 TDI, I/O TDI, I/O TDI, I/O 38 I/O I/O I/O 3 I/O I/O I/O 39 I/O I/O I/O 4 I/O I/O I/O 40 I/O I/O I/O 5 I/O I/O I/O 41 I/O I/O I/O 6 I/O I/O I/O 42 I/O I/O I/O 7 I/O I/O I/O 43 I/O I/O I/O 8 I/O I/O I/O 44 VCCI VCCI VCCI 9 TMS TMS TMS 45 I/O I/O I/O 10 VCCI VCCI VCCI 46 I/O I/O I/O 11 GND GND GND 47 I/O I/O I/O 12 I/O I/O I/O 48 I/O I/O I/O 13 I/O I/O I/O 49 I/O I/O I/O 14 I/O I/O I/O 50 I/O I/O I/O 15 I/O I/O I/O 51 I/O I/O I/O 16 I/O I/O I/O 52 I/O I/O I/O 17 I/O I/O I/O 53 I/O I/O I/O 18 I/O I/O I/O 54 PRB, I/O PRB, I/O PRB, I/O 19 VCCR VCCR VCCR 55 I/O I/O I/O 20 VCCA VCCA VCCA 56 VCCA VCCA VCCA 21 I/O I/O I/O 57 GND GND GND 22 I/O I/O I/O 58 VCCR VCCR VCCR 23 I/O I/O I/O 59 I/O I/O I/O 24 I/O I/O I/O 60 HCLK HCLK HCLK 25 I/O I/O I/O 61 I/O I/O I/O 26 I/O I/O I/O 62 I/O I/O I/O 27 I/O I/O I/O 63 I/O I/O I/O 28 GND GND GND 64 I/O I/O I/O 29 VCCI VCCI VCCI 65 I/O I/O I/O 30 VCCA VCCA VCCA 66 I/O I/O I/O 31 I/O I/O I/O 67 I/O I/O I/O 32 I/O I/O I/O 68 VCCI VCCI VCCI 33 I/O I/O I/O 69 I/O I/O I/O 34 I/O I/O I/O 70 I/O I/O I/O 35 I/O I/O I/O 71 TDO, I/O TDO, I/O TDO, I/O 36 GND GND GND 72 I/O I/O I/O 2 -8 v3.2 54SX Family FPGAs 144-Pin TQFP 144-Pin TQFP Pin Number A54SX08 Function A54SX16P Function A54SX32 Function Pin Number A54SX08 Function A54SX16P Function A54SX32 Function 73 GND GND GND 109 GND GND GND 74 I/O I/O I/O 110 I/O I/O I/O 75 I/O I/O I/O 111 I/O I/O I/O 76 I/O I/O I/O 112 I/O I/O I/O 77 I/O I/O I/O 113 I/O I/O I/O 78 I/O I/O I/O 114 I/O I/O I/O 79 VCCA VCCA VCCA 115 VCCI VCCI VCCI 80 VCCI VCCI VCCI 116 I/O I/O I/O 81 GND GND GND 117 I/O I/O I/O 82 I/O I/O I/O 118 I/O I/O I/O 83 I/O I/O I/O 119 I/O I/O I/O 84 I/O I/O I/O 120 I/O I/O I/O 85 I/O I/O I/O 121 I/O I/O I/O 86 I/O I/O I/O 122 I/O I/O I/O 87 I/O I/O I/O 123 I/O I/O I/O 88 I/O I/O I/O 124 I/O I/O I/O 89 VCCA VCCA VCCA 125 CLKA CLKA CLKA 90 VCCR VCCR VCCR 126 CLKB CLKB CLKB 91 I/O I/O I/O 127 VCCR VCCR VCCR 92 I/O I/O I/O 128 GND GND GND 93 I/O I/O I/O 129 VCCA VCCA VCCA 94 I/O I/O I/O 130 I/O I/O I/O 95 I/O I/O I/O 131 PRA, I/O PRA, I/O PRA, I/O 96 I/O I/O I/O 132 I/O I/O I/O 97 I/O I/O I/O 133 I/O I/O I/O 98 VCCA VCCA VCCA 134 I/O I/O I/O 99 GND GND GND 135 I/O I/O I/O 100 I/O I/O I/O 136 I/O I/O I/O 101 GND GND GND 137 I/O I/O I/O 102 VCCI VCCI VCCI 138 I/O I/O I/O 103 I/O I/O I/O 139 I/O I/O I/O 104 I/O I/O I/O 140 VCCI VCCI VCCI 105 I/O I/O I/O 141 I/O I/O I/O 106 I/O I/O I/O 142 I/O I/O I/O 107 I/O I/O I/O 143 I/O I/O I/O 108 I/O I/O I/O 144 TCK, I/O TCK, I/O TCK, I/O v3.2 2-9 54SX Family FPGAs 176-Pin TQFP 176 1 176-Pin TQFP Figure 2-4 • 176-Pin TQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -1 0 v3.2 54SX Family FPGAs 176-Pin TQFP 176-Pin TQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function GND 35 I/O I/O I/O TDI, I/O TDI, I/O 36 I/O I/O I/O NC I/O I/O 37 I/O I/O I/O 4 I/O I/O I/O 38 I/O I/O I/O 5 I/O I/O I/O 39 I/O I/O I/O 6 I/O I/O I/O 40 NC I/O I/O 7 I/O I/O I/O 41 I/O I/O I/O 8 I/O I/O I/O 42 NC I/O I/O 9 I/O I/O I/O 43 I/O I/O I/O 10 TMS TMS TMS 44 GND GND GND 11 VCCI VCCI VCCI 45 I/O I/O I/O 12 NC I/O I/O 46 I/O I/O I/O 13 I/O I/O I/O 47 I/O I/O I/O 14 I/O I/O I/O 48 I/O I/O I/O 15 I/O I/O I/O 49 I/O I/O I/O 16 I/O I/O I/O 50 I/O I/O I/O 17 I/O I/O I/O 51 I/O I/O I/O 18 I/O I/O I/O 52 VCCI VCCI VCCI 19 I/O I/O I/O 53 I/O I/O I/O 20 I/O I/O I/O 54 NC I/O I/O 21 GND GND GND 55 I/O I/O I/O 22 VCCA VCCA VCCA 56 I/O I/O I/O 23 GND GND GND 57 NC I/O I/O 24 I/O I/O I/O 58 I/O I/O I/O 25 I/O I/O I/O 59 I/O I/O I/O 26 I/O I/O I/O 60 I/O I/O I/O 27 I/O I/O I/O 61 I/O I/O I/O 28 I/O I/O I/O 62 I/O I/O I/O 29 I/O I/O I/O 63 I/O I/O I/O 30 I/O I/O I/O 64 PRB, I/O PRB, I/O PRB, I/O 31 I/O I/O I/O 65 GND GND GND 32 VCCI VCCI VCCI 66 VCCA VCCA VCCA 33 VCCA VCCA VCCA 67 VCCR VCCR VCCR 34 I/O I/O I/O 68 I/O I/O I/O Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 1 GND GND 2 TDI, I/O 3 v3.2 2-11 54SX Family FPGAs 176-Pin TQFP 176-Pin TQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 69 HCLK HCLK 70 I/O 71 2 -1 2 Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function HCLK 103 I/O I/O I/O I/O I/O 104 I/O I/O I/O I/O I/O I/O 105 I/O I/O I/O 72 I/O I/O I/O 106 I/O I/O I/O 73 I/O I/O I/O 107 I/O I/O I/O 74 I/O I/O I/O 108 GND GND GND 75 I/O I/O I/O 109 VCCA VCCA VCCA 76 I/O I/O I/O 110 GND GND GND 77 I/O I/O I/O 111 I/O I/O I/O 78 I/O I/O I/O 112 I/O I/O I/O 79 NC I/O I/O 113 I/O I/O I/O 80 I/O I/O I/O 114 I/O I/O I/O 81 NC I/O I/O 115 I/O I/O I/O 82 VCCI VCCI VCCI 116 I/O I/O I/O 83 I/O I/O I/O 117 I/O I/O I/O 84 I/O I/O I/O 118 NC I/O I/O 85 I/O I/O I/O 119 I/O I/O I/O 86 I/O I/O I/O 120 NC I/O I/O 87 TDO, I/O TDO, I/O TDO, I/O 121 NC I/O I/O 88 I/O I/O I/O 122 VCCA VCCA VCCA 89 GND GND GND 123 GND GND GND 90 NC I/O I/O 124 VCCI VCCI VCCI 91 NC I/O I/O 125 I/O I/O I/O 92 I/O I/O I/O 126 I/O I/O I/O 93 I/O I/O I/O 127 I/O I/O I/O 94 I/O I/O I/O 128 I/O I/O I/O 95 I/O I/O I/O 129 I/O I/O I/O 96 I/O I/O I/O 130 I/O I/O I/O 97 I/O I/O I/O 131 NC I/O I/O 98 VCCA VCCA VCCA 132 NC I/O I/O 99 VCCI VCCI VCCI 133 GND GND GND 100 I/O I/O I/O 134 I/O I/O I/O 101 I/O I/O I/O 135 I/O I/O I/O 102 I/O I/O I/O 136 I/O I/O I/O v3.2 54SX Family FPGAs 176-Pin TQFP 176-Pin TQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function 137 I/O I/O 138 I/O 139 Pin Number A54SX08 Function A54SX16, A54SX16P Function A54SX32 Function I/O 157 PRA, I/O PRA, I/O PRA, I/O I/O I/O 158 I/O I/O I/O I/O I/O I/O 159 I/O I/O I/O 140 VCCI VCCI VCCI 160 I/O I/O I/O 141 I/O I/O I/O 161 I/O I/O I/O 142 I/O I/O I/O 162 I/O I/O I/O 143 I/O I/O I/O 163 I/O I/O I/O 144 I/O I/O I/O 164 I/O I/O I/O 145 I/O I/O I/O 165 I/O I/O I/O 146 I/O I/O I/O 166 I/O I/O I/O 147 I/O I/O I/O 167 I/O I/O I/O 148 I/O I/O I/O 168 NC I/O I/O 149 I/O I/O I/O 169 VCCI VCCI VCCI 150 I/O I/O I/O 170 I/O I/O I/O 151 I/O I/O I/O 171 NC I/O I/O 152 CLKA CLKA CLKA 172 NC I/O I/O 153 CLKB CLKB CLKB 173 NC I/O I/O 154 VCCR VCCR VCCR 174 I/O I/O I/O 155 GND GND GND 175 I/O I/O I/O 156 VCCA VCCA VCCA 176 TCK, I/O TCK, I/O TCK, I/O v3.2 2-13 54SX Family FPGAs 100-Pin VQFP 100 1 100-Pin VQFP Figure 2-5 • 100-Pin VQFP (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -1 4 v3.2 54SX Family FPGAs 100-Pin VQFP 100-Pin VQFP 100-Pin VQFP Pin Number A54SX08 Function A54SX16, A54SX16P Function Pin Number A54SX08 Function A54SX16, A54SX16P Function Pin Number A54SX08 Function A54SX16, A54SX16P Function 1 GND GND 35 VCCA VCCA 69 GND GND 2 TDI, I/O TDI, I/O 36 GND GND 70 I/O I/O 3 I/O I/O 37 VCCR VCCR 71 I/O I/O 4 I/O I/O 38 I/O I/O 72 I/O I/O 5 I/O I/O 39 HCLK HCLK 73 I/O I/O 6 I/O I/O 40 I/O I/O 74 I/O I/O 7 TMS TMS 41 I/O I/O 75 I/O I/O 8 VCCI VCCI 42 I/O I/O 76 I/O I/O 9 GND GND 43 I/O I/O 77 I/O I/O 10 I/O I/O 44 VCCI VCCI 78 I/O I/O 11 I/O I/O 45 I/O I/O 79 I/O I/O 12 I/O I/O 46 I/O I/O 80 I/O I/O 13 I/O I/O 47 I/O I/O 81 I/O I/O 14 I/O I/O 48 I/O I/O 82 VCCI VCCI 15 I/O I/O 49 TDO, I/O TDO, I/O 83 I/O I/O 16 I/O I/O 50 I/O I/O 84 I/O I/O 17 I/O I/O 51 GND GND 85 I/O I/O 18 I/O I/O 52 I/O I/O 86 I/O I/O 19 I/O I/O 53 I/O I/O 87 CLKA CLKA 20 VCCI VCCI 54 I/O I/O 88 CLKB CLKB 21 I/O I/O 55 I/O I/O 89 VCCR VCCR 22 I/O I/O 56 I/O I/O 90 VCCA VCCA 23 I/O I/O 57 VCCA VCCA 91 GND GND 24 I/O I/O 58 VCCI VCCI 92 PRA, I/O PRA, I/O 25 I/O I/O 59 I/O I/O 93 I/O I/O 26 I/O I/O 60 I/O I/O 94 I/O I/O 27 I/O I/O 61 I/O I/O 95 I/O I/O 28 I/O I/O 62 I/O I/O 96 I/O I/O 29 I/O I/O 63 I/O I/O 97 I/O I/O 30 I/O I/O 64 I/O I/O 98 I/O I/O 31 I/O I/O 65 I/O I/O 99 I/O I/O 32 I/O I/O 66 I/O I/O 100 TCK, I/O TCK, I/O 33 I/O I/O 67 VCCA VCCA 34 PRB, I/O PRB, I/O 68 GND GND v3.2 2-15 54SX Family FPGAs 313-Pin PBGA 1 A B C A B C D D E F G E F G H J H J K L K L M N P R M N P R T U T U V W V W Y AA AB AC Y AA AB AC AD AE AD AE 1 Figure 2-6 • 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 313-Pin PBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. 2 -1 6 v3.2 54SX Family FPGAs 313-Pin PBGA 313-Pin PBGA 313-Pin PBGA 313-Pin PBGA Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function A1 GND AC5 I/O B10 I/O E15 I/O A3 NC AC7 I/O B12 I/O E17 I/O A5 I/O AC9 I/O B14 I/O E19 I/O A7 I/O AC11 I/O B16 I/O E21 I/O A9 I/O AC13 VCCR B18 I/O E23 I/O A11 I/O AC15 I/O B20 I/O E25 I/O A13 VCCR AC17 I/O B22 I/O F2 I/O A15 I/O AC19 I/O B24 I/O F4 I/O A17 I/O AC21 I/O C1 TDI, I/O F6 NC A19 I/O AC23 I/O C3 I/O F8 I/O A21 I/O AC25 NC C5 NC F10 NC A23 NC AD2 GND C7 I/O F12 I/O A25 GND AD4 I/O C9 I/O F14 I/O AA1 I/O AD6 VCCI C11 I/O F16 NC AA3 I/O AD8 I/O C13 VCCI F18 I/O AA5 NC AD10 I/O C15 I/O F20 I/O AA7 I/O AD12 PRB, I/O C17 I/O F22 I/O AA9 NC AD14 I/O C19 VCCI F24 I/O AA11 I/O AD16 I/O C21 I/O G1 I/O AA13 I/O AD18 I/O C23 I/O G3 TMS AA15 I/O AD20 I/O C25 NC G5 I/O AA17 I/O AD22 NC D2 I/O G7 I/O AA19 I/O AD24 I/O D4 NC G9 VCCI AA21 I/O AE1 NC D6 I/O G11 I/O AA23 NC AE3 I/O D8 I/O G13 CLKB AA25 I/O AE5 I/O D10 I/O G15 I/O AB2 NC AE7 I/O D12 I/O G17 I/O AB4 NC AE9 I/O D14 I/O G19 I/O AB6 I/O AE11 I/O D16 I/O G21 I/O AB8 I/O AE13 VCCA D18 I/O G23 I/O AB10 I/O AE15 I/O D20 I/O G25 I/O AB12 I/O AE17 I/O D22 I/O H2 I/O AB14 I/O AE19 I/O D24 NC H4 I/O AB16 I/O AE21 I/O E1 I/O H6 I/O AB18 VCCI AE23 TDO, I/O E3 NC H8 I/O AB20 NC AE25 GND E5 I/O H10 I/O AB22 I/O B2 TCK, I/O E7 I/O H12 PRA, I/O AB24 I/O B4 I/O E9 I/O H14 I/O AC1 I/O B6 I/O E11 I/O H16 I/O AC3 I/O B8 I/O E13 VCCA H18 NC v3.2 2-17 54SX Family FPGAs 313-Pin PBGA 313-Pin PBGA 313-Pin PBGA 313-Pin PBGA Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function H20 I/O L25 I/O R5 I/O V10 I/O H22 VCCI M2 I/O R7 I/O V12 I/O H24 I/O M4 I/O R9 I/O V14 I/O J1 I/O M6 I/O R11 I/O V16 NC J3 I/O M8 I/O R13 GND V18 I/O J5 I/O M10 I/O R15 I/O V20 I/O J7 NC M12 GND R17 I/O V22 VCCA J9 I/O M14 GND R19 I/O V24 VCCI J11 I/O M16 VCCI R21 I/O W1 I/O J13 CLKA M18 I/O R23 I/O W3 I/O J15 I/O M20 I/O R25 I/O W5 I/O J17 I/O M22 I/O T2 I/O W7 NC J19 I/O M24 I/O T4 I/O W9 I/O J21 GND N1 I/O T6 I/O W11 I/O J23 I/O N3 VCCA T8 I/O W13 VCCI J25 I/O N5 VCCR T10 I/O W15 I/O K2 I/O N7 I/O T12 I/O W17 I/O K4 I/O N9 VCCI T14 HCLK W19 I/O K6 I/O N11 GND T16 I/O W21 I/O K8 VCCI N13 GND T18 I/O W23 I/O K10 I/O N15 GND T20 I/O W25 I/O K12 I/O N17 I/O T22 I/O Y2 I/O K14 I/O N19 I/O T24 I/O Y4 I/O K16 I/O N21 I/O U1 I/O Y6 I/O K18 I/O N23 VCCR U3 I/O Y8 I/O K20 VCCA N25 VCCA U5 VCCI Y10 I/O K22 I/O P2 I/O U7 I/O Y12 I/O K24 I/O P4 I/O U9 I/O Y14 I/O L1 I/O P6 I/O U11 I/O Y16 I/O L3 I/O P8 I/O U13 I/O Y18 I/O L5 I/O P10 I/O U15 I/O Y20 NC L7 I/O P12 GND U17 I/O Y22 I/O L9 I/O P14 GND U19 I/O Y24 NC L11 I/O P16 I/O U21 I/O L13 GND P18 I/O U23 I/O L15 I/O P20 NC U25 I/O L17 I/O P22 I/O V2 VCCA L19 I/O P24 I/O V4 I/O L21 I/O R1 I/O V6 I/O L23 I/O R3 I/O V8 I/O 2 -1 8 v3.2 54SX Family FPGAs 329-Pin PBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 A B C D E F G H J K L M N P R T U V W Y AA AB AC Figure 2-7 • 329-Pin PBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v3.2 2-19 54SX Family FPGAs 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function A1 GND AA13 I/O AC2 VCCI B14 I/O A2 GND AA14 I/O AC3 NC B15 I/O A3 VCCI AA15 I/O AC4 I/O B16 I/O A4 NC AA16 I/O AC5 I/O B17 I/O A5 I/O AA17 I/O AC6 I/O B18 I/O A6 I/O AA18 I/O AC7 I/O B19 I/O A7 VCCI AA19 I/O AC8 I/O B20 I/O A8 NC AA20 TDO, I/O AC9 VCCI B21 I/O A9 I/O AA21 VCCI AC10 I/O B22 GND A10 I/O AA22 I/O AC11 I/O B23 VCCI A11 I/O AA23 VCCI AC12 I/O C1 NC A12 I/O AB1 I/O AC13 I/O C2 TDI, I/O A13 CLKB AB2 GND AC14 I/O C3 GND A14 I/O AB3 I/O AC15 NC C4 I/O A15 I/O AB4 I/O AC16 I/O C5 I/O A16 I/O AB5 I/O AC17 I/O C6 I/O A17 I/O AB6 I/O AC18 I/O C7 I/O A18 I/O AB7 I/O AC19 I/O C8 I/O A19 I/O AB8 I/O AC20 I/O C9 I/O A20 I/O AB9 I/O AC21 NC C10 I/O A21 NC AB10 I/O AC22 VCCI C11 I/O A22 VCCI AB11 PRB, I/O AC23 GND C12 I/O A23 GND AB12 I/O B1 VCCI C13 I/O AA1 VCCI AB13 HCLK B2 GND C14 I/O AA2 I/O AB14 I/O B3 I/O C15 I/O AA3 GND AB15 I/O B4 I/O C16 I/O AA4 I/O AB16 I/O B5 I/O C17 I/O AA5 I/O AB17 I/O B6 I/O C18 I/O AA6 I/O AB18 I/O B7 I/O C19 I/O AA7 I/O AB19 I/O B8 I/O C20 I/O AA8 I/O AB20 I/O B9 I/O C21 VCCI AA9 I/O AB21 I/O B10 I/O C22 GND AA10 I/O AB22 GND B11 I/O C23 NC AA11 I/O AB23 I/O B12 PRA, I/O D1 I/O AA12 I/O AC1 GND B13 CLKA D2 I/O 2 -2 0 v3.2 54SX Family FPGAs 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function D3 I/O F22 I/O K20 I/O N11 GND D4 TCK, I/O F23 I/O K21 I/O N12 GND D5 I/O G1 I/O K22 I/O N13 GND D6 I/O G2 I/O K23 I/O N14 GND D7 I/O G3 I/O L1 I/O N20 NC D8 I/O G4 I/O L2 I/O N21 I/O D9 I/O G20 I/O L3 I/O N22 I/O D10 I/O G21 I/O L4 VCCR N23 I/O D11 VCCA G22 I/O L10 GND P1 I/O D12 VCCR G23 GND L11 GND P2 I/O D13 I/O H1 I/O L12 GND P3 I/O D14 I/O H2 I/O L13 GND P4 I/O D15 I/O H3 I/O L14 GND P10 GND D16 I/O H4 I/O L20 VCCR P11 GND D17 I/O H20 VCCA L21 I/O P12 GND D18 I/O H21 I/O L22 I/O P13 GND D19 I/O H22 I/O L23 NC P14 GND D20 I/O H23 I/O M1 I/O P20 I/O D21 I/O J1 NC M2 I/O P21 I/O D22 I/O J2 I/O M3 I/O P22 I/O D23 I/O J3 I/O M4 VCCA P23 I/O E1 VCCI J4 I/O M10 GND R1 I/O E2 I/O J20 I/O M11 GND R2 I/O E3 I/O J21 I/O M12 GND R3 I/O E4 I/O J22 I/O M13 GND R4 I/O E20 I/O J23 I/O M14 GND R20 I/O E21 I/O K1 I/O M20 VCCA R21 I/O E22 I/O K2 I/O M21 I/O R22 I/O E23 I/O K3 I/O M22 I/O R23 I/O F1 I/O K4 I/O M23 VCCI T1 I/O F2 TMS K10 GND N1 I/O T2 I/O F3 I/O K11 GND N2 I/O T3 I/O F4 I/O K12 GND N3 I/O T4 I/O F20 I/O K13 GND N4 I/O T20 I/O F21 I/O K14 GND N10 GND T21 I/O v3.2 2-21 54SX Family FPGAs 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA 329-Pin PBGA Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function Pin Number A54SX32 Function T22 I/O V4 I/O W23 NC Y12 VCCA T23 I/O V20 I/O Y1 NC Y13 VCCR U1 I/O V21 I/O Y2 I/O Y14 I/O U2 I/O V22 I/O Y3 I/O Y15 I/O U3 VCCA V23 I/O Y4 GND Y16 I/O U4 I/O W1 I/O Y5 I/O Y17 I/O U20 I/O W2 I/O Y6 I/O Y18 I/O U21 VCCA W3 I/O Y7 I/O Y19 I/O U22 I/O W4 I/O Y8 I/O Y20 GND U23 I/O W20 I/O Y9 I/O Y21 I/O V1 VCCI W21 I/O Y10 I/O Y22 I/O V2 I/O W22 I/O Y11 I/O Y23 I/O V3 I/O 2 -2 2 v3.2 54SX Family FPGAs 144-Pin FBGA 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M Figure 2-8 • 144-Pin FBGA (Top View) Note For Package Manufacturing and Environmental information, visit the Package Resource center at http://www.actel.com/products/rescenter/package/index.html. v3.2 2-23 54SX Family FPGAs 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA 144-Pin FBGA Pin Number A54SX08 Function Pin Number A54SX08 Function Pin Number A54SX08 Function Pin Number A54SX08 Function A1 I/O D1 I/O G1 I/O K1 I/O A2 I/O D2 VCCI G2 GND K2 I/O A3 I/O D3 TDI, I/O G3 I/O K3 I/O A4 I/O D4 I/O G4 I/O K4 I/O A5 VCCA D5 I/O G5 GND K5 I/O A6 GND D6 I/O G6 GND K6 I/O A7 CLKA D7 I/O G7 GND K7 GND A8 I/O D8 I/O G8 VCCI K8 I/O A9 I/O D9 I/O G9 I/O K9 I/O A10 I/O D10 I/O G10 I/O K10 GND A11 I/O D11 I/O G11 I/O K11 I/O A12 I/O D12 I/O G12 I/O K12 I/O B1 I/O E1 I/O H1 I/O L1 GND B2 GND E2 I/O H2 I/O L2 I/O B3 I/O E3 I/O H3 I/O L3 I/O B4 I/O E4 I/O H4 I/O L4 I/O B5 I/O E5 TMS H5 VCCA L5 I/O B6 I/O E6 VCCI H6 VCCA L6 I/O B7 CLKB E7 VCCI H7 VCCI L7 HCLK B8 I/O E8 VCCI H8 VCCI L8 I/O B9 I/O E9 VCCA H9 VCCA L9 I/O B10 I/O E10 I/O H10 I/O L10 I/O B11 GND E11 GND H11 I/O L11 I/O B12 I/O E12 I/O H12 VCCR L12 I/O C1 I/O F1 I/O J1 I/O M1 I/O C2 I/O F2 I/O J2 I/O M2 I/O C3 TCK, I/O F3 VCCR J3 I/O M3 I/O C4 I/O F4 I/O J4 I/O M4 I/O C5 I/O F5 GND J5 I/O M5 I/O C6 PRA, I/O F6 GND J6 PRB, I/O M6 I/O C7 I/O F7 GND J7 I/O M7 VCCA C8 I/O F8 VCCI J8 I/O M8 I/O C9 I/O F9 I/O J9 I/O M9 I/O C10 I/O F10 GND J10 I/O M10 I/O C11 I/O F11 I/O J11 I/O M11 TDO, I/O C12 I/O F12 I/O J12 VCCA M12 I/O 2 -2 4 v3.2 54SX Family FPGAs Datasheet Information List of Changes The following table lists critical changes that were made in the current version of the document. Previous Version Changes in Current Version (v3.2) v3.1 (June 2003) v3.0.1 Page The "Ordering Information" was updated to include RoHS information. 1-ii The Product Plan was removed since all products have been released. N/A Information concerning the TRST pin in the "Probe Circuit Control Pins" section was removed. 1-6 The "Dedicated Test Mode" section is new. 1-6 The "Programming" section is new. 1-7 A note was added to the "Power-Up Sequencing" table. 1-15 A note was added to the "Power-Down Sequencing" table. The 3.3 V comments were updated for the following devices: A54SX08, A54SX16, A54SX32. 1-15 U11 and U13 were added to the "313-Pin PBGA" table. 2-17 Storage temperature in Table 1-3 was updated. 1-7 Table 1-1 was updated. 1-5 Datasheet Categories In order to provide the latest information to designers, some datasheets are published before data has been fully characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet Supplement." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advanced or production) containing general product information. This brief gives an overview of specific device and family information. Advanced This datasheet version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. Unmarked (production) This datasheet version contains information that is considered to be final. Datasheet Supplement The datasheet supplement gives specific device information for a derivative family that differs from the general family datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and for specifications that do not differ between the two families. International Traffic in Arms Regulations (ITAR) and Export Administration Regulations (EAR) The products described in this datasheet are subject to the International Traffic in Arms Regulations (ITAR) or the Export Administration Regulations (EAR). They may require an approved export license prior to their export. An export can include a release or disclosure to a foreign national inside or outside the United States. v3.2 3-1 Actel and the Actel logo are registered trademarks of Actel Corporation. All other trademarks are the property of their owners. www.actel.com Actel Corporation Actel Europe Ltd. Actel Japan www.jp.actel.com Actel Hong Kong www.actel.com.cn 2061 Stierlin Court Mountain View, CA 94043-4655 USA Phone 650.318.4200 Fax 650.318.4600 Dunlop House, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone +44 (0) 1276 401 450 Fax +44 (0) 1276 401 490 EXOS Ebisu Bldg. 4F 1-24-14 Ebisu Shibuya-ku Tokyo 150 Japan Phone +81.03.3445.7671 Fax +81.03.3445.7668 Suite 2114, Two Pacific Place 88 Queensway, Admiralty Hong Kong Phone +852 2185 6460 Fax +852 2185 6488 5172137-5/6.06