AGL600

Revision 19 IGLOO Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits Low Power • • • • • 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation 5 µW Power Consumption in Flash*Freeze Mode Low Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X†, and LVCMOS 2.5 V / 5.0 V Input† • Differential I/O Standards: LVPECL, LVDS, B-LVDS, and MLVDS (AGL250 and above) • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Hot-Swappable and Cold-Sparing I/Os‡ • Programmable Output Slew Rate† and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the IGLOO Family † • Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) High Capacity • 15K to 1 Million System Gates • Up to 144 Kbits of True Dual-Port SRAM • Up to 300 User I/Os Reprogrammable Flash Technology • • • • • 130-nm, 7-Layer Metal, Flash-Based CMOS Process Live-at-Power-Up (LAPU) Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance Clock Conditioning Circuit (CCC) and PLL In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled IGLOO® devices) via JTAG (IEEE 1532–compliant)† • FlashLock® Designed to Secure FPGA Contents Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit† RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations) • True Dual-Port SRAM (except ×18)† High-Performance Routing Hierarchy • Segmented, Hierarchical Routing and Clock Structure ARM Processor Support in IGLOO FPGAs • M1 IGLOO Devices—Cortex™-M1 Soft Processor Available with or without Debug Advanced I/O • 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above) IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 ARM-Enabled IGLOO Devices1 M1AGL250 M1AGL600 M1AGL1000 System Gates 15,000 30,000 60,000 125,000 250,000 400,000 600,000 1,000,000 Typical Equivalent Macrocells 128 256 512 1,024 2,048 – – – VersaTiles (D-flip-flops) 384 768 1,536 3,072 6,144 9,216 13,824 24,576 Flash*Freeze Mode (typical, µW) 5 5 10 16 24 32 36 53 RAM kbits (1,024 bits) – – 18 36 36 54 108 144 4,608-Bit Blocks – – 4 8 8 12 24 32 FlashROM Kbits (1,024 bits) 1 1 1 1 1 1 1 1 AES-Protected ISP 1 – – Yes Yes Yes Yes Yes Yes Integrated PLL in CCCs 2 – – 1 1 1 1 1 1 VersaNet Globals 3 6 6 18 18 18 18 18 18 I/O Banks 2 2 2 2 4 4 4 4 Maximum User I/Os 49 81 96 133 143 194 235 300 Package Pins UC/CS UC81 CS1212 CS121, CS81, CS1964 CS196 CS281 CS281 CS81 CS196 4 QFN QN68 QN48, QN68, QN132 QN132 QN132 QN132 VQFP VQ100 VQ100 VQ100 VQ100 FBGA FG144 FG144, FG256, FG144, FG256, FG144, FG256, FG144 FG144 FG484 FG484 FG484 Notes: 1. 2. 3. 4. 5. AES is not available for ARM-enabled IGLOO devices. AGL060 in CS121 does not support the PLL. Six chip (main) and twelve quadrant global networks are available for AGL060 and above. The M1AGL250 device does not support this package. The IGLOOe datasheet and IGLOOe FPGA Fabric User’s Guide provide information on higher densities and additional features. † AGL015 and AGL030 devices do not support this feature. September 2011 © 2011 Microsemi Corporation ‡ Supported only by AGL015 and AGL030 devices. I IGLOO Low Power Flash FPGAs I/Os Per Package1 IGLOO Devices ARM-Enabled IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 M1AGL250 I/O Type2 Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs Differential I/O Pairs – – – – – – – – 25 44 53 74 FG484 529 1.0 2.23 Single-Ended I/O 3 Single-Ended I/O 3 Single-Ended I/O 3 Single-Ended I/O 3 – – – – – – – – 97 177 215 300 FG256 289 1.0 1.60 Single-Ended I/O Single-Ended I/O Single-Ended I/O Single-Ended I/O AGL400 AGL600 M1AGL600 AGL1000 M1AGL1000 Package QN48 QN68 UC81 CS81 CS121 VQ100 QN132 CS196 FG144 FG256 CS281 FG4845 5 – 49 – – – – – – – – – – 34 49 66 66 – 77 81 – – – – – – – – – 96 71 80 – 96 – – – – – – – 96 71 84 133 97 – – – – – – 60 – 68 87 4 – – – 7 – 13 194 354 24 – – – – – – – – – – 143 97 178 – 194 – – – – – – – 35 25 38 – 38 – – – – – – – – 97 177 215 235 – – – – – – – – 25 43 53 60 1434 97 – – – Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the IGLOO FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 2. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of singleended user I/Os available is reduced by one. 3. Each used differential I/O pair reduces the number of single-ended I/Os available by two. 4. The M1AGL250 device does not support QN132 or CS196 packages. 5. FG256 and FG484 are footprint-compatible packages. Table 1 • IGLOO FPGAs Package Sizes Dimensions Package Length × Width (mm\mm) Nominal Area (mm2) Pitch (mm) Height (mm) UC81 4×4 16 0.4 0.80 CS81 5×5 25 0.5 0.80 CS121 6×6 36 0.5 0.99 QN48 6×6 36 0.4 0.90 QN68 8×8 64 0.4 0.90 QN132 8×8 64 0.5 0.75 CS196 8×8 64 0.5 1.20 CS281 FG144 VQ100 10 × 10 13 × 13 14 × 14 100 0.5 1.05 169 1.0 1.45 196 0.5 1.00 17 × 17 23 × 23 II R evis i o n 19 IGLOO Low Power Flash FPGAs IGLOO Ordering Information AGL1000 V2 _ FG G 144 Y I Application (Temperature Range) Blank = Commercial (0°C to +70°C Ambient Temperature) I = Industrial (–40°C to +85°C Ambient Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging (some packages also halogen-free) Package Type UC = Micro Chip Scale Package (0.4 mm pitch) CS = Chip Scale Package (0.4 mm and 0.5 mm pitches) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitch) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) FG = Fine Pitch Ball Grid Array (1.0 mm pitch) Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOO Devices AGL015 = 15,000 System Gates AGL030 = 30,000 System Gates AGL060 = 60,000 System Gates AGL125 = 125,000 System Gates AGL250 = 250,000 System Gates AGL400 = 400,000 System Gates AGL600 = 600,000 System Gates AGL1000 = 1,000,000 System Gates IGLOO Devices with Cortex-M1 M1AGL250 = 250,000 System Gates M1AGL600 = 600,000 System Gates M1AGL1000 = 1,000,000 System Gates Note: Marking Information: IGLOO V2 devices do not have V2 marking, but IGLOO V5 devices are marked accordingly. R ev i si o n 1 9 III IGLOO Low Power Flash FPGAs Temperature Grade Offerings AGL015 Package QN48 QN68 UC81 CS81 CS121 VQ100 QN132 CS196 FG144 FG256 CS281 FG484 – C, I – – – – – – – – – – C, I – C, I C, I – C, I C, I – – – – – – – – – C, I C, I C, I – C, I – – – – – – – C, I C, I C, I C, I C, I – – – AGL030 AGL060 AGL125 AGL250 M1AGL250 – – – C, I – C, I C, I C, I C, I – – – – – – – – – – C, I C, I C, I – C, I AGL400 AGL600 AGL1000 M1AGL600 M1AGL1000 – – – – – – – – C, I C, I C, I C, I – – – – – – – – C, I C, I C, I C, I C = Commercial temperature range: 0°C to 70°C ambient temperature. I = Industrial temperature range: –40°C to 85°C ambient temperature. IGLOO Device Status IGLOO Devices AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Status Production Production Production Production Production Production Production Production M1AGL600 M1AGL1000 Production Production M1AGL250 Production M1 IGLOO Devices Status References made to IGLOO devices also apply to ARM-enabled IGLOOe devices. The ARM-enabled part numbers start with M1 (Cortex-M1). Contact your local Microsemi SoC Products Group (formerly Actel) representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. AGL015 and AGL030 The AGL015 and AGL030 are architecturally compatible; there are no RAM or PLL features. IV R evis i o n 19 IGLOO Low Power Flash FPGAs Table of Contents IGLOO Device Family Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 IGLOO DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Power Calculation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-100 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-106 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-115 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-117 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-130 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-131 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-4 3-5 3-5 3-5 Package Pin Assignments UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CS121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 CS196 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 CS281 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25 QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27 QN132 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-30 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-39 FG144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-44 FG256 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-57 FG484 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-67 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 R ev i si o n 1 9 V 1 – IGLOO Device Family Overview General Description The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO devices enables entering and exiting an ultra-low power mode that consumes as little as 5 µW while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption (from 12 µW) while the IGLOO device is completely functional in the system. This allows the IGLOO device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO devices the advantage of being a secure, low power, singlechip solution that is live at power-up (LAPU). IGLOO is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGL015 and AGL030 devices have no PLL or RAM support. IGLOO devices have up to 1 million system gates, supported with up to 144 kbits of true dual-port SRAM and up to 300 user I/Os. M1 IGLOO devices support the high-performance, 32-bit Cortex-M1 processor developed by ARM for implementation in FPGAs. Cortex-M1 is a soft processor that is fully implemented in the FPGA fabric. It has a three-stage pipeline that offers a good balance between low power consumption and speed when implemented in an M1 IGLOO device. The processor runs the ARMv6-M instruction set, has a configurable nested interrupt controller, and can be implemented with or without the debug block. CortexM1 is available for free from Microsemi for use in M1 IGLOO FPGAs. The ARM-enabled devices have ordering numbers that begin with M1AGL and do not support AES decryption. Flash*Freeze Technology The IGLOO device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. When the IGLOO device enters Flash*Freeze mode, the device automatically shuts off the clocks and inputs to the FPGA core; when the device exits Flash*Freeze mode, all activity resumes and data is retained. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and availability of small-footprint, high pin-count packages, make IGLOO devices the best fit for portable electronics. R ev i si o n 1 9 1 -1 IGLOO Device Family Overview Flash Advantages Low Power Flash-based IGLOO devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO devices also have low dynamic power consumption to further maximize power savings; power is even further reduced by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO device the lowest total system power offered by any FPGA. Security Nonvolatile, flash-based IGLOO devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of protection in the FPGA industry for intellectual property and configuration data. In addition, all FlashROM data in IGLOO devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. The contents of a programmed IGLOO device cannot be read back, although secure design verification is possible. Security, built into the FPGA fabric, is an inherent component of the IGLOO family. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. The IGLOO family, with FlashLock and AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An IGLOO device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Live at Power-Up Flash-based IGLOO devices support Level 0 of the LAPU classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The LAPU feature of flash-based IGLOO devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO flash FPGAs allow the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike SRAMbased FPGAs the device does not need to reload configuration and design state from external memory components; instead it retains all necessary information to resume operation immediately. 1- 2 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAMbased FPGAs, Flash-based IGLOO devices allow all functionality to be live at power-up; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industrystandard AES algorithm. The IGLOO family device architecture mitigates the need for ASIC migration at higher user volumes. This makes the IGLOO family a cost-effective ASIC replacement solution, especially for applications in the consumer, networking/communications, computing, and avionics markets. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO family offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO family FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO architecture provides granularity comparable to standard-cell ASICs. The IGLOO device consists of five distinct and programmable architectural features (Figure 1-1 on page 1-4 and Figure 1-2 on page 1-4): • • • • • • Flash*Freeze technology FPGA VersaTiles Dedicated FlashROM Dedicated SRAM/FIFO memory† Extensive CCCs and PLLs† Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs. † The AGL015 and AGL030 do not support PLL or SRAM. R ev i si o n 1 9 1 -3 IGLOO Device Family Overview VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. Bank 0 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block* Bank 1 Bank 0 I/Os VersaTile Bank 1 Bank 0 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 1 * Not supported by AGL015 and AGL030 devices Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks (AGL015, AGL030, AGL060, and AGL125) Bank 0 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 3 Bank 1 I/Os VersaTile Bank 3 Bank 1 ISP AES Decryption* User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block (AGL600 and AGL1000) Bank 2 Figure 1-2 • IGLOO Device Architecture Overview with Four I/O Banks (AGL250, AGL600, AGL400, and AGL1000) 1- 4 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Flash*Freeze Technology The IGLOO device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be driven or can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and states. I/O states are tristated during Flash*Freeze mode or can be set to a certain state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 5 µW in this mode. Flash*Freeze technology allows the user to switch to active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned, which is advantageous because of the inherent low power static (as low as 12 µW) and dynamic capabilities of the IGLOO device. Refer to Figure 1-3 for an illustration of entering/exiting Flash*Freeze mode. Flash*Freeze Mode Control IGLOO FPGA Flash*Freeze Pin Figure 1-3 • IGLOO Flash*Freeze Mode VersaTiles The IGLOO core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The IGLOO VersaTile supports the following: • • • • All 3-input logic functions—LUT-3 equivalent Latch with clear or set D-flip-flop with clear or set Enable D-flip-flop with clear or set Refer to Figure 1-4 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR D-FF Y LUT-3 Y Figure 1-4 • VersaTile Configurations R ev i si o n 1 9 1 -5 IGLOO Device Family Overview User Nonvolatile FlashROM IGLOO devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • • • • • • • • Internet protocol addressing (wireless or fixed) System calibration settings Device serialization and/or inventory control Subscription-based business models (for example, set-top boxes) Secure key storage for secure communications algorithms Asset management/tracking Date stamping Version management The FlashROM is written using the standard IGLOO IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the AGL015 and AGL030 devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The Microsemi development software solutions, Libero® Integrated Design Environment (IDE) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature allows the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Libero IDE and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO devices (except the AGL015 and AGL030 devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGL015 and AGL030 devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC IGLOO devices provide designers with very flexible clock conditioning circuit (CCC) capabilities. Each member of the IGLOO family contains six CCCs. One CCC (center west side) has a PLL. The AGL015 and AGL030 do not have a PLL. The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC (center west side) has a PLL. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. 1- 6 R ev isio n 1 9 IGLOO Low Power Flash FPGAs The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs located near the CCC that have dedicated connections to the CCC block. The CCC block has these key features: • • • • • • • • • • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz 2 programmable delay types for clock skew minimization Clock frequency synthesis (for PLL only) Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). Output duty cycle = 50% ± 1.5% or better (for PLL only) Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) Maximum acquisition time is 300 µs (for PLL only) Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC (for PLL only) Additional CCC specifications: Global Clocking IGLOO devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards The IGLOO family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). IGLOO FPGAs support many different I/O standards—singleended and differential. The I/Os are organized into banks, with two or four banks per device. The configuration of these banks determines the I/O standards supported (Table 1-1). Table 1-1 • I/O Standards Supported I/O Standards Supported I/O Bank Type Advanced Standard Plus Device and Bank Location East and west banks of AGL250 and larger devices North and south banks of AGL250 and larger devices All banks of AGL060 and AGL125K Standard All banks of AGL015 and AGL030 LVTTL/ LVCMOS PCI/PCI-X LVPECL, LVDS, B-LVDS, M-LVDS ✓ ✓ ✓ ✓ ✓ Not supported ✓ Not supported Not supported R ev i si o n 1 9 1 -7 IGLOO Device Family Overview Each I/O module contains several input, output, and enable registers. These registers allow the implementation of the following: • • Single-Data-Rate applications Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point communications IGLOO banks for the AGL250 device and above support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can support up to 20 loads. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support IGLOO devices support JEDEC-defined wide range I/O operation. IGLOO devices support both the JESD8-B specification, covering 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-5 on page 1-9). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated 1- 8 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Figure 1-5 • I/O States During Programming Window 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. R ev i si o n 1 9 1 -9 2 – IGLOO DC and Switching Characteristics General Specifications Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Symbol VCC VJTAG VPUMP VCCPLL Absolute Maximum Ratings Parameter DC core supply voltage JTAG DC voltage Programming voltage Analog power supply (PLL) Limits1 –0.3 to 1.65 –0.3 to 3.75 –0.3 to 3.75 –0.3 to 1.65 –0.3 to 3.75 –0.3 V to 3.6 V (when I/O hot insertion mode is enabled) –0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower (when I/O hot-insertion mode is disabled) TSTG 3 TJ 3 Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User’s Guide for further information. 3. For flash programming and retention, maximum limits refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. Units V V V V V V VCCI and VMV 2 DC I/O buffer supply voltage VI I/O input voltage Storage Temperature Junction Temperature –65 to +150 +125 °C °C R ev i si o n 1 9 2 -1 IGLOO DC and Switching Characteristics Table 2-2 • Symbol TA TJ VCC 3 Recommended Operating Conditions 1 Parameter Ambient Temperature Junction Temperature 2 5 Commercial 0 to +70 0 to +85 1.14 to 1.575 1.4 to 3.6 Industrial –40 to +85 –40 to +100 1.14 to 1.575 1.4 to 3.6 3.15 to 3.45 0 to 3.6 1.14 to 1.575 1.14 to 1.26 1.14 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 Units °C °C V V V V V V V V V V V V V V V V 1.5 V DC core supply voltage 1.2 V–1.5 V wide range DC core supply voltage 4,6 1.425 to 1.575 1.425 to 1.575 VJTAG VPUMP VCCPLL 8 JTAG DC voltage Programming voltage Analog power supply (PLL) Programming Mode Operation 7 1.5 V DC core supply voltage5 3.15 to 3.45 0 to 3.6 1.425 to 1.575 1.425 to 1.575 1.2 V – 1.5 V DC core supply 1.14 to 1.575 voltage4,6 VCCI and 1.2 V DC core supply voltage6 VMV 9 1.2 V DC wide range DC supply voltage6 1.5 V DC supply voltage 1.8 V DC supply voltage 2.5 V DC supply voltage 3.0 V DC supply voltage 10 3.3 V DC supply voltage LVDS differential I/O LVPECL differential I/O Notes: 1.14 to 1.26 1.14 to 1.575 1.425 to 1.575 1.7 to 1.9 2.3 to 2.7 2.7 to 3.6 3.0 to 3.6 2.375 to 2.625 3.0 to 3.6 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Microsemi recommends that the user follow best design practices using Microsemi’s timing and power simulation tools. 3. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-25 on page 2-24. VCCI should be at the same voltage within a given I/O bank. 4. All IGLOO devices (V5 and V2) must be programmed with the VCC core voltage at 1.5 V. Applications using the V2 devices powered by 1.2 V supply must switch the core supply to 1.5 V for in-system programming. 5. For IGLOO® V5 devices 6. For IGLOO V2 devices only, operating at VCCI ≥ VCC. 7. VPUMP can be left floating during operation (not programming mode). 8. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User’s Guide for further information. 9. VMV pins must be connected to the corresponding VCCI pins. See the "Pin Descriptions" chapter of the IGLOO FPGA Fabric User’s Guide for further information. 10. 3.3 V wide range is compliant to the JESD-8B specification and supports 3.0 V VCCI operation. Table 2-3 • Product Grade Commercial Industrial Notes: Flash Programming Limits – Retention, Storage, and Operating Temperature1 Programming Cycles 500 500 Maximum Operating Junction Program Retention Maximum Storage Temperature TJ (°C) 2 (biased/unbiased) Temperature TSTG (°C) 2 20 years 20 years 110 110 100 100 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2- 2 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Table 2-4 • Overshoot and Undershoot Limits 1 Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 10% 5% 3V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at junction temperature at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. 3. This table does not provide PCI overshoot/undershoot limits. VCCI 2.7 V or less Maximum Overshoot/ Undershoot2 1.4 V 1.49 V 1.1 V 1.19 V 0.79 V 0.88 V 0.45 V 0.54 V 10% 5% 10% 5% 10% 5% I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOO device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5. There are five regions to consider during power-up. IGLOO I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 Devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • • During programming, I/Os become tristated and weakly pulled up to VCCI. JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. R ev i si o n 1 9 2 -3 IGLOO DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes low and/or the output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC®3 and ProASIC3E FPGA fabric user’s guides for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL, VOH / VOL, etc. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V VCCI Figure 2-1 • V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels 2- 4 R ev isio n 1 9 IGLOO Low Power Flash FPGAs VCC VCC = 1.575 V VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI is below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional (except differential inputs) but slower because VCCI/VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers do not meet VOH/VOL levels. Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI Figure 2-2 • V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels Thermal Characteristics Introduction The temperature variable in the Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = ΔT + TA EQ 1 where: TA = Ambient Temperature ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5 on page 2-6. P = Power dissipation R ev i si o n 1 9 2 -5 IGLOO DC and Switching Characteristics Package Thermal Characteristics The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute maximum junction temperature is 100°C. EQ 2 shows a sample calculation of the absolute maximum power dissipation allowed for the AGL1000-FG484 package at commercial temperature and in still air. Max. junction temp. ( ° C) – Max. ambient temp. ( ° C) 100 ° C – 70 ° C Maximum Power Allowed = ----------------------------------------------------------------------------------------------------------------------------------------- = ------------------------------------ = 1.28 W θ ja ( ° C/W) 23.3°C/W EQ 2 Table 2-5 • Package Thermal Resistivities θja Package Type Quad Flat No Lead (QN) Device AGL030 AGL060 AGL125 AGL250 AGL030 Very Thin Quad Flat Pack (VQ)* Chip Scale Package (CS) AGL1000 AGL400 AGL250 AGL125 AGL030 AGL060 AGL250 Micro Chip Scale Package (UC) Fine Pitch Ball Grid Array (FG) AGL030 AGL060 AGL1000 AGL400 AGL250 AGL1000 AGL1000 Pin Count 132 132 132 132 68 100 281 196 196 196 81 81 81 81 144 144 144 256 256 484 θjc 13.1 11.0 9.2 8.9 13.4 10.0 6.0 7.2 7.6 8.0 12.4 11.1 10.4 16.9 18.6 6.3 6.8 12.0 6.6 8.0 Still Air 21.4 21.2 21.1 21.0 68.4 35.3 28.0 37.1 38.3 39.5 32.8 28.8 26.9 40.6 55.2 31.6 37.6 38.6 28.1 23.3 1 m/s 16.8 16.6 16.5 16.4 45.8 29.4 22.8 31.1 32.2 33.4 28.5 24.8 22.3 35.2 49.4 26.2 31.2 34.7 24.4 19.0 2.5 m/s 15.3 15.0 14.9 14.8 43.1 27.1 21.5 28.9 30.0 31.1 27.2 23.5 20.9 33.7 47.2 24.2 29.0 33.0 22.7 16.7 Unit C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W C/W Note: *Thermal resistances for other device-package combinations will be posted in a later revision. Disclaimer: The simulation for determining the junction-to-air thermal resistance is based on JEDEC standards (JESD51) and assumptions made in building the model. Junction-to-case is based on SEMI G38-88. JESD51 is only used for comparing one package to another package, provided the two tests uses the same condition. They have little relevance in actual application and therefore should be used with a degree of caution. 2- 6 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) For IGLOO V2 or V5 devices, 1.5 V DC Core Supply Voltage Junction Temperature (°C) –40°C 0.934 0.855 0.799 0°C 0.953 0.874 0.816 25°C 0.971 0.891 0.832 70°C 1.000 0.917 0.857 85°C 1.007 0.924 0.864 100°C 1.013 0.929 0.868 Array Voltage VCC (V) 1.425 1.500 1.575 Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) For IGLOO V2, 1.2 V DC Core Supply Voltage Junction Temperature (°C) –40°C 0.967 0.864 0.794 0°C 0.978 0.874 0.803 25°C 0.991 0.885 0.814 70°C 1.000 0.894 0.821 85°C 1.006 0.899 0.827 100°C 1.010 0.902 0.830 Array Voltage VCC (V) 1.14 1.20 1.26 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power modes usage. Microsemi recommends using the PowerCalculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • Power Supply State per Mode Power Supply Configurations Modes/power supplies Flash*Freeze Sleep Shutdown No Flash*Freeze Note: Off: Power supply level = 0 V Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO Flash*Freeze Mode* Core Voltage Typical (25°C) 1.2 V 1.5 V AGL015 AGL030 AGL060 AGL125 AGL250 4 6 4 6 8 10 13 18 20 34 AGL400 27 51 AGL600 30 72 AGL1000 44 127 Units µA µA VCC On Off Off On VCCPLL On Off Off On VCCI On On Off On VJTAG On Off Off On VPUMP On/off/floating Off Off On/off/floating Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-10 through Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12 (PDC6 and PDC7). R ev i si o n 1 9 2 -7 IGLOO DC and Switching Characteristics Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO Sleep Mode* Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units VCCI/ VJTAG = 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) Typical (25°C) VCCI/VJTAG = 3.3 V (per bank) Typical (25°C) 1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 µA 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 µA 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 µA 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 µA 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 µA Note: IDD = NBANKS × ICCI. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-10 through Table 2-15 on page 2-11 and Table 2-16 on page 2-11 through Table 2-18 on page 2-12 (PDC6 and PDC7). Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO Shutdown Mode Core Voltage Typical (25°C) 1.2 V / 1.5 V AGL015 0 AGL030 0 Units µA 2- 8 R ev isio n 1 9 IGLOO Low Power Flash FPGAs Table 2-12 • Quiescent Supply Current (IDD), No IGLOO Flash*Freeze Mode1 Core Voltage AGL015 AGL030 AGL060 AGL125 AGL250 AGL400 AGL600 AGL1000 Units ICCA Current2 Typical (25°C) 1.2 V 1.5 V ICCI or IJTAG Current VCCI/VJTAG = 1.2 V (per bank) Typical (25°C) VCCI/VJTAG = 1.5 V (per bank) Typical (25°C) VCCI/VJTAG = 1.8 V (per bank) Typical (25°C) VCCI/VJTAG = 2.5 V (per bank) Typical (25°C) VCCI/VJTAG = 3.3 V (per bank) Typical (25°C) Notes: 1. IDD = NBANKS × ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC, VPUMP, and VCCPLL currents. 3. Values do not include I/O static contribution (PDC6 and PDC7). 3 5 14 6 16 10 20 13 28 18 44 25 66 28 82 42 137 µA µA 1.2 V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 1.7 µA 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.2 V / 1.5 V 1.8 1.8 1.8 1.8 1.8 1.8 1.8 1.8 µA 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.9 µA 2.2 2.2 2.2 2.2 2.2 2.2 2.2 2.2 µA 2.5 2.5 2.5 2.5 2.5 2.5 2.5 2.5 µA R ev i si o n 1 9 2 -9 IGLOO DC and Switching Characteristics Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Advanced I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. 2. 3. 4. PDC6 is the static power (where applicable) measured on VCCI. PAC9 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO V2 devices only 4 3 Static Power PDC6 (mW)1 – – – – – – – – – 2.26 5.72 Dynamic Power PAC9 (µW/MHz)2 16.27 16.27 4.65 1.61 0.96 0.58 0.58 17.67 17.67 23.39 59.05 3.3 3.3 2.5 1.8 1.5 1.2 1.2 3.3 3.3 2.5 3.3 Table 2-14 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard Plus I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range 3.3 V PCI 3.3 V PCI-X Notes: 1. 2. 3. 4. PDC6 is the static power (where applicable) measured on VCCI. PAC9 is the total dynamic power measured on VCCI. Applicable for IGLOO V2 devices only. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4 Static Power PDC6 (mW)1 – – – – – – – – – Dynamic Power PAC9 (µW/MHz)2 16.41 16.41 4.75 1.66 1.00 0.61 0.61 17.78 17.78 3.3 3.3 2.5 1.8 1.5 1.2 1.2 3.3 3.3 2- 10 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-15 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to Standard I/O Banks VCCI (V) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 4 3 Static Power PDC6 (mW)1 Dynamic Power PAC9 (µW/MHz)2 3.3 3.3 2.5 1.8 1.5 1.2 1.2 – – – – – – – 17.24 17.24 5.64 2.63 1.97 0.57 0.57 1.2 V LVCMOS Wide Range4 Notes: 1. 2. 3. 4. PDC6 is the static power (where applicable) measured on VCCI. PAC9 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO V2 devices only. Table 2-16 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Advanced I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range4 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS5 1.2 V LVCMOS Wide Range 3.3 V PCI 3.3 V PCI-X Differential LVDS LVPECL Notes: 1. 2. 3. 4. 5. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC7 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO V2 devices only. 5 VCCI (V) 3.3 3.3 2.5 1.8 1.5 1.2 1.2 3.3 3.3 2.5 3.3 Static Power PDC7 (mW)2 – – – – – – – – – 7.74 19.54 Dynamic Power PAC10 (µW/MHz)3 136.95 136.95 76.84 49.31 33.36 16.24 16.24 194.05 194.05 156.22 339.35 5 5 5 5 5 5 5 10 10 – – R ev i si o n 1 9 2- 11 IGLOO DC and Switching Characteristics Table 2-17 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Standard Plus I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 1. 2. 3. 4. 5. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC7 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO V2 devices only. 5 4 VCCI (V) 3.3 3.3 2.5 1.8 1.5 1.2 1.2 3.3 3.3 Static Power PDC7 (mW)2 – – – – – – – – – Dynamic Power PAC10 (µW/MHz)3 122.16 122.16 68.37 34.53 23.66 14.90 14.90 181.06 181.06 5 5 5 5 5 5 5 10 10 1.2 V LVCMOS Wide Range5 Table 2-18 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to Standard I/O Banks CLOAD (pF) Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 3.3V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS (JESD8-11) 1.2 V LVCMOS Notes: 1. 2. 3. 4. 5. Dynamic power consumption is given for standard load and software default drive strength and output slew. PDC7 is the static power (where applicable) measured on VCCI. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. Applicable for IGLOO V2 devices only. 5 5 4 VCCI (V) 3.3 3.3 2.5 1.8 1.5 1.2 1.2 Static Power PDC7 (mW)2 – – – – – – – Dynamic Power PAC10 (µW/MHz)3 104.38 104.38 59.86 31.26 21.96 13.49 13.49 5 5 5 5 5 5 5 1.2 V LVCMOS Wide Range 2- 12 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Power Consumption of Various Internal Resources Table 2-19 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standarddependent) Contribution of an I/O output pin (standarddependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic PLL contribution AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 14.48 2.48 12.77 1.85 12.77 1.58 11.03 1.58 0.81 0.11 11.03 0.81 9.3 0.81 9.3 0.41 9.3 0.41 PAC5 0.057 PAC6 0.207 PAC7 0.17 PAC8 PAC9 0.7 See Table 2-13 on page 2-10 through Table 2-15 on page 2-11. PAC10 See Table 2-16 on page 2-11 through Table 2-18 on page 2-12. PAC11 25.00 PAC12 30.00 PAC13 2.70 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE). R ev i si o n 1 9 2- 13 IGLOO DC and Switching Characteristics Table 2-20 • Different Components Contributing to the Static Power Consumption in IGLOO Devices For IGLOO V2 or V5 Devices, 1.5 V DC Core Supply Voltage Device-Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 PDC6 PDC7 Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-dependent) I/O input pin static power (standard-dependent) I/O output pin static power (standard-dependent) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 See Table 2-12 on page 2-9. See Table 2-11 on page 2-8. See Table 2-9 on page 2-7. 1.84 See Table 2-12 on page 2-9. See Table 2-13 on page 2-10 through Table 2-15 on page 2-11. See Table 2-16 on page 2-11 through Table 2-18 on page 2-12. * For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE). 2- 14 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-21 • Different Components Contributing to Dynamic Power Consumption in IGLOO Devices For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter PAC1 PAC2 PAC3 PAC4 Definition Clock contribution of a Global Rib Clock contribution of a Global Spine Clock contribution of a VersaTile row Clock contribution of a VersaTile used as a sequential module First contribution of a VersaTile used as a sequential module Second contribution of a VersaTile used as a sequential module Contribution of a VersaTile used as a combinatorial module Average contribution of a routing net Contribution of an I/O input pin (standarddependent) Contribution of an I/O output pin (standarddependent) Average contribution of a RAM block during a read operation Average contribution of a RAM block during a write operation Dynamic PLL contribution AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 9.28 1.59 8.19 1.19 8.19 1.01 7.07 1.01 0.52 0.07 7.07 0.52 5.96 0.52 5.96 0.26 5.96 0.26 PAC5 0.045 PAC6 0.186 PAC7 0.11 PAC8 PAC9 0.45 See Table 2-13 on page 2-10 through Table 2-15 on page 2-11. PAC10 See Table 2-16 on page 2-11 through Table 2-18 on page 2-12. PAC11 25.00 PAC12 30.00 PAC13 2.10 Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero IDE. R ev i si o n 1 9 2- 15 IGLOO DC and Switching Characteristics Table 2-22 • Different Components Contributing to the Static Power Consumption in IGLOO Device For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage Device Specific Static Power (mW) Parameter PDC1 PDC2 PDC3 PDC4 PDC5 PDC6 PDC7 Definition Array static power in Active mode Array static power in Static (Idle) mode Array static power in Flash*Freeze mode Static PLL contribution Bank quiescent power (VCCI-Dependent) I/O input pin static power (standard-dependent) I/O output pin static power (standarddependent) AGL1000 AGL600 AGL400 AGL250 AGL125 AGL060 AGL030 AGL015 See Table 2-12 on page 2-9. See Table 2-11 on page 2-8. See Table 2-9 on page 2-7. 0.90 See Table 2-12 on page 2-9. See Table 2-13 on page 2-10 through Table 2-15 on page 2-11. See Table 2-16 on page 2-11 through Table 2-18 on page 2-12. Note: For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or SmartPower tool in Libero® Integrated Design Environment (IDE). 2- 16 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Microsemi Libero IDE software. The power calculation methodology described below uses the following variables: • • • • • • • • The number of PLLs as well as the number and the frequency of each output clock generated The number of combinatorial and sequential cells used in the design The internal clock frequencies The number and the standard of I/O pins used in the design The number of RAM blocks used in the design Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-23 on page 2-19. Enable rates of output buffers—guidelines are provided for typical applications in Table 2-24 on page 2-19. Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-24 on page 2-19. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 + NINPUTS * PDC6 + NOUTPUTS * PDC7 NINPUTS is the number of I/O input buffers used in the design. NOUTPUTS is the number of I/O output buffers used in the design. NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE* PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in Table 2-23 on page 2-19. NROW is the number of VersaTile rows used in the design—guidelines are provided in Table 2-23 on page 2-19. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19. FCLK is the global clock signal frequency. R ev i si o n 1 9 2- 17 IGLOO DC and Switching Characteristics Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. α1 NC-CELL is the number of VersaTiles used as combinatorial modules in the design. is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-23 on page 2-19. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. FCLK is the global clock signal frequency. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-23 on page 2-19. β1 is the I/O buffer enable rate—guidelines are provided in Table 2-24 on page 2-19. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. β2 is the RAM enable rate for read operations. β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-24 on page 2-19. FWRITE-CLOCK is the memory write clock frequency. PLL Contribution—PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.† † If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. 2- 18 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. The average toggle rate of an 8-bit counter is 25%: – – – – – – Bit 0 (LSB) = 100% Bit 1 Bit 2 … Bit 7 (MSB) = 0.78125% Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 = 50% = 25% Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-23 • Toggle Rate Guidelines Recommended for Power Calculation Component Definition Toggle rate of VersaTile outputs I/O buffer toggle rate Guideline 10% 10% α1 α2 Component Table 2-24 • Enable Rate Guidelines Recommended for Power Calculation Definition I/O output buffer enable rate RAM enable rate for read operations RAM enable rate for write operations Guideline 100% 12.5% 12.5% β1 β2 β3 R ev i si o n 1 9 2- 19 IGLOO DC and Switching Characteristics User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Y tPD = 1.22 ns Combinational Cell Y tPD = 1.20 ns tDP = 1.72 ns Combinational Cell Y tPD = 1.80 ns Combinational Cell I/O Module (Registered) tPY = 1.20 ns LVPECL (Applicable to Advanced I/O Banks only) D Q tPD = 1.49 ns Combinational Cell Y tICLKQ = 0.43 ns tISUD = 0.47 ns Input LVTTL Clock Register Cell tPY = 0.87 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVDS, BLVDS, M-LVDS (Applicable for Advanced I/O Banks only) tCLKQ = 0.90 ns tSUD = 0.82 ns tPY = 1.35 ns Input LVTTL Clock tPY = 0.87 ns (Advanced I/O Banks) D Q Combinational Cell Y tPD = 0.92 ns tCLKQ = 0.90 ns tSUD = 0.82 ns Input LVTTL Clock tPY = 0.87 ns (Advanced I/O Banks) Register Cell D Q D tPD = 0.86 ns Y LVTTL Output drive strength = 8 mA High slew rate tDP = 4.12 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVCMOS 1.5 V Output drive strength = 4 mA High slew rate tDP = 4.42 ns (Advanced I/O Banks) I/O Module (Registered) Q LVTTL 3.3 V Output drive strength = 12 mA High slew rate I/O Module (Non-Registered) LVTTL Output drive strength = 12 mA High slew rate tDP = 3.05 ns (Advanced I/O Banks) I/O Module (Non-Registered) LVPECL (Applicable to Advanced I/O Banks Only)L tDP = 3.05 ns (Advanced I/O Banks) tOCLKQ = 1.02 ns tOSUD = 0.52 ns Figure 2-3 • Timing Model Operating Conditions: Std. Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices 2- 20 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs tPY tDIN PAD D Y Q DIN To Array CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) I/O Interface VIH PAD Vtrip Vtrip VCC VIL 50% Y GND tPY (R) tPY (F) VCC 50% DIN GND tDOUT (R) Figure 2-4 • Input Buffer Timing Model and Delays (example) 50% 50% tDOUT (F) R ev i si o n 1 9 2- 21 IGLOO DC and Switching Characteristics tDOUT DQ DOUT D From Array I/O Interface CLK tDP PAD Std Load tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) tDOUT VCC 50% VCC 50% 50% VOH Vtrip Vtrip VOL tDP (R) tDP (F) (F) tDOUT (R) 50% D 0V DOUT 0V PAD Figure 2-5 • Output Buffer Model and Delays (example) 2- 22 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs tEOUT D E Q tZL, tZH, tHZ, tLZ, tZLS, tZHS CLK EOUT D D Q DOUT CLK PAD I/O Interface tEOUT = MAX(tEOUT(r), tEOUT(f)) VCC D VCC E 50% tEOUT (R) 50% EOUT tZL PAD Vtrip VOL 50% tEOUT (F) VCC 50% tHZ 90% VCCI Vtrip 10% VCCI 50% tZH VCCI 50% tLZ VCC D VCC E 50% tEOUT (R) 50% tZLS PAD Vtrip VOL Vtrip 50% VCC EOUT 50% VOH 50% tZHS tEOUT (F) Figure 2-6 • Tristate Output Buffer Timing Model and Delays (example) R ev i si o n 1 9 2- 23 IGLOO DC and Switching Characteristics Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-25 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Advanced I/O Banks VIL Equivalent Software Default Drive Max. I/O Drive Strength Slew V Standard Strength Option2 Rate Min.V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range4,5 3.3 V PCI 3.3 V PCI-X Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable to V2 Devices operating at VCCI ≥ VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. VIH VOL VOH IOL1 IOH1 Min. V 2 Max. V 3.6 Max. V 0.4 Min. V 2.4 mA 12 mA 12 12 mA 12 mA High –0.3 0.8 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VCCI – 0.2 0.1 0.1 12 mA 12 mA 12 mA 2 mA 100 µA 12 mA 12 mA 12 mA 2 mA 2 mA High –0.3 0.7 1.7 2.7 1.9 0.7 0.45 1.7 12 12 12 12 2 0.1 High –0.3 0.35 * VCCI 0.65 * VCCI VCCI – 0.45 12 12 2 0.1 High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI 0.1 VCCI – 0.1 High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 Per PCI specifications Per PCI-X specifications 2- 24 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-26 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard Plus I/O Banks Equivalent Software Default Drive I/O Drive Strength Slew Min. Standard Strength Option2 Rate V 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range4 3.3 V PCI 3.3 V PCI-X Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable to V2 Devices operating at VCCI ≥ VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. VIL VIH VOL VOH IOL IOH Max. V 0.8 Min. V 2 Max. V 3.6 Max. V 0.4 Min. V 2.4 mA 12 mA 12 12 mA 12 mA High –0.3 100 µA 12 mA High –0.3 0.8 2 3.6 0.2 VDD-0.2 0.1 0.1 12 mA 8 mA 4 mA 2 mA 100 µA 12 mA 8 mA 4 mA 2 mA 2 mA High –0.3 0.7 1.7 2.7 1.9 0.7 0.45 1.7 VCCI – 0.45 12 8 4 2 0.1 12 8 4 2 0.1 High –0.3 0.35 * VCCI 0.65 * VCCI High –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI High –0.3 0.35 * VCCI 0.65 * VCCI 1.26 0.25 * VCCI 0.75 * VCCI High –0.3 0.3 * VCCI 0.7 * VCCI 1.575 0.1 VCCI – 0.1 Per PCI specifications Per PCI-X specifications R ev i si o n 1 9 2- 25 IGLOO DC and Switching Characteristics Table 2-27 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Applicable to Standard I/O Banks Equivalent Software Default Drive Drive Strength Slew Strength Option2 Rate 8 mA 8 mA High VIL VIH VOL VOH IOL1 IOH1 I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range4,5 Notes: Min. V –0.3 Max. V 0.8 Min. V 2 Max. V 3.6 Max. V 0.4 Min. V 2.4 mA mA 8 8 100 µA 8 mA High –0.3 0.8 2 3.6 0.2 VDD-0.2 0.1 0.1 8 mA 4 mA 2 mA 1 mA 100 µA 8 mA 4 mA 2 mA 1 mA 1 mA High High High High High –0.3 –0.3 –0.3 –0.3 –0.3 0.7 1.7 3.6 3.6 0.7 0.45 1.7 VCCI – 0.45 8 4 2 1 0.1 8 4 2 1 0.1 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.3 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 3.6 0.1 VCCI – 0.1 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVMCOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 4. Applicable to V2 Devices operating at VCCI ≥ VCC. 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification. 2- 26 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-28 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL4 DC I/O Standards 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS3 3 Industrial2 IIH5 µA 10 10 10 10 10 10 10 10 10 IIL4 µA 15 15 15 15 15 15 15 15 15 IIH5 µA 15 15 15 15 15 15 15 15 15 µA 10 10 10 10 10 10 10 10 10 1.2 V LVCMOS Wide Range 3.3 V PCI 3.3 V PCI-X Notes: 1. 2. 3. 4. 5. Commercial range (0°C < TA < 70°C) Industrial range (–40°C < TA < 85°C) Applicable to V2 Devices operating at VCCI ≥ VCC. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges R ev i si o n 1 9 2- 27 IGLOO DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-29 • Summary of AC Measuring Points Standard 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V VCMOS Wide Range 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI Measuring Trip Point (Vtrip) 1.4 V 1.4 V 1.2 V 0.90 V 0.75 V 0.60 V 0.60 V 0.285 * VCCI (RR) 0.615 * VCCI (FF) 3.3 V PCI-X 0.285 * VCCI (RR) 0.615 * VCCI (FF) Table 2-30 • I/O AC Parameter Definitions Parameter tDP tPY tDOUT tEOUT tDIN tHZ tZH tLZ tZL tZHS tZLS Parameter Definition Data to Pad delay through the Output Buffer Pad to Data delay through the Input Buffer Data to Output Buffer delay through the I/O interface Enable to Output Buffer Tristate Control delay through the I/O interface Input Buffer to Data delay through the I/O interface Enable to Pad delay through the Output Buffer—High to Z Enable to Pad delay through the Output Buffer—Z to High Enable to Pad delay through the Output Buffer—Low to Z Enable to Pad delay through the Output Buffer—Z to Low Enable to Pad delay through the Output Buffer with delayed enable—Z to High Enable to Pad delay through the Output Buffer with delayed enable—Z to Low 2- 28 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-31 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard) Applicable to Advanced I/O Banks Equivalent Software Default Drive Strength Option1 (mA) External Resistor (Ω) Capacitive Load (pF) Drive Strength I/O Standard Slew Rate tE O U T (ns) tDOUT (ns) tDIN (ns) tPY (ns) tZH (ns) tHZ (ns) tZLS (ns) tLZ (ns) tZHS (ns) – – tDP (ns) tZL (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X LVDS LVPECL Notes: 12 mA 12 High 5 – 0.97 2.09 0.18 0.85 0.66 2.14 1.68 2.67 3.05 5.73 5.27 ns 100 µA 12 High 5 – 0.97 2.93 0.18 1.19 0.66 2.95 2.27 3.81 4.30 6.54 5.87 ns 12 mA 12 mA 12 mA Per PCI spec Per PCI-X spec 24 mA 24 mA 12 12 12 – – High High High High High 5 5 5 10 10 – – – 0.97 2.09 0.18 1.08 0.66 2.14 1.83 2.73 2.93 5.73 5.43 ns 0.97 2.24 0.18 1.01 0.66 2.29 2.00 3.02 3.40 5.88 5.60 ns 0.97 2.50 0.18 1.17 0.66 2.56 2.27 3.21 3.48 6.15 5.86 ns 25 2 0.97 2.32 0.18 0.74 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns 25 2 0.97 2.32 0.19 0.70 0.66 2.37 1.78 2.67 3.05 5.96 5.38 ns – – High High – – – – 0.97 1.74 0.19 1.35 0.97 1.68 0.19 1.16 – – – – – – – – – – – – ns ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 9 2- 29 Units IGLOO DC and Switching Characteristics Table 2-32 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard) Applicable to Standard Plus I/O Banks Equivalent Software Default Drive Strength Option1 (mA) External Resistor (Ω) Capacitive Load (pF) Drive Strength I/O Standard tE O U T (ns) Slew Rate tDOUT (ns) tDIN (ns) tPY (ns) tZH (ns) tHZ (ns) tZLS (ns) tLZ (ns) tZHS (ns) tDP (ns) tZL (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 3.3 V PCI 3.3 V PCI-X Notes: 12 mA 12 High 5 – 0.97 1.75 0.18 0.85 0.66 1.79 1.40 2.36 2.79 5.38 4.99 ns 100 µA 12 High 5 – 0.97 2.45 0.18 1.20 0.66 2.47 1.92 3.33 3.90 6.06 5.51 ns 12 mA 8 mA 4 mA Per PCI spec Per PCIX spec 12 8 4 – – High High High High High 5 5 5 10 10 – – – 0.97 1.75 0.18 1.08 0.66 1.79 1.52 2.38 2.70 5.39 5.11 ns 0.97 1.97 0.18 1.01 0.66 2.02 1.76 2.46 2.66 5.61 5.36 ns 0.97 2.25 0.18 1.18 0.66 2.30 2.00 2.53 2.68 5.89 5.59 ns 25 2 0.97 1.97 0.18 0.73 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns 25 2 0.97 1.97 0.19 0.70 0.66 2.01 1.50 2.36 2.79 5.61 5.10 ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity. This resistor is not required during normal operation. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 30 R ev i sio n 1 9 Units IGLOO Low Power Flash FPGAs Table 2-33 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI (per standard) Applicable to Standard I/O Banks Equivalent Software Default Drive Strength Option1 (mA) External Resistor (Ω) Capacitive Load (pF) Drive Strength) I/O Standard Slew Rate tDIN (ns) tPY (ns) tE O U T (ns) tDOUT (ns) tDP (ns) tZH (ns) tHZ (ns) 2.26 3.17 2.15 2.06 2.03 tZL (ns) tLZ (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS Notes: 8 mA 8 High 5 – 0.97 1.85 0.18 0.83 0.66 1.89 1.46 1.96 100 µA 8 High 5 – 0.97 2.62 0.18 1.17 0.66 2.63 2.02 2.79 8 mA 4 mA 2 mA 8 4 2 High High High 5 5 5 – – – 0.97 0.97 0.97 1.88 2.18 2.51 0.18 0.18 0.18 1.04 0.98 1.14 0.66 0.66 0.66 1.92 2.22 2.56 1.63 1.93 2.21 1.95 1.97 1.99 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 9 2- 31 Units ns ns ns ns ns IGLOO DC and Switching Characteristics Table 2-34 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard) Applicable to Advanced I/O Banks Equivalent Software Default Drive Strength Option1 External Resistor (Ω) Capacitive Load (pF) Drive Strength I/O Standard tE O U T (ns) Slew Rate tDOUT (ns) tDIN (ns) tPY (ns) tZH (ns) tHZ (ns) tZLS (ns) tLZ (ns) tZHS (ns) – – tDP (ns) tZL (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range3 12 mA 12 mA High 5 – 1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns 100 µA 12 mA High 5 – 1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns 12 mA 12 mA High 12 mA 12 mA 2 mA 100 µA 12 mA High 12 mA High 2 mA 2 mA High High 5 5 5 5 5 – – – – – 1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns 1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns 1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns 1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns 1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns 3.3 V PCI Per PCI spec 3.3 V PCI-X LVDS LVPECL Notes: Per PCI-X spec 24 mA 24 mA – – High High 10 10 252 1.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns 252 1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns – – High High – – – – 1.55 2.27 0.25 1.57 1.55 2.24 0.25 1.38 – – – – – – – – – – – – ns ns 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 32 R ev i sio n 1 9 Units IGLOO Low Power Flash FPGAs Table 2-35 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard) Applicable to Standard Plus I/O Banks Equivalent Software Default Drive Strength Option1 (mA) External Resistor (Ω) Capacitive Load (pF) Drive Strength I/O Standard Slew Rate tDOUT (ns) tEOUT (ns) tZH (ns) tPY (ns) tZL (ns) tHZ (ns) tZHS (ns) tDIN (ns) tDP (ns) tZLS (ns) tLZ (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range2 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range3 3.3 V PCI 12 mA 12 High 5 – 1.55 2.31 0.26 0.97 1.10 2.34 1.86 2.93 3.64 8.12 7.65 ns 100 µA 12 High 5 – 1.55 3.20 0.26 1.32 1.10 3.20 2.52 4.01 4.97 8.99 8.31 ns 12 mA 8 mA 4 mA 2 mA 100 µA 12 8 4 2 2 High High High High High 5 5 5 5 5 – – – – – 1.55 2.29 0.26 1.19 1.10 2.32 1.94 2.94 3.52 8.10 7.73 ns 1.55 2.43 0.26 1.11 1.10 2.47 2.16 2.99 3.39 8.25 7.94 ns 1.55 2.68 0.26 1.27 1.10 2.72 2.39 3.07 3.37 8.50 8.18 ns 1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns 1.55 3.22 0.26 1.59 1.10 3.11 2.78 3.29 3.48 8.90 8.57 ns Per PCI spec Per PCI-X spec – High 10 252 1.55 2.53 0.26 0.84 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns 3.3 V PCI-X Notes: – High 10 252 1.55 2.53 0.25 0.85 1.10 2.57 1.98 2.93 3.64 8.35 7.76 ns 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification 4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-79 for connectivity. This resistor is not required during normal operation. 5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 9 2- 33 Units IGLOO DC and Switching Characteristics Table 2-36 • Summary of I/O Timing Characteristics—Software Default Settings, Std. Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per standard) Applicable to Standard I/O Banks Equivalent Software Default Drive Strength Option1 (mA) External Resistor (Ω) Capacitive Load (pF) Drive Strength I/O Standard Slew Rate tDOUT (ns) tDIN (ns) tDP (ns) tEOUT (ns) tZH (ns) tPY (ns) tZL (ns) tHZ (ns) tLZ (ns) 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range3 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range3 Notes: 8 mA 8 High 5 – 1.55 2.38 0.26 0.94 1.10 2.41 1.92 2.40 2.96 ns 100 µA 8 High 5 – 1.55 3.33 0.26 1.29 1.10 3.33 2.62 3.34 4.07 ns 8 mA 4 mA 2 mA 1 mA 100 µA 8 4 2 1 1 High High High High High 5 5 5 5 5 – – – – – 1.55 1.55 1.55 1.55 1.55 2.39 2.60 2.92 3.59 3.59 0.26 0.26 0.26 0.26 0.26 1.15 1.08 1.22 1.53 1.53 1.10 1.10 1.10 1.10 1.10 2.42 2.64 2.96 3.47 3.47 2.05 2.33 2.60 3.06 3.06 2.38 2.38 2.40 2.51 2.51 2.80 ns 2.62 ns 2.56 ns 2.49 ns 2.49 ns 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 34 R ev i sio n 1 9 Units IGLOO Low Power Flash FPGAs Detailed I/O DC Characteristics Table 2-37 • Input Capacitance Symbol CIN CINCLK Input capacitance Input capacitance on the clock pin Definition Conditions VIN = 0, f = 1.0 MHz VIN = 0, f = 1.0 MHz Min. Max. 8 8 Units pF pF Table 2-38 • I/O Output Buffer Maximum Resistances1 Applicable to Advanced I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS4 1.2 V LVCMOS Wide Range4 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec 4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC RPULL-DOWN (Ω)2 100 100 50 50 25 17 11 TBD 100 100 50 50 25 20 200 100 67 33 33 TBD TBD 25 RPULL-UP (Ω)3 300 300 150 150 75 50 33 TBD 200 200 100 100 50 40 224 112 75 37 37 TBD TBD 75 2 mA 100 μA Per PCI/PCI-X specification R ev i si o n 1 9 2- 35 IGLOO DC and Switching Characteristics Table 2-39 • I/O Output Buffer Maximum Resistances1 Applicable to Standard Plus I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 4 RPULL-DOWN (Ω)2 100 100 50 50 25 25 TBD 100 100 50 50 25 200 100 50 50 200 100 TBD TBD 25 RPULL-UP (Ω)3 300 300 150 150 75 75 TBD 200 200 100 100 50 225 112 56 56 224 112 TBD TBD 75 2 mA 100 μA Per PCI/PCI-X specification 1.2 V LVCMOS Wide Range4 3.3 V PCI/PCI-X Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec 4. Applicable to IGLOO V2 Devices operating at VCCI ≥ VCC 2- 36 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-40 • I/O Output Buffer Maximum Resistances1 Applicable to Standard I/O Banks Standard 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 2 mA 4 mA 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models located at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H spec 4 RPULL-DOWN (Ω)2 100 100 50 50 TBD 100 100 50 50 200 100 200 TBD TBD RPULL-UP (Ω)3 300 300 150 150 TBD 200 200 100 100 225 112 224 TBD TBD 2 mA 1 mA 100 μA Table 2-41 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 (Ω) VCCI 3.3 V 3.3 V Wide Range I/Os 2.5 V 1.8 V 1.5 V 1.2 V 1.2 V Wide Range I/Os Notes: 1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULLDOWN-MAX) = (VOLspec) / I(WEAK PULLDOWN-MIN) R(WEAK PULL-DOWN)2 (Ω) Min. 10 K 10 K 12 K 17 K 19 K 25 K 19 K Max. 45 K 45 K 74 K 110 K 140 K 150 K 150 K Min. 10 K 10 K 11 K 18 K 19 K 25 K 19 K Max. 45 K 45 K 55 K 70 K 90 K 110 K 110 K R ev i si o n 1 9 2- 37 IGLOO DC and Switching Characteristics Table 2-42 • I/O Short Currents IOSH/IOSL Applicable to Advanced I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 1.5 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Note: *TJ = 100°C 2 mA 100 μA Per PCI/PCI-X specification IOSL (mA)* 25 25 51 51 103 132 268 TBD 16 16 32 32 65 83 169 9 17 35 45 91 91 13 25 32 66 66 TBD TBD 103 IOSH (mA)* 27 27 54 54 109 127 181 TBD 18 18 37 37 74 87 124 11 22 44 51 74 74 16 33 39 55 55 TBD TBD 109 2- 38 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-43 • I/O Short Currents IOSH/IOSL Applicable to Standard Plus I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 12 mA 1.8 V LVCMOS 2 mA 4 mA 6 mA 8 mA 1.5 V LVCMOS 2 mA 4 mA 1.2 V LVCMOS 1.2 V LVCMOS Wide Range 3.3 V PCI/PCI-X Note: *TJ = 100°C 2 mA 100 μA Per PCI/PCI-X specification IOSL (mA)* 25 25 51 51 103 103 TBD 16 16 32 32 65 9 17 35 35 13 25 TBD TBD 103 IOSH (mA)* 27 27 54 54 109 109 TBD 18 18 37 37 74 11 22 44 44 16 33 TBD TBD 109 R ev i si o n 1 9 2- 39 IGLOO DC and Switching Characteristics Table 2-44 • I/O Short Currents IOSH/IOSL Applicable to Standard I/O Banks Drive Strength 3.3 V LVTTL / 3.3 V LVCMOS 2 mA 4 mA 6 mA 8 mA 3.3 V LVCMOS Wide Range 2.5 V LVCMOS 100 μA 2 mA 4 mA 6 mA 8 mA 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 1.2 V LVCMOS Wide Range Note: *TJ = 100°C The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 12 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-45 • Duration of Short Circuit Event before Failure Temperature –40°C –20°C 0°C 25°C 70°C 85°C 100°C Time before Failure > 20 years > 20 years > 20 years > 20 years 5 years 2 years 6 months 2 mA 4 mA 2 mA 1 mA 100 μA IOSL (mA)* 25 25 51 51 TBD 16 16 32 32 9 17 13 TBD TBD IOSH (mA)* 27 27 54 54 TBD 18 18 37 37 11 22 16 TBD TBD Table 2-46 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Buffer LVTTL/LVCMOS LVDS/B-LVDS/M-LVDS/ LVPECL Input Rise/Fall Time (min.) No requirement No requirement Input Rise/Fall Time (max.) 10 ns * 10 ns * Reliability 20 years (100°C) 10 years (100°C) Note: The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. 2- 40 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification. Table 2-47 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2 2 VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6 3.6 VOL Max. V 0.4 0.4 0.4 0.4 0.4 0.4 0.4 VOH Min. V 2.4 2.4 2.4 2.4 2.4 2.4 2.4 IOL IOH mA mA 2 4 6 8 2 4 6 8 IOSL Max. mA3 25 25 51 51 103 132 268 IOSH Max. mA3 27 27 54 54 109 127 181 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 10 10 10 10 10 10 12 12 16 16 24 24 Table 2-48 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. V 0.8 0.8 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 2 2 VIH Max. V 3.6 3.6 3.6 3.6 3.6 3.6 VOL Max. V 0.4 0.4 0.4 0.4 0.4 0.4 VOH Min. V 2.4 2.4 2.4 2.4 2.4 2.4 IOL IOH mA mA 2 4 6 8 12 16 2 4 6 8 12 16 IOSL Max. mA3 25 25 51 51 103 103 IOSH Max. mA3 27 27 54 54 109 109 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 10 10 10 10 R ev i si o n 1 9 2- 41 IGLOO DC and Switching Characteristics Table 2-49 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 3.3 V LVTTL / 3.3 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 Max. V 0.8 0.8 0.8 0.8 Min. V 2 2 2 2 VIH Max. V 3.6 3.6 3.6 3.6 VOL Max. V 0.4 0.4 0.4 0.4 VOH Min. V 2.4 2.4 2.4 2.4 IOL IOH mA mA 2 4 6 8 2 4 6 8 IOSL Max. mA3 25 25 51 51 IOSH Max. mA3 27 27 54 54 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 Test Point Datapath 5 pF R=1k Test Point Enable Path R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-7 • AC Loading Table 2-50 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points. 2- 42 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-51 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.15 7.42 7.42 6.89 6.74 6.66 tZHS 7.48 6.96 6.96 6.57 6.48 6.50 Units ns ns ns ns ns ns 4.47 0.18 0.85 3.74 0.18 0.85 3.74 0.18 0.85 3.23 0.18 0.85 3.08 0.18 0.85 3.00 0.18 0.85 4.56 3.89 2.24 2.19 3.82 3.37 2.49 2.63 3.82 3.37 2.49 2.63 3.30 2.98 2.66 2.91 3.14 2.89 2.70 2.99 3.06 2.91 2.74 3.27 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-52 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 2.73 0.18 0.85 2.32 0.18 0.85 2.32 0.18 0.85 2.09 0.18 0.85 2.05 0.18 0.85 2.07 0.18 0.85 2.79 2.22 2.25 2.32 6.38 5.82 2.37 1.85 2.50 2.76 5.96 5.45 2.37 1.85 2.50 2.76 5.96 5.45 2.14 1.68 2.67 3.05 5.73 5.27 2.10 1.64 2.70 3.12 5.69 5.24 2.12 1.60 2.75 3.41 5.71 5.20 Table 2-53 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 7.62 6.90 6.90 6.42 6.42 tZHS 7.05 6.59 6.59 6.22 6.22 Units ns ns ns ns ns 3.94 0.18 0.85 3.24 0.18 0.85 3.24 0.18 0.85 2.76 0.18 0.85 2.76 0.18 0.85 4.02 3.46 1.98 2.03 3.31 2.99 2.21 2.42 3.31 2.99 2.21 2.42 2.82 2.63 2.36 2.68 2.82 2.63 2.36 2.68 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 9 2- 43 IGLOO DC and Switching Characteristics Table 2-54 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns 2.32 0.18 0.85 1.94 0.18 0.85 1.94 0.18 0.85 1.75 0.18 0.85 1.75 0.18 0.85 2.37 1.90 1.98 2.13 5.96 5.49 1.99 1.57 2.20 2.53 5.58 5.16 1.99 1.57 2.20 2.53 5.58 5.16 1.79 1.40 2.36 2.79 5.38 4.99 1.79 1.40 2.36 2.79 5.38 4.99 Table 2-55 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 3.80 3.80 3.15 3.15 tDIN 0.18 0.18 0.18 0.18 tPY 0.83 0.83 0.83 0.83 tEOUT 0.66 0.66 0.66 0.66 tZL 3.88 3.88 3.21 3.21 tZH 3.41 3.41 2.94 2.94 tLZ 1.74 1.74 1.96 1.96 tHZ 1.78 1.78 2.17 2.17 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-56 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 2.19 2.19 1.85 1.85 tDIN 0.18 0.18 0.18 0.18 tPY 0.83 0.83 0.83 0.83 tEOUT 0.66 0.66 0.66 0.66 tZL 2.24 2.24 1.89 1.89 tZH 1.79 1.79 1.46 1.46 tLZ 1.74 1.74 1.96 1.96 tHZ 1.87 1.87 2.26 2.26 Units ns ns ns ns 2- 44 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Applies to 1.2 V DC Core Voltage Table 2-57 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 5.12 0.26 0.98 4.38 0.26 0.98 4.38 0.26 0.98 3.85 0.26 0.98 3.69 0.26 0.98 3.61 0.26 0.98 5.20 4.46 2.81 3.02 10.99 10.25 4.45 3.93 3.07 3.48 10.23 4.45 3.93 3.07 3.48 10.23 3.91 3.53 3.24 3.77 3.75 3.44 3.28 3.84 3.67 3.46 3.33 4.13 9.69 9.54 9.45 9.72 9.72 9.32 9.23 9.24 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-58 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.17 8.73 8.73 8.50 8.45 8.47 tZHS 8.54 8.15 8.15 7.97 7.93 7.89 Units ns ns ns ns ns ns 3.33 0.26 0.98 2.91 0.26 0.98 2.91 0.26 0.98 2.67 0.26 0.98 2.63 0.26 0.98 2.65 0.26 0.98 3.38 2.75 2.82 3.18 2.95 2.37 3.07 3.64 2.95 2.37 3.07 3.64 2.71 2.18 3.25 3.93 2.67 2.14 3.28 4.01 2.69 2.10 3.33 4.31 Table 2-59 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Speed Grade Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS 9.76 9.29 9.29 8.91 8.91 Units ns ns ns ns ns 4.56 0.26 0.97 3.84 0.26 0.97 3.84 0.26 0.97 3.35 0.26 0.97 3.35 0.26 0.97 4.63 3.98 2.54 2.83 10.42 3.90 3.50 2.77 3.24 3.90 3.50 2.77 3.24 3.40 3.13 2.93 3.51 3.40 3.13 2.93 3.51 9.69 9.69 9.19 9.19 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 1 9 2- 45 IGLOO DC and Switching Characteristics Table 2-60 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 8.72 8.33 8.33 8.12 8.12 tZHS 8.17 7.82 7.82 7.65 7.65 Units ns ns ns ns ns 2.89 0.26 0.97 2.50 0.26 0.97 2.50 0.26 0.97 2.31 0.26 0.97 2.31 0.26 0.97 2.93 2.38 2.53 2.96 2.54 2.04 2.77 3.37 2.54 2.04 2.77 3.37 2.34 1.86 2.93 3.64 2.34 1.86 2.93 3.64 Table 2-61 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 4.39 4.39 3.72 3.72 tDIN 0.26 0.26 0.26 0.26 tPY 0.94 0.94 0.94 0.94 tEOUT 1.10 1.10 1.10 1.10 tZL 4.46 4.46 3.78 3.78 tZH 3.91 3.91 3.43 3.43 tLZ 2.17 2.17 2.40 2.40 tHZ 2.44 2.44 2.85 2.85 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-62 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 2.74 2.74 2.38 2.38 tDIN 0.26 0.26 0.26 0.26 tPY 0.94 0.94 0.94 0.94 tEOUT 1.10 1.10 1.10 1.10 tZL 2.78 2.78 2.41 2.41 tZH 2.26 2.26 1.92 1.92 tLZ 2.17 2.17 2.40 2.40 tHZ 2.55 2.55 2.96 2.96 Units ns ns ns ns 2- 46 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs 3.3 V LVCMOS Wide Range Table 2-63 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Advanced I/O Banks 3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Equivalent Software Default Drive Min. Max. Min. Max. Max. Strength V V V V V Option1 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 0.8 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 2 3.6 3.6 3.6 3.6 3.6 3.6 3.6 0.2 0.2 0.2 0.2 0.2 0.2 0.2 Min. V VDD – 0.2 VDD – 0.2 VDD – 0.2 VDD – 0.2 VDD – 0.2 VDD – 0.2 VDD – 0.2 µA 100 100 100 100 100 100 100 µA 100 100 100 100 100 100 100 Max. mA4 TBD TBD TBD TBD TBD TBD TBD Max. mA4 TBD TBD TBD TBD TBD TBD TBD µA5 µA5 10 10 10 10 10 10 10 10 10 10 10 10 10 10 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 100°C junction temperature and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. R ev i si o n 1 9 2- 47 IGLOO DC and Switching Characteristics Table 2-64 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard Plus I/O Banks 3.3 V LVCMOS Wide Range Equivalent Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Min. V –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. Min. V V 0.8 0.8 0.8 0.8 0.8 0.8 2 2 2 2 2 2 Max. V 3.6 3.6 3.6 3.6 3.6 3.6 Max. V 0.2 0.2 0.2 0.2 0.2 0.2 Min. V µA µA Max. mA4 TBD TBD TBD TBD TBD TBD Max. mA4 TBD TBD TBD TBD TBD TBD µA5 µA5 10 10 10 10 10 10 10 10 10 10 10 10 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 100°C junction temperature and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. 2- 48 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-65 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Applicable to Standard I/O Banks 3.3 V LVCMOS Wide Range VIL VIH VOL VOH IOL IOH IOSL IOSH IIL2 IIH3 Drive Strength 100 µA 100 µA 100 µA 100 µA Notes: Equivalent Software Default Drive Min. Strength V Option1 2 mA 4 mA 6 mA 8 mA –0.3 –0.3 –0.3 –0.3 Max. Min. Max. V V V 0.8 0.8 0.8 0.8 2 2 2 2 3.6 3.6 3.6 3.6 Max. V 0.2 0.2 0.2 0.2 Min. V µA µA Max. mA4 TBD TBD TBD TBD Max. mA4 TBD TBD TBD TBD µA5 µA5 10 10 10 10 10 10 10 10 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 VDD – 0.2 100 100 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 4. Currents are measured at 100°C junction temperature and maximum voltage. 5. Currents are measured at 85°C junction temperature. 6. Software default selection highlighted in gray. Table 2-66 • 3.3 V LVCMOS Wide Range AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 3.3 Measuring Point* (V) 1.4 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points. R ev i si o n 1 9 2- 49 IGLOO DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-67 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Advanced Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 6.61 0.18 1.19 5.49 0.18 1.19 5.49 0.18 1.19 4.69 0.18 1.19 4.46 0.18 1.19 4.34 0.18 1.19 6.63 5.63 3.15 2.98 10.22 9.23 5.51 4.84 3.54 3.66 5.51 4.84 3.54 3.66 4.71 4.25 3.80 4.10 4.48 4.11 3.86 4.21 4.36 4.14 3.93 4.64 9.10 9.10 8.31 8.07 7.95 8.44 8.44 7.85 7.71 7.74 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-68 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Advanced Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 3.92 0.18 1.19 3.28 0.18 1.19 3.28 0.18 1.19 2.93 0.18 1.19 2.87 0.18 1.19 2.90 0.18 1.19 3.94 3.10 3.16 3.17 7.54 6.70 3.30 2.54 3.54 3.86 6.90 6.14 3.30 2.54 3.54 3.86 6.90 6.14 2.95 2.27 3.81 4.30 6.54 5.87 2.89 2.22 3.86 4.41 6.49 5.82 2.92 2.16 3.94 4.86 6.51 5.75 1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2. Software default selection highlighted in gray. 3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2- 50 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-69 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Plus Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 tDP 5.84 4.76 4.76 4.02 4.02 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL 5.86 4.78 4.78 4.04 4.04 tZH 5.04 4.33 4.33 3.78 3.78 tLZ 2.74 3.09 3.09 3.33 3.33 tHZ 2.71 3.33 3.33 3.73 3.73 tZLS 9.46 8.37 8.37 7.64 7.64 tZHS Units 8.64 7.93 7.93 7.37 7.37 ns ns ns ns ns 0.18 1.20 0.18 1.20 0.18 1.20 0.18 1.20 0.18 1.20 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-70 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Plus Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 tDP 3.33 2.75 2.75 2.45 2.45 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ 2.88 3.50 3.50 3.90 3.90 tZLS 6.94 6.36 6.36 6.06 6.06 tZHS 6.27 5.77 5.77 5.51 5.51 Units ns ns ns ns ns 0.18 1.20 0.18 1.20 0.18 1.20 0.18 1.20 0.18 1.20 3.35 2.68 2.73 2.77 2.17 3.08 2.77 2.17 3.08 2.47 1.92 3.33 2.47 1.92 3.33 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 9 2- 51 IGLOO DC and Switching Characteristics Table 2-71 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Banks Equivalent Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA Drive Strength 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 5.64 5.64 4.63 4.63 tDIN 0.18 0.18 0.18 0.18 tPY 1.17 1.17 1.17 1.17 tEOUT 0.66 0.66 0.66 0.66 tZL 5.65 5.65 4.64 4.64 tZH 4.98 4.98 4.26 4.26 tLZ 2.45 2.45 2.80 2.80 tHZ 2.42 2.42 3.02 3.02 Units ns ns ns ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-72 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Applicable to Standard Banks Equivalent Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA Drive Strength 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade 0.97 0.97 0.97 0.97 tDOUT 3.16 3.16 2.62 2.62 tDP 0.18 0.18 0.18 0.18 tDIN 1.17 1.17 1.17 1.17 tPY 0.66 0.66 0.66 0.66 tEOUT 3.17 3.17 2.63 2.63 tZL 2.53 2.53 2.02 2.02 tZH 2.45 2.45 2.79 2.79 tLZ 2.56 2.56 3.17 3.17 tHZ 0.97 0.97 0.97 0.97 Units ns ns ns ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 3. Software default selection highlighted in gray. 2- 52 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Applies to 1.2 V DC Core Voltage Table 2-73 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Applicable to Advanced Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 7.52 0.26 1.32 6.37 0.26 1.32 6.37 0.26 1.32 5.55 0.26 1.32 5.32 0.26 1.32 5.19 0.26 1.32 7.52 6.38 3.84 4.02 13.31 12.16 6.37 5.57 4.23 4.73 12.16 11.35 6.37 5.57 4.23 4.73 12.16 11.35 5.55 4.96 4.50 5.18 11.34 10.75 5.32 4.82 4.56 5.29 11.10 10.61 5.19 4.85 4.63 5.74 10.98 10.63 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-74 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 Applicable to Advanced Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY 1.32 1.32 1.32 1.32 1.32 1.32 tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 4.75 0.26 4.10 0.26 4.10 0.26 3.73 0.26 3.67 0.26 3.70 0.26 4.75 3.77 3.84 4.27 10.54 9.56 4.10 3.19 4.24 4.98 4.10 3.19 4.24 4.98 3.73 2.91 4.51 5.43 3.67 2.85 4.57 5.55 3.70 2.79 4.65 6.01 9.88 9.88 9.52 9.46 9.49 8.98 8.98 8.69 8.64 8.58 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 9 2- 53 IGLOO DC and Switching Characteristics Table 2-75 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 Applicable to Standard Plus Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 tZL 6.69 5.58 5.58 4.82 4.82 tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns 6.69 0.26 1.32 5.58 0.26 1.32 5.58 0.26 1.32 4.82 0.26 1.32 4.82 0.26 1.32 5.73 3.41 3.72 12.48 11.52 5.01 3.77 4.35 11.36 10.79 5.01 3.77 4.35 11.36 10.79 4.44 4.02 4.76 10.61 10.23 4.44 4.02 4.76 10.61 10.23 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-76 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 Applicable to Standard Plus Banks Equivalent Software Default Drive Strength Option1 4 mA 6 mA 8 mA 12 mA 16 mA Drive Strength 100 µA 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade tDOUT Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY 1.32 1.32 1.32 1.32 1.32 tEOUT 1.10 1.10 1.10 1.10 1.10 tZL 4.10 3.51 3.51 3.20 3.20 tZH 3.30 2.79 2.79 2.52 2.52 tLZ 3.40 3.76 3.76 4.01 4.01 tHZ 3.92 4.56 4.56 4.97 4.97 tZLS 9.89 9.30 9.30 8.99 8.99 tZHS Units 9.09 8.57 8.57 8.31 8.31 ns ns ns ns ns 4.10 0.26 3.51 0.26 3.51 0.26 3.20 0.26 3.20 0.26 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 3. Software default selection highlighted in gray. 2- 54 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-77 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 Applicable to Standard Banks Equivalent Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA Drive Strength 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 6.44 6.44 5.41 5.41 tDIN 0.26 0.26 0.26 0.26 tPY 1.29 1.29 1.29 1.29 tEOUT 1.10 1.10 1.10 1.10 tZL 6.44 6.44 5.41 5.41 tZH 5.64 5.64 4.91 4.91 tLZ 2.99 2.99 3.35 3.35 tHZ 3.28 3.28 3.89 3.89 Units ns ns ns ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-78 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 Applicable to Standard Banks Equivalent Software Default Drive Strength Option1 2 mA 4 mA 6 mA 8 mA Drive Strength 100 µA 100 µA 100 µA 100 µA Notes: Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 3.89 3.89 3.33 3.33 tDIN 0.26 0.26 0.26 0.26 tPY 1.29 1.29 1.29 1.29 tEOUT 1.10 1.10 1.10 1.10 tZL 3.89 3.89 3.33 3.33 tZH 3.13 3.13 2.62 2.62 tLZ 2.99 2.99 3.34 3.34 tHZ 3.45 3.45 4.07 4.07 Units ns ns ns ns 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ± 100 µA. Drive strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 1 9 2- 55 IGLOO DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 2.5 V applications. Table 2-79 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. V 0.7 0.7 0.7 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 VIH Max. V 2.7 2.7 2.7 2.7 2.7 2.7 2.7 VOL Max. V 0.7 0.7 0.7 0.7 0.7 0.7 0.7 VOH Min. V 1.7 1.7 1.7 1.7 1.7 1.7 1.7 IOL IOH mA mA 2 4 6 8 12 16 24 2 4 6 8 12 16 24 IOSH Max. mA3 16 16 32 32 65 83 169 IOSL Max. mA3 18 18 37 37 74 87 124 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 10 10 10 10 10 10 Table 2-80 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 –0.3 Max. V 0.7 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7 1.7 VIH Max. V 2.7 2.7 2.7 2.7 2.7 VOL Max. V 0.7 0.7 0.7 0.7 0.7 VOH Min. V 1.7 1.7 1.7 1.7 1.7 IOL IOH mA mA 2 4 6 8 12 2 4 6 8 12 IOSH Max. mA3 16 16 32 32 65 IOSL Max. mA3 18 18 37 37 74 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 10 10 2- 56 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-81 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 2.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 Max. V 0.7 0.7 0.7 0.7 Min. V 1.7 1.7 1.7 1.7 VIH Max. V 3.6 3.6 3.6 3.6 VOL Max. V 0.7 0.7 0.7 0.7 VOH Min. V 1.7 1.7 1.7 1.7 IOL IOH mA mA 2 4 6 8 2 4 6 8 IOSH Max. mA3 16 16 32 32 IOSL Max. mA3 18 18 37 37 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 Test Point Datapath 5 pF R=1k Test Point Enable Path R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-8 • AC Loading Table 2-82 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 2.5 Measuring Point* (V) 1.2 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points. R ev i si o n 1 9 2- 57 IGLOO DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-83 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.66 7.83 7.83 7.24 7.06 6.98 tZHS 8.19 7.53 7.53 7.06 6.95 6.98 Units ns ns ns ns ns ns 4.96 0.18 1.08 4.15 0.18 1.08 4.15 0.18 1.08 3.57 0.18 1.08 3.39 0.18 1.08 3.38 0.18 1.08 5.06 4.59 2.26 2.00 4.24 3.94 2.54 2.51 4.24 3.94 2.54 2.51 3.65 3.47 2.73 2.84 3.46 3.36 2.78 2.92 3.38 3.38 2.83 3.25 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-84 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.42 5.99 5.99 5.73 5.69 5.70 tZHS 6.19 5.68 5.68 5.43 5.38 5.32 Units ns ns ns ns ns ns 2.77 0.18 1.08 2.34 0.18 1.08 2.34 0.18 1.08 2.09 0.18 1.08 2.05 0.18 1.08 2.06 0.18 1.08 2.83 2.60 2.26 2.08 2.39 2.08 2.54 2.60 2.39 2.08 2.54 2.60 2.14 1.83 2.73 2.93 2.09 1.78 2.78 3.02 2.10 1.72 2.83 3.35 Table 2-85 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 8.10 7.29 7.29 6.74 tZHS 7.69 7.11 7.11 6.68 Units ns ns ns ns 4.42 0.18 1.08 3.62 0.18 1.08 3.62 0.18 1.08 3.09 0.18 1.08 4.51 4.10 1.96 1.85 3.70 3.52 2.21 2.32 3.70 3.52 2.21 2.32 3.15 3.09 2.39 2.61 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 58 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-86 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS tZHS 5.81 5.34 5.34 5.11 Units ns ns ns ns 2.36 0.18 1.08 1.97 0.18 1.08 1.97 0.18 1.08 1.75 0.18 1.08 2.41 2.21 1.96 1.92 6.01 2.01 1.75 2.21 2.40 5.61 2.01 1.75 2.21 2.40 5.61 1.79 1.52 2.38 2.70 5.39 Table 2-87 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 4.27 4.27 3.54 3.54 tDIN 0.18 0.18 0.18 0.18 tPY 1.04 1.04 1.04 1.04 tEOUT 0.66 0.66 0.66 0.66 tZL 4.36 4.36 3.61 3.61 tZH 4.06 4.06 3.48 3.48 tLZ 1.71 1.71 1.95 1.95 tHZ 1.62 1.62 2.08 2.08 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-88 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP 2.24 2.24 1.88 1.88 tDIN 0.18 0.18 0.18 0.18 tPY 1.04 1.04 1.04 1.04 tEOUT 0.66 0.66 0.66 0.66 tZL 2.29 2.29 1.92 1.92 tZH 2.09 2.09 1.63 1.63 tLZ 1.71 1.71 1.95 1.95 tHZ 1.68 1.68 2.15 2.15 Units ns ns ns ns R ev i si o n 1 9 2- 59 IGLOO DC and Switching Characteristics Applies to 1.2 V Core Voltage Table 2-89 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 5.59 0.26 1.20 4.76 0.26 1.20 4.76 0.26 1.20 4.17 0.26 1.20 3.98 0.26 1.20 3.90 0.26 1.20 5.68 5.14 2.82 2.80 11.47 10.93 4.84 4.47 3.10 3.33 10.62 10.26 4.84 4.47 3.10 3.33 10.62 10.26 4.23 3.99 3.30 3.67 10.02 4.04 3.88 3.34 3.76 3.96 3.90 3.40 4.09 9.83 9.75 9.77 9.66 9.68 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-90 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Advanced I/O Banks Drive Strength 4 mA 6 mA 8 mA 12 mA 16 mA 24 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.17 8.72 8.72 8.46 8.41 8.42 tZHS 8.88 8.34 8.34 8.08 8.03 7.97 Units ns ns ns ns ns ns 3.33 0.26 1.20 2.89 0.26 1.20 2.89 0.26 1.20 2.64 0.26 1.20 2.59 0.26 1.20 2.60 0.26 1.20 3.38 3.09 2.82 2.91 2.93 2.56 3.10 3.45 2.93 2.56 3.10 3.45 2.67 2.29 3.30 3.79 2.63 2.24 3.34 3.88 2.64 2.18 3.40 4.22 Table 2-91 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS tZHS Units ns ns ns ns 5.02 0.26 1.19 4.21 0.26 1.19 4.21 0.26 1.19 3.66 0.26 1.19 5.11 4.60 2.50 2.62 10.89 10.38 4.27 4.00 2.76 3.10 10.06 4.27 4.00 2.76 3.10 10.06 3.71 3.55 2.94 3.41 9.50 9.79 9.79 9.34 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 60 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-92 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Plus Banks Drive Strength 4 mA 6 mA 8 mA 12 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 8.74 8.33 8.33 8.10 tZHS 8.45 7.97 7.97 7.73 Units ns ns ns ns 2.91 0.26 1.19 2.51 0.26 1.19 2.51 0.26 1.19 2.29 0.26 1.19 2.95 2.66 2.50 2.72 2.54 2.18 2.75 3.21 2.54 2.18 2.75 3.21 2.32 1.94 2.94 3.52 Table 2-93 • 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 4.85 4.85 4.09 4.09 tDIN 0.26 0.26 0.26 0.26 tPY 1.15 1.15 1.15 1.15 tEOUT 1.10 1.10 1.10 1.10 tZL 4.93 4.93 4.16 4.16 tZH 4.55 4.55 3.95 3.95 tLZ 2.13 2.13 2.38 2.38 tHZ 2.24 2.24 2.71 2.71 Units ns ns ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-94 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Applicable to Standard Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP 2.76 2.76 2.39 2.39 tDIN 0.26 0.26 0.26 0.26 tPY 1.15 1.15 1.15 1.15 tEOUT 1.10 1.10 1.10 1.10 tZL 2.80 2.80 2.42 2.42 tZH 2.52 2.52 2.05 2.05 tLZ 2.13 2.13 2.38 2.38 tHZ 2.32 2.32 2.80 2.80 Units ns ns ns ns R ev i si o n 1 9 2- 61 IGLOO DC and Switching Characteristics 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-95 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max. V Min. V VIH Max. V 1.9 1.9 1.9 1.9 1.9 1.9 VOL Max. V 0.45 0.45 0.45 0.45 0.45 0.45 VOH Min. V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH mA mA 2 4 6 8 2 4 6 8 12 16 IOSH Max. mA3 9 17 35 45 91 91 IOSL Max. mA3 11 22 44 51 74 74 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI VCCI – 0.45 12 VCCI – 0.45 16 Table 2-96 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 –0.3 –0.3 Max. V Min. V VIH Max. V 1.9 1.9 1.9 1.9 VOL Max. V 0.45 0.45 0.45 0.45 VOH Min. V VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 VCCI – 0.45 IOL IOH mA mA 2 4 6 8 2 4 6 8 IOSH Max. mA3 9 17 35 35 IOSL Max. mA3 11 22 44 44 IIL1 IIH2 µA4 µA4 10 10 10 10 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 2- 62 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-97 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.8 V LVCMOS Drive Strength 2 mA 4 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 Max. V Min. V VIH Max. V 3.6 3.6 VOL Max. V 0.45 0.45 VOH Min. V VCCI – 0.45 VCCI – 0.45 IOL IOH mA mA 2 4 2 4 IOSH Max. mA3 9 17 IOSL Max. mA3 11 22 IIL1 IIH2 µA4 µA4 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI Test Point Datapath 5 pF R=1k Test Point Enable Path R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 35 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-9 • AC Loading Table 2-98 • AC Waveforms, Measuring Points, and Capacitive Loads Input Low (V) 0 Input High (V) 1.8 Measuring Point* (V) 0.9 CLOAD (pF) 5 * Measuring point = Vtrip. See Table 2-29 on page 2-28 for a complete table of trip points. Timing Characteristics 1.5 V DC Core Voltage Table 2-99 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Std. Std. Std. Std. Std. Std. 0.97 0.97 0.97 0.97 0.97 0.97 tDP 6.38 5.35 4.62 4.37 4.32 4.32 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL 6.51 5.46 4.71 4.46 4.37 4.37 tZH 5.93 5.04 4.44 4.31 4.32 4.32 tLZ tHZ tZLS tZHS 9.53 8.64 8.04 7.90 7.92 7.92 Units ns ns ns ns ns ns 0.18 1.01 0.18 1.01 0.18 1.01 0.18 1.01 0.18 1.01 0.18 1.01 2.33 1.56 10.10 2.67 2.38 2.90 2.79 2.95 2.89 3.03 3.30 3.03 3.30 9.05 8.31 8.05 7.97 7.97 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. R ev i si o n 1 9 2- 63 IGLOO DC and Switching Characteristics Table 2-100 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.80 6.27 5.95 5.89 5.88 5.88 tZHS 6.85 6.11 5.75 5.68 5.60 5.60 Units ns ns ns ns ns ns 3.25 0.18 1.01 2.62 0.18 1.01 2.31 0.18 1.01 2.25 0.18 1.01 2.24 0.18 1.01 2.24 0.18 1.01 3.21 3.25 2.33 1.61 2.68 2.51 2.66 2.46 2.36 2.15 2.90 2.87 2.30 2.08 2.95 2.98 2.29 2.00 3.02 3.40 2.29 2.00 3.02 3.40 Table 2-101 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength Speed Grade tDOUT 2 mA 4 mA 6 mA 8 mA Std. Std. Std. Std. 0.97 0.97 0.97 0.97 tDP 5.78 4.75 4.07 4.07 tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL 5.90 4.85 4.15 4.15 tZH 5.32 4.54 3.98 3.98 tLZ tHZ tZLS 9.49 8.44 7.75 7.75 tZHS 8.91 8.13 7.57 7.57 Units ns ns ns ns 0.18 1.01 0.18 1.01 0.18 1.01 0.18 1.01 1.95 1.47 2.25 2.21 2.46 2.58 2.46 2.58 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-102 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 0.97 0.97 0.97 0.97 tDP tDIN tPY tEOUT 0.66 0.66 0.66 0.66 tZL tZH tLZ tHZ tZLS 6.39 5.89 5.61 5.61 tZHS 6.35 5.69 5.36 5.36 Units ns ns ns ns 2.76 0.18 1.01 2.25 0.18 1.01 1.97 0.18 1.01 1.97 0.18 1.01 2.79 2.76 1.94 1.51 2.30 2.09 2.24 2.29 2.02 1.76 2.46 2.66 2.02 1.76 2.46 2.66 Table 2-103 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 0.97 0.97 tDP 5.63 4.69 tDIN 0.18 0.18 tPY 0.98 0.98 tEOUT 0.66 0.66 tZL 5.74 4.79 tZH 5.30 4.52 tLZ 1.68 1.97 tHZ 1.24 1.98 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. 2- 64 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-104 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Speed Grade Std. Std. tDOUT 2.62 2.18 tDP 0.18 0.18 tDIN 0.98 0.98 tPY 0.66 0.66 tEOUT 2.67 2.22 tZL 2.59 1.93 tZH 1.67 1.97 tLZ 1.29 2.06 tHZ 2.62 2.18 Units ns ns R ev i si o n 1 9 2- 65 IGLOO DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-105 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength Speed Grade tDOUT 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Std. Std. Std. Std. Std. Std. 1.55 1.55 1.55 1.55 1.55 1.55 tDP 6.97 5.91 5.16 4.90 4.83 4.83 tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL 7.08 6.01 5.24 4.98 4.90 4.90 tZH 6.48 5.57 4.95 4.81 4.83 4.83 tLZ tHZ tZLS tZHS Units ns ns ns ns ns ns 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 2.87 2.29 12.87 12.27 3.21 3.14 11.79 11.36 3.45 3.55 11.03 10.74 3.50 3.66 10.77 10.60 3.58 4.08 10.68 10.61 3.58 4.08 10.68 10.61 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-106 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Advanced I/O Banks Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA 16 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.49 8.95 8.62 8.56 8.55 8.55 tZHS 9.51 8.75 8.38 8.30 8.22 8.22 Units ns ns ns ns ns ns 3.73 0.26 1.11 3.12 0.26 1.11 2.79 0.26 1.11 2.73 0.26 1.11 2.72 0.26 1.11 2.72 0.26 1.11 3.71 3.73 2.86 2.34 3.16 2.97 3.21 3.22 2.83 2.59 3.45 3.65 2.77 2.52 3.50 3.75 2.76 2.43 3.58 4.19 2.76 2.43 3.58 4.19 Table 2-107 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength Speed Grade tDOUT 2 mA 4 mA 6 mA 8 mA Std. Std. Std. Std. 1.55 1.55 1.55 1.55 tDP 6.32 5.27 4.56 4.56 tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL 6.43 5.35 4.64 4.64 tZH 5.81 5.01 4.44 4.44 tLZ tHZ tZLS tZHS Units ns ns ns ns 0.26 1.11 0.26 1.11 0.26 1.11 0.26 1.11 2.47 2.16 12.22 11.60 2.78 2.92 11.14 10.79 3.00 3.30 10.42 10.22 3.00 3.30 10.42 10.22 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 66 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-108 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Plus Banks Drive Strength 2 mA 4 mA 6 mA 8 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. Std. Std. tDOUT 1.55 1.55 1.55 1.55 tDP tDIN tPY tEOUT 1.10 1.10 1.10 1.10 tZL tZH tLZ tHZ tZLS 9.05 8.54 8.25 8.25 tZHS 8.97 8.29 7.94 7.94 Units ns ns ns ns 3.22 0.26 1.11 2.72 0.26 1.11 2.43 0.26 1.11 2.43 0.26 1.11 3.26 3.18 2.47 2.20 2.75 2.50 2.78 3.01 2.47 2.16 2.99 3.39 2.47 2.16 2.99 3.39 Table 2-109 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Speed Grade Std. Std. tDOUT 1.55 1.55 tDP 6.13 5.17 tDIN 0.26 0.26 tPY 1.08 1.08 tEOUT 1.10 1.10 tZL 6.24 5.26 tZH 5.79 4.98 tLZ 2.08 2.38 tHZ 1.78 2.54 Units ns ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-110 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Applicable to Standard Banks Drive Strength 2 mA 4 mA Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Speed Grade Std. Std. tDOUT 3.06 2.60 tDP 0.26 0.26 tDIN 1.08 1.08 tPY 1.10 1.10 tEOUT 3.10 2.64 tZL 3.01 2.33 tZH 2.08 2.38 tLZ 1.83 2.62 tHZ 3.06 2.60 Units ns ns R ev i si o n 1 9 2- 67 IGLOO DC and Switching Characteristics 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for generalpurpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-111 • Minimum and Maximum DC Input and Output Levels Applicable to Advanced I/O Banks 1.5 V LVCMOS Drive Strength 2 mA 4 mA 6 mA 8 mA 12 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V Max. V VIH Min. V Max. V VOL Max. V 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI 0.25 * VCCI VOH Min. V 0.75 * VCCI 0.75 * VCCI 0.75 * VCCI 0.75 * VCCI IOL IOH IOSH mA mA 2 4 6 8 2 4 6 8 12 Max. mA3 13 25 32 66 66 IOSL IIL1 IIH2 Max. mA3 µA4 µA4 16 33 39 55 55 10 10 10 10 10 10 10 10 10 10 –0.3 0.35 * VCCI 0.65 * VCCI 1.575 –0.3 0.35 * VCCI 0.65 * VCCI 1.575 –0.3 0.35 * VCCI 0.65 * VCCI 1.575 –0.3 0.35 * VCCI 0.65 * VCCI 1.575 –0.3 0.35 * VCCI 0.65 * VCCI 1.575 0.75 * VCCI 12 Table 2-112 • Minimum and Maximum DC Input and Output Levels Applicable to Standard Plus I/O Banks 1.5 V LVCMOS Drive Strength 2 mA 4 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges 3. Currents are measured at 100°C junction temperature and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. VIL Min. V –0.3 –0.3 Max. V Min. V VIH Max. V 1.575 1.575 VOL Max. V VOH Min. V IOL IOH IOSH mA mA 2 4 2 4 Max. mA3 13 25 IOSL IIL1 IIH2 Max. mA3 µA4 µA4 16 33 10 10 10 10 0.35 * VCCI 0.65 * VCCI 0.35 * VCCI 0.65 * VCCI 0.25 * VCCI 0.75 * VCCI 0.25 * VCCI 0.75 * VCCI 2- 68 R ev i sio n 1 9 IGLOO Low Power Flash FPGAs Table 2-113 • Minimum and Maximum DC Input and Output Levels Applicable to Standard I/O Banks 1.5 V LVCMOS Drive Strength 2 mA Notes: 1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN