AGLN-NANO-KIT

Revision 20 DS0110 IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology Features and Benefits High-Performance Routing Hierarchy Low Power Advanced I/Os • Segmented, Hierarchical Routing and Clock Structure • • • • • nanoPower Consumption—Industry’s Lowest Power 1.2 V to 1.5 V Core Voltage Support for Low Power Supports Single-Voltage System Operation Low Power Active FPGA Operation Flash*Freeze Technology Enables Ultra-Low Power Consumption while Maintaining FPGA Content • Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode • 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation • Bank-Selectable I/O Voltages—up to 4 Banks per Chip • Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V • Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V • Wide Range Power Supply Voltage Support per JESD8-12, Allowing I/Os to Operate from 1.14 V to 1.575 V • I/O Registers on Input, Output, and Enable Paths • Selectable Schmitt Trigger Inputs • Hot-Swappable and Cold-Sparing I/Os • Programmable Output Slew Rate and Drive Strength • Weak Pull-Up/-Down • IEEE 1149.1 (JTAG) Boundary Scan Test • Pin-Compatible Packages across the IGLOO® Family † Small Footprint Packages • As Small as 3x3 mm in Size Wide Range of Features • 10,000 to 250,000 System Gates • Up to 36 kbits of True Dual-Port SRAM • Up to 71 User I/Os Reprogrammable Flash Technology • • • • • 130-nm, 7-Layer Metal, Flash-Based CMOS Process Instant On Level 0 Support Single-Chip Solution Retains Programmed Design When Powered Off 250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance In-System Programming (ISP) and Security • ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant) • FlashLock® Designed to Secure FPGA Contents • 1.2 V Programming Clock Conditioning Circuit (CCC) and PLL • Up to Six CCC Blocks, One with an Integrated PLL • Configurable Phase Shift, Multiply/Divide, Delay Capabilities, and External Feedback • Wide Input Frequency Range (1.5 MHz up to 250 MHz) Embedded Memory • 1 kbit of FlashROM User Nonvolatile Memory • SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)† • True Dual-Port SRAM (except × 18 organization)† Enhanced Commercial Temperature Range • Tj = -20°C to +85°C IGLOO nano Devices System Gates AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 10,000 20,000 60,000 125,000 250,000 Typical Equivalent Macrocells 86 172 512 1,024 2,048 VersaTiles (D-flip-flops) 260 520 1,536 3,072 6,144 Flash*Freeze Mode (typical, µW) 2 4 10 16 24 RAM Kbits (1,024 bits)2 – – 18 36 36 4,608-Bit Blocks2 – – 4 8 8 FlashROM Kbits (1,024 bits) 1 1 1 1 1 Secure (AES) ISP2 – – Yes Yes Yes Integrated PLL in CCCs 2,3 – – 1 1 1 VersaNet Globals 4 4 18 18 18 I/O Banks 2 3 2 2 4 Maximum User I/Os (packaged device) 34 52 71 71 68 Maximum User I/Os (Known Good Die) 34 52 71 71 68 UC36 QN48 CS81 QN68 CS81 CS81 CS81 VQ100 VQ100 VQ100 Package Pins UC/CS QFN VQFP Notes: 1. AGLN030 and smaller devices do not support this feature. 2. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. 3. For higher densities and support of additional features, refer to the DS0095: IGLOO Low Power Flash FPGAs Datasheet and IGLOOe Low-Power Flash FPGAs Datasheet . † AGLN030 and smaller devices do not support this feature. October 2019 © 2019 Microsemi Corporation I I/Os Per Package IGLOO nano Devices AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 Known Good Die 34 52 71 71 68 UC36 23 – – – – QN48 34 – – – – QN68 – 49 – – – UC81 – – – – – CS81 – 52 60 60 60 VQ100 – – 71 71 68 Notes: 1. When considering migrating your design to a lower- or higher-density device, refer to the DS0095: IGLOO Low Power Flash FPGAs Datasheet and IGLOO FPGA Fabric User’s Guide to ensure compliance with design and board migration requirements. 2. When the Flash*Freeze pin is used to directly enable Flash*Freeze mode and not used as a regular I/O, the number of single-ended user I/Os available is reduced by one. 3. "G" indicates RoHS-compliant packages. Refer to "IGLOO nano Ordering Information" on page IV for the location of the "G" in the part number. For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only. Table 1 • IGLOO nano FPGAs Package Sizes Dimensions Packages UC36 UC81 CS81 QN48 QN68 VQ100 Length × Width (mm\mm) 3x3 4x4 5x5 6x6 8x8 14 x 14 9 16 25 36 64 196 Nominal Area (mm2) Pitch (mm) 0.4 0.4 0.5 0.4 0.4 0.5 Height (mm) 0.80 0.80 0.80 0.90 0.90 1.20 II R evis i o n 20 IGLOO nano Low Power Flash FPGAs IGLOO nano Device Status IGLOO nano Devices Status AGLN010 Production AGLN020 Production AGLN060 Production AGLN125 Production AGLN250 Production IGLOO nano-Z Devices R ev i si o n 2 0 Status III IGLOO nano Ordering Information AGLN250 V2 _ Z G VQ 100 Y I Application (Temperature Range) Blank = Enhanced Commercial (–20°C to +85°C Junction Temperature) I = Industrial (–40°C to +100°C Junction Temperature) PP = Pre-Production ES = Engineering Sample (Room Temperature Only) Security Feature Y = Device Includes License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Blank = Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio Note: Only devices with packages greater than or equal to 5x5 are supported. Package Lead Count Lead-Free Packaging Blank = Standard Packaging G= RoHS-Compliant Packaging Package Type UC = Micro Chip Scale Package (0.4 mm pitch) CS = Chip Scale Package (0.5 mm pitch) QN = Quad Flat Pack No Leads (0.4 mm and 0.5 mm pitches) VQ = Very Thin Quad Flat Pack (0.5 mm pitch) DIELOT = Known Good Die Blank = Standard Supply Voltage 2 = 1.2 V to 1.5 V 5 = 1.5 V only Part Number IGLOO nano Devices AGLN010 = 10,000 System Gates AGLN020 = 20,000 System Gates AGLN030 = 30,000 System Gates AGLN060 = 60,000 System Gates AGLN125 = 125,000 System Gates AGLN250 = 250,000 System Gates Notes: 1. Marking Information: IGLOO nano V2 devices do not have a V2 marking, but IGLOO nano V5 devices are marked with a V5 designator. Devices Not Recommended For New Designs IV Revision 20 IGLOO nano Low Power Flash FPGAs Device Marking Microsemi normally topside marks the full ordering part number on each device. There are some exceptions to this, such as the V2 designator for IGLOO devices and packages where space is physically limited. Packages that have limited characters available are UC36, UC81, CS81, QN48, QN68, and QFN132. On these specific packages, a subset of the device marking will be used that includes the required legal information and as much of the part number as allowed by character limitation of the device. In this case, devices will have a truncated device marking and may exclude the applications markings, such as the I designator for Industrial Devices or the ES designator for Engineering Samples. Figure 1 shows an example of device marking based on the AGLN250V2-CSG81. The actual mark will vary by the device/package combination ordered. Device Name (seven characters) Package ACTEL AGLN250 CSG81 YYWW XXXXXXXX Product Temperature Grade Figure 1 • X Date Code Wafer Lot # XXX Country of Origin Example of Device Marking for Small Form Factor Packages Temperature Grade Offerings Package AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 UC36 C, I – – – – QN48 C, I – – – – QN68 – C, I – – – UC81 – – – – – CS81 – C, I C, I C, I C, I VQ100 – – C, I C, I C, I C = Enhanced Commercial temperature range: –20°C to +85°C junction temperature I = Industrial temperature range: –40°C to +100°C junction temperature Contact your local Microsemi representative for device availability: http://www.microsemi.com/soc/contact/default.aspx. R ev i si o n 2 0 V IGLOO nano Low Power Flash FPGAs Table of Contents IGLOO nano Device Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 IGLOO nano DC and Switching Characteristics General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Calculating Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 User I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 VersaTile Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-57 Global Resource Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-63 Clock Conditioning Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70 Embedded SRAM and FIFO Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-73 Embedded FlashROM Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87 JTAG 1532 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-88 Pin Descriptions Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . User Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JTAG Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Function Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-3 3-4 3-4 3-5 Package Pin Assignments UC36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 UC81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 CS81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 QN48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 QN68 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 VQ100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 Datasheet Information List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Safety Critical, Life Support, and High-Reliability Applications Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 R ev i si o n 2 0 VI 1 – IGLOO nano Device Overview General Description The IGLOO family of flash FPGAs, based on a 130-nm flash process, offers the lowest power FPGA, a single-chip solution, small footprint packages, reprogrammability, and an abundance of advanced features. The Flash*Freeze technology used in IGLOO nano devices enables entering and exiting an ultra-low power mode that consumes nanoPower while retaining SRAM and register data. Flash*Freeze technology simplifies power management through I/O and clock management with rapid recovery to operation mode. The Low Power Active capability (static idle) allows for ultra-low power consumption while the IGLOO nano device is completely functional in the system. This allows the IGLOO nano device to control system power management based on external inputs (e.g., scanning for keyboard stimulus) while consuming minimal power. Nonvolatile flash technology gives IGLOO nano devices the advantage of being a secure, low power, single-chip solution that is Instant On. The IGLOO nano device is reprogrammable and offers time-tomarket benefits at an ASIC-level unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA design flows and tools. IGLOO nano devices offer 1 kbit of on-chip, reprogrammable, nonvolatile FlashROM storage as well as clock conditioning circuitry based on an integrated phase-locked loop (PLL). The AGLN030 and smaller devices have no PLL or RAM support. IGLOO nano devices have up to 250 k system gates, supported with up to 36 kbits of true dual-port SRAM and up to 71 user I/Os. IGLOO nano devices increase the breadth of the IGLOO product line by adding new features and packages for greater customer value in high volume consumer, portable, and battery-backed markets. Features such as smaller footprint packages designed with two-layer PCBs in mind, power consumption measured in nanoPower, Schmitt trigger, and bus hold (hold previous I/O state in Flash*Freeze mode) functionality make these devices ideal for deployment in applications that require high levels of flexibility and low cost. Flash*Freeze Technology The IGLOO nano device offers unique Flash*Freeze technology, allowing the device to enter and exit ultra-low power Flash*Freeze mode. IGLOO nano devices do not need additional components to turn off I/Os or clocks while retaining the design information, SRAM content, and registers. Flash*Freeze technology is combined with in-system programmability, which enables users to quickly and easily upgrade and update their designs in the final stages of manufacturing or in the field. The ability of IGLOO nano V2 devices to support a wide range of core voltage (1.2 V to 1.5 V) allows further reduction in power consumption, thus achieving the lowest total system power. During Flash*Freeze mode, each I/O can be set to the following configurations: hold previous state, tristate, HIGH, or LOW. The availability of low power modes, combined with reprogrammability, a single-chip and single-voltage solution, and small-footprint packages make IGLOO nano devices the best fit for portable electronics. R ev i si o n 2 0 1-1 IGLOO nano Device Overview Flash Advantages Low Power Flash-based IGLOO nano devices exhibit power characteristics similar to those of an ASIC, making them an ideal choice for power-sensitive applications. IGLOO nano devices have only a very limited power-on current surge and no high-current transition period, both of which occur on many FPGAs. IGLOO nano devices also have low dynamic power consumption to further maximize power savings; power is reduced even further by the use of a 1.2 V core voltage. Low dynamic power consumption, combined with low static power consumption and Flash*Freeze technology, gives the IGLOO nano device the lowest total system power offered by any FPGA. Security Nonvolatile, flash-based IGLOO nano devices do not require a boot PROM, so there is no vulnerable external bitstream that can be easily copied. IGLOO nano devices incorporate FlashLock, which provides a unique combination of reprogrammability and design security without external overhead, advantages that only an FPGA with nonvolatile flash programming can offer. IGLOO nano devices utilize a 128-bit flash-based lock and a separate AES key to provide the highest level of security in the FPGA industry for programmed intellectual property and configuration data. In addition, all FlashROM data in IGLOO nano devices can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher encryption standard. AES was adopted by the National Institute of Standards and Technology (NIST) in 2000 and replaces the 1977 DES standard. IGLOO nano devices have a built-in AES decryption engine and a flash-based AES key that make them the most comprehensive programmable logic device security solution available today. IGLOO nano devices with AES-based security provide a high level of protection for remote field updates over public networks such as the Internet, and are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP thieves. Security, built into the FPGA fabric, is an inherent component of IGLOO nano devices. The flash cells are located beneath seven metal layers, and many device design and layout techniques have been used to make invasive attacks extremely difficult. IGLOO nano devices, with FlashLock and AES security, are unique in being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-standard security, making remote ISP possible. An IGLOO nano device provides the best available security for programmable logic designs. Single Chip Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the configuration data is an inherent part of the FPGA structure, and no external configuration data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based IGLOO nano FPGAs do not require system configuration components such as EEPROMs or microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system reliability. Instant On Microsemi flash-based IGLOO nano devices support Level 0 of the Instant On classification standard. This feature helps in system component initialization, execution of critical tasks before the processor wakes up, setup and configuration of memory blocks, clock generation, and bus activity management. The Instant On feature of flash-based IGLOO nano devices greatly simplifies total system design and reduces total system cost, often eliminating the need for CPLDs and clock generation PLLs. In addition, glitches and brownouts in system power will not corrupt the IGLOO nano device's flash configuration, and unlike SRAM-based FPGAs, the device will not have to be reloaded when system power is restored. This enables the reduction or complete removal of the configuration PROM, expensive voltage monitor, brownout detection, and clock generator devices from the PCB design. Flash-based IGLOO nano devices simplify total system design and reduce cost and design risk while increasing system reliability and improving system initialization time. IGLOO nano flash FPGAs enable the user to quickly enter and exit Flash*Freeze mode. This is done almost instantly (within 1 µs) and the device retains configuration and data in registers and RAM. Unlike SRAM-based FPGAs, the device does not need to reload configuration and design state from external memory components; instead it retains all necessary information to resume operation immediately. 1- 2 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Reduced Cost of Ownership Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike SRAM-based FPGAs, flash-based IGLOO nano devices allow all functionality to be Instant On; no external boot PROM is required. On-board security mechanisms prevent access to all the programming information and enable secure remote updates of the FPGA logic. Designers can perform secure remote in-system reprogramming to support future design iterations and field upgrades with confidence that valuable intellectual property cannot be compromised or copied. Secure ISP can be performed using the industry-standard AES algorithm. The IGLOO nano device architecture mitigates the need for ASIC migration at higher user volumes. This makes IGLOO nano devices cost-effective ASIC replacement solutions, especially for applications in the consumer, networking/communications, computing, and avionics markets. With a variety of devices under $1, IGLOO nano FPGAs enable cost-effective implementation of programmable logic and quick time to market. Firm-Error Immunity Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere, strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way. These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be a complete system failure. Firm errors do not exist in the configuration memory of IGLOO nano flash-based FPGAs. Once it is programmed, the flash cell configuration element of IGLOO nano FPGAs cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft) errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error detection and correction (EDAC) circuitry built into the FPGA fabric. Advanced Flash Technology The IGLOO nano device offers many benefits, including nonvolatility and reprogrammability, through an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS design techniques are used to implement logic and control functions. The combination of fine granularity, enhanced flexible routing resources, and abundant flash switches allows for very high logic utilization without compromising device routability or performance. Logic functions within the device are interconnected through a four-level routing hierarchy. IGLOO nano FPGAs utilize design and process techniques to minimize power consumption in all modes of operation. Advanced Architecture The proprietary IGLOO nano architecture provides granularity comparable to standard-cell ASICs. The IGLOO nano device consists of five distinct and programmable architectural features (Figure 1-3 on page 1-5 to Figure 1-4 on page 1-5): • Flash*Freeze technology • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory† • Extensive CCCs and PLLs† • Advanced I/O structure The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the IGLOO nano core tile as either a three-input lookup table (LUT) equivalent or a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC® family of third-generation-architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. † The AGLN030 and smaller devices do not support PLL or SRAM. R ev i si o n 2 0 1-3 IGLOO nano Device Overview Bank 1* I/Os Bank 1 Bank 0 VersaTile User Nonvolatile FlashROM Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Note: *Bank 0 for the AGLN030 device Figure 1-1 • IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030) Bank 1 I/Os Bank 2 Bank 0 VersaTile User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps CCC-GL Bank 1 Figure 1-2 • 1- 4 IGLOO Device Architecture Overview with Three I/O Banks and No RAM (AGLN020) R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs . Bank 0 Bank 0 Bank 1 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block I/Os ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology Charge Pumps Bank 0 Bank 1 VersaTile Bank 1 Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125) Bank 0 Bank 1 Bank 3 CCC RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block Bank 1 Bank 3 I/Os ISP AES Decryption User Nonvolatile FlashRom Flash*Freeze Technology VersaTile Charge Pumps Bank 2 Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250) R ev i si o n 2 0 1-5 IGLOO nano Device Overview Flash*Freeze Technology The IGLOO nano device has an ultra-low power static mode, called Flash*Freeze mode, which retains all SRAM and register information and can still quickly return to normal operation. Flash*Freeze technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the Flash*Freeze pin while all power supplies are kept at their original values. I/Os, global I/Os, and clocks can still be driven and can be toggling without impact on power consumption, and the device retains all core registers, SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state or be tristated during Flash*Freeze mode. Alternatively, I/Os can be set to a specific state using weak pull-up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins, or PLL, and the device consumes as little as 2 µW in this mode. Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power management of the device. The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide when it is safe to transition to this mode. Refer to Figure 1-5 for an illustration of entering/exiting Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode usage is not planned. IGLOO nano FPGA Flash*Freeze Mode Control Flash*Freeze Pin Figure 1-5 • IGLOO nano Flash*Freeze Mode VersaTiles The IGLOO nano core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS® core tiles. The IGLOO nano VersaTile supports the following: • All 3-input logic functions—LUT-3 equivalent • Latch with clear or set • D-flip-flop with clear or set • Enable D-flip-flop with clear or set Refer to Figure 1-6 for VersaTile configurations. LUT-3 Equivalent X1 X2 X3 LUT-3 Y D-Flip-Flop with Clear or Set Data CLK CLR Y D-FF Enable D-Flip-Flop with Clear or Set Data CLK Enable CLR Figure 1-6 • 1- 6 VersaTile Configurations R ev isio n 2 0 Y D-FF IGLOO nano Low Power Flash FPGAs User Nonvolatile FlashROM IGLOO nano devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The FlashROM can be used in diverse system applications: • Internet protocol addressing (wireless or fixed) • System calibration settings • Device serialization and/or inventory control • Subscription-based business models (for example, set-top boxes) • Secure key storage for secure communications algorithms • Asset management/tracking • Date stamping • Version management The FlashROM is written using the standard IGLOO nano IEEE 1532 JTAG programming interface. The core can be individually programmed (erased and written), and on-chip AES decryption can be used selectively to securely load data over public networks (except in the AGLN030 and smaller devices), as in security keys stored in the FlashROM for a user design. The FlashROM can be programmed via the JTAG programming interface, and its contents can be read back either through the JTAG programming interface or via direct FPGA core addressing. Note that the FlashROM can only be programmed from the JTAG interface and cannot be programmed from the internal logic array. The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8 banks and which of the 16 bytes within that bank are being read. The three most significant bits (MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of the FlashROM address define the byte. The IGLOO nano development software solutions, Libero® System-on-Chip (SoC) and Designer, have extensive support for the FlashROM. One such feature is auto-generation of sequential programming files for applications requiring a unique serial number in each part. Another feature enables the inclusion of static data for system version control. Data for the FlashROM can be generated quickly and easily using Microsemi Libero SoC and Designer software tools. Comprehensive programming file support is also included to allow for easy programming of large numbers of parts with differing FlashROM contents. SRAM and FIFO IGLOO nano devices (except the AGLN030 and smaller devices) have embedded SRAM blocks along their north and south sides. Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be configured with different bit widths on each port. For example, data can be sent through a 4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port (ROM emulation mode) using the UJTAG macro (except in the AGLN030 and smaller devices). In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control unit contains the counters necessary for generation of the read and write address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations. PLL and CCC Higher density IGLOO nano devices using either the two I/O bank or four I/O bank architectures provide designers with very flexible clock conditioning capabilities. AGLN060, AGLN125, and AGLN250 contain six CCCs. One CCC (center west side) has a PLL. The AGLN030 and smaller devices use different CCCs in their architecture (CCC-GL). These CCC-GLs contain a global MUX but do not have any PLLs or programmable delays. For devices using the six CCC block architecture, these are located at the four corners and the centers of the east and west sides. All six CCC blocks are usable; the four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine access. R ev i si o n 2 0 1-7 IGLOO nano Device Overview The inputs of the six CCC blocks are accessible from the FPGA core or from dedicated connections to the CCC block, which are located near the CCC. The CCC block has these key features: • Wide input frequency range (fIN_CCC) = 1.5 MHz up to 250 MHz • Output frequency range (fOUT_CCC) = 0.75 MHz up to 250 MHz • 2 programmable delay types for clock skew minimization • Clock frequency synthesis (for PLL only) Additional CCC specifications: • Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider configuration (for PLL only). • Output duty cycle = 50% ± 1.5% or better (for PLL only) • Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global network used (for PLL only) • Maximum acquisition time is 300 µs (for PLL only) • Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only) • Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz / fOUT_CCC (for PLL only) Global Clocking IGLOO nano devices have extensive support for multiple clocking domains. In addition to the CCC and PLL support described above, there is a comprehensive global clock distribution network. Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid distribution of high-fanout nets. I/Os with Advanced I/O Standards IGLOO nano FPGAs feature a flexible I/O structure, supporting a range of voltages (1.2 V, 1.2 V wide range, 1.5 V, 1.8 V, 2.5 V, 3.0 V wide range, and 3.3 V). The I/Os are organized into banks with two, three, or four banks per device. The configuration of these banks determines the I/O standards supported. Each I/O module contains several input, output, and enable registers. These registers allow the implementation of various single-data-rate applications for all versions of nano devices and double-datarate applications for the AGLN060, AGLN125, and AGLN250 devices. IGLOO nano devices support LVTTL and LVCMOS I/O standards, are hot-swappable, and support coldsparing and Schmitt trigger. Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card in a powered-up system. Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed when the system is powered up, while the component itself is powered down, or when power supplies are floating. Wide Range I/O Support IGLOO nano devices support JEDEC-defined wide range I/O operation. IGLOO nano devices support both the JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to 3.6 V, and JESD8-12 with its 1.2 V nominal, supporting an effective operating range of 1.14 V to 1.575 V. Wider I/O range means designers can eliminate power supplies or power conditioning components from the board or move to less costly components with greater tolerances. Wide range eases I/O bank management and provides enhanced protection from system voltage spikes, while providing the flexibility to easily run custom voltage applications. 1- 8 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Specifying I/O States During Programming You can modify the I/O states during programming in FlashPro. In FlashPro, this feature is supported for PDB files generated from Designer v8.5 or greater. See the FlashPro User’s Guide for more information. Note: PDB files generated from Designer v8.1 to Designer v8.4 (including all service packs) have limited display of Pin Numbers only. 1. Load a PDB from the FlashPro GUI. You must have a PDB loaded to modify the I/O states during programming. 2. From the FlashPro GUI, click PDB Configuration. A FlashPoint – Programming File Generator window appears. 3. Click the Specify I/O States During Programming button to display the Specify I/O States During Programming dialog box. 4. Sort the pins as desired by clicking any of the column headers to sort the entries by that header. Select the I/Os you wish to modify (Figure 1-7 on page 1-9). 5. Set the I/O Output State. You can set Basic I/O settings if you want to use the default I/O settings for your pins, or use Custom I/O settings to customize the settings for each pin. Basic I/O state settings: 1 – I/O is set to drive out logic High 0 – I/O is set to drive out logic Low Last Known State – I/O is set to the last value that was driven out prior to entering the programming mode, and then held at that value during programming Z -Tri-State: I/O is tristated Figure 1-7 • I/O States During Programming Window R ev i si o n 2 0 1-9 IGLOO nano Device Overview 6. Click OK to return to the FlashPoint – Programming File Generator window. Note: I/O States During programming are saved to the ADB and resulting programming files after completing programming file generation. 1- 10 R ev i sio n 2 0 2 – IGLOO nano DC and Switching Characteristics General Specifications The Z feature grade does not support the enhanced nano features of Schmitt trigger input, Flash*Freeze bus hold (hold previous I/O state in Flash*Freeze mode), cold-sparing, and hot-swap I/O capability. Refer to "IGLOO nano Ordering Information" on page IV for more information. Operating Conditions Stresses beyond those listed in Table 2-1 may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions specified in Table 2-2 on page 2-2 is not implied. Table 2-1 • Absolute Maximum Ratings Symbol Parameter Limits Units VCC DC core supply voltage –0.3 to 1.65 V VJTAG JTAG DC voltage –0.3 to 3.75 V VPUMP Programming voltage –0.3 to 3.75 V VCCPLL Analog power supply (PLL) –0.3 to 1.65 V VCCI DC I/O buffer supply voltage –0.3 to 3.75 V –0.3 V to 3.6 V V 1 VI I/O input voltage TSTG 2 Storage temperature –65 to +150 °C TJ 2 Junction temperature +125 °C Notes: 1. The device should be operated within the limits specified by the datasheet. During transitions, the input signal may undershoot or overshoot according to the limits shown in Table 2-4 on page 2-3. 2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for recommended operating limits, refer to Table 2-2 on page 2-2. R ev i si o n 2 0 2-1 IGLOO nano DC and Switching Characteristics Recommended Operating Conditions 1 Table 2-2 • Symbol 2 TJ Junction temperature VCC 1.5 V DC core supply voltage3 –20 to + 85 VJTAG 1.425 to 1.575 1.425 to 1.575 V 1.14 to 1.575 1.14 to 1.575 V 1.4 to 3.6 1.4 to 3.6 V 3.15 to 3.45 3.15 to 3.45 V 0 to 3.6 0 to 3.6 V 1.425 to 1.575 1.425 to 1.575 V 1.14 to 1.575 1.14 to 1.575 V 1.14 to 1.26 1.14 to 1.26 V 1.14 to 1.575 1.14 to 1.575 V 1.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V 1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V 2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V 3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V 3.3 V DC wide range supply voltage 10 2.7 to 3.6 2.7 to 3.6 V voltage4,5 Programming voltage Programming mode Operation VCCPLL 7 Units 2 °C JTAG DC voltage 6 Industrial –40 to +100 1.2 V–1.5 V wide range core VPUMP Extended Commercial Parameter 3 Analog power supply 1.5 V DC core supply voltage (PLL) 1.2 V–1.5 V wide range core supply voltage4 VCCI and 1.2 V DC supply voltage 4 VMV 8,9 1.2 V DC wide range supply voltage 4 Notes: 1. All parameters representing voltages are measured with respect to GND unless otherwise specified. 2. Default Junction Temperature Range in the Libero SoC software is set to 0°C to +70°C for commercial, and -40°C to +85°C for industrial. To ensure targeted reliability standards are met across the full range of junction temperatures, Microsemi recommends using custom settings for temperature range before running timing and power analysis tools. For more information regarding custom settings, refer to the New Project Dialog Box in the Libero Online Help. 3. For IGLOO® nano V5 devices 4. For IGLOO nano V2 devices only, operating at VCCI ≥ VCC 5. IGLOO nano V5 devices can be programmed with the VCC core voltage at 1.5 V only. IGLOO nano V2 devices can be programmed with the VCC core voltage at 1.2 V (with FlashPro4 only) or 1.5 V. If you are using FlashPro3 and want to do in-system programming using 1.2 V, please contact the factory. 6. VPUMP can be left floating during operation (not programming mode). 7. VCCPLL pins should be tied to VCC pins. See the "Pin Descriptions" chapter for further information. 8. VMV pins must be connected to the corresponding VCCI pins. See the Pin Descriptions chapter of the IGLOO nano FPGA Fabric User’s Guide for further information. 9. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each I/O standard are given in Table 2-21 on page 2-19. VCCI should be at the same voltage within a given I/O bank. 10. 3.3 V wide range is compliant to the JESD8-B specification and supports 3.0 V VCCI operation. Table 2-3 • Product Grade Flash Programming Limits – Retention, Storage, and Operating Temperature1 Programming Cycles Maximum Operating Junction Program Retention Maximum Storage Temperature TJ (°C) 2 (biased/unbiased) Temperature TSTG (°C) 2 Commercial 500 20 years 110 100 Industrial 500 20 years 110 100 Notes: 1. This is a stress rating only; functional operation at any condition other than those indicated is not implied. 2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device operating conditions and absolute limits. 2- 2 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-4 • Overshoot and Undershoot Limits 1 VCCI Average VCCI–GND Overshoot or Undershoot Duration as a Percentage of Clock Cycle2 Maximum Overshoot/ Undershoot2 10% 1.4 V 5% 1.49 V 10% 1.1 V 5% 1.19 V 10% 0.79 V 5% 0.88 V 10% 0.45 V 5% 0.54 V 2.7 V or less 3V 3.3 V 3.6 V Notes: 1. Based on reliability requirements at 85°C. 2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V. I/O Power-Up and Supply Voltage Thresholds for Power-On Reset (Commercial and Industrial) Sophisticated power-up management circuitry is designed into every IGLOO nano device. These circuits ensure easy transition from the powered-off state to the powered-up state of the device. The many different supplies can power up in any sequence with minimized current spikes or surges. In addition, the I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1 on page 2-4. There are five regions to consider during power-up. IGLOO nano I/Os are activated only if ALL of the following three conditions are met: 1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 and Figure 2-2 on page 2-5). 2. VCCI > VCC – 0.75 V (typical) 3. Chip is in the operating mode. VCCI Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.2 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.1 V Ramping up (V2 devices): 0.75 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.65 V < trip_point_down < 0.95 V VCC Trip Point: Ramping up (V5 devices): 0.6 V < trip_point_up < 1.1 V Ramping down (V5 devices): 0.5 V < trip_point_down < 1.0 V Ramping up (V2 devices): 0.65 V < trip_point_up < 1.05 V Ramping down (V2 devices): 0.55 V < trip_point_down < 0.95 V VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following: • During programming, I/Os become tristated and weakly pulled up to VCCI. • JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O behavior. R ev i si o n 2 0 2-3 IGLOO nano DC and Switching Characteristics PLL Behavior at Brownout Condition Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper powerup behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details). When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ± 0.25 V for V5 devices, and 0.75 V ± 0.2 V for V2 devices), the PLL output lock signal goes LOW and/or the output clock is lost. Refer to the "Brownout Voltage" section in the "Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the IGLOO nano FPGA Fabric User’s Guide for information on clock and lock recovery. Internal Power-Up Activation Sequence 1. Core 2. Input buffers 3. Output buffers, after 200 ns delay from input buffer activation To make sure the transition from input buffers to output buffers is clean, ensure that there is no path longer than 100 ns from input buffer to output buffer in your design. VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 4: I/O buffers are ON. Region 1: I/O Buffers are OFF I/Os are functional but slower because VCCI is below specification. For the same reason, input buffers do not Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. meet VIH / VIL levels, and output buffers do not meet VOH/VOL levels. VCC = 1.425 V Region 2: I/O buffers are ON. I/Os are functional but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH/VIL levels, and output buffers to not Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. meet VOH / VOL levels. Activation trip point: Va = 0.85 V ± 0.25 V Deactivation trip point: Vd = 0.75 V ± 0.25 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.3 V Deactivation trip point: Vd = 0.8 V ± 0.3 V Figure 2-1 • 2- 4 Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.425 V or 1.7 V or 2.3 V or 3.0 V V5 Devices – I/O State as a Function of VCCI and VCC Voltage Levels R ev isio n 2 0 VCCI IGLOO nano Low Power Flash FPGAs VCC = VCCI + VT where VT can be from 0.58 V to 0.9 V (typically 0.75 V) VCC VCC = 1.575 V Region 1: I/O Buffers are OFF Region 4: I/O buffers are ON. I/Os are functional but slower because VCCI is below specification. For the Region 5: I/O buffers are ON and power supplies are within specification. I/Os meet the entire datasheet and timer specifications for speed, VIH / VIL , VOH / VOL , etc. same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH / VOL levels. VCC = 1.14 V Region 2: I/O buffers are ON. I/Os are functional but slower because VCCI / VCC are below specification. For the same reason, input buffers do not meet VIH / VIL levels, and output buffers do not meet VOH/VOL levels. Activation trip point: Va = 0.85 V ± 0.2 V Deactivation trip point: Vd = 0.75 V ± 0.2 V Region 1: I/O buffers are OFF Activation trip point: Va = 0.9 V ± 0.15 V Deactivation trip point: Vd = 0.8 V ± 0.15 V Figure 2-2 • Region 3: I/O buffers are ON. I/Os are functional; I/O DC specifications are met, but I/Os are slower because the VCC is below specification. Min VCCI datasheet specification voltage at a selected I/O standard; i.e., 1.14 V,1.425 V, 1.7 V, 2.3 V, or 3.0 V VCCI V2 Devices – I/O State as a Function of VCCI and VCC Voltage Levels R ev i si o n 2 0 2-5 IGLOO nano DC and Switching Characteristics Thermal Characteristics Introduction The temperature variable in the Microsemi Designer software refers to the junction temperature, not the ambient temperature. This is an important distinction because dynamic and static power consumption cause the chip junction temperature to be higher than the ambient temperature. EQ 1 can be used to calculate junction temperature. TJ = Junction Temperature = ΔT + TA EQ 1 where: TA = Ambient temperature ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P θja = Junction-to-ambient of the package. θja numbers are located in Figure 2-5. P = Power dissipation Package Thermal Characteristics The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The maximum operating junction temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation allowed for a 484-pin FBGA package at commercial temperature and in still air. Max. junction temp. (°C) – Max. ambient temp. (°C) 100°C – 70°C Maximum Power Allowed = ------------------------------------------------------------------------------------------------------------------------------------------ = ------------------------------------- = 1.46 W 20.5°C/W θ ja (°C/W) EQ 2 Table 2-5 • Package Thermal Resistivities θja Package Type Chip Scale Package (CSP) Quad Flat No Lead (QFN) Very Thin Quad Flat Pack (VQFP) Pin Count θjc Still Air 200 ft./ min. 500 ft./ min. Units 36 TBD TBD TBD TBD C/W 81 TBD TBD TBD TBD C/W 48 TBD TBD TBD TBD C/W 68 TBD TBD TBD TBD C/W 100 TBD TBD TBD TBD C/W 100 10.0 35.3 29.4 27.1 C/W Temperature and Voltage Derating Factors Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C –20°C 0°C 25°C 70°C 85°C 100°C 1.425 0.947 0.956 0.965 0.978 1.000 1.009 1.013 1.5 0.875 0.883 0.892 0.904 0.925 0.932 0.937 1.575 0.821 0.829 0.837 0.848 0.868 0.875 0.879 2- 6 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) For IGLOO nano V2, 1.2 V DC Core Supply Voltage Junction Temperature (°C) Array Voltage VCC (V) –40°C –20°C 0°C 25°C 70°C 85°C 100°C 1.14 0.968 0.974 0.979 0.991 1.000 1.006 1.009 1.2 0.863 0.868 0.873 0.884 0.892 0.898 0.901 1.26 0.792 0.797 0.801 0.811 0.819 0.824 0.827 Calculating Power Dissipation Quiescent Supply Current Quiescent supply current (IDD) calculation depends on multiple factors, including operating voltages (VCC, VCCI, and VJTAG), operating temperature, system clock frequency, and power mode usage. Microsemi recommends using the Power Calculator and SmartPower software estimation tools to evaluate the projected static and active power based on the user design, power mode usage, operating voltage, and temperature. Table 2-8 • Power Supply State per Mode Power Supply Configurations Modes/Power Supplies VCC VCCPLL VCCI VJTAG VPUMP Flash*Freeze On On On On On/off/floating Sleep Off Off On Off Off Shutdown Off Off Off Off Off No Flash*Freeze On On On On On/off/floating Note: Off: Power Supply level = 0 V Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode* Typical (25°C) Core Voltage AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 Units 1.2 V 1.9 3.3 8 13 20 µA 1.5 V 5.8 6 10 18 34 µA Note: *IDD includes VCC, VPUMP, VCCI, VCCPLL, and VMV currents. Values do not include I/O static contribution, which is shown in Table 2-13 on page 2-9 through Table 2-14 on page 2-9 and Table 2-15 on page 2-10 through Table 2-18 on page 2-11 (PDC6 and PDC7). R ev i si o n 2 0 2-7 IGLOO nano DC and Switching Characteristics Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode* Core Voltage AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 Units VCCI= 1.2 V Typical (25°C) (per bank) 1.2 V 1.7 1.7 1.7 1.7 1.7 µA VCCI = 1.5 V (per bank) 1.2 V / Typical (25°C) 1.5 V 1.8 1.8 1.8 1.8 1.8 µA VCCI = 1.8 V (per bank) 1.2 V / Typical (25°C) 1.5 V 1.9 1.9 1.9 1.9 1.9 µA VCCI = 2.5 V (per bank) 1.2 V / Typical (25°C) 1.5 V 2.2 2.2 2.2 2.2 2.2 µA VCCI = 3.3 V (per bank) 1.2 V / Typical (25°C) 1.5 V 2.5 2.5 2.5 2.5 2.5 µA Note: *IDD = NBANKS * ICCI. Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode Typical (25°C) Core Voltage AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 Units 1.2 V / 1.5 V 0 0 0 0 0 µA Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1 Core Voltage AGLN010 AGLN020 AGLN060 AGLN125 AGLN250 Units 2 ICCA Current Typical (25°C) 1.2 V 3.7 5 10 13 18 µA 1.5 V 8 14 20 28 44 µA 1.2 V 1.7 1.7 1.7 1.7 1.7 µA VCCI / VJTAG = 1.5 V (per 1.2 V / 1.5 V bank) Typical (25°C) 1.8 1.8 1.8 1.8 1.8 µA VCCI / VJTAG = 1.8 V (per 1.2 V / 1.5 V bank) Typical (25°C) 1.9 1.9 1.9 1.9 1.9 µA VCCI / VJTAG = 2.5 V (per 1.2 V / 1.5 V bank) Typical (25°C) 2.2 2.2 2.2 2.2 2.2 µA VCCI / VJTAG = 3.3 V (per 1.2 V / 1.5 V bank) Typical (25°C) 2.5 2.5 2.5 2.5 2.5 µA ICCI or IJTAG Current VCCI / VJTAG = 1.2 V (per bank) Typical (25°C) Notes: 1. IDD = NBANKS * ICCI + ICCA. JTAG counts as one bank when powered. 2. Includes VCC, VCCPLL, and VPUMP currents. 2- 8 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Power per I/O Pin Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings Applicable to IGLOO nano I/O Banks VCCI (V) Dynamic Power PAC9 (µW/MHz) 1 3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.38 3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.89 3.3 16.38 3.3 V LVCMOS Wide Range – Schmitt Trigger 3.3 18.89 2.5 V LVCMOS 2.5 4.71 2.5 V LVCMOS – Schmitt Trigger 2.5 6.13 1.8 V LVCMOS 1.8 1.64 1.8 V LVCMOS – Schmitt Trigger 1.8 1.79 1.5 V LVCMOS (JESD8-11) 1.5 0.97 1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.96 1.2 0.57 1.2 0.52 1.2 0.57 1.2 0.52 Single-Ended 3.3 V LVCMOS Wide Range 2 3 1.2 V LVCMOS 1.2 V LVCMOS – Schmitt Trigger3 1.2 V LVCMOS Wide Range 3 1.2 V LVCMOS Wide Range – Schmitt Trigger3 Notes: 1. PAC9 is the total dynamic power measured on VCCI. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. 3. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC. Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 Applicable to IGLOO nano I/O Banks CLOAD (pF) VCCI (V) Dynamic Power PAC10 (µW/MHz)2 3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 107.98 3 5 3.3 107.98 2.5 V LVCMOS 5 2.5 61.24 1.8 V LVCMOS 5 1.8 31.28 5 1.5 21.50 5 1.2 15.22 Single-Ended 3.3 V LVCMOS Wide Range 1.5 V LVCMOS (JESD8-11) 4 1.2 V LVCMOS Notes: 1. 2. 3. 4. Dynamic power consumption is given for standard load and software default drive strength and output slew. PAC10 is the total dynamic power measured on VCCI. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. Applicable for IGLOO nano V2 devices operating at VCCI ≥ VCC. R ev i si o n 2 0 2-9 IGLOO nano DC and Switching Characteristics Power Consumption of Various Internal Resources Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage Device Specific Dynamic Power (µW/MHz) Parameter Definition AGLN250 AGLN125 AGLN060 AGLN020 AGLN010 PAC1 Clock contribution of a Global Rib 4.421 4.493 2.700 0 0 PAC2 Clock contribution of a Global Spine 2.704 1.976 1.982 4.002 2.633 PAC3 Clock contribution of a VersaTile row 1.496 1.504 1.511 1.346 1.340 PAC4 Clock contribution of a VersaTile used as a sequential module 0.152 0.153 0.153 0.148 0.143 PAC5 First contribution of a VersaTile used as a sequential module 0.057 PAC6 Second contribution of a VersaTile used as a sequential module 0.207 PAC7 Contribution of a VersaTile used as a combinatorial module 0.17 PAC8 Average contribution of a routing net 0.7 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-13 on page 2-9. PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14. PAC11 Average contribution of a RAM block during a read operation 25.00 N/A PAC12 Average contribution of a RAM block during a write operation 30.00 N/A PAC13 Dynamic contribution for PLL 2.70 N/A Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices For IGLOO nano V2 or V5 Devices, 1.5 V Core Supply Voltage Device -Specific Static Power (mW) Parameter Definition AGLN250 AGLN125 AGLN060 AGLN020 AGLN010 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-12 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 1 Static PLL contribution 1.84 PDC5 Bank quiescent power (VCCI-dependent)2 See Table 2-12 on page 2-8 N/A Notes: 1. Minimum contribution of the PLL when running at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC. 2- 10 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage Device-Specific Dynamic Power (µW/MHz) Parameter Definition AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010 PAC1 Clock contribution of a Global Rib 2.829 2.875 1.728 0 0 0 PAC2 Clock contribution of a Global Spine 1.731 1.265 1.268 2.562 2.562 1.685 PAC3 Clock contribution of a VersaTile row 0.957 0.963 0.967 0.862 0.862 0.858 PAC4 Clock contribution of a VersaTile used as a sequential module 0.098 0.098 0.098 0.094 0.094 0.091 PAC5 First contribution of a VersaTile used as a sequential module 0.045 PAC6 Second contribution of a VersaTile used as a sequential module 0.186 PAC7 Contribution of a VersaTile used as a combinatorial module 0.11 PAC8 Average contribution of a routing net 0.45 PAC9 Contribution of an I/O input pin (standard-dependent) See Table 2-13 on page 2-9 PAC10 Contribution of an I/O output pin (standard-dependent) See Table 2-14 on page 2-9 PAC11 Average contribution of a RAM block during a read operation 25.00 N/A PAC12 Average contribution of a RAM block during a write operation 30.00 N/A PAC13 Dynamic contribution for PLL 2.10 N/A Table 2-18 • Different Components Contributing to the Static Power Consumption in IGLOO nano Devices For IGLOO nano V2 Devices, 1.2 V Core Supply Voltage Device-Specific Static Power (mW) Parameter Definition AGLN250 AGLN125 AGLN060 AGLN020 AGLN015 AGLN010 PDC1 Array static power in Active mode See Table 2-12 on page 2-8 PDC2 Array static power in Static (Idle) mode See Table 2-12 on page 2-8 PDC3 Array static power in Flash*Freeze mode See Table 2-9 on page 2-7 PDC4 1 Static PLL contribution PDC5 Bank quiescent power (VCCI-dependent)2 0.90 N/A See Table 2-12 on page 2-8 Notes: 1. Minimum contribution of the PLL when running at lowest frequency. 2. For a different output load, drive strength, or slew rate, Microsemi recommends using the Microsemi power spreadsheet calculator or the SmartPower tool in Libero SoC. R ev i si o n 2 0 2- 11 IGLOO nano DC and Switching Characteristics Power Calculation Methodology This section describes a simplified method to estimate power consumption of an application. For more accurate and detailed power estimations, use the SmartPower tool in Libero SoC software. The power calculation methodology described below uses the following variables: • The number of PLLs as well as the number and the frequency of each output clock generated • The number of combinatorial and sequential cells used in the design • The internal clock frequencies • The number and the standard of I/O pins used in the design • The number of RAM blocks used in the design • Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on page 2-14. • Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on page 2-14. • Read rate and write rate to the memory—guidelines are provided for typical applications in Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the design. Methodology Total Power Consumption—PTOTAL PTOTAL = PSTAT + PDYN PSTAT is the total static power consumption. PDYN is the total dynamic power consumption. Total Static Power Consumption—PSTAT PSTAT = (PDC1 or PDC2 or PDC3) + NBANKS * PDC5 NBANKS is the number of I/O banks powered in the design. Total Dynamic Power Consumption—PDYN PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL Global Clock Contribution—PCLOCK PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL* PAC4) * FCLK NSPINE is the number of global spines used in the user design—guidelines are provided in the "Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide. NROW is the number of VersaTile rows used in the design—guidelines are provided in the "Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide. FCLK is the global clock signal frequency. NS-CELL is the number of VersaTiles used as sequential modules in the design. PAC1, PAC2, PAC3, and PAC4 are device-dependent. Sequential Cells Contribution—PS-CELL PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. When a multi-tile sequential cell is used, it should be accounted for as 1. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. 2- 12 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Combinatorial Cells Contribution—PC-CELL PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. Routing Net Contribution—PNET PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK NS-CELL is the number of VersaTiles used as sequential modules in the design. NC-CELL is the number of VersaTiles used as combinatorial modules in the design. α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Input Buffer Contribution—PINPUTS PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK NINPUTS is the number of I/O input buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. FCLK is the global clock signal frequency. I/O Output Buffer Contribution—POUTPUTS POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK NOUTPUTS is the number of I/O output buffers used in the design. α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14. β1 is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14. FCLK is the global clock signal frequency. RAM Contribution—PMEMORY PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3 NBLOCKS is the number of RAM blocks used in the design. FREAD-CLOCK is the memory read clock frequency. β2 is the RAM enable rate for read operations. FWRITE-CLOCK is the memory write clock frequency. β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on page 2-14. PLL Contribution—PPLL PPLL = PDC4 + PAC13 *FCLKOUT FCLKOUT is the output clock frequency.1 1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding contribution (PAC13* FCLKOUT product) to the total PLL contribution. R ev i si o n 2 0 2- 13 IGLOO nano DC and Switching Characteristics Guidelines Toggle Rate Definition A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency. Below are some examples: • The average toggle rate of a shift register is 100% because all flip-flop outputs toggle at half of the clock frequency. • The average toggle rate of an 8-bit counter is 25%: – Bit 0 (LSB) = 100% – Bit 1 = 50% – Bit 2 = 25% – … – Bit 7 (MSB) = 0.78125% – Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8 Enable Rate Definition Output enable rate is the average percentage of time during which tristate outputs are enabled. When nontristate output buffers are used, the enable rate should be 100%. Table 2-19 • Toggle Rate Guidelines Recommended for Power Calculation Component α1 α2 Definition Guideline Toggle rate of VersaTile outputs 10% I/O buffer toggle rate 10% Table 2-20 • Enable Rate Guidelines Recommended for Power Calculation Component β1 β2 β3 2- 14 Definition Guideline I/O output buffer enable rate 100% RAM enable rate for read operations 12.5% RAM enable rate for write operations 12.5% R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs User I/O Characteristics Timing Model I/O Module (Non-Registered) Combinational Cell Combinational Cell Y LVCMOS 2.5 V Output Drive Strength = 8 mA High Slew Rate Y tPD = 1.18 ns tPD = 0.90 ns tDP = 1.99 ns I/O Module (Non-Registered) Combinational Cell Y LVTTL Output drive strength = 4 mA High slew rate tDP = 2.35 ns tPD = 1.60 ns I/O Module (Non-Registered) Combinational Cell I/O Module (Registered) Y LVTTL Output drive strength = 8 mA High slew rate tPY = 1.06 ns tDP = 1.96 ns Input LVCMOS 2.5 V D tPD = 1.17 ns Q I/O Module (Non-Registered) Combinational Cell Y tICLKQ = 0.42 ns tISUD = 0.47 ns LVCMOS 1.5 V Output drive strength = 2 mA High slew rate tDP = 2.65 ns tPD = 0.87 ns Input LVTTL Clock Register Cell tPY = 0.85 ns D Combinational Cell Y Q I/O Module (Non-Registered) tPY = 1.15 ns Figure 2-3 • D Q D tPD = 0.91 ns tCLKQ = 0.89 ns tSUD = 0.81 ns LVCMOS 1.5 V I/O Module (Registered) Register Cell Q tDP = 1.96 ns tCLKQ = 0.89 ns tSUD = 0.81 ns Input LVTTL Clock Input LVTTL Clock tPY = 0.85 ns tPY = 0.85 ns LVTTL 3.3 V Output drive strength = 8 mA High slew rate tOCLKQ = 1.00 ns tOSUD = 0.51 ns Timing Model Operating Conditions: STD Speed, Commercial Temperature Range (TJ = 70°C), Worst-Case VCC = 1.425 V, for DC 1.5 V Core Voltage, Applicable to V2 and V5 Devices R ev i si o n 2 0 2- 15 IGLOO nano DC and Switching Characteristics tPY tDIN D PAD Q DIN Y CLK tPY = MAX(tPY(R), tPY(F)) tDIN = MAX(tDIN(R), tDIN(F)) To Array I/O Interface VIH PAD Vtrip Vtrip VIL VCC 50% 50% Y GND tPY (F) tPY (R) VCC 50% DIN GND 50% tDIN tDIN (R) Figure 2-4 • 2- 16 (F) Input Buffer Timing Model and Delays (example) R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs tDOUT tDP D Q PAD DOUT D Std Load CLK From Array tDP = MAX(tDP(R), tDP(F)) tDOUT = MAX(tDOUT(R), tDOUT(F)) I/O Interface tDOUT (R) D 50% tDOUT VCC (F) 50% 0V VCC DOUT 50% 50% 0V VOH Vtrip Vtrip VOL PAD tDP (R) Figure 2-5 • tDP (F) Output Buffer Model and Delays (example) R ev i si o n 2 0 2- 17 IGLOO nano DC and Switching Characteristics tEOUT D Q CLK E tZL, tZH, tHZ, tLZ, tZLS, tZHS EOUT D Q PAD DOUT CLK D tEOUT = MAX(tEOUT(r), tEOUT(f)) I/O Interface VCC D VCC 50% tEOUT (F) 50% E tEOUT (R) VCC 50% 50% 50% EOUT tZL tZH tHZ VCCI 90% VCCI PAD Vtrip Vtrip VOL 10% VCCI VCC D VCC E 50% tEOUT (R) 50% tEOUT (F) VCC EOUT 50% 50% 50% tZLS VOH tZHS PAD Vtrip Figure 2-6 • 2- 18 50% tLZ Vtrip VOL Tristate Output Buffer Timing Model and Delays (example) R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Overview of I/O Performance Summary of I/O DC Input and Output Levels – Default I/O Software Settings Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Applicable to Commercial and Industrial Conditions—Software Default Settings Equivalent Software Default Slew Min. Drive Drive Strength Strength2 Rate V I/O Standard 3.3 V LVTTL / 3.3 V LVCMOS VIH VOL VOH IOL1 IOH1 mA mA Max. V Min. V Max. V Max. V Min. V 2.4 8 mA High –0.3 0.8 2 3.6 0.4 3.3 V LVCMOS 100 µA Wide Range3 8 mA High –0.3 0.8 2 3.6 0.2 2.5 V LVCMOS 8 mA 8 mA High –0.3 0.7 1.7 3.6 0.7 1.8 V LVCMOS 4 mA 4 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 1.5 V LVCMOS 2 mA 2 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 1 mA 1 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 1 1 100 µA 1 mA High –0.3 0.3 * VCCI 0.7 * VCCI 3.6 1.2 V 8 mA VIL LVCMOS4 1.2 V LVCMOS Wide Range4,5 8 8 VCCI – 0.2 100 100 µA µA 1.7 8 8 VCCI – 0.45 4 4 0.1 VCCI – 0.1 100 100 µA µA Notes: 1. Currents are measured at 85°C junction temperature. 2. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 4. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC . 5. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range, as specified in the JESD8-12 specification. Table 2-22 • Summary of Maximum and Minimum DC Input Levels Applicable to Commercial and Industrial Conditions Commercial1 IIL 3 Industrial2 IIH 4 IIL 3 IIH 4 DC I/O Standards µA µA µA µA 3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15 3.3 V LVCOMS Wide Range 10 10 15 15 2.5 V LVCMOS 10 10 15 15 1.8 V LVCMOS 10 10 15 15 10 10 15 15 1.5 V LVCMOS 5 1.2 V LVCMOS 10 10 15 15 1.2 V LVCMOS Wide Range5 10 10 15 15 Notes: 1. Commercial range (–20°C < TA < 70°C) 2. Industrial range (–40°C < TA < 85°C) 3. IIH is the input leakage current per I/O pin over recommended operating conditions, where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. IIL is the input leakage current per I/O pin over recommended operating conditions, where –0.3 V < VIN < VIL. 5. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC. R ev i si o n 2 0 2- 19 IGLOO nano DC and Switching Characteristics Summary of I/O Timing Characteristics – Default I/O Software Settings Table 2-23 • Summary of AC Measuring Points Standard Measuring Trip Point (Vtrip) 3.3 V LVTTL / 3.3 V LVCMOS 1.4 V 3.3 V LVCMOS Wide Range 1.4 V 2.5 V LVCMOS 1.2 V 1.8 V LVCMOS 0.90 V 1.5 V LVCMOS 0.75 V 1.2 V LVCMOS 0.60 V 1.2 V LVCMOS Wide Range 0.60 V Table 2-24 • I/O AC Parameter Definitions Parameter Parameter Definition tDP Data to Pad delay through the Output Buffer tPY Pad to Data delay through the Input Buffer tDOUT Data to Output Buffer delay through the I/O interface tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface tDIN Input Buffer to Data delay through the I/O interface tHZ Enable to Pad delay through the Output Buffer—HIGH to Z tZH Enable to Pad delay through the Output Buffer—Z to HIGH tLZ Enable to Pad delay through the Output Buffer—LOW to Z tZL Enable to Pad delay through the Output Buffer—Z to LOW tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW 2- 20 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Applies to IGLOO nano at 1.5 V Core Operating Conditions ns 3.3 V LVCMOS 100 µA 8 mA Wide Range2 High 5 pF 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns 2.5 V LVCMOS 8 mA 8 mA High 5 pF 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns 1.8 V LVCMOS 4 mA 4 mA High 5 pF 0.97 2.08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns 1.5 V LVCMOS 2 mA 2 mA High 5 pF 0.97 2.39 0.19 1.19 1.52 0.66 2.44 2.24 2.02 2.15 ns Units 1.45 1.98 2.38 tHZ tZL 1.83 tLZ tEO UT 0.66 tZH tPYS 1.16 tPY 1.79 0.19 0.86 tDIN 5 pF 0.97 tDP High tDOUT Slew Rate 8 mA 3.3 V LVTTL / 3.3 V LVCMOS Capacitive Load (pF) Equivalent Software Default t Drive Strength Option1 8 mA I/O Standard Drive Strength (mA) Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 21 IGLOO nano DC and Switching Characteristics Applies to IGLOO nano at 1.2 V Core Operating Conditions 2.34 1.90 2.43 3.14 ns 3.3 V LVCMOS 100 µA 8 mA Wide Range2 High 5 pF 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns 2.5 V LVCMOS 8 mA 8 mA High 5 pF 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns 1.8 V LVCMOS 4 mA 4 mA High 5 pF 1.55 2.49 0.26 1.13 1.59 1.10 2.53 2.34 2.42 2.81 ns 1.5 V LVCMOS 2 mA 2 mA High 5 pF 1.55 2.78 0.26 1.27 1.77 1.10 2.82 2.62 2.44 2.74 ns 1.2 V LVCMOS 1 mA 1 mA High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns 1.2 V LVCMOS 100 µA 1 mA Wide Range3 High 5 pF 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns Units 1.10 tHZ tE O U T 1.36 tLZ tPYS 0.97 tZH tPY) 0.26 tZL tDIN 5 pF 1.55 2.31 tDP High tDOUT Slew Rate 8 mA 3.3 V LVTTL / 3.3 V LVCMOS Capacitive Load (pF) Equiv. Software Default Drive Strength Option1 8 mA I/O Standard Drive Strength (mA) Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings STD Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Notes: 1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification. 3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V side range as specified in the JESD8-12 specification. 4. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 22 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Detailed I/O DC Characteristics Table 2-27 • Input Capacitance Symbol Definition Conditions Min. Max. Units CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF Drive Strength RPULL-DOWN (Ω)2 RPULL-UP (Ω)3 2 mA 100 300 4 mA 100 300 6 mA 50 150 8 mA 50 150 Table 2-28 • I/O Output Buffer Maximum Resistances 1 Standard 3.3 V LVTTL / 3.3V LVCMOS 3.3 V LVCMOS Wide Range 100 µA 2.5 V LVCMOS 1.8 V LVCMOS 1.5 V LVCMOS 1.2 V LVCMOS 4 1.2 V LVCMOS Wide Range 4 Same as equivalent software default drive 2 mA 100 200 4 mA 100 200 6 mA 50 100 8 mA 50 100 2 mA 200 225 4 mA 100 112 2 mA 200 224 1 mA 315 315 100 µA 315 315 Notes: 1. These maximum values are provided for informational reasons only. Minimum output buffer resistance values depend on VCCI, drive strength selection, temperature, and process. For board design considerations and detailed output buffer resistances, use the corresponding IBIS models posted at http://www.microsemi.com/soc/download/ibis/default.aspx. 2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec 3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IO H s p e c 4. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC. R ev i si o n 2 0 2- 23 IGLOO nano DC and Switching Characteristics Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values R(WEAK PULL-UP)1 (Ω) R(WEAK PULL-DOWN)2 (Ω) VCCI Min. Max. Min. Max. 3.3 V 10 K 45 K 10 K 45 K 3.3 V (wide range I/Os) 10 K 45 K 10 K 45 K 2.5 V 11 K 55 K 12 K 74 K 1.8 V 18 K 70 K 17 K 110 K 1.5 V 19 K 90 K 19 K 140 K 1.2 V 25 K 110 K 25 K 150 K 1.2 V (wide range I/Os) 19 K 110 K 19 K 150 K Notes: 1. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / I(WEAK PULL-UP-MIN) 2. R(WEAK PULL-DOWN-MAX) = (VOLspec) / I(WEAK PULL-DOWN-MIN) Table 2-30 • I/O Short Currents IOSH/IOSL 3.3 V LVTTL / 3.3 V LVCMOS 3.3 V LVCMOS Wide Range 2.5 V LVCMOS Drive Strength IOSL (mA)* IOSH (mA)* 2 mA 25 27 4 mA 25 27 6 mA 51 54 8 mA 51 54 100 µA Same as equivalent software default drive 2 mA 16 18 4 mA 16 18 6 mA 32 37 8 mA 32 37 2 mA 9 11 4 mA 17 22 1.5 V LVCMOS 2 mA 13 16 1.2 V LVCMOS 1 mA 10 13 100 µA 10 13 1.8 V LVCMOS 1.2 V LVCMOS Wide Range Note: *TJ = 100°C 2- 24 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The reliability data below is based on a 3.3 V, 8 mA I/O setting, which is the worst case for this type of analysis. For example, at 100°C, the short current condition would have to be sustained for more than six months to cause a reliability concern. The I/O design does not contain any short circuit protection, but such protection would only be needed in extremely prolonged stress conditions. Table 2-31 • Duration of Short Circuit Event before Failure Temperature Time before Failure –40°C > 20 years –20°C > 20 years 0°C > 20 years 25°C > 20 years 70°C 5 years 85°C 2 years 100°C 6 months Table 2-32 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (Typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL / LVCMOS (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV 1.2 V LVCMOS (Schmitt trigger mode) 40 mV Table 2-33 • I/O Input Rise Time, Fall Time, and Related I/O Reliability Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (100°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis. 20 years (100°C) Input Buffer Note: *The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. R ev i si o n 2 0 2- 25 IGLOO nano DC and Switching Characteristics Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor–Transistor Logic (LVTTL) is a general purpose standard (EIA/JESD) for 3.3 V applications. It uses an LVTTL input buffer and push-pull output buffer. Table 2-34 • Minimum and Maximum DC Input and Output Levels 3.3 V LVTTL / 3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL 1 IIH 2 mA mA Max. mA3 Max. mA3 µA4 µA4 Drive Strength Min. V Max. V Min. V Max. V Max. V Min. V 2 mA –0.3 0.8 2 3.6 0.4 2.4 2 2 25 27 10 10 4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 25 27 10 10 6 mA –0.3 0.8 2 3.6 0.4 2.4 6 6 51 54 10 10 8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 51 54 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-7 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-35 • 3.3 V LVTTL/LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 3.3 1.4 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points. 2- 26 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns 4 mA STD 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns 6 mA STD 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns 8 mA STD 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns 4 mA STD 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns 6 mA STD 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns 8 mA STD 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 27 IGLOO nano DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-38 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 4.09 0.26 0.97 1.36 1.10 4.16 3.91 2.19 2.64 ns 4 mA STD 1.55 4.09 0.26 0.97 1.36 1.10 4.16 3.91 2.19 2.64 ns 6 mA STD 1.55 3.45 0.26 0.97 1.36 1.10 3.51 3.32 2.43 3.03 ns 8 mA STD 1.55 3.45 0.26 0.97 1.36 1.10 3.51 3.32 2.43 3.03 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-39 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 3.0 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 2.68 0.26 0.97 1.36 1.10 2.72 2.26 2.19 2.74 ns 4 mA STD 1.55 2.68 0.26 0.97 1.36 1.10 2.72 2.26 2.19 2.74 ns 6 mA STD 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns 8 mA STD 1.55 2.31 0.26 0.97 1.36 1.10 2.34 1.90 2.43 3.14 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 28 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 3.3 V LVCMOS Wide Range Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range 3.3 V LVCMOS Equivalent Wide Range1 VIL Software Default Drive Drive Max. Strength Min. Strength V V Option4 VIH VOL VOH IOL IOH IIL 2 IIH 3 Min. V Max. V Max. V Min. V µA µA µA5 µA5 100 µA 2 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10 100 µA 4 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10 100 µA 6 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10 100 µA 8 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10 Notes: 1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B specification. 2. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 3. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 5. Currents are measured at 85°C junction temperature. 6. Software default selection is highlighted in gray. R ev i si o n 2 0 2- 29 IGLOO nano DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-41 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 2 mA STD 0.97 5.23 0.19 1.20 1.66 0.66 5.24 5.00 2.47 2.56 ns 100 µA 4 mA STD 0.97 5.23 0.19 1.20 1.66 0.66 5.24 5.00 2.47 2.56 ns 100 µA 6 mA STD 0.97 4.27 0.19 1.20 1.66 0.66 4.28 4.12 2.83 3.16 ns 100 µA 8 mA STD 0.97 4.27 0.19 1.20 1.66 0.66 4.28 4.12 2.83 3.16 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-42 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 2 mA STD 0.97 3.11 0.19 1.20 1.66 0.66 3.13 2.55 2.47 2.70 ns 100 µA 4 mA STD 0.97 3.11 0.19 1.20 1.66 0.66 3.13 2.55 2.47 2.70 ns 100 µA 6 mA STD 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns 100 µA 8 mA STD 0.97 2.56 0.19 1.20 1.66 0.66 2.57 2.02 2.82 3.31 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. 2- 30 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Applies to 1.2 V DC Core Voltage Table 2-43 • 3.3 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 2 mA STD 1.55 6.01 0.26 1.31 1.91 1.10 6.01 5.66 3.02 3.49 ns 100 µA 4 mA STD 1.55 6.01 0.26 1.31 1.91 1.10 6.01 5.66 3.02 3.49 ns 100 µA 6 mA STD 1.55 5.02 0.26 1.31 1.91 1.10 5.02 4.76 3.38 4.10 ns 100 µA 8 mA STD 1.55 5.02 0.26 1.31 1.91 1.10 5.02 4.76 3.38 4.10 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-44 • 3.3 V LVCMOS Wide Range High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.7 V Equivalent Software Default Drive Drive Strength Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 100 µA 2 mA STD 1.55 3.82 0.26 1.31 1.91 1.10 3.82 3.15 3.01 3.65 ns 100 µA 4 mA STD 1.55 3.82 0.26 1.31 1.91 1.10 3.82 3.15 3.01 3.65 ns 100 µA 6 mA STD 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns 100 µA 8 mA STD 1.55 3.25 0.26 1.31 1.91 1.10 3.25 2.61 3.38 4.27 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. R ev i si o n 2 0 2- 31 IGLOO nano DC and Switching Characteristics 2.5 V LVCMOS Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 2.5 V applications. Table 2-45 • Minimum and Maximum DC Input and Output Levels 2.5 V LVCMOS Drive Strength VIL VIH VOL VOH IOL IOH Min., V Max., V Min., V Max., V Max., V Min., V mA mA IOSL Max., mA3 IIL 1 IIH 2 IOSH Max., mA3 µA4 µA4 2 mA –0.3 0.7 1.7 3.6 0.7 1.7 2 2 16 18 10 10 4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 16 18 10 10 6 mA –0.3 0.7 1.7 3.6 0.7 1.7 6 6 32 37 10 10 8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 32 37 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-8 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-46 • 2.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 2.5 1.2 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points. 2- 32 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns 4 mA STD 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns 8 mA STD 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns 8 mA STD 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-48 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns 4 mA STD 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns 6 mA STD 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns 8 mA STD 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 33 IGLOO nano DC and Switching Characteristics Applies to 1.2 V DC Core Voltage Table 2-49 • 2.5 LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 4.61 0.26 1.21 1.39 1.10 4.55 4.61 2.15 2.43 ns 4 mA STD 1.55 4.61 0.26 1.21 1.39 1.10 4.55 4.61 2.15 2.43 ns 6 mA STD 1.55 3.86 0.26 1.21 1.39 1.10 3.82 3.86 2.41 2.89 ns 8 mA STD 1.55 3.86 0.26 1.21 1.39 1.10 3.82 3.86 2.41 2.89 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-50 • 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 2.68 0.26 1.21 1.39 1.10 2.72 2.54 2.15 2.51 ns 4 mA STD 1.55 2.68 0.26 1.21 1.39 1.10 2.72 2.54 2.15 2.51 ns 6 mA STD 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns 8 mA STD 1.55 2.30 0.26 1.21 1.39 1.10 2.33 2.04 2.41 2.99 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 34 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.8 V LVCMOS Low-voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer. Table 2-51 • Minimum and Maximum DC Input and Output Levels 1.8 V LVCMOS VIL Max. V VOL VOH IOL IOH IOSL IOSH IIL 1 IIH 2 Max. V Max. V Min. V mA mA Max. mA3 Max. mA3 µA4 µA4 VIH Drive Strength Min. V Min. V 2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 9 11 10 10 4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 17 22 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath Figure 2-9 • 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ AC Loading Table 2-52 • 1.8 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.8 0.9 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points. R ev i si o n 2 0 2- 35 IGLOO nano DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-53 • 1.8 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 5.44 0.19 1.03 1.44 0.66 5.25 5.44 1.69 1.35 ns 4 mA STD 0.97 4.44 0.19 1.03 1.44 0.66 4.37 4.44 1.99 2.11 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-54 • 1.8 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 0.97 2.64 0.19 1.03 1.44 0.66 2.59 2.64 1.69 1.40 ns 4 mA STD 0.97 2.08 0.19 1.03 1.44 0.66 2.12 1.95 1.99 2.19 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Applies to 1.2 V DC Core Voltage Table 2-55 • 1.8 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 5.92 0.26 1.13 1.59 1.10 5.72 5.92 2.11 1.95 ns 4 mA STD 1.55 4.91 0.26 1.13 1.59 1.10 4.82 4.91 2.42 2.73 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-56 • 1.8 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.7 V Drive Strength Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units 2 mA STD 1.55 3.05 0.26 1.13 1.59 1.10 3.01 3.05 2.10 2.00 ns 4 mA STD 1.55 2.49 0.26 1.13 1.59 1.10 2.53 2.34 2.42 2.81 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 36 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.5 V LVCMOS (JESD8-11) Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer. Table 2-57 • Minimum and Maximum DC Input and Output Levels 1.5 V LVCMOS VIL Drive Min. Strength V 2 mA Max. V VIH Min. V Max. V –0.3 0.35 * VCCI 0.65 * VCCI 3.6 VOL VOH IOL IOH IOSL IOSH IIL 1 IIH 2 Max. V Min. V mA mA Max. mA3 Max. mA3 µA4 µA4 13 16 0.25 * VCCI 0.75 * VCCI 2 2 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. R=1k Test Point Enable Path Test Point Datapath 5 pF R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-10 • AC Loading Table 2-58 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) 0 Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.5 0.75 5 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points. R ev i si o n 2 0 2- 37 IGLOO nano DC and Switching Characteristics Timing Characteristics Applies to 1.5 V DC Core Voltage Table 2-59 • 1.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.97 5.39 0.19 1.19 1.62 0.66 5.48 5.39 2.02 2.06 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-60 • 1.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 0.97 2.39 0.19 1.19 1.62 0.66 2.44 2.24 2.02 2.15 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Applies to 1.2 V DC Core Voltage Table 2-61 • 1.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 5.87 0.26 1.27 1.77 1.10 5.92 5.87 2.45 2.65 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-62 • 1.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.4 V Drive Strength 2 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 2.78 0.26 1.27 1.77 1.10 2.82 2.62 2.44 2.74 ns Notes: 1. Software default selection highlighted in gray. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 38 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.2 V LVCMOS (JESD8-12A) Low-Voltage CMOS for 1.2 V complies with the LVCMOS standard JESD8-12A for general purpose 1.2 V applications. It uses a 1.2 V input buffer and a push-pull output buffer. Table 2-63 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS VIL Drive Min. Strength V 1 mA VIH Max. V Min. V –0.3 0.35 * VCCI 0.65 * VCCI VOL VOH IOL IOH IOSL Max. V Max. V Min. V mA mA 3.6 0.25 * VCCI 0.75 * VCCI 1 1 IOSH IIL 1 IIH 2 Max. mA3 Max. mA3 10 13 µA4 µA4 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Software default selection highlighted in gray. Datapath R to VCCI for tLZ / tZL / tZLS R to GND for tHZ / tZH / tZHS R=1k Test Point Enable Path Test Point 5 pF 5 pF for tZH / tZHS / tZL / tZLS 5 pF for tHZ / tLZ Figure 2-11 • AC Loading Table 2-64 • 1.2 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads Input LOW (V) Input HIGH (V) Measuring Point* (V) CLOAD (pF) 1.2 0.6 5 0 Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-65 • 1.2 V LVCMOS Low Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 1 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 8.30 0.26 1.56 2.27 1.10 7.97 7.54 2.56 2.55 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-66 • 1.2 V LVCMOS High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Drive Strength 1 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 39 IGLOO nano DC and Switching Characteristics 1.2 V LVCMOS Wide Range Table 2-67 • Minimum and Maximum DC Input and Output Levels 1.2 V LVCMOS Wide Range VIL Drive Min. Strength V 1 mA VOL VOH IOL IOH IOSL IOSH IIL 1 IIH 2 Max. V Max. V Min. V mA mA Max. mA3 Max. mA3 µA4 µA4 3.6 0.1 10 13 VIH Max. V Min. V –0.3 0.3 * VCCI 0.7 * VCCI VCCI – 0.1 100 100 10 10 Notes: 1. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL. 2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input current is larger when operating outside recommended ranges. 3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage. 4. Currents are measured at 85°C junction temperature. 5. Applicable to IGLOO nano V2 devices operating at VCCI ≥ VCC. 6. Software default selection highlighted in gray. Timing Characteristics Applies to 1.2 V DC Core Voltage Table 2-68 • 1.2 V LVCMOS Wide Range Low Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 µA 1 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 8.30 0.26 1.56 2.27 1.10 7.97 7.54 2.56 2.55 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-69 • 1.2 V LVCMOS Wide Range HIgh Slew – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 1.14 V Equivalent Software Default Drive Drive Strength Strength Option1 100 µA 1 mA Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ Units STD 1.55 3.50 0.26 1.56 2.27 1.10 3.37 3.10 2.55 2.66 ns Notes: 1. The minimum drive strength for any LVCMOS 1.2 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 3. Software default selection highlighted in gray. 2- 40 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs I/O Register Specifications Fully Registered I/O Buffers with Asynchronous Preset INBUF Preset L DOUT Data_out D C Q DFN1P1 E PRE F Y Core Array D Q DFN1P1 TRIBUF PRE INBUF Data Pad Out D EOUT CLKBUF CLK H I A PRE J D Q DFN1P1 Data Input I/O Register with: Active High Preset Positive-Edge Triggered INBUF D_Enable CLK CLKBUF Data Output Register and Enable Output Register with: Active High Preset Postive-Edge Triggered Figure 2-12 • Timing Model of Registered I/O Buffers with Asynchronous Preset R ev i si o n 2 0 2- 41 IGLOO nano DC and Switching Characteristics Table 2-70 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register F, H tOHD Data Hold Time for the Output Data Register F, H tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register J, H tOEHD Data Hold Time for the Output Enable Register J, H tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H tICLKQ Clock-to-Q of the Input Data Register A, E tISUD Data Setup Time for the Input Data Register C, A tIHD Data Hold Time for the Input Data Register C, A tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A Note: *See Figure 2-12 on page 2-41 for more information. 2- 42 R ev i sio n 2 0 H, DOUT L, DOUT H, EOUT I, EOUT IGLOO nano Low Power Flash FPGAs Fully Registered I/O Buffers with Asynchronous Clear D CC Q DFN1C1 EE Core Array D Q DFN1C1 TRIBUF INBUF Data Data_out FF Pad Out DOUT Y EOUT CLR CLR LL INBUF CLR CLKBUF CLK HH AA JJ DD D Q DFN1C1 Data Input I/O Register with Active High Clear Positive-Edge Triggered INBUF CLKBUF D_Enable CLK CLR Data Output Register and Enable Output Register with Active High Clear Positive-Edge Triggered Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear R ev i si o n 2 0 2- 43 IGLOO nano DC and Switching Characteristics Table 2-71 • Parameter Definition and Measuring Nodes Parameter Name Parameter Definition Measuring Nodes (from, to)* tOCLKQ Clock-to-Q of the Output Data Register tOSUD Data Setup Time for the Output Data Register FF, HH tOHD Data Hold Time for the Output Data Register FF, HH tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH tOECLKQ Clock-to-Q of the Output Enable Register tOESUD Data Setup Time for the Output Enable Register JJ, HH tOEHD Data Hold Time for the Output Enable Register JJ, HH tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH tICLKQ Clock-to-Q of the Input Data Register AA, EE tISUD Data Setup Time for the Input Data Register CC, AA tIHD Data Hold Time for the Input Data Register CC, AA tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA Note: *See Figure 2-13 on page 2-43 for more information. 2- 44 R ev i sio n 2 0 HH, DOUT LL, DOUT HH, EOUT II, EOUT IGLOO nano Low Power Flash FPGAs Input Register tICKMPWH tICKMPWL CLK 50% 50% 1 50% 50% 50% 0 tIWPRE Preset 50% 50% tIHD tISUD Data 50% 50% tIRECPRE tIREMPRE 50% 50% 50% tIWCLR 50% Clear tIRECCLR tIREMCLR 50% 50% tIPRE2Q 50% Out_1 50% tICLR2Q 50% tICLKQ Figure 2-14 • Input Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-72 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units 0.42 ns tICLKQ Clock-to-Q of the Input Data Register tISUD Data Setup Time for the Input Data Register 0.47 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.79 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.79 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 45 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-73 • Input Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tICLKQ Clock-to-Q of the Input Data Register 0.68 ns tISUD Data Setup Time for the Input Data Register 0.97 ns tIHD Data Hold Time for the Input Data Register 0.00 ns tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 1.19 ns tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 1.19 ns tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 ns tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 ns tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 46 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Output Register tOCKMPWH tOCKMPWL CLK 50% 50% 50% 50% 50% 50% 50% tOSUD tOHD Data_out 1 50% 50% 0 tOWPRE Preset tOREMPRE tORECPRE 50% 50% 50% tOWCLR 50% Clear tORECCLR tOREMCLR 50% 50% tOPRE2Q 50% DOUT 50% tOCLR2Q 50% tOCLKQ Figure 2-15 • Output Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-74 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.00 ns tOSUD Data Setup Time for the Output Data Register 0.51 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.34 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.34 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 47 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-75 • Output Data Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOCLKQ Clock-to-Q of the Output Data Register 1.52 ns tOSUD Data Setup Time for the Output Data Register 1.15 ns tOHD Data Hold Time for the Output Data Register 0.00 ns tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 1.96 ns tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 1.96 ns tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 ns tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 ns tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 48 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Output Enable Register tOECKMPWH tOECKMPWL 50% 50% 50% 50% 50% 50% 50% CLK tOESUD tOEHD D_Enable 1 50% 0 50% tOEWPRE tOEREMPRE tOERECPRE 50% 50% 50% Preset tOEWCLR 50% tOERECCLR tOEREMCLR 50% 50% Clear tOEPRE2Q 50% EOUT 50% tOECLR2Q 50% tOECLKQ Figure 2-16 • Output Enable Register Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-76 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 0.75 ns tOESUD Data Setup Time for the Output Enable Register 0.51 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.13 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.13 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 49 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-77 • Output Enable Register Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tOECLKQ Clock-to-Q of the Output Enable Register 1.10 ns tOESUD Data Setup Time for the Output Enable Register 1.15 ns tOEHD Data Hold Time for the Output Enable Register 0.00 ns tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 1.65 ns tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 1.65 ns tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 50 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs DDR Module Specifications Note: DDR is not supported for AGLN010 and AGLN020 devices. Input DDR Module Input DDR INBUF A Data D Out_QF (to core) E Out_QR (to core) FF1 B CLK CLKBUF FF2 C CLR INBUF DDR_IN Figure 2-17 • Input DDR Timing Model Table 2-78 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDRICLKQ1 Clock-to-Out Out_QR B, D tDDRICLKQ2 Clock-to-Out Out_QF B, E tDDRISUD Data Setup Time of DDR input A, B tDDRIHD Data Hold Time of DDR input A, B tDDRICLR2Q1 Clear-to-Out Out_QR C, D tDDRICLR2Q2 Clear-to-Out Out_QF C, E tDDRIREMCLR Clear Removal C, B tDDRIRECCLR Clear Recovery C, B R ev i si o n 2 0 2- 51 IGLOO nano DC and Switching Characteristics CLK tDDRISUD Data 1 2 3 4 5 6 tDDRIHD 7 8 9 tDDRIRECCLR CLR tDDRIREMCLR tDDRICLKQ1 tDDRICLR2Q1 Out_QF 2 6 4 tDDRICLKQ2 tDDRICLR2Q2 Out_QR 3 5 7 Figure 2-18 • Input DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-79 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.25 V Parameter Description Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.48 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.65 ns tDDRISUD1 Data Setup for Input DDR (negedge) 0.50 ns tDDRISUD2 Data Setup for Input DDR (posedge) 0.40 ns tDDRIHD1 Data Hold for Input DDR (negedge) 0.00 ns tDDRIHD2 Data Hold for Input DDR (posedge) 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 0.82 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.98 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.23 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 ns FDDRIMAX Maximum Frequency for Input DDR 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 52 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-80 • Input DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.76 ns tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.94 ns tDDRISUD1 Data Setup for Input DDR (negedge) 0.93 ns tDDRISUD2 Data Setup for Input DDR (posedge) 0.84 ns tDDRIHD1 Data Hold for Input DDR (negedge) 0.00 ns tDDRIHD2 Data Hold for Input DDR (posedge) 0.00 ns tDDRICLR2Q1 Asynchronous Clear-to-Out Out_QR for Input DDR 1.23 ns tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 1.42 ns tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 ns tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.24 ns tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.19 ns tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.31 ns tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.28 ns FDDRIMAX Maximum Frequency for Input DDR 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 2 0 2- 53 IGLOO nano DC and Switching Characteristics Output DDR Module Output DDR A Data_F (from core) X FF1 Out B CLK 0 X CLKBUF E X C X D Data_R (from core) 1 X OUTBUF FF2 B X CLR INBUF C X DDR_OUT Figure 2-19 • Output DDR Timing Model Table 2-81 • Parameter Definitions Parameter Name Parameter Definition Measuring Nodes (from, to) tDDROCLKQ Clock-to-Out B, E tDDROCLR2Q Asynchronous Clear-to-Out C, E tDDROREMCLR Clear Removal C, B tDDRORECCLR Clear Recovery C, B tDDROSUD1 Data Setup Data_F A, B tDDROSUD2 Data Setup Data_R D, B tDDROHD1 Data Hold Data_F A, B tDDROHD2 Data Hold Data_R D, B 2- 54 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs CLK tDDROSUD2 tDDROHD2 1 Data_F 2 5 tDDROHD1 tDDROREMCLR Data_R 6 4 3 7 8 9 10 11 tDDRORECCLR tDDROREMCLR CLR tDDROCLR2Q tDDROCLKQ Out 7 2 8 3 9 4 10 Figure 2-20 • Output DDR Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-82 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 1.07 ns tDDROSUD1 Data_F Data Setup for Output DDR 0.67 ns tDDROSUD2 Data_R Data Setup for Output DDR 0.67 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.38 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.23 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns FDDOMAX Maximum Frequency for the Output DDR 250.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 55 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-83 • Output DDR Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDDROCLKQ Clock-to-Out of DDR for Output DDR 1.60 ns tDDROSUD1 Data_F Data Setup for Output DDR 1.09 ns tDDROSUD2 Data_R Data Setup for Output DDR 1.16 ns tDDROHD1 Data_F Data Hold for Output DDR 0.00 ns tDDROHD2 Data_R Data Hold for Output DDR 0.00 ns tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 1.99 ns tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 ns tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.24 ns tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns FDDOMAX Maximum Frequency for the Output DDR 160.00 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 56 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs VersaTile Characteristics VersaTile Specifications as a Combinatorial Module The IGLOO nano library offers all combinations of LUT-3 combinatorial functions. In this section, timing characteristics are presented for a sample of the library. For more details, refer to the IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for Software v10.1. A A A OR2 NOR2 Y A AND2 A Y NAND2 B Y B A B C A XOR2 Y A A B C Y B B B Y INV NAND3 XOR3 Y A MAJ3 0 B Y MUX2 B Y 1 C S Figure 2-21 • Sample of Combinatorial Cells R ev i si o n 2 0 2- 57 IGLOO nano DC and Switching Characteristics tPD Fanout = 4 A Net NAND2 or Any Combinatorial Logic Length = 1 VersaTile B A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic tPD = MAX(tPD(RR), tPD(RF), tPD(FF), tPD(FR)) where edges are applicable for a particular combinatorial cell A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic A Net Length = 1 VersaTile B Y NAND2 or Any Combinatorial Logic VCC 50% 50% A, B, C GND VCC 50% 50% OUT GND VCC tPD tPD (FF) (RR) tPD OUT (FR) 50% tPD (RF) GND Figure 2-22 • Timing Model and Waveforms 2- 58 R ev i sio n 2 0 Y 50% IGLOO nano Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-84 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 0.76 ns Y=A·B tPD 0.87 ns Y = !(A · B) tPD 0.91 ns Y=A+B tPD 0.90 ns NOR2 Y = !(A + B) tPD 0.94 ns XOR2 Y=A⊕ B tPD 1.39 ns MAJ3 Y = MAJ(A, B, C) tPD 1.44 ns XOR3 Y=A⊕ B⊕ C tPD 1.60 ns MUX2 Y = A !S + B S tPD 1.17 ns AND3 Y=A·B·C tPD 1.18 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-85 • Combinatorial Cell Propagation Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Combinatorial Cell Equation Parameter Std. Units Y = !A tPD 1.33 ns Y=A·B tPD 1.48 ns Y = !(A · B) tPD 1.58 ns Y=A+B tPD 1.53 ns NOR2 Y = !(A + B) tPD 1.63 ns XOR2 Y=A⊕ B tPD 2.34 ns MAJ3 Y = MAJ(A, B, C) tPD 2.59 ns XOR3 Y=A⊕ B⊕ C tPD 2.74 ns MUX2 Y = A !S + B S tPD 2.03 ns AND3 Y=A·B·C tPD 2.11 ns INV AND2 NAND2 OR2 Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 2 0 2- 59 IGLOO nano DC and Switching Characteristics VersaTile Specifications as a Sequential Module The IGLOO nano library offers a wide variety of sequential cells, including flip-flops and latches. Each has a data input and optional enable, clear, or preset. In this section, timing characteristics are presented for a representative sample from the library. For more details, refer to the IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for Software v10.1. Data D Q Out Data Out D En DFN1 CLK Q DFN1E1 CLK PRE Data D Q Out En DFN1C1 CLK CLK CLR Figure 2-23 • Sample of Sequential Cells 2- 60 Data R ev i sio n 2 0 D Q DFI1E1P1 Out IGLOO nano Low Power Flash FPGAs tCKMPWH tCKMPWL CLK 50% 50% tSUD 50% Data 50% 50% 50% 50% 50% tHD 50% 0 EN 50% tHE PRE tRECPRE tWPRE 50% tSUE tREMPRE 50% 50% 50% CLR tPRE2Q 50% Out tREMCLR tRECCLR tWCLR 50% 50% tCLR2Q 50% 50% tCLKQ Figure 2-24 • Timing Model and Waveforms Timing Characteristics 1.5 V DC Core Voltage Table 2-86 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tCLKQ Clock-to-Q of the Core Register 0.89 ns tSUD Data Setup Time for the Core Register 0.81 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 0.73 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.60 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.62 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.23 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.56 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.56 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 61 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-87 • Register Delays Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Std. Units tCLKQ Clock-to-Q of the Core Register Description 1.61 ns tSUD Data Setup Time for the Core Register 1.17 ns tHD Data Hold Time for the Core Register 0.00 ns tSUE Enable Setup Time for the Core Register 1.29 ns tHE Enable Hold Time for the Core Register 0.00 ns tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.87 ns tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.89 ns tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 ns tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.24 ns tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 ns tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.24 ns tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.46 ns tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.46 ns tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.95 ns tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.95 ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 62 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Global Resource Characteristics AGLN125 Clock Tree Topology Clock delays are device-specific. Figure 2-25 is an example of a global tree used for clock routing. The global tree presented in Figure 2-25 is driven by a CCC located on the west side of the AGLN125 device. It is used to drive all D-flip-flops in the device. Central Global Rib VersaTile Rows CCC Global Spine Figure 2-25 • Example of Global Tree Use in an AGLN125 Device for Clock Routing R ev i si o n 2 0 2- 63 IGLOO nano DC and Switching Characteristics Global Tree Timing Characteristics Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer to the "Clock Conditioning Circuits" section on page 2-70. Table 2-88 to Table 2-95 on page 2-68 present minimum and maximum global clock delays within each device. Minimum and maximum delays are measured with minimum and maximum loading. Timing Characteristics 1.5 V DC Core Voltage Table 2-88 • AGLN010 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.13 1.42 ns tRCKH Input High Delay for Global Clock 1.15 1.50 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.35 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-89 • AGLN015 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Units ns ns ns ns ns Table 2-90 • AGLN020 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.21 1.55 ns tRCKH Input High Delay for Global Clock 1.23 1.65 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns 2- 64 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-90 • AGLN020 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter tRCKSW Description Min. 1 Max.2 Units 0.42 ns Maximum Skew for Global Clock Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-91 • AGLN060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.32 1.62 ns tRCKH Input High Delay for Global Clock 1.34 1.71 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.38 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 65 IGLOO nano DC and Switching Characteristics Table 2-92 • AGLN125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.36 1.71 ns tRCKH Input High Delay for Global Clock 1.39 1.82 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.43 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. Table 2-93 • AGLN250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.39 1.73 ns tRCKH Input High Delay for Global Clock 1.41 1.84 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.43 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 66 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-94 • AGLN010 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.71 2.09 ns tRCKH Input High Delay for Global Clock 1.78 2.31 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.53 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 2 0 2- 67 IGLOO nano DC and Switching Characteristics Table 2-95 • AGLN020 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 1.81 2.26 ns tRCKH Input High Delay for Global Clock 1.90 2.51 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.61 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-96 • AGLN060 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 2.02 2.42 ns tRCKH Input High Delay for Global Clock 2.09 2.65 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.56 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 68 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-97 • AGLN125 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min. 1 Max.2 Units tRCKL Input Low Delay for Global Clock 2.08 2.54 ns tRCKH Input High Delay for Global Clock 2.15 2.77 ns tRCKMPWH Minimum Pulse Width HIGH for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width LOW for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.62 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. Table 2-98 • AGLN250 Global Resource Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Std. Parameter Description Min.1 Max.2 Units tRCKL Input Low Delay for Global Clock 2.11 2.57 ns tRCKH Input High Delay for Global Clock 2.19 2.81 ns tRCKMPWH Minimum Pulse Width High for Global Clock 1.40 ns tRCKMPWL Minimum Pulse Width Low for Global Clock 1.65 ns tRCKSW Maximum Skew for Global Clock 0.62 ns Notes: 1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element, located in a lightly loaded row (single element is connected to the global net). 2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully loaded row (all available flip-flops are connected to the global net in the row). 3. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 2 0 2- 69 IGLOO nano DC and Switching Characteristics Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Table 2-99 • IGLOO nano CCC/PLL Specification For IGLOO nano V2 OR V5 Devices, 1.5 V DC Core Supply Voltage Parameter Min. Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Typ. 0.75 1, 2 360 Units 250 MHz 250 MHz 3 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic Max. ps 32 PLL 4,9 100 MHz 1 ns LockControl = 0 300 µs LockControl = 1 6.0 ms LockControl = 0 2.5 ns LockControl = 1 1.5 ns 48.5 51.5 % 1.25 15.65 ns 0.025 15.65 ns Input Cycle-to-Cycle Jitter (peak magnitude) Acquisition Time Tracking Jitter 5 Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2, 1, 2 VCO Output Peak-to-Peak Period Jitter 3.5 FCCC_OUT6 Max Peak-to-Peak Jitter ns Data 6,7,8 SSO ≤ 2 SSO ≤ 4 SSO ≤ 8 SSO ≤ 16 0.75 MHz to 50 MHz 0.50 0.60 0.80 1.20 % 50 MHz to 250 MHz 2.50 4.00 6.00 12.00 % Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.5 V 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT, regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, no matter what the settings are for the output divider. 7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.425 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 8. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out times within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO nano FPGA Fabric User’s Guide. 9. The AGLN010 and AGLN020 devices do not support PLLs. 2- 70 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Table 2-100 • IGLOO nano CCC/PLL Specification For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage Parameter Min. 1.5 Clock Conditioning Circuitry Input Frequency fIN_CCC 0.75 Clock Conditioning Circuitry Output Frequency fOUT_CCC Delay Increments in Programmable Delay Blocks Typ. 1, 2 Units 160 MHz 160 MHz 3 580 Number of Programmable Values in Each Programmable Delay Block Serial Clock (SCLK) for Dynamic PLL Max. ps 32 4,9 60 Input Cycle-to-Cycle Jitter (peak magnitude) 0.25 ns LockControl = 0 300 µs LockControl = 1 6.0 ms LockControl = 0 4 ns LockControl = 1 3 ns 48.5 51.5 % 2.3 20.86 ns 0.025 20.86 ns Acquisition Time Tracking Jitter 5 Output Duty Cycle Delay Range in Block: Programmable Delay 1 1, 2 Delay Range in Block: Programmable Delay 2 Delay Range in Block: Fixed Delay 1, 2 1, 2 VCO Output Peak-to-Peak Period Jitter FCCC_OUT 5.7 6 ns Max Peak-to-Peak Period Jitter 6,7,8 SSO ≤ 2 SSO ≤ 4 SSO ≤ 8 SSO ≤ 16 0.75 MHz to 50MHz 0.50 1.20 2.00 3.00 % 50 MHz to 100 MHz 2.50 5.00 7.00 15.00 % Notes: 1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings. 2. TJ = 25°C, VCC = 1.2 V. 3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay increments are available. Refer to the Libero SoC Online Help associated with the core for more information. 4. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values. 5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter. 6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT, regardless of the output divider settings. For example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, no matter what the settings are for the output divider. 7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V, VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load. 8. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out times within ±200 ps of each other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed Circuit Board Layout" section in the IGLOO nano FPGA Fabric User’s Guide. 9. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs. R ev i si o n 2 0 2- 71 IGLOO nano DC and Switching Characteristics Output Signal Tperiod_max Tperiod_min Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min. Figure 2-26 • Peak-to-Peak Jitter Definition 2- 72 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Embedded SRAM and FIFO Characteristics SRAM RAM512X18 RAM4K9 ADDRA11 ADDRA10 DOUTA8 DOUTA7 RADDR8 RADDR7 RD17 RD16 ADDRA0 DINA8 DINA7 DOUTA0 RADDR0 RD0 RW1 RW0 DINA0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA PIPE REN RCLK ADDRB11 ADDRB10 DOUTB8 DOUTB7 ADDRB0 DOUTB0 DINB8 DINB7 WADDR8 WADDR7 WADDR0 WD17 WD16 WD0 DINB0 WW1 WW0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WEN WCLK RESET RESET Figure 2-27 • RAM Models R ev i si o n 2 0 2- 73 IGLOO nano DC and Switching Characteristics Timing Waveforms tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENS tENH WEN tCKQ1 DOUT|RD Dn D0 D1 D2 tDOH1 Figure 2-28 • RAM Read for Pass-Through Output. Applicable to Both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK t AS tAH A1 A0 [R|W]ADDR A2 tBKS tBKH BLK tENH tENS WEN tCKQ2 DOUT|RD Dn D0 D1 tDOH2 Figure 2-29 • RAM Read for Pipelined Output. Applicable to Both RAM4K9 and RAM512x18. 2- 74 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs tCYC tCKH tCKL CLK tAS tAH A0 [R|W]ADDR A1 A2 tBKS tBKH BLK tENS tENH WEN tDS DI0 DIN|WD tDH DI1 D2 Dn DOUT|RD Figure 2-30 • RAM Write, Output Retained (WMODE = 0). Applicable to Both RAM4K9 and RAM512x18. tCYC tCKH tCKL CLK tAS tAH A0 ADDR A1 A2 tBKS tBKH BLK tENS WEN tDS DI0 DIN DOUT (pass-through) DOUT (pipelined) tDH DI1 Dn DI2 DI1 DI0 DI0 Dn DI1 Figure 2-31 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only. R ev i si o n 2 0 2- 75 IGLOO nano DC and Switching Characteristics tCYC tCKH tCKL CLK RESET tRSTBQ DOUT|RD Dm Dn Figure 2-32 • RAM Reset. Applicable to Both RAM4K9 and RAM512x18. 2- 76 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-101 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.68 ns tENH REN, WEN hold time 0.13 ns tBKS BLK setup time 1.37 ns tBKH BLK hold time 0.13 ns tDS Input data (DIN) setup time 0.59 ns tDH Input data (DIN) hold time 0.30 ns tCKQ1 Clock HIGH to new data valid on DOUT (output retained, WMODE = 0) 2.94 ns Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1) 2.55 ns Clock HIGH to new data valid on DOUT (pipelined) 1.51 ns 1 Address collision clk-to-clk delay for reliable write after write on same address; applicable 0.23 to closing edge ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address; 0.35 applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address; 0.41 applicable to opening edge ns tRSTBQ RESET Low to data out Low on DOUT (flow-through) 1.72 ns RESET Low to data out Low on DOUT (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 ns tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz tCKQ2 tC2CWWL Notes: 1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based FPGAs and SoC FPGAs App Note. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 77 IGLOO nano DC and Switching Characteristics Table 2-102 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tAS Address setup time 0.69 ns tAH Address hold time 0.13 ns tENS REN, WEN setup time 0.61 ns tENH REN, WEN hold time 0.07 ns tDS Input data (WD) setup time 0.59 ns tDH Input data (WD) hold time 0.30 ns tCKQ1 Clock HIGH to new data valid on RD (output retained) 3.51 ns Clock HIGH to new data valid on RD (pipelined) 1.43 ns 1 Address collision clk-to-clk delay for reliable read access after write on same address; 0.35 applicable to opening edge ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address; 0.42 applicable to opening edge ns tCKQ2 tC2CRWH tRSTBQ RESET Low to data out Low on RD (flow-through) 1.72 ns RESET Low to data out Low on RD (pipelined) 1.72 ns tREMRSTB RESET removal 0.51 0.51 tRECRSTB RESET recovery 2.68 ns tMPWRSTB RESET minimum pulse width 0.68 ns tCYC Clock cycle time 6.24 ns FMAX Maximum frequency 160 MHz Notes: 1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based FPGAs and SoC FPGAs App Note. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 78 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs 1.2 V DC Core Voltage Table 2-103 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Std. Units tAS Address setup time Description 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.25 ns tENH REN, WEN hold time 0.25 ns tBKS BLK setup time 2.54 ns tBKH BLK hold time 0.25 ns tDS Input data (DIN) setup time 1.10 ns tDH Input data (DIN) hold time 0.55 ns tCKQ1 Clock HIGH to new data valid on DOUT (output retained, WMODE = 0) 5.51 ns Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1) 4.77 ns Clock HIGH to new data valid on DOUT (pipelined) 2.82 ns 1 Address collision clk-to-clk delay for reliable write after write on same address; applicable to closing edge 0.30 ns tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.89 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 1.01 ns tRSTBQ RESET LOW to data out LOW on DOUT (flow-through) 3.21 ns RESET LOW to data out LOW on DO (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz tCKQ2 tC2CWWL Notes: 1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based FPGAs and SoC FPGAs App Note. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. R ev i si o n 2 0 2- 79 IGLOO nano DC and Switching Characteristics Table 2-104 • RAM512X18 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tAS Address setup time 1.28 ns tAH Address hold time 0.25 ns tENS REN, WEN setup time 1.13 ns tENH REN, WEN hold time 0.13 ns tDS Input data (WD) setup time 1.10 ns tDH Input data (WD) hold time 0.55 ns tCKQ1 Clock High to new data valid on RD (output retained) 6.56 ns Clock High to new data valid on RD (pipelined) 2.67 ns 1 Address collision clk-to-clk delay for reliable read access after write on same address; applicable to opening edge 0.87 ns tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same address; applicable to opening edge 1.04 ns tRSTBQ RESET LOW to data out LOW on RD (flow through) 3.21 ns RESET LOW to data out LOW on RD (pipelined) 3.21 ns tREMRSTB RESET removal 0.93 ns tRECRSTB RESET recovery 4.94 ns tMPWRSTB RESET minimum pulse width 1.18 ns tCYC Clock cycle time 10.90 ns FMAX Maximum frequency 92 MHz tCKQ2 tC2CRWH Notes: 1. For more information, refer to the application note AC374: Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based FPGAs and SoC FPGAs App Note. 2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 80 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs FIFO FIFO4K18 RW2 RW1 RW0 WW2 WW1 WW0 ESTOP FSTOP RD17 RD16 RD0 FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 AEVAL0 AFVAL11 AFVAL10 AFVAL0 REN RBLK RCLK WD17 WD16 WD0 WEN WBLK WCLK RPIPE RESET Figure 2-33 • FIFO Model R ev i si o n 2 0 2- 81 IGLOO nano DC and Switching Characteristics Timing Waveforms tCYC RCLK tENH tENS REN tBKH tBKS RBLK tCKQ1 RD (flow-through) Dn D0 D1 D2 D0 D1 tCKQ2 RD (pipelined) Dn Figure 2-34 • FIFO Read tCYC WCLK tENS tENH WEN WBLK tBKS tBKH tDS WD DI0 tDH DI1 Figure 2-35 • FIFO Write 2- 82 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs RCLK/ WCLK tMPWRSTB tRSTCK RESET tRSTFG EMPTY tRSTAF AEMPTY tRSTFG FULL tRSTAF AFULL WA/RA (Address Counter) MATCH (A0) Figure 2-36 • FIFO Reset tCYC RCLK tRCKEF EMPTY tCKAF AEMPTY WA/RA (Address Counter) NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY) Figure 2-37 • FIFO EMPTY Flag and AEMPTY Flag Assertion R ev i si o n 2 0 2- 83 IGLOO nano DC and Switching Characteristics tCYC WCLK tWCKFF FULL tCKAF AFULL WA/RA NO MATCH (Address Counter) NO MATCH Dist = AFF_TH MATCH (FULL) Figure 2-38 • FIFO FULL Flag and AFULL Flag Assertion WCLK WA/RA MATCH (Address Counter) (EMPTY) RCLK NO MATCH 1st Rising Edge After 1st Write NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1 2nd Rising Edge After 1st Write tRCKEF EMPTY tCKAF AEMPTY Figure 2-39 • FIFO EMPTY Flag and AEMPTY Flag Deassertion RCLK WA/RA (Address Counter) WCLK MATCH (FULL) NO MATCH 1st Rising Edge After 1st Read NO MATCH NO MATCH NO MATCH Dist = AFF_TH – 1 1st Rising Edge After 2nd Read tWCKF FULL tCKAF AFULL Figure 2-40 • FIFO FULL Flag and AFULL Flag Deassertion 2- 84 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Timing Characteristics 1.5 V DC Core Voltage Table 2-105 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tENS REN, WEN Setup Time 1.66 ns tENH REN, WEN Hold Time 0.13 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (WD) Setup Time 0.63 ns tDH Input Data (WD) Hold Time 0.20 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 2.77 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 1.50 ns tRCKEF RCLK High to Empty Flag Valid 2.94 ns tWCKFF WCLK High to Full Flag Valid 2.79 ns tCKAF Clock High to Almost Empty/Full Flag Valid 10.71 ns tRSTFG RESET Low to Empty/Full Flag Valid 2.90 ns tRSTAF RESET Low to Almost Empty/Full Flag Valid 10.60 ns tRSTBQ RESET Low to Data Out LOW on RD (flow-through) 1.68 ns RESET Low to Data Out LOW on RD (pipelined) 1.68 ns tREMRSTB RESET Removal 0.51 ns tRECRSTB RESET Recovery 2.68 ns tMPWRSTB RESET Minimum Pulse Width 0.68 ns tCYC Clock Cycle Time 6.24 ns FMAX Maximum Frequency for FIFO 160 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. R ev i si o n 2 0 2- 85 IGLOO nano DC and Switching Characteristics 1.2 V DC Core Voltage Table 2-106 • FIFO Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description Std. Units tENS REN, WEN Setup Time 3.44 ns tENH REN, WEN Hold Time 0.26 ns tBKS BLK Setup Time 0.30 ns tBKH BLK Hold Time 0.00 ns tDS Input Data (DI) Setup Time 1.30 ns tDH Input Data (DI) Hold Time 0.41 ns tCKQ1 Clock High to New Data Valid on RD (flow-through) 5.67 ns tCKQ2 Clock High to New Data Valid on RD (pipelined) 3.02 ns tRCKEF RCLK High to Empty Flag Valid 6.02 ns tWCKFF WCLK High to Full Flag Valid 5.71 ns tCKAF Clock High to Almost Empty/Full Flag Valid 22.17 ns tRSTFG RESET LOW to Empty/Full Flag Valid 5.93 ns tRSTAF RESET LOW to Almost Empty/Full Flag Valid 21.94 ns tRSTBQ RESET LOW to Data Out Low on RD (flow-through) 3.41 ns RESET LOW to Data Out Low on RD (pipelined) 4.09 3.41 tREMRSTB RESET Removal 1.02 ns tRECRSTB RESET Recovery 5.48 ns tMPWRSTB RESET Minimum Pulse Width 1.18 ns tCYC Clock Cycle Time 10.90 ns FMAX Maximum Frequency for FIFO 92 MHz Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values. 2- 86 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs Embedded FlashROM Characteristics tSU CLK tSU tHOLD Address tSU tHOLD A0 tHOLD A1 tCKQ2 tCKQ2 D0 Data tCKQ2 D0 D1 Figure 2-41 • Timing Diagram Timing Characteristics 1.5 V DC Core Voltage Table 2-107 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V Parameter Description Std. Units tSU Address Setup Time 0.57 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 20.90 ns FMAX Maximum Clock Frequency 15 MHz Std. Units 1.2 V DC Core Voltage Table 2-108 • Embedded FlashROM Access Time Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V Parameter Description tSU Address Setup Time 0.59 ns tHOLD Address Hold Time 0.00 ns tCK2Q Clock to Out 35.74 ns FMAX Maximum Clock Frequency 10 MHz R ev i si o n 2 0 2- 87 IGLOO nano DC and Switching Characteristics JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-15 for more details. Timing Characteristics 1.5 V DC Core Voltage Table 2-109 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.00 ns tDIHD Test Data Input Hold Time 2.00 ns tTMSSU Test Mode Select Setup Time 1.00 ns tTMDHD Test Mode Select Hold Time 2.00 ns tTCK2Q Clock to Q (data out) 8.00 ns tRSTB2Q Reset to Q (data out) 25.00 ns FTCKMAX TCK Maximum Frequency 15 MHz tTRSTREM ResetB Removal Time 0.58 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 1.2 V DC Core Voltage Table 2-110 • JTAG 1532 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description Std. Units tDISU Test Data Input Setup Time 1.50 ns tDIHD Test Data Input Hold Time 3.00 ns tTMSSU Test Mode Select Setup Time 1.50 ns tTMDHD Test Mode Select Hold Time 3.00 ns tTCK2Q Clock to Q (data out) 11.00 ns tRSTB2Q Reset to Q (data out) 30.00 ns FTCKMAX TCK Maximum Frequency 9.00 MHz tTRSTREM ResetB Removal Time 1.18 ns tTRSTREC ResetB Recovery Time 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. 2- 88 R ev i sio n 2 0 3 – Pin Descriptions Supply Pins GND Ground Ground supply voltage to the core, I/O outputs, and I/O logic. GNDQ Ground (quiet) Quiet ground supply voltage to input buffers of I/O banks. Within the package, the GNDQ plane is decoupled from the simultaneous switching noise originated from the output buffer ground domain. This minimizes the noise transfer within the package and improves input signal integrity. GNDQ must always be connected to GND on the board. VCC Core Supply Voltage Supply voltage to the FPGA core, nominally 1.5 V for IGLOO nano V5 devices, and 1.2 V or 1.5 V for IGLOO nano V2 devices. VCC is required for powering the JTAG state machine in addition to VJTAG. Even when a device is in bypass mode in a JTAG chain of interconnected devices, both VCC and VJTAG must remain powered to allow JTAG signals to pass through the device. VCCIBx I/O Supply Voltage Supply voltage to the bank's I/O output buffers and I/O logic. Bx is the I/O bank number. There are up to eight I/O banks on low power flash devices plus a dedicated VJTAG bank. Each bank can have a separate VCCI connection. All I/Os in a bank will run off the same VCCIBx supply. VCCI can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VCCI pins tied to GND. VMVx I/O Supply Voltage (quiet) Quiet supply voltage to the input buffers of each I/O bank. x is the bank number. Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks. This minimizes the noise transfer within the package and improves input signal integrity. Each bank must have at least one VMV connection, and no VMV should be left unconnected. All I/Os in a bank run off the same VMVx supply. VMV is used to provide a quiet supply voltage to the input buffers of each I/O bank. VMVx can be 1.2 V, 1.5 V, 1.8 V, 2.5 V, or 3.3 V, nominal voltage. Unused I/O banks should have their corresponding VMV pins tied to GND. VMV and VCCI should be at the same voltage within a given I/O bank. Used VMV pins must be connected to the corresponding VCCI pins of the same bank (i.e., VMV0 to VCCIB0, VMV1 to VCCIB1, etc.). VCCPLA/B/C/D/E/F PLL Supply Voltage Supply voltage to analog PLL, nominally 1.5 V or 1.2 V. When the PLLs are not used, the Microsemi Designer place-and-route tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. Microsemi recommends tying VCCPLx to VCC and using proper filtering circuits to decouple VCC noise from the PLLs. Refer to the PLL Power Supply Decoupling section of the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter in the IGLOO nano FPGA Fabric User’s Guide for a complete board solution for the PLL analog power supply and ground. There is one VCCPLF pin on IGLOO nano devices. VCOMPLA/B/C/D/E/F PLL Ground Ground to analog PLL power supplies. When the PLLs are not used, the Microsemi Designer place-androute tool automatically disables the unused PLLs to lower power consumption. The user should tie unused VCCPLx and VCOMPLx pins to ground. There is one VCOMPLF pin on IGLOO nano devices. VJTAG JTAG Supply Voltage Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG R ev i si o n 2 0 3-1 Pin Descriptions interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. It should be noted that VCC is required to be powered for JTAG operation; VJTAG alone is insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals will not be able to transition the device, even in bypass mode. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. VPUMP Programming Supply Voltage IGLOO nano devices support single-voltage ISP of the configuration flash and FlashROM. For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming power supply voltage (VPUMP) range is listed in the datasheet. When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of oscillation from the charge pump circuitry. For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible. Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent filtering capacitors rather than supplying them from a common rail. User Pins I/O User Input/Output The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are compatible with the I/O standard selected. During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC supplies continuously powered up, when the device transitions from programming to operating mode, the I/Os are instantly configured to the desired user configuration. Unused I/Os are configured as follows: GL • Output buffer is disabled (with tristate value of high impedance) • Input buffer is disabled (with tristate value of high impedance) • Weak pull-up is programmed Globals GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have identical capabilities. Unused GL pins are configured as inputs with pull-up resistors. See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in IGLOO and ProASIC3 Devices" chapter in the IGLOO nano FPGA Fabric User’s Guide. All inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals. The inputs to the global network are multiplexed, and only one input can be used as a global input. Refer to the "I/O Structures in nano Devices" chapter of the IGLOO nano FPGA Fabric User’s Guide for an explanation of the naming of global pins. FF Flash*Freeze Mode Activation Pin Flash*Freeze is available on IGLOO nano devices. The FF pin is a dedicated input pin used to enter and exit Flash*Freeze mode. The FF pin is active low, has the same characteristics as a single-ended I/O, and must meet the maximum rise and fall times. When Flash*Freeze mode is not used in the design, the FF pin is available as a regular I/O. When Flash*Freeze mode is used, the FF pin must not be left floating to avoid accidentally entering Flash*Freeze mode. While in Flash*Freeze mode, the Flash*Freeze pin should be constantly asserted. The Flash*Freeze pin can be used with any single-ended I/O standard supported by the I/O bank in which the pin is located, and input signal levels compatible with the I/O standard selected. The FF pin 3- 2 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs should be treated as a sensitive asynchronous signal. When defining pin placement and board layout, simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be considered. Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both Flash*Freeze mode and normal operation mode. No user intervention is required. Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO nano devices. The Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to larger or smaller IGLOO nano devices while maintaining the same pin location on the board. Refer to the "Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO nano FPGA Fabric User’s Guide for more information on I/O states during Flash*Freeze mode. Table 3-1 • Flash*Freeze Pin Locations for IGLOO nano Devices Package Flash*Freeze Pin CS81/UC81 H2 QN48 14 QN68 18 VQ100 27 UC36 E2 JTAG Pins Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST pin could be tied to GND. TCK Test Clock Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired state. Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Refer to Table 3-2 for more information. Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins Tie-Off Resistance 1,2 VJTAG VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Notes: 1. The TCK pin can be pulled-up or pulled-down. 2. The TRST pin is pulled-down. 3. Equivalent parallel resistance if more than one device is on the JTAG chain R ev i si o n 2 0 3-3 Pin Descriptions Table 3-3 • TRST and TCK Pull-Down Recommendations VJTAG Tie-Off Resistance* VJTAG at 3.3 V 200 Ω to 1 kΩ VJTAG at 2.5 V 200 Ω to 1 kΩ VJTAG at 1.8 V 500 Ω to 1 kΩ VJTAG at 1.5 V 500 Ω to 1 kΩ Note: Equivalent parallel resistance if more than one device is on the JTAG chain TDI Test Data Input Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal weak pull-up resistor on the TDI pin. TDO Test Data Output Serial output for JTAG boundary scan, ISP, and UJTAG usage. TMS Test Mode Select The TMS pin controls the use of the IEEE 1532 boundary scan pins (TCK, TDI, TDO, TRST). There is an internal weak pull-up resistor on the TMS pin. TRST Boundary Scan Reset Pin The TRST pin functions as an active-low input to asynchronously initialize (or reset) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST pin. If JTAG is not used, an external pull-down resistor could be included to ensure the test access port (TAP) is held in reset mode. The resistor values must be chosen from Table 3-2 and must satisfy the parallel resistance value requirement. The values in Table 3-2 correspond to the resistor recommended when a single device is used, and the equivalent parallel resistor when multiple devices are connected via a JTAG chain. In critical applications, an upset in the JTAG circuit could allow entrance to an undesired JTAG state. In such cases, Microsemi recommends tying off TRST to GND through a resistor placed close to the FPGA pin. Note that to operate at all VJTAG voltages, 500 Ω to 1 kΩ will satisfy the requirements. Special Function Pins NC No Connect This pin is not connected to circuitry within the device. These pins can be driven to any voltage or can be left floating with no effect on the operation of the device. DC Do Not Connect This pin should not be connected to any signals on the PCB. These pins should be left unconnected. Packaging Semiconductor technology is constantly shrinking in size while growing in capability and functional integration. To enable next-generation silicon technologies, semiconductor packages have also evolved to provide improved performance and flexibility. Microsemi consistently delivers packages that provide the necessary mechanical and environmental protection to ensure consistent reliability and performance. Microsemi IC packaging technology efficiently supports high-density FPGAs with large-pin-count Ball Grid Arrays (BGAs), but is also flexible enough to accommodate stringent form factor requirements for Chip Scale Packaging (CSP). In addition, Microsemi offers a variety of packages designed to meet your most demanding application and economic requirements for today's embedded and mobile systems. 3- 4 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Related Documents User Guides IGLOO nano FPGA Fabric User’s Guide Packaging Documents The following documents provide packaging information and device selection for low power flash devices. Product Catalog FPGA and SoC Product Catalog Lists devices currently recommended for new designs and the packages available for each member of the family. Use this document or the datasheet tables to determine the best package for your design, and which package drawing to use. Package Mechanical Drawings This document contains the package mechanical drawings for all packages currently or previously supplied by Microsemi. Use the bookmarks to navigate to the package mechanical drawings. Additional packaging materials are on the Microsemi SoC Products Group website: http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 2 0 3-5 4 – Package Pin Assignments UC36 Pin 1 Pad Corner 6 5 4 3 2 1 A B C D E F Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. R ev i si o n 2 0 4-1 Package Pin Assignments UC36 UC36 Pin Number AGLN010 Function Pin Number AGLN010 Function A1 IO21RSB1 F5 TMS A2 IO18RSB1 F6 TDO A3 IO13RSB1 A4 GDC0/IO00RSB0 A5 IO06RSB0 A6 GDA0/IO04RSB0 B1 GEC0/IO37RSB1 B2 IO20RSB1 B3 IO15RSB1 B4 IO09RSB0 B5 IO08RSB0 B6 IO07RSB0 C1 IO22RSB1 C2 GEA0/IO34RSB1 C3 GND C4 GND C5 VCCIB0 C6 IO02RSB0 D1 IO33RSB1 D2 VCCIB1 D3 VCC D4 VCC D5 IO10RSB0 D6 IO11RSB0 E1 IO32RSB1 E2 FF/IO31RSB1 E3 TCK E4 VPUMP E5 TRST E6 VJTAG F1 IO29RSB1 F2 IO25RSB1 F3 IO23RSB1 F4 TDI 4- 2 R ev isio n 2 0 Package Pin Assignments UC81 A1 Ball Pad Corner 9 8 7 6 5 4 3 2 1 A B C D E F G H J Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 3 R ev isio n 2 0 Package Pin Assignments CS81 A1 Ball Pad Corner 9 8 7 6 5 4 3 2 1 A B C D E F G H J Note: This is the bottom view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. 4- 4 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs CS81 CS81 CS81 Pin Number AGLN020 Function Pin Number AGLN020 Function Pin Number AGLN020 Function A1 IO64RSB2 E1 GEC0/IO48RSB2 J1 IO38RSB1 A2 IO54RSB2 E2 GEA0/IO47RSB2 J2 IO37RSB1 A3 IO57RSB2 E3 NC J3 IO33RSB1 A4 IO36RSB1 E4 VCCIB1 J4 IO30RSB1 A5 IO32RSB1 E5 VCC J5 IO27RSB1 A6 IO24RSB1 E6 VCCIB0 J6 IO23RSB1 A7 IO20RSB1 E7 NC J7 TCK A8 IO04RSB0 E8 GDA0/IO15RSB0 J8 TMS A9 IO08RSB0 E9 GDC0/IO14RSB0 J9 VPUMP B1 IO59RSB2 F1 IO46RSB2 B2 IO55RSB2 F2 IO45RSB2 B3 IO62RSB2 F3 NC B4 IO34RSB1 F4 GND B5 IO28RSB1 F5 VCCIB1 B6 IO22RSB1 F6 NC B7 IO18RSB1 F7 NC B8 IO00RSB0 F8 IO16RSB0 B9 IO03RSB0 F9 IO17RSB0 C1 IO51RSB2 G1 IO43RSB2 C2 IO50RSB2 G2 IO42RSB2 C3 NC G3 IO41RSB2 C4 NC G4 IO31RSB1 C5 NC G5 NC C6 NC G6 IO21RSB1 C7 NC G7 NC C8 IO10RSB0 G8 VJTAG C9 IO07RSB0 G9 TRST D1 IO49RSB2 H1 IO40RSB2 D2 IO44RSB2 H2 FF/IO39RSB1 D3 NC H3 IO35RSB1 D4 VCC H4 IO29RSB1 D5 VCCIB2 H5 IO26RSB1 D6 GND H6 IO25RSB1 D7 NC H7 IO19RSB1 D8 IO13RSB0 H8 TDI D9 IO12RSB0 H9 TDO R ev i si o n 2 0 4-5 Package Pin Assignments CS81 CS81 CS81 Pin Number AGLN060 Function Pin Number AGLN060 Function Pin Number AGLN060 Function A1 GAA0/IO02RSB0 E1 GFB0/IO83RSB1 J1 GEA2/IO68RSB1 A2 GAA1/IO03RSB0 E2 GFB1/IO84RSB1 J2 GEC2/IO66RSB1 A3 GAC0/IO06RSB0 E3 GFA1/IO81RSB1 J3 IO64RSB1 A4 IO09RSB0 E4 VCCIB1 J4 IO61RSB1 A5 IO13RSB0 E5 VCC J5 IO58RSB1 A6 IO18RSB0 E6 VCCIB0 J6 IO55RSB1 A7 GBB0/IO21RSB0 E7 GCA1/IO39RSB0 J7 TCK A8 GBA1/IO24RSB0 E8 GCA0/IO40RSB0 J8 TMS A9 GBA2/IO25RSB0 E9 GCB2/IO42RSB0 J9 VPUMP GAA2/IO95RSB1 1 VCCPLF 1 B1 4- 6 F1 B2 GAB0/IO04RSB0 F2 VCOMPLF B3 GAC1/IO07RSB0 F3 GND B4 IO08RSB0 F4 GND B5 IO15RSB0 F5 VCCIB1 B6 GBC0/IO19RSB0 F6 GND B7 GBB1/IO22RSB0 F7 GDA1/IO49RSB0 B8 IO26RSB0 F8 GDC1/IO45RSB0 B9 GBB2/IO27RSB0 F9 GDC0/IO46RSB0 C1 GAB2/IO93RSB1 G1 GEA0/IO69RSB1 C2 IO94RSB1 G2 GEC1/IO74RSB1 C3 GND G3 GEB1/IO72RSB1 C4 IO10RSB0 G4 IO63RSB1 C5 IO17RSB0 G5 IO60RSB1 C6 GND G6 IO54RSB1 C7 GBA0/IO23RSB0 G7 GDB2/IO52RSB1 C8 GBC2/IO29RSB0 G8 VJTAG C9 IO31RSB0 G9 TRST D1 GAC2/IO91RSB1 H1 GEA1/IO70RSB1 D2 IO92RSB1 H2 FF/GEB2/IO67RSB1 D3 GFA2/IO80RSB1 H3 IO65RSB1 D4 VCC H4 IO62RSB1 D5 VCCIB0 H5 IO59RSB1 D6 GND H6 IO56RSB1 2 GDA2/IO51RSB1 D7 GCC2/IO43RSB0 H7 D8 GCC1/IO35RSB0 H8 TDI D9 GCC0/IO36RSB0 H9 TDO R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs CS81 CS81 CS81 Pin Number AGLN125 Function Pin Number AGLN125 Function Pin Number AGLN125 Function A1 GAA0/IO00RSB0 E1 GFB0/IO120RSB1 J1 GEA2/IO103RSB1 A2 GAA1/IO01RSB0 E2 GFB1/IO121RSB1 J2 GEC2/IO101RSB1 A3 GAC0/IO04RSB0 E3 GFA1/IO118RSB1 J3 IO97RSB1 A4 IO13RSB0 E4 VCCIB1 J4 IO93RSB1 A5 IO22RSB0 E5 VCC J5 IO90RSB1 A6 IO32RSB0 E6 VCCIB0 J6 IO78RSB1 A7 GBB0/IO37RSB0 E7 GCA0/IO56RSB0 J7 TCK A8 GBA1/IO40RSB0 E8 GCA1/IO55RSB0 J8 TMS A9 GBA2/IO41RSB0 E9 GCB2/IO58RSB0 J9 VPUMP B1 GAA2/IO132RSB1 F1* VCCPLF B2 GAB0/IO02RSB0 F2* VCOMPLF B3 GAC1/IO05RSB0 F3 GND B4 IO11RSB0 F4 GND B5 IO25RSB0 F5 VCCIB1 B6 GBC0/IO35RSB0 F6 GND B7 GBB1/IO38RSB0 F7 GDA1/IO65RSB0 B8 IO42RSB0 F8 GDC1/IO61RSB0 B9 GBB2/IO43RSB0 F9 GDC0/IO62RSB0 C1 GAB2/IO130RSB1 G1 GEA0/IO104RSB1 C2 IO131RSB1 G2 GEC0/IO108RSB1 C3 GND G3 GEB1/IO107RSB1 C4 IO15RSB0 G4 IO96RSB1 C5 IO28RSB0 G5 IO92RSB1 C6 GND G6 IO72RSB1 C7 GBA0/IO39RSB0 G7 GDB2/IO68RSB1 C8 GBC2/IO45RSB0 G8 VJTAG C9 IO47RSB0 G9 TRST D1 GAC2/IO128RSB1 H1 GEA1/IO105RSB1 D2 IO129RSB1 H2 FF/GEB2/IO102RSB1 D3 GFA2/IO117RSB1 H3 IO99RSB1 D4 VCC H4 IO94RSB1 D5 VCCIB0 H5 IO91RSB1 D6 GND H6 IO81RSB1 D7 GCC2/IO59RSB0 H7 GDA2/IO67RSB1 D8 GCC1/IO51RSB0 H8 TDI D9 GCC0/IO52RSB0 H9 TDO R ev i si o n 2 0 4-7 Package Pin Assignments CS81 CS81 CS81 Pin Number AGLN250 Function Pin Number AGLN250 Function Pin Number AGLN250 Function A1 GAA0/IO00RSB0 E1 GFB0/IO59RSB3 J1 GEA2/IO50RSB2 A2 GAA1/IO01RSB0 E2 GFB1/IO60RSB3 J2 GEC2/IO48RSB2 A3 GAC0/IO04RSB0 E3 GFA1/IO58RSB3 J3 IO46RSB2 A4 IO07RSB0 E4 VCCIB3 J4 IO43RSB2 A5 IO09RSB0 E5 VCC J5 IO40RSB2 A6 IO12RSB0 E6 VCCIB1 J6 IO38RSB2 A7 GBB0/IO16RSB0 E7 GCA0/IO28RSB1 J7 TCK A8 GBA1/IO19RSB0 E8 GCA1/IO27RSB1 J8 TMS A9 GBA2/IO20RSB1 E9 GCB2/IO29RSB1 J9 VPUMP B1 GAA2/IO67RSB3 F1 VCCPLF B2 GAB0/IO02RSB0 F2 VCOMPLF B3 GAC1/IO05RSB0 F3 GND B4 IO06RSB0 F4 GND B5 IO10RSB0 F5 VCCIB2 B6 GBC0/IO14RSB0 F6 GND B7 GBB1/IO17RSB0 F7 GDA1/IO33RSB1 B8 IO21RSB1 F8 GDC1/IO31RSB1 B9 GBB2/IO22RSB1 F9 GDC0/IO32RSB1 C1 GAB2/IO65RSB3 G1 GEA0/IO51RSB3 C2 IO66RSB3 G2 GEC1/IO54RSB3 C3 GND G3 GEC0/IO53RSB3 C4 IO08RSB0 G4 IO45RSB2 C5 IO11RSB0 G5 IO42RSB2 C6 GND G6 IO37RSB2 C7 GBA0/IO18RSB0 G7 GDB2/IO35RSB2 C8 GBC2/IO23RSB1 G8 VJTAG C9 IO24RSB1 G9 TRST D1 GAC2/IO63RSB3 H1 GEA1/IO52RSB3 D2 IO64RSB3 H2 FF/GEB2/IO49RSB2 D3 GFA2/IO56RSB3 H3 IO47RSB2 D4 VCC H4 IO44RSB2 D5 VCCIB0 H5 IO41RSB2 D6 GND H6 IO39RSB2 D7 IO30RSB1 H7 GDA2/IO34RSB2 D8 GCC1/IO25RSB1 H8 TDI D9 GCC0/IO26RSB1 H9 TDO 4- 8 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs QN48 Pin 1 48 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Notes: 1. Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN060-CS81. 2. The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin H7 in AGLN060-CS81. R ev i si o n 2 0 4-9 Package Pin Assignments QN48 QN48 Pin Number AGLN010 Function Pin Number AGLN010 Function 1 GEC0/IO37RSB1 34 GND 2 IO36RSB1 35 VCC 3 GEA0/IO34RSB1 36 IO07RSB0 4 IO22RSB1 37 IO06RSB0 5 GND 38 GDA0/IO05RSB0 6 VCCIB1 39 IO03RSB0 7 IO24RSB1 40 GDC0/IO01RSB0 8 IO33RSB1 41 IO12RSB1 9 IO26RSB1 42 IO13RSB1 10 IO32RSB1 43 IO15RSB1 11 IO27RSB1 44 IO16RSB1 12 IO29RSB1 45 IO18RSB1 13 IO30RSB1 46 IO19RSB1 14 FF/IO31RSB1 47 IO20RSB1 15 IO28RSB1 48 IO21RSB1 16 IO25RSB1 17 IO23RSB1 18 VCC 19 VCCIB1 20 IO17RSB1 21 IO14RSB1 22 TCK 23 TDI 24 TMS 25 VPUMP 26 TDO 27 TRST 28 VJTAG 29 IO11RSB0 30 IO10RSB0 31 IO09RSB0 32 IO08RSB0 33 VCCIB0 Notes: 1. Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN060Z-CS81. 2. The bus hold attribute (hold previous I/O state in Flash*Freeze mode) is not supported for pin H7 in AGLN060Z-CS81. 4- 10 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs QN68 Pin A1 Mark 68 1 Notes: 1. This is the bottom view of the package. 2. The die attach paddle of the package is tied to ground (GND). Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN125-CS81. R ev i si o n 2 0 4- 11 Package Pin Assignments QN68 QN68 Pin Number AGLN020 Function Pin Number AGLN020 Function 1 IO60RSB2 36 TDO 2 IO54RSB2 37 TRST 3 IO52RSB2 38 VJTAG 4 IO50RSB2 39 IO17RSB0 5 IO49RSB2 40 IO16RSB0 6 GEC0/IO48RSB2 41 GDA0/IO15RSB0 7 GEA0/IO47RSB2 42 GDC0/IO14RSB0 8 VCC 43 IO13RSB0 9 GND 44 VCCIB0 10 VCCIB2 45 GND 11 IO46RSB2 46 VCC 12 IO45RSB2 47 IO12RSB0 13 IO44RSB2 48 IO11RSB0 14 IO43RSB2 49 IO09RSB0 15 IO42RSB2 50 IO05RSB0 16 IO41RSB2 51 IO00RSB0 17 IO40RSB2 52 IO07RSB0 18 FF/IO39RSB1 53 IO03RSB0 19 IO37RSB1 54 IO18RSB1 20 IO35RSB1 55 IO20RSB1 21 IO33RSB1 56 IO22RSB1 22 IO31RSB1 57 IO24RSB1 23 IO30RSB1 58 IO28RSB1 24 VCC 59 NC 25 GND 60 GND 26 VCCIB1 61 NC 27 IO27RSB1 62 IO32RSB1 28 IO25RSB1 63 IO34RSB1 29 IO23RSB1 64 IO36RSB1 30 IO21RSB1 65 IO61RSB2 31 IO19RSB1 66 IO58RSB2 32 TCK 67 IO56RSB2 33 TDI 68 IO63RSB2 34 TMS 35 VPUMP Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN125Z-CS81. 4- 12 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs VQ100 100 1 Note: This is the top view of the package. Note For Package Manufacturing and Environmental information, visit the Resource Center at http://www.microsemi.com/soc/products/solutions/package/docs.aspx. Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN250-CS81. R ev i si o n 2 0 4- 13 Package Pin Assignments VQ100 VQ100 VQ100 Pin Number AGLN060 Function Pin Number AGLN060 Function Pin Number AGLN060 Function 1 GND 37 VCC 73 GBA2/IO25RSB0 2 GAA2/IO51RSB1 38 GND 74 VMV0 3 IO52RSB1 39 VCCIB1 75 GNDQ 4 GAB2/IO53RSB1 40 IO60RSB1 76 GBA1/IO24RSB0 5 IO95RSB1 41 IO59RSB1 77 GBA0/IO23RSB0 6 GAC2/IO94RSB1 42 IO58RSB1 78 GBB1/IO22RSB0 7 IO93RSB1 43 IO57RSB1 79 GBB0/IO21RSB0 8 IO92RSB1 44 GDC2/IO56RSB1 80 GBC1/IO20RSB0 9 GND 45* GDB2/IO55RSB1 81 GBC0/IO19RSB0 10 GFB1/IO87RSB1 46 GDA2/IO54RSB1 82 IO18RSB0 11 GFB0/IO86RSB1 47 TCK 83 IO17RSB0 12 VCOMPLF 48 TDI 84 IO15RSB0 13 GFA0/IO85RSB1 49 TMS 85 IO13RSB0 14 VCCPLF 50 VMV1 86 IO11RSB0 15 GFA1/IO84RSB1 51 GND 87 VCCIB0 16 GFA2/IO83RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO10RSB0 19 GEC1/IO77RSB1 55 TRST 91 IO09RSB0 20 GEB1/IO75RSB1 56 VJTAG 92 IO08RSB0 21 GEB0/IO74RSB1 57 GDA1/IO49RSB0 93 GAC1/IO07RSB0 22 GEA1/IO73RSB1 58 GDC0/IO46RSB0 94 GAC0/IO06RSB0 23 GEA0/IO72RSB1 59 GDC1/IO45RSB0 95 GAB1/IO05RSB0 24 VMV1 60 GCC2/IO43RSB0 96 GAB0/IO04RSB0 25 GNDQ 61 GCB2/IO42RSB0 97 GAA1/IO03RSB0 26 GEA2/IO71RSB1 62 GCA0/IO40RSB0 98 GAA0/IO02RSB0 27 FF/GEB2/IO70RSB1 63 GCA1/IO39RSB0 99 IO01RSB0 28 GEC2/IO69RSB1 64 GCC0/IO36RSB0 100 IO00RSB0 29 IO68RSB1 65 GCC1/IO35RSB0 30 IO67RSB1 66 VCCIB0 31 IO66RSB1 67 GND 32 IO65RSB1 68 VCC 33 IO64RSB1 69 IO31RSB0 34 IO63RSB1 70 GBC2/IO29RSB0 35 IO62RSB1 71 GBB2/IO27RSB0 36 IO61RSB1 72 IO26RSB0 Note: * Pin numbers F1 and F2 must be connected to ground because a PLL is not supported for AGLN250Z-CS81. 4- 14 R ev i sio n 2 0 IGLOO nano Low Power Flash FPGAs VQ100 VQ100 VQ100 Pin Number AGLN125 Function Pin Number AGLN125 Function Pin Number AGLN125 Function 1 GND 37 VCC 73 GBA2/IO41RSB0 2 GAA2/IO67RSB1 38 GND 74 VMV0 3 IO68RSB1 39 VCCIB1 75 GNDQ 4 GAB2/IO69RSB1 40 IO87RSB1 76 GBA1/IO40RSB0 5 IO132RSB1 41 IO84RSB1 77 GBA0/IO39RSB0 6 GAC2/IO131RSB1 42 IO81RSB1 78 GBB1/IO38RSB0 7 IO130RSB1 43 IO75RSB1 79 GBB0/IO37RSB0 8 IO129RSB1 44 GDC2/IO72RSB1 80 GBC1/IO36RSB0 9 GND 45 GDB2/IO71RSB1 81 GBC0/IO35RSB0 10 GFB1/IO124RSB1 46 GDA2/IO70RSB1 82 IO32RSB0 11 GFB0/IO123RSB1 47 TCK 83 IO28RSB0 12 VCOMPLF 48 TDI 84 IO25RSB0 13 GFA0/IO122RSB1 49 TMS 85 IO22RSB0 14 VCCPLF 50 VMV1 86 IO19RSB0 15 GFA1/IO121RSB1 51 GND 87 VCCIB0 16 GFA2/IO120RSB1 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB1 54 TDO 90 IO15RSB0 19 GEC0/IO111RSB1 55 TRST 91 IO13RSB0 20 GEB1/IO110RSB1 56 VJTAG 92 IO11RSB0 21 GEB0/IO109RSB1 57 GDA1/IO65RSB0 93 IO09RSB0 22 GEA1/IO108RSB1 58 GDC0/IO62RSB0 94 IO07RSB0 23 GEA0/IO107RSB1 59 GDC1/IO61RSB0 95 GAC1/IO05RSB0 24 VMV1 60 GCC2/IO59RSB0 96 GAC0/IO04RSB0 25 GNDQ 61 GCB2/IO58RSB0 97 GAB1/IO03RSB0 26 GEA2/IO106RSB1 62 GCA0/IO56RSB0 98 GAB0/IO02RSB0 27 FF/GEB2/IO105RSB1 63 GCA1/IO55RSB0 99 GAA1/IO01RSB0 28 GEC2/IO104RSB1 64 GCC0/IO52RSB0 100 GAA0/IO00RSB0 29 IO102RSB1 65 GCC1/IO51RSB0 30 IO100RSB1 66 VCCIB0 31 IO99RSB1 67 GND 32 IO97RSB1 68 VCC 33 IO96RSB1 69 IO47RSB0 34 IO95RSB1 70 GBC2/IO45RSB0 35 IO94RSB1 71 GBB2/IO43RSB0 36 IO93RSB1 72 IO42RSB0 R ev i si o n 2 0 4- 15 Package Pin Assignments VQ100 VQ100 VQ100 Pin Number AGLN250 Function Pin Number AGLN250 Function Pin Number AGLN250 Function 1 GND 37 VCC 73 GBA2/IO20RSB1 2 GAA2/IO67RSB3 38 GND 74 VMV1 3 IO66RSB3 39 VCCIB2 75 GNDQ 4 GAB2/IO65RSB3 40 IO39RSB2 76 GBA1/IO19RSB0 5 IO64RSB3 41 IO38RSB2 77 GBA0/IO18RSB0 6 GAC2/IO63RSB3 42 IO37RSB2 78 GBB1/IO17RSB0 7 IO62RSB3 43 GDC2/IO36RSB2 79 GBB0/IO16RSB0 8 IO61RSB3 44 GDB2/IO35RSB2 80 GBC1/IO15RSB0 9 GND 45 GDA2/IO34RSB2 81 GBC0/IO14RSB0 10 GFB1/IO60RSB3 46 GNDQ 82 IO13RSB0 11 GFB0/IO59RSB3 47 TCK 83 IO12RSB0 12 VCOMPLF 48 TDI 84 IO11RSB0 13 GFA0/IO57RSB3 49 TMS 85 IO10RSB0 14 VCCPLF 50 VMV2 86 IO09RSB0 15 GFA1/IO58RSB3 51 GND 87 VCCIB0 16 GFA2/IO56RSB3 52 VPUMP 88 GND 17 VCC 53 NC 89 VCC 18 VCCIB3 54 TDO 90 IO08RSB0 19 GFC2/IO55RSB3 55 TRST 91 IO07RSB0 20 GEC1/IO54RSB3 56 VJTAG 92 IO06RSB0 21 GEC0/IO53RSB3 57 GDA1/IO33RSB1 93 GAC1/IO05RSB0 22 GEA1/IO52RSB3 58 GDC0/IO32RSB1 94 GAC0/IO04RSB0 23 GEA0/IO51RSB3 59 GDC1/IO31RSB1 95 GAB1/IO03RSB0 24 VMV3 60 IO30RSB1 96 GAB0/IO02RSB0 25 GNDQ 61 GCB2/IO29RSB1 97 GAA1/IO01RSB0 26 GEA2/IO50RSB2 62 GCA1/IO27RSB1 98 GAA0/IO00RSB0 27 FF/GEB2/IO49RSB2 63 GCA0/IO28RSB1 99 GNDQ 28 GEC2/IO48RSB2 64 GCC0/IO26RSB1 100 VMV0 29 IO47RSB2 65 GCC1/IO25RSB1 30 IO46RSB2 66 VCCIB1 31 IO45RSB2 67 GND 32 IO44RSB2 68 VCC 33 IO43RSB2 69 IO24RSB1 34 IO42RSB2 70 GBC2/IO23RSB1 35 IO41RSB2 71 GBB2/IO22RSB1 36 IO40RSB2 72 IO21RSB1 4- 16 R ev i sio n 2 0 5 – Datasheet Information List of Changes The following table lists critical changes that were made in each version of the IGLOO nano datasheet. R ev i si o n 2 0 5-1 IGLOO nano Low Power Flash FPGAs Revision Revision 20 (October 2019) Changes Page Modified the table under the "Features and Benefits" section by removing references to AGLN015. 1-I Modified the table under the "I/Os Per Package" section by removing references to AGLN015. 1-II Modified the "IGLOO nano Device Status" section. 1-III Modified the "IGLOO nano Ordering Information" section by removing references to AGLN015. 1-IV Removed the "Devices Not Recommended For New Designs" section. Modified the "Device Marking" section. 1-V Removed the "IGLOO nano Products Available in the Z Feature Grade" section. Modified the "Temperature Grade Offerings" section. 1-V Removed reference of AGLN015 from the Figure 1-2. 1-4 Modified "Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*" table by removing references to AGLN015. 2-7 Modified "Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*" table by removing references to AGLN015. 2-8 Modified "Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*" table by removing references to AGLN015. 2-8 Modified "Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1" table by removing references to AGLN015. 2-8 Modified "Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices" table by removing references to AGLN015. 2-10 Modified "Different Components Contributing to the Static Power Consumption in IGLOO nano Devices" table by removing references to AGLN015. 2-10 Modified "Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices" table by removing references to AGLN015. 2-11 Modified "Different Components Contributing to the Static Power Consumption in IGLOO nano Devices" table by removing references to AGLN015. 2-11 Modified the note under the"DDR Module Specifications" section by removing reference to AGLN015. 2-51 Modified the "Global Tree Timing Characteristics" section by removing references to AGLN015. 2-64 Modified the notes in the"Clock Conditioning Circuits" section by removing reference to AGLN015. 2-70 Modified the "UC81" section. 4-3 Modified the "CS81" section. 4-4 Modified the "QN48" section. 4-9 Modified the "QN68" section. 4-11 Modified the "VQ100" section. 4-13 R ev i si o n 2 0 5-2 Datasheet Information Revision Revision 19 (October 2015) Changes Page Modified the note to include device/package obsoletion information in "Features and Benefits" section (SAR 69724). 1-I Added a note under Security Feature "Y" in "IGLOO nano Ordering Information" section (SAR 70553). 1-IV Modified AGLN250 pin assignment table to match with I/O Attribute Editor tool from Libero in "CS81" Package (SAR 59049). 4-4 Modified the nominal area to 25 for CS81 Package in Table 1 (SAR 71127). 1-II Modified the title of AGLN125Z pin assignment table for "CS81" Package (SAR 71127). 4-4 Revision 18 Modified the "Device Marking" section and updated Figure 1 • Example of Device (November 2013) Marking for Small Form Factor Packages to reflect updates suggested per CN1004 published on 5/10/2010 (SAR 52036). Revision 17 (May 2013) V Deleted details related to Ambient temperature from "Enhanced Commercial I, IV, V, Temperature Range", "IGLOO nano Ordering Information", "Temperature Grade and 2-2 Offerings", and Table 2-2 • Recommended Operating Conditions 1 to remove ambiguities arising due to the same, and modified Note 2 (SAR 47063). Revision 16 The "IGLOO nano Ordering Information" section has been updated to mention "Y" as (December 2012) "Blank" mentioning "Device Does Not Include License to Implement IP Based on the Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43174). The note in Table 2-99 • IGLOO nano CCC/PLL Specification and Table 2-100 • IGLOO nano CCC/PLL Specification referring the reader to SmartGen was revised to refer instead to the online help associated with the core (SAR 42565). Live at Power-Up (LAPU) has been replaced with ’Instant On’. IV 2-70, 2-71 NA Revision 15 The status of the AGLN125 device has been modified from ’Advance’ to ’Production’ in (September 2012) the "IGLOO nano Device Status" section (SAR 41416). III Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip (SoC) throughout the document (SAR 40274). NA Revision 14 The "Security" section was modified to clarify that Microsemi does not support read-back (September 2012) of programmed data. 1-2 Revision 13 (June 2012) Figure Figure 2-34 • FIFO Read and Figure 2-35 • FIFO Write have been added (SAR 34842). 2-82 The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section in the "Pin Descriptions" section: "Within the package, the VMV plane is decoupled from the simultaneous switching noise originating from the output buffer VCCI domain" and replaced with “Within the package, the VMV plane biases the input stage of the I/Os in the I/O banks” (SAR 38319). The datasheet mentions that "VMV pins must be connected to the corresponding VCCI pins" for an ESD enhancement. 3-1 The "In-System Programming (ISP) and Security" section and "Security" section were revised to clarify that although no existing security measures can give an absolute guarantee, Microsemi FPGAs implement the best security available in the industry (SAR 34663). I, 1-2 Notes indicating that AGLN015 is not recommended for new designs have been added (SAR 35759). III, IV Revision 12 (March 2012) Notes indicating that nano-Z devices are not recommended for new designs have been added. The "Devices Not Recommended For New Designs" section is new (SAR 36759). 5- 3 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Revision Revision 12 (continued) Changes Page The Y security option and Licensed DPA Logo were added to the "IGLOO nano Ordering Information" section. The trademarked Licensed DPA Logo identifies that a product is covered by a DPA counter-measures license from Cryptography Research (SAR 34722). IV The following sentence was removed from the "Advanced Architecture" section: "In addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V) programming of IGLOO nano devices via an IEEE 1532 JTAG interface" (SAR 34683). 1-3 The "Specifying I/O States During Programming" section is new (SAR 34694). 1-9 The reference to guidelines for global spines and VersaTile rows, given in the "Global Clock Contribution—PCLOCK" section, was corrected to the "Spine Architecture" section of the Global Resources chapter in the IGLOO nano FPGA Fabric User's Guide (SAR 34732). 2-12 Figure 2-4 has been modified for DIN waveform; the Rise and Fall time label has been changed to tDIN (37106). 2-16 The AC Loading figures in the "Single-Ended I/O Characteristics" section were updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section (SAR 34885). 2-26, 2-20 The notes regarding drive strength in the "Summary of I/O Timing Characteristics – Default I/O Software Settings" section, "3.3 V LVCMOS Wide Range" section and "1.2 V LVCMOS Wide Range" section tables were revised for clarification. They now state that the minimum drive strength for the default software configuration when run in wide range is ±100 µA. The drive strength displayed in software is supported in normal range only. For a detailed I/V curve, refer to the IBIS models (SAR 34765). 2-20, 2-29, 2-40 Added values for minimum pulse width and removed the FRMAX row from Table 2-88 2-64 to through Table 2-98 in the "Global Tree Timing Characteristics" section. Use the software 2-69 to determine the FRMAX for the device you are using (SAR 36953). Table 2-99 • IGLOO nano CCC/PLL Specification and Table 2-100 • IGLOO nano CCC/PLL Specification were updated. A note was added indicating that when the CCC/PLL core is generated by Mircosemi core generator software, not all delay values of the specified delay increments are available (SAR 34817). 2-70 and 2-71 The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics" tables, Figure 2-36 • FIFO Reset, and the FIFO "Timing Characteristics" tables were revised to ensure consistency with the software names (SAR 35754). 2-74, 2-77, 2-85 Reference was made to a new application note, Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail (SAR 34865). Revision 11 (Jul 2010) July 2010 The "Pin Descriptions" chapter has been added (SAR 34770). 3-1 Package names used in the "Package Pin Assignments" section were revised to match standards given in Package Mechanical Drawings (SAR 34770). 4-1 The status of the AGLN060 device has changed from Advance to Production. III The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-15 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices for 1.5 V core supply voltage (SAR 26404). 2-10 The values for PAC1, PAC2, PAC3, and PAC4 were updated in Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices for 1.2 V core supply voltage (SAR 26404). 2-11 The versioning system for datasheets has been changed. Datasheets are assigned a revision number that increments each time the datasheet is revised. The "IGLOO nano Device Status" table on page III indicates the status for each device in the device family. N/A R ev i si o n 2 0 5-4 Datasheet Information Revision Revision 10 (Apr 2010) 5- 5 Changes Page References to differential inputs were removed from the datasheet, since IGLOO nano devices do not support differential inputs (SAR 21449). N/A A parenthetical note, "hold previous I/O state in Flash*Freeze mode," was added to each occurrence of bus hold in the datasheet (SAR 24079). N/A The "In-System Programming (ISP) and Security" section was revised to add 1.2 V programming. I The note connected with the "IGLOO nano Ordering Information" table was revised to clarify features not available for Z feature grade devices. IV The "IGLOO nano Device Status" table is new. III The definition of C in the "Temperature Grade Offerings" table was changed to "extended commercial temperature range". V 1.2 V wide range was added to the list of voltage ranges in the "I/Os with Advanced I/O Standards" section. 1-8 A note was added to Table 2-2 • Recommended Operating Conditions 1 regarding switching from 1.2 V to 1.5 V core voltage for in-system programming. The VJTAG voltage was changed from "1.425 to 3.6" to "1.4 to 3.6" (SAR 24052). The note regarding voltage for programming V2 and V5 devices was revised (SAR 25213). The maximum value for VPUMP programming voltage (operation mode) was changed from 3.45 V to 3.6 V (SAR 25220). 2-2 Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were updated. Table 2-8 • Power Supply State per Mode is new. 2-6, 2-7 The tables in the "Quiescent Supply Current" section were updated (SAR 24882 and SAR 24112). 2-7 VJTAG was removed from Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode* (SARs 24112, 24882, and 79503). 2-8 The note stating what was included in IDD was removed from Table 2-11 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode. The note, "per VCCI or VJTAG bank" was removed from Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1. The note giving IDD was changed to "IDD = NBANKS * ICCI + ICCA." 2-8 The values in Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1 were updated. Wide range support information was added. 2-9 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Revision Revision 10 (continued) Changes Page The following tables were updated with current available information. The equivalent 2-19 through software default drive strength option was added. 2-40 Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings Table 2-28 • I/O Output Buffer Maximum Resistances 1 Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances Table 2-30 • I/O Short Currents IOSH/IOSL Timing tables in the "Single-Ended I/O Characteristics" section, including new tables for 3.3 V and 1.2 V LVCMOS wide range. Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range Table 2-63 • Minimum and Maximum DC Input and Output Levels Table 2-67 • Minimum and Maximum DC Input and Output Levels (new) The formulas in the notes to Table 2-29 • I/O Weak Pull-Up/Pull-Down Resistances were revised (SAR 21348). 2-24 The text introducing Table 2-31 • Duration of Short Circuit Event before Failure was revised to state six months at 100° instead of three months at 110° for reliability concerns. The row for 110° was removed from the table. 2-25 The following sentence was deleted from the "2.5 V LVCMOS" section (SAR 24916): "It uses a 5-V tolerant input buffer and push-pull output buffer." 2-32 The FDDRIMAX and FDDOMAX values were added to tables in the "DDR Module Specifications" section (SAR 23919). A note was added stating that DDR is not supported for AGLN010, AGLN015, and AGLN020. 2-51 Tables in the "Global Tree Timing Characteristics" section were updated with new information available. 2-64 Table 2-99 • IGLOO nano CCC/PLL Specification and Table 2-100 • IGLOO nano CCC/PLL Specification were revised (SAR 79390). 2-70, 2-71 Tables in the SRAM "Timing Characteristics" section and FIFO "Timing Characteristics" section were updated with new information available. 2-77, 2-85 Table 3-3 • TRST and TCK Pull-Down Recommendations is new. 3-4 A note was added to the "CS81" pin tables for AGLN060, AGLN060Z, AGLN125, 4-6, AGLN125Z, AGLN250, and AGLN250Z indicating that pins F1 and F2 must be grounded through (SAR 25007). 4-13 A note was added to the "CS81" and "VQ100" pin tables for AGLN060 and AGLN060Z stating that bus hold is not available for pin H7 or pin 45 (SAR 24079). 4-6, 4-14 The AGLN250 function for pin C8 in the "CS81" table was revised (SAR 22134). 4-8 R ev i si o n 2 0 5-6 Datasheet Information Revision / Version Changes Revision 9 (Mar2010) All product tables and pin tables were updated to show clearly that AGLN030 is Product Brief Advance available only in the Z feature grade at this time. The nano-Z feature grade devices are designated with a Z at the end of the part number. v0.9 Page N/A Packaging Advance v0.8 Revision 8 (Jan 2009) The "Reprogrammable Flash Technology" section was revised to add "250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System Performance". I Product Brief Advance The note for AGLN030 in the "IGLOO nano Devices" table and "I/Os Per v0.8 Package" table was revised to remove the statement regarding package compatibility with lower density nano devices. II, II The "I/Os with Advanced I/O Standards" section was revised to add definitions for hot-swap and cold-sparing. 1-8 Packaging Advance v0.7 The "UC81", "CS81", "QN48", and "QN68" pin tables for AGLN030 are new. The "CS81"pin table for AGLN060 is new. 4-3, 4-4, 4-9, 4-11 4-6 The "UC81" and "VQ100" pin tables for AGLN060Z are new. 4-3, 4-13 The "UC81" and "VQ100" pin tables for AGLN125Z are new. 4-3, 4-13 The "UC81" and "VQ100" pin tables for AGLN250Z is new. 4-3, "VQ100" The –F speed grade is no longer offered for IGLOO nano devices and was Product Brief Advance removed from the datasheet. v0.7 Revision 7 (Apr 2009) N/A DC and Switching Characteristics Advance v0.3 Revision 6 (Mar 2009) The "VQ100" pin table for AGLN030 is new. "VQ100" Packaging Advance v0.6 Revision 5 (Feb 2009) The "100-Pin QFN" section was removed. N/A The QN100 package was removed for all devices. N/A Packaging Advance v0.5 Revision 4 (Feb 2009) Product Brief Advance "IGLOO nano Devices" table was updated to change the maximum user I/Os for v0.6 AGLN030 from 81 to 77. The "Device Marking" section is new. Revision 3 (Feb 2009) The following table note was removed from "IGLOO nano Devices" table: "Six Product Brief Advance chip (main) and three quadrant global networks are available for AGLN060 and above." v0.5 The CS81 package was added for AGLN250 in the GLOO nano Products Available in the Z Feature Grade table. Packaging Advance v0.4 The "UC81" and "CS81" pin tables for AGLN020 are new. The "CS81" pin table for AGLN250 is new. 5- 7 R ev isio n 2 0 II V II N/A 4-3, 4-5 4-8 IGLOO nano Low Power Flash FPGAs Revision / Version Changes Revision 2 (Dec 2008) Page The second table note in "IGLOO nano Devices" table was revised to state, Product Brief Advance "AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs. AGLN030 and smaller devices do not support this feature." v0.4 II The I/Os per package for CS81 were revised to 60 for AGLN060, AGLN125, and AGLN250 in the "I/Os Per Package"table. II Packaging Advance v0.3 The "UC36" pin table is new. 4-2 The "Advanced I/Os" section was updated to include wide power supply voltage support for 1.14 V to 1.575 V. Product Brief Advance v0.3 Revision 1 (Nov 2008) I The AGLN030 device was added to product tables and replaces AGL030 entries that were formerly in the tables. N/A The "I/Os Per Package"table was updated for the CS81 package to change the number of I/Os for AGLN060, AGLN125, and AGLN250 from 66 to 64. II The "Wide Range I/O Support" section is new. 1-8 The table notes and references were revised in Table 2-2 • Recommended Operating Conditions 1. VMV was included with VCCI and a table note was added stating, "VMV pins must be connected to the corresponding VCCI pins. See Pin Descriptions for further information." Please review carefully. 2-2 VJTAG was added to the list in the table note for Table 2-9 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Flash*Freeze Mode*. Values were added for AGLN010, AGLN015, and AGLN030 for 1.5 V. 2-7 VCCI was removed from the list in the table note for Table 2-10 • Quiescent Supply Current (IDD) Characteristics, IGLOO nano Sleep Mode*. 2-8 Values for ICCA current were updated for AGLN010, AGLN015, and AGLN030 in Table 2-12 • Quiescent Supply Current (IDD), No IGLOO nano Flash*Freeze Mode1. 2-8 Values for PAC1 and PAC2 were added to Table 2-15 • Different Components 2-10, 2-11 Contributing to Dynamic Power Consumption in IGLOO nano Devices and Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO nano Devices. Table notes regarding wide range support were added to Table 2-21 • Summary of Maximum and Minimum DC Input and Output Levels. 2-19 1.2 V LVCMOS wide range values were added to Table 2-22 • Summary of 2-19, 2-20 Maximum and Minimum DC Input Levels and Table 2-23 • Summary of AC Measuring Points. The following table note was added to Table 2-25 • Summary of I/O Timing Characteristics—Software Default Settings and Table 2-26 • Summary of I/O Timing Characteristics—Software Default Settings: "All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range, as specified in the JESD8-B specification." 2-21 3.3 V LVCMOS Wide Range and 1.2 V Wide Range were added to Table 2-28 • 2-23, 2-24 I/O Output Buffer Maximum Resistances 1 andTable 2-30 • I/O Short Currents IOSH/IOSL. R ev i si o n 2 0 5-8 Datasheet Information Revision / Version Changes Page Revision 1 (cont’d) The "QN48" pin diagram was revised. 4-10 Packaging Advance v0.2 Note 2 for the "QN48", "QN68", and "100-Pin QFN" pin diagrams was changed to 4-10, 4-11 "The die attach paddle of the package is tied to ground (GND)." The "VQ100" pin diagram was revised to move the pin IDs to the upper left corner instead of the upper right corner. 4-13 The following tables and sections were updated to add the UC81 and CS81 Product Brief Advance packages for AGL030: v0.2 "IGLOO nano Devices" "I/Os Per Package" IGLOO nano Products Available in the Z Feature Grade "Temperature Grade Offerings" 1-V Revision 0 (Oct 2008) The "I/Os Per Package" table was updated to add the following information to table note 4: "For nano devices, the VQ100 package is offered in both leaded and RoHS-compliant versions. All other packages are RoHS-compliant only." II The IGLOO nano Products Available in the Z Feature Grade section was updated to remove QN100 for AGLN250. N/A The device architecture figures, Figure 1-3 • IGLOO Device Architecture Overview 1-4 with Two I/O Banks (AGLN060, AGLN125) through Figure 1-4 • IGLOO Device through Architecture Overview with Four I/O Banks (AGLN250), were revised. Figure 1-1 • 1-5 IGLOO Device Architecture Overview with Two I/O Banks and No RAM (AGLN010 and AGLN030) is new. 5- 9 The "PLL and CCC" section was revised to include information about CCC-GLs in AGLN020 and smaller devices. 1-7 The "I/Os with Advanced I/O Standards" section was revised to add information about IGLOO nano devices supporting double-data-rate applications. 1-8 R ev isio n 2 0 IGLOO nano Low Power Flash FPGAs Datasheet Categories Categories In order to provide the latest information to designers, some datasheet parameters are published before data has been fully characterized from silicon devices. The data provided for a given device, as highlighted in the "IGLOO nano Device Status" table on page III, is designated as either "Product Brief," "Advance," "Preliminary," or "Production." The definitions of these categories are as follows: Product Brief The product brief is a summarized version of a datasheet (advance or production) and contains general product information. This document gives an overview of specific device and family information. Advance This version contains initial estimated information based on simulation, other products, devices, or speed grades. This information can be used as estimates, but not for production. This label only applies to the DC and Switching Characteristics chapter of the datasheet and will only be used when the data has not been fully characterized. Preliminary The datasheet contains information based on simulation and/or initial characterization. The information is believed to be correct, but changes are possible. Unmarked (production) This version contains information that is considered to be final. Export Administration Regulations (EAR) The products described in this document are subject to the Export Administration Regulations (EAR). They could require an approved export license prior to export from the United States. An export includes release of product or disclosure of technology to a foreign national inside or outside the United States. Safety Critical, Life Support, and High-Reliability Applications Policy The Microsemi products described in this advance status document may not have completed Microsemi’s qualification process. Microsemi may amend or enhance products during the product introduction and qualification process, resulting in changes in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Microsemi product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-support, and other high-reliability applications. Consult Microsemi’s Terms and Conditions for specific liability exclusions relating to life-support applications. A reliability report covering all of the Microsemi SoC Products Group’s products is at http://www.microsemi.com/socdocuments/ORT_Report.pdf. Microsemi also offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your local Microsemi sales office for additional reliability information. R ev i si o n 2 0 5- 10 Microsemi Corporate Headquarters One Enterprise, Aliso Viejo, CA 92656 USA Within the USA: +1 (800) 713-4113 Outside the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 Fax: +1 (949) 215-4996 E-mail: sales.support@microsemi.com www.microsemi.com ©2019 Microsemi, a wholly owned subsidiary of Microchip Technology Inc. All rights reserved. Microsemi and the Microsemi logo are registered trademarks of Microsemi Corporation. All other trademarks and service marks are the property of their respective owners. Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or the suitability of its products and services for any particular purpose, nor does Microsemi assume any liability whatsoever arising out of the application or use of any product or circuit. The products sold hereunder and any other products sold by Microsemi have been subject to limited testing and should not be used in conjunction with mission-critical equipment or applications. Any performance specifications are believed to be reliable but are not verified, and Buyer must conduct and complete all performance and other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s responsibility to independently determine suitability of any products and to test and verify the same. The information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this document is proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this document or to any products and services at any time without notice. About Microsemi Microsemi, a wholly owned subsidiary of Microchip Technology Inc. (Nasdaq: MCHP), offers a comprehensive portfolio of semiconductor and system solutions for aerospace & defense, communications, data center and industrial markets. Products include high-performance and radiationhardened analog mixed-signal integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and synchronization devices and precise time solutions, setting the world's standard for time; voice processing devices; RF solutions; discrete components; enterprise storage and communication solutions, security technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and services. Learn more at www.microsemi.com. 51700110-19/10.19