DS3102GN+

19-4617; Rev 5; 8/10 DS3102 Stratum 2/3E/3 Timing Card IC with Synchronous Ethernet Support General Description The DS3102 is a low-cost, feature-rich timing IC for telecom timing cards. With 8 input clocks, the device directly accepts both line timing from a large number of line cards and external timing from external DS1/E1 BITS transceivers. The DS3102 continually monitors all input clocks and performs automatic hitless reference switching if the primary reference fails. The T0 DPLL complies with the Stratum 2, 3E, 3, 4E and 4 requirements of GR-1244, GR-253, G.812 Types I – IV, G.813 and G.8262. The highly programmable DS3102 support numerous input and output frequencies including rates required for SONET/SDH, Synchronous Ethernet (1G, 10G, and 100Mbps), wireless base stations, and CMTS systems. PLL bandwidths from 0.5mHz to 400Hz are supported, and a wide variety of PLL characteristics and device features can be configured to meet the needs of many different applications. Two DS3102 devices can Features  Synchronization for Stratum 2, 3E, 3, 4E and 4 plus SMC, SEC and EEC        8 Input Clocks      be configured in a master/slave arrangement for timing card equipment protection. The DS3102 register set is backward compatible with Semtech’s ACS8522 timing card IC. The DS3102 has a different package and pin arrangement than the ACS8522.  SONET/SDH Equipment Clocks (SECs) Synchronous Ethernet Equipment Clocks (EECs) Timing Card IC in WAN Equipment Including MSPPs, Ethernet Switches, Routers, DSLAMs, and Wireless Base Stations  Ordering Information PART DS3102GN DS3102GN+ TEMP RANGE PIN-PACKAGE -40C to +85C -40C to +85C 81 CSBGA (10mm)2 81 CSBGA (10mm)2 +Denotes a lead(Pb)-free/RoHS-compliant package.  Three CMOS/TTL Outputs (≤ 125MHz) Two LVDS/LVPECL Outputs (≤ 312.50MHz) Two Dual CMOS/TTL and LVDS/LVPECL Outputs Five CMOS Outputs Have Additional Output Pins That Can Be Powered at 2.5V or 3.3V Numerous Output Clock Frequencies Supported: SONET/SDH: 6.48, N x 19.44, N x 51.84MHz Ethernet xMII: 2.5, 25, 125, 156.25, 312.5MHz PDH: N x DS1, N x E1, N x DS2, DS3, E3 Other: 10, 10.24, 13, 30.72MHz Frame Sync: 2kHz, 8kHz Custom Clock Rates: Any Multiple of 2kHz Up to 77.76MHz, Any Multiple of 8kHz Up to 311.04MHz, Any Multiple of 10kHz Up to 388.79MHz General  SPI is a trademark of Motorola, Inc. Four CMOS/TTL Inputs (≤ 125MHz) Four LVDS/LVPECL/CMOS/TTL Inputs (≤ 156.25MHz) Three Optional Frame-Sync Inputs (CMOS/TTL) Continuous Input Clock Quality Monitoring Numerous Input Clock Frequencies Supported: SONET/SDH: 6.48, N x 19.44, N x 51.84MHz Ethernet xMII: 2.5, 25, 125, 156.25MHz PDH: N x DS1, N x E1, N x DS2, DS3, E3 Frame Sync: 2kHz, 4kHz, 8kHz Custom: Any Multiple of 2kHz Up to 131.072MHz, Any Multiple of 8kHz Up to 155.52MHz 7 Output Clocks     Applications Meets Requirements of GR-1244 Stratum 2 – 4, GR-253, G.812 Types I – IV, G.813, and G.8262 Stratum 2, 3E or 3 Holdover Accuracy with Suitable External Oscillator Programmable Bandwidth: 0.5mHz to 400Hz Hitless Reference Switching on Loss of Input Automatic or Manual Phase Build-Out Frequency Conversion Among SONET/SDH, PDH, Ethernet, Wireless, and CMTS Rates    Internal Compensation for Master Clock Oscillator SPI™ Processor Interface 1.8V Operation with 3.3V I/O (5V Tolerant) Industrial Temperature Range Maxim Integrated Products 1 Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. ____________________________________________________________________________________________ DS3102 Table of Contents 1. STANDARDS COMPLIANCE ..........................................................................................................6 2. APPLICATION EXAMPLE ...............................................................................................................7 3. BLOCK DIAGRAM ...........................................................................................................................8 4. DETAILED DESCRIPTION ..............................................................................................................9 5. DETAILED FEATURES .................................................................................................................11 5.1 5.2 5.3 5.4 5.5 5.6 5.7 INPUT CLOCK FEATURES ...............................................................................................................11 T0 DPLL FEATURES ......................................................................................................................11 T4 DPLL FEATURES ......................................................................................................................11 OUTPUT APLL FEATURES .............................................................................................................12 OUTPUT CLOCK FEATURES ............................................................................................................12 REDUNDANCY FEATURES ..............................................................................................................12 GENERAL FEATURES .....................................................................................................................12 6. PIN DESCRIPTIONS ......................................................................................................................13 7. FUNCTIONAL DESCRIPTION .......................................................................................................17 7.1 7.2 7.3 7.4 OVERVIEW ....................................................................................................................................17 DEVICE IDENTIFICATION AND PROTECTION .....................................................................................18 LOCAL OSCILLATOR AND MASTER CLOCK CONFIGURATION.............................................................18 INPUT CLOCK CONFIGURATION ......................................................................................................19 7.4.1 7.4.2 7.5 INPUT CLOCK MONITORING ............................................................................................................21 7.5.1 7.5.2 7.5.3 7.6 Priority Configuration............................................................................................................................ 23 Automatic Selection Algorithm ............................................................................................................. 23 Forced Selection .................................................................................................................................. 24 Ultra-Fast Reference Switching ........................................................................................................... 24 External Reference Switching Mode.................................................................................................... 24 Output Clock Phase Continuity During Reference Switching .............................................................. 25 Frequency Monitoring Hysteresis Required by Telcordia GR-1244-CORE......................................... 25 DPLL ARCHITECTURE AND CONFIGURATION ..................................................................................26 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.7.8 7.7.9 7.7.10 7.7.11 7.7.12 7.7.13 7.8 Frequency Monitoring .......................................................................................................................... 21 Activity Monitoring ................................................................................................................................ 21 Selected Reference Activity Monitoring ............................................................................................... 22 INPUT CLOCK PRIORITY, SELECTION, AND SWITCHING ....................................................................23 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.6.7 7.7 Signal Format Configuration ................................................................................................................ 19 Frequency Configuration...................................................................................................................... 20 T0 DPLL State Machine ....................................................................................................................... 27 T4 DPLL State Machine ....................................................................................................................... 30 Bandwidth ............................................................................................................................................ 32 Damping Factor.................................................................................................................................... 32 Phase Detectors................................................................................................................................... 32 Loss-of-Lock Detection ........................................................................................................................ 33 Phase Build-Out ................................................................................................................................... 34 Input to Output (Manual) Phase Adjustment........................................................................................ 35 Phase Recalibration ............................................................................................................................. 35 Frequency and Phase Measurement................................................................................................... 35 Input Jitter and Wander Tolerance....................................................................................................... 37 Jitter and Wander Transfer .................................................................................................................. 37 Output Jitter and Wander ..................................................................................................................... 38 OUTPUT CLOCK CONFIGURATION...................................................................................................38 7.8.1 7.8.2 Signal Format Configuration ................................................................................................................ 39 Frequency Configuration...................................................................................................................... 39 19-4617; Rev 5; 8/10 2 of 142 ____________________________________________________________________________________________ DS3102 7.9 EQUIPMENT REDUNDANCY CONFIGURATION...................................................................................46 7.9.1 7.9.2 7.9.3 7.9.4 7.10 7.11 7.12 7.13 8. Master-Slave Output Clock-Phase Alignment ..................................................................................... 46 Master-Slave Frame and Multiframe Alignment with the External Frame-Sync Signals ..................... 47 SYNCn Pins ......................................................................................................................................... 49 Other Configuration Options ................................................................................................................ 50 MICROPROCESSOR INTERFACE ..................................................................................................50 RESET LOGIC .............................................................................................................................53 POWER-SUPPLY CONSIDERATIONS .............................................................................................53 INITIALIZATION............................................................................................................................53 REGISTER DESCRIPTIONS .........................................................................................................54 8.1 8.2 8.3 8.4 9. STATUS BITS .................................................................................................................................54 CONFIGURATION FIELDS ................................................................................................................54 MULTIREGISTER FIELDS .................................................................................................................54 REGISTER DEFINITIONS .................................................................................................................55 JTAG TEST ACCESS PORT AND BOUNDARY SCAN .............................................................124 9.1 9.2 9.3 9.4 10. JTAG DESCRIPTION ....................................................................................................................124 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION .............................................................125 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS ......................................................................127 JTAG TEST REGISTERS ..............................................................................................................128 ELECTRICAL CHARACTERISTICS............................................................................................129 10.1 10.2 10.3 10.4 10.5 10.6 DC CHARACTERISTICS .............................................................................................................129 INPUT CLOCK TIMING ...............................................................................................................133 OUTPUT CLOCK TIMING ............................................................................................................133 SPI INTERFACE TIMING ............................................................................................................134 JTAG INTERFACE TIMING .........................................................................................................136 RESET PIN TIMING ...................................................................................................................137 11. PIN ASSIGNMENTS ....................................................................................................................138 12. PACKAGE INFORMATION .........................................................................................................140 13. ACRONYMS AND ABBREVIATIONS .........................................................................................141 14. DATA SHEET REVISION HISTORY............................................................................................142 19-4617; Rev 5; 8/10 3 of 142 ____________________________________________________________________________________________ DS3102 List of Figures Figure 2-1. Typical Application Example ..................................................................................................................... 7 Figure 3-1. Block Diagram ........................................................................................................................................... 8 Figure 7-1. DPLL Block Diagram ............................................................................................................................... 26 Figure 7-2. T0 DPLL State Transition Diagram ......................................................................................................... 28 Figure 7-3. T4 DPLL State Transition Diagram ......................................................................................................... 31 Figure 7-4. FSYNC 8kHz Options.............................................................................................................................. 45 Figure 7-5. SPI Clock Phase Options ........................................................................................................................ 51 Figure 7-6. SPI Bus Transactions.............................................................................................................................. 52 Figure 9-1. JTAG Block Diagram............................................................................................................................. 124 Figure 9-2. JTAG TAP Controller State Machine .................................................................................................... 126 Figure 10-1. Recommended Termination for LVDS Pins ........................................................................................ 131 Figure 10-2. Recommended Termination for LVPECL Signals on LVDS Input Pins .............................................. 131 Figure 10-3. Recommended Termination for LVPECL-Compatible Output Pins .................................................... 132 Figure 10-4. SPI Interface Timing Diagram ............................................................................................................. 135 Figure 10-5. JTAG Timing Diagram......................................................................................................................... 136 Figure 10-6. Reset Pin Timing Diagram .................................................................................................................. 137 Figure 11-1. Pin Assignment Diagram..................................................................................................................... 139 19-4617; Rev 5; 8/10 4 of 142 ____________________________________________________________________________________________ DS3102 List of Tables Table 1-1. Applicable Telecom Standards................................................................................................................... 6 Table 6-1. Input Clock Pin Descriptions .................................................................................................................... 13 Table 6-2. Output Clock Pin Descriptions.................................................................................................................. 14 Table 6-3. Global Pin Descriptions ............................................................................................................................ 15 Table 6-4. SPI Bus Mode Pin Descriptions ............................................................................................................... 15 Table 6-5. JTAG Interface Pin Descriptions .............................................................................................................. 16 Table 6-6. Power-Supply Pin Descriptions ................................................................................................................ 16 Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements..................................................................................... 18 Table 7-2. Input Clock Capabilities ............................................................................................................................ 19 Table 7-3. Locking Frequency Modes ....................................................................................................................... 20 Table 7-4. Default Input Clock Priorities .................................................................................................................... 23 Table 7-5. Damping Factors and Peak Jitter/Wander Gain....................................................................................... 32 Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode .......................................................... 37 Table 7-7. Output Clock Capabilities ......................................................................................................................... 38 Table 7-8. Digital1 Frequencies................................................................................................................................. 40 Table 7-9. Digital2 Frequencies................................................................................................................................. 41 Table 7-10. APLL Frequency to Output Frequencies (T0 APLL and T4 APLL) ........................................................ 41 Table 7-11. T0 APLL Frequency Configuration ......................................................................................................... 41 Table 7-12. T0 APLL2 Frequency Configuration ....................................................................................................... 41 Table 7-13. T4 APLL Frequency Configuration ......................................................................................................... 42 Table 7-14. OC1 to OC7 Output Frequency Selection .............................................................................................. 42 Table 7-15. Standard Frequencies for Programmable Outputs ................................................................................ 43 Table 7-16. Equipment Redundancy Methodology ................................................................................................... 46 Table 7-17. External Frame-Sync Mode and Source ................................................................................................ 48 Table 7-18. External Frame-Sync Source ................................................................................................................. 49 Table 8-1. Register Map ............................................................................................................................................ 55 Table 9-1. JTAG Instruction Codes ......................................................................................................................... 127 Table 9-2. JTAG ID Code ........................................................................................................................................ 128 Table 10-1. Recommended DC Operating Conditions ............................................................................................ 129 Table 10-2. DC Characteristics................................................................................................................................ 129 Table 10-3. CMOS/TTL Pins ................................................................................................................................... 130 Table 10-4. LVDS/LVPECL Input Pins .................................................................................................................... 130 Table 10-5. LVDS Output Pins ................................................................................................................................ 130 Table 10-6. LVPECL Level-Compatible Output Pins............................................................................................... 131 Table 10-7. Input Clock Timing................................................................................................................................ 133 Table 10-8. Input Clock to Output Clock Delay ....................................................................................................... 133 Table 10-9. Output Clock Phase Alignment, Frame-Sync Alignment Mode............................................................ 133 Table 10-10. SPI Interface Timing ........................................................................................................................... 134 Table 10-11. JTAG Interface Timing........................................................................................................................ 136 Table 10-12. Reset Pin Timing ................................................................................................................................ 137 Table 11-1. Pin Assignments Sorted by Signal Name............................................................................................. 138 Table 12-1. CSBGA Package Thermal Properties, Natural Convection ................................................................. 140 19-4617; Rev 5; 8/10 5 of 142 ____________________________________________________________________________________________ DS3102 1. Standards Compliance Table 1-1. Applicable Telecom Standards SPECIFICATION ANSI T1.101 TIA/EIA-644-A ETSI EN 300 417-6-1 EN 300 462-3-1 EN 300 462-5-1 IEEE IEEE 1149.1 ITU-T G.781 G.783 G.812 G.813 G.823 G.824 G.825 G.8261 G.8262 TELCORDIA GR-253-CORE GR-378-CORE GR-1244-CORE 19-4617; Rev 5; 8/10 SPECIFICATION TITLE Synchronization Interface Standard, 1999 Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits, 2001 Transmission and Multiplexing (TM); Generic requirements of transport functionality of equipment; Part 6-1: Synchronization layer functions, v1.1.3 (1999-05) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 3-1: The control of jitter and wander within synchronization networks, v1.1.1 (1998-05) Transmission and Multiplexing (TM); Generic requirements for synchronization networks; Part 5-1: Timing characteristics of slave clocks suitable for operation in Synchronous Digital Hierarchy (SDH) Equipment, v1.1.2 (1998-05) Standard Test Access Port and Boundary-Scan Architecture, 1990 Synchronization layer functions (06/1999) Characteristics of synchronous digital hierarchy (SDH) equipment functional blocks (10/2000 plus Amendment 1 06/2002 and Corrigendum 2 03/2003) Timing requirements of slave clocks suitable for use as node clocks in synchronization networks (06/1998) Timing characteristics of SDH equipment slave clocks (SEC) (03/2003) The control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy (03/2000) The control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy (03/2000) The control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (SDH) (03/2000) Timing and synchronization aspects in packet networks (05/2006, prepublished) Timing characteristics of synchronous Ethernet equipment slave clock (EEC) (08/2007) SONET Transport Systems: Common Generic Criteria, Issue 3, September 2000 Generic Requirements for Timing Signal Generators, Issue 2, February 1999 Clocks for the Synchronized Network: Common Generic Criteria, Issue 2, December 2000 6 of 142 ____________________________________________________________________________________________ DS3102 2. Application Example Figure 2-1. Typical Application Example activty and frequency monitoring, select highest priority valid input Backplane create derived DS1 or E1/2048 kHz clock from 19.44 MHz frequency locked to line clock Timing Card (1 of 2) micro controller N DS1, E1 or 2048 kHz DS3102 BITS Tx Monitor, Divider, Selector T4 DPLL BITS Tx TCXO or OCXO N to BITS/SSU T4 APLL T0 APLL T0 DPLL typically 19.44 MHz point-to-point or multidrop buses Monitor, Divider, Selector BITS Rx from BITS/SSU BITS Rx DS1, E1 or 2048 kHz N Timing Card (2 of 2) Identical to Timing Card 1 N Line Card (1 of N) clock/data recovery, equalizer, framer, extract SSMs Stratum 2, 3E or 3: jitter/wander filtering, hitless switching, phase adjust, holdover divide line clock down to backplane rate, send to timing cards Line Card (N of N) DPLL select best system clock, hitless switching, basic holdover 19-4617; Rev 5; 8/10 APLL to port SERDES clock multiplication, jitter cleanup 7 of 142 ____________________________________________________________________________________________ DS3102 3. Block Diagram Figure 3-1. Block Diagram IC1 POS/NEG IC2 POS/NEG IC3 IC4 IC5 POS/NEG IC6 POS/NEG IC8 IC9 (Frequency Conversion) PLL Bypass T0 DPLL (Filtering, Holdover, Hitless Switching, Frequency Conversion) WDT GPIO[4:1] SRFAIL LOCK SRCSW SONSDH CPOL CPHA CS SCLK SDI SDO INTREQ/SRFAIL RST (SPI Serial) and HW Control and Status Pins TEST (Muxes, 7 DFS Blocks, 3 APLLs, Output Dividers) Master Clock Generator Microprocessor Port JTAG Output Clock Synthesizer and Selector WDT Input Clock Selector, Divider and Monitor SYNC1 SYNC2 SYNC3 JTRST JTMS JTCLK JTDI JTDO OC1 OC2 OC3 OC4 OC5 OC1B OC2B OC3B OC4B OC5B OC4 POS/NEG OC5 POS/NEG OC6 POS/NEG OC7 POS/NEG T4 DPLL FSYNC MFSYNC DS3102 REFCLK Local Oscillator See Figure 7-1 for a detailed view of the T0 and T4 DPLLs and the Output Clock Synthesizer and Selector block. 19-4617; Rev 5; 8/10 8 of 142 ____________________________________________________________________________________________ DS3102 4. Detailed Description Figure 3-1 illustrates the blocks described in this section and how they relate to one another. Section 5 provides a detailed feature list. The DS3102 is a highly integrated timing card IC for systems with SONET/SDH or Synchronous Ethernet ports. At the core of this device are two digital phase-locked loops (DPLLs) labeled T0 and T4 1. DPLL technology makes use of digital-signal processing (DSP) and digital-frequency synthesis (DFS) techniques to implement PLLs that are precise, flexible, and have consistent performance over voltage, temperature, and manufacturing process variations. The DS3102’s DPLLs are digitally configurable for input and output frequencies, loop bandwidth, damping factor, pull-in/hold-in range, and a variety of other factors. Both DPLLs can directly lock to many common telecom frequencies and also can lock at 8kHz to any multiple of 8kHz up to 156.25MHz. The DPLLs can also tolerate and filter significant amounts of jitter and wander. The T0 DPLL is responsible for generating the system clocks used to time the outgoing traffic interfaces of the system (SONET/SDH, Synchronous Ethernet, etc.). To perform this role in a variety of systems with diverse performance requirements, the T0 DPLL has a sophisticated feature set and is highly configurable. T0 can automatically transition among free-run, locked, and holdover states without software intervention. In free-run, T0 generates a stable, low-noise clock with the same frequency accuracy as the external oscillator connected to the REFCLK pin. With software calibration the DS3102 can even improve the accuracy to within 0.02ppm. When an input reference has been validated, T0 transitions to the locked state in which its output clock accuracy is equal to the accuracy of the input reference. While in the locked state, T0 acquires a high-accuracy long-term average frequency value to use as the holdover frequency. When its selected reference fails, T0 can very quickly detect the failure and enter the holdover state to avoid affecting its output clock. From holdover it can automatically switch to the next highest priority input reference, again without affecting its output clock (hitless switching). Switching among input references can be either revertive or nonrevertive. When all input references are lost, T0 stays in holdover, in which it generates a stable low-noise clock with initial frequency accuracy equal to its stored holdover value and drift performance determined by the quality of the external oscillator. With a suitable local oscillator the T0 DPLL provides holdover performance suitable for all applications up to and including Stratum 2. T0 can also perform phase build-outs and fine-granularity output clock phase adjustments. The T4 DPLL has a much less demanding role to play and therefore is much simpler than T0. Often T4 is used as a frequency converter to create a derived DS1- or E1-rate clock (frequency locked to an incoming SONET/SDH port) to be sent to a nearby BITS Timing Signal Generator (TSG, Telcordia terminology) or Synchronization Supply Unit (SSU, ITU-T terminology). In other applications T4 is phase-locked to T0 and used as a frequency converter to produce additional output clock rates for use within the system, such as N x DS1, N x E1, N x DS2, DS3, E3, 125MHz for Synchronous Gigabit Ethernet, or 156.25MHz for Synchronous 10G Ethernet. T4 can also be configured as a measuring tool to measure the frequency of an input reference or the phase difference between two input references. At the front end of both the T0 and T4 DPLLs is the Input Clock Selector, Divider, and Monitor (ICSDM) block. This block continuously monitors as many as 8 different input clocks of various frequencies for activity and frequency accuracy. In addition, ICSDM maintains separate input clock priority tables for the T0 and T4 DPLLs, and can automatically select and provide the highest priority valid clock to each DPLL without any software intervention. The ICSDM block can also divide the selected clock down to a lower rate as needed by the DPLL. The Output Clock Synthesizer and Selector (OCSS) block shown in Figure 3-1 and in more detail in Figure 7-1 contains three output APLLs—T0 APLL, T0 APLL2, and T4 APLL—and their associated DFS engines and output divider logic plus several additional DFS engines. The APLL DFS blocks perform frequency translation, creating clocks of other frequencies that are phase/frequency locked to the output clock of the associated DPLL. The APLLs multiply the clock rates from the APLL DFS blocks and simultaneously attenuate jitter. Altogether the output blocks of the DS3102 can produce more than 90 different output frequencies including common SONET/SDH, PDH and Synchronous Ethernet rates plus 2kHz and 8kHz frame-sync pulses. 1 These names are adapted from output ports of the SETS function specified in ITU-T and ETSI standards such as ETSI EN 300 462-2-1. 19-4617; Rev 5; 8/10 9 of 142 ____________________________________________________________________________________________ DS3102 The entire chip is clocked from the external oscillator connected to the REFCLK pin. Thus, the free-run and holdover stability of the DS3102-based timing card is entirely a function of the stability of the external oscillator, the performance of which can be selected to match the application: TCXO, OCXO, double-oven OCXO, etc. The 12.8MHz clock from the external oscillator is multiplied by 16 by the Master Clock Generator block to create the 204.8MHz master clock used by the rest of the device. Since every block on the device depends on the master clock and therefore the local oscillator clock for proper operation, the master clock generator has a watchdog timer (WDT) function that can be used to signal a local microprocessor in the event of a local oscillator clock failure. The DS3102 also has several features to support master/slave timing card redundancy and protection. Two DS3102 devices on redundant cards can be configured to maintain the same priority tables, choose the same input references, and generate output clocks and frame syncs with the same frequency and phase. 19-4617; Rev 5; 8/10 10 of 142 ____________________________________________________________________________________________ DS3102 5. Detailed Features 5.1 Input Clock Features       5.2                 5.3            Eight input clocks: four CMOS/TTL (≤ 125MHz) and four LVDS/LVPECL/CMOS/TTL (≤ 156.25MHz) CMOS/TTL input clocks accept any multiple of 2kHz up to 125MHz LVDS/LVPECL inputs accept any multiple of 2kHz up to 131.072MHz, any multiple of 8kHz up to 155.52MHz plus 156.25MHz All input clocks are constantly monitored by programmable frequency monitors and activity monitors Fast activity monitor can disqualify the selected reference after two missing clock cycles Three optional 2/4/8kHz frame-sync inputs T0 DPLL Features High-resolution DPLL plus two or three low-jitter output APLLs Sophisticated state machine automatically transitions between free-run, locked, and holdover states Revertive or nonrevertive reference selection algorithm Programmable bandwidth from 0.5mHz to 400Hz Separately configurable acquisition bandwidth and locked bandwidth Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (360 capture) or nearest edge phase locking (180 capture) Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time Phase build-out in response to reference switching Less than 5 ns output clock phase transient during phase build-out Output phase adjustment up to 200ns in 6ps steps with respect to selected input reference High-resolution frequency and phase measurement Holdover frequency averaging over 8- or 110-minute intervals Fast detection of input clock failure and transition to holdover mode Low-jitter frame sync (8kHz) and multiframe sync (2kHz) aligned with output clocks T4 DPLL Features High-resolution DPLL plus low-jitter output APLL Programmable bandwidth from 18Hz to 70Hz Programmable damping factor to balance lock time with peaking: 1.2, 2.5, 5, 10, or 20 Multiple phase detectors: phase/frequency, early/late, and multicycle Phase/frequency locking (360 capture) or nearest edge phase locking (180 capture) Multicycle phase detection and locking (up to 8191UI) improves jitter tolerance and lock time 2kHz and 8kHz frame syncs with programmable polarity and pulse width Can operate independently or locked to T0 DPLL Phase detector can be used to measure phase difference between two input clocks Optional PLL bypass mode provides input clock monitoring, selection, and optional frequency division but bypasses the DPLL and APLL when they are not needed (e.g., dividing an input clock to 8kHz) High-resolution frequency and phase measurement 19-4617; Rev 5; 8/10 11 of 142 ____________________________________________________________________________________________ DS3102 5.4     5.5        5.6    5.7      Output APLL Features Three separate clock multiplying, jitter attenuating APLLs can simultaneously produce SONET/SDH rates, Fast/Gigabit Ethernet rates, and 10G Ethernet rates, all locked to a common reference clock The T0 APLL, always connected to the T0 DPLL, has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x 25MHz, and N x 62.5MHz The T4 APLL can be connected to either the T0 DPLL or the T4 DPLL and has frequency options suitable for N x 19.44MHz, N x DS1, N x E1, N x DS2, DS3, E3, N x 10MHz, N x 10.24MHz, N x 13MHz, N x 25MHz, and N x 62.5MHz The T0 APLL2, always connected to the T0 DPLL, produces 312.5MHz for 10G Synchronous Ethernet applications Output Clock Features Seven output clocks: three CMOS/TTL (≤ 125MHz), two LVDS/LVPECL (≤ 312.50MHz), and two dual CMOS/TTL and LVDS/LVPECL Output clock rates include 2kHz, 8kHz, N x DS1, N x E1, DS2, DS3, E3, 6.48MHz, 19.44MHz, 38.88MHz, 51.84MHz, 77.76MHz, 155.52MHz, 311.04MHz, 2.5MHz, 25MHz, 125MHz, 156.25MHz, 312.50MHz, 10MHz, 10.24MHz, 13MHz, 30.72MHz, and various multiples and submultiples of these rates Custom clock rates also available: any multiple of 2kHz up to 77.76MHz, any multiple of 8kHz up to 311.04MHz, and any multiple of 10kHz up to 388.79MHz Three independent output APLLs support simultaneous generation of 155.52MHz for SONET/SDH, 125MHz for Gigabit Ethernet, and 156.25/312.5MHz for 10G Ethernet (plus various multiples/submultiples of each) All outputs have < 1ns peak-to-peak output jitter; outputs from APLLs have < 0.5ns peak-to-peak Each CMOS/TTL clock output has two leads, the standard output (e.g., OC1) with a 3.3V power supply, and the “B” output (e.g., OC1B) connected to the VDDIOB power supply for optional 2.5V output signal levels. 8kHz frame sync and 2kHz multiframe sync outputs have programmable polarity and pulse width and can be disciplined by a 2kHz or 8kHz sync input Redundancy Features Devices on redundant timing cards can be configured for master/slave operation Clocks and frame syncs can be cross-wired between devices to ensure that slave always tracks master Input clock priority tables can easily be kept synchronized between master and slave General Features Operates from a single external 12.800MHz local oscillator (XO, TCXO, or OCXO) On-chip watchdog circuit for the local (REFCLK) oscillator SPI serial microprocessor interface Four general-purpose I/O pins Register set can be write protected 19-4617; Rev 5; 8/10 12 of 142 ____________________________________________________________________________________________ DS3102 6. Pin Descriptions Table 6-1. Input Clock Pin Descriptions PIN NAME(1) TYPE(2) REFCLK I IC1POS, IC1NEG IDIFF IC2POS, IC2NEG IDIFF IC3 IPD IC4 IPD IC5POS, IC5NEG IDIFF IC6POS, IC6NEG IDIFF IC8 IPD IC9 IPD SYNC1 IPD SYNC2 IPD FSCR3:SOURCE ! = 11XX. This pin is not used for the external frame-sync signal. FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC4 or IC6, depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame-Sync 3 Input. 2kHz, 4kHz, or 8kHz. SYNC3 IPU FSCR3:SOURCE ! = 11XX. This pin is not used for the external frame-sync signal. FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC9 or IC2, depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. 19-4617; Rev 5; 8/10 PIN DESCRIPTION Reference Clock. Connect to a 12.800MHz, high-accuracy, high-stability, low-noise local oscillator (TCXO, OCXO, or XO). See Section 7.3. Input Clock 1. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 8kHz). LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2. CMOS/TTL: Bias IC1NEG to 1.4V and connect the single-ended signal to IC1POS. Input Clock 2. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 8kHz). LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2. CMOS/TTL: Bias IC2NEG to 1.4V and connect the single-ended signal to IC2POS. This input can be associated with the SYNC3 pin. Input Clock 3. CMOS/TTL. Programmable frequency (default 8kHz). This input can be associated with the SYNC1 pin. Input Clock 4. CMOS/TTL. Programmable frequency (default 8kHz). This input can be associated with the SYNC2 pin. Input Clock 5. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44MHz). LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2. CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS. This input can be associated with the SYNC1 pin. Input Clock 6. LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44MHz). LVDS/LVPECL: See Table 10-4, Figure 10-1, and Figure 10-2. CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS. This input can be associated with the SYNC2 pin. Input Clock 8. CMOS/TTL. Programmable input reference (default 19.44MHz). Input Clock 9. CMOS/TTL. Programmable frequency (default 19.44MHz). This input can be associated with the SYNC3 pin. Frame-Sync 1 Input. 2kHz, 4kHz, or 8kHz. FSCR3:SOURCE ! = 11XX. This pin is the external frame-sync input associated with any input pin using the FSCR3:SOURCE field. FSCR3:SOURCE = 11XX. This pin is the external frame-sync signal associated with IC3 or IC5, depending on which one is currently selected and the setting of FSCR1.SYNCSRC[1:0]. Frame-Sync 2 Input. 2kHz, 4kHz, or 8kHz. 13 of 142 ____________________________________________________________________________________________ DS3102 Table 6-2. Output Clock Pin Descriptions PIN NAME(1) TYPE(2) OC1 O Output Clock 1. CMOS/TTL. Programmable frequency (default 6.48MHz). OC2 O Output Clock 2. CMOS/TTL. Programmable frequency (default 38.88MHz). OC3 O Output Clock 3. CMOS/TTL. Programmable frequency (default 19.44MHz). OC4 O Output Clock 4. CMOS/TTL. Programmable frequency (default 38.88MHz). OC5 O OC4POS, OC4NEG ODIFF OC5POS, OC5NEG ODIFF OC6POS, OC6NEG ODIFF OC7POS, OC7NEG ODIFF OC1B/ GPIO1 O3 OC2B/ GPIO2 O3 OC3B/ GPIO3 O3 OC4B O3 OC5B O3 FSYNC O3 MFSYNC O3 19-4617; Rev 5; 8/10 PIN DESCRIPTION Output Clock 5. CMOS/TTL. Programmable frequency (default 1.544MHz or 2.048MHz depending on the value SONSDH pin at power-up or reset). Output Clock 4. LVDS/LVPECL. These pins present the same clock as the OC4 pin but in differential signal format. The output mode is selected by MCR8.OC4SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure 10-3. Output Clock 5. LVDS/LVPECL. These pins present the same clock as the OC5 pin but in differential signal format. The output mode is selected by MCR8.OC5SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure 10-3. Output Clock 6. LVDS/LVPECL. Programmable frequency (default 38.88MHz LVDS). The output mode is selected by MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure 10-3. Output Clock 7. LVDS/LVPECL. Programmable frequency (default 19.44MHz LVDS). The output mode is selected by MCR8.OC7SF[1:0]. See Table 10-5, Table 10-6, Figure 10-1, and Figure 10-3. Output Clock 1B/General-Purpose I/O 1. CMOS/TTL (default CLK1B, disabled). This pin is programmable as an output clock pin or a GPIO pin using OCR6.OC1BEN. When programmed as a clock output pin (OC1BEN = 1) it presents the same clock as the OC1 pin. This pin is powered from the VDDIOB power-supply pin. Output Clock 2B/General-Purpose I/O 2. CMOS/TTL (default CLK2B, disabled). This pin is programmable as an output clock pin or a GPIO pin using OCR6.OC2BEN. When programmed as a clock output pin (OC2BEN = 1) it presents the same clock as the OC2 pin. This pin is powered from the VDDIOB power-supply pin. Output Clock 3B/General-Purpose I/O 3. CMOS/TTL (default CLK3B, disabled). This pin is programmable as an output clock pin or a GPIO pin using OCR6.OC3BEN. When programmed as a clock output pin (OC3BEN = 1) it presents the same clock as the OC3 pin. This pin is powered from the VDDIOB power-supply pin. Output Clock 4B. CMOS/TTL (default off). When enabled (OCR6.OC4BEN = 1), this pin presents the same clock as the OC4 pin. This pin is powered from the VDDIOB power-supply pin. Output Clock 5B. CMOS/TTL (default off) . When enabled (OCR6.OC5BEN = 1), this pin presents the same clock as the OC5 pin. This pin is powered from the VDDIOB power-supply pin. FSYNC. CMOS/TTL. 8kHz frame sync or clock (default 50% duty cycle clock, noninverted). The pulse polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL. MFSYNC. CMOS/TTL. 2kHz frame sync or clock (default 50% duty cycle clock, noninverted). The pulse polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL. 14 of 142 ____________________________________________________________________________________________ DS3102 Table 6-3. Global Pin Descriptions PIN NAME(1) TYPE(2) RST IPU SRCSW IPD TEST IPD WDT I/O SONSDH/ GPIO4 I/OPD SRFAIL O LOCK O INTREQ/ LOS O3 PIN DESCRIPTION Reset (Active Low). When this global asynchronous reset is pulled low, all internal circuitry is reset to default values. The device is held in reset as long as RST is low. RST should be held low for at least two REFCLK cycles after the external oscillator has stabilized and is providing valid clock signals. Source Switching. Fast source-switching control input. See Section 7.6.5. The value of this pin is latched into MCR10:EXTSW when RST goes high. After RST goes high this pin can be used to select between IC3/IC5 and IC4/IC6, if enabled. Factory Test Mode Select. Wire this pin to VSS for normal operation. Watchdog Timer Pin. Analog node for the REFCLK watchdog timer. Connect to a resistor (R) to VDDIO and a capacitor (C) to ground. Suggested values are R = 10k and C = 0.01F. See Section 7.3. SONET/SDH Frequency Select Input/General-Purpose I/O 4. When RST goes high the state of this pin sets the reset-default state of MCR3:SONSDH, MCR6:DIG1SS, and MCR6:DIG2SS. After RST goes high this pin can be used as a general-purpose I/O pin. GPCR:GPIO4D configures this pin as an input or an output. GPCR:GPIO4O specifies the output value. GPSR:GPIO4 indicates the state of the pin. Reset latched values: 0 = SDH rates (N x 2.048MHz) 1 = SONET rates (N x 1.544MHz) SRFAIL Status. When MCR10:SRFPIN = 1, this pin follows the state of the SRFAIL latched status bit in the MSR2 register. This gives the system a very fast indication of the failure of the current reference. When MCR10:SRFPIN = 0, SRFAIL is disabled (high impedance). T0 DPLL LOCK Status. When MCR1.LOCKPIN = 1, this pin indicates the lock state of the T0 DPLL. When MCR1.LOCKPIN = 0, LOCK is disabled (low). 0 = Not locked 1 = Locked Interrupt Request/Loss of Signal. Programmable (default: INTREQ). The INTCR:LOS bit determines whether the pin indicates interrupt requests or loss of signal (i.e., loss of selected reference). INTCR:LOS = 0: INTREQ Mode. The behavior of this pin is configured in the INTCR register. Polarity can be active high or active low. Drive action can be push-pull or open drain. The pin can also be configured as a general-purpose output if the interrupt request function is not needed. INTCR:LOS = 1: LOS Mode. This pin indicates the real-time state of the selected reference activity monitor (see Section 7.5.3). This function is most useful when external switching mode (Section 7.6.5) is enabled (MCR10:EXTSW = 1). Table 6-4. SPI Bus Mode Pin Descriptions See Section 7.10 for functional description and Section 10.4 for timing specifications. PIN NAME(1) TYPE(2) CS IPU Chip Select. This pin must be asserted (low) to read or write internal registers. SCLK SDI SDO I I O CPHA I CPOL IPD Serial Clock. SCLK is always driven by the SPI bus master. Serial Data Input. The SPI bus master transmits data to the device on this pin. Serial Data Output. The device transmits data to the SPI bus master on this pin. Clock Phase. See Figure 7-5. 0 = Data is latched on the leading edge of the SCLK pulse. 1 = Data is latched on the trailing edge of the SCLK pulse. Clock Polarity. See Figure 7-5. 0 = SCLK is normally low and pulses high during bus transactions. 1 = SCLK is normally high and pulses low during bus transactions. 19-4617; Rev 5; 8/10 PIN DESCRIPTION 15 of 142 ____________________________________________________________________________________________ DS3102 Table 6-5. JTAG Interface Pin Descriptions See Section 9 for functional description and Section 10.5 for timing specifications. PIN NAME(1) TYPE(2) JTRST IPU JTCLK I JTDI IPU JTDO O3 JTMS IPU PIN DESCRIPTION JTAG Test Reset (Active Low). Asynchronously resets the test access port (TAP) controller. If not used, JTRST can be held low or high. JTAG Clock. Shifts data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, JTCLK can be held low or high. JTAG Test Data Input. Test instructions and data are clocked in on this pin on the rising edge of JTCLK. If not used, JTDI can be held low or high. JTAG Test Data Output. Test instructions and data are clocked out on this pin on the falling edge of JTCLK. If not used, leave unconnected. JTAG Test Mode Select. Sampled on the rising edge of JTCLK and is used to place the port into the various defined IEEE 1149.1 states. If not used connect to VDDIO or leave unconnected. Table 6-6. Power-Supply Pin Descriptions PIN NAME(1) VDD VDDIO VDDIOB VSS VDD_OC45 VSS_OC45 VDD_OC67 VSS_OC67 AVDD_PLL1 AVSS_PLL1 AVDD_PLL2 AVSS_PLL2 AVDD_PLL3 AVSS_PLL3 AVDD_PLL4 AVSS_PLL4 TYPE(2) P P P P P P P P P P P P P P P P PIN DESCRIPTION Core Power Supply. 1.8V 10%. I/O Power Supply. 3.3V 5%. Power for Pins OC1B to OC5B. Voltage can be from 2.5V 5% to 3.3V 5%. Ground Reference Power Supply for Differential Outputs OC4POS/NEG and OC5POS/NEG. 1.8V 10%. Return for Differential Outputs OC4POS/NEG and OC5POS/NEG Power Supply for Differential Outputs OC6POS/NEG and OC7POS/NEG. 1.8V 10%. Return for LVDS Differential Outputs OC6POS/NEG and OC7POS/NEG Power Supply for Master Clock Generator APLL. 1.8V 10%. Return for Master Clock Generator APLL Power Supply for T0 APLL. 1.8V 10%. Return for T0 APLL Power Supply for T4 APLL. 1.8V 10%. Return for T4 APLL Power Supply for T0 APLL2. 1.8V 10%. Return for T0 APLL2 Note 1: All pin names with an overbar (e.g., RST) are active low. Note 2: All pins, except power and analog pins, are CMOS/TTL, unless otherwise specified in the pin description. PIN TYPES I = input pin IDIFF = input pin that is LVDS/LVPECL differential signal compatible IPD = input pin with internal 50k pulldown IPU = input pin with internal 50k pullup I/O = input/output pin IOPD = input/output pin with internal 50k pulldown IOPU = input/output pin with internal 50k pullup O = output pin O3 = output pin that can placed in a high-impedance state ODIFF = output pin that is LVDS/LVPECL differential signal compatible P = power-supply pin Note 3: All digital pins, except OCn, are I/O pins in JTAG mode. OCn pins do not have JTAG functionality. 19-4617; Rev 5; 8/10 16 of 142 ____________________________________________________________________________________________ DS3102 7. Functional Description 7.1 Overview The DS3102 has eight input clocks pins and three frame-sync input pins. The device can output as many as nine different clock frequencies on 16 output clock pins. There are two separate DPLLs in the device: the highperformance T0 DPLL and the simpler the T4 DPLL. Both DPLLs can generate output clocks. See Figure 3-1. Four of the input clock pins are single-ended and can accept clock signals from 2kHz to 125MHz. The other four are differential inputs that can accept clock signals up to 156.25MHz. The differential inputs can be configured to accept differential LVDS or LVPECL signals or single-ended CMOS/TTL signals. Each input clock can be monitored continually for activity and/or frequency. Frequency can be compared to both a hard limit and a soft limit. Inputs outside the hard limit are declared invalid, while inputs inside the hard limit but outside the soft limit are merely flagged. Each input can be marked unavailable or given a priority number. Separate input priority numbers are maintained for the T0 DPLL and the T4 DPLL. Except in special modes, the highest priority valid input is automatically selected as the reference for each path. SRFAIL is set or cleared based on activity and/or frequency of the selected input. Both the T0 DPLL and the T4 DPLL can directly lock to many common telecom and datacom frequencies, including, but not limited to, 8kHz, DS1, E1, 10MHz, 19.44MHz, and 38.88MHz as well as Ethernet frequencies including 25MHz, 62.5MHz, 125MHz, and 156.25MHz. The DPLLs can also lock to multiples of the standard directlock frequencies including 8kHz. The T0 DPLL is the high-performance path with all the features needed for line timing synchronization. The T4 DPLL is a simpler auxiliary path typically used to provide derived DS1s, E1s, or other synchronization signals to an external BITS/SSU. The T4 APLL can be connected to either the T4 DPLL or the T0 DPLL to provide extra lowjitter output frequencies from the T0 DPLL. There is also a dedicated low-jitter APLL output that operates at 312.5MHz for 10G Ethernet applications. Using the optional PLL bypass, the T4 selected reference, after any frequency division, can be directly output on any of the OC1 to OC7 output clock pins. Both DPLLs have these features:        Automatic reference selection based on input activity, quality, and priority Optional manual reference selection/forcing Configurable quality thresholds for each input Adjustable PLL characteristics, including bandwidth, pull-in range, and damping factor Ability to lock to several common telecom and Ethernet frequencies plus multiples of any standard direct lock frequency. Frequency conversion between input and output using digital frequency synthesis Combined performance of a stable, consistent digital PLL and low-jitter analog output PLLs The T0 DPLL has these additional features not available in the T4 DPLL:         A full state machine for automatic transitions among free-run, locked, and holdover states Nonrevertive reference switching mode Phase build-out for reference switching (“hitless”) and for phase hits on the selected reference Output vs. input phase offset control 21 bandwidth selections from 0.5mHz to 400Hz (vs. three selections for the T4 DPLL) Noise rejection circuitry for low-frequency references Output phase alignment to input frame-sync signal Several frequency averaging methods for acquiring the holdover frequency The T4 DPLL has these additional features not available in the T0 DPLL:   Three bandwidth selections limited to 18Hz to 70Hz Optional mode to measure the phase difference between two input clocks 19-4617; Rev 5; 8/10 17 of 142 ____________________________________________________________________________________________ DS3102 Typically, the internal state machine controls the T0 DPLL, but manual control by system software is also available. The T4 DPLL has a simpler state machine that software cannot directly control. In either DPLL, however, software can override the DPLL logic using manual reference selection. The output and feedback synthesizers are locked to either the T0 DPLL or the T4 DPLL. Most of the output signals that are locked to the same DPLL are always aligned to the falling edge at 2kHz. The outputs of the T0 DPLL and the T4 DPLL can be connected to seven output DFS engines. See Figure 7-1. Three of these output DFS engines are associated with high-speed APLLs that multiply the DPLL clock rate and filter DPLL output jitter. The outputs of the APLLs are divided down to make a wide variety of possible frequencies available at the output clock pins. T0 APLL and T0 APLL2 are always locked to the T0 DPLL, while the T4 APLL can lock to either the T4 DPLL or the T0 DPLL. The output frequencies from the T0 DPLL can be synchronized to an input 2, 4, or 8kHz sync signal (SYNC1, SYNC2, or SYNC3 input pins). This synchronization to a low-frequency input enables, among other things, two redundant timing cards to maintain output frame-sync alignment with one another. The OC1 to OC7 output clocks can be configured for a variety of different frequencies that are frequency and phase-locked to either the T0 DPLL or the T4 DPLL. The OC6 and OC7 outputs are LVDS/LVPECL; OC4 and OC5 are available in both LVDS/LVPECL and 3.3V CMOS; and OC1 to OC3 are 3.3V CMOS. There are five outputs OC1B to OC5B that can be 3.3V or 2.5V CMOS outputs. Altogether more than 60 output frequencies are possible, ranging from 2kHz to 312.5MHz. The FSYNC output clock is always 8kHz, and the MFSYNC output clock is always 2kHz. 7.2 Device Identification and Protection The 16-bit read-only ID field in the ID1 and ID2 registers is set to 0C1Eh = 3102 decimal. The device revision can be read from the REV register. Contact the factory to interpret this value and determine the latest revision. The register set can be protected from inadvertent writes using the PROT register. 7.3 Local Oscillator and Master Clock Configuration The T0 DPLL, the T4 DPLL, and the output DFS engines operate from a 204.8MHz master clock. The master clock is synthesized from a 12.800MHz clock originating from a local oscillator attached to the REFCLK pin. The stability of the T0 DPLL in free-run or holdover is equivalent to the stability of the local oscillator. Selection of an appropriate local oscillator is therefore of crucial importance if the telecom standards listed in Table 1-1 are to be met. Simple XOs or TCXOs can be used in less stringent cases, but OCXOs may be required in the most demanding applications. Even OCXOs may need to be shielded to avoid slow frequency changes due to ambient temperature fluctuations and drift. Careful evaluation of the local oscillator component is necessary to ensure proper performance. Contact Maxim at www.maxim-ic.com/support for recommended oscillators. For reference, the Telcordia GR-1244-CORE stability requirements for Stratum 2, Stratum 3E and Stratum 3 are listed in Table 7-1. Table 7-1. GR-1244 Stratum 2/3E/3 Stability Requirements PARAMETER Temperature STRATUM 2 n/a Drift (nontemp)  1 x 10-10/day STRATUM 3E  10 x 10-9  1.16 x 10-14/sec ( 1 x 10-9/day) STRATUM 3  280 x 10-9  4.63 x 10-13/sec ( 40 x 10-9/day) Note: Refer to GR-1244-CORE for additional details. The stability of the local oscillator is very important, but its absolute frequency accuracy is less important because the DPLLs can compensate for frequency inaccuracies when synthesizing the 204.8MHz master clock from the local oscillator clock. The MCLKFREQ field in registers MCLK1 and MCLK2 specifies the frequency adjustment to be applied. The adjust can be from -771ppm to +514ppm in 0.0196229ppm (i.e., ~0.02ppm) steps. The DS3102 has a watchdog circuit that causes an interrupt on the INTREQ pin when the local oscillator attached to the REFCLK pin is significantly off frequency. The watchdog interrupt is not maskable, but is subject to the INTCR register settings. When the watchdog circuit activates, reads of any and all registers in the device will return 19-4617; Rev 5; 8/10 18 of 142 ____________________________________________________________________________________________ DS3102 00h to indicate the failure. In response to the activation of the INTREQ pin or during periodic polling, if system software ever reads 00h from the ID registers (which are hard-coded to 0C1Eh = 3102 decimal), it can conclude that the local oscillator attached to that DS3102 has failed. For proper operation of the watchdog timer, connect the WDT pin to a 10k resistor (R) to VDDIO and a 0.01F capacitor (C) to VSS. 7.4 Input Clock Configuration The DS3102 has eight input clocks: IC1 to IC6, IC8, and IC9. Table 7-2 provides summary information about each clock, including signal format and available frequencies. The device tolerates a wide range of duty cycles on input clocks, out to a minimum high time or minimum low time of 3ns or 30% of the clock period, whichever is smaller. 7.4.1 Signal Format Configuration Inputs with CMOS/TTL signal format accept both TTL and 3.3V CMOS levels. One key configuration bit that affects the available frequencies is the SONSDH bit in MCR3. When SONSDH = 1 (SONET mode), the 1.544MHz frequency is available. When SONSDH = 0 (SDH mode), the 2.048MHz frequency is available. During reset the default value of this bit is latched from the SONSDH pin. Input clocks IC1, IC2, IC5, and IC6 can be configured to accept LVDS, LVPECL, or CMOS/TTL signals by using the proper set of external components. The recommended LVDS termination is shown in Figure 10-1 while the recommended LVPECL termination is shown in Figure 10-2. The electrical specifications for these inputs are listed in Table 10-4. To configure these differential inputs to accept single-ended CMOS/TTL signals, use a voltagedivider to bias the ICxNEG pin to approximately 1.4V and connect the single-ended signal to the ICxPOS pin. If a differential input is not used it should be configured left unconnected (one input is internally pulled high and the other internally pulled low). (See also MCR5:IC5SF and IC6SF.) Table 7-2. Input Clock Capabilities INPUT CLOCK IC1 IC2 IC3 IC4 IC5 IC6 IC8 IC9 SIGNAL FORMATS LVDS/LVPECL or CMOS/TTL LVDS/LVPECL or CMOS/TTL CMOS/TTL CMOS/TTL LVDS/LVPECL or CMOS/TTL LVDS/LVPECL or CMOS/TTL CMOS/TTL CMOS/TTL FREQUENCIES (MHz) (2) Up to 156.25 Up to 156.25 (2) Up to 125 (1) Up to 125 (1) Up to 156.25 (2) Up to 156.25 (2) Up to 125 (1) Up to 125 (1) DEFAULT FREQUENCY 8kHz 8kHz 8kHz 8kHz 19.44MHz 19.44MHz 19.44MHz 19.44MHz Note 1: Available frequencies for CMOS/TTL input clocks are: 2kHz, 4kHz, 8kHz, 1.544MHz (SONET mode), 2.048MHz (SDH mode), 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, and any multiple of 2kHz up to 125MHz. Note 2: Available frequencies for LVDS/LVPECL input clocks include all CMOS/TTL frequencies in Note 1 plus any multiple of 8kHz up to 155.52MHz and 156.25MHz. 19-4617; Rev 5; 8/10 19 of 142 ____________________________________________________________________________________________ DS3102 7.4.2 Frequency Configuration Input clock frequencies are configured in the FREQ field of the ICR registers. The DIVN and LOCK8K bits of these same registers specify the locking frequency mode, as shown in Table 7-3. Table 7-3. Locking Frequency Modes DIVN LOCK8K 0 0 1 1 0 1 0 1 LOCKING FREQUENCY MODE Direct Lock LOCK8K DIVN Alternate Direct Lock 7.4.2.1 Direct Lock Mode In direct lock mode, the DPLLs lock to the selected reference at the frequency specified in the corresponding ICR register. Direct lock mode can only be used for input clocks with these specific frequencies: 2kHz, 4kHz, 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz, 77.76MHz, and 155.52MHz. For the 155.52MHz case, the input clock is internally divided by two, and the DPLL direct-locks at 77.76MHz. The DIVN mode can be used to divide an input down to any of these frequencies except 155.52MHz. MTIE figures may be marginally better in direct lock mode because the higher frequencies allow more frequent phase updates. 7.4.2.2 Alternate Direct Lock Mode Alternate direct lock mode is the same as direct lock mode except an alternate list of direct lock frequencies is used (see the FREQ field definition in the ICR register description). The alternate frequencies are included to support clock rates found in Ethernet, CMTS, wireless, and GPS applications. The alternate frequencies are: 10MHz, 25MHz, 62.5MHz, 125MHz, and 156.25MHz. The frequencies 62.5MHz, 125MHz, and 156.25MHz are internally divided down to 31.25MHz, while 10MHz and 25MHz are internally divided down to 5MHz. 7.4.2.3 LOCK8K Mode In LOCK8K mode, an internal divider is configured to divide the selected reference down to 8kHz. The DPLL locks to the 8kHz output of the divider. LOCK8K mode can only be used for input clocks with the standard direct lock frequencies: 8kHz, 1.544MHz, 2.048MHz, 5MHz, 6.312MHz, 6.48MHz, 19.44MHz, 25.0MHz, 25.92MHz, 31.25MHz, 38.88MHz, 51.84MHz, 62.5MHz, 77.76MHz, and 155.52MHz. LOCK8K mode is enabled for a particular input clock by setting the LOCK8K bit in the corresponding ICR register. LOCK8K mode gives a greater tolerance to input jitter when the multicycle phase detector is disabled because it uses lower frequencies for phase comparisons. The clock edge to lock to on the selected reference can be configured using the 8KPOL bit in the TEST1 register. For 2kHz and 4kHz clocks the LOCK8K bit is ignored and direct-lock mode is used. 7.4.2.4 DIVN Mode In DIVN mode, an internal divider is configured from the value stored in the DIVN registers. The DIVN value must be chosen so that when the selected reference is divided by DIVN + 1, the resulting clock frequency is the same as the standard direct lock frequency selected in the FREQ field of the ICR register. The DPLL locks to the output of the divider. DIVN mode can only be used for input clocks whose frequency is less than or equal to 155.52MHz. The DIVN register field can range from 0 to 65,535 inclusive. The same DIVN + 1 factor is used for all input clocks configured for DIVN mode. Note that although the DIVN divider is able to divide down clock rates as high as 155.52MHz, the CMOS/TTL inputs are only rated for a maximum clock rate of 125MHz. 19-4617; Rev 5; 8/10 20 of 142 ____________________________________________________________________________________________ DS3102 7.5 Input Clock Monitoring Each input clock is continuously monitored for frequency accuracy and activity. Frequency monitoring is desribed in Section 7.5.1, while activity monitoring is described in Sections 7.5.2 and 7.5.3. Any input clock that has a frequency out-of-band alarm or activity alarm is automatically declared invalid. The valid/invalid state of each input clock is reported in the corresponding real-time status bit in registers VALSR1 or VALSR2. When the valid/invalid state of a clock changes, the corresponding latched status bit is set in registers MSR1 or MSR2, and an interrupt request occurs if the corresponding interrupt enable bit is set in registers IER1 or IER2. Input clocks marked invalid cannot be automatically selected as the reference for either DPLL. If the T4 DPLL does not have any valid input clocks available, the T4NOIN status bit is set to 1 in MSR3. 7.5.1 Frequency Monitoring The DS3102 monitors the frequency of each input clock and invalidates any clock whose frequency is outside specified limits. Two different monitors are available: the course frequency range monitor and the high-resolution frequency monitor. The course frequency range monitor can quickly (less than 2ms) determine whether the input clock frequency is within approximately 10,000ppm of the target frequency. When the frequency range monitor is enabled by setting MCR1:FREN = 1, input clocks with frequency outside the 10,000ppm limit are very quickly disqualified. The high-resolution frequency monitor has two frequency limits that can be specified: a soft limit and a hard limit. For all input clocks except the T0 DPLL’s selected reference, these limits are specified in the ILIMIT register. For the T0 DPLL’s selected reference, the limits are specified in the SRLIMIT register. When the frequency of an input clock is greater than or equal to the soft limit, the corresponding SOFT alarm bit is set to 1 in the ISR registers. The soft limit is only for monitoring; triggering it does not invalidate the clock. When the frequency of an input clock is greater than or equal to the hard limit, the corresponding HARD alarm bit is set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. Monitoring according to the hard and soft limits is enabled/disabled using the HARDEN and SOFTEN bits in the MCR10 register. Both the ILIMIT and SRLIMIT registers have a default soft limit of 11.43ppm and a default hard limit of 15.24ppm. Limits can be set from 3.81ppm to 60.96ppm in 3.81ppm steps. Frequency monitoring is only done on an input clock when the clock does not have an activity alarm. 4 Frequency measurements can be done with respect to the internal 204.8MHz master clock or the T0 DPLL internal frequency, as specified by the FMONCLK bit in MCR10. Measured frequency can be read from any frequency monitor by specifying the input clock in the FMEASIN field of MCR11 and reading the frequency from the FMEAS register. 7.5.2 Activity Monitoring Each input clock is monitored for activity and proper behavior using a leaky bucket accumulator. A leaky bucket accumulator is similar to an analog integrator: the output amplitude increases in the presence of input events and gradually decays in the absence of events. When events occur infrequently, the accumulator value decays fully between events and no alarm is declared. When events occur close enough together, the accumulator increments faster than it can decay and eventually reaches the alarm threshold. After an alarm has been declared, if events occur infrequently enough, the accumulator can decay faster than it is incremented and eventually reaches the alarm clear threshold. The leaky bucket events come from the frequency range and fast activity monitors. The leaky bucket accumulator for each input clock can be assigned one of four configurations (0 to 3) in the BUCKET field of the ICR registers. Each leaky bucket configuration has programmable size, alarm declare threshold, alarm clear threshold, and decay rate, all of which are specified in the LBxy registers. Activity monitoring is divided into 128ms intervals. The accumulator is incremented once for each 128ms interval in which the input clock is inactive for more than two cycles (more than four cycles for 155.52MHz, 156.25MHz, 125MHz, 62.5MHz, 25MHz, and 10MHz input clocks). Thus the “fill” rate of the bucket is at most 1 unit per 128ms, or approximately 8 units/second. During each period of 1, 2, 4, or 8 intervals (programmable), the accumulator 19-4617; Rev 5; 8/10 21 of 142 ____________________________________________________________________________________________ DS3102 decrements if no irregularities occur. Thus the “leak” rate of the bucket is approximately 8, 4, 2, or 1 units/second. A leak is prevented when a fill event occurs in the same interval. When the value of an accumulator reaches the alarm threshold (LBxU register), the corresponding ACT alarm bit is set to 1 in the ISR registers, and the clock is marked invalid in the VALSR registers. When the value of an accumulator reaches the alarm clear threshold (LBxL register), the activity alarm is cleared by clearing the clock’s ACT bit. The accumulator cannot increment past the size of the bucket specified in the LBxS register. The decay rate of the accumulator is specified in the LBxD register. The values stored in the leaky bucket configuration registers must have the following relationship at all times: LBxS ≥ LBxU > LBxL. 4 When the leaky bucket is empty, the minimum time to declare an activity alarm in seconds is LBxU / 8 (where the x in LBxU is the leaky bucket configuration number 0 to 3). The minimum time to clear an activity alarm in seconds is 2^LBxD * (LBxS – LBxL) / 8. For example, assume LBxU = 8, LBxL = 1, LBxS = 10, and LBxD = 0. The minimum time to declare an activity alarm would be 8 / 8 = 1 second. The minimum time to clear the activity alarm would be 2^0 * (10 – 1) / 8 = 1.125 seconds. 7.5.3 Selected Reference Activity Monitoring The input clock that each DPLL is currently locked to is called the selected reference. The quality of a DPLL’s selected reference is exceedingly important, since missing cycles and other anomalies on the selected reference can cause unwanted jitter, wander, or frequency offset on the output clocks. When anomalies occur on the selected reference they must be detected as soon as possible to give the DPLL opportunity to temporarily disconnect from the reference until the reference is available again. By design, the regular input clock activity monitor (Section 7.5.2) is too slow to be suitable for monitoring the selected reference. Instead, each DPLL has its own fast activity monitor that detects that the frequency is within range (approximately 10,000ppm) and detects inactivity within approximately two missing reference clock cycles (approximately four missing cycles for 156.25MHz, 155.52MHz, 125MHz, 62.5MHz, 25MHz, and 10MHz references). When the T0 DPLL detects a no-activity event, it immediately enters mini-holdover mode to isolate itself from the selected reference and sets the SRFAIL latched status bit in MSR2. The setting of the SRFAIL bit can cause an interrupt request if the corresponding enable bit is set in IER2. If MCR10:SRFPIN = 1, the SRFAIL output pin follows the state of the SRFAIL status bit. Optionally, a no-activity event can also cause an ultra-fast reference switch (see Section 7.6.4). When PHLIM1:NALOL = 0 (default), the T0 DPLL does not declare loss-of-lock during no-activity events. If the selected reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL continues to track the selected reference using nearest edge locking (180) to avoid cycle slips. When NALOL = 1, the T0 DPLL declares loss-of-lock during no-activity events. This causes the T0 DPLL state machine to transition to the loss-of-lock state, which sets the MSR2:STATE bit and causes an interrupt request if enabled. If the selected reference becomes available again before any alarms are declared by the activity monitor, the T0 DPLL tracks the selected reference using phase/frequency locking (360) until phase lock is reestablished. When the T4 DPLL detects a no-activity event, its behavior is similar to the T0 DPLL with respect to the PHLIM1:NALOL control bit. Unlike the T0 DPLL, however, the T4 DPLL does not set the SRFAIL status bit. If NALOL = 1, the T4 DPLL clears the OPSTATE:T4LOCK status bit, which sets MSR3:T4LOCK and causes an interrupt request if enabled. 19-4617; Rev 5; 8/10 22 of 142 ____________________________________________________________________________________________ DS3102 7.6 Input Clock Priority, Selection, and Switching 7.6.1 Priority Configuration During normal operation, the selected reference for the T0 DPLL and the selected reference for the T4 DPLL are chosen automatically based on the priority rankings assigned to the input clocks in the input priority registers (IPR1 to IPR5). Each of these registers has priority fields for one or two input clocks. When T4T0 = 0 in the MCR11 register, the IPR registers specify the input clock priorities for the T0 DPLL. When T4T0 = 1, the IPR registers specify the input clock priorities for the T4 DPLL. The default input clock priorities, for both PLLs, are shown in Table 7-4. Any unused input clock should be given the priority value 0, which disables the clock and marks it as unavailable for selection. Priority 1 is highest while priority 15 is lowest. The same priority can be given to two or more clocks. Table 7-4. Default Input Clock Priorities INPUT CLOCK IC1 IC2 IC3 IC4 IC5 IC6 IC8 IC9 T0 DPLL DEFAULT PRIORITY 0 (off) 1 2 3 0 (off) 0 (off) 4 5 T4 DPLL DEFAULT PRIORITY 0 (off) 1 2 3 0 (off) 0 (off) 5 0 (off) 7.6.2 Automatic Selection Algorithm The real-time valid/invalid state of each input clock is maintained in the VALSR1 and VALSR2 registers. The selected reference can be marked invalid for phase lock, frequency, or activity. Other input clocks can be invalidated for frequency or activity. The reference selection algorithm for each DPLL chooses the highest priority valid input clock to be the selected reference. To select the proper input clock based on these criteria, the selection algorithm maintains a priority table of valid inputs. The top three entries in this table and the selected reference are displayed in the PTAB1 and PTAB2 registers. When T4T0 = 0 in the MCR11 register, these registers indicate the highest priority input clocks for the T0 DPLL. When T4T0 = 1, they indicate the highest priority input clocks for the T4 DPLL. If two or more input clocks are given the same priority number, those inputs are prioritized among themselves using a fixed circular list. If one equal-priority clock is the selected reference but becomes invalid, the next equal-priority clock in the list becomes the selected reference. If an equal-priority clock that is not the selected reference becomes invalid, it is simply skipped over in the circular list. The selection among equal-priority inputs is inherently nonrevertive, and revertive switching mode (see next paragraph) has no effect in the case where multiple equalpriority inputs have the highest priority. An important input to the selection algorithm for the T0 DPLL is the REVERT bit in the MCR3 register. In revertive mode (REVERT = 1), if an input clock with a higher priority than the selected reference becomes valid, the higher priority reference immediately becomes the selected reference. In nonrevertive mode (REVERT = 0), the higher priority reference does not immediately become the selected reference but does become the highest priority reference in the priority table (REF1 field in the PTAB1 register). (The selection algorithm always switches to the highest priority valid input when the selected reference goes invalid, regardless of the state of the REVERT bit.) For many applications, nonrevertive mode is preferred for the T0 DPLL because it minimizes disturbances on the output clocks due to reference switching. The T4 DPLL always operates in revertive mode. 19-4617; Rev 5; 8/10 23 of 142 ____________________________________________________________________________________________ DS3102 In nonrevertive mode, planned switchover to a newly valid higher priority input clock can be done manually under software control. The validation of the new higher priority clock sets the corresponding status bit in the MSR1 or MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. System software can then respond to this change of state by briefly enabling revertive mode (toggling REVERT high then back low) to drive the switchover to the higher priority clock. In most systems redundant timing cards are required, with one functioning as the master and the other as the slave. In such systems the priority tables of the master and slave must match. The register set makes it easy for the slave’s priority table to track the master’s table. At system start-up, the same priorities must be assigned to the input clocks, for both DPLLs, in the master and slave devices. During operation, if an input clock becomes valid or invalid in one device (master or slave), the change is flagged in that device’s MSR1 or MSR2 register, which can drive an interrupt request on the INTREQ pin if needed. The real-time valid/invalid state of the input clocks can then be read from that device’s VALSR1 and VALSR2 registers. Once the nature of the state change is understood, the control bits of the other device’s VALCR1 and VALCR2 registers can be manipulated to mark clocks invalid in the other device as well. 7.6.3 Forced Selection The T0FORCE field in the MCR2 register and the T4FORCE field in the MCR4 register provide a way to force a specified input clock to be the selected reference for the T0 and T4 DPLLs, respectively. In both T0FORCE and T4FORCE, values of 0 and 15 specify normal operation with automatic reference selection. Values from 1 to 6 and 8 and 9 specify the input clock to be the forced selection; other values will cause no input to be selected. Internally, forcing is accomplished by giving the specified clock the highest priority (as specified in PTAB1:REF1). In revertive mode (MCR3:REVERT = 1) the forced clock automatically becomes the selected reference (as specified in PTAB1:SELREF) as well. In nonrevertive mode (T0 DPLL only) the forced clock only becomes the selected reference when the existing selected reference is invalidated or made unavailable for selection. In both revertive and nonrevertive modes when an input is forced to be the highest priority, the normal highest priority input (when no input is forced) is listed as the second-highest priority (PTAB2:REF2) and the normal second-highest priority input is listed as the third-highest priority (PTAB2:REF3). When the T4 DPLL is used to measure the phase difference between the T0 DPLL selected reference and another reference input by setting the T0CR1:T4MT0 bit, the T4FORCE field in the MCR4 register can be used to select the other reference input. 7.6.4 Ultra-Fast Reference Switching By default, disqualification of the selected reference and switchover to another reference occurs when the activity monitor’s inactivity alarm threshold has been crossed, a process that takes on the order of hundreds of milliseconds or seconds. For the T0 DPLL, an option for extremely fast disqualification and switchover is also available. When ultra-fast switching is enabled (MCR10:UFSW = 1), if the fast activity monitor detects approximately two missing clock cycles, it declares the reference failed by forcing the leaky bucket accumulator to its upper threshold (see Section 7.5.2) and initiates reference switching. This is in addition to setting the SRFAIL latched status bit in MSR2 and optionally generating an interrupt request, as described in Section 7.5.3. When ultra-fast switching occurs, the T0 DPLL transitions to the prelocked 2 state, which allows switching to occur faster by bypassing the loss-of-lock state. The device should be in nonrevertive mode when ultra-fast switching is enabled. If the device is in revertive mode, ultra-fast switching could cause excessive reference switching when the highest priority input is intermittent. 7.6.5 External Reference Switching Mode In this mode the SRCSW input pin controls reference switching between two clock inputs. This mode is enabled by setting the EXTSW bit to 1 in the MCR10 register. In this mode, if the SRCSW pin is high, the T0 DPLL is forced to lock to input IC3 (if the priority of IC3 is nonzero in IPR2) or IC5 (if the priority of IC3 is zero) whether or not the selected input has a valid reference signal. If the SRCSW pin is low, the T0 DPLL is forced to lock to input IC4 (if the priority of IC4 is nonzero in IPR2) or IC6 (if the priority of IC4 is zero) whether or not the selected input has a valid reference signal. During reset the default value of the EXTSW bit is latched from the SRCSW pin. If external reference switching mode is enabled during reset, the default frequency tolerance (DLIMIT registers) is configured to 80ppm rather than the normal default of 9.2ppm. 19-4617; Rev 5; 8/10 24 of 142 ____________________________________________________________________________________________ DS3102 In external reference switching mode the device is simply a clock switch, and the T0 DPLL is forced to lock onto the selected reference whether it is valid. Unlike forced reference selection (Section 7.6.3) this mode controls the PTAB1:SELREF field directly and is, therefore, not affected by the state of the MCR3:REVERT bit. During external reference switching mode, only PTAB1:SELREF is affected; the REF1, REF2, and REF3 fields in the PTAB registers continue to indicate the highest, second-highest, and third-highest priority valid inputs chosen by the automatic selection logic. External reference switching mode only affects the T0 DPLL. 7.6.6 Output Clock Phase Continuity During Reference Switching If phase build-out is enabled (PBOEN = 1 in MCR10) or the DPLL frequency limit (DLIMIT) is set to less than 30ppm, the device always complies with the GR-1244-CORE requirement that the rate of phase change must be less than 81ns per 1.326ms during reference switching. 7.6.7 Frequency Monitoring Hysteresis Required by Telcordia GR-1244-CORE For stratum 3 and stratum 3E applications, taking all Telcordia GR-1244-CORE requirements together, the DS3102 must accept input clocks with frequency offsets of less than ±9.2ppm and must reject input clocks with frequency offsets of more than ±12.0ppm. In between 9.2ppm and 12.0ppm the actual accept and reject thresholds must be separated by at least 0.46ppm. To realize GR-1244-CORE compliant thresholds for stratum 3 and stratum 3E, the appropriate settings are ILIMIT.HARD=2, DLIMIT1,2.HARDLIM=0x99, SRLIMIT.HARD=3. An accept threshold greater than 9.2ppm is provided by the ILIMIT.HARD value. Setting ILIMIT.HARD=2 gives a value of 11.43ppm according to the register description, but the actual threshold is halfway between the values given in the register description. Therefore ILIMIT.HARD=2 is halfway between 7.62ppm and 11.43ppm. This gives an accept threshold of 9.53ppm. A reject threshold less than 12.0ppm is provided by the DLIMIT1,2.HARDLIM value. If the frequency of the selected reference exceeds this limit the DPLL does not track it and goes out of lock. After a loss-of-lock timeout (specified by PHLKTO) the DPLL rejects the input. Finally, the SRLIMIT.HARD=3 value provides a backup reject threshold in case the selected reference frequency goes off frequency too rapidly. As with ILIMIT.HARD, the actual threshold is halfway between the values given in the register description. Therefore SRLIMIT.HARD=3 is halfway between 11.43ppm and 15.24ppm. This gives a backup reject threshold of 13.34ppm. 19-4617; Rev 5; 8/10 25 of 142 ____________________________________________________________________________________________ DS3102 7.7 DPLL Architecture and Configuration Both T0 and T4 are digital PLLs with separate analog PLLs (APLLs) as the output stage. This architecture combines the benefits of both PLL types. See Figure 7-1. Figure 7-1. DPLL Block Diagram PLL Bypass T4 selected reference T4 PFD and Loop Filter 0 Locking Frequency 1 T0CR1:T4MT0 T4 Foward DFS T4 Feedback DFS 2K8K DFS DIG12 DFS MCR7:DIG1SRC T0CR1:LKT4T0 MCR7:DIG2SRC T0CR1:LKT4T0 T0 PFD and Loop Filter T0 Foward DFS T0 Feedback DFS Locking Frequency ICRn:FREQ[3:0] DIG1 MCR6:DIG1SS MCR6:DIG1F[1:0] DIG12 DFS T0 selected reference 2K8K FSCR1:2K8KSRC T0CR1:LKT4T0 ICRn:FREQ[3:0] T4 DPLL 2 DIG2 MCR6:DIG2SS MCR6:DIG2F[1:0] MCR6:DIG2AF T4 APLL DFS T4 Output APLL APLL Output Dividers OCRm:OFREQn[3:0] OCR5:AOFn T0CR1:T4APT0 T0CR1:LKT4T0 T4CR1:T4FREQ[3:0] T0CR1:T0FT4[2:0] T0 Output APLL APLL Output Dividers T0 APLL2 DFS T0 Output APLL2 APLL Output Dividers FSYNC DFS 2 T0 APLL DFS OC1, OC2, OC3, OC4, OC5, OC6, OC7 T0CR1:T0FREQ[2:0] SYNC2K SYNC2K T0 DPLL OUTPUT DFS 19-4617; Rev 5; 8/10 FSCR2:INDEP FSYNC, MFSYNC OCR4:FSEN, MFSEN FSCR1:8KINV, 2KINV FSCR1:8KPOL, 2KPOL 26 of 142 ____________________________________________________________________________________________ DS3102 Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations, temperature, and voltage; and (2) flexible behavior that is easily programmed through the configuration registers. DPLLs use digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8MHz) is multiplied up from the 12.800MHz local oscillator clock applied to the REFCLK pin. This master clock is then digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1ns pkpk. The analog PLLs filter the jitter from the DPLLs, reducing the 1ns pk-pk jitter to less than 0.5ns pk-pk and 60ps RMS, typical, measured broadband (10Hz to 1GHz). The DPLLs in the device are configurable for many PLL parameters including bandwidth, damping factor, input frequency, pull-in/hold-in range, input-to-output phase offset, phase build-out, and more. No knowledge of loop equations or gain parameters is required to configure and operate the device. No external components are required for the DPLLs or the APLLs except the high-quality local oscillator connected to the REFCLK pin. The T0 DPLL to T0 APLL path is the main path through the device. The T0 DPLL has a full freerun/locked/holdover state machine and full programmability. The T4 DPLL to T4 APLL path is a simpler frequency converter/synthesis path, lacking the low bandwidth settings, phase build-out, and phase adjustment controls found in the T0 DPLL. 7.7.1 T0 DPLL State Machine The T0 DPLL has three main timing modes: locked, holdover, and free-run. The control state machine for the T0 DPLL has states for each timing mode as well as three temporary states: prelocked, prelocked 2, and loss-of-lock. The state transition diagram is shown in Figure 7-2. Descriptions of each state are given in the paragraphs below. During normal operation the state machine controls state transitions. When necessary, however, the state can be forced using the T0STATE field of the MCR1 register. Whenever the T0 DPLL changes state, the STATE bit in MSR2 is set, which can cause an interrupt request if enabled. The current T0 DPLL state can be read from the T0STATE field of the OPSTATE register. 7.7.1.1 Free-Run State Free-run mode is the reset default state. In free-run all output clocks are derived from the 12.800MHz local oscillator attached to the REFCLK pin. The frequency of each output clock is a specific multiple of the local oscillator. The frequency accuracy of each output clock is equal to the frequency accuracy of the master clock, which can be calibrated using the MCLKFREQ field in registers MCLK1 and MCLK2 (see Section 7.3). The state machine transitions from free-run to the prelocked state when at least one input clock is valid. 7.7.1.2 Prelocked State The prelocked state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the selected reference. If phase lock (see Section 7.7.6) is achieved for 2 seconds during this period, the state machine transitions to locked mode. If the DPLL fails to lock to the selected reference within the phase-lock timeout period specified by PHLKTO, a phase-lock alarm is raised (corresponding LOCK bit set in the ISR register), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid, the state machine re-enters the prelocked state and tries to lock to the alternate input clock. If no other input clocks are valid for two seconds, the state machine transitions back to the free-run state. In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock timeout period, the state machine re-enters the prelocked state and tries to lock the higher priority input. If a phase-lock timeout period longer than 100 seconds is required for locking (such as 700 seconds for Stratum 3E or 1000 seconds for Stratum 2 applications), the PHLKTO register must be configured accordingly. 19-4617; Rev 5; 8/10 27 of 142 ____________________________________________________________________________________________ DS3102 Figure 7-2. T0 DPLL State Transition Diagram Free-Run select ref (001) Reset (selected reference invalid > 2s OR out of lock >100s) AND no valid input clock [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher priority input)] AND valid input clock available all input clocks evaluated at least one input valid Prelocked wait for  100s (110) phase-locked to selected reference > 2s [selected reference invalid OR (revertive mode AND valid higher-priority input)] AND valid input clock available phase-locked to selected reference > 2s Locked (100) phase-lock regained on selected reference within 100s loss-of-lock on selected reference [selected reference invalid OR (revertive mode AND valid higher-priority input) OR out of lock >100s] AND Prelocked 2 Loss-of-Lock valid input clock available wait for  100s wait for  100s (101) (111) [selected reference invalid OR out of lock >100s OR (revertive mode AND valid higher priority input)] AND valid input clock available selected reference invalid > 2s AND no valid input clock available (selected reference invalid > 2s OR out of lock >100s) AND no valid input clock available Holdover select ref (010) (selected reference invalid > 2s OR out of lock >100s) AND no valid input clock available all input clocks evaluated at least one input valid Note 1: An input clock is valid when it has no activity alarm, no hard frequency limit alarm, and no phase-lock alarm (see the VALSR registers and the ISR registers). Note 2: All input clocks are continuously monitored for activity and frequency. Note 3: Only the selected reference is monitored for loss-of-lock. Note 4: Phase lock is declared internally when the DPLL has maintained phase lock continuously for approximately 1 to 2 seconds. Note 5: To simply the diagram, the phase-lock timeout period is always shown as 100s, which is the default value of the PHLKTO register. Longer or shorter timeout periods can be specified as needed by writing the appropriate value to the PHLKTO register. Note 6: When selected reference is invalid and the DPLL is not in free-run or holdover, the DPLL is in a temporary holdover state. 19-4617; Rev 5; 8/10 28 of 142 ____________________________________________________________________________________________ DS3102 7.7.1.3 Locked State The T0 DPLL state machine can reach the locked state from the prelocked, prelocked 2, or loss-of-lock states when the DPLL has locked to the selected reference for at least 2 seconds (see Section 7.7.6). In the locked state the output clocks track the phase and frequency of the selected reference. If the MCR1.LOCKPIN bit is set, the LOCK pin is driven high when the T0 DPLL is in the locked state. While in the locked state, if the selected reference is so impaired that an activity alarm or a hard frequency limit alarm is raised (corresponding ACT bit set in the ISR register), the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine immediately transitions to either the prelocked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). If loss-of-lock (see Section 7.7.6) is declared while in the locked state, the state machine transitions to the loss-oflock state. 7.7.1.4 Loss-of-Lock State When the loss-of-lock detectors (see Section 7.7.6) indicate loss-of-lock, the state machine immediately transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds (default value of PHLKTO register) to regain phase lock. If phase lock is regained during that period for more than 2 seconds, the state machine transitions back to the locked state. If during the phase-lock timeout period specified by PHLKTO the selected reference is so impaired that an activity alarm or a hard frequency limit alarm is raised (corresponding ACT bit or HARD bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR registers), and after being invalid for 2 seconds the state machine transitions to either the prelocked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid). If phase lock cannot be regained by the end of the phase-lock timeout period, a phase-lock alarm is raised (corresponding LOCK bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR registers), and the state machine transitions to either the prelocked 2 state (if another valid input clock is available) or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid). 7.7.1.5 Prelocked 2 State The prelocked and prelocked 2 states are similar. The prelocked 2 state provides a 100-second period (default value of PHLKTO register) for the DPLL to lock to the new selected reference. If phase lock (see Section 7.7.6) is achieved for more than 2 seconds during this period, the state machine transitions to locked mode. If the DPLL fails to lock to the new selected reference within the phase-lock timeout period specified by PHLKTO, a phase-lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit goes low in VALSR registers). If another input clock is valid, the state machine re-enters the prelocked 2 state and tries to lock to the alternate input clock. If no other input clocks are valid for 2 seconds, the state machine transitions to the holdover state. In revertive mode (REVERT = 1 in MCR3), if a higher priority input clock becomes valid during the phase-lock timeout period, the state machine re-enters the prelocked 2 state and tries to lock to the higher priority input. If a phase-lock timeout period longer than 100 seconds is required for locking (such as 700 seconds for Stratum 3E or 1000 seconds for Stratum 2 applications), the PHLKTO register must be configured accordingly. 7.7.1.6 Holdover State The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no other valid input clocks available. During holdover the T0 DPLL is not phase-locked to any input clock but instead generates its output frequency from stored frequency information, which is typically the averaged frequency of the 19-4617; Rev 5; 8/10 29 of 142 ____________________________________________________________________________________________ DS3102 DPLL when it was in the locked state. The device can be configured for manual or automatic holdover as described in the following subsections. When at least one input clock has been declared valid, the state machine immediately transitions from holdover to the prelocked 2 state and tries to lock to the highest priority valid clock. 7.7.1.6.1 Automatic Holdover For automatic holdover (FRUNHO = 0 in MCR3), the device can be further configured for instantaneous mode or averaged mode. In instantaneous mode (AVG = 0 in HOCR3), the holdover frequency is set to the DPLL’s current frequency 50ms to 100ms before entry into holdover (i.e., the value of the FREQ field in the FREQ1, FREQ2, and FREQ3 registers when MCR11:T4T0 = 0). The FREQ field is the DPLL’s integral path and, therefore, is an average frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not used in order to minimize the effect of recent phase disturbances on the holdover frequency. In averaged mode (AVG = 1 in HOCR3 and MANHO = 0 in MCR3), the holdover frequency is set to an internally averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged. The FAST bit in HOCR3 determines the period of this averaging. When FAST = 1, the frequency is averaged for a period of approximately 8 minutes. When FAST = 0 (slow), the frequency is averaged for a period of approximately 110 minutes. The T0 DPLL indicates that it has acquired valid holdover values by setting the FHORDY and SHORDY status bits in VALSR2 (real-time status) and MSR4 (latched status). If FAST = 0 and the T0 DPLL must enter holdover before the 110-minute average is available, the 8-minute average is used, if available. Otherwise, the instantaneous value from the integral path is used. If FAST = 1 and the T0 DPLL must enter holdover before the 8-minute average is available, an instantaneous value of 50ms to 100ms old from the integral path is used instead. 7.7.1.6.2 Manual Holdover For manual holdover (MANHO = 1 in MCR3), the holdover frequency is set by the HOFREQ field in the HOCR1, HOCR2, and HOCR3 registers. The HOFREQ field has the same size and format as the current frequency field (FREQ[18:0] in the FREQ1, FREQ2, and FREQ3 registers). If desired, software can, during locked operation, read the current frequency from FREQ, filter or average it over time, and write the resulting holdover frequency to HOFREQ. The FREQ field is derived from the DPLL’s integral path, and thus can be considered an average frequency with a rate of change inversely proportional to the DPLL bandwidth. To combine internal averaging with additional software filtering, the HOFREQ field can be configured to read out the internally averaged frequency when RDAVG = 1 in the HOCR3 register. This averaged value can be read from HOFREQ regardless of the current holdover mode. The FAST bit in HOCR3 specifies whether the value read is from the fast averager or the slow averager. 7.7.1.7 Mini-Holdover When the selected reference fails, the fast activity monitor (Section 7.5.3) isolates the T0 DPLL from the reference within one or two clock cycles to avoid adverse effects on the DPLL frequency. When this fast isolation occurs, the DPLL enters a temporary mini-holdover mode, with a frequency as specified by the MINIHO field of HOCR3. Miniholdover lasts until the selected reference returns or a new input clock has been chosen as the selected reference or the state machine enters the holdover state. If the manual holdover mode is set (MANHO = 1 in MCR3), the MINIHO field of HOCR3 is ignored and the mini-holdover frequency is the same as the manual holdover frequency. 7.7.2 T4 DPLL State Machine The T4 DPLL state machine is similar to the T0 DPLL, as shown in Figure 7-3. The T4 DPLL states are similar to the equivalent states of the T0 DPLL, but the only state indicator is the T4LOCK bit in the OPSTATE register. Note that the T4 DPLL only operates in revertive switching mode. The full-holdover and mini-holdover modes are instantaneous (see the first paragraph of Section 7.7.1.6.1). 19-4617; Rev 5; 8/10 30 of 142 ____________________________________________________________________________________________ DS3102 Figure 7-3. T4 DPLL State Transition Diagram RESET FREE-RUN SELECTED REFERENCE INACTIVE > 2s SELECTED REFERENCE ACTIVE PRELOCKED PHASE-LOCKED TO SELECTED REFERENCE > 2s SELECTED REFERENCE SWITCH LOCKED SELECTED REFERENCE INACTIVE > 2s SELECTED REFERENCE PHASE-LOCKED > 2s PHASE-LOCK REGAINED ON SELECTED REFERENCE > 2s LOSS-OF-LOCK ON SELECTED REFERENCE SELECTED REFERENCE INACTIVE > 2s SELECTED REFERENCE SWITCH PRELOCKED 2 LOSS-OF-LOCK HOLDOVER SELECTED REFERENCE INACTIVE > 2s SELECTED REFERENCE ACTIVE 19-4617; Rev 5; 8/10 31 of 142 ____________________________________________________________________________________________ DS3102 7.7.3 Bandwidth The bandwidth of the T4 DPLL is configured in the T4BW register to be 18Hz to 70Hz. The bandwidth of the T0 DPLL is configured in the T0ABW and T0LBW registers for various values from 0.5mHz to 400Hz. The AUTOBW bit in the MCR9 register controls automatic bandwidth selection. When AUTOBW = 1, the T0 DPLL uses the T0ABW bandwidth during acquisition (not phase-locked) and the T0LBW bandwidth when phase-locked. When AUTOBW = 0 the T0 DPLL uses the T0LBW bandwidth all the time, both during acquisition and when phase-locked. When LIMINT = 1 in the MCR9 register, the DPLL’s integral path is limited (i.e., frozen) when the DPLL reaches minimum or maximum frequency. Setting LIMINT = 1 minimizes overshoot when the DPLL is pulling in. 7.7.4 Damping Factor The damping factor for the T0 DPLL is configured in the DAMP field of the T0CR2 register, while the damping factor of the T4 DPLL is configured in the DAMP field of the T4CR2 register. The reset default damping factors for both DPLLs are chosen to give a maximum jitter/wander gain peak of approximately 0.1dB. Available settings are a function of DPLL bandwidth (configured in the T4BW, T0ABW, and T0LBW registers). See Table 7-5. Table 7-5. Damping Factors and Peak Jitter/Wander Gain BANDWIDTH (Hz) DAMP[2:0] VALUE DAMPING FACTOR GAIN PEAK (dB) 0.5m to 4 1, 2, 3, 4, 5 5 0.1 8 1 2, 3, 4, 5 1 2 3, 4, 5 1 2 3 4, 5 1 2 3 4 5 2.5 5 1.2 2.5 5 1.2 2.5 5 10 1.2 2.5 5 10 20 0.2 0.1 0.4 0.2 0.1 0.4 0.2 0.1 0.06 0.4 0.2 0.1 0.06 0.03 18 35 70 to 400 7.7.5 Phase Detectors Phase detectors are used to compare a PLL’s feedback clock with its input clock. Several phase detectors are available in the T0 and T4 DPLLs:    Phase/frequency detector (PFD) Early/late phase detector (PD2) for fine resolution Multicycle phase detector (MCPD) for large input jitter tolerance and/or faster lock times These detectors can be used in combination to give fine phase resolution combined with large jitter tolerance. As with the rest of the DPLL logic, the phase detectors operate at input frequencies up to 77.76MHz. The multicycle phase detector detects and remembers phase differences of many cycles (up to 8191UI). When locking to 8kHz or lower, the normal phase/frequency detectors are always used. 19-4617; Rev 5; 8/10 32 of 142 ____________________________________________________________________________________________ DS3102 The T0 DPLL phase detectors can be configured for normal phase/frequency locking (360 capture) or nearest edge phase locking (180 capture). With nearest edge detection the phase detectors are immune to occasional missing clock cycles. The DPLL automatically switches to nearest edge locking when the multicycle phase detector is disabled and the other phase detectors determine that phase lock has been achieved. Setting D180 = 1 in the TEST1 register disables nearest edge locking and forces the T0 DPLL to use phase/frequency locking. The T4 DPLL always has nearest edge locking enabled. The early/late phase detector, also known as phase detector 2, is enabled and configured in the PD2 fields of registers T0CR2 and T0CR3 for the T0 DPLL and registers T4CR2 and T4CR3 for the T4 DPLL. The reset default settings of these registers are appropriate for all operating modes. Adjustments only affect small signal overshoot and bandwidth. The multicycle phase detector is enabled by setting MCPDEN = 1 in the PHLIM2 register. The range of the MCPD—from 1UI up to 8191UI—is configured in the COARSELIM field of PHLIM2. The MCPD tracks phase position over many clock cycles, giving high jitter tolerance. Thus, the use of the MCPD is an alternative to the use of LOCK8K mode for jitter tolerance. When a DPLL is direct locking to 8kHz, 4kHz, or 2kHz, or in LOCK8K mode, the multicycle phase detector is automatically disabled. When USEMCPD = 1 in PHLIM2, the MCPD is used in the DPLL loop, giving faster pull-in but more overshoot. In this mode the loop has similar behavior to LOCK8K mode. In both cases large phase differences contribute to the dynamics of the loop. When enabled by MCPDEN = 1, the MCPD tracks the phase position whether or not it is used in the DPLL loop. When the input clock is divided before being sent to the phase detector, the divider output clock edge gets aligned to the feedback clock edge before the DPLL starts to lock to a new input clock signal or after the input clock signal has a temporary signal loss. This helps ensure locking to the nearest input clock edge, which reduces output transients and decreases lock times. 7.7.6 Loss-of-Lock Detection Loss-of-lock can be triggered by any of the following in both the T0 and T4 DPLLs:     The fine phase-lock detector (measures phase between input and feedback clocks) The coarse phase-lock detector (measures whole cycle slips) Hard frequency limit detector Inactivity detector The fine phase-lock detector is enabled by setting FLEN = 1 in the PHLIM1 register. The fine phase limit is configured in the FINELIM field of PHLIM1. The coarse phase-lock detector is enabled by setting CLEN = 1 in the PHLIM2 register. The coarse phase limit is configured in the COARSELIM field of PHLIM2. This coarse phase-lock detector is part of the multicycle phase detector (MCPD) described in Section 7.7.5. The COARSELIM field sets both the MCPD range and the coarse phase limit, since the two are equivalent. If loss-of-lock should not be declared for multiple-UI input jitter, the fine phase-lock detector should be disabled and the coarse phase-lock detector should be used instead. The hard frequency limit detector is enabled by setting FLLOL = 1 in the DLIMIT3 register. The hard limit for the T0 DPLL is configured in registers DLIMIT1 and DLIMIT2. The T4 DPLL hard limit is fixed at 80ppm. When the DPLL frequency reaches the hard limit, loss-of-lock is declared. The DLIMIT3 register also has the SOFTLIM field to specify a soft frequency limit. Exceeding the soft frequency limit does not cause loss-of-lock to be declared. When the T0 DPLL frequency reaches the soft limit, the T0SOFT status bit is set in the OPSTATE register. When the T4 DPLL frequency reaches the soft limit, the T4SOFT status bit is set in OPSTATE. The inactivity detector is enabled by setting NALOL = 1 in the PHLIM1 register. When this detector is enabled the DPLL declares loss-of-lock after one or two missing clock cycles on the selected reference. See Section 7.5.3. When the T0 DPLL declares loss-of-lock, the state machine immediately transitions to the loss-of-lock state, which sets the STATE bit in the MSR2 register and requests an interrupt if enabled. 19-4617; Rev 5; 8/10 33 of 142 ____________________________________________________________________________________________ DS3102 When the T4 DPLL declares loss-of-lock, the T4LOCK bit is cleared in the OPSTATE register, which sets the T4LOCK bit in the MSR3 register and requests an interrupt if enabled. 7.7.7 Phase Build-Out 7.7.7.1 Phase Monitor The T0 DPLL has a phase monitor that measures the phase error between the input clock reference and the DPLL output. The phase monitor is enabled by setting PHMON:PMEN = 1. When the T0 DPLL is set for low bandwidth, a phase transient on the input causes an immediate phase error that is gradually reduced as the DPLL tracks the input. When the measured phase error exceeds the limit set in the PHMON:PMLIM field, the phase monitor declares a phase monitor alarm by setting the MSR3:PHMON bit. The PMLIM field can be configured for a limit ranging from about 1s to about 3.5s. 7.7.7.2 Phase Build-Out in Response to Input Phase Transients See Telcordia GR-1244-CORE Section 5.7 for an explanation of phase build-out (PBO) and the requirement for Stratum 2 and 3E clocks to perform PBO in response to input phase transients. When the phase monitor is enabled (as described in Section 7.7.7.1) and PHMON:PMPBEN = 1, the T0 DPLL automatically triggers PBO events in response to input transients greater than the limit set in PHMON:PMLIM. The range of limits available in the PMLIM field allows the T0 DPLL to be configured to build out input transients greater than 3.5s, greater than 1s, or any threshold in between. To determine when to perform PBO, the phase monitor watches for phase changes greater than 100ns in a 10ms interval on the selected reference. When such a phase change occurs, an internal 0.1 second timer is started. If during this interval the phase change is greater than the PMLIM threshold then a PBO event occurs. During a PBO event the device enters a temporary holdover state in which the phase difference between the selected reference and the output is measured and fed into the DPLL loop to absorb the input transient. After a PBO event, regardless of the input phase transient, the output phase transient is less than or equal to 5ns. Phase build-out can be frozen at the current phase offset by setting MCR10:PBOFRZ = 1. When PBO is frozen the T0 DPLL ignores subsequent phase build-out events and maintains the current phase offset between input and outputs. 7.7.7.3 Automatic Phase Build-Out in Response to Reference Switching When MCR10:PBOEN = 0, phase build-out is not performed during reference switching. The T0 DPLL always locks to the selected reference at zero degrees of phase. With PBO disabled, transitions from a failed reference to the next highest priority reference and transitions from holdover or free-run to locked mode cause phase transients on output clocks as the T0 DPLL jumps from its previous phase to the phase of the new selected reference. When MCR10:PBOEN = 1, phase build-out is performed during reference switching (or exiting from holdover). With PBO enabled, if the selected reference fails and another valid reference is available, the device enters a temporary holdover state in which the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. Similarly, during transitions from full holdover, mini-holdover, or free-run to locked mode, the phase difference between the new reference and the output is measured and fed into the DPLL loop to absorb the input phase difference. After a PBO event, regardless of the input phase difference, the output phase transient is less than or equal to 5ns. Any time that PBO is enabled it can also be frozen at the current phase offset by setting MCR10:PBOFRZ = 1. When PBO is frozen, the T0 DPLL ignores subsequent phase build-out events and maintains the current phase offset between inputs and outputs. Disabling PBO while the T0 DPLL is not in the free-run or holdover states (locking or locked) causes a phase change on the output clocks while the DPLL switches to tracking the selected reference with zero degrees of phase error. The rate of phase change on the output clocks depends on the DPLL bandwidth. Enabling PBO (which includes unfreezing) while locking or locked also causes a PBO event. 19-4617; Rev 5; 8/10 34 of 142 ____________________________________________________________________________________________ DS3102 7.7.7.4 PBO Phase Offset Adjustment An uncertainty of up to 5ns is introduced each time a phase build-out event occurs. This uncertainty results in a phase hit on the output. Over a large number of phase build-out events the mean error should be zero. The PBOFF register specifies a small fixed offset for each phase build-out event to skew the average error toward zero and eliminate accumulation of phase shifts in one direction. 7.7.8 Input to Output (Manual) Phase Adjustment When phase build-out is disabled (PBOEN = 0 in MCR10), the OFFSET registers can be used to adjust the phase of the T0 DPLL output clocks with respect to the selected reference when locked. Output phase offset can be adjusted over a 200ns range in 6ps increments. This phase adjustment occurs in the feedback clock so that the output clocks are adjusted to compensate. The rate of change is therefore a function of DPLL bandwidth. Simply writing to the OFFSET registers with phase build-out disabled causes a change in the input to output phase, which can be considered to be a delay adjustment. Changing the OFFSET adjustment while in free-run or holdover state does not cause an output phase offset until it exits the state and enters one of the locking states. 7.7.9 Phase Recalibration When a phase buildout occurs, either automatic or manual, the feedback frequency synthesizer does not get an internal alignment signal to keep it aligned with the output dividers, and, therefore, the phase difference between input and output can become incorrect. Setting the FSCR3:RECAL bit periodically causes a recalibration process to be executed, which corrects any phase error that may have occurred. During the recalibration process the device puts the DPLL into mini-holdover, internally ramps the phase offset to zero, resets all clock dividers, ramps the phase offset to the value stored in the OFFSET registers, and switches the DPLL out of mini-holdover. If the OFFSET registers are written during the recalibration process, the process ramps the phase offset to the new offset value. 7.7.10 Frequency and Phase Measurement When the T4 DPLL is not needed to generate an output frequency locked to an input clock, it can measure precise frequency by locking onto any input. It can also measure phase between the T0 selected reference and any input by setting the T0CR1.T4MT0 bit. The T4 APLL can still be used to clean up jitter on a synthesized clock from the T0 DPLL. When the T0CR1.T4MT0 bit is set the T4 DPLL goes to the free-run state. Standard input clock frequency monitoring is described in Section 7.5.1. The input clock monitors report measured frequency with 3.8ppm resolution. More accurate measurement of frequency and phase can be accomplished using the DPLLs. The T0 DPLL is always monitoring its selected reference, but if the T4 DPLL is not otherwise used to lock to an input, it can be configured as a high-resolution phase monitor. The REFCLK signal accuracy after being adjusted with MCLKFREQ is used for the frequency reference. Software can then connect the T4 DPLL to various input clocks on a rotating basis to measure phase between the T0 DPLL input and another input. See the T4FORCE field of MCR4. DPLL frequency measurements can be read from the FREQ field spanning registers FREQ1, FREQ2, and FREQ3. This field indicates the frequency of the selected reference for either the T0 DPLL or the T4 DPLL, depending on the setting of the T4T0 bit in MCR11. This frequency measurement has a resolution of 0.0003068ppm over a 80ppm range. The value read from the FREQ field is the DPLL’s integral path value, which is an averaged measurement with an averaging time inversely proportional to DPLL bandwidth. DPLL phase measurements can be read from the PHASE field spanning registers PHASE1 and PHASE2. This field indicates the phase difference seen by the phase detector for either the T0 DPLL or the T4 DPLL, depending on the setting of the T4T0 bit in MCR11. This phase measurement has a resolution of approximately 0.703 degrees and is internally averaged with a -3dB attenuation point of approximately 100Hz. Thus, for low DPLL bandwidths, the PHASE field gives input phase wander in the frequency band from the DPLL corner frequency up to 100Hz. This information could be used by software to compute a crude MTIE measurement. 19-4617; Rev 5; 8/10 35 of 142 ____________________________________________________________________________________________ DS3102 For the T0 DPLL the PHASE field always indicates the phase difference between the selected reference and the internal feedback clock. The T4 DPLL, however, can be configured to measure the phase difference between two input clocks. When T0CR1:T4MT0 = 1, the T4 DPLL locking capability is disabled, and the T4 phase detector is configured to compare the T0 DPLL selected reference with the T4 DPLL selected reference. Any input clock can then be forced to be the T4 DPLL selected reference using the T4FORCE field of MCR4. This feature can be used, for example, to measure the phase difference between the T0 DPLL’s selected reference and its next highest priority reference. Software could compute MTIE and TDEV with respect to the T0 DPLL selected reference for any or all the other input clocks. When comparing the phase of the T0 and T4 selected references by setting T0CR1:T4MT0 = 1, several details must be considered. In this mode, the T4 path receives a copy of the T0 selected reference, either directly or through a divider to 8kHz. If the T4 selected reference is divided down to 8kHz using LOCK8K or DIVN modes (see Section 7.4.2), the copy of the T0 selected reference is also divided down to 8kHz. If the T4 selected reference is configured for direct-lock mode, the copy of the T0 selected reference is not divided down and must be the same frequency as the T4 selected reference. See Table 7-6 for more details. (While T0CR1:T4MT0 = 1, the T0 path continues to lock to the T0 selected reference in the manner specified in the corresponding ICR register.) 19-4617; Rev 5; 8/10 36 of 142 ____________________________________________________________________________________________ DS3102 Table 7-6. T0 DPLL Adaptation for the T4 DPLL Phase Measurement Mode LOCKING MODE FOR T4 SELECTED REFERENCE LOCKING MODE FOR T0 SELECTED REFERENCE LOCKING MODE FOR COPY OF T0 SELECTED REFERENCE FREQUENCY OF THE T4 SELECTED REFERENCE FOR T4MT0 PHASE MEASUREMENT FREQUENCY OF THE T0 SELECTED REFERENCE FOR T4MT0 PHASE MEASUREMENT LOCK8K or DIVN(8K) DIRECT LOCK8K 8kHz 8kHz LOCK8K or DIVN(8K) LOCK8K LOCK8K 8kHz 8kHz LOCK8K or DIVN(8K) DIVN (8K) DIVN 8kHz 8kHz LOCK8K or DIVN(8K) DIVN (not 8K) DIRECT 8kHz 8kHz DIVN (not 8K) Any DIRECT Same as the T4 forced reference input frequency Same as the T0 selected reference input frequency(1) DIRECT Any DIRECT Same as the T4 forced reference input frequency Same as the T0 selected reference input frequency(1) Note 1: In this case the T0 select reference must be the same frequency as the T4 selected reference. Note 2: If the T4 selected reference frequency is 8kHz and the T0 selected reference is a different frequency, the two references can be compared by configuring the T4 selected reference for 8kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided down to 8kHz using either LOCK8K or DIVN mode. Note 3: DIVN(8K) means that the FREQ field is set to 8kHz, DIVN(not 8K) means the FREQ field is not set to 8kHz. 7.7.11 Input Jitter and Wander Tolerance The device is compliant with the jitter and wander tolerance requirements of the standards listed in Table 1-1. Wander can be tolerated up to the point where wander causes an apparent long-term frequency offset larger than the limits specified in the ILIMIT and/or SRLIMIT registers. In such a situation the input clock would be declared invalid. When using the 360/180 PFD, jitter can be tolerated up to the point of eye closure. Either LOCK8K mode (see Section 7.4.2.3) or the multicycle phase detector (see Section 7.7.5) should be used for high jitter tolerance. 7.7.12 Jitter and Wander Transfer The transfer of jitter and wander from the selected reference to the output clocks has a programmable transfer function that is determined by the DPLL bandwidth. (See Section 7.7.3.) In the T0 DPLL, the 3dB corner frequency of the jitter transfer function can be set to any of 21 positions from 0.5mHz to 400Hz. In the T4 DPLL the 3dB corner frequency of the jitter transfer function can be set to various values from 18Hz to 70Hz. During locked mode, the transfer of wander from the local oscillator clock (connected to the REFCLK pin) to the output clocks is not significant as long as the DPLL bandwidth is set high enough to allow the DPLL to quickly compensate for oscillator frequency changes. During free-run and holdover modes, local oscillator wander has a much more significant effect. See Section 7.3. 19-4617; Rev 5; 8/10 37 of 142 ____________________________________________________________________________________________ DS3102 7.7.13 Output Jitter and Wander Several factors contribute to jitter and wander on the output clocks, including:    Jitter and wander amplitude on the selected reference (while in the locked state) The jitter/wander transfer characteristic of the device (while in the locked state) The jitter and wander on the local oscillator clock signal (especially wander while in the holdover state) The DPLL in the device has programmable bandwidth (see Section 7.7.3). With respect to jitter and wander, the DPLL behaves as a lowpass filter with a programmable pole. The bandwidth of the DPLL is normally set low enough to strongly attenuate jitter. The wander and jitter attenuation depends on the DPLL bandwidth chosen. Over time, frequency changes in the local oscillator can cause a phase difference between the selected reference and the output clocks. This is especially true at lower frequency DPLL bandwidths because the DPLL’s rate of change may be slower than the oscillator’s rate of change. Oscillators with better stability will minimize this effect. In some applications, an OCXO may be required rather than a TCXO. In the most demanding applications, the OCXO may need to be shielded to further reduce the rate of temperature change and thus the rate of frequency change. 7.8 Output Clock Configuration A total of 16 output clock pins, OC1 to OC5, OC1B to OC5B, OC4POS/NEG to OC7POS/NEG, FSYNC, and MFSYNC are available on the device. Output clocks OC1 to OC7 are individually configurable for a variety of frequencies derived from either the T0 DPLL or the T4 DPLL. OC1B to OC5B are powered from a dedicated I/O power pin that can be set to any voltage from 2.2V to 3.3V. Output clocks FSYNC and MFSYNC serve as 8kHz frame-sync and 2kHz multiframe-sync outputs, respectively. Table 7-7 provides more detail on the capabilities of the output clock pins. Table 7-7. Output Clock Capabilities OUTPUT CLOCK OC1 OC2 OC3 OC4 OC5 OC1B OC2B OC3B OC4B OC5B OC4 OC5 OC6 OC7 FSYNC MFSYNC 19-4617; Rev 5; 8/10 SIGNAL FORMAT FREQUENCIES SUPPORTED CMOS/TTL 3.3V powered CMOS/TTL 2.5V or 3.3V powered Frequency selection per Section 7.8.2.3 and Table 7-8 to Table 7-14. LVDS/LVPECL CMOS/TTL 8kHz frame sync with programmable pulse width and polarity. 2kHz multiframe sync with programmable pulse width and polarity. 38 of 142 ____________________________________________________________________________________________ DS3102 7.8.1 Signal Format Configuration Output clocks OC4, OC5, OC6, and OC7 are LVDS-compatible, LVPECL level-compatible outputs. The type of output can be selected or the output can be disabled using the OCnSF configuration bits in the MCR8 register. The LVPECL level-compatible mode generates a differential signal that is large enough for most LVPECL receivers. Some LVPECL receivers have a limited common mode signal range which can be accommodated for by using an AC-coupled signal. The LVDS electrical specifications are listed in Table 10-5, and the recommended LVDS termination is shown in Figure 10-1. The LVPECL level-compatible electrical specifications are listed in Table 10-6, and the recommended LVPECL receiver termination is shown in Figure 10-3. These differential outputs can be easily interfaced to LVDS, LVPECL, and CML inputs on neighboring ICs using a few external passive components. See Maxim App Note HFAN-1.0 for details. The other output clocks are CMOS/TTL signal format. 7.8.2 Frequency Configuration The frequency of output clocks OC1 to OC7 is a function of the settings used to configure the components of the T0 and T4 PLL paths. These components are shown in the detailed block diagram of Figure 7-1. The DS3102 uses digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8MHz) is divided down to the desired output frequency by adding a number to an accumulator. The DFS output is a coding of the clock output phase that is used by a special circuit to determine where to put the edges of the output clock between the clock edges of the master clock. The edges of the output clock, however, are not ideally located in time resulting in jitter with an amplitude typically less than 1ns pk-pk. 7.8.2.1 T0 and T4 DPLL Details See Figure 7-1. The T0 and T4 forward-DFS blocks use the 204.8MHz master clock and DFS technology to synthesize internal clocks from which the output and feedback clocks are derived. The T4 DPLL only has a single DFS output clock signal for both the output clocks and the feedback clock, whereas there are two DFS output clock signals in the T0 DPLL—one for the output clocks and one for the feedback clock. In the T0 DPLL, the feedback clock-signal output handles phase build-out or any phase offset configured in the OFFSET registers. Thus, the T0 DPLL output clock signals and the feedback clock signal are frequency-locked but may have a phase offset. The T0 and T4 feedback-DFS blocks are always connected to the T0 forward DFS and the T4 forward DFS, respectively. The feedback-DFS blocks synthesize the appropriate locking frequencies for use by the phase-frequency detectors (PFDs). See Section 7.4.2. 7.8.2.2 Output DFS and APLL Details See Figure 7-1. The output clock frequencies are determined by two 2kHz/8kHz DFS blocks, two DIG12 DFS blocks, and three APLL DFS blocks. Four of the DFS blocks can be connected to either the T0 DPLL or the T4 DPLL, and three are always connected to the T0 DPLL. The T0 APLL, the T0 APLL2 and the T4 APLL (and their output dividers) get their frequency references from three associated APLL DFS blocks. All the output DFS blocks are connected to the T0 DPLL when MCR4:LKT4T0 = 1. The 2K8K DFS and FSYNC DFS blocks generate both 2kHz and 8kHz signals which have about 1ns pk-pk jitter. The FSYNC (8kHz) and MFSYNC(2 kHz) signals come from the FSYNC DFS block, which is always connected to the T0 DPLL when not in independent mode (FSCR2:INDEP = 1). The 2kHz and 8kHz signals available on output clocks OC1 to OC7 come from the 2K8K DFS, which can be connected to either the T0 DPLL or the T4 DPLL depending on FSCR1:2K8KSRC and MCR4:LKT4T0. The DIG1 DFS can generate an N x DS1 or NxE1 signal with about 1ns pk-pk jitter. The DIG2 DFS can generate an N x DS1, N x E1, 6.312MHz, 10MHz, or N x 19.44MHz clock with approximately 1ns pk-pk jitter. Each DIG12 DFS can be connected to either the T0 DPLL or the T4 DPLL using MCR7:DIG1SRC or MCR7:DIG2SRC and MCR4:LKT4T0. The frequency of the DIG1 clock is configured by the DIG1SS bit in MCR6 and the DIG1F[1:0] field in MCR7. The frequency of the DIG2 clock is configured by the DIG2AF and DIG2SS bits in MCR6 and the 19-4617; Rev 5; 8/10 39 of 142 ____________________________________________________________________________________________ DS3102 DIG2F[1:0] field in MCR7. DIG1 and DIG2 can be independently configured for any of the frequencies shown in Table 7-8 and Table 7-9, respectively. The APLL DFS blocks and their associated output APLLs and output dividers can generate many different frequencies. The T0 APLL DFS and the T0 APLL2 DFS are always connected to the T0 DPLL. The T4 APLL DFS can be connected to either the T0 DPLL or the T4 DPLL depending on T0CR1:T4APT0 and MCR4:LKT4T0. The T0 APLL frequencies that can be generated are listed in Table 7-11. The T0 APLL2 frequency is always 312.500MHz. The T4 APLL frequencies that can be generated are listed in Table 7-13. The output frequencies that can be generated from the APLL circuits are listed in Table 7-10. The T4 APLL is disabled and powered down when T4CR1:T4FREQ = 0000 and T0CR1:T4APT0 = 0. In this mode all outputs connected to the T4 APLL are driven low. Together the T0 APLL, T0 APLL2, and T4 APLL can simultaneously generate SONET/SDH clock rates, Gigabit Ethernet clock rates (e.g., 125MHz), and 10G Ethernet clock rates (e.g., 156.25MHz), all locked to the same selected reference. This capability supports mixed SONET/SDH and Synchronous Ethernet line cards. 7.8.2.3 OC1 to OC7 Configuration The following is a step-by-step procedure for configuring the frequencies of output clocks OC1 to OC7: 1) Determine whether the T4 APLL must be independent of the T0 DPLL. If the T4 APLL must be independent, set T4APT0 = 0 in register T0CR1. If the T4 APLL must be locked to the T0 DPLL, set T4APT0 = 1. 2) Use Table 7-10 to select a set of output frequencies for each APLL, T0 and T4. Each APLL can only generate one set of output frequencies. (In SONET/SDH equipment, the T0 APLL is typically configured for a frequency of 311.04MHz to get 19.44MHz and/or 38.88MHz output clocks to distribute to system line cards.) 3) Determine from Table 7-10 the T0 and T4 APLL frequencies required for the frequency sets chosen in step 2. 4) Configure the T0FREQ field in register T0CR1 as shown in Table 7-11 for the T0 APLL frequency determined in step 3. Configure the T4FREQ field in register T4CR1 as shown in Table 7-13 for the T4 APLL frequency determined in step 3. If the T4 APLL is locked to the T0 DPLL, the T4APT0 and T0FT4 fields in T0CR1 must also be configured as shown in Table 7-13. 5) Using Table 7-10 and Table 7-14, configure the frequencies of output clocks OC1 to OC7 in the OFREQn fields of registers OCR1 to OCR4 and the AOFn bit in the OCR5 register. Table 7-15 lists all standard frequencies for the output clocks and specifies how to configure the T0 APLL and/or the T4 APLL to obtain each frequency. Table 7-15 also indicates the expected jitter amplitude for each frequency. Table 7-8. Digital1 Frequencies DIG1F[1:0] SETTING IN MCR7 00 01 10 11 00 01 10 11 19-4617; Rev 5; 8/10 DIG1SS SETTING IN MCR6 0 0 0 0 1 1 1 1 FREQUENCY (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 JITTER (pk-pk ns, typ)