DS31406GN+

ABRIDGED DATA SHEET 19-5711; Rev 0; 12/10 DS31406 2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem which has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS. Features          PART DS31406GN+ TEMP RANGE PIN-PACKAGE -40C to +85C 256 CSBGA +Denotes a lead(Pb)-free/RoHS-compliant package. SPI is a trademark of Motorola, Inc. Hitless Reference Switching on Loss of Input Automatic or Manual Phase Build-Out Holdover on Loss of All Inputs Programmable Bandwidth, 0.5mHz to 400Hz Seven Digital Frequency Synthesizers  Produce Any 2kHz Multiple Up to 77.76MHz  Per-DFS Clock Phase Adjust  Three Output APLLs  Output Frequencies to 750MHz  High Resolution Fractional Scaling for FEC and 64B/66B (e.g., 255/237, 255/238, 66/64) or Any Other Scaling Requirement  Less than 1ps RMS Output Jitter  Simultaneously Produce Three Low-Jitter Rates from the Same Reference (e.g., 622.08MHz for SONET, 255/237*622.08MHz for OTU2, and 156.25MHz for 10GE)  14 Output Clocks in Seven Groups  Nearly Any Frequency from